From: Claudiu Zissulescu <claziss@synopsys.com>
Date: Wed, 9 Nov 2016 14:30:35 +0000 (+0100)
Subject: [ARC] Fix printing 'b' mnemonics.
X-Git-Url: http://git.efficios.com/?a=commitdiff_plain;h=c4b943d7aed5edbfc31aa1e9dc9e7bcf108d76a0;p=deliverable%2Fbinutils-gdb.git

[ARC] Fix printing 'b' mnemonics.

gas/
2016-11-22  Claudiu Zissulescu  <claziss@synopsys.com>

	* testsuite/gas/arc/b.d: Update test result.

opcode/
2016-11-22  Claudiu Zissulescu  <claziss@synopsys.com>

	* arc-tbl.h: Reorder conditional flags with delay flags for 'b'
	instructions.
---

diff --git a/gas/ChangeLog b/gas/ChangeLog
index 71cc677dd7..58142eaced 100644
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,3 +1,7 @@
+2016-11-22  Claudiu Zissulescu  <claziss@synopsys.com>
+
+	* testsuite/gas/arc/b.d: Update test result.
+
 2016-11-22  Alan Modra  <amodra@gmail.com>
 
 	PR 20744
diff --git a/gas/testsuite/gas/arc/b.d b/gas/testsuite/gas/arc/b.d
index 87afdc043e..50bc30581c 100644
--- a/gas/testsuite/gas/arc/b.d
+++ b/gas/testsuite/gas/arc/b.d
@@ -39,8 +39,8 @@ Disassembly of section .text:
   78:	0789 ffcf           	b	0 <text_label>
   7c:	0785 ffef           	b.d	0 <text_label>
   80:	264a 7000           	mov	0,0
-  84:	077c ffe1           	b.deq	-132
+  84:	077c ffe1           	beq.d	-132
   88:	264a 7000           	mov	0,0
   8c:	0774 ffc2           	bne	-140
-  90:	0770 ffe6           	b.dnc	-144
+  90:	0770 ffe6           	bnc.d	-144
   94:	264a 7000           	mov	0,0
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index b78e70dfd0..9cd641a963 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,8 @@
+2016-11-22  Claudiu Zissulescu  <claziss@synopsys.com>
+
+	* arc-tbl.h: Reorder conditional flags with delay flags for 'b'
+	instructions.
+
 2016-11-18  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 
 	* aarch64-tbl.h (QL_V3SAMEHSD_ROT, QL_ELEMENT_ROT): Define.
diff --git a/opcodes/arc-tbl.h b/opcodes/arc-tbl.h
index 3246d8d0e0..c6e246eda7 100644
--- a/opcodes/arc-tbl.h
+++ b/opcodes/arc-tbl.h
@@ -1394,7 +1394,7 @@
 { "b", 0x00010000, 0xF8010000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE, { SIMM25_A16_5 }, { C_D }},
 
 /* b<.d><cc> s21 00000ssssssssss0SSSSSSSSSSNQQQQQ.  */
-{ "b", 0x00000000, 0xF8010000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE, { SIMM21_A16_5 }, { C_D, C_CC }},
+{ "b", 0x00000000, 0xF8010000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE, { SIMM21_A16_5 }, { C_CC, C_D }},
 
 /* bbit0<.d> b,c,s9 00001bbbsssssss1SBBBCCCCCCN01110.  */
 { "bbit0", 0x0801000E, 0xF801001F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, BRANCH, COND, { RB, RC, SIMM9_A16_8 }, { C_D }},