From: Tamar Christina Date: Fri, 6 Jul 2018 15:15:41 +0000 (+0100) Subject: Fix the read/write flag for these registers on AArch64 X-Git-Url: http://git.efficios.com/?a=commitdiff_plain;h=cba05feb51cb97f75f9a7814b081ce45245ac7b2;p=deliverable%2Fbinutils-gdb.git Fix the read/write flag for these registers on AArch64 The previous constraints were based on information already in opcodes and it seems that a few of them were wrong. I have now hand verified the ones changed by the previous patch and corrected where needed. This prevents a warning to be issued when one shouldn't be. opcodes/ PR binutils/23369 * aarch64-opc.c (aarch64_sys_regs): Make read/write csselr_el1, vsesr_el2, osdtrrx_el1, osdtrtx_el1, pmsidr_el1. gas/testsuite/ PR binutils/23369 * gas/aarch64/msr.d (csselr_el1, vsesr_el2, osdtrrx_el1, osdtrtx_el1, pmsidr_el1): New. * gas/aarch64/msr.s: Likewise. --- diff --git a/gas/ChangeLog b/gas/ChangeLog index aa4e948eb3..70357b9d75 100644 --- a/gas/ChangeLog +++ b/gas/ChangeLog @@ -1,3 +1,10 @@ +2018-07-06 Tamar Christina + + PR binutils/23369 + * testsuite/gas/aarch64/msr.d (csselr_el1, + vsesr_el2, osdtrrx_el1, osdtrtx_el1, pmsidr_el1): New. + * testsuite/gas/aarch64/msr.s: Likewise. + 2018-07-06 Nick Clifton * write.c (maybe_generate_build_notes): Bias reloc offsets by the diff --git a/gas/testsuite/gas/aarch64/msr.d b/gas/testsuite/gas/aarch64/msr.d index 92d33ddf75..4d5e630921 100644 --- a/gas/testsuite/gas/aarch64/msr.d +++ b/gas/testsuite/gas/aarch64/msr.d @@ -1,3 +1,4 @@ +#as: -march=armv8.2-a+profile #objdump: -dr .*: file format .* @@ -15,3 +16,13 @@ Disassembly of section \.text: 1c: d53b4220 mrs x0, daif 20: d50040bf msr spsel, #0x0 24: d50041bf msr spsel, #0x1 + 28: d51a0000 msr csselr_el1, x0 + 2c: d53a0000 mrs x0, csselr_el1 + 30: d51c5260 msr vsesr_el2, x0 + 34: d53c5260 mrs x0, vsesr_el2 + 38: d5100040 msr osdtrrx_el1, x0 + 3c: d5300040 mrs x0, osdtrrx_el1 + 40: d5100340 msr osdtrtx_el1, x0 + 44: d5300340 mrs x0, osdtrtx_el1 + 48: d51899e0 msr pmsidr_el1, x0 + 4c: d53899e0 mrs x0, pmsidr_el1 diff --git a/gas/testsuite/gas/aarch64/msr.s b/gas/testsuite/gas/aarch64/msr.s index 5511286a61..e33843cfb1 100644 --- a/gas/testsuite/gas/aarch64/msr.s +++ b/gas/testsuite/gas/aarch64/msr.s @@ -34,3 +34,18 @@ func: msr spsel, #0 msr spsel, #1 + + msr csselr_el1, x0 + mrs x0, csselr_el1 + + msr vsesr_el2, x0 + mrs x0, vsesr_el2 + + msr osdtrrx_el1, x0 + mrs x0, osdtrrx_el1 + + msr osdtrtx_el1, x0 + mrs x0, osdtrtx_el1 + + msr pmsidr_el1, x0 + mrs x0, pmsidr_el1 diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index 149737e1ed..70d35ebdae 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,3 +1,9 @@ +2018-07-06 Tamar Christina + + PR binutils/23369 + * aarch64-opc.c (aarch64_sys_regs): Make read/write csselr_el1, + vsesr_el2, osdtrrx_el1, osdtrtx_el1, pmsidr_el1. + 2018-07-02 Maciej W. Rozycki PR tdep/8282 diff --git a/opcodes/aarch64-opc.c b/opcodes/aarch64-opc.c index 2a10f005a7..ba2af7bfc2 100644 --- a/opcodes/aarch64-opc.c +++ b/opcodes/aarch64-opc.c @@ -3735,7 +3735,7 @@ const aarch64_sys_reg aarch64_sys_regs [] = { "id_aa64afr1_el1", CPENC(3,0,C0,C5,5), F_REG_READ }, /* RO */ { "id_aa64zfr0_el1", CPENC (3, 0, C0, C4, 4), F_ARCHEXT | F_REG_READ }, /* RO */ { "clidr_el1", CPENC(3,1,C0,C0,1), F_REG_READ }, /* RO */ - { "csselr_el1", CPENC(3,2,C0,C0,0), F_REG_READ }, /* RO */ + { "csselr_el1", CPENC(3,2,C0,C0,0), 0 }, { "vpidr_el2", CPENC(3,4,C0,C0,0), 0 }, { "vmpidr_el2", CPENC(3,4,C0,C0,5), 0 }, { "sctlr_el1", CPENC(3,0,C1,C0,0), 0 }, @@ -3795,7 +3795,7 @@ const aarch64_sys_reg aarch64_sys_regs [] = { "esr_el2", CPENC(3,4,C5,C2,0), 0 }, { "esr_el3", CPENC(3,6,C5,C2,0), 0 }, { "esr_el12", CPENC (3, 5, C5, C2, 0), F_ARCHEXT }, - { "vsesr_el2", CPENC (3, 4, C5, C2, 3), F_ARCHEXT | F_REG_READ }, /* RO */ + { "vsesr_el2", CPENC (3, 4, C5, C2, 3), F_ARCHEXT }, { "fpexc32_el2", CPENC(3,4,C5,C3,0), 0 }, { "erridr_el1", CPENC (3, 0, C5, C3, 0), F_ARCHEXT | F_REG_READ }, /* RO */ { "errselr_el1", CPENC (3, 0, C5, C3, 1), F_ARCHEXT }, @@ -3879,8 +3879,8 @@ const aarch64_sys_reg aarch64_sys_regs [] = { "dbgdtr_el0", CPENC(2,3,C0, C4, 0), 0 }, { "dbgdtrrx_el0", CPENC(2,3,C0, C5, 0), F_REG_READ }, /* r */ { "dbgdtrtx_el0", CPENC(2,3,C0, C5, 0), F_REG_WRITE }, /* w */ - { "osdtrrx_el1", CPENC(2,0,C0, C0, 2), F_REG_READ }, /* r */ - { "osdtrtx_el1", CPENC(2,0,C0, C3, 2), F_REG_WRITE }, /* w */ + { "osdtrrx_el1", CPENC(2,0,C0, C0, 2), 0 }, + { "osdtrtx_el1", CPENC(2,0,C0, C3, 2), 0 }, { "oseccr_el1", CPENC(2,0,C0, C6, 2), 0 }, { "dbgvcr32_el2", CPENC(2,4,C0, C7, 0), 0 }, { "dbgbvr0_el1", CPENC(2,0,C0, C0, 4), 0 }, @@ -3965,7 +3965,7 @@ const aarch64_sys_reg aarch64_sys_regs [] = { "pmsfcr_el1", CPENC (3, 0, C9, C9, 4), F_ARCHEXT }, /* rw */ { "pmsevfr_el1", CPENC (3, 0, C9, C9, 5), F_ARCHEXT }, /* rw */ { "pmslatfr_el1", CPENC (3, 0, C9, C9, 6), F_ARCHEXT }, /* rw */ - { "pmsidr_el1", CPENC (3, 0, C9, C9, 7), F_ARCHEXT | F_REG_READ }, /* ro */ + { "pmsidr_el1", CPENC (3, 0, C9, C9, 7), F_ARCHEXT }, /* rw */ { "pmscr_el2", CPENC (3, 4, C9, C9, 0), F_ARCHEXT }, /* rw */ { "pmscr_el12", CPENC (3, 5, C9, C9, 0), F_ARCHEXT }, /* rw */ { "pmcr_el0", CPENC(3,3,C9,C12, 0), 0 },