From: Alan Modra Date: Mon, 11 May 2020 00:14:25 +0000 (+0930) Subject: Power10 bit manipulation operations X-Git-Url: http://git.efficios.com/?a=commitdiff_plain;h=ec40e91c77ecf4ca853577aa7d68bdaf5aeedfd5;p=deliverable%2Fbinutils-gdb.git Power10 bit manipulation operations opcodes/ * ppc-opc.c (UIM8, P_U8XX4_MASK): Define. (powerpc_opcodes): Add vgnb, vcfuged, vpextd, vpdepd, vclzdm, vctzdm, cntlzdm, pdepd, pextd, cfuged, cnttzdm. (prefix_opcodes): Add xxeval. gas/ * testsuite/gas/ppc/bitmanip.d, * testsuite/gas/ppc/bitmanip.s: New test. * testsuite/gas/ppc/ppc.exp: Run it. --- diff --git a/gas/ChangeLog b/gas/ChangeLog index 04eede4a6f..11a20f5a06 100644 --- a/gas/ChangeLog +++ b/gas/ChangeLog @@ -1,3 +1,9 @@ +2020-05-11 Alan Modra + + * testsuite/gas/ppc/bitmanip.d, + * testsuite/gas/ppc/bitmanip.s: New test. + * testsuite/gas/ppc/ppc.exp: Run it. + 2020-05-11 Alan Modra * testsuite/gas/ppc/genpcv.d, diff --git a/gas/testsuite/gas/ppc/bitmanip.d b/gas/testsuite/gas/ppc/bitmanip.d new file mode 100644 index 0000000000..27f4a0cfa6 --- /dev/null +++ b/gas/testsuite/gas/ppc/bitmanip.d @@ -0,0 +1,23 @@ +#as: -mpower10 +#objdump: -dr -Mpower10 +#name: bit manipulation + +.* + + +Disassembly of section \.text: + +0+0 <_start>: +.*: (7f df e9 b8|b8 e9 df 7f) cfuged r31,r30,r29 +.*: (7f 7c d0 76|76 d0 7c 7f) cntlzdm r28,r27,r26 +.*: (7f 19 bc 76|76 bc 19 7f) cnttzdm r25,r24,r23 +.*: (7e b6 a1 38|38 a1 b6 7e) pdepd r22,r21,r20 +.*: (7e 53 89 78|78 89 53 7e) pextd r19,r18,r17 +.*: (12 0f 77 84|84 77 0f 12) vclzdm v16,v15,v14 +.*: (11 ac 5f c4|c4 5f ac 11) vctzdm v13,v12,v11 +.*: (11 49 45 cd|cd 45 49 11) vpdepd v10,v9,v8 +.*: (10 e6 2d 8d|8d 2d e6 10) vpextd v7,v6,v5 +.*: (10 83 15 4d|4d 15 83 10) vcfuged v4,v3,v2 +.*: (10 27 04 cc|cc 04 27 10) vgnb r1,v0,7 +.*: (05 00 00 3f|3f 00 00 05) xxeval vs63,vs31,vs62,vs30,63 +.*: (8b ff f7 93|93 f7 ff 8b) diff --git a/gas/testsuite/gas/ppc/bitmanip.s b/gas/testsuite/gas/ppc/bitmanip.s new file mode 100644 index 0000000000..d4d5774df1 --- /dev/null +++ b/gas/testsuite/gas/ppc/bitmanip.s @@ -0,0 +1,14 @@ + .text +_start: + cfuged 31,30,29 + cntlzdm 28,27,26 + cnttzdm 25,24,23 + pdepd 22,21,20 + pextd 19,18,17 + vclzdm 16,15,14 + vctzdm 13,12,11 + vpdepd 10,9,8 + vpextd 7,6,5 + vcfuged 4,3,2 + vgnb 1,0,7 + xxeval 63,31,62,30,0x3f diff --git a/gas/testsuite/gas/ppc/ppc.exp b/gas/testsuite/gas/ppc/ppc.exp index 6b4e11a942..0e53a4caa3 100644 --- a/gas/testsuite/gas/ppc/ppc.exp +++ b/gas/testsuite/gas/ppc/ppc.exp @@ -140,3 +140,4 @@ run_dump_test "simd_perm" run_dump_test "outerprod" run_dump_test "maskmanip" run_dump_test "genpcv" +run_dump_test "bitmanip" diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index 9db4c82cf9..c53e18f7b7 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,3 +1,10 @@ +2020-05-11 Alan Modra + + * ppc-opc.c (UIM8, P_U8XX4_MASK): Define. + (powerpc_opcodes): Add vgnb, vcfuged, vpextd, vpdepd, vclzdm, + vctzdm, cntlzdm, pdepd, pextd, cfuged, cnttzdm. + (prefix_opcodes): Add xxeval. + 2020-05-11 Alan Modra * ppc-opc.c (powerpc_opcodes): Add xxgenpcvbm, xxgenpcvhm, diff --git a/opcodes/ppc-opc.c b/opcodes/ppc-opc.c index 804d013e5b..b8c841cc14 100644 --- a/opcodes/ppc-opc.c +++ b/opcodes/ppc-opc.c @@ -2306,8 +2306,12 @@ const struct powerpc_operand powerpc_operands[] = #define UIM3 IMM32 + 1 { 0x7, 32, NULL, NULL, 0}, + /* The UIM field in a vector eval prefix instruction. */ +#define UIM8 UIM3 + 1 + { 0xff, 32, NULL, NULL, 0}, + /* The IX field in xxsplti32dx. */ -#define IX UIM3 + 1 +#define IX UIM8 + 1 { 0x1, 17, NULL, NULL, 0 }, /* The PMSK field in GER rank 8 prefix instructions. */ @@ -3107,6 +3111,7 @@ const unsigned int num_powerpc_operands = (sizeof (powerpc_operands) /* Mask for prefix vector permute insns. */ #define P_XX4_MASK (PREFIX_MASK | XX4_MASK) #define P_UXX4_MASK (P_XX4_MASK & ~(7ULL << 32)) +#define P_U8XX4_MASK (P_XX4_MASK & ~(0xffULL << 32)) /* MMIRR:XX3-form 8-byte outer product instructions. */ #define P_GER_MASK ((-1ULL << 40) | XX3_MASK | (3 << 21) | 1) @@ -4738,6 +4743,7 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"evaddsmiaaw", VX (4,1225), VX_MASK, PPCSPE, 0, {RS, RA}}, {"evsubfumiaaw",VX (4,1226), VX_MASK, PPCSPE, 0, {RS, RA}}, {"evsubfsmiaaw",VX (4,1227), VX_MASK, PPCSPE, 0, {RS, RA}}, +{"vgnb", VX (4,1228), VX_MASK, POWER10, 0, {RT, VB, UIMM3}}, {"vpkudus", VX (4,1230), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, {"machhwso", XO (4, 108,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, {"machhwso.", XO (4, 108,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, @@ -4796,6 +4802,7 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"evmwlsmfaaw", VX (4,1355), VX_MASK, PPCSPE, 0, {RD, RA, RB}}, {"evmwhumiaa", VX (4,1356), VX_MASK, PPCSPE, 0, {RD, RA, RB}}, {"vbpermq", VX (4,1356), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, +{"vcfuged", VX (4,1357), VX_MASK, POWER10, 0, {VD, VA, VB}}, {"evmwhsmiaa", VX (4,1357), VX_MASK, PPCSPE, 0, {RD, RA, RB}}, {"vpksdus", VX (4,1358), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, {"evmwhsmfaa", VX (4,1359), VX_MASK, PPCSPE, 0, {RD, RA, RB}}, @@ -4834,6 +4841,7 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"evmhesmianw", VX (4,1417), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, {"evmhesmfanw", VX (4,1419), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, {"evmhoumianw", VX (4,1420), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, +{"vpextd", VX (4,1421), VX_MASK, POWER10, 0, {VD, VA, VB}}, {"evmhosmianw", VX (4,1421), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, {"evmhosmfanw", VX (4,1423), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, {"macchwsuo", XO (4, 204,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, @@ -4862,6 +4870,7 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"evmwlsmfanw", VX (4,1483), VX_MASK, PPCSPE, 0, {RD, RA, RB}}, {"evmwhumian", VX (4,1484), VX_MASK, PPCSPE, 0, {RD, RA, RB}}, {"vbpermd", VX (4,1484), VX_MASK, PPCVEC3, 0, {VD, VA, VB}}, +{"vpdepd", VX (4,1485), VX_MASK, POWER10, 0, {VD, VA, VB}}, {"evmwhsmian", VX (4,1485), VX_MASK, PPCSPE, 0, {RD, RA, RB}}, {"vpksdss", VX (4,1486), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, {"evmwhsmfan", VX (4,1487), VX_MASK, PPCSPE, 0, {RD, RA, RB}}, @@ -4977,6 +4986,7 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"vsubsws", VX (4,1920), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, {"vclzw", VX (4,1922), VXVA_MASK, PPCVEC2, 0, {VD, VB}}, {"vpopcntw", VX (4,1923), VXVA_MASK, PPCVEC2, 0, {VD, VB}}, +{"vclzdm", VX (4,1924), VX_MASK, POWER10, 0, {VD, VA, VB}}, {"vcmpgtsw.", VXR(4, 902,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}}, {"udi14fcm.", APU(4, 963,0), APU_MASK, PPC440, 0, {URT, URA, URB}}, {"vcmpgtsq.", VXR(4, 903,1), VXR_MASK, POWER10, 0, {VD, VA, VB}}, @@ -4989,6 +4999,7 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"maclhwsuo.", XO (4, 460,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, {"vclzd", VX (4,1986), VXVA_MASK, PPCVEC2, 0, {VD, VB}}, {"vpopcntd", VX (4,1987), VXVA_MASK, PPCVEC2, 0, {VD, VB}}, +{"vctzdm", VX (4,1988), VX_MASK, POWER10, 0, {VD, VA, VB}}, {"vcmpbfp.", VXR(4, 966,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}}, {"udi15fcm.", APU(4, 995,0), APU_MASK, PPC440, 0, {URT, URA, URB}}, {"vcmpgtsd.", VXR(4, 967,1), VXR_MASK, PPCVEC2, 0, {VD, VA, VB}}, @@ -6102,6 +6113,8 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"cntlzd", XRC(31,58,0), XRB_MASK, PPC64, 0, {RA, RS}}, {"cntlzd.", XRC(31,58,1), XRB_MASK, PPC64, 0, {RA, RS}}, +{"cntlzdm", X(31,59), X_MASK, POWER10, 0, {RA, RS, RB}}, + {"andc", XRC(31,60,0), X_MASK, COM, 0, {RA, RS, RB}}, {"andc.", XRC(31,60,1), X_MASK, COM, 0, {RA, RS, RB}}, @@ -6236,6 +6249,7 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"prtyw", X(31,154), XRB_MASK, POWER6|PPCA2|PPC476, 0, {RA, RS}}, {"brw", X(31,155), XRB_MASK, POWER10, 0, {RA, RS}}, +{"pdepd", X(31,156), X_MASK, POWER10, 0, {RA, RS, RB}}, {"stdepx", X(31,157), X_MASK, E500MC|PPCA2, 0, {RS, RA0, RB}}, @@ -6278,6 +6292,7 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"prtyd", X(31,186), XRB_MASK, POWER6|PPCA2, 0, {RA, RS}}, {"brd", X(31,187), XRB_MASK, POWER10, 0, {RA, RS}}, +{"pextd", X(31,188), X_MASK, POWER10, 0, {RA, RS, RB}}, {"cmprb", X(31,192), XCMP_MASK, POWER9, 0, {BF, L, RA, RB}}, @@ -6318,6 +6333,7 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"sleq.", XRC(31,217,1), X_MASK, M601, 0, {RA, RS, RB}}, {"brh", X(31,219), XRB_MASK, POWER10, 0, {RA, RS}}, +{"cfuged", X(31,220), X_MASK, POWER10, 0, {RA, RS, RB}}, {"stbepx", X(31,223), X_MASK, E500MC|PPCA2, 0, {RS, RA0, RB}}, @@ -7170,6 +7186,8 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"cnttzd", XRC(31,570,0), XRB_MASK, POWER9, 0, {RA, RS}}, {"cnttzd.", XRC(31,570,1), XRB_MASK, POWER9, 0, {RA, RS}}, +{"cnttzdm", X(31,571), X_MASK, POWER10, 0, {RA, RS, RB}}, + {"mcrxrx", X(31,576), XBFRARB_MASK, POWER9, 0, {BF}}, {"lwdcbx", X(31,578), X_MASK, E200Z4, 0, {RT, RA, RB}}, @@ -8408,6 +8426,7 @@ const struct powerpc_opcode prefix_opcodes[] = { {"xxblendvw", P8RR|XX4(33,2), P_XX4_MASK, POWER10, 0, {XT6, XA6, XB6, XC6}}, {"xxblendvd", P8RR|XX4(33,3), P_XX4_MASK, POWER10, 0, {XT6, XA6, XB6, XC6}}, {"xxpermx", P8RR|XX4(34,0), P_UXX4_MASK, POWER10, 0, {XT6, XA6, XB6, XC6, UIM3}}, +{"xxeval", P8RR|XX4(34,1), P_U8XX4_MASK, POWER10, 0, {XT6, XA6, XB6, XC6, UIM8}}, {"plbz", PMLS|OP(34), P_D_MASK, POWER10, 0, {RT, D34, PRA0, PCREL}}, {"pstw", PMLS|OP(36), P_D_MASK, POWER10, 0, {RS, D34, PRA0, PCREL}}, {"pstb", PMLS|OP(38), P_D_MASK, POWER10, 0, {RS, D34, PRA0, PCREL}},