From e23eba971dd409b999dd83d8df0f842680c1c642 Mon Sep 17 00:00:00 2001 From: Nick Clifton Date: Tue, 1 Nov 2016 16:45:57 +0000 Subject: [PATCH] Add support for RISC-V architecture. bfd * Makefile.am: Add entries for riscv32-elf and riscv64-elf. * config.bdf: Likewise. * configure.ac: Likewise. * Makefile.in: Regenerate. * configure: Regenerate. * archures.c: Add bfd_riscv_arch. * reloc.c: Add riscv relocs. * targets.c: Add riscv_elf32_vec and riscv_elf64_vec. * bfd-in2.h: Regenerate. * libbfd.h: Regenerate. * elf-bfd.h: Add RISCV_ELF_DATA to enum elf_target_id. * elfnn-riscv.c: New file. * elfxx-riscv.c: New file. * elfxx-riscv.h: New file. binutils* readelf.c (guess_is_rela): Add EM_RISCV. (get_machine_name): Likewise. (dump_relocations): Add support for riscv relocations. (get_machine_flags): Add support for riscv flags. (is_32bit_abs_reloc): Add R_RISCV_32. (is_64bit_abs_reloc): Add R_RISCV_64. (is_none_reloc): Add R_RISCV_NONE. * testsuite/binutils-all/objdump.exp (cpus_expected): Add riscv. Expect the debug_ranges test to fail. gas * Makefile.am: Add riscv files. * Makefile.in: Regenerate. * NEWS: Mention the support for this architecture. * configure.in: Define a default architecture. * configure: Regenerate. * configure.tgt: Add entries for riscv. * doc/as.texinfo: Likewise. * testsuite/gas/all/gas.exp: Expect the redef tests to fail. * testsuite/gas/elf/elf.exp: Expect the groupauto tests to fail. * config/tc-riscv.c: New file. * config/tc-riscv.h: New file. * doc/c-riscv.texi: New file. * testsuite/gas/riscv: New directory. * testsuite/gas/riscv/riscv.exp: New file. * testsuite/gas/riscv/t_insns.d: New file. * testsuite/gas/riscv/t_insns.s: New file. ld * Makefile.am: Add riscv files. * Makefile.in: Regenerate. * NEWS: Mention the support for this target. * configure.tgt: Add riscv entries. * emulparams/elf32lriscv-defs.sh: New file. * emulparams/elf32lriscv.sh: New file. * emulparams/elf64lriscv-defs.sh: New file. * emulparams/elf64lriscv.sh: New file. * emultempl/riscvelf.em: New file. opcodes * configure.ac: Add entry for bfd_riscv_arch. * configure: Regenerate. * disassemble.c (disassembler): Add support for riscv. (disassembler_usage): Likewise. * riscv-dis.c: New file. * riscv-opc.c: New file. include * dis-asm.h: Add prototypes for print_insn_riscv and print_riscv_disassembler_options. * elf/riscv.h: New file. * opcode/riscv-opc.h: New file. * opcode/riscv.h: New file. --- bfd/ChangeLog | 19 + bfd/Makefile.am | 28 +- bfd/Makefile.in | 32 +- bfd/archures.c | 7 +- bfd/bfd-in2.h | 43 + bfd/config.bfd | 15 + bfd/configure | 2 + bfd/configure.ac | 2 + bfd/cpu-riscv.c | 79 + bfd/elf-bfd.h | 1 + bfd/elfnn-riscv.c | 3160 +++++++++++++++++++ bfd/elfxx-riscv.c | 815 +++++ bfd/elfxx-riscv.h | 33 + bfd/libbfd.h | 38 + bfd/reloc.c | 80 + bfd/targets.c | 6 + binutils/ChangeLog | 14 + binutils/readelf.c | 20 +- binutils/testsuite/binutils-all/objdump.exp | 4 +- gas/ChangeLog | 21 + gas/Makefile.am | 2 + gas/Makefile.in | 17 + gas/NEWS | 2 + gas/config/tc-riscv.c | 2408 ++++++++++++++ gas/config/tc-riscv.h | 101 + gas/configure | 2 +- gas/configure.ac | 2 +- gas/configure.tgt | 6 +- gas/doc/as.texinfo | 19 + gas/doc/c-riscv.texi | 48 + gas/testsuite/gas/all/gas.exp | 8 +- gas/testsuite/gas/elf/elf.exp | 3 + gas/testsuite/gas/riscv/riscv.exp | 23 + gas/testsuite/gas/riscv/t_insns.d | 10 + gas/testsuite/gas/riscv/t_insns.s | 2 + include/ChangeLog | 10 + include/dis-asm.h | 2 + include/elf/riscv.h | 92 + include/opcode/riscv-opc.h | 1160 +++++++ include/opcode/riscv.h | 342 ++ ld/ChangeLog | 14 + ld/Makefile.am | 13 + ld/Makefile.in | 15 + ld/NEWS | 2 +- ld/configure.tgt | 6 + ld/emulparams/elf32lriscv-defs.sh | 42 + ld/emulparams/elf32lriscv.sh | 2 + ld/emulparams/elf64lriscv-defs.sh | 13 + ld/emulparams/elf64lriscv.sh | 2 + ld/emultempl/riscvelf.em | 68 + opcodes/ChangeLog | 11 + opcodes/configure | 1 + opcodes/configure.ac | 1 + opcodes/disassemble.c | 8 + opcodes/riscv-dis.c | 502 +++ opcodes/riscv-opc.c | 624 ++++ 56 files changed, 9982 insertions(+), 20 deletions(-) create mode 100644 bfd/cpu-riscv.c create mode 100644 bfd/elfnn-riscv.c create mode 100644 bfd/elfxx-riscv.c create mode 100644 bfd/elfxx-riscv.h create mode 100644 gas/config/tc-riscv.c create mode 100644 gas/config/tc-riscv.h create mode 100644 gas/doc/c-riscv.texi create mode 100644 gas/testsuite/gas/riscv/riscv.exp create mode 100644 gas/testsuite/gas/riscv/t_insns.d create mode 100644 gas/testsuite/gas/riscv/t_insns.s create mode 100644 include/elf/riscv.h create mode 100644 include/opcode/riscv-opc.h create mode 100644 include/opcode/riscv.h create mode 100644 ld/emulparams/elf32lriscv-defs.sh create mode 100644 ld/emulparams/elf32lriscv.sh create mode 100644 ld/emulparams/elf64lriscv-defs.sh create mode 100644 ld/emulparams/elf64lriscv.sh create mode 100644 ld/emultempl/riscvelf.em create mode 100644 opcodes/riscv-dis.c create mode 100644 opcodes/riscv-opc.c diff --git a/bfd/ChangeLog b/bfd/ChangeLog index 5e0a918a6b..75ffab57f8 100644 --- a/bfd/ChangeLog +++ b/bfd/ChangeLog @@ -1,3 +1,22 @@ +2016-11-01 Palmer Dabbelt + Andrew Waterman + + Add support for RISC-V architecture. + * Makefile.am: Add entries for riscv32-elf and riscv64-elf. + * config.bdf: Likewise. + * configure.ac: Likewise. + * Makefile.in: Regenerate. + * configure: Regenerate. + * archures.c: Add bfd_riscv_arch. + * reloc.c: Add riscv relocs. + * targets.c: Add riscv_elf32_vec and riscv_elf64_vec. + * bfd-in2.h: Regenerate. + * libbfd.h: Regenerate. + * elf-bfd.h: Add RISCV_ELF_DATA to enum elf_target_id. + * elfnn-riscv.c: New file. + * elfxx-riscv.c: New file. + * elfxx-riscv.h: New file. + 2016-10-31 Alan Modra PR 20748 diff --git a/bfd/Makefile.am b/bfd/Makefile.am index e04be5a560..0d5dd4a423 100644 --- a/bfd/Makefile.am +++ b/bfd/Makefile.am @@ -148,6 +148,7 @@ ALL_MACHINES = \ cpu-plugin.lo \ cpu-powerpc.lo \ cpu-rs6000.lo \ + cpu-riscv.lo \ cpu-rl78.lo \ cpu-rx.lo \ cpu-s390.lo \ @@ -235,6 +236,7 @@ ALL_MACHINES_CFILES = \ cpu-plugin.c \ cpu-powerpc.c \ cpu-rs6000.c \ + cpu-riscv.c \ cpu-rl78.c \ cpu-rx.c \ cpu-s390.c \ @@ -671,18 +673,21 @@ BFD64_BACKENDS = \ elf64-hppa.lo \ elf64-ia64.lo \ elf64-ia64-vms.lo \ + elfxx-ia64.lo \ + elfn32-mips.lo \ elf64-mips.lo \ + elfxx-mips.lo \ elf64-mmix.lo \ elf64-ppc.lo \ + elf32-riscv.lo \ + elf64-riscv.lo \ + elfxx-riscv.lo \ elf64-s390.lo \ elf64-sh64.lo \ elf64-sparc.lo \ elf64-tilegx.lo \ elf64-x86-64.lo \ elf64.lo \ - elfn32-mips.lo \ - elfxx-ia64.lo \ - elfxx-mips.lo \ mach-o-aarch64.lo \ mach-o-x86-64.lo \ mmo.lo \ @@ -722,6 +727,7 @@ BFD64_BACKENDS_CFILES = \ elfxx-aarch64.c \ elfxx-ia64.c \ elfxx-mips.c \ + elfxx-riscv.c \ mach-o-aarch64.c \ mach-o-x86-64.c \ mmo.c \ @@ -785,7 +791,9 @@ SOURCE_CFILES = \ BUILD_CFILES = \ elf32-aarch64.c elf64-aarch64.c \ - elf32-ia64.c elf64-ia64.c peigen.c pepigen.c pex64igen.c + elf32-ia64.c elf64-ia64.c \ + elf32-riscv.c elf64-riscv.c \ + peigen.c pepigen.c pex64igen.c CFILES = $(SOURCE_CFILES) $(BUILD_CFILES) @@ -955,6 +963,18 @@ elf64-ia64.c : elfnn-ia64.c $(SED) -e s/NN/64/g < $(srcdir)/elfnn-ia64.c > elf64-ia64.new mv -f elf64-ia64.new elf64-ia64.c +elf32-riscv.c : elfnn-riscv.c + rm -f elf32-riscv.c + echo "#line 1 \"$(srcdir)/elfnn-riscv.c\"" > elf32-riscv.new + sed -e s/NN/32/g < $(srcdir)/elfnn-riscv.c >> elf32-riscv.new + mv -f elf32-riscv.new elf32-riscv.c + +elf64-riscv.c : elfnn-riscv.c + rm -f elf64-riscv.c + echo "#line 1 \"$(srcdir)/elfnn-riscv.c\"" > elf64-riscv.new + sed -e s/NN/64/g < $(srcdir)/elfnn-riscv.c >> elf64-riscv.new + mv -f elf64-riscv.new elf64-riscv.c + peigen.c : peXXigen.c rm -f peigen.c $(SED) -e s/XX/pe/g < $(srcdir)/peXXigen.c > peigen.new diff --git a/bfd/Makefile.in b/bfd/Makefile.in index 64658c5081..661155c833 100644 --- a/bfd/Makefile.in +++ b/bfd/Makefile.in @@ -481,6 +481,7 @@ ALL_MACHINES = \ cpu-plugin.lo \ cpu-powerpc.lo \ cpu-rs6000.lo \ + cpu-riscv.lo \ cpu-rl78.lo \ cpu-rx.lo \ cpu-s390.lo \ @@ -568,6 +569,7 @@ ALL_MACHINES_CFILES = \ cpu-plugin.c \ cpu-powerpc.c \ cpu-rs6000.c \ + cpu-riscv.c \ cpu-rl78.c \ cpu-rx.c \ cpu-s390.c \ @@ -1006,18 +1008,21 @@ BFD64_BACKENDS = \ elf64-hppa.lo \ elf64-ia64.lo \ elf64-ia64-vms.lo \ + elfxx-ia64.lo \ + elfn32-mips.lo \ elf64-mips.lo \ + elfxx-mips.lo \ elf64-mmix.lo \ elf64-ppc.lo \ + elf32-riscv.lo \ + elf64-riscv.lo \ + elfxx-riscv.lo \ elf64-s390.lo \ elf64-sh64.lo \ elf64-sparc.lo \ elf64-tilegx.lo \ elf64-x86-64.lo \ elf64.lo \ - elfn32-mips.lo \ - elfxx-ia64.lo \ - elfxx-mips.lo \ mach-o-aarch64.lo \ mach-o-x86-64.lo \ mmo.lo \ @@ -1057,6 +1062,7 @@ BFD64_BACKENDS_CFILES = \ elfxx-aarch64.c \ elfxx-ia64.c \ elfxx-mips.c \ + elfxx-riscv.c \ mach-o-aarch64.c \ mach-o-x86-64.c \ mmo.c \ @@ -1122,7 +1128,9 @@ SOURCE_CFILES = \ BUILD_CFILES = \ elf32-aarch64.c elf64-aarch64.c \ - elf32-ia64.c elf64-ia64.c peigen.c pepigen.c pex64igen.c + elf32-ia64.c elf64-ia64.c \ + elf32-riscv.c elf64-riscv.c \ + peigen.c pepigen.c pex64igen.c CFILES = $(SOURCE_CFILES) $(BUILD_CFILES) SOURCE_HFILES = \ @@ -1412,6 +1420,7 @@ distclean-compile: @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/cpu-pj.Plo@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/cpu-plugin.Plo@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/cpu-powerpc.Plo@am__quote@ +@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/cpu-riscv.Plo@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/cpu-rl78.Plo@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/cpu-rs6000.Plo@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/cpu-rx.Plo@am__quote@ @@ -1501,6 +1510,7 @@ distclean-compile: @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf32-or1k.Plo@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf32-pj.Plo@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf32-ppc.Plo@am__quote@ +@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf32-riscv.Plo@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf32-rl78.Plo@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf32-rx.Plo@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf32-s390.Plo@am__quote@ @@ -1532,6 +1542,7 @@ distclean-compile: @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf64-mips.Plo@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf64-mmix.Plo@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf64-ppc.Plo@am__quote@ +@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf64-riscv.Plo@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf64-s390.Plo@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf64-sh64.Plo@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf64-sparc.Plo@am__quote@ @@ -1543,6 +1554,7 @@ distclean-compile: @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elfxx-aarch64.Plo@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elfxx-ia64.Plo@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elfxx-mips.Plo@am__quote@ +@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elfxx-riscv.Plo@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elfxx-sparc.Plo@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elfxx-tilegx.Plo@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/epoc-pe-arm.Plo@am__quote@ @@ -2080,6 +2092,18 @@ elf64-ia64.c : elfnn-ia64.c $(SED) -e s/NN/64/g < $(srcdir)/elfnn-ia64.c > elf64-ia64.new mv -f elf64-ia64.new elf64-ia64.c +elf32-riscv.c : elfnn-riscv.c + rm -f elf32-riscv.c + echo "#line 1 \"$(srcdir)/elfnn-riscv.c\"" > elf32-riscv.new + sed -e s/NN/32/g < $(srcdir)/elfnn-riscv.c >> elf32-riscv.new + mv -f elf32-riscv.new elf32-riscv.c + +elf64-riscv.c : elfnn-riscv.c + rm -f elf64-riscv.c + echo "#line 1 \"$(srcdir)/elfnn-riscv.c\"" > elf64-riscv.new + sed -e s/NN/64/g < $(srcdir)/elfnn-riscv.c >> elf64-riscv.new + mv -f elf64-riscv.new elf64-riscv.c + peigen.c : peXXigen.c rm -f peigen.c $(SED) -e s/XX/pe/g < $(srcdir)/peXXigen.c > peigen.new diff --git a/bfd/archures.c b/bfd/archures.c index af70b18157..e503492310 100644 --- a/bfd/archures.c +++ b/bfd/archures.c @@ -457,6 +457,9 @@ DESCRIPTION .#define bfd_mach_cris_v0_v10 255 .#define bfd_mach_cris_v32 32 .#define bfd_mach_cris_v10_v32 1032 +. bfd_arch_riscv, +.#define bfd_mach_riscv32 132 +.#define bfd_mach_riscv64 164 . bfd_arch_rl78, .#define bfd_mach_rl78 0x75 . bfd_arch_rx, {* Renesas RX. *} @@ -628,6 +631,7 @@ extern const bfd_arch_info_type bfd_pj_arch; extern const bfd_arch_info_type bfd_plugin_arch; extern const bfd_arch_info_type bfd_powerpc_archs[]; #define bfd_powerpc_arch bfd_powerpc_archs[0] +extern const bfd_arch_info_type bfd_riscv_arch; extern const bfd_arch_info_type bfd_rs6000_arch; extern const bfd_arch_info_type bfd_rl78_arch; extern const bfd_arch_info_type bfd_rx_arch; @@ -717,8 +721,9 @@ static const bfd_arch_info_type * const bfd_archures_list[] = &bfd_or1k_arch, &bfd_pdp11_arch, &bfd_powerpc_arch, - &bfd_rs6000_arch, + &bfd_riscv_arch, &bfd_rl78_arch, + &bfd_rs6000_arch, &bfd_rx_arch, &bfd_s390_arch, &bfd_score_arch, diff --git a/bfd/bfd-in2.h b/bfd/bfd-in2.h index 3c0ff9d8ea..fdb7878828 100644 --- a/bfd/bfd-in2.h +++ b/bfd/bfd-in2.h @@ -2295,6 +2295,9 @@ enum bfd_architecture #define bfd_mach_cris_v0_v10 255 #define bfd_mach_cris_v32 32 #define bfd_mach_cris_v10_v32 1032 + bfd_arch_riscv, +#define bfd_mach_riscv32 132 +#define bfd_mach_riscv64 164 bfd_arch_rl78, #define bfd_mach_rl78 0x75 bfd_arch_rx, /* Renesas RX. */ @@ -4691,6 +4694,46 @@ number for the IN and OUT instructions */ number for the SBIC, SBIS, SBI and CBI instructions */ BFD_RELOC_AVR_PORT5, +/* RISC-V relocations. */ + BFD_RELOC_RISCV_HI20, + BFD_RELOC_RISCV_PCREL_HI20, + BFD_RELOC_RISCV_PCREL_LO12_I, + BFD_RELOC_RISCV_PCREL_LO12_S, + BFD_RELOC_RISCV_LO12_I, + BFD_RELOC_RISCV_LO12_S, + BFD_RELOC_RISCV_GPREL12_I, + BFD_RELOC_RISCV_GPREL12_S, + BFD_RELOC_RISCV_TPREL_HI20, + BFD_RELOC_RISCV_TPREL_LO12_I, + BFD_RELOC_RISCV_TPREL_LO12_S, + BFD_RELOC_RISCV_TPREL_ADD, + BFD_RELOC_RISCV_CALL, + BFD_RELOC_RISCV_CALL_PLT, + BFD_RELOC_RISCV_ADD8, + BFD_RELOC_RISCV_ADD16, + BFD_RELOC_RISCV_ADD32, + BFD_RELOC_RISCV_ADD64, + BFD_RELOC_RISCV_SUB8, + BFD_RELOC_RISCV_SUB16, + BFD_RELOC_RISCV_SUB32, + BFD_RELOC_RISCV_SUB64, + BFD_RELOC_RISCV_GOT_HI20, + BFD_RELOC_RISCV_TLS_GOT_HI20, + BFD_RELOC_RISCV_TLS_GD_HI20, + BFD_RELOC_RISCV_JMP, + BFD_RELOC_RISCV_TLS_DTPMOD32, + BFD_RELOC_RISCV_TLS_DTPREL32, + BFD_RELOC_RISCV_TLS_DTPMOD64, + BFD_RELOC_RISCV_TLS_DTPREL64, + BFD_RELOC_RISCV_TLS_TPREL32, + BFD_RELOC_RISCV_TLS_TPREL64, + BFD_RELOC_RISCV_ALIGN, + BFD_RELOC_RISCV_RVC_BRANCH, + BFD_RELOC_RISCV_RVC_JUMP, + BFD_RELOC_RISCV_RVC_LUI, + BFD_RELOC_RISCV_GPREL_I, + BFD_RELOC_RISCV_GPREL_S, + /* Renesas RL78 Relocations. */ BFD_RELOC_RL78_NEG8, BFD_RELOC_RL78_NEG16, diff --git a/bfd/config.bfd b/bfd/config.bfd index 6400722282..98663fd0af 100644 --- a/bfd/config.bfd +++ b/bfd/config.bfd @@ -122,6 +122,7 @@ or1k*|or1knd*) targ_archs=bfd_or1k_arch ;; pdp11*) targ_archs=bfd_pdp11_arch ;; pj*) targ_archs="bfd_pj_arch bfd_i386_arch";; powerpc*) targ_archs="bfd_rs6000_arch bfd_powerpc_arch" ;; +riscv*) targ_archs=bfd_riscv_arch ;; rs6000) targ_archs="bfd_rs6000_arch bfd_powerpc_arch" ;; s390*) targ_archs=bfd_s390_arch ;; sh*) targ_archs=bfd_sh_arch ;; @@ -1359,6 +1360,20 @@ case "${targ}" in targ_selvecs="powerpc_pei_le_vec powerpc_pei_vec powerpc_pe_le_vec powerpc_pe_vec" ;; +#ifdef BFD64 + riscv32-*-*) + targ_defvec=riscv_elf32_vec + targ_selvecs="riscv_elf32_vec" + want64=true + ;; + + riscv64-*-*) + targ_defvec=riscv_elf64_vec + targ_selvecs="riscv_elf32_vec riscv_elf64_vec" + want64=true + ;; +#endif + rl78-*-elf) targ_defvec=rl78_elf32_vec ;; diff --git a/bfd/configure b/bfd/configure index 828406952f..68db12f34f 100755 --- a/bfd/configure +++ b/bfd/configure @@ -14475,6 +14475,8 @@ do powerpc_pei_vec) tb="$tb pei-ppc.lo peigen.lo $coff" ;; powerpc_pei_le_vec) tb="$tb pei-ppc.lo peigen.lo $coff" ;; powerpc_xcoff_vec) tb="$tb coff-rs6000.lo $xcoff" ;; + riscv_elf32_vec) tb="$tb elf32-riscv.lo elfxx-riscv.lo elf32.lo $elf" ;; + riscv_elf64_vec) tb="$tb elf64-riscv.lo elf64.lo elfxx-riscv.lo elf32.lo $elf"; target_size=64 ;; rl78_elf32_vec) tb="$tb elf32-rl78.lo elf32.lo $elf" ;; rs6000_xcoff64_vec) tb="$tb coff64-rs6000.lo aix5ppc-core.lo $xcoff"; target_size=64 ;; rs6000_xcoff64_aix_vec) tb="$tb coff64-rs6000.lo aix5ppc-core.lo $xcoff"; target_size=64 ;; diff --git a/bfd/configure.ac b/bfd/configure.ac index 669cff7532..6f11d293ee 100644 --- a/bfd/configure.ac +++ b/bfd/configure.ac @@ -606,6 +606,8 @@ do powerpc_pei_vec) tb="$tb pei-ppc.lo peigen.lo $coff" ;; powerpc_pei_le_vec) tb="$tb pei-ppc.lo peigen.lo $coff" ;; powerpc_xcoff_vec) tb="$tb coff-rs6000.lo $xcoff" ;; + riscv_elf32_vec) tb="$tb elf32-riscv.lo elfxx-riscv.lo elf32.lo $elf" ;; + riscv_elf64_vec) tb="$tb elf64-riscv.lo elf64.lo elfxx-riscv.lo elf32.lo $elf"; target_size=64 ;; rl78_elf32_vec) tb="$tb elf32-rl78.lo elf32.lo $elf" ;; rs6000_xcoff64_vec) tb="$tb coff64-rs6000.lo aix5ppc-core.lo $xcoff"; target_size=64 ;; rs6000_xcoff64_aix_vec) tb="$tb coff64-rs6000.lo aix5ppc-core.lo $xcoff"; target_size=64 ;; diff --git a/bfd/cpu-riscv.c b/bfd/cpu-riscv.c new file mode 100644 index 0000000000..a938199889 --- /dev/null +++ b/bfd/cpu-riscv.c @@ -0,0 +1,79 @@ +/* BFD backend for RISC-V + Copyright 2011-2016 Free Software Foundation, Inc. + + Contributed by Andrew Waterman (andrew@sifive.com). + Based on MIPS target. + + This file is part of BFD, the Binary File Descriptor library. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; see the file COPYING3. If not, + see . */ + +#include "sysdep.h" +#include "bfd.h" +#include "libbfd.h" + +/* This routine is provided two arch_infos and returns an arch_info + that is compatible with both, or NULL if none exists. */ + +static const bfd_arch_info_type * +riscv_compatible (const bfd_arch_info_type *a, const bfd_arch_info_type *b) +{ + if (a->arch != b->arch) + return NULL; + + /* Machine compatibility is checked in + _bfd_riscv_elf_merge_private_bfd_data. */ + + return a; +} + +#define N(BITS_WORD, BITS_ADDR, NUMBER, PRINT, DEFAULT, NEXT) \ + { \ + BITS_WORD, /* bits in a word */ \ + BITS_ADDR, /* bits in an address */ \ + 8, /* 8 bits in a byte */ \ + bfd_arch_riscv, \ + NUMBER, \ + "riscv", \ + PRINT, \ + 3, \ + DEFAULT, \ + riscv_compatible, \ + bfd_default_scan, \ + bfd_arch_default_fill, \ + NEXT, \ + } + +/* This enum must be kept in the same order as arch_info_struct. */ +enum +{ + I_riscv64, + I_riscv32 +}; + +#define NN(index) (&arch_info_struct[(index) + 1]) + +/* This array must be kept in the same order as the anonymous enum above, + and each entry except the last should end with NN (my enum value). */ +static const bfd_arch_info_type arch_info_struct[] = +{ + N (64, 64, bfd_mach_riscv64, "riscv:rv64", FALSE, NN (I_riscv64)), + N (32, 32, bfd_mach_riscv32, "riscv:rv32", FALSE, 0) +}; + +/* The default architecture is riscv:rv64. */ + +const bfd_arch_info_type bfd_riscv_arch = + N (64, 64, 0, "riscv", TRUE, &arch_info_struct[0]); diff --git a/bfd/elf-bfd.h b/bfd/elf-bfd.h index af2af2c5e3..50151cbcbb 100644 --- a/bfd/elf-bfd.h +++ b/bfd/elf-bfd.h @@ -477,6 +477,7 @@ enum elf_target_id XGATE_ELF_DATA, TILEGX_ELF_DATA, TILEPRO_ELF_DATA, + RISCV_ELF_DATA, GENERIC_ELF_DATA }; diff --git a/bfd/elfnn-riscv.c b/bfd/elfnn-riscv.c new file mode 100644 index 0000000000..be1de22670 --- /dev/null +++ b/bfd/elfnn-riscv.c @@ -0,0 +1,3160 @@ +/* RISC-V-specific support for NN-bit ELF. + Copyright 2011-2016 Free Software Foundation, Inc. + + Contributed by Andrew Waterman (andrew@sifive.com). + Based on TILE-Gx and MIPS targets. + + This file is part of BFD, the Binary File Descriptor library. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; see the file COPYING3. If not, + see . */ + +/* This file handles RISC-V ELF targets. */ + +#include "sysdep.h" +#include "bfd.h" +#include "libbfd.h" +#include "bfdlink.h" +#include "genlink.h" +#include "elf-bfd.h" +#include "elfxx-riscv.h" +#include "elf/riscv.h" +#include "opcode/riscv.h" + +#define ARCH_SIZE NN + +#define MINUS_ONE ((bfd_vma)0 - 1) + +#define RISCV_ELF_LOG_WORD_BYTES (ARCH_SIZE == 32 ? 2 : 3) + +#define RISCV_ELF_WORD_BYTES (1 << RISCV_ELF_LOG_WORD_BYTES) + +/* The name of the dynamic interpreter. This is put in the .interp + section. */ + +#define ELF64_DYNAMIC_INTERPRETER "/lib/ld.so.1" +#define ELF32_DYNAMIC_INTERPRETER "/lib32/ld.so.1" + +#define ELF_ARCH bfd_arch_riscv +#define ELF_TARGET_ID RISCV_ELF_DATA +#define ELF_MACHINE_CODE EM_RISCV +#define ELF_MAXPAGESIZE 0x1000 +#define ELF_COMMONPAGESIZE 0x1000 + +/* The RISC-V linker needs to keep track of the number of relocs that it + decides to copy as dynamic relocs in check_relocs for each symbol. + This is so that it can later discard them if they are found to be + unnecessary. We store the information in a field extending the + regular ELF linker hash table. */ + +struct riscv_elf_dyn_relocs +{ + struct riscv_elf_dyn_relocs *next; + + /* The input section of the reloc. */ + asection *sec; + + /* Total number of relocs copied for the input section. */ + bfd_size_type count; + + /* Number of pc-relative relocs copied for the input section. */ + bfd_size_type pc_count; +}; + +/* RISC-V ELF linker hash entry. */ + +struct riscv_elf_link_hash_entry +{ + struct elf_link_hash_entry elf; + + /* Track dynamic relocs copied for this symbol. */ + struct riscv_elf_dyn_relocs *dyn_relocs; + +#define GOT_UNKNOWN 0 +#define GOT_NORMAL 1 +#define GOT_TLS_GD 2 +#define GOT_TLS_IE 4 +#define GOT_TLS_LE 8 + char tls_type; +}; + +#define riscv_elf_hash_entry(ent) \ + ((struct riscv_elf_link_hash_entry *)(ent)) + +struct _bfd_riscv_elf_obj_tdata +{ + struct elf_obj_tdata root; + + /* tls_type for each local got entry. */ + char *local_got_tls_type; +}; + +#define _bfd_riscv_elf_tdata(abfd) \ + ((struct _bfd_riscv_elf_obj_tdata *) (abfd)->tdata.any) + +#define _bfd_riscv_elf_local_got_tls_type(abfd) \ + (_bfd_riscv_elf_tdata (abfd)->local_got_tls_type) + +#define _bfd_riscv_elf_tls_type(abfd, h, symndx) \ + (*((h) != NULL ? &riscv_elf_hash_entry (h)->tls_type \ + : &_bfd_riscv_elf_local_got_tls_type (abfd) [symndx])) + +#define is_riscv_elf(bfd) \ + (bfd_get_flavour (bfd) == bfd_target_elf_flavour \ + && elf_tdata (bfd) != NULL \ + && elf_object_id (bfd) == RISCV_ELF_DATA) + +#include "elf/common.h" +#include "elf/internal.h" + +struct riscv_elf_link_hash_table +{ + struct elf_link_hash_table elf; + + /* Short-cuts to get to dynamic linker sections. */ + asection *sdynbss; + asection *srelbss; + asection *sdyntdata; + + /* Small local sym to section mapping cache. */ + struct sym_cache sym_cache; +}; + + +/* Get the RISC-V ELF linker hash table from a link_info structure. */ +#define riscv_elf_hash_table(p) \ + (elf_hash_table_id ((struct elf_link_hash_table *) ((p)->hash)) \ + == RISCV_ELF_DATA ? ((struct riscv_elf_link_hash_table *) ((p)->hash)) : NULL) + +static void +riscv_info_to_howto_rela (bfd *abfd ATTRIBUTE_UNUSED, + arelent *cache_ptr, + Elf_Internal_Rela *dst) +{ + cache_ptr->howto = riscv_elf_rtype_to_howto (ELFNN_R_TYPE (dst->r_info)); +} + +static void +riscv_elf_append_rela (bfd *abfd, asection *s, Elf_Internal_Rela *rel) +{ + const struct elf_backend_data *bed; + bfd_byte *loc; + + bed = get_elf_backend_data (abfd); + loc = s->contents + (s->reloc_count++ * bed->s->sizeof_rela); + bed->s->swap_reloca_out (abfd, rel, loc); +} + +/* PLT/GOT stuff. */ + +#define PLT_HEADER_INSNS 8 +#define PLT_ENTRY_INSNS 4 +#define PLT_HEADER_SIZE (PLT_HEADER_INSNS * 4) +#define PLT_ENTRY_SIZE (PLT_ENTRY_INSNS * 4) + +#define GOT_ENTRY_SIZE RISCV_ELF_WORD_BYTES + +#define GOTPLT_HEADER_SIZE (2 * GOT_ENTRY_SIZE) + +#define sec_addr(sec) ((sec)->output_section->vma + (sec)->output_offset) + +static bfd_vma +riscv_elf_got_plt_val (bfd_vma plt_index, struct bfd_link_info *info) +{ + return sec_addr (riscv_elf_hash_table (info)->elf.sgotplt) + + GOTPLT_HEADER_SIZE + (plt_index * GOT_ENTRY_SIZE); +} + +#if ARCH_SIZE == 32 +# define MATCH_LREG MATCH_LW +#else +# define MATCH_LREG MATCH_LD +#endif + +/* Generate a PLT header. */ + +static void +riscv_make_plt_header (bfd_vma gotplt_addr, bfd_vma addr, uint32_t *entry) +{ + bfd_vma gotplt_offset_high = RISCV_PCREL_HIGH_PART (gotplt_addr, addr); + bfd_vma gotplt_offset_low = RISCV_PCREL_LOW_PART (gotplt_addr, addr); + + /* auipc t2, %hi(.got.plt) + sub t1, t1, t3 # shifted .got.plt offset + hdr size + 12 + l[w|d] t3, %lo(.got.plt)(t2) # _dl_runtime_resolve + addi t1, t1, -(hdr size + 12) # shifted .got.plt offset + addi t0, t2, %lo(.got.plt) # &.got.plt + srli t1, t1, log2(16/PTRSIZE) # .got.plt offset + l[w|d] t0, PTRSIZE(t0) # link map + jr t3 */ + + entry[0] = RISCV_UTYPE (AUIPC, X_T2, gotplt_offset_high); + entry[1] = RISCV_RTYPE (SUB, X_T1, X_T1, X_T3); + entry[2] = RISCV_ITYPE (LREG, X_T3, X_T2, gotplt_offset_low); + entry[3] = RISCV_ITYPE (ADDI, X_T1, X_T1, -(PLT_HEADER_SIZE + 12)); + entry[4] = RISCV_ITYPE (ADDI, X_T0, X_T2, gotplt_offset_low); + entry[5] = RISCV_ITYPE (SRLI, X_T1, X_T1, 4 - RISCV_ELF_LOG_WORD_BYTES); + entry[6] = RISCV_ITYPE (LREG, X_T0, X_T0, RISCV_ELF_WORD_BYTES); + entry[7] = RISCV_ITYPE (JALR, 0, X_T3, 0); +} + +/* Generate a PLT entry. */ + +static void +riscv_make_plt_entry (bfd_vma got, bfd_vma addr, uint32_t *entry) +{ + /* auipc t3, %hi(.got.plt entry) + l[w|d] t3, %lo(.got.plt entry)(t3) + jalr t1, t3 + nop */ + + entry[0] = RISCV_UTYPE (AUIPC, X_T3, RISCV_PCREL_HIGH_PART (got, addr)); + entry[1] = RISCV_ITYPE (LREG, X_T3, X_T3, RISCV_PCREL_LOW_PART(got, addr)); + entry[2] = RISCV_ITYPE (JALR, X_T1, X_T3, 0); + entry[3] = RISCV_NOP; +} + +/* Create an entry in an RISC-V ELF linker hash table. */ + +static struct bfd_hash_entry * +link_hash_newfunc (struct bfd_hash_entry *entry, + struct bfd_hash_table *table, const char *string) +{ + /* Allocate the structure if it has not already been allocated by a + subclass. */ + if (entry == NULL) + { + entry = + bfd_hash_allocate (table, + sizeof (struct riscv_elf_link_hash_entry)); + if (entry == NULL) + return entry; + } + + /* Call the allocation method of the superclass. */ + entry = _bfd_elf_link_hash_newfunc (entry, table, string); + if (entry != NULL) + { + struct riscv_elf_link_hash_entry *eh; + + eh = (struct riscv_elf_link_hash_entry *) entry; + eh->dyn_relocs = NULL; + eh->tls_type = GOT_UNKNOWN; + } + + return entry; +} + +/* Create a RISC-V ELF linker hash table. */ + +static struct bfd_link_hash_table * +riscv_elf_link_hash_table_create (bfd *abfd) +{ + struct riscv_elf_link_hash_table *ret; + bfd_size_type amt = sizeof (struct riscv_elf_link_hash_table); + + ret = (struct riscv_elf_link_hash_table *) bfd_zmalloc (amt); + if (ret == NULL) + return NULL; + + if (!_bfd_elf_link_hash_table_init (&ret->elf, abfd, link_hash_newfunc, + sizeof (struct riscv_elf_link_hash_entry), + RISCV_ELF_DATA)) + { + free (ret); + return NULL; + } + + return &ret->elf.root; +} + +/* Create the .got section. */ + +static bfd_boolean +riscv_elf_create_got_section (bfd *abfd, struct bfd_link_info *info) +{ + flagword flags; + asection *s, *s_got; + struct elf_link_hash_entry *h; + const struct elf_backend_data *bed = get_elf_backend_data (abfd); + struct elf_link_hash_table *htab = elf_hash_table (info); + + /* This function may be called more than once. */ + s = bfd_get_linker_section (abfd, ".got"); + if (s != NULL) + return TRUE; + + flags = bed->dynamic_sec_flags; + + s = bfd_make_section_anyway_with_flags (abfd, + (bed->rela_plts_and_copies_p + ? ".rela.got" : ".rel.got"), + (bed->dynamic_sec_flags + | SEC_READONLY)); + if (s == NULL + || ! bfd_set_section_alignment (abfd, s, bed->s->log_file_align)) + return FALSE; + htab->srelgot = s; + + s = s_got = bfd_make_section_anyway_with_flags (abfd, ".got", flags); + if (s == NULL + || !bfd_set_section_alignment (abfd, s, bed->s->log_file_align)) + return FALSE; + htab->sgot = s; + + /* The first bit of the global offset table is the header. */ + s->size += bed->got_header_size; + + if (bed->want_got_plt) + { + s = bfd_make_section_anyway_with_flags (abfd, ".got.plt", flags); + if (s == NULL + || !bfd_set_section_alignment (abfd, s, + bed->s->log_file_align)) + return FALSE; + htab->sgotplt = s; + + /* Reserve room for the header. */ + s->size += GOTPLT_HEADER_SIZE; + } + + if (bed->want_got_sym) + { + /* Define the symbol _GLOBAL_OFFSET_TABLE_ at the start of the .got + section. We don't do this in the linker script because we don't want + to define the symbol if we are not creating a global offset + table. */ + h = _bfd_elf_define_linkage_sym (abfd, info, s_got, + "_GLOBAL_OFFSET_TABLE_"); + elf_hash_table (info)->hgot = h; + if (h == NULL) + return FALSE; + } + + return TRUE; +} + +/* Create .plt, .rela.plt, .got, .got.plt, .rela.got, .dynbss, and + .rela.bss sections in DYNOBJ, and set up shortcuts to them in our + hash table. */ + +static bfd_boolean +riscv_elf_create_dynamic_sections (bfd *dynobj, + struct bfd_link_info *info) +{ + struct riscv_elf_link_hash_table *htab; + + htab = riscv_elf_hash_table (info); + BFD_ASSERT (htab != NULL); + + if (!riscv_elf_create_got_section (dynobj, info)) + return FALSE; + + if (!_bfd_elf_create_dynamic_sections (dynobj, info)) + return FALSE; + + htab->sdynbss = bfd_get_linker_section (dynobj, ".dynbss"); + if (!bfd_link_pic (info)) + { + htab->srelbss = bfd_get_linker_section (dynobj, ".rela.bss"); + htab->sdyntdata = + bfd_make_section_anyway_with_flags (dynobj, ".tdata.dyn", + SEC_ALLOC | SEC_THREAD_LOCAL); + } + + if (!htab->elf.splt || !htab->elf.srelplt || !htab->sdynbss + || (!bfd_link_pic (info) && (!htab->srelbss || !htab->sdyntdata))) + abort (); + + return TRUE; +} + +/* Copy the extra info we tack onto an elf_link_hash_entry. */ + +static void +riscv_elf_copy_indirect_symbol (struct bfd_link_info *info, + struct elf_link_hash_entry *dir, + struct elf_link_hash_entry *ind) +{ + struct riscv_elf_link_hash_entry *edir, *eind; + + edir = (struct riscv_elf_link_hash_entry *) dir; + eind = (struct riscv_elf_link_hash_entry *) ind; + + if (eind->dyn_relocs != NULL) + { + if (edir->dyn_relocs != NULL) + { + struct riscv_elf_dyn_relocs **pp; + struct riscv_elf_dyn_relocs *p; + + /* Add reloc counts against the indirect sym to the direct sym + list. Merge any entries against the same section. */ + for (pp = &eind->dyn_relocs; (p = *pp) != NULL; ) + { + struct riscv_elf_dyn_relocs *q; + + for (q = edir->dyn_relocs; q != NULL; q = q->next) + if (q->sec == p->sec) + { + q->pc_count += p->pc_count; + q->count += p->count; + *pp = p->next; + break; + } + if (q == NULL) + pp = &p->next; + } + *pp = edir->dyn_relocs; + } + + edir->dyn_relocs = eind->dyn_relocs; + eind->dyn_relocs = NULL; + } + + if (ind->root.type == bfd_link_hash_indirect + && dir->got.refcount <= 0) + { + edir->tls_type = eind->tls_type; + eind->tls_type = GOT_UNKNOWN; + } + _bfd_elf_link_hash_copy_indirect (info, dir, ind); +} + +static bfd_boolean +riscv_elf_record_tls_type (bfd *abfd, struct elf_link_hash_entry *h, + unsigned long symndx, char tls_type) +{ + char *new_tls_type = &_bfd_riscv_elf_tls_type (abfd, h, symndx); + + *new_tls_type |= tls_type; + if ((*new_tls_type & GOT_NORMAL) && (*new_tls_type & ~GOT_NORMAL)) + { + (*_bfd_error_handler) + (_("%B: `%s' accessed both as normal and thread local symbol"), + abfd, h ? h->root.root.string : ""); + return FALSE; + } + return TRUE; +} + +static bfd_boolean +riscv_elf_record_got_reference (bfd *abfd, struct bfd_link_info *info, + struct elf_link_hash_entry *h, long symndx) +{ + struct riscv_elf_link_hash_table *htab = riscv_elf_hash_table (info); + Elf_Internal_Shdr *symtab_hdr = &elf_tdata (abfd)->symtab_hdr; + + if (htab->elf.sgot == NULL) + { + if (!riscv_elf_create_got_section (htab->elf.dynobj, info)) + return FALSE; + } + + if (h != NULL) + { + h->got.refcount += 1; + return TRUE; + } + + /* This is a global offset table entry for a local symbol. */ + if (elf_local_got_refcounts (abfd) == NULL) + { + bfd_size_type size = symtab_hdr->sh_info * (sizeof (bfd_vma) + 1); + if (!(elf_local_got_refcounts (abfd) = bfd_zalloc (abfd, size))) + return FALSE; + _bfd_riscv_elf_local_got_tls_type (abfd) + = (char *) (elf_local_got_refcounts (abfd) + symtab_hdr->sh_info); + } + elf_local_got_refcounts (abfd) [symndx] += 1; + + return TRUE; +} + +static bfd_boolean +bad_static_reloc (bfd *abfd, unsigned r_type, struct elf_link_hash_entry *h) +{ + (*_bfd_error_handler) + (_("%B: relocation %s against `%s' can not be used when making a shared " + "object; recompile with -fPIC"), + abfd, riscv_elf_rtype_to_howto (r_type)->name, + h != NULL ? h->root.root.string : "a local symbol"); + bfd_set_error (bfd_error_bad_value); + return FALSE; +} +/* Look through the relocs for a section during the first phase, and + allocate space in the global offset table or procedure linkage + table. */ + +static bfd_boolean +riscv_elf_check_relocs (bfd *abfd, struct bfd_link_info *info, + asection *sec, const Elf_Internal_Rela *relocs) +{ + struct riscv_elf_link_hash_table *htab; + Elf_Internal_Shdr *symtab_hdr; + struct elf_link_hash_entry **sym_hashes; + const Elf_Internal_Rela *rel; + asection *sreloc = NULL; + + if (bfd_link_relocatable (info)) + return TRUE; + + htab = riscv_elf_hash_table (info); + symtab_hdr = &elf_tdata (abfd)->symtab_hdr; + sym_hashes = elf_sym_hashes (abfd); + + if (htab->elf.dynobj == NULL) + htab->elf.dynobj = abfd; + + for (rel = relocs; rel < relocs + sec->reloc_count; rel++) + { + unsigned int r_type; + unsigned long r_symndx; + struct elf_link_hash_entry *h; + + r_symndx = ELFNN_R_SYM (rel->r_info); + r_type = ELFNN_R_TYPE (rel->r_info); + + if (r_symndx >= NUM_SHDR_ENTRIES (symtab_hdr)) + { + (*_bfd_error_handler) (_("%B: bad symbol index: %d"), + abfd, r_symndx); + return FALSE; + } + + if (r_symndx < symtab_hdr->sh_info) + h = NULL; + else + { + h = sym_hashes[r_symndx - symtab_hdr->sh_info]; + while (h->root.type == bfd_link_hash_indirect + || h->root.type == bfd_link_hash_warning) + h = (struct elf_link_hash_entry *) h->root.u.i.link; + + /* PR15323, ref flags aren't set for references in the same + object. */ + h->root.non_ir_ref = 1; + } + + switch (r_type) + { + case R_RISCV_TLS_GD_HI20: + if (!riscv_elf_record_got_reference (abfd, info, h, r_symndx) + || !riscv_elf_record_tls_type (abfd, h, r_symndx, GOT_TLS_GD)) + return FALSE; + break; + + case R_RISCV_TLS_GOT_HI20: + if (bfd_link_pic (info)) + info->flags |= DF_STATIC_TLS; + if (!riscv_elf_record_got_reference (abfd, info, h, r_symndx) + || !riscv_elf_record_tls_type (abfd, h, r_symndx, GOT_TLS_IE)) + return FALSE; + break; + + case R_RISCV_GOT_HI20: + if (!riscv_elf_record_got_reference (abfd, info, h, r_symndx) + || !riscv_elf_record_tls_type (abfd, h, r_symndx, GOT_NORMAL)) + return FALSE; + break; + + case R_RISCV_CALL_PLT: + /* This symbol requires a procedure linkage table entry. We + actually build the entry in adjust_dynamic_symbol, + because this might be a case of linking PIC code without + linking in any dynamic objects, in which case we don't + need to generate a procedure linkage table after all. */ + + if (h != NULL) + { + h->needs_plt = 1; + h->plt.refcount += 1; + } + break; + + case R_RISCV_CALL: + case R_RISCV_JAL: + case R_RISCV_BRANCH: + case R_RISCV_RVC_BRANCH: + case R_RISCV_RVC_JUMP: + case R_RISCV_PCREL_HI20: + /* In shared libraries, these relocs are known to bind locally. */ + if (bfd_link_pic (info)) + break; + goto static_reloc; + + case R_RISCV_TPREL_HI20: + if (!bfd_link_executable (info)) + return bad_static_reloc (abfd, r_type, h); + if (h != NULL) + riscv_elf_record_tls_type (abfd, h, r_symndx, GOT_TLS_LE); + goto static_reloc; + + case R_RISCV_HI20: + if (bfd_link_pic (info)) + return bad_static_reloc (abfd, r_type, h); + /* Fall through. */ + + case R_RISCV_COPY: + case R_RISCV_JUMP_SLOT: + case R_RISCV_RELATIVE: + case R_RISCV_64: + case R_RISCV_32: + /* Fall through. */ + + static_reloc: + /* This reloc might not bind locally. */ + if (h != NULL) + h->non_got_ref = 1; + + if (h != NULL && !bfd_link_pic (info)) + { + /* We may need a .plt entry if the function this reloc + refers to is in a shared lib. */ + h->plt.refcount += 1; + } + + /* If we are creating a shared library, and this is a reloc + against a global symbol, or a non PC relative reloc + against a local symbol, then we need to copy the reloc + into the shared library. However, if we are linking with + -Bsymbolic, we do not need to copy a reloc against a + global symbol which is defined in an object we are + including in the link (i.e., DEF_REGULAR is set). At + this point we have not seen all the input files, so it is + possible that DEF_REGULAR is not set now but will be set + later (it is never cleared). In case of a weak definition, + DEF_REGULAR may be cleared later by a strong definition in + a shared library. We account for that possibility below by + storing information in the relocs_copied field of the hash + table entry. A similar situation occurs when creating + shared libraries and symbol visibility changes render the + symbol local. + + If on the other hand, we are creating an executable, we + may need to keep relocations for symbols satisfied by a + dynamic library if we manage to avoid copy relocs for the + symbol. */ + if ((bfd_link_pic (info) + && (sec->flags & SEC_ALLOC) != 0 + && (! riscv_elf_rtype_to_howto (r_type)->pc_relative + || (h != NULL + && (! info->symbolic + || h->root.type == bfd_link_hash_defweak + || !h->def_regular)))) + || (!bfd_link_pic (info) + && (sec->flags & SEC_ALLOC) != 0 + && h != NULL + && (h->root.type == bfd_link_hash_defweak + || !h->def_regular))) + { + struct riscv_elf_dyn_relocs *p; + struct riscv_elf_dyn_relocs **head; + + /* When creating a shared object, we must copy these + relocs into the output file. We create a reloc + section in dynobj and make room for the reloc. */ + if (sreloc == NULL) + { + sreloc = _bfd_elf_make_dynamic_reloc_section + (sec, htab->elf.dynobj, RISCV_ELF_LOG_WORD_BYTES, + abfd, /*rela?*/ TRUE); + + if (sreloc == NULL) + return FALSE; + } + + /* If this is a global symbol, we count the number of + relocations we need for this symbol. */ + if (h != NULL) + head = &((struct riscv_elf_link_hash_entry *) h)->dyn_relocs; + else + { + /* Track dynamic relocs needed for local syms too. + We really need local syms available to do this + easily. Oh well. */ + + asection *s; + void *vpp; + Elf_Internal_Sym *isym; + + isym = bfd_sym_from_r_symndx (&htab->sym_cache, + abfd, r_symndx); + if (isym == NULL) + return FALSE; + + s = bfd_section_from_elf_index (abfd, isym->st_shndx); + if (s == NULL) + s = sec; + + vpp = &elf_section_data (s)->local_dynrel; + head = (struct riscv_elf_dyn_relocs **) vpp; + } + + p = *head; + if (p == NULL || p->sec != sec) + { + bfd_size_type amt = sizeof *p; + p = ((struct riscv_elf_dyn_relocs *) + bfd_alloc (htab->elf.dynobj, amt)); + if (p == NULL) + return FALSE; + p->next = *head; + *head = p; + p->sec = sec; + p->count = 0; + p->pc_count = 0; + } + + p->count += 1; + p->pc_count += riscv_elf_rtype_to_howto (r_type)->pc_relative; + } + + break; + + case R_RISCV_GNU_VTINHERIT: + if (!bfd_elf_gc_record_vtinherit (abfd, sec, h, rel->r_offset)) + return FALSE; + break; + + case R_RISCV_GNU_VTENTRY: + if (!bfd_elf_gc_record_vtentry (abfd, sec, h, rel->r_addend)) + return FALSE; + break; + + default: + break; + } + } + + return TRUE; +} + +static asection * +riscv_elf_gc_mark_hook (asection *sec, + struct bfd_link_info *info, + Elf_Internal_Rela *rel, + struct elf_link_hash_entry *h, + Elf_Internal_Sym *sym) +{ + if (h != NULL) + switch (ELFNN_R_TYPE (rel->r_info)) + { + case R_RISCV_GNU_VTINHERIT: + case R_RISCV_GNU_VTENTRY: + return NULL; + } + + return _bfd_elf_gc_mark_hook (sec, info, rel, h, sym); +} + +/* Update the got entry reference counts for the section being removed. */ + +static bfd_boolean +riscv_elf_gc_sweep_hook (bfd *abfd, + struct bfd_link_info *info, + asection *sec, + const Elf_Internal_Rela *relocs) +{ + const Elf_Internal_Rela *rel, *relend; + Elf_Internal_Shdr *symtab_hdr = &elf_symtab_hdr (abfd); + struct elf_link_hash_entry **sym_hashes = elf_sym_hashes (abfd); + bfd_signed_vma *local_got_refcounts = elf_local_got_refcounts (abfd); + + if (bfd_link_relocatable (info)) + return TRUE; + + elf_section_data (sec)->local_dynrel = NULL; + + for (rel = relocs, relend = relocs + sec->reloc_count; rel < relend; rel++) + { + unsigned long r_symndx; + struct elf_link_hash_entry *h = NULL; + + r_symndx = ELFNN_R_SYM (rel->r_info); + if (r_symndx >= symtab_hdr->sh_info) + { + struct riscv_elf_link_hash_entry *eh; + struct riscv_elf_dyn_relocs **pp; + struct riscv_elf_dyn_relocs *p; + + h = sym_hashes[r_symndx - symtab_hdr->sh_info]; + while (h->root.type == bfd_link_hash_indirect + || h->root.type == bfd_link_hash_warning) + h = (struct elf_link_hash_entry *) h->root.u.i.link; + eh = (struct riscv_elf_link_hash_entry *) h; + for (pp = &eh->dyn_relocs; (p = *pp) != NULL; pp = &p->next) + if (p->sec == sec) + { + /* Everything must go for SEC. */ + *pp = p->next; + break; + } + } + + switch (ELFNN_R_TYPE (rel->r_info)) + { + case R_RISCV_GOT_HI20: + case R_RISCV_TLS_GOT_HI20: + case R_RISCV_TLS_GD_HI20: + if (h != NULL) + { + if (h->got.refcount > 0) + h->got.refcount--; + } + else + { + if (local_got_refcounts && + local_got_refcounts[r_symndx] > 0) + local_got_refcounts[r_symndx]--; + } + break; + + case R_RISCV_HI20: + case R_RISCV_PCREL_HI20: + case R_RISCV_COPY: + case R_RISCV_JUMP_SLOT: + case R_RISCV_RELATIVE: + case R_RISCV_64: + case R_RISCV_32: + case R_RISCV_BRANCH: + case R_RISCV_CALL: + case R_RISCV_JAL: + case R_RISCV_RVC_BRANCH: + case R_RISCV_RVC_JUMP: + if (bfd_link_pic (info)) + break; + /* Fall through. */ + + case R_RISCV_CALL_PLT: + if (h != NULL) + { + if (h->plt.refcount > 0) + h->plt.refcount--; + } + break; + + default: + break; + } + } + + return TRUE; +} + +/* Adjust a symbol defined by a dynamic object and referenced by a + regular object. The current definition is in some section of the + dynamic object, but we're not including those sections. We have to + change the definition to something the rest of the link can + understand. */ + +static bfd_boolean +riscv_elf_adjust_dynamic_symbol (struct bfd_link_info *info, + struct elf_link_hash_entry *h) +{ + struct riscv_elf_link_hash_table *htab; + struct riscv_elf_link_hash_entry * eh; + struct riscv_elf_dyn_relocs *p; + bfd *dynobj; + asection *s; + + htab = riscv_elf_hash_table (info); + BFD_ASSERT (htab != NULL); + + dynobj = htab->elf.dynobj; + + /* Make sure we know what is going on here. */ + BFD_ASSERT (dynobj != NULL + && (h->needs_plt + || h->type == STT_GNU_IFUNC + || h->u.weakdef != NULL + || (h->def_dynamic + && h->ref_regular + && !h->def_regular))); + + /* If this is a function, put it in the procedure linkage table. We + will fill in the contents of the procedure linkage table later + (although we could actually do it here). */ + if (h->type == STT_FUNC || h->type == STT_GNU_IFUNC || h->needs_plt) + { + if (h->plt.refcount <= 0 + || SYMBOL_CALLS_LOCAL (info, h) + || (ELF_ST_VISIBILITY (h->other) != STV_DEFAULT + && h->root.type == bfd_link_hash_undefweak)) + { + /* This case can occur if we saw a R_RISCV_CALL_PLT reloc in an + input file, but the symbol was never referred to by a dynamic + object, or if all references were garbage collected. In such + a case, we don't actually need to build a PLT entry. */ + h->plt.offset = (bfd_vma) -1; + h->needs_plt = 0; + } + + return TRUE; + } + else + h->plt.offset = (bfd_vma) -1; + + /* If this is a weak symbol, and there is a real definition, the + processor independent code will have arranged for us to see the + real definition first, and we can just use the same value. */ + if (h->u.weakdef != NULL) + { + BFD_ASSERT (h->u.weakdef->root.type == bfd_link_hash_defined + || h->u.weakdef->root.type == bfd_link_hash_defweak); + h->root.u.def.section = h->u.weakdef->root.u.def.section; + h->root.u.def.value = h->u.weakdef->root.u.def.value; + return TRUE; + } + + /* This is a reference to a symbol defined by a dynamic object which + is not a function. */ + + /* If we are creating a shared library, we must presume that the + only references to the symbol are via the global offset table. + For such cases we need not do anything here; the relocations will + be handled correctly by relocate_section. */ + if (bfd_link_pic (info)) + return TRUE; + + /* If there are no references to this symbol that do not use the + GOT, we don't need to generate a copy reloc. */ + if (!h->non_got_ref) + return TRUE; + + /* If -z nocopyreloc was given, we won't generate them either. */ + if (info->nocopyreloc) + { + h->non_got_ref = 0; + return TRUE; + } + + eh = (struct riscv_elf_link_hash_entry *) h; + for (p = eh->dyn_relocs; p != NULL; p = p->next) + { + s = p->sec->output_section; + if (s != NULL && (s->flags & SEC_READONLY) != 0) + break; + } + + /* If we didn't find any dynamic relocs in read-only sections, then + we'll be keeping the dynamic relocs and avoiding the copy reloc. */ + if (p == NULL) + { + h->non_got_ref = 0; + return TRUE; + } + + /* We must allocate the symbol in our .dynbss section, which will + become part of the .bss section of the executable. There will be + an entry for this symbol in the .dynsym section. The dynamic + object will contain position independent code, so all references + from the dynamic object to this symbol will go through the global + offset table. The dynamic linker will use the .dynsym entry to + determine the address it must put in the global offset table, so + both the dynamic object and the regular object will refer to the + same memory location for the variable. */ + + /* We must generate a R_RISCV_COPY reloc to tell the dynamic linker + to copy the initial value out of the dynamic object and into the + runtime process image. We need to remember the offset into the + .rel.bss section we are going to use. */ + if ((h->root.u.def.section->flags & SEC_ALLOC) != 0 && h->size != 0) + { + htab->srelbss->size += sizeof (ElfNN_External_Rela); + h->needs_copy = 1; + } + + if (eh->tls_type & ~GOT_NORMAL) + return _bfd_elf_adjust_dynamic_copy (info, h, htab->sdyntdata); + + return _bfd_elf_adjust_dynamic_copy (info, h, htab->sdynbss); +} + +/* Allocate space in .plt, .got and associated reloc sections for + dynamic relocs. */ + +static bfd_boolean +allocate_dynrelocs (struct elf_link_hash_entry *h, void *inf) +{ + struct bfd_link_info *info; + struct riscv_elf_link_hash_table *htab; + struct riscv_elf_link_hash_entry *eh; + struct riscv_elf_dyn_relocs *p; + + if (h->root.type == bfd_link_hash_indirect) + return TRUE; + + info = (struct bfd_link_info *) inf; + htab = riscv_elf_hash_table (info); + BFD_ASSERT (htab != NULL); + + if (htab->elf.dynamic_sections_created + && h->plt.refcount > 0) + { + /* Make sure this symbol is output as a dynamic symbol. + Undefined weak syms won't yet be marked as dynamic. */ + if (h->dynindx == -1 + && !h->forced_local) + { + if (! bfd_elf_link_record_dynamic_symbol (info, h)) + return FALSE; + } + + if (WILL_CALL_FINISH_DYNAMIC_SYMBOL (1, bfd_link_pic (info), h)) + { + asection *s = htab->elf.splt; + + if (s->size == 0) + s->size = PLT_HEADER_SIZE; + + h->plt.offset = s->size; + + /* Make room for this entry. */ + s->size += PLT_ENTRY_SIZE; + + /* We also need to make an entry in the .got.plt section. */ + htab->elf.sgotplt->size += GOT_ENTRY_SIZE; + + /* We also need to make an entry in the .rela.plt section. */ + htab->elf.srelplt->size += sizeof (ElfNN_External_Rela); + + /* If this symbol is not defined in a regular file, and we are + not generating a shared library, then set the symbol to this + location in the .plt. This is required to make function + pointers compare as equal between the normal executable and + the shared library. */ + if (! bfd_link_pic (info) + && !h->def_regular) + { + h->root.u.def.section = s; + h->root.u.def.value = h->plt.offset; + } + } + else + { + h->plt.offset = (bfd_vma) -1; + h->needs_plt = 0; + } + } + else + { + h->plt.offset = (bfd_vma) -1; + h->needs_plt = 0; + } + + if (h->got.refcount > 0) + { + asection *s; + bfd_boolean dyn; + int tls_type = riscv_elf_hash_entry (h)->tls_type; + + /* Make sure this symbol is output as a dynamic symbol. + Undefined weak syms won't yet be marked as dynamic. */ + if (h->dynindx == -1 + && !h->forced_local) + { + if (! bfd_elf_link_record_dynamic_symbol (info, h)) + return FALSE; + } + + s = htab->elf.sgot; + h->got.offset = s->size; + dyn = htab->elf.dynamic_sections_created; + if (tls_type & (GOT_TLS_GD | GOT_TLS_IE)) + { + /* TLS_GD needs two dynamic relocs and two GOT slots. */ + if (tls_type & GOT_TLS_GD) + { + s->size += 2 * RISCV_ELF_WORD_BYTES; + htab->elf.srelgot->size += 2 * sizeof (ElfNN_External_Rela); + } + + /* TLS_IE needs one dynamic reloc and one GOT slot. */ + if (tls_type & GOT_TLS_IE) + { + s->size += RISCV_ELF_WORD_BYTES; + htab->elf.srelgot->size += sizeof (ElfNN_External_Rela); + } + } + else + { + s->size += RISCV_ELF_WORD_BYTES; + if (WILL_CALL_FINISH_DYNAMIC_SYMBOL (dyn, bfd_link_pic (info), h)) + htab->elf.srelgot->size += sizeof (ElfNN_External_Rela); + } + } + else + h->got.offset = (bfd_vma) -1; + + eh = (struct riscv_elf_link_hash_entry *) h; + if (eh->dyn_relocs == NULL) + return TRUE; + + /* In the shared -Bsymbolic case, discard space allocated for + dynamic pc-relative relocs against symbols which turn out to be + defined in regular objects. For the normal shared case, discard + space for pc-relative relocs that have become local due to symbol + visibility changes. */ + + if (bfd_link_pic (info)) + { + if (SYMBOL_CALLS_LOCAL (info, h)) + { + struct riscv_elf_dyn_relocs **pp; + + for (pp = &eh->dyn_relocs; (p = *pp) != NULL; ) + { + p->count -= p->pc_count; + p->pc_count = 0; + if (p->count == 0) + *pp = p->next; + else + pp = &p->next; + } + } + + /* Also discard relocs on undefined weak syms with non-default + visibility. */ + if (eh->dyn_relocs != NULL + && h->root.type == bfd_link_hash_undefweak) + { + if (ELF_ST_VISIBILITY (h->other) != STV_DEFAULT) + eh->dyn_relocs = NULL; + + /* Make sure undefined weak symbols are output as a dynamic + symbol in PIEs. */ + else if (h->dynindx == -1 + && !h->forced_local) + { + if (! bfd_elf_link_record_dynamic_symbol (info, h)) + return FALSE; + } + } + } + else + { + /* For the non-shared case, discard space for relocs against + symbols which turn out to need copy relocs or are not + dynamic. */ + + if (!h->non_got_ref + && ((h->def_dynamic + && !h->def_regular) + || (htab->elf.dynamic_sections_created + && (h->root.type == bfd_link_hash_undefweak + || h->root.type == bfd_link_hash_undefined)))) + { + /* Make sure this symbol is output as a dynamic symbol. + Undefined weak syms won't yet be marked as dynamic. */ + if (h->dynindx == -1 + && !h->forced_local) + { + if (! bfd_elf_link_record_dynamic_symbol (info, h)) + return FALSE; + } + + /* If that succeeded, we know we'll be keeping all the + relocs. */ + if (h->dynindx != -1) + goto keep; + } + + eh->dyn_relocs = NULL; + + keep: ; + } + + /* Finally, allocate space. */ + for (p = eh->dyn_relocs; p != NULL; p = p->next) + { + asection *sreloc = elf_section_data (p->sec)->sreloc; + sreloc->size += p->count * sizeof (ElfNN_External_Rela); + } + + return TRUE; +} + +/* Find any dynamic relocs that apply to read-only sections. */ + +static bfd_boolean +readonly_dynrelocs (struct elf_link_hash_entry *h, void *inf) +{ + struct riscv_elf_link_hash_entry *eh; + struct riscv_elf_dyn_relocs *p; + + eh = (struct riscv_elf_link_hash_entry *) h; + for (p = eh->dyn_relocs; p != NULL; p = p->next) + { + asection *s = p->sec->output_section; + + if (s != NULL && (s->flags & SEC_READONLY) != 0) + { + ((struct bfd_link_info *) inf)->flags |= DF_TEXTREL; + return FALSE; + } + } + return TRUE; +} + +static bfd_boolean +riscv_elf_size_dynamic_sections (bfd *output_bfd, struct bfd_link_info *info) +{ + struct riscv_elf_link_hash_table *htab; + bfd *dynobj; + asection *s; + bfd *ibfd; + + htab = riscv_elf_hash_table (info); + BFD_ASSERT (htab != NULL); + dynobj = htab->elf.dynobj; + BFD_ASSERT (dynobj != NULL); + + if (elf_hash_table (info)->dynamic_sections_created) + { + /* Set the contents of the .interp section to the interpreter. */ + if (bfd_link_executable (info) && !info->nointerp) + { + s = bfd_get_linker_section (dynobj, ".interp"); + BFD_ASSERT (s != NULL); + s->size = strlen (ELFNN_DYNAMIC_INTERPRETER) + 1; + s->contents = (unsigned char *) ELFNN_DYNAMIC_INTERPRETER; + } + } + + /* Set up .got offsets for local syms, and space for local dynamic + relocs. */ + for (ibfd = info->input_bfds; ibfd != NULL; ibfd = ibfd->link.next) + { + bfd_signed_vma *local_got; + bfd_signed_vma *end_local_got; + char *local_tls_type; + bfd_size_type locsymcount; + Elf_Internal_Shdr *symtab_hdr; + asection *srel; + + if (! is_riscv_elf (ibfd)) + continue; + + for (s = ibfd->sections; s != NULL; s = s->next) + { + struct riscv_elf_dyn_relocs *p; + + for (p = elf_section_data (s)->local_dynrel; p != NULL; p = p->next) + { + if (!bfd_is_abs_section (p->sec) + && bfd_is_abs_section (p->sec->output_section)) + { + /* Input section has been discarded, either because + it is a copy of a linkonce section or due to + linker script /DISCARD/, so we'll be discarding + the relocs too. */ + } + else if (p->count != 0) + { + srel = elf_section_data (p->sec)->sreloc; + srel->size += p->count * sizeof (ElfNN_External_Rela); + if ((p->sec->output_section->flags & SEC_READONLY) != 0) + info->flags |= DF_TEXTREL; + } + } + } + + local_got = elf_local_got_refcounts (ibfd); + if (!local_got) + continue; + + symtab_hdr = &elf_symtab_hdr (ibfd); + locsymcount = symtab_hdr->sh_info; + end_local_got = local_got + locsymcount; + local_tls_type = _bfd_riscv_elf_local_got_tls_type (ibfd); + s = htab->elf.sgot; + srel = htab->elf.srelgot; + for (; local_got < end_local_got; ++local_got, ++local_tls_type) + { + if (*local_got > 0) + { + *local_got = s->size; + s->size += RISCV_ELF_WORD_BYTES; + if (*local_tls_type & GOT_TLS_GD) + s->size += RISCV_ELF_WORD_BYTES; + if (bfd_link_pic (info) + || (*local_tls_type & (GOT_TLS_GD | GOT_TLS_IE))) + srel->size += sizeof (ElfNN_External_Rela); + } + else + *local_got = (bfd_vma) -1; + } + } + + /* Allocate global sym .plt and .got entries, and space for global + sym dynamic relocs. */ + elf_link_hash_traverse (&htab->elf, allocate_dynrelocs, info); + + if (htab->elf.sgotplt) + { + struct elf_link_hash_entry *got; + got = elf_link_hash_lookup (elf_hash_table (info), + "_GLOBAL_OFFSET_TABLE_", + FALSE, FALSE, FALSE); + + /* Don't allocate .got.plt section if there are no GOT nor PLT + entries and there is no refeence to _GLOBAL_OFFSET_TABLE_. */ + if ((got == NULL + || !got->ref_regular_nonweak) + && (htab->elf.sgotplt->size == GOTPLT_HEADER_SIZE) + && (htab->elf.splt == NULL + || htab->elf.splt->size == 0) + && (htab->elf.sgot == NULL + || (htab->elf.sgot->size + == get_elf_backend_data (output_bfd)->got_header_size))) + htab->elf.sgotplt->size = 0; + } + + /* The check_relocs and adjust_dynamic_symbol entry points have + determined the sizes of the various dynamic sections. Allocate + memory for them. */ + for (s = dynobj->sections; s != NULL; s = s->next) + { + if ((s->flags & SEC_LINKER_CREATED) == 0) + continue; + + if (s == htab->elf.splt + || s == htab->elf.sgot + || s == htab->elf.sgotplt + || s == htab->sdynbss) + { + /* Strip this section if we don't need it; see the + comment below. */ + } + else if (strncmp (s->name, ".rela", 5) == 0) + { + if (s->size != 0) + { + /* We use the reloc_count field as a counter if we need + to copy relocs into the output file. */ + s->reloc_count = 0; + } + } + else + { + /* It's not one of our sections. */ + continue; + } + + if (s->size == 0) + { + /* If we don't need this section, strip it from the + output file. This is mostly to handle .rela.bss and + .rela.plt. We must create both sections in + create_dynamic_sections, because they must be created + before the linker maps input sections to output + sections. The linker does that before + adjust_dynamic_symbol is called, and it is that + function which decides whether anything needs to go + into these sections. */ + s->flags |= SEC_EXCLUDE; + continue; + } + + if ((s->flags & SEC_HAS_CONTENTS) == 0) + continue; + + /* Allocate memory for the section contents. Zero the memory + for the benefit of .rela.plt, which has 4 unused entries + at the beginning, and we don't want garbage. */ + s->contents = (bfd_byte *) bfd_zalloc (dynobj, s->size); + if (s->contents == NULL) + return FALSE; + } + + if (elf_hash_table (info)->dynamic_sections_created) + { + /* Add some entries to the .dynamic section. We fill in the + values later, in riscv_elf_finish_dynamic_sections, but we + must add the entries now so that we get the correct size for + the .dynamic section. The DT_DEBUG entry is filled in by the + dynamic linker and used by the debugger. */ +#define add_dynamic_entry(TAG, VAL) \ + _bfd_elf_add_dynamic_entry (info, TAG, VAL) + + if (bfd_link_executable (info)) + { + if (!add_dynamic_entry (DT_DEBUG, 0)) + return FALSE; + } + + if (htab->elf.srelplt->size != 0) + { + if (!add_dynamic_entry (DT_PLTGOT, 0) + || !add_dynamic_entry (DT_PLTRELSZ, 0) + || !add_dynamic_entry (DT_PLTREL, DT_RELA) + || !add_dynamic_entry (DT_JMPREL, 0)) + return FALSE; + } + + if (!add_dynamic_entry (DT_RELA, 0) + || !add_dynamic_entry (DT_RELASZ, 0) + || !add_dynamic_entry (DT_RELAENT, sizeof (ElfNN_External_Rela))) + return FALSE; + + /* If any dynamic relocs apply to a read-only section, + then we need a DT_TEXTREL entry. */ + if ((info->flags & DF_TEXTREL) == 0) + elf_link_hash_traverse (&htab->elf, readonly_dynrelocs, info); + + if (info->flags & DF_TEXTREL) + { + if (!add_dynamic_entry (DT_TEXTREL, 0)) + return FALSE; + } + } +#undef add_dynamic_entry + + return TRUE; +} + +#define TP_OFFSET 0 +#define DTP_OFFSET 0x800 + +/* Return the relocation value for a TLS dtp-relative reloc. */ + +static bfd_vma +dtpoff (struct bfd_link_info *info, bfd_vma address) +{ + /* If tls_sec is NULL, we should have signalled an error already. */ + if (elf_hash_table (info)->tls_sec == NULL) + return 0; + return address - elf_hash_table (info)->tls_sec->vma - DTP_OFFSET; +} + +/* Return the relocation value for a static TLS tp-relative relocation. */ + +static bfd_vma +tpoff (struct bfd_link_info *info, bfd_vma address) +{ + /* If tls_sec is NULL, we should have signalled an error already. */ + if (elf_hash_table (info)->tls_sec == NULL) + return 0; + return address - elf_hash_table (info)->tls_sec->vma - TP_OFFSET; +} + +/* Return the global pointer's value, or 0 if it is not in use. */ + +static bfd_vma +riscv_global_pointer_value (struct bfd_link_info *info) +{ + struct bfd_link_hash_entry *h; + + h = bfd_link_hash_lookup (info->hash, "_gp", FALSE, FALSE, TRUE); + if (h == NULL || h->type != bfd_link_hash_defined) + return 0; + + return h->u.def.value + sec_addr (h->u.def.section); +} + +/* Emplace a static relocation. */ + +static bfd_reloc_status_type +perform_relocation (const reloc_howto_type *howto, + const Elf_Internal_Rela *rel, + bfd_vma value, + asection *input_section, + bfd *input_bfd, + bfd_byte *contents) +{ + if (howto->pc_relative) + value -= sec_addr (input_section) + rel->r_offset; + value += rel->r_addend; + + switch (ELFNN_R_TYPE (rel->r_info)) + { + case R_RISCV_HI20: + case R_RISCV_TPREL_HI20: + case R_RISCV_PCREL_HI20: + case R_RISCV_GOT_HI20: + case R_RISCV_TLS_GOT_HI20: + case R_RISCV_TLS_GD_HI20: + if (ARCH_SIZE > 32 && !VALID_UTYPE_IMM (RISCV_CONST_HIGH_PART (value))) + return bfd_reloc_overflow; + value = ENCODE_UTYPE_IMM (RISCV_CONST_HIGH_PART (value)); + break; + + case R_RISCV_LO12_I: + case R_RISCV_GPREL_I: + case R_RISCV_TPREL_LO12_I: + case R_RISCV_PCREL_LO12_I: + value = ENCODE_ITYPE_IMM (value); + break; + + case R_RISCV_LO12_S: + case R_RISCV_GPREL_S: + case R_RISCV_TPREL_LO12_S: + case R_RISCV_PCREL_LO12_S: + value = ENCODE_STYPE_IMM (value); + break; + + case R_RISCV_CALL: + case R_RISCV_CALL_PLT: + if (ARCH_SIZE > 32 && !VALID_UTYPE_IMM (RISCV_CONST_HIGH_PART (value))) + return bfd_reloc_overflow; + value = ENCODE_UTYPE_IMM (RISCV_CONST_HIGH_PART (value)) + | (ENCODE_ITYPE_IMM (value) << 32); + break; + + case R_RISCV_JAL: + if (!VALID_UJTYPE_IMM (value)) + return bfd_reloc_overflow; + value = ENCODE_UJTYPE_IMM (value); + break; + + case R_RISCV_BRANCH: + if (!VALID_SBTYPE_IMM (value)) + return bfd_reloc_overflow; + value = ENCODE_SBTYPE_IMM (value); + break; + + case R_RISCV_RVC_BRANCH: + if (!VALID_RVC_B_IMM (value)) + return bfd_reloc_overflow; + value = ENCODE_RVC_B_IMM (value); + break; + + case R_RISCV_RVC_JUMP: + if (!VALID_RVC_J_IMM (value)) + return bfd_reloc_overflow; + value = ENCODE_RVC_J_IMM (value); + break; + + case R_RISCV_RVC_LUI: + if (!VALID_RVC_LUI_IMM (RISCV_CONST_HIGH_PART (value))) + return bfd_reloc_overflow; + value = ENCODE_RVC_LUI_IMM (RISCV_CONST_HIGH_PART (value)); + break; + + case R_RISCV_32: + case R_RISCV_64: + case R_RISCV_ADD8: + case R_RISCV_ADD16: + case R_RISCV_ADD32: + case R_RISCV_ADD64: + case R_RISCV_SUB8: + case R_RISCV_SUB16: + case R_RISCV_SUB32: + case R_RISCV_SUB64: + case R_RISCV_TLS_DTPREL32: + case R_RISCV_TLS_DTPREL64: + break; + + default: + return bfd_reloc_notsupported; + } + + bfd_vma word = bfd_get (howto->bitsize, input_bfd, contents + rel->r_offset); + word = (word & ~howto->dst_mask) | (value & howto->dst_mask); + bfd_put (howto->bitsize, input_bfd, word, contents + rel->r_offset); + + return bfd_reloc_ok; +} + +/* Remember all PC-relative high-part relocs we've encountered to help us + later resolve the corresponding low-part relocs. */ + +typedef struct +{ + bfd_vma address; + bfd_vma value; +} riscv_pcrel_hi_reloc; + +typedef struct riscv_pcrel_lo_reloc +{ + asection * input_section; + struct bfd_link_info * info; + reloc_howto_type * howto; + const Elf_Internal_Rela * reloc; + bfd_vma addr; + const char * name; + bfd_byte * contents; + struct riscv_pcrel_lo_reloc * next; +} riscv_pcrel_lo_reloc; + +typedef struct +{ + htab_t hi_relocs; + riscv_pcrel_lo_reloc *lo_relocs; +} riscv_pcrel_relocs; + +static hashval_t +riscv_pcrel_reloc_hash (const void *entry) +{ + const riscv_pcrel_hi_reloc *e = entry; + return (hashval_t)(e->address >> 2); +} + +static bfd_boolean +riscv_pcrel_reloc_eq (const void *entry1, const void *entry2) +{ + const riscv_pcrel_hi_reloc *e1 = entry1, *e2 = entry2; + return e1->address == e2->address; +} + +static bfd_boolean +riscv_init_pcrel_relocs (riscv_pcrel_relocs *p) +{ + + p->lo_relocs = NULL; + p->hi_relocs = htab_create (1024, riscv_pcrel_reloc_hash, + riscv_pcrel_reloc_eq, free); + return p->hi_relocs != NULL; +} + +static void +riscv_free_pcrel_relocs (riscv_pcrel_relocs *p) +{ + riscv_pcrel_lo_reloc *cur = p->lo_relocs; + + while (cur != NULL) + { + riscv_pcrel_lo_reloc *next = cur->next; + free (cur); + cur = next; + } + + htab_delete (p->hi_relocs); +} + +static bfd_boolean +riscv_record_pcrel_hi_reloc (riscv_pcrel_relocs *p, bfd_vma addr, bfd_vma value) +{ + riscv_pcrel_hi_reloc entry = {addr, value - addr}; + riscv_pcrel_hi_reloc **slot = + (riscv_pcrel_hi_reloc **) htab_find_slot (p->hi_relocs, &entry, INSERT); + + BFD_ASSERT (*slot == NULL); + *slot = (riscv_pcrel_hi_reloc *) bfd_malloc (sizeof (riscv_pcrel_hi_reloc)); + if (*slot == NULL) + return FALSE; + **slot = entry; + return TRUE; +} + +static bfd_boolean +riscv_record_pcrel_lo_reloc (riscv_pcrel_relocs *p, + asection *input_section, + struct bfd_link_info *info, + reloc_howto_type *howto, + const Elf_Internal_Rela *reloc, + bfd_vma addr, + const char *name, + bfd_byte *contents) +{ + riscv_pcrel_lo_reloc *entry; + entry = (riscv_pcrel_lo_reloc *) bfd_malloc (sizeof (riscv_pcrel_lo_reloc)); + if (entry == NULL) + return FALSE; + *entry = (riscv_pcrel_lo_reloc) {input_section, info, howto, reloc, addr, + name, contents, p->lo_relocs}; + p->lo_relocs = entry; + return TRUE; +} + +static bfd_boolean +riscv_resolve_pcrel_lo_relocs (riscv_pcrel_relocs *p) +{ + riscv_pcrel_lo_reloc *r; + + for (r = p->lo_relocs; r != NULL; r = r->next) + { + bfd *input_bfd = r->input_section->owner; + + riscv_pcrel_hi_reloc search = {r->addr, 0}; + riscv_pcrel_hi_reloc *entry = htab_find (p->hi_relocs, &search); + if (entry == NULL) + { + ((*r->info->callbacks->reloc_overflow) + (r->info, NULL, r->name, r->howto->name, (bfd_vma) 0, + input_bfd, r->input_section, r->reloc->r_offset)); + return TRUE; + } + + perform_relocation (r->howto, r->reloc, entry->value, r->input_section, + input_bfd, r->contents); + } + + return TRUE; +} + +/* Relocate a RISC-V ELF section. + + The RELOCATE_SECTION function is called by the new ELF backend linker + to handle the relocations for a section. + + The relocs are always passed as Rela structures. + + This function is responsible for adjusting the section contents as + necessary, and (if generating a relocatable output file) adjusting + the reloc addend as necessary. + + This function does not have to worry about setting the reloc + address or the reloc symbol index. + + LOCAL_SYMS is a pointer to the swapped in local symbols. + + LOCAL_SECTIONS is an array giving the section in the input file + corresponding to the st_shndx field of each local symbol. + + The global hash table entry for the global symbols can be found + via elf_sym_hashes (input_bfd). + + When generating relocatable output, this function must handle + STB_LOCAL/STT_SECTION symbols specially. The output symbol is + going to be the section symbol corresponding to the output + section, which means that the addend must be adjusted + accordingly. */ + +static bfd_boolean +riscv_elf_relocate_section (bfd *output_bfd, + struct bfd_link_info *info, + bfd *input_bfd, + asection *input_section, + bfd_byte *contents, + Elf_Internal_Rela *relocs, + Elf_Internal_Sym *local_syms, + asection **local_sections) +{ + Elf_Internal_Rela *rel; + Elf_Internal_Rela *relend; + riscv_pcrel_relocs pcrel_relocs; + bfd_boolean ret = FALSE; + asection *sreloc = elf_section_data (input_section)->sreloc; + struct riscv_elf_link_hash_table *htab = riscv_elf_hash_table (info); + Elf_Internal_Shdr *symtab_hdr = &elf_symtab_hdr (input_bfd); + struct elf_link_hash_entry **sym_hashes = elf_sym_hashes (input_bfd); + bfd_vma *local_got_offsets = elf_local_got_offsets (input_bfd); + + if (!riscv_init_pcrel_relocs (&pcrel_relocs)) + return FALSE; + + relend = relocs + input_section->reloc_count; + for (rel = relocs; rel < relend; rel++) + { + unsigned long r_symndx; + struct elf_link_hash_entry *h; + Elf_Internal_Sym *sym; + asection *sec; + bfd_vma relocation; + bfd_reloc_status_type r = bfd_reloc_ok; + const char *name; + bfd_vma off, ie_off; + bfd_boolean unresolved_reloc, is_ie = FALSE; + bfd_vma pc = sec_addr (input_section) + rel->r_offset; + int r_type = ELFNN_R_TYPE (rel->r_info), tls_type; + reloc_howto_type *howto = riscv_elf_rtype_to_howto (r_type); + const char *msg = NULL; + + if (r_type == R_RISCV_GNU_VTINHERIT || r_type == R_RISCV_GNU_VTENTRY) + continue; + + /* This is a final link. */ + r_symndx = ELFNN_R_SYM (rel->r_info); + h = NULL; + sym = NULL; + sec = NULL; + unresolved_reloc = FALSE; + if (r_symndx < symtab_hdr->sh_info) + { + sym = local_syms + r_symndx; + sec = local_sections[r_symndx]; + relocation = _bfd_elf_rela_local_sym (output_bfd, sym, &sec, rel); + } + else + { + bfd_boolean warned, ignored; + + RELOC_FOR_GLOBAL_SYMBOL (info, input_bfd, input_section, rel, + r_symndx, symtab_hdr, sym_hashes, + h, sec, relocation, + unresolved_reloc, warned, ignored); + if (warned) + { + /* To avoid generating warning messages about truncated + relocations, set the relocation's address to be the same as + the start of this section. */ + if (input_section->output_section != NULL) + relocation = input_section->output_section->vma; + else + relocation = 0; + } + } + + if (sec != NULL && discarded_section (sec)) + RELOC_AGAINST_DISCARDED_SECTION (info, input_bfd, input_section, + rel, 1, relend, howto, 0, contents); + + if (bfd_link_relocatable (info)) + continue; + + if (h != NULL) + name = h->root.root.string; + else + { + name = (bfd_elf_string_from_elf_section + (input_bfd, symtab_hdr->sh_link, sym->st_name)); + if (name == NULL || *name == '\0') + name = bfd_section_name (input_bfd, sec); + } + + switch (r_type) + { + case R_RISCV_NONE: + case R_RISCV_TPREL_ADD: + case R_RISCV_COPY: + case R_RISCV_JUMP_SLOT: + case R_RISCV_RELATIVE: + /* These require nothing of us at all. */ + continue; + + case R_RISCV_HI20: + case R_RISCV_BRANCH: + case R_RISCV_RVC_BRANCH: + case R_RISCV_RVC_LUI: + case R_RISCV_LO12_I: + case R_RISCV_LO12_S: + /* These require no special handling beyond perform_relocation. */ + break; + + case R_RISCV_GOT_HI20: + if (h != NULL) + { + bfd_boolean dyn, pic; + + off = h->got.offset; + BFD_ASSERT (off != (bfd_vma) -1); + dyn = elf_hash_table (info)->dynamic_sections_created; + pic = bfd_link_pic (info); + + if (! WILL_CALL_FINISH_DYNAMIC_SYMBOL (dyn, pic, h) + || (pic && SYMBOL_REFERENCES_LOCAL (info, h))) + { + /* This is actually a static link, or it is a + -Bsymbolic link and the symbol is defined + locally, or the symbol was forced to be local + because of a version file. We must initialize + this entry in the global offset table. Since the + offset must always be a multiple of the word size, + we use the least significant bit to record whether + we have initialized it already. + + When doing a dynamic link, we create a .rela.got + relocation entry to initialize the value. This + is done in the finish_dynamic_symbol routine. */ + if ((off & 1) != 0) + off &= ~1; + else + { + bfd_put_NN (output_bfd, relocation, + htab->elf.sgot->contents + off); + h->got.offset |= 1; + } + } + else + unresolved_reloc = FALSE; + } + else + { + BFD_ASSERT (local_got_offsets != NULL + && local_got_offsets[r_symndx] != (bfd_vma) -1); + + off = local_got_offsets[r_symndx]; + + /* The offset must always be a multiple of the word size. + So, we can use the least significant bit to record + whether we have already processed this entry. */ + if ((off & 1) != 0) + off &= ~1; + else + { + if (bfd_link_pic (info)) + { + asection *s; + Elf_Internal_Rela outrel; + + /* We need to generate a R_RISCV_RELATIVE reloc + for the dynamic linker. */ + s = htab->elf.srelgot; + BFD_ASSERT (s != NULL); + + outrel.r_offset = sec_addr (htab->elf.sgot) + off; + outrel.r_info = + ELFNN_R_INFO (0, R_RISCV_RELATIVE); + outrel.r_addend = relocation; + relocation = 0; + riscv_elf_append_rela (output_bfd, s, &outrel); + } + + bfd_put_NN (output_bfd, relocation, + htab->elf.sgot->contents + off); + local_got_offsets[r_symndx] |= 1; + } + } + relocation = sec_addr (htab->elf.sgot) + off; + if (!riscv_record_pcrel_hi_reloc (&pcrel_relocs, pc, relocation)) + r = bfd_reloc_overflow; + break; + + case R_RISCV_ADD8: + case R_RISCV_ADD16: + case R_RISCV_ADD32: + case R_RISCV_ADD64: + { + bfd_vma old_value = bfd_get (howto->bitsize, input_bfd, + contents + rel->r_offset); + relocation = old_value + relocation; + } + break; + + case R_RISCV_SUB8: + case R_RISCV_SUB16: + case R_RISCV_SUB32: + case R_RISCV_SUB64: + { + bfd_vma old_value = bfd_get (howto->bitsize, input_bfd, + contents + rel->r_offset); + relocation = old_value - relocation; + } + break; + + case R_RISCV_CALL_PLT: + case R_RISCV_CALL: + case R_RISCV_JAL: + case R_RISCV_RVC_JUMP: + if (bfd_link_pic (info) && h != NULL && h->plt.offset != MINUS_ONE) + { + /* Refer to the PLT entry. */ + relocation = sec_addr (htab->elf.splt) + h->plt.offset; + unresolved_reloc = FALSE; + } + break; + + case R_RISCV_TPREL_HI20: + relocation = tpoff (info, relocation); + break; + + case R_RISCV_TPREL_LO12_I: + case R_RISCV_TPREL_LO12_S: + relocation = tpoff (info, relocation); + if (VALID_ITYPE_IMM (relocation + rel->r_addend)) + { + /* We can use tp as the base register. */ + bfd_vma insn = bfd_get_32 (input_bfd, contents + rel->r_offset); + insn &= ~(OP_MASK_RS1 << OP_SH_RS1); + insn |= X_TP << OP_SH_RS1; + bfd_put_32 (input_bfd, insn, contents + rel->r_offset); + } + break; + + case R_RISCV_GPREL_I: + case R_RISCV_GPREL_S: + { + bfd_vma gp = riscv_global_pointer_value (info); + bfd_boolean x0_base = VALID_ITYPE_IMM (relocation + rel->r_addend); + if (x0_base || VALID_ITYPE_IMM (relocation + rel->r_addend - gp)) + { + /* We can use x0 or gp as the base register. */ + bfd_vma insn = bfd_get_32 (input_bfd, contents + rel->r_offset); + insn &= ~(OP_MASK_RS1 << OP_SH_RS1); + if (!x0_base) + { + rel->r_addend -= gp; + insn |= X_GP << OP_SH_RS1; + } + bfd_put_32 (input_bfd, insn, contents + rel->r_offset); + } + else + r = bfd_reloc_overflow; + break; + } + + case R_RISCV_PCREL_HI20: + if (!riscv_record_pcrel_hi_reloc (&pcrel_relocs, pc, + relocation + rel->r_addend)) + r = bfd_reloc_overflow; + break; + + case R_RISCV_PCREL_LO12_I: + case R_RISCV_PCREL_LO12_S: + if (riscv_record_pcrel_lo_reloc (&pcrel_relocs, input_section, info, + howto, rel, relocation, name, + contents)) + continue; + r = bfd_reloc_overflow; + break; + + case R_RISCV_TLS_DTPREL32: + case R_RISCV_TLS_DTPREL64: + relocation = dtpoff (info, relocation); + break; + + case R_RISCV_32: + case R_RISCV_64: + if ((input_section->flags & SEC_ALLOC) == 0) + break; + + if ((bfd_link_pic (info) + && (h == NULL + || ELF_ST_VISIBILITY (h->other) == STV_DEFAULT + || h->root.type != bfd_link_hash_undefweak) + && (! howto->pc_relative + || !SYMBOL_CALLS_LOCAL (info, h))) + || (!bfd_link_pic (info) + && h != NULL + && h->dynindx != -1 + && !h->non_got_ref + && ((h->def_dynamic + && !h->def_regular) + || h->root.type == bfd_link_hash_undefweak + || h->root.type == bfd_link_hash_undefined))) + { + Elf_Internal_Rela outrel; + bfd_boolean skip_static_relocation, skip_dynamic_relocation; + + /* When generating a shared object, these relocations + are copied into the output file to be resolved at run + time. */ + + outrel.r_offset = + _bfd_elf_section_offset (output_bfd, info, input_section, + rel->r_offset); + skip_static_relocation = outrel.r_offset != (bfd_vma) -2; + skip_dynamic_relocation = outrel.r_offset >= (bfd_vma) -2; + outrel.r_offset += sec_addr (input_section); + + if (skip_dynamic_relocation) + memset (&outrel, 0, sizeof outrel); + else if (h != NULL && h->dynindx != -1 + && !(bfd_link_pic (info) + && SYMBOLIC_BIND (info, h) + && h->def_regular)) + { + outrel.r_info = ELFNN_R_INFO (h->dynindx, r_type); + outrel.r_addend = rel->r_addend; + } + else + { + outrel.r_info = ELFNN_R_INFO (0, R_RISCV_RELATIVE); + outrel.r_addend = relocation + rel->r_addend; + } + + riscv_elf_append_rela (output_bfd, sreloc, &outrel); + if (skip_static_relocation) + continue; + } + break; + + case R_RISCV_TLS_GOT_HI20: + is_ie = TRUE; + /* Fall through. */ + + case R_RISCV_TLS_GD_HI20: + if (h != NULL) + { + off = h->got.offset; + h->got.offset |= 1; + } + else + { + off = local_got_offsets[r_symndx]; + local_got_offsets[r_symndx] |= 1; + } + + tls_type = _bfd_riscv_elf_tls_type (input_bfd, h, r_symndx); + BFD_ASSERT (tls_type & (GOT_TLS_IE | GOT_TLS_GD)); + /* If this symbol is referenced by both GD and IE TLS, the IE + reference's GOT slot follows the GD reference's slots. */ + ie_off = 0; + if ((tls_type & GOT_TLS_GD) && (tls_type & GOT_TLS_IE)) + ie_off = 2 * GOT_ENTRY_SIZE; + + if ((off & 1) != 0) + off &= ~1; + else + { + Elf_Internal_Rela outrel; + int indx = 0; + bfd_boolean need_relocs = FALSE; + + if (htab->elf.srelgot == NULL) + abort (); + + if (h != NULL) + { + bfd_boolean dyn, pic; + dyn = htab->elf.dynamic_sections_created; + pic = bfd_link_pic (info); + + if (WILL_CALL_FINISH_DYNAMIC_SYMBOL (dyn, pic, h) + && (!pic || !SYMBOL_REFERENCES_LOCAL (info, h))) + indx = h->dynindx; + } + + /* The GOT entries have not been initialized yet. Do it + now, and emit any relocations. */ + if ((bfd_link_pic (info) || indx != 0) + && (h == NULL + || ELF_ST_VISIBILITY (h->other) == STV_DEFAULT + || h->root.type != bfd_link_hash_undefweak)) + need_relocs = TRUE; + + if (tls_type & GOT_TLS_GD) + { + if (need_relocs) + { + outrel.r_offset = sec_addr (htab->elf.sgot) + off; + outrel.r_addend = 0; + outrel.r_info = ELFNN_R_INFO (indx, R_RISCV_TLS_DTPMODNN); + bfd_put_NN (output_bfd, 0, + htab->elf.sgot->contents + off); + riscv_elf_append_rela (output_bfd, htab->elf.srelgot, &outrel); + if (indx == 0) + { + BFD_ASSERT (! unresolved_reloc); + bfd_put_NN (output_bfd, + dtpoff (info, relocation), + (htab->elf.sgot->contents + off + + RISCV_ELF_WORD_BYTES)); + } + else + { + bfd_put_NN (output_bfd, 0, + (htab->elf.sgot->contents + off + + RISCV_ELF_WORD_BYTES)); + outrel.r_info = ELFNN_R_INFO (indx, R_RISCV_TLS_DTPRELNN); + outrel.r_offset += RISCV_ELF_WORD_BYTES; + riscv_elf_append_rela (output_bfd, htab->elf.srelgot, &outrel); + } + } + else + { + /* If we are not emitting relocations for a + general dynamic reference, then we must be in a + static link or an executable link with the + symbol binding locally. Mark it as belonging + to module 1, the executable. */ + bfd_put_NN (output_bfd, 1, + htab->elf.sgot->contents + off); + bfd_put_NN (output_bfd, + dtpoff (info, relocation), + (htab->elf.sgot->contents + off + + RISCV_ELF_WORD_BYTES)); + } + } + + if (tls_type & GOT_TLS_IE) + { + if (need_relocs) + { + bfd_put_NN (output_bfd, 0, + htab->elf.sgot->contents + off + ie_off); + outrel.r_offset = sec_addr (htab->elf.sgot) + + off + ie_off; + outrel.r_addend = 0; + if (indx == 0) + outrel.r_addend = tpoff (info, relocation); + outrel.r_info = ELFNN_R_INFO (indx, R_RISCV_TLS_TPRELNN); + riscv_elf_append_rela (output_bfd, htab->elf.srelgot, &outrel); + } + else + { + bfd_put_NN (output_bfd, tpoff (info, relocation), + htab->elf.sgot->contents + off + ie_off); + } + } + } + + BFD_ASSERT (off < (bfd_vma) -2); + relocation = sec_addr (htab->elf.sgot) + off + (is_ie ? ie_off : 0); + if (!riscv_record_pcrel_hi_reloc (&pcrel_relocs, pc, relocation)) + r = bfd_reloc_overflow; + unresolved_reloc = FALSE; + break; + + default: + r = bfd_reloc_notsupported; + } + + /* Dynamic relocs are not propagated for SEC_DEBUGGING sections + because such sections are not SEC_ALLOC and thus ld.so will + not process them. */ + if (unresolved_reloc + && !((input_section->flags & SEC_DEBUGGING) != 0 + && h->def_dynamic) + && _bfd_elf_section_offset (output_bfd, info, input_section, + rel->r_offset) != (bfd_vma) -1) + { + (*_bfd_error_handler) + (_("%B(%A+0x%lx): unresolvable %s relocation against symbol `%s'"), + input_bfd, + input_section, + (long) rel->r_offset, + howto->name, + h->root.root.string); + continue; + } + + if (r == bfd_reloc_ok) + r = perform_relocation (howto, rel, relocation, input_section, + input_bfd, contents); + + switch (r) + { + case bfd_reloc_ok: + continue; + + case bfd_reloc_overflow: + info->callbacks->reloc_overflow + (info, (h ? &h->root : NULL), name, howto->name, + (bfd_vma) 0, input_bfd, input_section, rel->r_offset); + break; + + case bfd_reloc_undefined: + info->callbacks->undefined_symbol + (info, name, input_bfd, input_section, rel->r_offset, + TRUE); + break; + + case bfd_reloc_outofrange: + msg = _("internal error: out of range error"); + break; + + case bfd_reloc_notsupported: + msg = _("internal error: unsupported relocation error"); + break; + + case bfd_reloc_dangerous: + msg = _("internal error: dangerous relocation"); + break; + + default: + msg = _("internal error: unknown error"); + break; + } + + if (msg) + info->callbacks->warning + (info, msg, name, input_bfd, input_section, rel->r_offset); + goto out; + } + + ret = riscv_resolve_pcrel_lo_relocs (&pcrel_relocs); +out: + riscv_free_pcrel_relocs (&pcrel_relocs); + return ret; +} + +/* Finish up dynamic symbol handling. We set the contents of various + dynamic sections here. */ + +static bfd_boolean +riscv_elf_finish_dynamic_symbol (bfd *output_bfd, + struct bfd_link_info *info, + struct elf_link_hash_entry *h, + Elf_Internal_Sym *sym) +{ + struct riscv_elf_link_hash_table *htab = riscv_elf_hash_table (info); + const struct elf_backend_data *bed = get_elf_backend_data (output_bfd); + + if (h->plt.offset != (bfd_vma) -1) + { + /* We've decided to create a PLT entry for this symbol. */ + bfd_byte *loc; + bfd_vma i, header_address, plt_idx, got_address; + uint32_t plt_entry[PLT_ENTRY_INSNS]; + Elf_Internal_Rela rela; + + BFD_ASSERT (h->dynindx != -1); + + /* Calculate the address of the PLT header. */ + header_address = sec_addr (htab->elf.splt); + + /* Calculate the index of the entry. */ + plt_idx = (h->plt.offset - PLT_HEADER_SIZE) / PLT_ENTRY_SIZE; + + /* Calculate the address of the .got.plt entry. */ + got_address = riscv_elf_got_plt_val (plt_idx, info); + + /* Find out where the .plt entry should go. */ + loc = htab->elf.splt->contents + h->plt.offset; + + /* Fill in the PLT entry itself. */ + riscv_make_plt_entry (got_address, header_address + h->plt.offset, + plt_entry); + for (i = 0; i < PLT_ENTRY_INSNS; i++) + bfd_put_32 (output_bfd, plt_entry[i], loc + 4*i); + + /* Fill in the initial value of the .got.plt entry. */ + loc = htab->elf.sgotplt->contents + + (got_address - sec_addr (htab->elf.sgotplt)); + bfd_put_NN (output_bfd, sec_addr (htab->elf.splt), loc); + + /* Fill in the entry in the .rela.plt section. */ + rela.r_offset = got_address; + rela.r_addend = 0; + rela.r_info = ELFNN_R_INFO (h->dynindx, R_RISCV_JUMP_SLOT); + + loc = htab->elf.srelplt->contents + plt_idx * sizeof (ElfNN_External_Rela); + bed->s->swap_reloca_out (output_bfd, &rela, loc); + + if (!h->def_regular) + { + /* Mark the symbol as undefined, rather than as defined in + the .plt section. Leave the value alone. */ + sym->st_shndx = SHN_UNDEF; + /* If the symbol is weak, we do need to clear the value. + Otherwise, the PLT entry would provide a definition for + the symbol even if the symbol wasn't defined anywhere, + and so the symbol would never be NULL. */ + if (!h->ref_regular_nonweak) + sym->st_value = 0; + } + } + + if (h->got.offset != (bfd_vma) -1 + && !(riscv_elf_hash_entry(h)->tls_type & (GOT_TLS_GD | GOT_TLS_IE))) + { + asection *sgot; + asection *srela; + Elf_Internal_Rela rela; + + /* This symbol has an entry in the GOT. Set it up. */ + + sgot = htab->elf.sgot; + srela = htab->elf.srelgot; + BFD_ASSERT (sgot != NULL && srela != NULL); + + rela.r_offset = sec_addr (sgot) + (h->got.offset &~ (bfd_vma) 1); + + /* If this is a -Bsymbolic link, and the symbol is defined + locally, we just want to emit a RELATIVE reloc. Likewise if + the symbol was forced to be local because of a version file. + The entry in the global offset table will already have been + initialized in the relocate_section function. */ + if (bfd_link_pic (info) + && (info->symbolic || h->dynindx == -1) + && h->def_regular) + { + asection *sec = h->root.u.def.section; + rela.r_info = ELFNN_R_INFO (0, R_RISCV_RELATIVE); + rela.r_addend = (h->root.u.def.value + + sec->output_section->vma + + sec->output_offset); + } + else + { + BFD_ASSERT (h->dynindx != -1); + rela.r_info = ELFNN_R_INFO (h->dynindx, R_RISCV_NN); + rela.r_addend = 0; + } + + bfd_put_NN (output_bfd, 0, + sgot->contents + (h->got.offset & ~(bfd_vma) 1)); + riscv_elf_append_rela (output_bfd, srela, &rela); + } + + if (h->needs_copy) + { + Elf_Internal_Rela rela; + + /* This symbols needs a copy reloc. Set it up. */ + BFD_ASSERT (h->dynindx != -1); + + rela.r_offset = sec_addr (h->root.u.def.section) + h->root.u.def.value; + rela.r_info = ELFNN_R_INFO (h->dynindx, R_RISCV_COPY); + rela.r_addend = 0; + riscv_elf_append_rela (output_bfd, htab->srelbss, &rela); + } + + /* Mark some specially defined symbols as absolute. */ + if (h == htab->elf.hdynamic + || (h == htab->elf.hgot || h == htab->elf.hplt)) + sym->st_shndx = SHN_ABS; + + return TRUE; +} + +/* Finish up the dynamic sections. */ + +static bfd_boolean +riscv_finish_dyn (bfd *output_bfd, struct bfd_link_info *info, + bfd *dynobj, asection *sdyn) +{ + struct riscv_elf_link_hash_table *htab = riscv_elf_hash_table (info); + const struct elf_backend_data *bed = get_elf_backend_data (output_bfd); + size_t dynsize = bed->s->sizeof_dyn; + bfd_byte *dyncon, *dynconend; + + dynconend = sdyn->contents + sdyn->size; + for (dyncon = sdyn->contents; dyncon < dynconend; dyncon += dynsize) + { + Elf_Internal_Dyn dyn; + asection *s; + + bed->s->swap_dyn_in (dynobj, dyncon, &dyn); + + switch (dyn.d_tag) + { + case DT_PLTGOT: + s = htab->elf.sgotplt; + dyn.d_un.d_ptr = s->output_section->vma + s->output_offset; + break; + case DT_JMPREL: + s = htab->elf.srelplt; + dyn.d_un.d_ptr = s->output_section->vma + s->output_offset; + break; + case DT_PLTRELSZ: + s = htab->elf.srelplt; + dyn.d_un.d_val = s->size; + break; + default: + continue; + } + + bed->s->swap_dyn_out (output_bfd, &dyn, dyncon); + } + return TRUE; +} + +static bfd_boolean +riscv_elf_finish_dynamic_sections (bfd *output_bfd, + struct bfd_link_info *info) +{ + bfd *dynobj; + asection *sdyn; + struct riscv_elf_link_hash_table *htab; + + htab = riscv_elf_hash_table (info); + BFD_ASSERT (htab != NULL); + dynobj = htab->elf.dynobj; + + sdyn = bfd_get_linker_section (dynobj, ".dynamic"); + + if (elf_hash_table (info)->dynamic_sections_created) + { + asection *splt; + bfd_boolean ret; + + splt = htab->elf.splt; + BFD_ASSERT (splt != NULL && sdyn != NULL); + + ret = riscv_finish_dyn (output_bfd, info, dynobj, sdyn); + + if (ret != TRUE) + return ret; + + /* Fill in the head and tail entries in the procedure linkage table. */ + if (splt->size > 0) + { + int i; + uint32_t plt_header[PLT_HEADER_INSNS]; + riscv_make_plt_header (sec_addr (htab->elf.sgotplt), + sec_addr (splt), plt_header); + + for (i = 0; i < PLT_HEADER_INSNS; i++) + bfd_put_32 (output_bfd, plt_header[i], splt->contents + 4*i); + } + + elf_section_data (splt->output_section)->this_hdr.sh_entsize + = PLT_ENTRY_SIZE; + } + + if (htab->elf.sgotplt) + { + asection *output_section = htab->elf.sgotplt->output_section; + + if (bfd_is_abs_section (output_section)) + { + (*_bfd_error_handler) + (_("discarded output section: `%A'"), htab->elf.sgotplt); + return FALSE; + } + + if (htab->elf.sgotplt->size > 0) + { + /* Write the first two entries in .got.plt, needed for the dynamic + linker. */ + bfd_put_NN (output_bfd, (bfd_vma) -1, htab->elf.sgotplt->contents); + bfd_put_NN (output_bfd, (bfd_vma) 0, + htab->elf.sgotplt->contents + GOT_ENTRY_SIZE); + } + + elf_section_data (output_section)->this_hdr.sh_entsize = GOT_ENTRY_SIZE; + } + + if (htab->elf.sgot) + { + asection *output_section = htab->elf.sgot->output_section; + + if (htab->elf.sgot->size > 0) + { + /* Set the first entry in the global offset table to the address of + the dynamic section. */ + bfd_vma val = sdyn ? sec_addr (sdyn) : 0; + bfd_put_NN (output_bfd, val, htab->elf.sgot->contents); + } + + elf_section_data (output_section)->this_hdr.sh_entsize = GOT_ENTRY_SIZE; + } + + return TRUE; +} + +/* Return address for Ith PLT stub in section PLT, for relocation REL + or (bfd_vma) -1 if it should not be included. */ + +static bfd_vma +riscv_elf_plt_sym_val (bfd_vma i, const asection *plt, + const arelent *rel ATTRIBUTE_UNUSED) +{ + return plt->vma + PLT_HEADER_SIZE + i * PLT_ENTRY_SIZE; +} + +static enum elf_reloc_type_class +riscv_reloc_type_class (const struct bfd_link_info *info ATTRIBUTE_UNUSED, + const asection *rel_sec ATTRIBUTE_UNUSED, + const Elf_Internal_Rela *rela) +{ + switch (ELFNN_R_TYPE (rela->r_info)) + { + case R_RISCV_RELATIVE: + return reloc_class_relative; + case R_RISCV_JUMP_SLOT: + return reloc_class_plt; + case R_RISCV_COPY: + return reloc_class_copy; + default: + return reloc_class_normal; + } +} + +/* Merge backend specific data from an object file to the output + object file when linking. */ + +static bfd_boolean +_bfd_riscv_elf_merge_private_bfd_data (bfd *ibfd, struct bfd_link_info *info) +{ + bfd *obfd = info->output_bfd; + flagword new_flags = elf_elfheader (ibfd)->e_flags; + flagword old_flags = elf_elfheader (obfd)->e_flags; + + if (!is_riscv_elf (ibfd) || !is_riscv_elf (obfd)) + return TRUE; + + if (strcmp (bfd_get_target (ibfd), bfd_get_target (obfd)) != 0) + { + (*_bfd_error_handler) + (_("%B: ABI is incompatible with that of the selected emulation"), + ibfd); + return FALSE; + } + + if (!_bfd_elf_merge_object_attributes (ibfd, info)) + return FALSE; + + if (! elf_flags_init (obfd)) + { + elf_flags_init (obfd) = TRUE; + elf_elfheader (obfd)->e_flags = new_flags; + return TRUE; + } + + /* Disallow linking soft-float and hard-float. */ + if ((old_flags ^ new_flags) & EF_RISCV_SOFT_FLOAT) + { + (*_bfd_error_handler) + (_("%B: can't link hard-float modules with soft-float modules"), ibfd); + goto fail; + } + + /* Allow linking RVC and non-RVC, and keep the RVC flag. */ + elf_elfheader (obfd)->e_flags |= new_flags & EF_RISCV_RVC; + + return TRUE; + +fail: + bfd_set_error (bfd_error_bad_value); + return FALSE; +} + +/* Delete some bytes from a section while relaxing. */ + +static bfd_boolean +riscv_relax_delete_bytes (bfd *abfd, asection *sec, bfd_vma addr, size_t count) +{ + unsigned int i, symcount; + bfd_vma toaddr = sec->size; + struct elf_link_hash_entry **sym_hashes = elf_sym_hashes (abfd); + Elf_Internal_Shdr *symtab_hdr = &elf_tdata (abfd)->symtab_hdr; + unsigned int sec_shndx = _bfd_elf_section_from_bfd_section (abfd, sec); + struct bfd_elf_section_data *data = elf_section_data (sec); + bfd_byte *contents = data->this_hdr.contents; + + /* Actually delete the bytes. */ + sec->size -= count; + memmove (contents + addr, contents + addr + count, toaddr - addr - count); + + /* Adjust the location of all of the relocs. Note that we need not + adjust the addends, since all PC-relative references must be against + symbols, which we will adjust below. */ + for (i = 0; i < sec->reloc_count; i++) + if (data->relocs[i].r_offset > addr && data->relocs[i].r_offset < toaddr) + data->relocs[i].r_offset -= count; + + /* Adjust the local symbols defined in this section. */ + for (i = 0; i < symtab_hdr->sh_info; i++) + { + Elf_Internal_Sym *sym = (Elf_Internal_Sym *) symtab_hdr->contents + i; + if (sym->st_shndx == sec_shndx) + { + /* If the symbol is in the range of memory we just moved, we + have to adjust its value. */ + if (sym->st_value > addr && sym->st_value <= toaddr) + sym->st_value -= count; + + /* If the symbol *spans* the bytes we just deleted (i.e. its + *end* is in the moved bytes but its *start* isn't), then we + must adjust its size. */ + if (sym->st_value <= addr + && sym->st_value + sym->st_size > addr + && sym->st_value + sym->st_size <= toaddr) + sym->st_size -= count; + } + } + + /* Now adjust the global symbols defined in this section. */ + symcount = ((symtab_hdr->sh_size / sizeof (ElfNN_External_Sym)) + - symtab_hdr->sh_info); + + for (i = 0; i < symcount; i++) + { + struct elf_link_hash_entry *sym_hash = sym_hashes[i]; + + if ((sym_hash->root.type == bfd_link_hash_defined + || sym_hash->root.type == bfd_link_hash_defweak) + && sym_hash->root.u.def.section == sec) + { + /* As above, adjust the value if needed. */ + if (sym_hash->root.u.def.value > addr + && sym_hash->root.u.def.value <= toaddr) + sym_hash->root.u.def.value -= count; + + /* As above, adjust the size if needed. */ + if (sym_hash->root.u.def.value <= addr + && sym_hash->root.u.def.value + sym_hash->size > addr + && sym_hash->root.u.def.value + sym_hash->size <= toaddr) + sym_hash->size -= count; + } + } + + return TRUE; +} + +/* Relax AUIPC + JALR into JAL. */ + +static bfd_boolean +_bfd_riscv_relax_call (bfd *abfd, asection *sec, asection *sym_sec, + struct bfd_link_info *link_info, + Elf_Internal_Rela *rel, + bfd_vma symval, + unsigned int max_alignment, + bfd_boolean *again) +{ + bfd_byte *contents = elf_section_data (sec)->this_hdr.contents; + bfd_signed_vma foff = symval - (sec_addr (sec) + rel->r_offset); + bfd_boolean near_zero = (symval + RISCV_IMM_REACH/2) < RISCV_IMM_REACH; + bfd_vma auipc, jalr; + int rd, r_type, len = 4, rvc = elf_elfheader (abfd)->e_flags & EF_RISCV_RVC; + + /* If the call crosses section boundaries, an alignment directive could + cause the PC-relative offset to later increase. */ + if (VALID_UJTYPE_IMM (foff) && sym_sec->output_section != sec->output_section) + foff += (foff < 0 ? -max_alignment : max_alignment); + + /* See if this function call can be shortened. */ + if (!VALID_UJTYPE_IMM (foff) && !(!bfd_link_pic (link_info) && near_zero)) + return TRUE; + + /* Shorten the function call. */ + BFD_ASSERT (rel->r_offset + 8 <= sec->size); + + auipc = bfd_get_32 (abfd, contents + rel->r_offset); + jalr = bfd_get_32 (abfd, contents + rel->r_offset + 4); + rd = (jalr >> OP_SH_RD) & OP_MASK_RD; + rvc = rvc && VALID_RVC_J_IMM (foff) && ARCH_SIZE == 32; + + if (rvc && (rd == 0 || rd == X_RA)) + { + /* Relax to C.J[AL] rd, addr. */ + r_type = R_RISCV_RVC_JUMP; + auipc = rd == 0 ? MATCH_C_J : MATCH_C_JAL; + len = 2; + } + else if (VALID_UJTYPE_IMM (foff)) + { + /* Relax to JAL rd, addr. */ + r_type = R_RISCV_JAL; + auipc = MATCH_JAL | (rd << OP_SH_RD); + } + else /* near_zero */ + { + /* Relax to JALR rd, x0, addr. */ + r_type = R_RISCV_LO12_I; + auipc = MATCH_JALR | (rd << OP_SH_RD); + } + + /* Replace the R_RISCV_CALL reloc. */ + rel->r_info = ELFNN_R_INFO (ELFNN_R_SYM (rel->r_info), r_type); + /* Replace the AUIPC. */ + bfd_put (8 * len, abfd, auipc, contents + rel->r_offset); + + /* Delete unnecessary JALR. */ + *again = TRUE; + return riscv_relax_delete_bytes (abfd, sec, rel->r_offset + len, 8 - len); +} + +/* Traverse all output sections and return the max alignment. */ + +static unsigned int +_bfd_riscv_get_max_alignment (asection *sec) +{ + unsigned int max_alignment_power = 0; + asection *o; + + for (o = sec->output_section->owner->sections; o != NULL; o = o->next) + { + if (o->alignment_power > max_alignment_power) + max_alignment_power = o->alignment_power; + } + + return 1 << max_alignment_power; +} + +/* Relax non-PIC global variable references. */ + +static bfd_boolean +_bfd_riscv_relax_lui (bfd *abfd, + asection *sec, + asection *sym_sec, + struct bfd_link_info *link_info, + Elf_Internal_Rela *rel, + bfd_vma symval, + unsigned int max_alignment, + bfd_boolean *again) +{ + bfd_byte *contents = elf_section_data (sec)->this_hdr.contents; + bfd_vma gp = riscv_global_pointer_value (link_info); + int use_rvc = elf_elfheader (abfd)->e_flags & EF_RISCV_RVC; + + /* Mergeable symbols and code might later move out of range. */ + if (sym_sec->flags & (SEC_MERGE | SEC_CODE)) + return TRUE; + + BFD_ASSERT (rel->r_offset + 4 <= sec->size); + + /* Is the reference in range of x0 or gp? + Valid gp range conservatively because of alignment issue. */ + if (VALID_ITYPE_IMM (symval) + || (symval >= gp && VALID_ITYPE_IMM (symval - gp + max_alignment)) + || (symval < gp && VALID_ITYPE_IMM (symval - gp - max_alignment))) + { + unsigned sym = ELFNN_R_SYM (rel->r_info); + switch (ELFNN_R_TYPE (rel->r_info)) + { + case R_RISCV_LO12_I: + rel->r_info = ELFNN_R_INFO (sym, R_RISCV_GPREL_I); + return TRUE; + + case R_RISCV_LO12_S: + rel->r_info = ELFNN_R_INFO (sym, R_RISCV_GPREL_S); + return TRUE; + + case R_RISCV_HI20: + /* We can delete the unnecessary LUI and reloc. */ + rel->r_info = ELFNN_R_INFO (0, R_RISCV_NONE); + *again = TRUE; + return riscv_relax_delete_bytes (abfd, sec, rel->r_offset, 4); + + default: + abort (); + } + } + + /* Can we relax LUI to C.LUI? Alignment might move the section forward; + account for this assuming page alignment at worst. */ + if (use_rvc + && ELFNN_R_TYPE (rel->r_info) == R_RISCV_HI20 + && VALID_RVC_LUI_IMM (RISCV_CONST_HIGH_PART (symval)) + && VALID_RVC_LUI_IMM (RISCV_CONST_HIGH_PART (symval + ELF_MAXPAGESIZE))) + { + /* Replace LUI with C.LUI if legal (i.e., rd != x2/sp). */ + bfd_vma lui = bfd_get_32 (abfd, contents + rel->r_offset); + if (((lui >> OP_SH_RD) & OP_MASK_RD) == X_SP) + return TRUE; + + lui = (lui & (OP_MASK_RD << OP_SH_RD)) | MATCH_C_LUI; + bfd_put_32 (abfd, lui, contents + rel->r_offset); + + /* Replace the R_RISCV_HI20 reloc. */ + rel->r_info = ELFNN_R_INFO (ELFNN_R_SYM (rel->r_info), R_RISCV_RVC_LUI); + + *again = TRUE; + return riscv_relax_delete_bytes (abfd, sec, rel->r_offset + 2, 2); + } + + return TRUE; +} + +/* Relax non-PIC TLS references. */ + +static bfd_boolean +_bfd_riscv_relax_tls_le (bfd *abfd, + asection *sec, + asection *sym_sec ATTRIBUTE_UNUSED, + struct bfd_link_info *link_info, + Elf_Internal_Rela *rel, + bfd_vma symval, + unsigned int max_alignment ATTRIBUTE_UNUSED, + bfd_boolean *again) +{ + /* See if this symbol is in range of tp. */ + if (RISCV_CONST_HIGH_PART (tpoff (link_info, symval)) != 0) + return TRUE; + + /* We can delete the unnecessary LUI and tp add. The LO12 reloc will be + made directly tp-relative. */ + BFD_ASSERT (rel->r_offset + 4 <= sec->size); + rel->r_info = ELFNN_R_INFO (0, R_RISCV_NONE); + + *again = TRUE; + return riscv_relax_delete_bytes (abfd, sec, rel->r_offset, 4); +} + +/* Implement R_RISCV_ALIGN by deleting excess alignment NOPs. */ + +static bfd_boolean +_bfd_riscv_relax_align (bfd *abfd, asection *sec, + asection *sym_sec ATTRIBUTE_UNUSED, + struct bfd_link_info *link_info ATTRIBUTE_UNUSED, + Elf_Internal_Rela *rel, + bfd_vma symval, + unsigned int max_alignment ATTRIBUTE_UNUSED, + bfd_boolean *again ATTRIBUTE_UNUSED) +{ + bfd_byte *contents = elf_section_data (sec)->this_hdr.contents; + bfd_vma alignment = 1, pos; + while (alignment <= rel->r_addend) + alignment *= 2; + + symval -= rel->r_addend; + bfd_vma aligned_addr = ((symval - 1) & ~(alignment - 1)) + alignment; + bfd_vma nop_bytes = aligned_addr - symval; + + /* Once we've handled an R_RISCV_ALIGN, we can't relax anything else. */ + sec->sec_flg0 = TRUE; + + /* Make sure there are enough NOPs to actually achieve the alignment. */ + if (rel->r_addend < nop_bytes) + return FALSE; + + /* Delete the reloc. */ + rel->r_info = ELFNN_R_INFO (0, R_RISCV_NONE); + + /* If the number of NOPs is already correct, there's nothing to do. */ + if (nop_bytes == rel->r_addend) + return TRUE; + + /* Write as many RISC-V NOPs as we need. */ + for (pos = 0; pos < (nop_bytes & -4); pos += 4) + bfd_put_32 (abfd, RISCV_NOP, contents + rel->r_offset + pos); + + /* Write a final RVC NOP if need be. */ + if (nop_bytes % 4 != 0) + bfd_put_16 (abfd, RVC_NOP, contents + rel->r_offset + pos); + + /* Delete the excess bytes. */ + return riscv_relax_delete_bytes (abfd, sec, rel->r_offset + nop_bytes, + rel->r_addend - nop_bytes); +} + +/* Relax a section. Pass 0 shortens code sequences unless disabled. + Pass 1, which cannot be disabled, handles code alignment directives. */ + +static bfd_boolean +_bfd_riscv_relax_section (bfd *abfd, asection *sec, + struct bfd_link_info *info, + bfd_boolean *again) +{ + Elf_Internal_Shdr *symtab_hdr = &elf_symtab_hdr (abfd); + struct riscv_elf_link_hash_table *htab = riscv_elf_hash_table (info); + struct bfd_elf_section_data *data = elf_section_data (sec); + Elf_Internal_Rela *relocs; + bfd_boolean ret = FALSE; + unsigned int i; + unsigned int max_alignment; + + *again = FALSE; + + if (bfd_link_relocatable (info) + || sec->sec_flg0 + || (sec->flags & SEC_RELOC) == 0 + || sec->reloc_count == 0 + || (info->disable_target_specific_optimizations + && info->relax_pass == 0)) + return TRUE; + + /* Read this BFD's relocs if we haven't done so already. */ + if (data->relocs) + relocs = data->relocs; + else if (!(relocs = _bfd_elf_link_read_relocs (abfd, sec, NULL, NULL, + info->keep_memory))) + goto fail; + + max_alignment = _bfd_riscv_get_max_alignment (sec); + + /* Examine and consider relaxing each reloc. */ + for (i = 0; i < sec->reloc_count; i++) + { + asection *sym_sec; + Elf_Internal_Rela *rel = relocs + i; + typeof (&_bfd_riscv_relax_call) relax_func = NULL; + int type = ELFNN_R_TYPE (rel->r_info); + bfd_vma symval; + + if (info->relax_pass == 0) + { + if (type == R_RISCV_CALL || type == R_RISCV_CALL_PLT) + relax_func = _bfd_riscv_relax_call; + else if (type == R_RISCV_HI20 + || type == R_RISCV_LO12_I + || type == R_RISCV_LO12_S) + relax_func = _bfd_riscv_relax_lui; + else if (type == R_RISCV_TPREL_HI20 || type == R_RISCV_TPREL_ADD) + relax_func = _bfd_riscv_relax_tls_le; + } + else if (type == R_RISCV_ALIGN) + relax_func = _bfd_riscv_relax_align; + + if (!relax_func) + continue; + + data->relocs = relocs; + + /* Read this BFD's contents if we haven't done so already. */ + if (!data->this_hdr.contents + && !bfd_malloc_and_get_section (abfd, sec, &data->this_hdr.contents)) + goto fail; + + /* Read this BFD's symbols if we haven't done so already. */ + if (symtab_hdr->sh_info != 0 + && !symtab_hdr->contents + && !(symtab_hdr->contents = + (unsigned char *) bfd_elf_get_elf_syms (abfd, symtab_hdr, + symtab_hdr->sh_info, + 0, NULL, NULL, NULL))) + goto fail; + + /* Get the value of the symbol referred to by the reloc. */ + if (ELFNN_R_SYM (rel->r_info) < symtab_hdr->sh_info) + { + /* A local symbol. */ + Elf_Internal_Sym *isym = ((Elf_Internal_Sym *) symtab_hdr->contents + + ELFNN_R_SYM (rel->r_info)); + + if (isym->st_shndx == SHN_UNDEF) + sym_sec = sec, symval = sec_addr (sec) + rel->r_offset; + else + { + BFD_ASSERT (isym->st_shndx < elf_numsections (abfd)); + sym_sec = elf_elfsections (abfd)[isym->st_shndx]->bfd_section; + if (sec_addr (sym_sec) == 0) + continue; + symval = sec_addr (sym_sec) + isym->st_value; + } + } + else + { + unsigned long indx; + struct elf_link_hash_entry *h; + + indx = ELFNN_R_SYM (rel->r_info) - symtab_hdr->sh_info; + h = elf_sym_hashes (abfd)[indx]; + + while (h->root.type == bfd_link_hash_indirect + || h->root.type == bfd_link_hash_warning) + h = (struct elf_link_hash_entry *) h->root.u.i.link; + + if (h->plt.offset != MINUS_ONE) + symval = sec_addr (htab->elf.splt) + h->plt.offset; + else if (h->root.u.def.section->output_section == NULL + || (h->root.type != bfd_link_hash_defined + && h->root.type != bfd_link_hash_defweak)) + continue; + else + symval = sec_addr (h->root.u.def.section) + h->root.u.def.value; + + sym_sec = h->root.u.def.section; + } + + symval += rel->r_addend; + + if (!relax_func (abfd, sec, sym_sec, info, rel, symval, + max_alignment, again)) + goto fail; + } + + ret = TRUE; + +fail: + if (relocs != data->relocs) + free (relocs); + + return ret; +} + +#if ARCH_SIZE == 32 +# define PRSTATUS_SIZE 0 /* FIXME */ +# define PRSTATUS_OFFSET_PR_CURSIG 12 +# define PRSTATUS_OFFSET_PR_PID 24 +# define PRSTATUS_OFFSET_PR_REG 72 +# define ELF_GREGSET_T_SIZE 128 +# define PRPSINFO_SIZE 128 +# define PRPSINFO_OFFSET_PR_PID 16 +# define PRPSINFO_OFFSET_PR_FNAME 32 +# define PRPSINFO_OFFSET_PR_PSARGS 48 +#else +# define PRSTATUS_SIZE 376 +# define PRSTATUS_OFFSET_PR_CURSIG 12 +# define PRSTATUS_OFFSET_PR_PID 32 +# define PRSTATUS_OFFSET_PR_REG 112 +# define ELF_GREGSET_T_SIZE 256 +# define PRPSINFO_SIZE 136 +# define PRPSINFO_OFFSET_PR_PID 24 +# define PRPSINFO_OFFSET_PR_FNAME 40 +# define PRPSINFO_OFFSET_PR_PSARGS 56 +#endif + +/* Support for core dump NOTE sections. */ + +static bfd_boolean +riscv_elf_grok_prstatus (bfd *abfd, Elf_Internal_Note *note) +{ + switch (note->descsz) + { + default: + return FALSE; + + case PRSTATUS_SIZE: /* sizeof(struct elf_prstatus) on Linux/RISC-V. */ + /* pr_cursig */ + elf_tdata (abfd)->core->signal + = bfd_get_16 (abfd, note->descdata + PRSTATUS_OFFSET_PR_CURSIG); + + /* pr_pid */ + elf_tdata (abfd)->core->lwpid + = bfd_get_32 (abfd, note->descdata + PRSTATUS_OFFSET_PR_PID); + break; + } + + /* Make a ".reg/999" section. */ + return _bfd_elfcore_make_pseudosection (abfd, ".reg", ELF_GREGSET_T_SIZE, + note->descpos + PRSTATUS_OFFSET_PR_REG); +} + +static bfd_boolean +riscv_elf_grok_psinfo (bfd *abfd, Elf_Internal_Note *note) +{ + switch (note->descsz) + { + default: + return FALSE; + + case PRPSINFO_SIZE: /* sizeof(struct elf_prpsinfo) on Linux/RISC-V. */ + /* pr_pid */ + elf_tdata (abfd)->core->pid + = bfd_get_32 (abfd, note->descdata + PRPSINFO_OFFSET_PR_PID); + + /* pr_fname */ + elf_tdata (abfd)->core->program = _bfd_elfcore_strndup + (abfd, note->descdata + PRPSINFO_OFFSET_PR_FNAME, 16); + + /* pr_psargs */ + elf_tdata (abfd)->core->command = _bfd_elfcore_strndup + (abfd, note->descdata + PRPSINFO_OFFSET_PR_PSARGS, 80); + break; + } + + /* Note that for some reason, a spurious space is tacked + onto the end of the args in some (at least one anyway) + implementations, so strip it off if it exists. */ + + { + char *command = elf_tdata (abfd)->core->command; + int n = strlen (command); + + if (0 < n && command[n - 1] == ' ') + command[n - 1] = '\0'; + } + + return TRUE; +} + + +#define TARGET_LITTLE_SYM riscv_elfNN_vec +#define TARGET_LITTLE_NAME "elfNN-littleriscv" + +#define elf_backend_reloc_type_class riscv_reloc_type_class + +#define bfd_elfNN_bfd_reloc_name_lookup riscv_reloc_name_lookup +#define bfd_elfNN_bfd_link_hash_table_create riscv_elf_link_hash_table_create +#define bfd_elfNN_bfd_reloc_type_lookup riscv_reloc_type_lookup +#define bfd_elfNN_bfd_merge_private_bfd_data \ + _bfd_riscv_elf_merge_private_bfd_data + +#define elf_backend_copy_indirect_symbol riscv_elf_copy_indirect_symbol +#define elf_backend_create_dynamic_sections riscv_elf_create_dynamic_sections +#define elf_backend_check_relocs riscv_elf_check_relocs +#define elf_backend_adjust_dynamic_symbol riscv_elf_adjust_dynamic_symbol +#define elf_backend_size_dynamic_sections riscv_elf_size_dynamic_sections +#define elf_backend_relocate_section riscv_elf_relocate_section +#define elf_backend_finish_dynamic_symbol riscv_elf_finish_dynamic_symbol +#define elf_backend_finish_dynamic_sections riscv_elf_finish_dynamic_sections +#define elf_backend_gc_mark_hook riscv_elf_gc_mark_hook +#define elf_backend_gc_sweep_hook riscv_elf_gc_sweep_hook +#define elf_backend_plt_sym_val riscv_elf_plt_sym_val +#define elf_backend_grok_prstatus riscv_elf_grok_prstatus +#define elf_backend_grok_psinfo riscv_elf_grok_psinfo +#define elf_info_to_howto_rel NULL +#define elf_info_to_howto riscv_info_to_howto_rela +#define bfd_elfNN_bfd_relax_section _bfd_riscv_relax_section + +#define elf_backend_init_index_section _bfd_elf_init_1_index_section + +#define elf_backend_can_gc_sections 1 +#define elf_backend_can_refcount 1 +#define elf_backend_want_got_plt 1 +#define elf_backend_plt_readonly 1 +#define elf_backend_plt_alignment 4 +#define elf_backend_want_plt_sym 1 +#define elf_backend_got_header_size (ARCH_SIZE / 8) +#define elf_backend_rela_normal 1 +#define elf_backend_default_execstack 0 + +#include "elfNN-target.h" diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c new file mode 100644 index 0000000000..bd68fe4f14 --- /dev/null +++ b/bfd/elfxx-riscv.c @@ -0,0 +1,815 @@ +/* RISC-V-specific support for ELF. + Copyright 2011-2016 Free Software Foundation, Inc. + + Contributed by Andrew Waterman (andrew@sifive.com). + Based on TILE-Gx and MIPS targets. + + This file is part of BFD, the Binary File Descriptor library. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; see the file COPYING3. If not, + see . */ + +#include "sysdep.h" +#include "bfd.h" +#include "libbfd.h" +#include "elf-bfd.h" +#include "elf/riscv.h" +#include "opcode/riscv.h" +#include "libiberty.h" +#include "elfxx-riscv.h" +#include + +#define MINUS_ONE ((bfd_vma)0 - 1) + +/* The relocation table used for SHT_RELA sections. */ + +static reloc_howto_type howto_table[] = +{ + /* No relocation. */ + HOWTO (R_RISCV_NONE, /* type */ + 0, /* rightshift */ + 3, /* size */ + 0, /* bitsize */ + FALSE, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_dont, /* complain_on_overflow */ + bfd_elf_generic_reloc, /* special_function */ + "R_RISCV_NONE", /* name */ + FALSE, /* partial_inplace */ + 0, /* src_mask */ + 0, /* dst_mask */ + FALSE), /* pcrel_offset */ + + /* 32 bit relocation. */ + HOWTO (R_RISCV_32, /* type */ + 0, /* rightshift */ + 2, /* size */ + 32, /* bitsize */ + FALSE, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_dont, /* complain_on_overflow */ + bfd_elf_generic_reloc, /* special_function */ + "R_RISCV_32", /* name */ + FALSE, /* partial_inplace */ + 0, /* src_mask */ + 0xffffffff, /* dst_mask */ + FALSE), /* pcrel_offset */ + + /* 64 bit relocation. */ + HOWTO (R_RISCV_64, /* type */ + 0, /* rightshift */ + 4, /* size */ + 64, /* bitsize */ + FALSE, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_dont, /* complain_on_overflow */ + bfd_elf_generic_reloc, /* special_function */ + "R_RISCV_64", /* name */ + FALSE, /* partial_inplace */ + 0, /* src_mask */ + MINUS_ONE, /* dst_mask */ + FALSE), /* pcrel_offset */ + + /* Relocation against a local symbol in a shared object. */ + HOWTO (R_RISCV_RELATIVE, /* type */ + 0, /* rightshift */ + 2, /* size */ + 32, /* bitsize */ + FALSE, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_dont, /* complain_on_overflow */ + bfd_elf_generic_reloc, /* special_function */ + "R_RISCV_RELATIVE", /* name */ + FALSE, /* partial_inplace */ + 0, /* src_mask */ + 0xffffffff, /* dst_mask */ + FALSE), /* pcrel_offset */ + + HOWTO (R_RISCV_COPY, /* type */ + 0, /* rightshift */ + 0, /* this one is variable size */ + 0, /* bitsize */ + FALSE, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_bitfield, /* complain_on_overflow */ + bfd_elf_generic_reloc, /* special_function */ + "R_RISCV_COPY", /* name */ + FALSE, /* partial_inplace */ + 0x0, /* src_mask */ + 0x0, /* dst_mask */ + FALSE), /* pcrel_offset */ + + HOWTO (R_RISCV_JUMP_SLOT, /* type */ + 0, /* rightshift */ + 4, /* size */ + 64, /* bitsize */ + FALSE, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_bitfield, /* complain_on_overflow */ + bfd_elf_generic_reloc, /* special_function */ + "R_RISCV_JUMP_SLOT", /* name */ + FALSE, /* partial_inplace */ + 0x0, /* src_mask */ + 0x0, /* dst_mask */ + FALSE), /* pcrel_offset */ + + /* Dynamic TLS relocations. */ + HOWTO (R_RISCV_TLS_DTPMOD32, /* type */ + 0, /* rightshift */ + 4, /* size */ + 32, /* bitsize */ + FALSE, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_dont, /* complain_on_overflow */ + bfd_elf_generic_reloc, /* special_function */ + "R_RISCV_TLS_DTPMOD32", /* name */ + FALSE, /* partial_inplace */ + MINUS_ONE, /* src_mask */ + MINUS_ONE, /* dst_mask */ + FALSE), /* pcrel_offset */ + + HOWTO (R_RISCV_TLS_DTPMOD64, /* type */ + 0, /* rightshift */ + 4, /* size */ + 64, /* bitsize */ + FALSE, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_dont, /* complain_on_overflow */ + bfd_elf_generic_reloc, /* special_function */ + "R_RISCV_TLS_DTPMOD64", /* name */ + FALSE, /* partial_inplace */ + MINUS_ONE, /* src_mask */ + MINUS_ONE, /* dst_mask */ + FALSE), /* pcrel_offset */ + + HOWTO (R_RISCV_TLS_DTPREL32, /* type */ + 0, /* rightshift */ + 4, /* size */ + 32, /* bitsize */ + FALSE, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_dont, /* complain_on_overflow */ + bfd_elf_generic_reloc, /* special_function */ + "R_RISCV_TLS_DTPREL32", /* name */ + TRUE, /* partial_inplace */ + MINUS_ONE, /* src_mask */ + MINUS_ONE, /* dst_mask */ + FALSE), /* pcrel_offset */ + + HOWTO (R_RISCV_TLS_DTPREL64, /* type */ + 0, /* rightshift */ + 4, /* size */ + 64, /* bitsize */ + FALSE, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_dont, /* complain_on_overflow */ + bfd_elf_generic_reloc, /* special_function */ + "R_RISCV_TLS_DTPREL64", /* name */ + TRUE, /* partial_inplace */ + MINUS_ONE, /* src_mask */ + MINUS_ONE, /* dst_mask */ + FALSE), /* pcrel_offset */ + + HOWTO (R_RISCV_TLS_TPREL32, /* type */ + 0, /* rightshift */ + 2, /* size */ + 32, /* bitsize */ + FALSE, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_dont, /* complain_on_overflow */ + bfd_elf_generic_reloc, /* special_function */ + "R_RISCV_TLS_TPREL32", /* name */ + FALSE, /* partial_inplace */ + MINUS_ONE, /* src_mask */ + MINUS_ONE, /* dst_mask */ + FALSE), /* pcrel_offset */ + + HOWTO (R_RISCV_TLS_TPREL64, /* type */ + 0, /* rightshift */ + 4, /* size */ + 64, /* bitsize */ + FALSE, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_dont, /* complain_on_overflow */ + bfd_elf_generic_reloc, /* special_function */ + "R_RISCV_TLS_TPREL64", /* name */ + FALSE, /* partial_inplace */ + MINUS_ONE, /* src_mask */ + MINUS_ONE, /* dst_mask */ + FALSE), /* pcrel_offset */ + + /* Reserved for future relocs that the dynamic linker must understand. */ + EMPTY_HOWTO (12), + EMPTY_HOWTO (13), + EMPTY_HOWTO (14), + EMPTY_HOWTO (15), + + /* 12-bit PC-relative branch offset. */ + HOWTO (R_RISCV_BRANCH, /* type */ + 0, /* rightshift */ + 2, /* size */ + 32, /* bitsize */ + TRUE, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_signed, /* complain_on_overflow */ + bfd_elf_generic_reloc, /* special_function */ + "R_RISCV_BRANCH", /* name */ + FALSE, /* partial_inplace */ + 0, /* src_mask */ + ENCODE_SBTYPE_IMM (-1U), /* dst_mask */ + TRUE), /* pcrel_offset */ + + /* 20-bit PC-relative jump offset. */ + HOWTO (R_RISCV_JAL, /* type */ + 0, /* rightshift */ + 2, /* size */ + 32, /* bitsize */ + TRUE, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_dont, /* complain_on_overflow */ + /* This needs complex overflow + detection, because the upper 36 + bits must match the PC + 4. */ + bfd_elf_generic_reloc, /* special_function */ + "R_RISCV_JAL", /* name */ + FALSE, /* partial_inplace */ + 0, /* src_mask */ + ENCODE_UJTYPE_IMM (-1U), /* dst_mask */ + TRUE), /* pcrel_offset */ + + /* 32-bit PC-relative function call (AUIPC/JALR). */ + HOWTO (R_RISCV_CALL, /* type */ + 0, /* rightshift */ + 2, /* size */ + 64, /* bitsize */ + TRUE, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_dont, /* complain_on_overflow */ + bfd_elf_generic_reloc, /* special_function */ + "R_RISCV_CALL", /* name */ + FALSE, /* partial_inplace */ + 0, /* src_mask */ + ENCODE_UTYPE_IMM (-1U) | ((bfd_vma) ENCODE_ITYPE_IMM (-1U) << 32), + /* dst_mask */ + TRUE), /* pcrel_offset */ + + /* 32-bit PC-relative function call (AUIPC/JALR). */ + HOWTO (R_RISCV_CALL_PLT, /* type */ + 0, /* rightshift */ + 2, /* size */ + 64, /* bitsize */ + TRUE, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_dont, /* complain_on_overflow */ + bfd_elf_generic_reloc, /* special_function */ + "R_RISCV_CALL_PLT", /* name */ + FALSE, /* partial_inplace */ + 0, /* src_mask */ + ENCODE_UTYPE_IMM (-1U) | ((bfd_vma) ENCODE_ITYPE_IMM (-1U) << 32), + /* dst_mask */ + TRUE), /* pcrel_offset */ + + /* High 20 bits of 32-bit PC-relative GOT access. */ + HOWTO (R_RISCV_GOT_HI20, /* type */ + 0, /* rightshift */ + 2, /* size */ + 32, /* bitsize */ + TRUE, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_dont, /* complain_on_overflow */ + bfd_elf_generic_reloc, /* special_function */ + "R_RISCV_GOT_HI20", /* name */ + FALSE, /* partial_inplace */ + 0, /* src_mask */ + ENCODE_UTYPE_IMM (-1U), /* dst_mask */ + FALSE), /* pcrel_offset */ + + /* High 20 bits of 32-bit PC-relative TLS IE GOT access. */ + HOWTO (R_RISCV_TLS_GOT_HI20, /* type */ + 0, /* rightshift */ + 2, /* size */ + 32, /* bitsize */ + TRUE, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_dont, /* complain_on_overflow */ + bfd_elf_generic_reloc, /* special_function */ + "R_RISCV_TLS_GOT_HI20", /* name */ + FALSE, /* partial_inplace */ + 0, /* src_mask */ + ENCODE_UTYPE_IMM (-1U), /* dst_mask */ + FALSE), /* pcrel_offset */ + + /* High 20 bits of 32-bit PC-relative TLS GD GOT reference. */ + HOWTO (R_RISCV_TLS_GD_HI20, /* type */ + 0, /* rightshift */ + 2, /* size */ + 32, /* bitsize */ + TRUE, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_dont, /* complain_on_overflow */ + bfd_elf_generic_reloc, /* special_function */ + "R_RISCV_TLS_GD_HI20", /* name */ + FALSE, /* partial_inplace */ + 0, /* src_mask */ + ENCODE_UTYPE_IMM (-1U), /* dst_mask */ + FALSE), /* pcrel_offset */ + + /* High 20 bits of 32-bit PC-relative reference. */ + HOWTO (R_RISCV_PCREL_HI20, /* type */ + 0, /* rightshift */ + 2, /* size */ + 32, /* bitsize */ + TRUE, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_dont, /* complain_on_overflow */ + bfd_elf_generic_reloc, /* special_function */ + "R_RISCV_PCREL_HI20", /* name */ + FALSE, /* partial_inplace */ + 0, /* src_mask */ + ENCODE_UTYPE_IMM (-1U), /* dst_mask */ + TRUE), /* pcrel_offset */ + + /* Low 12 bits of a 32-bit PC-relative load or add. */ + HOWTO (R_RISCV_PCREL_LO12_I, /* type */ + 0, /* rightshift */ + 2, /* size */ + 32, /* bitsize */ + FALSE, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_dont, /* complain_on_overflow */ + bfd_elf_generic_reloc, /* special_function */ + "R_RISCV_PCREL_LO12_I", /* name */ + FALSE, /* partial_inplace */ + 0, /* src_mask */ + ENCODE_ITYPE_IMM (-1U), /* dst_mask */ + FALSE), /* pcrel_offset */ + + /* Low 12 bits of a 32-bit PC-relative store. */ + HOWTO (R_RISCV_PCREL_LO12_S, /* type */ + 0, /* rightshift */ + 2, /* size */ + 32, /* bitsize */ + FALSE, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_dont, /* complain_on_overflow */ + bfd_elf_generic_reloc, /* special_function */ + "R_RISCV_PCREL_LO12_S", /* name */ + FALSE, /* partial_inplace */ + 0, /* src_mask */ + ENCODE_STYPE_IMM (-1U), /* dst_mask */ + FALSE), /* pcrel_offset */ + + /* High 20 bits of 32-bit absolute address. */ + HOWTO (R_RISCV_HI20, /* type */ + 0, /* rightshift */ + 2, /* size */ + 32, /* bitsize */ + FALSE, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_dont, /* complain_on_overflow */ + bfd_elf_generic_reloc, /* special_function */ + "R_RISCV_HI20", /* name */ + FALSE, /* partial_inplace */ + 0, /* src_mask */ + ENCODE_UTYPE_IMM (-1U), /* dst_mask */ + FALSE), /* pcrel_offset */ + + /* High 12 bits of 32-bit load or add. */ + HOWTO (R_RISCV_LO12_I, /* type */ + 0, /* rightshift */ + 2, /* size */ + 32, /* bitsize */ + FALSE, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_dont, /* complain_on_overflow */ + bfd_elf_generic_reloc, /* special_function */ + "R_RISCV_LO12_I", /* name */ + FALSE, /* partial_inplace */ + 0, /* src_mask */ + ENCODE_ITYPE_IMM (-1U), /* dst_mask */ + FALSE), /* pcrel_offset */ + + /* High 12 bits of 32-bit store. */ + HOWTO (R_RISCV_LO12_S, /* type */ + 0, /* rightshift */ + 2, /* size */ + 32, /* bitsize */ + FALSE, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_dont, /* complain_on_overflow */ + bfd_elf_generic_reloc, /* special_function */ + "R_RISCV_LO12_S", /* name */ + FALSE, /* partial_inplace */ + 0, /* src_mask */ + ENCODE_STYPE_IMM (-1U), /* dst_mask */ + FALSE), /* pcrel_offset */ + + /* High 20 bits of TLS LE thread pointer offset. */ + HOWTO (R_RISCV_TPREL_HI20, /* type */ + 0, /* rightshift */ + 2, /* size */ + 32, /* bitsize */ + FALSE, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_signed, /* complain_on_overflow */ + bfd_elf_generic_reloc, /* special_function */ + "R_RISCV_TPREL_HI20", /* name */ + TRUE, /* partial_inplace */ + 0, /* src_mask */ + ENCODE_UTYPE_IMM (-1U), /* dst_mask */ + FALSE), /* pcrel_offset */ + + /* Low 12 bits of TLS LE thread pointer offset for loads and adds. */ + HOWTO (R_RISCV_TPREL_LO12_I, /* type */ + 0, /* rightshift */ + 2, /* size */ + 32, /* bitsize */ + FALSE, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_signed, /* complain_on_overflow */ + bfd_elf_generic_reloc, /* special_function */ + "R_RISCV_TPREL_LO12_I", /* name */ + FALSE, /* partial_inplace */ + 0, /* src_mask */ + ENCODE_ITYPE_IMM (-1U), /* dst_mask */ + FALSE), /* pcrel_offset */ + + /* Low 12 bits of TLS LE thread pointer offset for stores. */ + HOWTO (R_RISCV_TPREL_LO12_S, /* type */ + 0, /* rightshift */ + 2, /* size */ + 32, /* bitsize */ + FALSE, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_signed, /* complain_on_overflow */ + bfd_elf_generic_reloc, /* special_function */ + "R_RISCV_TPREL_LO12_S", /* name */ + FALSE, /* partial_inplace */ + 0, /* src_mask */ + ENCODE_STYPE_IMM (-1U), /* dst_mask */ + FALSE), /* pcrel_offset */ + + /* TLS LE thread pointer usage. */ + HOWTO (R_RISCV_TPREL_ADD, /* type */ + 0, /* rightshift */ + 2, /* size */ + 32, /* bitsize */ + FALSE, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_dont, /* complain_on_overflow */ + bfd_elf_generic_reloc, /* special_function */ + "R_RISCV_TPREL_ADD", /* name */ + TRUE, /* partial_inplace */ + 0, /* src_mask */ + 0, /* dst_mask */ + FALSE), /* pcrel_offset */ + + /* 8-bit in-place addition, for local label subtraction. */ + HOWTO (R_RISCV_ADD8, /* type */ + 0, /* rightshift */ + 0, /* size */ + 32, /* bitsize */ + FALSE, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_dont, /* complain_on_overflow */ + bfd_elf_generic_reloc, /* special_function */ + "R_RISCV_ADD8", /* name */ + FALSE, /* partial_inplace */ + 0, /* src_mask */ + MINUS_ONE, /* dst_mask */ + FALSE), /* pcrel_offset */ + + /* 16-bit in-place addition, for local label subtraction. */ + HOWTO (R_RISCV_ADD16, /* type */ + 0, /* rightshift */ + 1, /* size */ + 16, /* bitsize */ + FALSE, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_dont, /* complain_on_overflow */ + bfd_elf_generic_reloc, /* special_function */ + "R_RISCV_ADD16", /* name */ + FALSE, /* partial_inplace */ + 0, /* src_mask */ + MINUS_ONE, /* dst_mask */ + FALSE), /* pcrel_offset */ + + /* 32-bit in-place addition, for local label subtraction. */ + HOWTO (R_RISCV_ADD32, /* type */ + 0, /* rightshift */ + 2, /* size */ + 32, /* bitsize */ + FALSE, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_dont, /* complain_on_overflow */ + bfd_elf_generic_reloc, /* special_function */ + "R_RISCV_ADD32", /* name */ + FALSE, /* partial_inplace */ + 0, /* src_mask */ + MINUS_ONE, /* dst_mask */ + FALSE), /* pcrel_offset */ + + /* 64-bit in-place addition, for local label subtraction. */ + HOWTO (R_RISCV_ADD64, /* type */ + 0, /* rightshift */ + 4, /* size */ + 64, /* bitsize */ + FALSE, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_dont, /* complain_on_overflow */ + bfd_elf_generic_reloc, /* special_function */ + "R_RISCV_ADD64", /* name */ + FALSE, /* partial_inplace */ + 0, /* src_mask */ + MINUS_ONE, /* dst_mask */ + FALSE), /* pcrel_offset */ + + /* 8-bit in-place addition, for local label subtraction. */ + HOWTO (R_RISCV_SUB8, /* type */ + 0, /* rightshift */ + 0, /* size */ + 8, /* bitsize */ + FALSE, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_dont, /* complain_on_overflow */ + bfd_elf_generic_reloc, /* special_function */ + "R_RISCV_SUB8", /* name */ + FALSE, /* partial_inplace */ + 0, /* src_mask */ + MINUS_ONE, /* dst_mask */ + FALSE), /* pcrel_offset */ + + /* 16-bit in-place addition, for local label subtraction. */ + HOWTO (R_RISCV_SUB16, /* type */ + 0, /* rightshift */ + 1, /* size */ + 16, /* bitsize */ + FALSE, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_dont, /* complain_on_overflow */ + bfd_elf_generic_reloc, /* special_function */ + "R_RISCV_SUB16", /* name */ + FALSE, /* partial_inplace */ + 0, /* src_mask */ + MINUS_ONE, /* dst_mask */ + FALSE), /* pcrel_offset */ + + /* 32-bit in-place addition, for local label subtraction. */ + HOWTO (R_RISCV_SUB32, /* type */ + 0, /* rightshift */ + 2, /* size */ + 32, /* bitsize */ + FALSE, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_dont, /* complain_on_overflow */ + bfd_elf_generic_reloc, /* special_function */ + "R_RISCV_SUB32", /* name */ + FALSE, /* partial_inplace */ + 0, /* src_mask */ + MINUS_ONE, /* dst_mask */ + FALSE), /* pcrel_offset */ + + /* 64-bit in-place addition, for local label subtraction. */ + HOWTO (R_RISCV_SUB64, /* type */ + 0, /* rightshift */ + 4, /* size */ + 64, /* bitsize */ + FALSE, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_dont, /* complain_on_overflow */ + bfd_elf_generic_reloc, /* special_function */ + "R_RISCV_SUB64", /* name */ + FALSE, /* partial_inplace */ + 0, /* src_mask */ + MINUS_ONE, /* dst_mask */ + FALSE), /* pcrel_offset */ + + /* GNU extension to record C++ vtable hierarchy */ + HOWTO (R_RISCV_GNU_VTINHERIT, /* type */ + 0, /* rightshift */ + 4, /* size */ + 0, /* bitsize */ + FALSE, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_dont, /* complain_on_overflow */ + NULL, /* special_function */ + "R_RISCV_GNU_VTINHERIT", /* name */ + FALSE, /* partial_inplace */ + 0, /* src_mask */ + 0, /* dst_mask */ + FALSE), /* pcrel_offset */ + + /* GNU extension to record C++ vtable member usage */ + HOWTO (R_RISCV_GNU_VTENTRY, /* type */ + 0, /* rightshift */ + 4, /* size */ + 0, /* bitsize */ + FALSE, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_dont, /* complain_on_overflow */ + _bfd_elf_rel_vtable_reloc_fn, /* special_function */ + "R_RISCV_GNU_VTENTRY", /* name */ + FALSE, /* partial_inplace */ + 0, /* src_mask */ + 0, /* dst_mask */ + FALSE), /* pcrel_offset */ + + /* Indicates an alignment statement. The addend field encodes how many + bytes of NOPs follow the statement. The desired alignment is the + addend rounded up to the next power of two. */ + HOWTO (R_RISCV_ALIGN, /* type */ + 0, /* rightshift */ + 2, /* size */ + 0, /* bitsize */ + FALSE, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_dont, /* complain_on_overflow */ + bfd_elf_generic_reloc, /* special_function */ + "R_RISCV_ALIGN", /* name */ + FALSE, /* partial_inplace */ + 0, /* src_mask */ + 0, /* dst_mask */ + TRUE), /* pcrel_offset */ + + /* 8-bit PC-relative branch offset. */ + HOWTO (R_RISCV_RVC_BRANCH, /* type */ + 0, /* rightshift */ + 2, /* size */ + 32, /* bitsize */ + TRUE, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_signed, /* complain_on_overflow */ + bfd_elf_generic_reloc, /* special_function */ + "R_RISCV_RVC_BRANCH", /* name */ + FALSE, /* partial_inplace */ + 0, /* src_mask */ + ENCODE_RVC_B_IMM (-1U), /* dst_mask */ + TRUE), /* pcrel_offset */ + + /* 11-bit PC-relative jump offset. */ + HOWTO (R_RISCV_RVC_JUMP, /* type */ + 0, /* rightshift */ + 2, /* size */ + 32, /* bitsize */ + TRUE, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_dont, /* complain_on_overflow */ + /* This needs complex overflow + detection, because the upper 36 + bits must match the PC + 4. */ + bfd_elf_generic_reloc, /* special_function */ + "R_RISCV_RVC_JUMP", /* name */ + FALSE, /* partial_inplace */ + 0, /* src_mask */ + ENCODE_RVC_J_IMM (-1U), /* dst_mask */ + TRUE), /* pcrel_offset */ + + /* High 6 bits of 18-bit absolute address. */ + HOWTO (R_RISCV_RVC_LUI, /* type */ + 0, /* rightshift */ + 2, /* size */ + 32, /* bitsize */ + FALSE, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_dont, /* complain_on_overflow */ + bfd_elf_generic_reloc, /* special_function */ + "R_RISCV_RVC_LUI", /* name */ + FALSE, /* partial_inplace */ + 0, /* src_mask */ + ENCODE_RVC_IMM (-1U), /* dst_mask */ + FALSE), /* pcrel_offset */ + + /* High 12 bits of 32-bit load or add. */ + HOWTO (R_RISCV_GPREL_I, /* type */ + 0, /* rightshift */ + 2, /* size */ + 32, /* bitsize */ + FALSE, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_dont, /* complain_on_overflow */ + bfd_elf_generic_reloc, /* special_function */ + "R_RISCV_GPREL_I", /* name */ + FALSE, /* partial_inplace */ + 0, /* src_mask */ + ENCODE_ITYPE_IMM (-1U), /* dst_mask */ + FALSE), /* pcrel_offset */ + + /* High 12 bits of 32-bit store. */ + HOWTO (R_RISCV_GPREL_S, /* type */ + 0, /* rightshift */ + 2, /* size */ + 32, /* bitsize */ + FALSE, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_dont, /* complain_on_overflow */ + bfd_elf_generic_reloc, /* special_function */ + "R_RISCV_GPREL_S", /* name */ + FALSE, /* partial_inplace */ + 0, /* src_mask */ + ENCODE_STYPE_IMM (-1U), /* dst_mask */ + FALSE), /* pcrel_offset */ +}; + +/* A mapping from BFD reloc types to RISC-V ELF reloc types. */ + +struct elf_reloc_map +{ + bfd_reloc_code_real_type bfd_val; + enum elf_riscv_reloc_type elf_val; +}; + +static const struct elf_reloc_map riscv_reloc_map[] = +{ + { BFD_RELOC_NONE, R_RISCV_NONE }, + { BFD_RELOC_32, R_RISCV_32 }, + { BFD_RELOC_64, R_RISCV_64 }, + { BFD_RELOC_RISCV_ADD8, R_RISCV_ADD8 }, + { BFD_RELOC_RISCV_ADD16, R_RISCV_ADD16 }, + { BFD_RELOC_RISCV_ADD32, R_RISCV_ADD32 }, + { BFD_RELOC_RISCV_ADD64, R_RISCV_ADD64 }, + { BFD_RELOC_RISCV_SUB8, R_RISCV_SUB8 }, + { BFD_RELOC_RISCV_SUB16, R_RISCV_SUB16 }, + { BFD_RELOC_RISCV_SUB32, R_RISCV_SUB32 }, + { BFD_RELOC_RISCV_SUB64, R_RISCV_SUB64 }, + { BFD_RELOC_CTOR, R_RISCV_64 }, + { BFD_RELOC_12_PCREL, R_RISCV_BRANCH }, + { BFD_RELOC_RISCV_HI20, R_RISCV_HI20 }, + { BFD_RELOC_RISCV_LO12_I, R_RISCV_LO12_I }, + { BFD_RELOC_RISCV_LO12_S, R_RISCV_LO12_S }, + { BFD_RELOC_RISCV_PCREL_LO12_I, R_RISCV_PCREL_LO12_I }, + { BFD_RELOC_RISCV_PCREL_LO12_S, R_RISCV_PCREL_LO12_S }, + { BFD_RELOC_RISCV_CALL, R_RISCV_CALL }, + { BFD_RELOC_RISCV_CALL_PLT, R_RISCV_CALL_PLT }, + { BFD_RELOC_RISCV_PCREL_HI20, R_RISCV_PCREL_HI20 }, + { BFD_RELOC_RISCV_JMP, R_RISCV_JAL }, + { BFD_RELOC_RISCV_GOT_HI20, R_RISCV_GOT_HI20 }, + { BFD_RELOC_RISCV_TLS_DTPMOD32, R_RISCV_TLS_DTPMOD32 }, + { BFD_RELOC_RISCV_TLS_DTPREL32, R_RISCV_TLS_DTPREL32 }, + { BFD_RELOC_RISCV_TLS_DTPMOD64, R_RISCV_TLS_DTPMOD64 }, + { BFD_RELOC_RISCV_TLS_DTPREL64, R_RISCV_TLS_DTPREL64 }, + { BFD_RELOC_RISCV_TLS_TPREL32, R_RISCV_TLS_TPREL32 }, + { BFD_RELOC_RISCV_TLS_TPREL64, R_RISCV_TLS_TPREL64 }, + { BFD_RELOC_RISCV_TPREL_HI20, R_RISCV_TPREL_HI20 }, + { BFD_RELOC_RISCV_TPREL_ADD, R_RISCV_TPREL_ADD }, + { BFD_RELOC_RISCV_TPREL_LO12_S, R_RISCV_TPREL_LO12_S }, + { BFD_RELOC_RISCV_TPREL_LO12_I, R_RISCV_TPREL_LO12_I }, + { BFD_RELOC_RISCV_TLS_GOT_HI20, R_RISCV_TLS_GOT_HI20 }, + { BFD_RELOC_RISCV_TLS_GD_HI20, R_RISCV_TLS_GD_HI20 }, + { BFD_RELOC_RISCV_ALIGN, R_RISCV_ALIGN }, + { BFD_RELOC_RISCV_RVC_BRANCH, R_RISCV_RVC_BRANCH }, + { BFD_RELOC_RISCV_RVC_JUMP, R_RISCV_RVC_JUMP }, + { BFD_RELOC_RISCV_RVC_LUI, R_RISCV_RVC_LUI }, + { BFD_RELOC_RISCV_GPREL_I, R_RISCV_GPREL_I }, + { BFD_RELOC_RISCV_GPREL_S, R_RISCV_GPREL_S }, +}; + +/* Given a BFD reloc type, return a howto structure. */ + +reloc_howto_type * +riscv_reloc_type_lookup (bfd *abfd ATTRIBUTE_UNUSED, + bfd_reloc_code_real_type code) +{ + unsigned int i; + + for (i = 0; i < ARRAY_SIZE (riscv_reloc_map); i++) + if (riscv_reloc_map[i].bfd_val == code) + return &howto_table[(int) riscv_reloc_map[i].elf_val]; + + bfd_set_error (bfd_error_bad_value); + return NULL; +} + +reloc_howto_type * +riscv_reloc_name_lookup (bfd *abfd ATTRIBUTE_UNUSED, const char *r_name) +{ + unsigned int i; + + for (i = 0; i < ARRAY_SIZE (howto_table); i++) + if (howto_table[i].name && strcasecmp (howto_table[i].name, r_name) == 0) + return &howto_table[i]; + + return NULL; +} + +reloc_howto_type * +riscv_elf_rtype_to_howto (unsigned int r_type) +{ + if (r_type >= ARRAY_SIZE (howto_table)) + { + (*_bfd_error_handler) (_("unrecognized relocation (0x%x)"), r_type); + bfd_set_error (bfd_error_bad_value); + return NULL; + } + return &howto_table[r_type]; +} diff --git a/bfd/elfxx-riscv.h b/bfd/elfxx-riscv.h new file mode 100644 index 0000000000..28600e8e60 --- /dev/null +++ b/bfd/elfxx-riscv.h @@ -0,0 +1,33 @@ +/* RISC-V ELF specific backend routines. + Copyright 2011-2016 Free Software Foundation, Inc. + + Contributed by Andrew Waterman (andrew@sifive.com). + Based on MIPS target. + + This file is part of BFD, the Binary File Descriptor library. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; see the file COPYING3. If not, + see . */ + +#include "elf/common.h" +#include "elf/internal.h" + +extern reloc_howto_type * +riscv_reloc_name_lookup (bfd *, const char *); + +extern reloc_howto_type * +riscv_reloc_type_lookup (bfd *, bfd_reloc_code_real_type); + +extern reloc_howto_type * +riscv_elf_rtype_to_howto (unsigned int r_type); diff --git a/bfd/libbfd.h b/bfd/libbfd.h index 83ffc6a9d5..5ec39939c3 100644 --- a/bfd/libbfd.h +++ b/bfd/libbfd.h @@ -2166,6 +2166,44 @@ static const char *const bfd_reloc_code_real_names[] = { "@@uninitialized@@", "BFD_RELOC_AVR_LDS_STS_16", "BFD_RELOC_AVR_PORT6", "BFD_RELOC_AVR_PORT5", + "BFD_RELOC_RISCV_HI20", + "BFD_RELOC_RISCV_PCREL_HI20", + "BFD_RELOC_RISCV_PCREL_LO12_I", + "BFD_RELOC_RISCV_PCREL_LO12_S", + "BFD_RELOC_RISCV_LO12_I", + "BFD_RELOC_RISCV_LO12_S", + "BFD_RELOC_RISCV_GPREL12_I", + "BFD_RELOC_RISCV_GPREL12_S", + "BFD_RELOC_RISCV_TPREL_HI20", + "BFD_RELOC_RISCV_TPREL_LO12_I", + "BFD_RELOC_RISCV_TPREL_LO12_S", + "BFD_RELOC_RISCV_TPREL_ADD", + "BFD_RELOC_RISCV_CALL", + "BFD_RELOC_RISCV_CALL_PLT", + "BFD_RELOC_RISCV_ADD8", + "BFD_RELOC_RISCV_ADD16", + "BFD_RELOC_RISCV_ADD32", + "BFD_RELOC_RISCV_ADD64", + "BFD_RELOC_RISCV_SUB8", + "BFD_RELOC_RISCV_SUB16", + "BFD_RELOC_RISCV_SUB32", + "BFD_RELOC_RISCV_SUB64", + "BFD_RELOC_RISCV_GOT_HI20", + "BFD_RELOC_RISCV_TLS_GOT_HI20", + "BFD_RELOC_RISCV_TLS_GD_HI20", + "BFD_RELOC_RISCV_JMP", + "BFD_RELOC_RISCV_TLS_DTPMOD32", + "BFD_RELOC_RISCV_TLS_DTPREL32", + "BFD_RELOC_RISCV_TLS_DTPMOD64", + "BFD_RELOC_RISCV_TLS_DTPREL64", + "BFD_RELOC_RISCV_TLS_TPREL32", + "BFD_RELOC_RISCV_TLS_TPREL64", + "BFD_RELOC_RISCV_ALIGN", + "BFD_RELOC_RISCV_RVC_BRANCH", + "BFD_RELOC_RISCV_RVC_JUMP", + "BFD_RELOC_RISCV_RVC_LUI", + "BFD_RELOC_RISCV_GPREL_I", + "BFD_RELOC_RISCV_GPREL_S", "BFD_RELOC_RL78_NEG8", "BFD_RELOC_RL78_NEG16", "BFD_RELOC_RL78_NEG24", diff --git a/bfd/reloc.c b/bfd/reloc.c index 6ee3a4e04f..7c67eebacb 100644 --- a/bfd/reloc.c +++ b/bfd/reloc.c @@ -5047,6 +5047,86 @@ ENUM ENUMDOC This is a 5 bit reloc for the AVR that stores an I/O register number for the SBIC, SBIS, SBI and CBI instructions + +ENUM + BFD_RELOC_RISCV_HI20 +ENUMX + BFD_RELOC_RISCV_PCREL_HI20 +ENUMX + BFD_RELOC_RISCV_PCREL_LO12_I +ENUMX + BFD_RELOC_RISCV_PCREL_LO12_S +ENUMX + BFD_RELOC_RISCV_LO12_I +ENUMX + BFD_RELOC_RISCV_LO12_S +ENUMX + BFD_RELOC_RISCV_GPREL12_I +ENUMX + BFD_RELOC_RISCV_GPREL12_S +ENUMX + BFD_RELOC_RISCV_TPREL_HI20 +ENUMX + BFD_RELOC_RISCV_TPREL_LO12_I +ENUMX + BFD_RELOC_RISCV_TPREL_LO12_S +ENUMX + BFD_RELOC_RISCV_TPREL_ADD +ENUMX + BFD_RELOC_RISCV_CALL +ENUMX + BFD_RELOC_RISCV_CALL_PLT +ENUMX + BFD_RELOC_RISCV_ADD8 +ENUMX + BFD_RELOC_RISCV_ADD16 +ENUMX + BFD_RELOC_RISCV_ADD32 +ENUMX + BFD_RELOC_RISCV_ADD64 +ENUMX + BFD_RELOC_RISCV_SUB8 +ENUMX + BFD_RELOC_RISCV_SUB16 +ENUMX + BFD_RELOC_RISCV_SUB32 +ENUMX + BFD_RELOC_RISCV_SUB64 +ENUMX + BFD_RELOC_RISCV_GOT_HI20 +ENUMX + BFD_RELOC_RISCV_TLS_GOT_HI20 +ENUMX + BFD_RELOC_RISCV_TLS_GD_HI20 +ENUMX + BFD_RELOC_RISCV_JMP +ENUMX + BFD_RELOC_RISCV_TLS_DTPMOD32 +ENUMX + BFD_RELOC_RISCV_TLS_DTPREL32 +ENUMX + BFD_RELOC_RISCV_TLS_DTPMOD64 +ENUMX + BFD_RELOC_RISCV_TLS_DTPREL64 +ENUMX + BFD_RELOC_RISCV_TLS_TPREL32 +ENUMX + BFD_RELOC_RISCV_TLS_TPREL64 +ENUMX + BFD_RELOC_RISCV_ALIGN +ENUMX + BFD_RELOC_RISCV_RVC_BRANCH +ENUMX + BFD_RELOC_RISCV_RVC_JUMP +ENUMX + BFD_RELOC_RISCV_RVC_LUI +ENUMX + BFD_RELOC_RISCV_GPREL_I +ENUMX + BFD_RELOC_RISCV_GPREL_S +ENUMDOC + RISC-V relocations. + ENUM BFD_RELOC_RL78_NEG8 ENUMX diff --git a/bfd/targets.c b/bfd/targets.c index a0fd7dfef4..bc61c0228f 100644 --- a/bfd/targets.c +++ b/bfd/targets.c @@ -799,6 +799,8 @@ extern const bfd_target powerpc_pe_le_vec; extern const bfd_target powerpc_pei_vec; extern const bfd_target powerpc_pei_le_vec; extern const bfd_target powerpc_xcoff_vec; +extern const bfd_target riscv_elf32_vec; +extern const bfd_target riscv_elf64_vec; extern const bfd_target rl78_elf32_vec; extern const bfd_target rs6000_xcoff64_vec; extern const bfd_target rs6000_xcoff64_aix_vec; @@ -1303,6 +1305,10 @@ static const bfd_target * const _bfd_target_vector[] = &powerpc_xcoff_vec, #endif + &riscv_elf32_vec, +#ifdef BFD64 + &riscv_elf64_vec, +#endif &rl78_elf32_vec, #ifdef BFD64 diff --git a/binutils/ChangeLog b/binutils/ChangeLog index ac2f1c5680..9b720d95e1 100644 --- a/binutils/ChangeLog +++ b/binutils/ChangeLog @@ -1,3 +1,17 @@ +2016-11-01 Palmer Dabbelt + Andrew Waterman + + Add support for RISC-V architecture. + * readelf.c (guess_is_rela): Add EM_RISCV. + (get_machine_name): Likewise. + (dump_relocations): Add support for riscv relocations. + (get_machine_flags): Add support for riscv flags. + (is_32bit_abs_reloc): Add R_RISCV_32. + (is_64bit_abs_reloc): Add R_RISCV_64. + (is_none_reloc): Add R_RISCV_NONE. + * testsuite/binutils-all/objdump.exp (cpus_expected): Add riscv. + Expect the debug_ranges test to fail. + 2016-10-17 Nick Clifton * readelf.c (apply_relocations): Fail if the symbol table section diff --git a/binutils/readelf.c b/binutils/readelf.c index 69942cf711..114486cc98 100644 --- a/binutils/readelf.c +++ b/binutils/readelf.c @@ -124,6 +124,7 @@ #include "elf/metag.h" #include "elf/microblaze.h" #include "elf/mips.h" +#include "elf/riscv.h" #include "elf/mmix.h" #include "elf/mn10200.h" #include "elf/mn10300.h" @@ -775,6 +776,7 @@ guess_is_rela (unsigned int e_machine) case EM_OR1K: case EM_PPC64: case EM_PPC: + case EM_RISCV: case EM_RL78: case EM_RX: case EM_S390: @@ -1314,6 +1316,10 @@ dump_relocations (FILE * file, rtype = elf_mips_reloc_type (type); break; + case EM_RISCV: + rtype = elf_riscv_reloc_type (type); + break; + case EM_ALPHA: rtype = elf_alpha_reloc_type (type); break; @@ -2327,6 +2333,7 @@ get_machine_name (unsigned e_machine) case EM_CR16: case EM_MICROBLAZE: case EM_MICROBLAZE_OLD: return "Xilinx MicroBlaze"; + case EM_RISCV: return "RISC-V"; case EM_RL78: return "Renesas RL78"; case EM_RX: return "Renesas RX"; case EM_METAG: return "Imagination Technologies Meta processor architecture"; @@ -2363,7 +2370,6 @@ get_machine_name (unsigned e_machine) case EM_CSR_KALIMBA: return "CSR Kalimba architecture family"; case EM_Z80: return "Zilog Z80"; case EM_AMDGPU: return "AMD GPU architecture"; - case EM_RISCV: return "RISC-V"; default: snprintf (buff, sizeof (buff), _(": 0x%x"), e_machine); return buff; @@ -3308,6 +3314,13 @@ get_machine_flags (unsigned e_flags, unsigned e_machine) decode_NDS32_machine_flags (e_flags, buf, sizeof buf); break; + case EM_RISCV: + if (e_flags & EF_RISCV_RVC) + strcat (buf, ", RVC"); + if (e_flags & EF_RISCV_SOFT_FLOAT) + strcat (buf, ", soft-float ABI"); + break; + case EM_SH: switch ((e_flags & EF_SH_MACH_MASK)) { @@ -11788,6 +11801,8 @@ is_32bit_abs_reloc (unsigned int reloc_type) return reloc_type == 1; /* R_PPC64_ADDR32. */ case EM_PPC: return reloc_type == 1; /* R_PPC_ADDR32. */ + case EM_RISCV: + return reloc_type == 1; /* R_RISCV_32. */ case EM_RL78: return reloc_type == 1; /* R_RL78_DIR32. */ case EM_RX: @@ -11941,6 +11956,8 @@ is_64bit_abs_reloc (unsigned int reloc_type) return reloc_type == 80; /* R_PARISC_DIR64. */ case EM_PPC64: return reloc_type == 38; /* R_PPC64_ADDR64. */ + case EM_RISCV: + return reloc_type == 2; /* R_RISCV_64. */ case EM_SPARC32PLUS: case EM_SPARCV9: case EM_SPARC: @@ -12112,6 +12129,7 @@ is_none_reloc (unsigned int reloc_type) case EM_PARISC: /* R_PARISC_NONE. */ case EM_PPC64: /* R_PPC64_NONE. */ case EM_PPC: /* R_PPC_NONE. */ + case EM_RISCV: /* R_RISCV_NONE. */ case EM_S390: /* R_390_NONE. */ case EM_S390_OLD: case EM_SH: /* R_SH_NONE. */ diff --git a/binutils/testsuite/binutils-all/objdump.exp b/binutils/testsuite/binutils-all/objdump.exp index f097a7e071..377c5b1de7 100644 --- a/binutils/testsuite/binutils-all/objdump.exp +++ b/binutils/testsuite/binutils-all/objdump.exp @@ -38,7 +38,7 @@ lappend cpus_expected aarch64 alpha arc ARC700 ARCv2 arm cris lappend cpus_expected d10v d30v fr30 fr500 fr550 h8 hppa i386 i860 i960 iamcu ip2022 lappend cpus_expected m16c m32c m32r m68hc11 m68hc12 m68k m88k MCore mep c5 h1 MicroBlaze lappend cpus_expected mips mn10200 mn10300 ms1 msp MSP430 nds32 n1h_v3 ns32k -lappend cpus_expected or1k or1knd pj powerpc pyramid romp rs6000 s390 sh sparc +lappend cpus_expected or1k or1knd pj powerpc pyramid riscv romp rs6000 s390 sh sparc lappend cpus_expected tahoe tic54x tic80 tilegx tms320c30 tms320c4x tms320c54x lappend cpus_expected v850 vax we32k x86-64 xscale xtensa z8k z8001 z8002 @@ -265,7 +265,7 @@ if { ![is_elf_format] } then { send_log "\n" } - setup_xfail "msp430-*-*" "nds32*-*-*" + setup_xfail "msp430-*-*" "nds32*-*-*" "riscv*-*-*" if { [regexp_diff objdump.out $srcdir/$subdir/dw2-ranges.W] } then { fail "objdump -W for debug_ranges" } else { diff --git a/gas/ChangeLog b/gas/ChangeLog index 05febd74a4..8eabfd53c2 100644 --- a/gas/ChangeLog +++ b/gas/ChangeLog @@ -1,3 +1,24 @@ +2016-11-01 Palmer Dabbelt + Andrew Waterman + + Add support for RISC-V architecture. + * Makefile.am: Add riscv files. + * Makefile.in: Regenerate. + * NEWS: Mention the support for this architecture. + * configure.in: Define a default architecture. + * configure: Regenerate. + * configure.tgt: Add entries for riscv. + * doc/as.texinfo: Likewise. + * testsuite/gas/all/gas.exp: Expect the redef tests to fail. + * testsuite/gas/elf/elf.exp: Expect the groupauto tests to fail. + * config/tc-riscv.c: New file. + * config/tc-riscv.h: New file. + * doc/c-riscv.texi: New file. + * testsuite/gas/riscv: New directory. + * testsuite/gas/riscv/riscv.exp: New file. + * testsuite/gas/riscv/t_insns.d: New file. + * testsuite/gas/riscv/t_insns.s: New file. + 2016-10-27 Andrew Burgess * config/tc-arc.c (arc_target): Delete. diff --git a/gas/Makefile.am b/gas/Makefile.am index 6fa32ea05f..cdaf9f5a16 100644 --- a/gas/Makefile.am +++ b/gas/Makefile.am @@ -177,6 +177,7 @@ TARGET_CPU_CFILES = \ config/tc-pdp11.c \ config/tc-pj.c \ config/tc-ppc.c \ + config/tc-riscv.c \ config/tc-rl78.c \ config/tc-rx.c \ config/tc-s390.c \ @@ -250,6 +251,7 @@ TARGET_CPU_HFILES = \ config/tc-pdp11.h \ config/tc-pj.h \ config/tc-ppc.h \ + config/tc-riscv.h \ config/tc-rl78.h \ config/tc-rx.h \ config/tc-s390.h \ diff --git a/gas/Makefile.in b/gas/Makefile.in index 5b3c223816..84f746dd1e 100644 --- a/gas/Makefile.in +++ b/gas/Makefile.in @@ -472,6 +472,7 @@ TARGET_CPU_CFILES = \ config/tc-pdp11.c \ config/tc-pj.c \ config/tc-ppc.c \ + config/tc-riscv.c \ config/tc-rl78.c \ config/tc-rx.c \ config/tc-s390.c \ @@ -545,6 +546,7 @@ TARGET_CPU_HFILES = \ config/tc-pdp11.h \ config/tc-pj.h \ config/tc-ppc.h \ + config/tc-riscv.h \ config/tc-rl78.h \ config/tc-rx.h \ config/tc-s390.h \ @@ -903,6 +905,7 @@ distclean-compile: @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/tc-pdp11.Po@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/tc-pj.Po@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/tc-ppc.Po@am__quote@ +@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/tc-riscv.Po@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/tc-rl78.Po@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/tc-rx.Po@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/tc-s390.Po@am__quote@ @@ -1623,6 +1626,20 @@ tc-ppc.obj: config/tc-ppc.c @AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@ @am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) -c -o tc-ppc.obj `if test -f 'config/tc-ppc.c'; then $(CYGPATH_W) 'config/tc-ppc.c'; else $(CYGPATH_W) '$(srcdir)/config/tc-ppc.c'; fi` +tc-riscv.o: config/tc-riscv.c +@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) -MT tc-riscv.o -MD -MP -MF $(DEPDIR)/tc-riscv.Tpo -c -o tc-riscv.o `test -f 'config/tc-riscv.c' || echo '$(srcdir)/'`config/tc-riscv.c +@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/tc-riscv.Tpo $(DEPDIR)/tc-riscv.Po +@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='config/tc-riscv.c' object='tc-riscv.o' libtool=no @AMDEPBACKSLASH@ +@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@ +@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) -c -o tc-riscv.o `test -f 'config/tc-riscv.c' || echo '$(srcdir)/'`config/tc-riscv.c + +tc-riscv.obj: config/tc-riscv.c +@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) -MT tc-riscv.obj -MD -MP -MF $(DEPDIR)/tc-riscv.Tpo -c -o tc-riscv.obj `if test -f 'config/tc-riscv.c'; then $(CYGPATH_W) 'config/tc-riscv.c'; else $(CYGPATH_W) '$(srcdir)/config/tc-riscv.c'; fi` +@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/tc-riscv.Tpo $(DEPDIR)/tc-riscv.Po +@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='config/tc-riscv.c' object='tc-riscv.obj' libtool=no @AMDEPBACKSLASH@ +@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@ +@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) -c -o tc-riscv.obj `if test -f 'config/tc-riscv.c'; then $(CYGPATH_W) 'config/tc-riscv.c'; else $(CYGPATH_W) '$(srcdir)/config/tc-riscv.c'; fi` + tc-rl78.o: config/tc-rl78.c @am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) -MT tc-rl78.o -MD -MP -MF $(DEPDIR)/tc-rl78.Tpo -c -o tc-rl78.o `test -f 'config/tc-rl78.c' || echo '$(srcdir)/'`config/tc-rl78.c @am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/tc-rl78.Tpo $(DEPDIR)/tc-rl78.Po diff --git a/gas/NEWS b/gas/NEWS index 2dd2245d6e..25ad9ab371 100644 --- a/gas/NEWS +++ b/gas/NEWS @@ -1,5 +1,7 @@ -*- text -*- +* Add support for the RISC-V architecture. + Changes in 2.27: * Default to --enable-compressed-debug-sections=gas for Linux/x86 targets. diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c new file mode 100644 index 0000000000..592c95a47f --- /dev/null +++ b/gas/config/tc-riscv.c @@ -0,0 +1,2408 @@ +/* tc-riscv.c -- RISC-V assembler + Copyright 2011-2016 Free Software Foundation, Inc. + + Contributed by Andrew Waterman (andrew@sifive.com). + Based on MIPS target. + + This file is part of GAS. + + GAS is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. + + GAS is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; see the file COPYING3. If not, + see . */ + +#include "as.h" +#include "config.h" +#include "subsegs.h" +#include "safe-ctype.h" + +#include "itbl-ops.h" +#include "dwarf2dbg.h" +#include "dw2gencfi.h" + +#include "elf/riscv.h" +#include "opcode/riscv.h" + +#include + +/* Information about an instruction, including its format, operands + and fixups. */ +struct riscv_cl_insn +{ + /* The opcode's entry in riscv_opcodes. */ + const struct riscv_opcode *insn_mo; + + /* The encoded instruction bits. */ + insn_t insn_opcode; + + /* The frag that contains the instruction. */ + struct frag *frag; + + /* The offset into FRAG of the first instruction byte. */ + long where; + + /* The relocs associated with the instruction, if any. */ + fixS *fixp; +}; + +#ifndef DEFAULT_ARCH +#define DEFAULT_ARCH "riscv64" +#endif + +static const char default_arch[] = DEFAULT_ARCH; + +unsigned xlen = 0; /* width of an x-register */ + +#define LOAD_ADDRESS_INSN (xlen == 64 ? "ld" : "lw") +#define ADD32_INSN (xlen == 64 ? "addiw" : "addi") + +static unsigned elf_flags = 0; + +/* This is the set of options which the .option pseudo-op may modify. */ + +struct riscv_set_options +{ + int pic; /* Generate position-independent code. */ + int rvc; /* Generate RVC code. */ +}; + +static struct riscv_set_options riscv_opts = +{ + 0, /* pic */ + 0, /* rvc */ +}; + +static void +riscv_set_rvc (bfd_boolean rvc_value) +{ + if (rvc_value) + elf_flags |= EF_RISCV_RVC; + + riscv_opts.rvc = rvc_value; +} + +struct riscv_subset +{ + const char *name; + + struct riscv_subset *next; +}; + +static struct riscv_subset *riscv_subsets; + +static bfd_boolean +riscv_subset_supports (const char *feature) +{ + struct riscv_subset *s; + char *p; + unsigned xlen_required = strtoul (feature, &p, 10); + + if (xlen_required && xlen != xlen_required) + return FALSE; + + for (s = riscv_subsets; s != NULL; s = s->next) + if (strcasecmp (s->name, p) == 0) + return TRUE; + + return FALSE; +} + +static void +riscv_add_subset (const char *subset) +{ + struct riscv_subset *s = xmalloc (sizeof *s); + + s->name = xstrdup (subset); + s->next = riscv_subsets; + riscv_subsets = s; +} + +/* Set which ISA and extensions are available. Formally, ISA strings must + begin with RV32 or RV64, but we allow the prefix to be omitted. + + FIXME: Version numbers are not supported yet. */ +static void +riscv_set_arch (const char *p) +{ + const char *all_subsets = "IMAFDC"; + const char *extension = NULL; + int rvc = 0; + int i; + + if (strncasecmp (p, "RV32", 4) == 0) + { + xlen = 32; + p += 4; + } + else if (strncasecmp (p, "RV64", 4) == 0) + { + xlen = 64; + p += 4; + } + else if (strncasecmp (p, "RV", 2) == 0) + p += 2; + + switch (TOUPPER(*p)) + { + case 'I': + break; + + case 'G': + p++; + /* Fall through. */ + + case '\0': + for (i = 0; all_subsets[i] != '\0'; i++) + { + const char subset[] = {all_subsets[i], '\0'}; + riscv_add_subset (subset); + } + break; + + default: + as_fatal ("`I' must be the first ISA subset name specified (got %c)", + *p); + } + + while (*p) + { + if (TOUPPER(*p) == 'X') + { + char *subset = xstrdup (p), *q = subset; + + while (*++q != '\0' && *q != '_') + ; + *q = '\0'; + + if (extension) + as_fatal ("only one eXtension is supported (found %s and %s)", + extension, subset); + extension = subset; + riscv_add_subset (subset); + p += strlen (subset); + free (subset); + } + else if (*p == '_') + p++; + else if ((all_subsets = strchr (all_subsets, *p)) != NULL) + { + const char subset[] = {*p, 0}; + riscv_add_subset (subset); + if (TOUPPER(*p) == 'C') + rvc = 1; + all_subsets++; + p++; + } + else + as_fatal ("unsupported ISA subset %c", *p); + } + + if (rvc) + { + /* Override -m[no-]rvc setting if C was explicitly listed. */ + riscv_set_rvc (TRUE); + } + else + { + /* Add RVC anyway. -m[no-]rvc toggles its availability. */ + riscv_add_subset ("C"); + } +} + +/* Handle of the OPCODE hash table. */ +static struct hash_control *op_hash = NULL; + +/* This array holds the chars that always start a comment. If the + pre-processor is disabled, these aren't very useful */ +const char comment_chars[] = "#"; + +/* This array holds the chars that only start a comment at the beginning of + a line. If the line seems to have the form '# 123 filename' + .line and .file directives will appear in the pre-processed output */ +/* Note that input_file.c hand checks for '#' at the beginning of the + first line of the input file. This is because the compiler outputs + #NO_APP at the beginning of its output. */ +/* Also note that C style comments are always supported. */ +const char line_comment_chars[] = "#"; + +/* This array holds machine specific line separator characters. */ +const char line_separator_chars[] = ";"; + +/* Chars that can be used to separate mant from exp in floating point nums */ +const char EXP_CHARS[] = "eE"; + +/* Chars that mean this number is a floating point constant */ +/* As in 0f12.456 */ +/* or 0d1.2345e12 */ +const char FLT_CHARS[] = "rRsSfFdDxXpP"; + +/* Macros for encoding relaxation state for RVC branches and far jumps. */ +#define RELAX_BRANCH_ENCODE(uncond, rvc, length) \ + ((relax_substateT) \ + (0xc0000000 \ + | ((uncond) ? 1 : 0) \ + | ((rvc) ? 2 : 0) \ + | ((length) << 2))) +#define RELAX_BRANCH_P(i) (((i) & 0xf0000000) == 0xc0000000) +#define RELAX_BRANCH_LENGTH(i) (((i) >> 2) & 0xF) +#define RELAX_BRANCH_RVC(i) (((i) & 2) != 0) +#define RELAX_BRANCH_UNCOND(i) (((i) & 1) != 0) + +/* Is the given value a sign-extended 32-bit value? */ +#define IS_SEXT_32BIT_NUM(x) \ + (((x) &~ (offsetT) 0x7fffffff) == 0 \ + || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff)) + +/* Is the given value a zero-extended 32-bit value? Or a negated one? */ +#define IS_ZEXT_32BIT_NUM(x) \ + (((x) &~ (offsetT) 0xffffffff) == 0 \ + || (((x) &~ (offsetT) 0xffffffff) == ~ (offsetT) 0xffffffff)) + +/* Change INSN's opcode so that the operand given by FIELD has value VALUE. + INSN is a riscv_cl_insn structure and VALUE is evaluated exactly once. */ +#define INSERT_OPERAND(FIELD, INSN, VALUE) \ + INSERT_BITS ((INSN).insn_opcode, VALUE, OP_MASK_##FIELD, OP_SH_##FIELD) + +/* Determine if an instruction matches an opcode. */ +#define OPCODE_MATCHES(OPCODE, OP) \ + (((OPCODE) & MASK_##OP) == MATCH_##OP) + +static char *expr_end; + +/* The default target format to use. */ + +const char * +riscv_target_format (void) +{ + return xlen == 64 ? "elf64-littleriscv" : "elf32-littleriscv"; +} + +/* Return the length of instruction INSN. */ + +static inline unsigned int +insn_length (const struct riscv_cl_insn *insn) +{ + return riscv_insn_length (insn->insn_opcode); +} + +/* Initialise INSN from opcode entry MO. Leave its position unspecified. */ + +static void +create_insn (struct riscv_cl_insn *insn, const struct riscv_opcode *mo) +{ + insn->insn_mo = mo; + insn->insn_opcode = mo->match; + insn->frag = NULL; + insn->where = 0; + insn->fixp = NULL; +} + +/* Install INSN at the location specified by its "frag" and "where" fields. */ + +static void +install_insn (const struct riscv_cl_insn *insn) +{ + char *f = insn->frag->fr_literal + insn->where; + md_number_to_chars (f, insn->insn_opcode, insn_length (insn)); +} + +/* Move INSN to offset WHERE in FRAG. Adjust the fixups accordingly + and install the opcode in the new location. */ + +static void +move_insn (struct riscv_cl_insn *insn, fragS *frag, long where) +{ + insn->frag = frag; + insn->where = where; + if (insn->fixp != NULL) + { + insn->fixp->fx_frag = frag; + insn->fixp->fx_where = where; + } + install_insn (insn); +} + +/* Add INSN to the end of the output. */ + +static void +add_fixed_insn (struct riscv_cl_insn *insn) +{ + char *f = frag_more (insn_length (insn)); + move_insn (insn, frag_now, f - frag_now->fr_literal); +} + +static void +add_relaxed_insn (struct riscv_cl_insn *insn, int max_chars, int var, + relax_substateT subtype, symbolS *symbol, offsetT offset) +{ + frag_grow (max_chars); + move_insn (insn, frag_now, frag_more (0) - frag_now->fr_literal); + frag_var (rs_machine_dependent, max_chars, var, + subtype, symbol, offset, NULL); +} + +/* Compute the length of a branch sequence, and adjust the stored length + accordingly. If FRAGP is NULL, the worst-case length is returned. */ + +static unsigned +relaxed_branch_length (fragS *fragp, asection *sec, int update) +{ + int jump, rvc, length = 8; + + if (!fragp) + return length; + + jump = RELAX_BRANCH_UNCOND (fragp->fr_subtype); + rvc = RELAX_BRANCH_RVC (fragp->fr_subtype); + length = RELAX_BRANCH_LENGTH (fragp->fr_subtype); + + /* Assume jumps are in range; the linker will catch any that aren't. */ + length = jump ? 4 : 8; + + if (fragp->fr_symbol != NULL + && S_IS_DEFINED (fragp->fr_symbol) + && sec == S_GET_SEGMENT (fragp->fr_symbol)) + { + offsetT val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset; + bfd_vma rvc_range = jump ? RVC_JUMP_REACH : RVC_BRANCH_REACH; + val -= fragp->fr_address + fragp->fr_fix; + + if (rvc && (bfd_vma)(val + rvc_range/2) < rvc_range) + length = 2; + else if ((bfd_vma)(val + RISCV_BRANCH_REACH/2) < RISCV_BRANCH_REACH) + length = 4; + else if (!jump && rvc) + length = 6; + } + + if (update) + fragp->fr_subtype = RELAX_BRANCH_ENCODE (jump, rvc, length); + + return length; +} + +struct regname +{ + const char *name; + unsigned int num; +}; + +enum reg_class +{ + RCLASS_GPR, + RCLASS_FPR, + RCLASS_CSR, + RCLASS_MAX +}; + +static struct hash_control *reg_names_hash = NULL; + +#define ENCODE_REG_HASH(cls, n) \ + ((void *)(uintptr_t)((n) * RCLASS_MAX + (cls) + 1)) +#define DECODE_REG_CLASS(hash) (((uintptr_t)(hash) - 1) % RCLASS_MAX) +#define DECODE_REG_NUM(hash) (((uintptr_t)(hash) - 1) / RCLASS_MAX) + +static void +hash_reg_name (enum reg_class class, const char *name, unsigned n) +{ + void *hash = ENCODE_REG_HASH (class, n); + const char *retval = hash_insert (reg_names_hash, name, hash); + + if (retval != NULL) + as_fatal (_("internal error: can't hash `%s': %s"), name, retval); +} + +static void +hash_reg_names (enum reg_class class, const char * const names[], unsigned n) +{ + unsigned i; + + for (i = 0; i < n; i++) + hash_reg_name (class, names[i], i); +} + +static unsigned int +reg_lookup_internal (const char *s, enum reg_class class) +{ + struct regname *r = (struct regname *) hash_find (reg_names_hash, s); + + if (r == NULL || DECODE_REG_CLASS (r) != class) + return -1; + return DECODE_REG_NUM (r); +} + +static bfd_boolean +reg_lookup (char **s, enum reg_class class, unsigned int *regnop) +{ + char *e; + char save_c; + int reg = -1; + + /* Find end of name. */ + e = *s; + if (is_name_beginner (*e)) + ++e; + while (is_part_of_name (*e)) + ++e; + + /* Terminate name. */ + save_c = *e; + *e = '\0'; + + /* Look for the register. Advance to next token if one was recognized. */ + if ((reg = reg_lookup_internal (*s, class)) >= 0) + *s = e; + + *e = save_c; + if (regnop) + *regnop = reg; + return reg >= 0; +} + +static bfd_boolean +arg_lookup (char **s, const char *const *array, size_t size, unsigned *regnop) +{ + const char *p = strchr (*s, ','); + size_t i, len = p ? (size_t)(p - *s) : strlen (*s); + + for (i = 0; i < size; i++) + if (array[i] != NULL && strncmp (array[i], *s, len) == 0) + { + *regnop = i; + *s += len; + return TRUE; + } + + return FALSE; +} + +/* For consistency checking, verify that all bits are specified either + by the match/mask part of the instruction definition, or by the + operand list. */ +static bfd_boolean +validate_riscv_insn (const struct riscv_opcode *opc) +{ + const char *p = opc->args; + char c; + insn_t used_bits = opc->mask; + int insn_width = 8 * riscv_insn_length (opc->match); + insn_t required_bits = ~0ULL >> (64 - insn_width); + + if ((used_bits & opc->match) != (opc->match & required_bits)) + { + as_bad (_("internal: bad RISC-V opcode (mask error): %s %s"), + opc->name, opc->args); + return FALSE; + } + +#define USE_BITS(mask,shift) (used_bits |= ((insn_t)(mask) << (shift))) + while (*p) + switch (c = *p++) + { + case 'C': /* RVC */ + switch (c = *p++) + { + case 'a': used_bits |= ENCODE_RVC_J_IMM(-1U); break; + case 'c': break; /* RS1, constrained to equal sp */ + case 'i': used_bits |= ENCODE_RVC_SIMM3(-1U); break; + case 'j': used_bits |= ENCODE_RVC_IMM(-1U); break; + case 'k': used_bits |= ENCODE_RVC_LW_IMM(-1U); break; + case 'l': used_bits |= ENCODE_RVC_LD_IMM(-1U); break; + case 'm': used_bits |= ENCODE_RVC_LWSP_IMM(-1U); break; + case 'n': used_bits |= ENCODE_RVC_LDSP_IMM(-1U); break; + case 'p': used_bits |= ENCODE_RVC_B_IMM(-1U); break; + case 's': USE_BITS (OP_MASK_CRS1S, OP_SH_CRS1S); break; + case 't': USE_BITS (OP_MASK_CRS2S, OP_SH_CRS2S); break; + case 'u': used_bits |= ENCODE_RVC_IMM(-1U); break; + case 'v': used_bits |= ENCODE_RVC_IMM(-1U); break; + case 'w': break; /* RS1S, constrained to equal RD */ + case 'x': break; /* RS2S, constrained to equal RD */ + case 'K': used_bits |= ENCODE_RVC_ADDI4SPN_IMM(-1U); break; + case 'L': used_bits |= ENCODE_RVC_ADDI16SP_IMM(-1U); break; + case 'M': used_bits |= ENCODE_RVC_SWSP_IMM(-1U); break; + case 'N': used_bits |= ENCODE_RVC_SDSP_IMM(-1U); break; + case 'U': break; /* RS1, constrained to equal RD */ + case 'V': USE_BITS (OP_MASK_CRS2, OP_SH_CRS2); break; + case '<': used_bits |= ENCODE_RVC_IMM(-1U); break; + case '>': used_bits |= ENCODE_RVC_IMM(-1U); break; + case 'T': USE_BITS (OP_MASK_CRS2, OP_SH_CRS2); break; + case 'D': USE_BITS (OP_MASK_CRS2S, OP_SH_CRS2S); break; + default: + as_bad (_("internal: bad RISC-V opcode (unknown operand type `C%c'): %s %s"), + c, opc->name, opc->args); + return FALSE; + } + break; + case ',': break; + case '(': break; + case ')': break; + case '<': USE_BITS (OP_MASK_SHAMTW, OP_SH_SHAMTW); break; + case '>': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break; + case 'A': break; + case 'D': USE_BITS (OP_MASK_RD, OP_SH_RD); break; + case 'Z': USE_BITS (OP_MASK_RS1, OP_SH_RS1); break; + case 'E': USE_BITS (OP_MASK_CSR, OP_SH_CSR); break; + case 'I': break; + case 'R': USE_BITS (OP_MASK_RS3, OP_SH_RS3); break; + case 'S': USE_BITS (OP_MASK_RS1, OP_SH_RS1); break; + case 'U': USE_BITS (OP_MASK_RS1, OP_SH_RS1); /* fallthru */ + case 'T': USE_BITS (OP_MASK_RS2, OP_SH_RS2); break; + case 'd': USE_BITS (OP_MASK_RD, OP_SH_RD); break; + case 'm': USE_BITS (OP_MASK_RM, OP_SH_RM); break; + case 's': USE_BITS (OP_MASK_RS1, OP_SH_RS1); break; + case 't': USE_BITS (OP_MASK_RS2, OP_SH_RS2); break; + case 'P': USE_BITS (OP_MASK_PRED, OP_SH_PRED); break; + case 'Q': USE_BITS (OP_MASK_SUCC, OP_SH_SUCC); break; + case 'o': + case 'j': used_bits |= ENCODE_ITYPE_IMM(-1U); break; + case 'a': used_bits |= ENCODE_UJTYPE_IMM(-1U); break; + case 'p': used_bits |= ENCODE_SBTYPE_IMM(-1U); break; + case 'q': used_bits |= ENCODE_STYPE_IMM(-1U); break; + case 'u': used_bits |= ENCODE_UTYPE_IMM(-1U); break; + case '[': break; + case ']': break; + case '0': break; + default: + as_bad (_("internal: bad RISC-V opcode " + "(unknown operand type `%c'): %s %s"), + c, opc->name, opc->args); + return FALSE; + } +#undef USE_BITS + if (used_bits != required_bits) + { + as_bad (_("internal: bad RISC-V opcode (bits 0x%lx undefined): %s %s"), + ~(unsigned long)(used_bits & required_bits), + opc->name, opc->args); + return FALSE; + } + return TRUE; +} + +struct percent_op_match +{ + const char *str; + bfd_reloc_code_real_type reloc; +}; + +/* This function is called once, at assembler startup time. It should set up + all the tables, etc. that the MD part of the assembler will need. */ + +void +md_begin (void) +{ + int i = 0; + + if (! bfd_set_arch_mach (stdoutput, bfd_arch_riscv, 0)) + as_warn (_("Could not set architecture and machine")); + + op_hash = hash_new (); + + while (riscv_opcodes[i].name) + { + const char *name = riscv_opcodes[i].name; + const char *hash_error = + hash_insert (op_hash, name, (void *) &riscv_opcodes[i]); + + if (hash_error) + { + fprintf (stderr, _("internal error: can't hash `%s': %s\n"), + riscv_opcodes[i].name, hash_error); + /* Probably a memory allocation problem? Give up now. */ + as_fatal (_("Broken assembler. No assembly attempted.")); + } + + do + { + if (riscv_opcodes[i].pinfo != INSN_MACRO) + { + if (!validate_riscv_insn (&riscv_opcodes[i])) + as_fatal (_("Broken assembler. No assembly attempted.")); + } + ++i; + } + while (riscv_opcodes[i].name && !strcmp (riscv_opcodes[i].name, name)); + } + + reg_names_hash = hash_new (); + hash_reg_names (RCLASS_GPR, riscv_gpr_names_numeric, NGPR); + hash_reg_names (RCLASS_GPR, riscv_gpr_names_abi, NGPR); + hash_reg_names (RCLASS_FPR, riscv_fpr_names_numeric, NFPR); + hash_reg_names (RCLASS_FPR, riscv_fpr_names_abi, NFPR); + +#define DECLARE_CSR(name, num) hash_reg_name (RCLASS_CSR, #name, num); +#include "opcode/riscv-opc.h" +#undef DECLARE_CSR + + /* Set the default alignment for the text section. */ + record_alignment (text_section, riscv_opts.rvc ? 1 : 2); +} + +/* Output an instruction. IP is the instruction information. + ADDRESS_EXPR is an operand of the instruction to be used with + RELOC_TYPE. */ + +static void +append_insn (struct riscv_cl_insn *ip, expressionS *address_expr, + bfd_reloc_code_real_type reloc_type) +{ + dwarf2_emit_insn (0); + + if (reloc_type != BFD_RELOC_UNUSED) + { + reloc_howto_type *howto; + + gas_assert(address_expr); + if (reloc_type == BFD_RELOC_12_PCREL + || reloc_type == BFD_RELOC_RISCV_JMP) + { + int j = reloc_type == BFD_RELOC_RISCV_JMP; + int best_case = riscv_insn_length (ip->insn_opcode); + unsigned worst_case = relaxed_branch_length (NULL, NULL, 0); + add_relaxed_insn (ip, worst_case, best_case, + RELAX_BRANCH_ENCODE (j, best_case == 2, worst_case), + address_expr->X_add_symbol, + address_expr->X_add_number); + return; + } + else if (address_expr->X_op == O_constant) + { + switch (reloc_type) + { + case BFD_RELOC_32: + ip->insn_opcode |= address_expr->X_add_number; + goto append; + + case BFD_RELOC_RISCV_HI20: + { + insn_t imm = RISCV_CONST_HIGH_PART (address_expr->X_add_number); + ip->insn_opcode |= ENCODE_UTYPE_IMM (imm); + goto append; + } + + case BFD_RELOC_RISCV_LO12_S: + ip->insn_opcode |= ENCODE_STYPE_IMM (address_expr->X_add_number); + goto append; + + case BFD_RELOC_RISCV_LO12_I: + ip->insn_opcode |= ENCODE_ITYPE_IMM (address_expr->X_add_number); + goto append; + + default: + break; + } + } + + howto = bfd_reloc_type_lookup (stdoutput, reloc_type); + if (howto == NULL) + as_bad (_("Unsupported RISC-V relocation number %d"), reloc_type); + + ip->fixp = fix_new_exp (ip->frag, ip->where, + bfd_get_reloc_size (howto), + address_expr, FALSE, reloc_type); + } + +append: + add_fixed_insn (ip); + install_insn (ip); +} + +/* Build an instruction created by a macro expansion. This is passed + a pointer to the count of instructions created so far, an + expression, the name of the instruction to build, an operand format + string, and corresponding arguments. */ + +static void +macro_build (expressionS *ep, const char *name, const char *fmt, ...) +{ + const struct riscv_opcode *mo; + struct riscv_cl_insn insn; + bfd_reloc_code_real_type r; + va_list args; + + va_start (args, fmt); + + r = BFD_RELOC_UNUSED; + mo = (struct riscv_opcode *) hash_find (op_hash, name); + gas_assert (mo); + + /* Find a non-RVC variant of the instruction. append_insn will compress + it if possible. */ + while (riscv_insn_length (mo->match) < 4) + mo++; + gas_assert (strcmp (name, mo->name) == 0); + + create_insn (&insn, mo); + for (;;) + { + switch (*fmt++) + { + case 'd': + INSERT_OPERAND (RD, insn, va_arg (args, int)); + continue; + + case 's': + INSERT_OPERAND (RS1, insn, va_arg (args, int)); + continue; + + case 't': + INSERT_OPERAND (RS2, insn, va_arg (args, int)); + continue; + + case '>': + INSERT_OPERAND (SHAMT, insn, va_arg (args, int)); + continue; + + case 'j': + case 'u': + case 'q': + gas_assert (ep != NULL); + r = va_arg (args, int); + continue; + + case '\0': + break; + case ',': + continue; + default: + as_fatal (_("internal error: invalid macro")); + } + break; + } + va_end (args); + gas_assert (r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL); + + append_insn (&insn, ep, r); +} + +/* Sign-extend 32-bit mode constants that have bit 31 set and all higher bits + unset. */ +static void +normalize_constant_expr (expressionS *ex) +{ + if (xlen > 32) + return; + if ((ex->X_op == O_constant || ex->X_op == O_symbol) + && IS_ZEXT_32BIT_NUM (ex->X_add_number)) + ex->X_add_number = (((ex->X_add_number & 0xffffffff) ^ 0x80000000) + - 0x80000000); +} + +/* Fail if an expression is not a constant. */ + +static void +check_absolute_expr (struct riscv_cl_insn *ip, expressionS *ex) +{ + if (ex->X_op == O_big) + as_bad (_("unsupported large constant")); + else if (ex->X_op != O_constant) + as_bad (_("Instruction %s requires absolute expression"), + ip->insn_mo->name); + normalize_constant_expr (ex); +} + +static symbolS * +make_internal_label (void) +{ + return (symbolS *) local_symbol_make (FAKE_LABEL_NAME, now_seg, + (valueT) frag_now_fix(), frag_now); +} + +/* Load an entry from the GOT. */ +static void +pcrel_access (int destreg, int tempreg, expressionS *ep, + const char *lo_insn, const char *lo_pattern, + bfd_reloc_code_real_type hi_reloc, + bfd_reloc_code_real_type lo_reloc) +{ + expressionS ep2; + ep2.X_op = O_symbol; + ep2.X_add_symbol = make_internal_label (); + ep2.X_add_number = 0; + + macro_build (ep, "auipc", "d,u", tempreg, hi_reloc); + macro_build (&ep2, lo_insn, lo_pattern, destreg, tempreg, lo_reloc); +} + +static void +pcrel_load (int destreg, int tempreg, expressionS *ep, const char *lo_insn, + bfd_reloc_code_real_type hi_reloc, + bfd_reloc_code_real_type lo_reloc) +{ + pcrel_access (destreg, tempreg, ep, lo_insn, "d,s,j", hi_reloc, lo_reloc); +} + +static void +pcrel_store (int srcreg, int tempreg, expressionS *ep, const char *lo_insn, + bfd_reloc_code_real_type hi_reloc, + bfd_reloc_code_real_type lo_reloc) +{ + pcrel_access (srcreg, tempreg, ep, lo_insn, "t,s,q", hi_reloc, lo_reloc); +} + +/* PC-relative function call using AUIPC/JALR, relaxed to JAL. */ +static void +riscv_call (int destreg, int tempreg, expressionS *ep, + bfd_reloc_code_real_type reloc) +{ + macro_build (ep, "auipc", "d,u", tempreg, reloc); + macro_build (NULL, "jalr", "d,s", destreg, tempreg); +} + +/* Load an integer constant into a register. */ + +static void +load_const (int reg, expressionS *ep) +{ + int shift = RISCV_IMM_BITS; + expressionS upper = *ep, lower = *ep; + lower.X_add_number = (int32_t) ep->X_add_number << (32-shift) >> (32-shift); + upper.X_add_number -= lower.X_add_number; + + if (ep->X_op != O_constant) + { + as_bad (_("unsupported large constant")); + return; + } + + if (xlen > 32 && !IS_SEXT_32BIT_NUM(ep->X_add_number)) + { + /* Reduce to a signed 32-bit constant using SLLI and ADDI. */ + while (((upper.X_add_number >> shift) & 1) == 0) + shift++; + + upper.X_add_number = (int64_t) upper.X_add_number >> shift; + load_const(reg, &upper); + + macro_build (NULL, "slli", "d,s,>", reg, reg, shift); + if (lower.X_add_number != 0) + macro_build (&lower, "addi", "d,s,j", reg, reg, BFD_RELOC_RISCV_LO12_I); + } + else + { + /* Simply emit LUI and/or ADDI to build a 32-bit signed constant. */ + int hi_reg = 0; + + if (upper.X_add_number != 0) + { + macro_build (ep, "lui", "d,u", reg, BFD_RELOC_RISCV_HI20); + hi_reg = reg; + } + + if (lower.X_add_number != 0 || hi_reg == 0) + macro_build (ep, ADD32_INSN, "d,s,j", reg, hi_reg, + BFD_RELOC_RISCV_LO12_I); + } +} + +/* Expand RISC-V assembly macros into one or more instructions. */ +static void +macro (struct riscv_cl_insn *ip, expressionS *imm_expr, + bfd_reloc_code_real_type *imm_reloc) +{ + int rd = (ip->insn_opcode >> OP_SH_RD) & OP_MASK_RD; + int rs1 = (ip->insn_opcode >> OP_SH_RS1) & OP_MASK_RS1; + int rs2 = (ip->insn_opcode >> OP_SH_RS2) & OP_MASK_RS2; + int mask = ip->insn_mo->mask; + + switch (mask) + { + case M_LI: + load_const (rd, imm_expr); + break; + + case M_LA: + case M_LLA: + /* Load the address of a symbol into a register. */ + if (!IS_SEXT_32BIT_NUM (imm_expr->X_add_number)) + as_bad (_("offset too large")); + + if (imm_expr->X_op == O_constant) + load_const (rd, imm_expr); + else if (riscv_opts.pic && mask == M_LA) /* Global PIC symbol */ + pcrel_load (rd, rd, imm_expr, LOAD_ADDRESS_INSN, + BFD_RELOC_RISCV_GOT_HI20, BFD_RELOC_RISCV_PCREL_LO12_I); + else /* Local PIC symbol, or any non-PIC symbol */ + pcrel_load (rd, rd, imm_expr, "addi", + BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_I); + break; + + case M_LA_TLS_GD: + pcrel_load (rd, rd, imm_expr, "addi", + BFD_RELOC_RISCV_TLS_GD_HI20, BFD_RELOC_RISCV_PCREL_LO12_I); + break; + + case M_LA_TLS_IE: + pcrel_load (rd, rd, imm_expr, LOAD_ADDRESS_INSN, + BFD_RELOC_RISCV_TLS_GOT_HI20, BFD_RELOC_RISCV_PCREL_LO12_I); + break; + + case M_LB: + pcrel_load (rd, rd, imm_expr, "lb", + BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_I); + break; + + case M_LBU: + pcrel_load (rd, rd, imm_expr, "lbu", + BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_I); + break; + + case M_LH: + pcrel_load (rd, rd, imm_expr, "lh", + BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_I); + break; + + case M_LHU: + pcrel_load (rd, rd, imm_expr, "lhu", + BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_I); + break; + + case M_LW: + pcrel_load (rd, rd, imm_expr, "lw", + BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_I); + break; + + case M_LWU: + pcrel_load (rd, rd, imm_expr, "lwu", + BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_I); + break; + + case M_LD: + pcrel_load (rd, rd, imm_expr, "ld", + BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_I); + break; + + case M_FLW: + pcrel_load (rd, rs1, imm_expr, "flw", + BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_I); + break; + + case M_FLD: + pcrel_load (rd, rs1, imm_expr, "fld", + BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_I); + break; + + case M_SB: + pcrel_store (rs2, rs1, imm_expr, "sb", + BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_S); + break; + + case M_SH: + pcrel_store (rs2, rs1, imm_expr, "sh", + BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_S); + break; + + case M_SW: + pcrel_store (rs2, rs1, imm_expr, "sw", + BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_S); + break; + + case M_SD: + pcrel_store (rs2, rs1, imm_expr, "sd", + BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_S); + break; + + case M_FSW: + pcrel_store (rs2, rs1, imm_expr, "fsw", + BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_S); + break; + + case M_FSD: + pcrel_store (rs2, rs1, imm_expr, "fsd", + BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_S); + break; + + case M_CALL: + riscv_call (rd, rs1, imm_expr, *imm_reloc); + break; + + default: + as_bad (_("Macro %s not implemented"), ip->insn_mo->name); + break; + } +} + +static const struct percent_op_match percent_op_utype[] = +{ + {"%tprel_hi", BFD_RELOC_RISCV_TPREL_HI20}, + {"%pcrel_hi", BFD_RELOC_RISCV_PCREL_HI20}, + {"%tls_ie_pcrel_hi", BFD_RELOC_RISCV_TLS_GOT_HI20}, + {"%tls_gd_pcrel_hi", BFD_RELOC_RISCV_TLS_GD_HI20}, + {"%hi", BFD_RELOC_RISCV_HI20}, + {0, 0} +}; + +static const struct percent_op_match percent_op_itype[] = +{ + {"%lo", BFD_RELOC_RISCV_LO12_I}, + {"%tprel_lo", BFD_RELOC_RISCV_TPREL_LO12_I}, + {"%pcrel_lo", BFD_RELOC_RISCV_PCREL_LO12_I}, + {0, 0} +}; + +static const struct percent_op_match percent_op_stype[] = +{ + {"%lo", BFD_RELOC_RISCV_LO12_S}, + {"%tprel_lo", BFD_RELOC_RISCV_TPREL_LO12_S}, + {"%pcrel_lo", BFD_RELOC_RISCV_PCREL_LO12_S}, + {0, 0} +}; + +static const struct percent_op_match percent_op_rtype[] = +{ + {"%tprel_add", BFD_RELOC_RISCV_TPREL_ADD}, + {0, 0} +}; + +/* Return true if *STR points to a relocation operator. When returning true, + move *STR over the operator and store its relocation code in *RELOC. + Leave both *STR and *RELOC alone when returning false. */ + +static bfd_boolean +parse_relocation (char **str, bfd_reloc_code_real_type *reloc, + const struct percent_op_match *percent_op) +{ + for ( ; percent_op->str; percent_op++) + if (strncasecmp (*str, percent_op->str, strlen (percent_op->str)) == 0) + { + int len = strlen (percent_op->str); + + if (!ISSPACE ((*str)[len]) && (*str)[len] != '(') + continue; + + *str += strlen (percent_op->str); + *reloc = percent_op->reloc; + + /* Check whether the output BFD supports this relocation. + If not, issue an error and fall back on something safe. */ + if (!bfd_reloc_type_lookup (stdoutput, percent_op->reloc)) + { + as_bad ("relocation %s isn't supported by the current ABI", + percent_op->str); + *reloc = BFD_RELOC_UNUSED; + } + return TRUE; + } + return FALSE; +} + +static void +my_getExpression (expressionS *ep, char *str) +{ + char *save_in; + + save_in = input_line_pointer; + input_line_pointer = str; + expression (ep); + expr_end = input_line_pointer; + input_line_pointer = save_in; +} + +/* Parse string STR as a 16-bit relocatable operand. Store the + expression in *EP and the relocation, if any, in RELOC. + Return the number of relocation operators used (0 or 1). + + On exit, EXPR_END points to the first character after the expression. */ + +static size_t +my_getSmallExpression (expressionS *ep, bfd_reloc_code_real_type *reloc, + char *str, const struct percent_op_match *percent_op) +{ + size_t reloc_index; + unsigned crux_depth, str_depth, regno; + char *crux; + + /* First, check for integer registers. */ + if (reg_lookup (&str, RCLASS_GPR, ®no)) + { + ep->X_op = O_register; + ep->X_add_number = regno; + return 0; + } + + /* Search for the start of the main expression. + End the loop with CRUX pointing to the start + of the main expression and with CRUX_DEPTH containing the number + of open brackets at that point. */ + reloc_index = -1; + str_depth = 0; + do + { + reloc_index++; + crux = str; + crux_depth = str_depth; + + /* Skip over whitespace and brackets, keeping count of the number + of brackets. */ + while (*str == ' ' || *str == '\t' || *str == '(') + if (*str++ == '(') + str_depth++; + } + while (*str == '%' + && reloc_index < 1 + && parse_relocation (&str, reloc, percent_op)); + + my_getExpression (ep, crux); + str = expr_end; + + /* Match every open bracket. */ + while (crux_depth > 0 && (*str == ')' || *str == ' ' || *str == '\t')) + if (*str++ == ')') + crux_depth--; + + if (crux_depth > 0) + as_bad ("unclosed '('"); + + expr_end = str; + + return reloc_index; +} + +/* This routine assembles an instruction into its binary format. As a + side effect, it sets the global variable imm_reloc to the type of + relocation to do if one of the operands is an address expression. */ + +static const char * +riscv_ip (char *str, struct riscv_cl_insn *ip, expressionS *imm_expr, + bfd_reloc_code_real_type *imm_reloc) +{ + char *s; + const char *args; + char c = 0; + struct riscv_opcode *insn; + char *argsStart; + unsigned int regno; + char save_c = 0; + int argnum; + const struct percent_op_match *p; + const char *error = "unrecognized opcode"; + + /* Parse the name of the instruction. Terminate the string if whitespace + is found so that hash_find only sees the name part of the string. */ + for (s = str; *s != '\0'; ++s) + if (ISSPACE (*s)) + { + save_c = *s; + *s++ = '\0'; + break; + } + + insn = (struct riscv_opcode *) hash_find (op_hash, str); + + argsStart = s; + for ( ; insn && insn->name && strcmp (insn->name, str) == 0; insn++) + { + if (!riscv_subset_supports (insn->subset)) + continue; + + create_insn (ip, insn); + argnum = 1; + + imm_expr->X_op = O_absent; + *imm_reloc = BFD_RELOC_UNUSED; + p = percent_op_itype; + + for (args = insn->args;; ++args) + { + s += strspn (s, " \t"); + switch (*args) + { + case '\0': /* End of args. */ + if (insn->pinfo != INSN_MACRO) + { + if (!insn->match_func (insn, ip->insn_opcode)) + break; + if (riscv_insn_length (insn->match) == 2 && !riscv_opts.rvc) + break; + } + if (*s != '\0') + break; + /* Successful assembly. */ + error = NULL; + goto out; + + case 'C': /* RVC */ + switch (*++args) + { + case 's': /* RS1 x8-x15 */ + if (!reg_lookup (&s, RCLASS_GPR, ®no) + || !(regno >= 8 && regno <= 15)) + break; + INSERT_OPERAND (CRS1S, *ip, regno % 8); + continue; + case 'w': /* RS1 x8-x15, constrained to equal RD x8-x15. */ + if (!reg_lookup (&s, RCLASS_GPR, ®no) + || EXTRACT_OPERAND (CRS1S, ip->insn_opcode) + 8 != regno) + break; + continue; + case 't': /* RS2 x8-x15 */ + if (!reg_lookup (&s, RCLASS_GPR, ®no) + || !(regno >= 8 && regno <= 15)) + break; + INSERT_OPERAND (CRS2S, *ip, regno % 8); + continue; + case 'x': /* RS2 x8-x15, constrained to equal RD x8-x15. */ + if (!reg_lookup (&s, RCLASS_GPR, ®no) + || EXTRACT_OPERAND (CRS2S, ip->insn_opcode) + 8 != regno) + break; + continue; + case 'U': /* RS1, constrained to equal RD. */ + if (!reg_lookup (&s, RCLASS_GPR, ®no) + || EXTRACT_OPERAND (RD, ip->insn_opcode) != regno) + break; + continue; + case 'V': /* RS2 */ + if (!reg_lookup (&s, RCLASS_GPR, ®no)) + break; + INSERT_OPERAND (CRS2, *ip, regno); + continue; + case 'c': /* RS1, constrained to equal sp. */ + if (!reg_lookup (&s, RCLASS_GPR, ®no) + || regno != X_SP) + break; + continue; + case '>': + if (my_getSmallExpression (imm_expr, imm_reloc, s, p) + || imm_expr->X_op != O_constant + || imm_expr->X_add_number <= 0 + || imm_expr->X_add_number >= 64) + break; + ip->insn_opcode |= ENCODE_RVC_IMM (imm_expr->X_add_number); +rvc_imm_done: + s = expr_end; + imm_expr->X_op = O_absent; + continue; + case '<': + if (my_getSmallExpression (imm_expr, imm_reloc, s, p) + || imm_expr->X_op != O_constant + || !VALID_RVC_IMM (imm_expr->X_add_number) + || imm_expr->X_add_number <= 0 + || imm_expr->X_add_number >= 32) + break; + ip->insn_opcode |= ENCODE_RVC_IMM (imm_expr->X_add_number); + goto rvc_imm_done; + case 'i': + if (my_getSmallExpression (imm_expr, imm_reloc, s, p) + || imm_expr->X_op != O_constant + || imm_expr->X_add_number == 0 + || !VALID_RVC_SIMM3 (imm_expr->X_add_number)) + break; + ip->insn_opcode |= ENCODE_RVC_SIMM3 (imm_expr->X_add_number); + goto rvc_imm_done; + case 'j': + if (my_getSmallExpression (imm_expr, imm_reloc, s, p) + || imm_expr->X_op != O_constant + || imm_expr->X_add_number == 0 + || !VALID_RVC_IMM (imm_expr->X_add_number)) + break; + ip->insn_opcode |= ENCODE_RVC_IMM (imm_expr->X_add_number); + goto rvc_imm_done; + case 'k': + if (my_getSmallExpression (imm_expr, imm_reloc, s, p) + || imm_expr->X_op != O_constant + || !VALID_RVC_LW_IMM (imm_expr->X_add_number)) + break; + ip->insn_opcode |= ENCODE_RVC_LW_IMM (imm_expr->X_add_number); + goto rvc_imm_done; + case 'l': + if (my_getSmallExpression (imm_expr, imm_reloc, s, p) + || imm_expr->X_op != O_constant + || !VALID_RVC_LD_IMM (imm_expr->X_add_number)) + break; + ip->insn_opcode |= ENCODE_RVC_LD_IMM (imm_expr->X_add_number); + goto rvc_imm_done; + case 'm': + if (my_getSmallExpression (imm_expr, imm_reloc, s, p) + || imm_expr->X_op != O_constant + || !VALID_RVC_LWSP_IMM (imm_expr->X_add_number)) + break; + ip->insn_opcode |= + ENCODE_RVC_LWSP_IMM (imm_expr->X_add_number); + goto rvc_imm_done; + case 'n': + if (my_getSmallExpression (imm_expr, imm_reloc, s, p) + || imm_expr->X_op != O_constant + || !VALID_RVC_LDSP_IMM (imm_expr->X_add_number)) + break; + ip->insn_opcode |= + ENCODE_RVC_LDSP_IMM (imm_expr->X_add_number); + goto rvc_imm_done; + case 'K': + if (my_getSmallExpression (imm_expr, imm_reloc, s, p) + || imm_expr->X_op != O_constant + || !VALID_RVC_ADDI4SPN_IMM (imm_expr->X_add_number) + || imm_expr->X_add_number == 0) + break; + ip->insn_opcode |= + ENCODE_RVC_ADDI4SPN_IMM (imm_expr->X_add_number); + goto rvc_imm_done; + case 'L': + if (my_getSmallExpression (imm_expr, imm_reloc, s, p) + || imm_expr->X_op != O_constant + || !VALID_RVC_ADDI16SP_IMM (imm_expr->X_add_number) + || imm_expr->X_add_number == 0) + break; + ip->insn_opcode |= + ENCODE_RVC_ADDI16SP_IMM (imm_expr->X_add_number); + goto rvc_imm_done; + case 'M': + if (my_getSmallExpression (imm_expr, imm_reloc, s, p) + || imm_expr->X_op != O_constant + || !VALID_RVC_SWSP_IMM (imm_expr->X_add_number)) + break; + ip->insn_opcode |= + ENCODE_RVC_SWSP_IMM (imm_expr->X_add_number); + goto rvc_imm_done; + case 'N': + if (my_getSmallExpression (imm_expr, imm_reloc, s, p) + || imm_expr->X_op != O_constant + || !VALID_RVC_SDSP_IMM (imm_expr->X_add_number)) + break; + ip->insn_opcode |= + ENCODE_RVC_SDSP_IMM (imm_expr->X_add_number); + goto rvc_imm_done; + case 'u': + p = percent_op_utype; + if (my_getSmallExpression (imm_expr, imm_reloc, s, p)) + break; +rvc_lui: + if (imm_expr->X_op != O_constant + || imm_expr->X_add_number <= 0 + || imm_expr->X_add_number >= RISCV_BIGIMM_REACH + || (imm_expr->X_add_number >= RISCV_RVC_IMM_REACH / 2 + && (imm_expr->X_add_number < + RISCV_BIGIMM_REACH - RISCV_RVC_IMM_REACH / 2))) + break; + ip->insn_opcode |= ENCODE_RVC_IMM (imm_expr->X_add_number); + goto rvc_imm_done; + case 'v': + if (my_getSmallExpression (imm_expr, imm_reloc, s, p) + || (imm_expr->X_add_number & (RISCV_IMM_REACH - 1)) + || ((int32_t)imm_expr->X_add_number + != imm_expr->X_add_number)) + break; + imm_expr->X_add_number = + ((uint32_t) imm_expr->X_add_number) >> RISCV_IMM_BITS; + goto rvc_lui; + case 'p': + goto branch; + case 'a': + goto jump; + case 'D': /* Floating-point RS2 x8-x15. */ + if (!reg_lookup (&s, RCLASS_FPR, ®no) + || !(regno >= 8 && regno <= 15)) + break; + INSERT_OPERAND (CRS2S, *ip, regno % 8); + continue; + case 'T': /* Floating-point RS2. */ + if (!reg_lookup (&s, RCLASS_FPR, ®no)) + break; + INSERT_OPERAND (CRS2, *ip, regno); + continue; + default: + as_bad (_("bad RVC field specifier 'C%c'\n"), *args); + } + break; + + case ',': + ++argnum; + if (*s++ == *args) + continue; + s--; + break; + + case '(': + case ')': + case '[': + case ']': + if (*s++ == *args) + continue; + break; + + case '<': /* Shift amount, 0 - 31. */ + my_getExpression (imm_expr, s); + check_absolute_expr (ip, imm_expr); + if ((unsigned long) imm_expr->X_add_number > 31) + as_warn (_("Improper shift amount (%lu)"), + (unsigned long) imm_expr->X_add_number); + INSERT_OPERAND (SHAMTW, *ip, imm_expr->X_add_number); + imm_expr->X_op = O_absent; + s = expr_end; + continue; + + case '>': /* Shift amount, 0 - (XLEN-1). */ + my_getExpression (imm_expr, s); + check_absolute_expr (ip, imm_expr); + if ((unsigned long) imm_expr->X_add_number >= xlen) + as_warn (_("Improper shift amount (%lu)"), + (unsigned long) imm_expr->X_add_number); + INSERT_OPERAND (SHAMT, *ip, imm_expr->X_add_number); + imm_expr->X_op = O_absent; + s = expr_end; + continue; + + case 'Z': /* CSRRxI immediate. */ + my_getExpression (imm_expr, s); + check_absolute_expr (ip, imm_expr); + if ((unsigned long) imm_expr->X_add_number > 31) + as_warn (_("Improper CSRxI immediate (%lu)"), + (unsigned long) imm_expr->X_add_number); + INSERT_OPERAND (RS1, *ip, imm_expr->X_add_number); + imm_expr->X_op = O_absent; + s = expr_end; + continue; + + case 'E': /* Control register. */ + if (reg_lookup (&s, RCLASS_CSR, ®no)) + INSERT_OPERAND (CSR, *ip, regno); + else + { + my_getExpression (imm_expr, s); + check_absolute_expr (ip, imm_expr); + if ((unsigned long) imm_expr->X_add_number > 0xfff) + as_warn(_("Improper CSR address (%lu)"), + (unsigned long) imm_expr->X_add_number); + INSERT_OPERAND (CSR, *ip, imm_expr->X_add_number); + imm_expr->X_op = O_absent; + s = expr_end; + } + continue; + + case 'm': /* Rounding mode. */ + if (arg_lookup (&s, riscv_rm, ARRAY_SIZE (riscv_rm), ®no)) + { + INSERT_OPERAND (RM, *ip, regno); + continue; + } + break; + + case 'P': + case 'Q': /* Fence predecessor/successor. */ + if (arg_lookup (&s, riscv_pred_succ, ARRAY_SIZE (riscv_pred_succ), + ®no)) + { + if (*args == 'P') + INSERT_OPERAND (PRED, *ip, regno); + else + INSERT_OPERAND (SUCC, *ip, regno); + continue; + } + break; + + case 'd': /* Destination register. */ + case 's': /* Source register. */ + case 't': /* Target register. */ + if (reg_lookup (&s, RCLASS_GPR, ®no)) + { + c = *args; + if (*s == ' ') + ++s; + + /* Now that we have assembled one operand, we use the args + string to figure out where it goes in the instruction. */ + switch (c) + { + case 's': + INSERT_OPERAND (RS1, *ip, regno); + break; + case 'd': + INSERT_OPERAND (RD, *ip, regno); + break; + case 't': + INSERT_OPERAND (RS2, *ip, regno); + break; + } + continue; + } + break; + + case 'D': /* Floating point rd. */ + case 'S': /* Floating point rs1. */ + case 'T': /* Floating point rs2. */ + case 'U': /* Floating point rs1 and rs2. */ + case 'R': /* Floating point rs3. */ + if (reg_lookup (&s, RCLASS_FPR, ®no)) + { + c = *args; + if (*s == ' ') + ++s; + switch (c) + { + case 'D': + INSERT_OPERAND (RD, *ip, regno); + break; + case 'S': + INSERT_OPERAND (RS1, *ip, regno); + break; + case 'U': + INSERT_OPERAND (RS1, *ip, regno); + /* fallthru */ + case 'T': + INSERT_OPERAND (RS2, *ip, regno); + break; + case 'R': + INSERT_OPERAND (RS3, *ip, regno); + break; + } + continue; + } + + break; + + case 'I': + my_getExpression (imm_expr, s); + if (imm_expr->X_op != O_big + && imm_expr->X_op != O_constant) + break; + normalize_constant_expr (imm_expr); + s = expr_end; + continue; + + case 'A': + my_getExpression (imm_expr, s); + normalize_constant_expr (imm_expr); + /* The 'A' format specifier must be a symbol. */ + if (imm_expr->X_op != O_symbol) + break; + *imm_reloc = BFD_RELOC_32; + s = expr_end; + continue; + + case 'j': /* Sign-extended immediate. */ + *imm_reloc = BFD_RELOC_RISCV_LO12_I; + p = percent_op_itype; + goto alu_op; + case 'q': /* Store displacement. */ + p = percent_op_stype; + *imm_reloc = BFD_RELOC_RISCV_LO12_S; + goto load_store; + case 'o': /* Load displacement. */ + p = percent_op_itype; + *imm_reloc = BFD_RELOC_RISCV_LO12_I; + goto load_store; + case '0': /* AMO "displacement," which must be zero. */ + p = percent_op_rtype; + *imm_reloc = BFD_RELOC_UNUSED; +load_store: + /* Check whether there is only a single bracketed expression + left. If so, it must be the base register and the + constant must be zero. */ + imm_expr->X_op = O_constant; + imm_expr->X_add_number = 0; + if (*s == '(' && strchr (s + 1, '(') == 0) + continue; +alu_op: + /* If this value won't fit into a 16 bit offset, then go + find a macro that will generate the 32 bit offset + code pattern. */ + if (!my_getSmallExpression (imm_expr, imm_reloc, s, p)) + { + normalize_constant_expr (imm_expr); + if (imm_expr->X_op != O_constant + || (*args == '0' && imm_expr->X_add_number != 0) + || imm_expr->X_add_number >= (signed)RISCV_IMM_REACH/2 + || imm_expr->X_add_number < -(signed)RISCV_IMM_REACH/2) + break; + } + + s = expr_end; + continue; + + case 'p': /* PC-relative offset. */ +branch: + *imm_reloc = BFD_RELOC_12_PCREL; + my_getExpression (imm_expr, s); + s = expr_end; + continue; + + case 'u': /* Upper 20 bits. */ + p = percent_op_utype; + if (!my_getSmallExpression (imm_expr, imm_reloc, s, p) + && imm_expr->X_op == O_constant) + { + if (imm_expr->X_add_number < 0 + || imm_expr->X_add_number >= (signed)RISCV_BIGIMM_REACH) + as_bad (_("lui expression not in range 0..1048575")); + + *imm_reloc = BFD_RELOC_RISCV_HI20; + imm_expr->X_add_number <<= RISCV_IMM_BITS; + } + s = expr_end; + continue; + + case 'a': /* 20-bit PC-relative offset. */ +jump: + my_getExpression (imm_expr, s); + s = expr_end; + *imm_reloc = BFD_RELOC_RISCV_JMP; + continue; + + case 'c': + my_getExpression (imm_expr, s); + s = expr_end; + if (strcmp (s, "@plt") == 0) + { + *imm_reloc = BFD_RELOC_RISCV_CALL_PLT; + s += 4; + } + else + *imm_reloc = BFD_RELOC_RISCV_CALL; + continue; + + default: + as_fatal (_("internal error: bad argument type %c"), *args); + } + break; + } + s = argsStart; + error = _("illegal operands"); + } + +out: + /* Restore the character we might have clobbered above. */ + if (save_c) + *(argsStart - 1) = save_c; + + return error; +} + +void +md_assemble (char *str) +{ + struct riscv_cl_insn insn; + expressionS imm_expr; + bfd_reloc_code_real_type imm_reloc = BFD_RELOC_UNUSED; + + const char *error = riscv_ip (str, &insn, &imm_expr, &imm_reloc); + + if (error) + { + as_bad ("%s `%s'", error, str); + return; + } + + if (insn.insn_mo->pinfo == INSN_MACRO) + macro (&insn, &imm_expr, &imm_reloc); + else + append_insn (&insn, &imm_expr, imm_reloc); +} + +const char * +md_atof (int type, char *litP, int *sizeP) +{ + return ieee_md_atof (type, litP, sizeP, TARGET_BYTES_BIG_ENDIAN); +} + +void +md_number_to_chars (char *buf, valueT val, int n) +{ + number_to_chars_littleendian (buf, val, n); +} + +const char *md_shortopts = "O::g::G:"; + +enum options +{ + OPTION_M32 = OPTION_MD_BASE, + OPTION_M64, + OPTION_MARCH, + OPTION_PIC, + OPTION_NO_PIC, + OPTION_MSOFT_FLOAT, + OPTION_MHARD_FLOAT, + OPTION_MRVC, + OPTION_MNO_RVC, + OPTION_END_OF_ENUM +}; + +struct option md_longopts[] = +{ + {"m32", no_argument, NULL, OPTION_M32}, + {"m64", no_argument, NULL, OPTION_M64}, + {"march", required_argument, NULL, OPTION_MARCH}, + {"fPIC", no_argument, NULL, OPTION_PIC}, + {"fpic", no_argument, NULL, OPTION_PIC}, + {"fno-pic", no_argument, NULL, OPTION_NO_PIC}, + {"mrvc", no_argument, NULL, OPTION_MRVC}, + {"mno-rvc", no_argument, NULL, OPTION_MNO_RVC}, + {"msoft-float", no_argument, NULL, OPTION_MSOFT_FLOAT}, + {"mhard-float", no_argument, NULL, OPTION_MHARD_FLOAT}, + + {NULL, no_argument, NULL, 0} +}; +size_t md_longopts_size = sizeof (md_longopts); + +enum float_mode +{ + FLOAT_MODE_DEFAULT, + FLOAT_MODE_SOFT, + FLOAT_MODE_HARD +}; +static enum float_mode float_mode = FLOAT_MODE_DEFAULT; + +int +md_parse_option (int c, const char *arg) +{ + switch (c) + { + case OPTION_MRVC: + riscv_set_rvc (TRUE); + break; + + case OPTION_MNO_RVC: + riscv_set_rvc (FALSE); + break; + + case OPTION_MSOFT_FLOAT: + float_mode = FLOAT_MODE_SOFT; + break; + + case OPTION_MHARD_FLOAT: + float_mode = FLOAT_MODE_HARD; + break; + + case OPTION_M32: + xlen = 32; + break; + + case OPTION_M64: + xlen = 64; + break; + + case OPTION_MARCH: + riscv_set_arch (arg); + break; + + case OPTION_NO_PIC: + riscv_opts.pic = FALSE; + break; + + case OPTION_PIC: + riscv_opts.pic = TRUE; + break; + + default: + return 0; + } + + return 1; +} + +void +riscv_after_parse_args (void) +{ + if (riscv_subsets == NULL) + riscv_set_arch ("RVIMAFD"); + + if (xlen == 0) + { + if (strcmp (default_arch, "riscv32") == 0) + xlen = 32; + else if (strcmp (default_arch, "riscv64") == 0) + xlen = 64; + else + as_bad ("unknown default architecture `%s'", default_arch); + } +} + +long +md_pcrel_from (fixS *fixP) +{ + return fixP->fx_where + fixP->fx_frag->fr_address; +} + +/* Apply a fixup to the object file. */ + +void +md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED) +{ + bfd_byte *buf = (bfd_byte *) (fixP->fx_frag->fr_literal + fixP->fx_where); + + /* Remember value for tc_gen_reloc. */ + fixP->fx_addnumber = *valP; + + switch (fixP->fx_r_type) + { + case BFD_RELOC_RISCV_TLS_GOT_HI20: + case BFD_RELOC_RISCV_TLS_GD_HI20: + case BFD_RELOC_RISCV_TLS_DTPREL32: + case BFD_RELOC_RISCV_TLS_DTPREL64: + case BFD_RELOC_RISCV_TPREL_HI20: + case BFD_RELOC_RISCV_TPREL_LO12_I: + case BFD_RELOC_RISCV_TPREL_LO12_S: + case BFD_RELOC_RISCV_TPREL_ADD: + S_SET_THREAD_LOCAL (fixP->fx_addsy); + /* Fall through. */ + + case BFD_RELOC_RISCV_GOT_HI20: + case BFD_RELOC_RISCV_PCREL_HI20: + case BFD_RELOC_RISCV_HI20: + case BFD_RELOC_RISCV_LO12_I: + case BFD_RELOC_RISCV_LO12_S: + case BFD_RELOC_RISCV_ADD8: + case BFD_RELOC_RISCV_ADD16: + case BFD_RELOC_RISCV_ADD32: + case BFD_RELOC_RISCV_ADD64: + case BFD_RELOC_RISCV_SUB8: + case BFD_RELOC_RISCV_SUB16: + case BFD_RELOC_RISCV_SUB32: + case BFD_RELOC_RISCV_SUB64: + gas_assert (fixP->fx_addsy != NULL); + /* Nothing needed to do. The value comes from the reloc entry. */ + break; + + case BFD_RELOC_64: + case BFD_RELOC_32: + case BFD_RELOC_16: + case BFD_RELOC_8: + if (fixP->fx_addsy && fixP->fx_subsy) + { + fixP->fx_next = xmemdup (fixP, sizeof (*fixP), sizeof (*fixP)); + fixP->fx_next->fx_addsy = fixP->fx_subsy; + fixP->fx_next->fx_subsy = NULL; + fixP->fx_next->fx_offset = 0; + fixP->fx_subsy = NULL; + + switch (fixP->fx_r_type) + { + case BFD_RELOC_64: + fixP->fx_r_type = BFD_RELOC_RISCV_ADD64; + fixP->fx_next->fx_r_type = BFD_RELOC_RISCV_SUB64; + break; + + case BFD_RELOC_32: + fixP->fx_r_type = BFD_RELOC_RISCV_ADD32; + fixP->fx_next->fx_r_type = BFD_RELOC_RISCV_SUB32; + break; + + case BFD_RELOC_16: + fixP->fx_r_type = BFD_RELOC_RISCV_ADD16; + fixP->fx_next->fx_r_type = BFD_RELOC_RISCV_SUB16; + break; + + case BFD_RELOC_8: + fixP->fx_r_type = BFD_RELOC_RISCV_ADD8; + fixP->fx_next->fx_r_type = BFD_RELOC_RISCV_SUB8; + + default: + /* This case is unreachable. */ + abort (); + } + } + /* Fall through. */ + + case BFD_RELOC_RVA: + /* If we are deleting this reloc entry, we must fill in the + value now. This can happen if we have a .word which is not + resolved when it appears but is later defined. */ + if (fixP->fx_addsy == NULL) + { + gas_assert (fixP->fx_size <= sizeof (valueT)); + md_number_to_chars ((char *) buf, *valP, fixP->fx_size); + fixP->fx_done = 1; + } + break; + + case BFD_RELOC_RISCV_JMP: + if (fixP->fx_addsy) + { + /* Fill in a tentative value to improve objdump readability. */ + bfd_vma target = S_GET_VALUE (fixP->fx_addsy) + *valP; + bfd_vma delta = target - md_pcrel_from (fixP); + bfd_putl32 (bfd_getl32 (buf) | ENCODE_UJTYPE_IMM (delta), buf); + } + break; + + case BFD_RELOC_12_PCREL: + if (fixP->fx_addsy) + { + /* Fill in a tentative value to improve objdump readability. */ + bfd_vma target = S_GET_VALUE (fixP->fx_addsy) + *valP; + bfd_vma delta = target - md_pcrel_from (fixP); + bfd_putl32 (bfd_getl32 (buf) | ENCODE_SBTYPE_IMM (delta), buf); + } + break; + + case BFD_RELOC_RISCV_RVC_BRANCH: + if (fixP->fx_addsy) + { + /* Fill in a tentative value to improve objdump readability. */ + bfd_vma target = S_GET_VALUE (fixP->fx_addsy) + *valP; + bfd_vma delta = target - md_pcrel_from (fixP); + bfd_putl16 (bfd_getl16 (buf) | ENCODE_RVC_B_IMM (delta), buf); + } + break; + + case BFD_RELOC_RISCV_RVC_JUMP: + if (fixP->fx_addsy) + { + /* Fill in a tentative value to improve objdump readability. */ + bfd_vma target = S_GET_VALUE (fixP->fx_addsy) + *valP; + bfd_vma delta = target - md_pcrel_from (fixP); + bfd_putl16 (bfd_getl16 (buf) | ENCODE_RVC_J_IMM (delta), buf); + } + break; + + case BFD_RELOC_RISCV_PCREL_LO12_S: + case BFD_RELOC_RISCV_PCREL_LO12_I: + case BFD_RELOC_RISCV_CALL: + case BFD_RELOC_RISCV_CALL_PLT: + case BFD_RELOC_RISCV_ALIGN: + break; + + default: + /* We ignore generic BFD relocations we don't know about. */ + if (bfd_reloc_type_lookup (stdoutput, fixP->fx_r_type) != NULL) + as_fatal (_("internal error: bad relocation #%d"), fixP->fx_r_type); + } +} + +/* This structure is used to hold a stack of .option values. */ + +struct riscv_option_stack +{ + struct riscv_option_stack *next; + struct riscv_set_options options; +}; + +static struct riscv_option_stack *riscv_opts_stack; + +/* Handle the .option pseudo-op. */ + +static void +s_riscv_option (int x ATTRIBUTE_UNUSED) +{ + char *name = input_line_pointer, ch; + + while (!is_end_of_line[(unsigned char) *input_line_pointer]) + ++input_line_pointer; + ch = *input_line_pointer; + *input_line_pointer = '\0'; + + if (strcmp (name, "rvc") == 0) + riscv_set_rvc (TRUE); + else if (strcmp (name, "norvc") == 0) + riscv_set_rvc (FALSE); + else if (strcmp (name, "pic") == 0) + riscv_opts.pic = TRUE; + else if (strcmp (name, "nopic") == 0) + riscv_opts.pic = FALSE; + else if (strcmp (name, "soft-float") == 0) + float_mode = FLOAT_MODE_SOFT; + else if (strcmp (name, "hard-float") == 0) + float_mode = FLOAT_MODE_HARD; + else if (strcmp (name, "push") == 0) + { + struct riscv_option_stack *s; + + s = (struct riscv_option_stack *) xmalloc (sizeof *s); + s->next = riscv_opts_stack; + s->options = riscv_opts; + riscv_opts_stack = s; + } + else if (strcmp (name, "pop") == 0) + { + struct riscv_option_stack *s; + + s = riscv_opts_stack; + if (s == NULL) + as_bad (_(".option pop with no .option push")); + else + { + riscv_opts = s->options; + riscv_opts_stack = s->next; + free (s); + } + } + else + { + as_warn (_("Unrecognized .option directive: %s\n"), name); + } + *input_line_pointer = ch; + demand_empty_rest_of_line (); +} + +/* Handle the .dtprelword and .dtpreldword pseudo-ops. They generate + a 32-bit or 64-bit DTP-relative relocation (BYTES says which) for + use in DWARF debug information. */ + +static void +s_dtprel (int bytes) +{ + expressionS ex; + char *p; + + expression (&ex); + + if (ex.X_op != O_symbol) + { + as_bad (_("Unsupported use of %s"), (bytes == 8 + ? ".dtpreldword" + : ".dtprelword")); + ignore_rest_of_line (); + } + + p = frag_more (bytes); + md_number_to_chars (p, 0, bytes); + fix_new_exp (frag_now, p - frag_now->fr_literal, bytes, &ex, FALSE, + (bytes == 8 + ? BFD_RELOC_RISCV_TLS_DTPREL64 + : BFD_RELOC_RISCV_TLS_DTPREL32)); + + demand_empty_rest_of_line (); +} + +/* Handle the .bss pseudo-op. */ + +static void +s_bss (int ignore ATTRIBUTE_UNUSED) +{ + subseg_set (bss_section, 0); + demand_empty_rest_of_line (); +} + +/* Align to a given power of two. */ + +static void +s_align (int bytes_p) +{ + int fill_value = 0, fill_value_specified = 0; + int min_text_alignment = riscv_opts.rvc ? 2 : 4; + int alignment = get_absolute_expression(), bytes; + + if (bytes_p) + { + bytes = alignment; + if (bytes < 1 || (bytes & (bytes-1)) != 0) + as_bad (_("alignment not a power of 2: %d"), bytes); + for (alignment = 0; bytes > 1; bytes >>= 1) + alignment++; + } + + bytes = 1 << alignment; + + if (alignment < 0 || alignment > 31) + as_bad (_("unsatisfiable alignment: %d"), alignment); + + if (*input_line_pointer == ',') + { + ++input_line_pointer; + fill_value = get_absolute_expression (); + fill_value_specified = 1; + } + + if (!fill_value_specified + && subseg_text_p (now_seg) + && bytes > min_text_alignment) + { + /* Emit the worst-case NOP string. The linker will delete any + unnecessary NOPs. This allows us to support code alignment + in spite of linker relaxations. */ + bfd_vma i, worst_case_bytes = bytes - min_text_alignment; + char *nops = frag_more (worst_case_bytes); + for (i = 0; i < worst_case_bytes - 2; i += 4) + md_number_to_chars (nops + i, RISCV_NOP, 4); + if (i < worst_case_bytes) + md_number_to_chars (nops + i, RVC_NOP, 2); + + expressionS ex; + ex.X_op = O_constant; + ex.X_add_number = worst_case_bytes; + + fix_new_exp (frag_now, nops - frag_now->fr_literal, 0, + &ex, FALSE, BFD_RELOC_RISCV_ALIGN); + } + else if (alignment) + frag_align (alignment, fill_value, 0); + + record_alignment (now_seg, alignment); + + demand_empty_rest_of_line (); +} + +int +md_estimate_size_before_relax (fragS *fragp, asection *segtype) +{ + return (fragp->fr_var = relaxed_branch_length (fragp, segtype, FALSE)); +} + +/* Translate internal representation of relocation info to BFD target + format. */ + +arelent * +tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp) +{ + arelent *reloc = (arelent *) xmalloc (sizeof (arelent)); + + reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *)); + *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); + reloc->address = fixp->fx_frag->fr_address + fixp->fx_where; + reloc->addend = fixp->fx_addnumber; + + reloc->howto = bfd_reloc_type_lookup (stdoutput, fixp->fx_r_type); + if (reloc->howto == NULL) + { + if ((fixp->fx_r_type == BFD_RELOC_16 || fixp->fx_r_type == BFD_RELOC_8) + && fixp->fx_addsy != NULL && fixp->fx_subsy != NULL) + { + /* We don't have R_RISCV_8/16, but for this special case, + we can use R_RISCV_ADD8/16 with R_RISCV_SUB8/16. */ + return reloc; + } + + as_bad_where (fixp->fx_file, fixp->fx_line, + _("cannot represent %s relocation in object file"), + bfd_get_reloc_code_name (fixp->fx_r_type)); + return NULL; + } + + return reloc; +} + +int +riscv_relax_frag (asection *sec, fragS *fragp, long stretch ATTRIBUTE_UNUSED) +{ + if (RELAX_BRANCH_P (fragp->fr_subtype)) + { + offsetT old_var = fragp->fr_var; + fragp->fr_var = relaxed_branch_length (fragp, sec, TRUE); + return fragp->fr_var - old_var; + } + + return 0; +} + +/* Expand far branches to multi-instruction sequences. */ + +static void +md_convert_frag_branch (fragS *fragp) +{ + bfd_byte *buf; + expressionS exp; + fixS *fixp; + insn_t insn; + int rs1, reloc; + + buf = (bfd_byte *)fragp->fr_literal + fragp->fr_fix; + + exp.X_op = O_symbol; + exp.X_add_symbol = fragp->fr_symbol; + exp.X_add_number = fragp->fr_offset; + + gas_assert (fragp->fr_var == RELAX_BRANCH_LENGTH (fragp->fr_subtype)); + + if (RELAX_BRANCH_RVC (fragp->fr_subtype)) + { + switch (RELAX_BRANCH_LENGTH (fragp->fr_subtype)) + { + case 8: + case 4: + /* Expand the RVC branch into a RISC-V one. */ + insn = bfd_getl16 (buf); + rs1 = 8 + ((insn >> OP_SH_CRS1S) & OP_MASK_CRS1S); + if ((insn & MASK_C_J) == MATCH_C_J) + insn = MATCH_JAL; + else if ((insn & MASK_C_JAL) == MATCH_C_JAL) + insn = MATCH_JAL | (X_RA << OP_SH_RD); + else if ((insn & MASK_C_BEQZ) == MATCH_C_BEQZ) + insn = MATCH_BEQ | (rs1 << OP_SH_RS1); + else if ((insn & MASK_C_BNEZ) == MATCH_C_BNEZ) + insn = MATCH_BNE | (rs1 << OP_SH_RS1); + else + abort (); + bfd_putl32 (insn, buf); + break; + + case 6: + /* Invert the branch condition. Branch over the jump. */ + insn = bfd_getl16 (buf); + insn ^= MATCH_C_BEQZ ^ MATCH_C_BNEZ; + insn |= ENCODE_RVC_B_IMM (6); + bfd_putl16 (insn, buf); + buf += 2; + goto jump; + + case 2: + /* Just keep the RVC branch. */ + reloc = RELAX_BRANCH_UNCOND (fragp->fr_subtype) + ? BFD_RELOC_RISCV_RVC_JUMP : BFD_RELOC_RISCV_RVC_BRANCH; + fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal, + 2, &exp, FALSE, reloc); + buf += 2; + goto done; + + default: + abort(); + } + } + + switch (RELAX_BRANCH_LENGTH (fragp->fr_subtype)) + { + case 8: + gas_assert (!RELAX_BRANCH_UNCOND (fragp->fr_subtype)); + + /* Invert the branch condition. Branch over the jump. */ + insn = bfd_getl32 (buf); + insn ^= MATCH_BEQ ^ MATCH_BNE; + insn |= ENCODE_SBTYPE_IMM (8); + md_number_to_chars ((char *) buf, insn, 4); + buf += 4; + +jump: + /* Jump to the target. */ + fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal, + 4, &exp, FALSE, BFD_RELOC_RISCV_JMP); + md_number_to_chars ((char *) buf, MATCH_JAL, 4); + buf += 4; + break; + + case 4: + reloc = RELAX_BRANCH_UNCOND (fragp->fr_subtype) + ? BFD_RELOC_RISCV_JMP : BFD_RELOC_12_PCREL; + fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal, + 4, &exp, FALSE, reloc); + buf += 4; + break; + + default: + abort (); + } + +done: + fixp->fx_file = fragp->fr_file; + fixp->fx_line = fragp->fr_line; + + gas_assert (buf == (bfd_byte *)fragp->fr_literal + + fragp->fr_fix + fragp->fr_var); + + fragp->fr_fix += fragp->fr_var; +} + +/* Relax a machine dependent frag. This returns the amount by which + the current size of the frag should change. */ + +void +md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT asec ATTRIBUTE_UNUSED, + fragS *fragp) +{ + gas_assert (RELAX_BRANCH_P (fragp->fr_subtype)); + md_convert_frag_branch (fragp); +} + +void +md_show_usage (FILE *stream) +{ + fprintf (stream, _("\ +RISC-V options:\n\ + -m32 assemble RV32 code\n\ + -m64 assemble RV64 code (default)\n\ + -fpic generate position-independent code\n\ + -fno-pic don't generate position-independent code (default)\n\ + -msoft-float don't use F registers for floating-point values\n\ + -mhard-float use F registers for floating-point values (default)\n\ + -mno-rvc disable the C extension for compressed instructions (default)\n\ + -mrvc enable the C extension for compressed instructions\n\ + -march=ISA set the RISC-V architecture, RV64IMAFD by default\n\ +")); +} + +/* Standard calling conventions leave the CFA at SP on entry. */ +void +riscv_cfi_frame_initial_instructions (void) +{ + cfi_add_CFA_def_cfa_register (X_SP); +} + +int +tc_riscv_regname_to_dw2regnum (char *regname) +{ + int reg; + + if ((reg = reg_lookup_internal (regname, RCLASS_GPR)) >= 0) + return reg; + + if ((reg = reg_lookup_internal (regname, RCLASS_FPR)) >= 0) + return reg + 32; + + as_bad (_("unknown register `%s'"), regname); + return -1; +} + +void +riscv_elf_final_processing (void) +{ + enum float_mode elf_float_mode = float_mode; + + elf_elfheader (stdoutput)->e_flags |= elf_flags; + + if (elf_float_mode == FLOAT_MODE_DEFAULT) + { + struct riscv_subset *subset; + + /* Assume soft-float unless D extension is present. */ + elf_float_mode = FLOAT_MODE_SOFT; + + for (subset = riscv_subsets; subset != NULL; subset = subset->next) + if (strcasecmp (subset->name, "D") == 0) + elf_float_mode = FLOAT_MODE_HARD; + } + + if (elf_float_mode == FLOAT_MODE_SOFT) + elf_elfheader (stdoutput)->e_flags |= EF_RISCV_SOFT_FLOAT; +} + +/* Parse the .sleb128 and .uleb128 pseudos. Only allow constant expressions, + since these directives break relaxation when used with symbol deltas. */ + +static void +s_riscv_leb128 (int sign) +{ + expressionS exp; + char *save_in = input_line_pointer; + + expression (&exp); + if (exp.X_op != O_constant) + as_bad (_("non-constant .%cleb128 is not supported"), sign ? 's' : 'u'); + demand_empty_rest_of_line (); + + input_line_pointer = save_in; + return s_leb128 (sign); +} + +/* Pseudo-op table. */ + +static const pseudo_typeS riscv_pseudo_table[] = +{ + /* RISC-V-specific pseudo-ops. */ + {"option", s_riscv_option, 0}, + {"half", cons, 2}, + {"word", cons, 4}, + {"dword", cons, 8}, + {"dtprelword", s_dtprel, 4}, + {"dtpreldword", s_dtprel, 8}, + {"bss", s_bss, 0}, + {"align", s_align, 0}, + {"p2align", s_align, 0}, + {"balign", s_align, 1}, + {"uleb128", s_riscv_leb128, 0}, + {"sleb128", s_riscv_leb128, 1}, + + { NULL, NULL, 0 }, +}; + +void +riscv_pop_insert (void) +{ + extern void pop_insert (const pseudo_typeS *); + + pop_insert (riscv_pseudo_table); +} diff --git a/gas/config/tc-riscv.h b/gas/config/tc-riscv.h new file mode 100644 index 0000000000..c2a11cefe9 --- /dev/null +++ b/gas/config/tc-riscv.h @@ -0,0 +1,101 @@ +/* tc-riscv.h -- header file for tc-riscv.c. + Copyright 2011-2016 Free Software Foundation, Inc. + + Contributed by Andrew Waterman (andrew@sifive.com). + Based on MIPS target. + + This file is part of GAS. + + GAS is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. + + GAS is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; see the file COPYING3. If not, + see . */ + +#ifndef TC_RISCV +#define TC_RISCV + +#include "opcode/riscv.h" + +struct frag; +struct expressionS; + +#define TARGET_BYTES_BIG_ENDIAN 0 + +#define TARGET_ARCH bfd_arch_riscv + +#define WORKING_DOT_WORD 1 +#define LOCAL_LABELS_FB 1 + +/* Symbols named FAKE_LABEL_NAME are emitted when generating DWARF, so make + sure FAKE_LABEL_NAME is printable. It still must be distinct from any + real label name. So, append a space, which other labels can't contain. */ +#define FAKE_LABEL_NAME ".L0 " + +#define md_relax_frag(segment, fragp, stretch) \ + riscv_relax_frag (segment, fragp, stretch) +extern int riscv_relax_frag (asection *, struct frag *, long); + +#define md_section_align(seg,size) (size) +#define md_undefined_symbol(name) (0) +#define md_operand(x) + +/* FIXME: it is unclear if this is used, or if it is even correct. */ +#define MAX_MEM_FOR_RS_ALIGN_CODE (1 + 2) + +/* The ISA of the target may change based on command-line arguments. */ +#define TARGET_FORMAT riscv_target_format() +extern const char * riscv_target_format (void); + +#define md_after_parse_args() riscv_after_parse_args() +extern void riscv_after_parse_args (void); + +#define md_parse_long_option(arg) riscv_parse_long_option (arg) +extern int riscv_parse_long_option (const char *); + +/* Let the linker resolve all the relocs due to relaxation. */ +#define tc_fix_adjustable(fixp) 0 +#define md_allow_local_subtract(l,r,s) 0 + +/* Values passed to md_apply_fix don't include symbol values. */ +#define MD_APPLY_SYM_VALUE(FIX) 0 + +/* Global syms must not be resolved, to support ELF shared libraries. */ +#define EXTERN_FORCE_RELOC \ + (OUTPUT_FLAVOR == bfd_target_elf_flavour) + +/* Postpone text-section label subtraction calculation until linking, since + linker relaxations might change the deltas. */ +#define TC_FORCE_RELOCATION_SUB_SAME(FIX, SEG) ((SEG)->flags & SEC_CODE) +#define TC_FORCE_RELOCATION_SUB_LOCAL(FIX, SEG) 1 +#define TC_VALIDATE_FIX_SUB(FIX, SEG) 1 +#define TC_FORCE_RELOCATION_LOCAL(FIX) 1 +#define DIFF_EXPR_OK 1 + +extern void riscv_pop_insert (void); +#define md_pop_insert() riscv_pop_insert () + +#define TARGET_USE_CFIPOP 1 + +#define tc_cfi_frame_initial_instructions riscv_cfi_frame_initial_instructions +extern void riscv_cfi_frame_initial_instructions (void); + +#define tc_regname_to_dw2regnum tc_riscv_regname_to_dw2regnum +extern int tc_riscv_regname_to_dw2regnum (char *); + +extern unsigned xlen; +#define DWARF2_DEFAULT_RETURN_COLUMN X_RA +#define DWARF2_CIE_DATA_ALIGNMENT (-(int) (xlen / 8)) + +#define elf_tc_final_processing riscv_elf_final_processing +extern void riscv_elf_final_processing (void); + +#endif /* TC_RISCV */ diff --git a/gas/configure b/gas/configure index 6fae0d9d70..08d4ed0dcb 100755 --- a/gas/configure +++ b/gas/configure @@ -12552,7 +12552,7 @@ $as_echo "#define NDS32_DEFAULT_AUDIO_EXT 1" >>confdefs.h $as_echo "$enable_audio_ext" >&6; } ;; - i386 | s390 | sparc) + i386 | riscv | s390 | sparc) if test $this_target = $target ; then cat >>confdefs.h <<_ACEOF diff --git a/gas/configure.ac b/gas/configure.ac index 13f51073c0..c0d59897c8 100644 --- a/gas/configure.ac +++ b/gas/configure.ac @@ -510,7 +510,7 @@ changequote([,])dnl AC_MSG_RESULT($enable_audio_ext) ;; - i386 | s390 | sparc) + i386 | riscv | s390 | sparc) if test $this_target = $target ; then AC_DEFINE_UNQUOTED(DEFAULT_ARCH, "${arch}", [Default architecture.]) fi diff --git a/gas/configure.tgt b/gas/configure.tgt index e2df65957b..3e230cba93 100644 --- a/gas/configure.tgt +++ b/gas/configure.tgt @@ -87,6 +87,8 @@ case ${cpu} in pj*) cpu_type=pj endian=big ;; powerpc*le*) cpu_type=ppc endian=little ;; powerpc*) cpu_type=ppc endian=big ;; + riscv32*) cpu_type=riscv endian=little arch=riscv32 ;; + riscv64*) cpu_type=riscv endian=little arch=riscv64 ;; rs6000*) cpu_type=ppc ;; rl78*) cpu_type=rl78 ;; rx) cpu_type=rx ;; @@ -391,6 +393,8 @@ case ${generic_target} in ppc-*-kaos*) fmt=elf ;; ppc-*-lynxos*) fmt=elf em=lynx ;; + riscv*-*-*) fmt=elf endian=little em=linux ;; + s390-*-linux-*) fmt=elf em=linux ;; s390-*-tpf*) fmt=elf ;; @@ -488,7 +492,7 @@ case ${generic_target} in esac case ${cpu_type} in - aarch64 | alpha | arm | i386 | ia64 | microblaze | mips | ns32k | or1k | or1knd | pdp11 | ppc | sparc | z80 | z8k) + aarch64 | alpha | arm | i386 | ia64 | microblaze | mips | ns32k | or1k | or1knd | pdp11 | ppc | riscv | sparc | z80 | z8k) bfd_gas=yes ;; esac diff --git a/gas/doc/as.texinfo b/gas/doc/as.texinfo index 82cc72dd2b..b1d94d5414 100644 --- a/gas/doc/as.texinfo +++ b/gas/doc/as.texinfo @@ -1647,6 +1647,25 @@ PowerPC processor. @end ifset +@ifset RISCV + +@ifclear man +@xref{RISC-V-Opts}, for the options available when @value{AS} is configured +for a RISC-V processor. +@end ifclear + +@ifset man +@c man begin OPTIONS +The following options are available when @value{AS} is configured for a +RISC-V processor. +@c man end +@c man begin INCLUDE +@include c-riscv.texi +@c ended inside the included file +@end ifset + +@end ifset + @c man begin OPTIONS @ifset RX See the info pages for documentation of the RX-specific options. diff --git a/gas/doc/c-riscv.texi b/gas/doc/c-riscv.texi new file mode 100644 index 0000000000..984b75c68f --- /dev/null +++ b/gas/doc/c-riscv.texi @@ -0,0 +1,48 @@ +@c Copyright (C) 2016 Free Software Foundation, Inc. +@c This is part of the GAS anual. +@c For copying conditions, see the file as.texinfo +@c man end + +@ifset GENERIC +@page +@node RISC-V-Dependent +@chapter RISC-V Dependent Features +@end ifset +@ifclear GENERIC +@node Machine Dependencies +@chapter RISC-V Dependent Features +@end ifclear + +@cindex RISC-V support +@menu +* RISC-V Options:: RISC-V Options +@end menu + +@node RISC-V Options +@section Options + +The following table lists all availiable RISC-V specific options + +@c man begin OPTIONS +@table @gcctabopt +@cindex @samp{-m32} option, RISC-V +@cindex @samp{-m64} option, RISC-V +@item -m32 | -m64 +Select the base ISA, either RV32 or RV64. + +@cindex @samp{-mrvc} option, RISC-V +@item -mrvc +Enables the C ISA subset for compressed instructions. + +@cindex @samp{-msoft-float} option, RISC-V +@cindex @samp{-mhard-float} option, RISC-V +@item -msoft-float | -mhard-float +Select the floating-point ABI, hard-float has F registers while soft-float +doesn't. + +@cindex @samp{-march=RV{32,64}{G,I}{M,}{A,}{F,}{D,}{C,}} option, RISC-V +@item -march=RV{32,64}{G,I}{M,}{A,}{F,}{D,}{C,} +Select the base isa, as specified by ISA. For example -march=RV32IMA. + +@end table +@c man end diff --git a/gas/testsuite/gas/all/gas.exp b/gas/testsuite/gas/all/gas.exp index bfb13ed22c..eb225fc2ce 100644 --- a/gas/testsuite/gas/all/gas.exp +++ b/gas/testsuite/gas/all/gas.exp @@ -159,10 +159,10 @@ case $target_triplet in { # These targets fail redef2 because they disallow redefined # symbols on relocs. setup_xfail "m68hc1*-*-*" "m6811-*-*" "m6812-*-*" "rl78-*-*" - setup_xfail "rx-*-*" "vax*-*-*" "xgate*-*-*" "z8k-*-*" + setup_xfail "riscv*-*-*" "rx-*-*" "vax*-*-*" "xgate*-*-*" "z8k-*-*" run_dump_test redef2 setup_xfail "m68hc1*-*-*" "m6811-*-*" "m6812-*-*" "rl78-*-*" - setup_xfail "rx-*-*" "vax*-*-*" "xgate*-*-*" "z8k-*-*" + setup_xfail "riscv*-*-*" "rx-*-*" "vax*-*-*" "xgate*-*-*" "z8k-*-*" # rs6000-aix disallows redefinition via .comm. setup_xfail "*-*-aix*" # SOM uses a different syntax for .comm @@ -277,8 +277,8 @@ if { ![istarget *c30*-*-*] && ![istarget hppa*-*-*] } then { # The vax fails because VMS can apparently actually handle this # case in relocs, so gas doesn't handle it itself. - # msp430 and mn10[23]00 emit two relocs to handle the difference of two symbols. - setup_xfail "mn10200-*-*" "mn10300*-*-*" "msp430*-*-*" "vax*-*-vms*" + # msp430, mn10[23]00 and riscv emit two relocs to handle the difference of two symbols. + setup_xfail "mn10200-*-*" "mn10300*-*-*" "msp430*-*-*" "riscv*-*-*" "vax*-*-vms*" do_930509a } diff --git a/gas/testsuite/gas/elf/elf.exp b/gas/testsuite/gas/elf/elf.exp index d57665e5fd..df9f4ba7b0 100644 --- a/gas/testsuite/gas/elf/elf.exp +++ b/gas/testsuite/gas/elf/elf.exp @@ -120,12 +120,14 @@ if { [is_elf_format] } then { run_dump_test "group2" case $target_triplet in { { hppa64*-*-hpux* } { } + { riscv*-*-* } { } default { run_dump_test "groupautoa" } } case $target_triplet in { { hppa64*-*-hpux* } { } + { riscv*-*-* } { } { xtensa*-*-* } { } default { run_dump_test "groupautob" @@ -144,6 +146,7 @@ if { [is_elf_format] } then { { mn10300-*-* } { } { msp43*-*-* } { } { rl78-*-* } { } + { riscv*-*-* } { } { rx-*-* } { } default { # The next test can fail if the target does not convert fixups diff --git a/gas/testsuite/gas/riscv/riscv.exp b/gas/testsuite/gas/riscv/riscv.exp new file mode 100644 index 0000000000..27d73cddb9 --- /dev/null +++ b/gas/testsuite/gas/riscv/riscv.exp @@ -0,0 +1,23 @@ +# Expect script for RISC-V assembler tests. +# Copyright (C) 2011-2016 Free Software Foundation, Inc. +# +# This file is part of the GNU Binutils. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 3 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, +# MA 02110-1301, USA. + +if [istarget riscv*-*-*] { + run_dump_test "t_insns" +} diff --git a/gas/testsuite/gas/riscv/t_insns.d b/gas/testsuite/gas/riscv/t_insns.d new file mode 100644 index 0000000000..720f0db293 --- /dev/null +++ b/gas/testsuite/gas/riscv/t_insns.d @@ -0,0 +1,10 @@ +#as: +#objdump: -dr + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : +[ ]+0:[ ]+00000013[ ]+nop diff --git a/gas/testsuite/gas/riscv/t_insns.s b/gas/testsuite/gas/riscv/t_insns.s new file mode 100644 index 0000000000..9945688331 --- /dev/null +++ b/gas/testsuite/gas/riscv/t_insns.s @@ -0,0 +1,2 @@ +target: + nop diff --git a/include/ChangeLog b/include/ChangeLog index 7b44b04bb9..c4ddcb2ffe 100644 --- a/include/ChangeLog +++ b/include/ChangeLog @@ -1,3 +1,13 @@ +2016-11-01 Palmer Dabbelt + Andrew Waterman + + Add support for RISC-V architecture. + * dis-asm.h: Add prototypes for print_insn_riscv and + print_riscv_disassembler_options. + * elf/riscv.h: New file. + * opcode/riscv-opc.h: New file. + * opcode/riscv.h: New file. + 2016-10-17 Nick Clifton * elf/common.h (DT_SYMTAB_SHNDX): Define. diff --git a/include/dis-asm.h b/include/dis-asm.h index 05bfa37d9b..2cefff4115 100644 --- a/include/dis-asm.h +++ b/include/dis-asm.h @@ -263,6 +263,7 @@ extern int print_insn_little_arm (bfd_vma, disassemble_info *); extern int print_insn_little_mips (bfd_vma, disassemble_info *); extern int print_insn_little_nios2 (bfd_vma, disassemble_info *); extern int print_insn_little_powerpc (bfd_vma, disassemble_info *); +extern int print_insn_riscv (bfd_vma, disassemble_info *); extern int print_insn_little_score (bfd_vma, disassemble_info *); extern int print_insn_lm32 (bfd_vma, disassemble_info *); extern int print_insn_m32c (bfd_vma, disassemble_info *); @@ -327,6 +328,7 @@ extern void print_aarch64_disassembler_options (FILE *); extern void print_i386_disassembler_options (FILE *); extern void print_mips_disassembler_options (FILE *); extern void print_ppc_disassembler_options (FILE *); +extern void print_riscv_disassembler_options (FILE *); extern void print_arm_disassembler_options (FILE *); extern void print_arc_disassembler_options (FILE *); extern void parse_arm_disassembler_option (char *); diff --git a/include/elf/riscv.h b/include/elf/riscv.h new file mode 100644 index 0000000000..8415659092 --- /dev/null +++ b/include/elf/riscv.h @@ -0,0 +1,92 @@ +/* RISC-V ELF support for BFD. + Copyright 2011-2016 Free Software Foundation, Inc. + + Contributed by Andrew Waterman (andrew@sifive.com). + Based on MIPS ELF support for BFD, by Ian Lance Taylor. + + This file is part of BFD, the Binary File Descriptor library. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; see the file COPYING3. If not, + see . */ + +/* This file holds definitions specific to the RISCV ELF ABI. Note + that most of this is not actually implemented by BFD. */ + +#ifndef _ELF_RISCV_H +#define _ELF_RISCV_H + +#include "elf/reloc-macros.h" +#include "libiberty.h" + +/* Relocation types. */ +START_RELOC_NUMBERS (elf_riscv_reloc_type) + /* Relocation types used by the dynamic linker. */ + RELOC_NUMBER (R_RISCV_NONE, 0) + RELOC_NUMBER (R_RISCV_32, 1) + RELOC_NUMBER (R_RISCV_64, 2) + RELOC_NUMBER (R_RISCV_RELATIVE, 3) + RELOC_NUMBER (R_RISCV_COPY, 4) + RELOC_NUMBER (R_RISCV_JUMP_SLOT, 5) + RELOC_NUMBER (R_RISCV_TLS_DTPMOD32, 6) + RELOC_NUMBER (R_RISCV_TLS_DTPMOD64, 7) + RELOC_NUMBER (R_RISCV_TLS_DTPREL32, 8) + RELOC_NUMBER (R_RISCV_TLS_DTPREL64, 9) + RELOC_NUMBER (R_RISCV_TLS_TPREL32, 10) + RELOC_NUMBER (R_RISCV_TLS_TPREL64, 11) + + /* Relocation types not used by the dynamic linker. */ + RELOC_NUMBER (R_RISCV_BRANCH, 16) + RELOC_NUMBER (R_RISCV_JAL, 17) + RELOC_NUMBER (R_RISCV_CALL, 18) + RELOC_NUMBER (R_RISCV_CALL_PLT, 19) + RELOC_NUMBER (R_RISCV_GOT_HI20, 20) + RELOC_NUMBER (R_RISCV_TLS_GOT_HI20, 21) + RELOC_NUMBER (R_RISCV_TLS_GD_HI20, 22) + RELOC_NUMBER (R_RISCV_PCREL_HI20, 23) + RELOC_NUMBER (R_RISCV_PCREL_LO12_I, 24) + RELOC_NUMBER (R_RISCV_PCREL_LO12_S, 25) + RELOC_NUMBER (R_RISCV_HI20, 26) + RELOC_NUMBER (R_RISCV_LO12_I, 27) + RELOC_NUMBER (R_RISCV_LO12_S, 28) + RELOC_NUMBER (R_RISCV_TPREL_HI20, 29) + RELOC_NUMBER (R_RISCV_TPREL_LO12_I, 30) + RELOC_NUMBER (R_RISCV_TPREL_LO12_S, 31) + RELOC_NUMBER (R_RISCV_TPREL_ADD, 32) + RELOC_NUMBER (R_RISCV_ADD8, 33) + RELOC_NUMBER (R_RISCV_ADD16, 34) + RELOC_NUMBER (R_RISCV_ADD32, 35) + RELOC_NUMBER (R_RISCV_ADD64, 36) + RELOC_NUMBER (R_RISCV_SUB8, 37) + RELOC_NUMBER (R_RISCV_SUB16, 38) + RELOC_NUMBER (R_RISCV_SUB32, 39) + RELOC_NUMBER (R_RISCV_SUB64, 40) + RELOC_NUMBER (R_RISCV_GNU_VTINHERIT, 41) + RELOC_NUMBER (R_RISCV_GNU_VTENTRY, 42) + RELOC_NUMBER (R_RISCV_ALIGN, 43) + RELOC_NUMBER (R_RISCV_RVC_BRANCH, 44) + RELOC_NUMBER (R_RISCV_RVC_JUMP, 45) + RELOC_NUMBER (R_RISCV_RVC_LUI, 46) + RELOC_NUMBER (R_RISCV_GPREL_I, 47) + RELOC_NUMBER (R_RISCV_GPREL_S, 48) +END_RELOC_NUMBERS (R_RISCV_max) + +/* Processor specific flags for the ELF header e_flags field. */ + +/* File may contain compressed instructions. */ +#define EF_RISCV_RVC 0x0001 + +/* File uses the soft-float calling convention. */ +#define EF_RISCV_SOFT_FLOAT 0x0002 + +#endif /* _ELF_RISCV_H */ diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h new file mode 100644 index 0000000000..d10c7f8145 --- /dev/null +++ b/include/opcode/riscv-opc.h @@ -0,0 +1,1160 @@ +/* Automatically generated by parse-opcodes. */ +#ifndef RISCV_ENCODING_H +#define RISCV_ENCODING_H +#define MATCH_SLLI_RV32 0x1013 +#define MASK_SLLI_RV32 0xfe00707f +#define MATCH_SRLI_RV32 0x5013 +#define MASK_SRLI_RV32 0xfe00707f +#define MATCH_SRAI_RV32 0x40005013 +#define MASK_SRAI_RV32 0xfe00707f +#define MATCH_FRFLAGS 0x102073 +#define MASK_FRFLAGS 0xfffff07f +#define MATCH_FSFLAGS 0x101073 +#define MASK_FSFLAGS 0xfff0707f +#define MATCH_FSFLAGSI 0x105073 +#define MASK_FSFLAGSI 0xfff0707f +#define MATCH_FRRM 0x202073 +#define MASK_FRRM 0xfffff07f +#define MATCH_FSRM 0x201073 +#define MASK_FSRM 0xfff0707f +#define MATCH_FSRMI 0x205073 +#define MASK_FSRMI 0xfff0707f +#define MATCH_FSCSR 0x301073 +#define MASK_FSCSR 0xfff0707f +#define MATCH_FRCSR 0x302073 +#define MASK_FRCSR 0xfffff07f +#define MATCH_RDCYCLE 0xc0002073 +#define MASK_RDCYCLE 0xfffff07f +#define MATCH_RDTIME 0xc0102073 +#define MASK_RDTIME 0xfffff07f +#define MATCH_RDINSTRET 0xc0202073 +#define MASK_RDINSTRET 0xfffff07f +#define MATCH_RDCYCLEH 0xc8002073 +#define MASK_RDCYCLEH 0xfffff07f +#define MATCH_RDTIMEH 0xc8102073 +#define MASK_RDTIMEH 0xfffff07f +#define MATCH_RDINSTRETH 0xc8202073 +#define MASK_RDINSTRETH 0xfffff07f +#define MATCH_SCALL 0x73 +#define MASK_SCALL 0xffffffff +#define MATCH_SBREAK 0x100073 +#define MASK_SBREAK 0xffffffff +#define MATCH_BEQ 0x63 +#define MASK_BEQ 0x707f +#define MATCH_BNE 0x1063 +#define MASK_BNE 0x707f +#define MATCH_BLT 0x4063 +#define MASK_BLT 0x707f +#define MATCH_BGE 0x5063 +#define MASK_BGE 0x707f +#define MATCH_BLTU 0x6063 +#define MASK_BLTU 0x707f +#define MATCH_BGEU 0x7063 +#define MASK_BGEU 0x707f +#define MATCH_JALR 0x67 +#define MASK_JALR 0x707f +#define MATCH_JAL 0x6f +#define MASK_JAL 0x7f +#define MATCH_LUI 0x37 +#define MASK_LUI 0x7f +#define MATCH_AUIPC 0x17 +#define MASK_AUIPC 0x7f +#define MATCH_ADDI 0x13 +#define MASK_ADDI 0x707f +#define MATCH_SLLI 0x1013 +#define MASK_SLLI 0xfc00707f +#define MATCH_SLTI 0x2013 +#define MASK_SLTI 0x707f +#define MATCH_SLTIU 0x3013 +#define MASK_SLTIU 0x707f +#define MATCH_XORI 0x4013 +#define MASK_XORI 0x707f +#define MATCH_SRLI 0x5013 +#define MASK_SRLI 0xfc00707f +#define MATCH_SRAI 0x40005013 +#define MASK_SRAI 0xfc00707f +#define MATCH_ORI 0x6013 +#define MASK_ORI 0x707f +#define MATCH_ANDI 0x7013 +#define MASK_ANDI 0x707f +#define MATCH_ADD 0x33 +#define MASK_ADD 0xfe00707f +#define MATCH_SUB 0x40000033 +#define MASK_SUB 0xfe00707f +#define MATCH_SLL 0x1033 +#define MASK_SLL 0xfe00707f +#define MATCH_SLT 0x2033 +#define MASK_SLT 0xfe00707f +#define MATCH_SLTU 0x3033 +#define MASK_SLTU 0xfe00707f +#define MATCH_XOR 0x4033 +#define MASK_XOR 0xfe00707f +#define MATCH_SRL 0x5033 +#define MASK_SRL 0xfe00707f +#define MATCH_SRA 0x40005033 +#define MASK_SRA 0xfe00707f +#define MATCH_OR 0x6033 +#define MASK_OR 0xfe00707f +#define MATCH_AND 0x7033 +#define MASK_AND 0xfe00707f +#define MATCH_ADDIW 0x1b +#define MASK_ADDIW 0x707f +#define MATCH_SLLIW 0x101b +#define MASK_SLLIW 0xfe00707f +#define MATCH_SRLIW 0x501b +#define MASK_SRLIW 0xfe00707f +#define MATCH_SRAIW 0x4000501b +#define MASK_SRAIW 0xfe00707f +#define MATCH_ADDW 0x3b +#define MASK_ADDW 0xfe00707f +#define MATCH_SUBW 0x4000003b +#define MASK_SUBW 0xfe00707f +#define MATCH_SLLW 0x103b +#define MASK_SLLW 0xfe00707f +#define MATCH_SRLW 0x503b +#define MASK_SRLW 0xfe00707f +#define MATCH_SRAW 0x4000503b +#define MASK_SRAW 0xfe00707f +#define MATCH_LB 0x3 +#define MASK_LB 0x707f +#define MATCH_LH 0x1003 +#define MASK_LH 0x707f +#define MATCH_LW 0x2003 +#define MASK_LW 0x707f +#define MATCH_LD 0x3003 +#define MASK_LD 0x707f +#define MATCH_LBU 0x4003 +#define MASK_LBU 0x707f +#define MATCH_LHU 0x5003 +#define MASK_LHU 0x707f +#define MATCH_LWU 0x6003 +#define MASK_LWU 0x707f +#define MATCH_SB 0x23 +#define MASK_SB 0x707f +#define MATCH_SH 0x1023 +#define MASK_SH 0x707f +#define MATCH_SW 0x2023 +#define MASK_SW 0x707f +#define MATCH_SD 0x3023 +#define MASK_SD 0x707f +#define MATCH_FENCE 0xf +#define MASK_FENCE 0x707f +#define MATCH_FENCE_I 0x100f +#define MASK_FENCE_I 0x707f +#define MATCH_MUL 0x2000033 +#define MASK_MUL 0xfe00707f +#define MATCH_MULH 0x2001033 +#define MASK_MULH 0xfe00707f +#define MATCH_MULHSU 0x2002033 +#define MASK_MULHSU 0xfe00707f +#define MATCH_MULHU 0x2003033 +#define MASK_MULHU 0xfe00707f +#define MATCH_DIV 0x2004033 +#define MASK_DIV 0xfe00707f +#define MATCH_DIVU 0x2005033 +#define MASK_DIVU 0xfe00707f +#define MATCH_REM 0x2006033 +#define MASK_REM 0xfe00707f +#define MATCH_REMU 0x2007033 +#define MASK_REMU 0xfe00707f +#define MATCH_MULW 0x200003b +#define MASK_MULW 0xfe00707f +#define MATCH_DIVW 0x200403b +#define MASK_DIVW 0xfe00707f +#define MATCH_DIVUW 0x200503b +#define MASK_DIVUW 0xfe00707f +#define MATCH_REMW 0x200603b +#define MASK_REMW 0xfe00707f +#define MATCH_REMUW 0x200703b +#define MASK_REMUW 0xfe00707f +#define MATCH_AMOADD_W 0x202f +#define MASK_AMOADD_W 0xf800707f +#define MATCH_AMOXOR_W 0x2000202f +#define MASK_AMOXOR_W 0xf800707f +#define MATCH_AMOOR_W 0x4000202f +#define MASK_AMOOR_W 0xf800707f +#define MATCH_AMOAND_W 0x6000202f +#define MASK_AMOAND_W 0xf800707f +#define MATCH_AMOMIN_W 0x8000202f +#define MASK_AMOMIN_W 0xf800707f +#define MATCH_AMOMAX_W 0xa000202f +#define MASK_AMOMAX_W 0xf800707f +#define MATCH_AMOMINU_W 0xc000202f +#define MASK_AMOMINU_W 0xf800707f +#define MATCH_AMOMAXU_W 0xe000202f +#define MASK_AMOMAXU_W 0xf800707f +#define MATCH_AMOSWAP_W 0x800202f +#define MASK_AMOSWAP_W 0xf800707f +#define MATCH_LR_W 0x1000202f +#define MASK_LR_W 0xf9f0707f +#define MATCH_SC_W 0x1800202f +#define MASK_SC_W 0xf800707f +#define MATCH_AMOADD_D 0x302f +#define MASK_AMOADD_D 0xf800707f +#define MATCH_AMOXOR_D 0x2000302f +#define MASK_AMOXOR_D 0xf800707f +#define MATCH_AMOOR_D 0x4000302f +#define MASK_AMOOR_D 0xf800707f +#define MATCH_AMOAND_D 0x6000302f +#define MASK_AMOAND_D 0xf800707f +#define MATCH_AMOMIN_D 0x8000302f +#define MASK_AMOMIN_D 0xf800707f +#define MATCH_AMOMAX_D 0xa000302f +#define MASK_AMOMAX_D 0xf800707f +#define MATCH_AMOMINU_D 0xc000302f +#define MASK_AMOMINU_D 0xf800707f +#define MATCH_AMOMAXU_D 0xe000302f +#define MASK_AMOMAXU_D 0xf800707f +#define MATCH_AMOSWAP_D 0x800302f +#define MASK_AMOSWAP_D 0xf800707f +#define MATCH_LR_D 0x1000302f +#define MASK_LR_D 0xf9f0707f +#define MATCH_SC_D 0x1800302f +#define MASK_SC_D 0xf800707f +#define MATCH_ECALL 0x73 +#define MASK_ECALL 0xffffffff +#define MATCH_EBREAK 0x100073 +#define MASK_EBREAK 0xffffffff +#define MATCH_URET 0x200073 +#define MASK_URET 0xffffffff +#define MATCH_SRET 0x10200073 +#define MASK_SRET 0xffffffff +#define MATCH_HRET 0x20200073 +#define MASK_HRET 0xffffffff +#define MATCH_MRET 0x30200073 +#define MASK_MRET 0xffffffff +#define MATCH_DRET 0x7b200073 +#define MASK_DRET 0xffffffff +#define MATCH_SFENCE_VM 0x10400073 +#define MASK_SFENCE_VM 0xfff07fff +#define MATCH_WFI 0x10500073 +#define MASK_WFI 0xffffffff +#define MATCH_CSRRW 0x1073 +#define MASK_CSRRW 0x707f +#define MATCH_CSRRS 0x2073 +#define MASK_CSRRS 0x707f +#define MATCH_CSRRC 0x3073 +#define MASK_CSRRC 0x707f +#define MATCH_CSRRWI 0x5073 +#define MASK_CSRRWI 0x707f +#define MATCH_CSRRSI 0x6073 +#define MASK_CSRRSI 0x707f +#define MATCH_CSRRCI 0x7073 +#define MASK_CSRRCI 0x707f +#define MATCH_FADD_S 0x53 +#define MASK_FADD_S 0xfe00007f +#define MATCH_FSUB_S 0x8000053 +#define MASK_FSUB_S 0xfe00007f +#define MATCH_FMUL_S 0x10000053 +#define MASK_FMUL_S 0xfe00007f +#define MATCH_FDIV_S 0x18000053 +#define MASK_FDIV_S 0xfe00007f +#define MATCH_FSGNJ_S 0x20000053 +#define MASK_FSGNJ_S 0xfe00707f +#define MATCH_FSGNJN_S 0x20001053 +#define MASK_FSGNJN_S 0xfe00707f +#define MATCH_FSGNJX_S 0x20002053 +#define MASK_FSGNJX_S 0xfe00707f +#define MATCH_FMIN_S 0x28000053 +#define MASK_FMIN_S 0xfe00707f +#define MATCH_FMAX_S 0x28001053 +#define MASK_FMAX_S 0xfe00707f +#define MATCH_FSQRT_S 0x58000053 +#define MASK_FSQRT_S 0xfff0007f +#define MATCH_FADD_D 0x2000053 +#define MASK_FADD_D 0xfe00007f +#define MATCH_FSUB_D 0xa000053 +#define MASK_FSUB_D 0xfe00007f +#define MATCH_FMUL_D 0x12000053 +#define MASK_FMUL_D 0xfe00007f +#define MATCH_FDIV_D 0x1a000053 +#define MASK_FDIV_D 0xfe00007f +#define MATCH_FSGNJ_D 0x22000053 +#define MASK_FSGNJ_D 0xfe00707f +#define MATCH_FSGNJN_D 0x22001053 +#define MASK_FSGNJN_D 0xfe00707f +#define MATCH_FSGNJX_D 0x22002053 +#define MASK_FSGNJX_D 0xfe00707f +#define MATCH_FMIN_D 0x2a000053 +#define MASK_FMIN_D 0xfe00707f +#define MATCH_FMAX_D 0x2a001053 +#define MASK_FMAX_D 0xfe00707f +#define MATCH_FCVT_S_D 0x40100053 +#define MASK_FCVT_S_D 0xfff0007f +#define MATCH_FCVT_D_S 0x42000053 +#define MASK_FCVT_D_S 0xfff0007f +#define MATCH_FSQRT_D 0x5a000053 +#define MASK_FSQRT_D 0xfff0007f +#define MATCH_FLE_S 0xa0000053 +#define MASK_FLE_S 0xfe00707f +#define MATCH_FLT_S 0xa0001053 +#define MASK_FLT_S 0xfe00707f +#define MATCH_FEQ_S 0xa0002053 +#define MASK_FEQ_S 0xfe00707f +#define MATCH_FLE_D 0xa2000053 +#define MASK_FLE_D 0xfe00707f +#define MATCH_FLT_D 0xa2001053 +#define MASK_FLT_D 0xfe00707f +#define MATCH_FEQ_D 0xa2002053 +#define MASK_FEQ_D 0xfe00707f +#define MATCH_FCVT_W_S 0xc0000053 +#define MASK_FCVT_W_S 0xfff0007f +#define MATCH_FCVT_WU_S 0xc0100053 +#define MASK_FCVT_WU_S 0xfff0007f +#define MATCH_FCVT_L_S 0xc0200053 +#define MASK_FCVT_L_S 0xfff0007f +#define MATCH_FCVT_LU_S 0xc0300053 +#define MASK_FCVT_LU_S 0xfff0007f +#define MATCH_FMV_X_S 0xe0000053 +#define MASK_FMV_X_S 0xfff0707f +#define MATCH_FCLASS_S 0xe0001053 +#define MASK_FCLASS_S 0xfff0707f +#define MATCH_FCVT_W_D 0xc2000053 +#define MASK_FCVT_W_D 0xfff0007f +#define MATCH_FCVT_WU_D 0xc2100053 +#define MASK_FCVT_WU_D 0xfff0007f +#define MATCH_FCVT_L_D 0xc2200053 +#define MASK_FCVT_L_D 0xfff0007f +#define MATCH_FCVT_LU_D 0xc2300053 +#define MASK_FCVT_LU_D 0xfff0007f +#define MATCH_FMV_X_D 0xe2000053 +#define MASK_FMV_X_D 0xfff0707f +#define MATCH_FCLASS_D 0xe2001053 +#define MASK_FCLASS_D 0xfff0707f +#define MATCH_FCVT_S_W 0xd0000053 +#define MASK_FCVT_S_W 0xfff0007f +#define MATCH_FCVT_S_WU 0xd0100053 +#define MASK_FCVT_S_WU 0xfff0007f +#define MATCH_FCVT_S_L 0xd0200053 +#define MASK_FCVT_S_L 0xfff0007f +#define MATCH_FCVT_S_LU 0xd0300053 +#define MASK_FCVT_S_LU 0xfff0007f +#define MATCH_FMV_S_X 0xf0000053 +#define MASK_FMV_S_X 0xfff0707f +#define MATCH_FCVT_D_W 0xd2000053 +#define MASK_FCVT_D_W 0xfff0007f +#define MATCH_FCVT_D_WU 0xd2100053 +#define MASK_FCVT_D_WU 0xfff0007f +#define MATCH_FCVT_D_L 0xd2200053 +#define MASK_FCVT_D_L 0xfff0007f +#define MATCH_FCVT_D_LU 0xd2300053 +#define MASK_FCVT_D_LU 0xfff0007f +#define MATCH_FMV_D_X 0xf2000053 +#define MASK_FMV_D_X 0xfff0707f +#define MATCH_FLW 0x2007 +#define MASK_FLW 0x707f +#define MATCH_FLD 0x3007 +#define MASK_FLD 0x707f +#define MATCH_FSW 0x2027 +#define MASK_FSW 0x707f +#define MATCH_FSD 0x3027 +#define MASK_FSD 0x707f +#define MATCH_FMADD_S 0x43 +#define MASK_FMADD_S 0x600007f +#define MATCH_FMSUB_S 0x47 +#define MASK_FMSUB_S 0x600007f +#define MATCH_FNMSUB_S 0x4b +#define MASK_FNMSUB_S 0x600007f +#define MATCH_FNMADD_S 0x4f +#define MASK_FNMADD_S 0x600007f +#define MATCH_FMADD_D 0x2000043 +#define MASK_FMADD_D 0x600007f +#define MATCH_FMSUB_D 0x2000047 +#define MASK_FMSUB_D 0x600007f +#define MATCH_FNMSUB_D 0x200004b +#define MASK_FNMSUB_D 0x600007f +#define MATCH_FNMADD_D 0x200004f +#define MASK_FNMADD_D 0x600007f +#define MATCH_C_ADDI4SPN 0x0 +#define MASK_C_ADDI4SPN 0xe003 +#define MATCH_C_FLD 0x2000 +#define MASK_C_FLD 0xe003 +#define MATCH_C_LW 0x4000 +#define MASK_C_LW 0xe003 +#define MATCH_C_FLW 0x6000 +#define MASK_C_FLW 0xe003 +#define MATCH_C_FSD 0xa000 +#define MASK_C_FSD 0xe003 +#define MATCH_C_SW 0xc000 +#define MASK_C_SW 0xe003 +#define MATCH_C_FSW 0xe000 +#define MASK_C_FSW 0xe003 +#define MATCH_C_ADDI 0x1 +#define MASK_C_ADDI 0xe003 +#define MATCH_C_JAL 0x2001 +#define MASK_C_JAL 0xe003 +#define MATCH_C_LI 0x4001 +#define MASK_C_LI 0xe003 +#define MATCH_C_LUI 0x6001 +#define MASK_C_LUI 0xe003 +#define MATCH_C_SRLI 0x8001 +#define MASK_C_SRLI 0xec03 +#define MATCH_C_SRAI 0x8401 +#define MASK_C_SRAI 0xec03 +#define MATCH_C_ANDI 0x8801 +#define MASK_C_ANDI 0xec03 +#define MATCH_C_SUB 0x8c01 +#define MASK_C_SUB 0xfc63 +#define MATCH_C_XOR 0x8c21 +#define MASK_C_XOR 0xfc63 +#define MATCH_C_OR 0x8c41 +#define MASK_C_OR 0xfc63 +#define MATCH_C_AND 0x8c61 +#define MASK_C_AND 0xfc63 +#define MATCH_C_SUBW 0x9c01 +#define MASK_C_SUBW 0xfc63 +#define MATCH_C_ADDW 0x9c21 +#define MASK_C_ADDW 0xfc63 +#define MATCH_C_J 0xa001 +#define MASK_C_J 0xe003 +#define MATCH_C_BEQZ 0xc001 +#define MASK_C_BEQZ 0xe003 +#define MATCH_C_BNEZ 0xe001 +#define MASK_C_BNEZ 0xe003 +#define MATCH_C_SLLI 0x2 +#define MASK_C_SLLI 0xe003 +#define MATCH_C_FLDSP 0x2002 +#define MASK_C_FLDSP 0xe003 +#define MATCH_C_LWSP 0x4002 +#define MASK_C_LWSP 0xe003 +#define MATCH_C_FLWSP 0x6002 +#define MASK_C_FLWSP 0xe003 +#define MATCH_C_MV 0x8002 +#define MASK_C_MV 0xf003 +#define MATCH_C_ADD 0x9002 +#define MASK_C_ADD 0xf003 +#define MATCH_C_FSDSP 0xa002 +#define MASK_C_FSDSP 0xe003 +#define MATCH_C_SWSP 0xc002 +#define MASK_C_SWSP 0xe003 +#define MATCH_C_FSWSP 0xe002 +#define MASK_C_FSWSP 0xe003 +#define MATCH_C_NOP 0x1 +#define MASK_C_NOP 0xffff +#define MATCH_C_ADDI16SP 0x6101 +#define MASK_C_ADDI16SP 0xef83 +#define MATCH_C_JR 0x8002 +#define MASK_C_JR 0xf07f +#define MATCH_C_JALR 0x9002 +#define MASK_C_JALR 0xf07f +#define MATCH_C_EBREAK 0x9002 +#define MASK_C_EBREAK 0xffff +#define MATCH_C_LD 0x6000 +#define MASK_C_LD 0xe003 +#define MATCH_C_SD 0xe000 +#define MASK_C_SD 0xe003 +#define MATCH_C_ADDIW 0x2001 +#define MASK_C_ADDIW 0xe003 +#define MATCH_C_LDSP 0x6002 +#define MASK_C_LDSP 0xe003 +#define MATCH_C_SDSP 0xe002 +#define MASK_C_SDSP 0xe003 +#define MATCH_CUSTOM0 0xb +#define MASK_CUSTOM0 0x707f +#define MATCH_CUSTOM0_RS1 0x200b +#define MASK_CUSTOM0_RS1 0x707f +#define MATCH_CUSTOM0_RS1_RS2 0x300b +#define MASK_CUSTOM0_RS1_RS2 0x707f +#define MATCH_CUSTOM0_RD 0x400b +#define MASK_CUSTOM0_RD 0x707f +#define MATCH_CUSTOM0_RD_RS1 0x600b +#define MASK_CUSTOM0_RD_RS1 0x707f +#define MATCH_CUSTOM0_RD_RS1_RS2 0x700b +#define MASK_CUSTOM0_RD_RS1_RS2 0x707f +#define MATCH_CUSTOM1 0x2b +#define MASK_CUSTOM1 0x707f +#define MATCH_CUSTOM1_RS1 0x202b +#define MASK_CUSTOM1_RS1 0x707f +#define MATCH_CUSTOM1_RS1_RS2 0x302b +#define MASK_CUSTOM1_RS1_RS2 0x707f +#define MATCH_CUSTOM1_RD 0x402b +#define MASK_CUSTOM1_RD 0x707f +#define MATCH_CUSTOM1_RD_RS1 0x602b +#define MASK_CUSTOM1_RD_RS1 0x707f +#define MATCH_CUSTOM1_RD_RS1_RS2 0x702b +#define MASK_CUSTOM1_RD_RS1_RS2 0x707f +#define MATCH_CUSTOM2 0x5b +#define MASK_CUSTOM2 0x707f +#define MATCH_CUSTOM2_RS1 0x205b +#define MASK_CUSTOM2_RS1 0x707f +#define MATCH_CUSTOM2_RS1_RS2 0x305b +#define MASK_CUSTOM2_RS1_RS2 0x707f +#define MATCH_CUSTOM2_RD 0x405b +#define MASK_CUSTOM2_RD 0x707f +#define MATCH_CUSTOM2_RD_RS1 0x605b +#define MASK_CUSTOM2_RD_RS1 0x707f +#define MATCH_CUSTOM2_RD_RS1_RS2 0x705b +#define MASK_CUSTOM2_RD_RS1_RS2 0x707f +#define MATCH_CUSTOM3 0x7b +#define MASK_CUSTOM3 0x707f +#define MATCH_CUSTOM3_RS1 0x207b +#define MASK_CUSTOM3_RS1 0x707f +#define MATCH_CUSTOM3_RS1_RS2 0x307b +#define MASK_CUSTOM3_RS1_RS2 0x707f +#define MATCH_CUSTOM3_RD 0x407b +#define MASK_CUSTOM3_RD 0x707f +#define MATCH_CUSTOM3_RD_RS1 0x607b +#define MASK_CUSTOM3_RD_RS1 0x707f +#define MATCH_CUSTOM3_RD_RS1_RS2 0x707b +#define MASK_CUSTOM3_RD_RS1_RS2 0x707f +#define CSR_FFLAGS 0x1 +#define CSR_FRM 0x2 +#define CSR_FCSR 0x3 +#define CSR_CYCLE 0xc00 +#define CSR_TIME 0xc01 +#define CSR_INSTRET 0xc02 +#define CSR_HPMCOUNTER3 0xc03 +#define CSR_HPMCOUNTER4 0xc04 +#define CSR_HPMCOUNTER5 0xc05 +#define CSR_HPMCOUNTER6 0xc06 +#define CSR_HPMCOUNTER7 0xc07 +#define CSR_HPMCOUNTER8 0xc08 +#define CSR_HPMCOUNTER9 0xc09 +#define CSR_HPMCOUNTER10 0xc0a +#define CSR_HPMCOUNTER11 0xc0b +#define CSR_HPMCOUNTER12 0xc0c +#define CSR_HPMCOUNTER13 0xc0d +#define CSR_HPMCOUNTER14 0xc0e +#define CSR_HPMCOUNTER15 0xc0f +#define CSR_HPMCOUNTER16 0xc10 +#define CSR_HPMCOUNTER17 0xc11 +#define CSR_HPMCOUNTER18 0xc12 +#define CSR_HPMCOUNTER19 0xc13 +#define CSR_HPMCOUNTER20 0xc14 +#define CSR_HPMCOUNTER21 0xc15 +#define CSR_HPMCOUNTER22 0xc16 +#define CSR_HPMCOUNTER23 0xc17 +#define CSR_HPMCOUNTER24 0xc18 +#define CSR_HPMCOUNTER25 0xc19 +#define CSR_HPMCOUNTER26 0xc1a +#define CSR_HPMCOUNTER27 0xc1b +#define CSR_HPMCOUNTER28 0xc1c +#define CSR_HPMCOUNTER29 0xc1d +#define CSR_HPMCOUNTER30 0xc1e +#define CSR_HPMCOUNTER31 0xc1f +#define CSR_SSTATUS 0x100 +#define CSR_SIE 0x104 +#define CSR_STVEC 0x105 +#define CSR_SSCRATCH 0x140 +#define CSR_SEPC 0x141 +#define CSR_SCAUSE 0x142 +#define CSR_SBADADDR 0x143 +#define CSR_SIP 0x144 +#define CSR_SPTBR 0x180 +#define CSR_MSTATUS 0x300 +#define CSR_MISA 0x301 +#define CSR_MEDELEG 0x302 +#define CSR_MIDELEG 0x303 +#define CSR_MIE 0x304 +#define CSR_MTVEC 0x305 +#define CSR_MSCRATCH 0x340 +#define CSR_MEPC 0x341 +#define CSR_MCAUSE 0x342 +#define CSR_MBADADDR 0x343 +#define CSR_MIP 0x344 +#define CSR_TSELECT 0x7a0 +#define CSR_TDATA1 0x7a1 +#define CSR_TDATA2 0x7a2 +#define CSR_TDATA3 0x7a3 +#define CSR_DCSR 0x7b0 +#define CSR_DPC 0x7b1 +#define CSR_DSCRATCH 0x7b2 +#define CSR_MCYCLE 0xb00 +#define CSR_MINSTRET 0xb02 +#define CSR_MHPMCOUNTER3 0xb03 +#define CSR_MHPMCOUNTER4 0xb04 +#define CSR_MHPMCOUNTER5 0xb05 +#define CSR_MHPMCOUNTER6 0xb06 +#define CSR_MHPMCOUNTER7 0xb07 +#define CSR_MHPMCOUNTER8 0xb08 +#define CSR_MHPMCOUNTER9 0xb09 +#define CSR_MHPMCOUNTER10 0xb0a +#define CSR_MHPMCOUNTER11 0xb0b +#define CSR_MHPMCOUNTER12 0xb0c +#define CSR_MHPMCOUNTER13 0xb0d +#define CSR_MHPMCOUNTER14 0xb0e +#define CSR_MHPMCOUNTER15 0xb0f +#define CSR_MHPMCOUNTER16 0xb10 +#define CSR_MHPMCOUNTER17 0xb11 +#define CSR_MHPMCOUNTER18 0xb12 +#define CSR_MHPMCOUNTER19 0xb13 +#define CSR_MHPMCOUNTER20 0xb14 +#define CSR_MHPMCOUNTER21 0xb15 +#define CSR_MHPMCOUNTER22 0xb16 +#define CSR_MHPMCOUNTER23 0xb17 +#define CSR_MHPMCOUNTER24 0xb18 +#define CSR_MHPMCOUNTER25 0xb19 +#define CSR_MHPMCOUNTER26 0xb1a +#define CSR_MHPMCOUNTER27 0xb1b +#define CSR_MHPMCOUNTER28 0xb1c +#define CSR_MHPMCOUNTER29 0xb1d +#define CSR_MHPMCOUNTER30 0xb1e +#define CSR_MHPMCOUNTER31 0xb1f +#define CSR_MUCOUNTEREN 0x320 +#define CSR_MSCOUNTEREN 0x321 +#define CSR_MHPMEVENT3 0x323 +#define CSR_MHPMEVENT4 0x324 +#define CSR_MHPMEVENT5 0x325 +#define CSR_MHPMEVENT6 0x326 +#define CSR_MHPMEVENT7 0x327 +#define CSR_MHPMEVENT8 0x328 +#define CSR_MHPMEVENT9 0x329 +#define CSR_MHPMEVENT10 0x32a +#define CSR_MHPMEVENT11 0x32b +#define CSR_MHPMEVENT12 0x32c +#define CSR_MHPMEVENT13 0x32d +#define CSR_MHPMEVENT14 0x32e +#define CSR_MHPMEVENT15 0x32f +#define CSR_MHPMEVENT16 0x330 +#define CSR_MHPMEVENT17 0x331 +#define CSR_MHPMEVENT18 0x332 +#define CSR_MHPMEVENT19 0x333 +#define CSR_MHPMEVENT20 0x334 +#define CSR_MHPMEVENT21 0x335 +#define CSR_MHPMEVENT22 0x336 +#define CSR_MHPMEVENT23 0x337 +#define CSR_MHPMEVENT24 0x338 +#define CSR_MHPMEVENT25 0x339 +#define CSR_MHPMEVENT26 0x33a +#define CSR_MHPMEVENT27 0x33b +#define CSR_MHPMEVENT28 0x33c +#define CSR_MHPMEVENT29 0x33d +#define CSR_MHPMEVENT30 0x33e +#define CSR_MHPMEVENT31 0x33f +#define CSR_MVENDORID 0xf11 +#define CSR_MARCHID 0xf12 +#define CSR_MIMPID 0xf13 +#define CSR_MHARTID 0xf14 +#define CSR_CYCLEH 0xc80 +#define CSR_TIMEH 0xc81 +#define CSR_INSTRETH 0xc82 +#define CSR_HPMCOUNTER3H 0xc83 +#define CSR_HPMCOUNTER4H 0xc84 +#define CSR_HPMCOUNTER5H 0xc85 +#define CSR_HPMCOUNTER6H 0xc86 +#define CSR_HPMCOUNTER7H 0xc87 +#define CSR_HPMCOUNTER8H 0xc88 +#define CSR_HPMCOUNTER9H 0xc89 +#define CSR_HPMCOUNTER10H 0xc8a +#define CSR_HPMCOUNTER11H 0xc8b +#define CSR_HPMCOUNTER12H 0xc8c +#define CSR_HPMCOUNTER13H 0xc8d +#define CSR_HPMCOUNTER14H 0xc8e +#define CSR_HPMCOUNTER15H 0xc8f +#define CSR_HPMCOUNTER16H 0xc90 +#define CSR_HPMCOUNTER17H 0xc91 +#define CSR_HPMCOUNTER18H 0xc92 +#define CSR_HPMCOUNTER19H 0xc93 +#define CSR_HPMCOUNTER20H 0xc94 +#define CSR_HPMCOUNTER21H 0xc95 +#define CSR_HPMCOUNTER22H 0xc96 +#define CSR_HPMCOUNTER23H 0xc97 +#define CSR_HPMCOUNTER24H 0xc98 +#define CSR_HPMCOUNTER25H 0xc99 +#define CSR_HPMCOUNTER26H 0xc9a +#define CSR_HPMCOUNTER27H 0xc9b +#define CSR_HPMCOUNTER28H 0xc9c +#define CSR_HPMCOUNTER29H 0xc9d +#define CSR_HPMCOUNTER30H 0xc9e +#define CSR_HPMCOUNTER31H 0xc9f +#define CSR_MCYCLEH 0xb80 +#define CSR_MINSTRETH 0xb82 +#define CSR_MHPMCOUNTER3H 0xb83 +#define CSR_MHPMCOUNTER4H 0xb84 +#define CSR_MHPMCOUNTER5H 0xb85 +#define CSR_MHPMCOUNTER6H 0xb86 +#define CSR_MHPMCOUNTER7H 0xb87 +#define CSR_MHPMCOUNTER8H 0xb88 +#define CSR_MHPMCOUNTER9H 0xb89 +#define CSR_MHPMCOUNTER10H 0xb8a +#define CSR_MHPMCOUNTER11H 0xb8b +#define CSR_MHPMCOUNTER12H 0xb8c +#define CSR_MHPMCOUNTER13H 0xb8d +#define CSR_MHPMCOUNTER14H 0xb8e +#define CSR_MHPMCOUNTER15H 0xb8f +#define CSR_MHPMCOUNTER16H 0xb90 +#define CSR_MHPMCOUNTER17H 0xb91 +#define CSR_MHPMCOUNTER18H 0xb92 +#define CSR_MHPMCOUNTER19H 0xb93 +#define CSR_MHPMCOUNTER20H 0xb94 +#define CSR_MHPMCOUNTER21H 0xb95 +#define CSR_MHPMCOUNTER22H 0xb96 +#define CSR_MHPMCOUNTER23H 0xb97 +#define CSR_MHPMCOUNTER24H 0xb98 +#define CSR_MHPMCOUNTER25H 0xb99 +#define CSR_MHPMCOUNTER26H 0xb9a +#define CSR_MHPMCOUNTER27H 0xb9b +#define CSR_MHPMCOUNTER28H 0xb9c +#define CSR_MHPMCOUNTER29H 0xb9d +#define CSR_MHPMCOUNTER30H 0xb9e +#define CSR_MHPMCOUNTER31H 0xb9f +#define CAUSE_MISALIGNED_FETCH 0x0 +#define CAUSE_FAULT_FETCH 0x1 +#define CAUSE_ILLEGAL_INSTRUCTION 0x2 +#define CAUSE_BREAKPOINT 0x3 +#define CAUSE_MISALIGNED_LOAD 0x4 +#define CAUSE_FAULT_LOAD 0x5 +#define CAUSE_MISALIGNED_STORE 0x6 +#define CAUSE_FAULT_STORE 0x7 +#define CAUSE_USER_ECALL 0x8 +#define CAUSE_SUPERVISOR_ECALL 0x9 +#define CAUSE_HYPERVISOR_ECALL 0xa +#define CAUSE_MACHINE_ECALL 0xb +#endif +#ifdef DECLARE_INSN +DECLARE_INSN(slli_rv32, MATCH_SLLI_RV32, MASK_SLLI_RV32) +DECLARE_INSN(srli_rv32, MATCH_SRLI_RV32, MASK_SRLI_RV32) +DECLARE_INSN(srai_rv32, MATCH_SRAI_RV32, MASK_SRAI_RV32) +DECLARE_INSN(frflags, MATCH_FRFLAGS, MASK_FRFLAGS) +DECLARE_INSN(fsflags, MATCH_FSFLAGS, MASK_FSFLAGS) +DECLARE_INSN(fsflagsi, MATCH_FSFLAGSI, MASK_FSFLAGSI) +DECLARE_INSN(frrm, MATCH_FRRM, MASK_FRRM) +DECLARE_INSN(fsrm, MATCH_FSRM, MASK_FSRM) +DECLARE_INSN(fsrmi, MATCH_FSRMI, MASK_FSRMI) +DECLARE_INSN(fscsr, MATCH_FSCSR, MASK_FSCSR) +DECLARE_INSN(frcsr, MATCH_FRCSR, MASK_FRCSR) +DECLARE_INSN(rdcycle, MATCH_RDCYCLE, MASK_RDCYCLE) +DECLARE_INSN(rdtime, MATCH_RDTIME, MASK_RDTIME) +DECLARE_INSN(rdinstret, MATCH_RDINSTRET, MASK_RDINSTRET) +DECLARE_INSN(rdcycleh, MATCH_RDCYCLEH, MASK_RDCYCLEH) +DECLARE_INSN(rdtimeh, MATCH_RDTIMEH, MASK_RDTIMEH) +DECLARE_INSN(rdinstreth, MATCH_RDINSTRETH, MASK_RDINSTRETH) +DECLARE_INSN(scall, MATCH_SCALL, MASK_SCALL) +DECLARE_INSN(sbreak, MATCH_SBREAK, MASK_SBREAK) +DECLARE_INSN(beq, MATCH_BEQ, MASK_BEQ) +DECLARE_INSN(bne, MATCH_BNE, MASK_BNE) +DECLARE_INSN(blt, MATCH_BLT, MASK_BLT) +DECLARE_INSN(bge, MATCH_BGE, MASK_BGE) +DECLARE_INSN(bltu, MATCH_BLTU, MASK_BLTU) +DECLARE_INSN(bgeu, MATCH_BGEU, MASK_BGEU) +DECLARE_INSN(jalr, MATCH_JALR, MASK_JALR) +DECLARE_INSN(jal, MATCH_JAL, MASK_JAL) +DECLARE_INSN(lui, MATCH_LUI, MASK_LUI) +DECLARE_INSN(auipc, MATCH_AUIPC, MASK_AUIPC) +DECLARE_INSN(addi, MATCH_ADDI, MASK_ADDI) +DECLARE_INSN(slli, MATCH_SLLI, MASK_SLLI) +DECLARE_INSN(slti, MATCH_SLTI, MASK_SLTI) +DECLARE_INSN(sltiu, MATCH_SLTIU, MASK_SLTIU) +DECLARE_INSN(xori, MATCH_XORI, MASK_XORI) +DECLARE_INSN(srli, MATCH_SRLI, MASK_SRLI) +DECLARE_INSN(srai, MATCH_SRAI, MASK_SRAI) +DECLARE_INSN(ori, MATCH_ORI, MASK_ORI) +DECLARE_INSN(andi, MATCH_ANDI, MASK_ANDI) +DECLARE_INSN(add, MATCH_ADD, MASK_ADD) +DECLARE_INSN(sub, MATCH_SUB, MASK_SUB) +DECLARE_INSN(sll, MATCH_SLL, MASK_SLL) +DECLARE_INSN(slt, MATCH_SLT, MASK_SLT) +DECLARE_INSN(sltu, MATCH_SLTU, MASK_SLTU) +DECLARE_INSN(xor, MATCH_XOR, MASK_XOR) +DECLARE_INSN(srl, MATCH_SRL, MASK_SRL) +DECLARE_INSN(sra, MATCH_SRA, MASK_SRA) +DECLARE_INSN(or, MATCH_OR, MASK_OR) +DECLARE_INSN(and, MATCH_AND, MASK_AND) +DECLARE_INSN(addiw, MATCH_ADDIW, MASK_ADDIW) +DECLARE_INSN(slliw, MATCH_SLLIW, MASK_SLLIW) +DECLARE_INSN(srliw, MATCH_SRLIW, MASK_SRLIW) +DECLARE_INSN(sraiw, MATCH_SRAIW, MASK_SRAIW) +DECLARE_INSN(addw, MATCH_ADDW, MASK_ADDW) +DECLARE_INSN(subw, MATCH_SUBW, MASK_SUBW) +DECLARE_INSN(sllw, MATCH_SLLW, MASK_SLLW) +DECLARE_INSN(srlw, MATCH_SRLW, MASK_SRLW) +DECLARE_INSN(sraw, MATCH_SRAW, MASK_SRAW) +DECLARE_INSN(lb, MATCH_LB, MASK_LB) +DECLARE_INSN(lh, MATCH_LH, MASK_LH) +DECLARE_INSN(lw, MATCH_LW, MASK_LW) +DECLARE_INSN(ld, MATCH_LD, MASK_LD) +DECLARE_INSN(lbu, MATCH_LBU, MASK_LBU) +DECLARE_INSN(lhu, MATCH_LHU, MASK_LHU) +DECLARE_INSN(lwu, MATCH_LWU, MASK_LWU) +DECLARE_INSN(sb, MATCH_SB, MASK_SB) +DECLARE_INSN(sh, MATCH_SH, MASK_SH) +DECLARE_INSN(sw, MATCH_SW, MASK_SW) +DECLARE_INSN(sd, MATCH_SD, MASK_SD) +DECLARE_INSN(fence, MATCH_FENCE, MASK_FENCE) +DECLARE_INSN(fence_i, MATCH_FENCE_I, MASK_FENCE_I) +DECLARE_INSN(mul, MATCH_MUL, MASK_MUL) +DECLARE_INSN(mulh, MATCH_MULH, MASK_MULH) +DECLARE_INSN(mulhsu, MATCH_MULHSU, MASK_MULHSU) +DECLARE_INSN(mulhu, MATCH_MULHU, MASK_MULHU) +DECLARE_INSN(div, MATCH_DIV, MASK_DIV) +DECLARE_INSN(divu, MATCH_DIVU, MASK_DIVU) +DECLARE_INSN(rem, MATCH_REM, MASK_REM) +DECLARE_INSN(remu, MATCH_REMU, MASK_REMU) +DECLARE_INSN(mulw, MATCH_MULW, MASK_MULW) +DECLARE_INSN(divw, MATCH_DIVW, MASK_DIVW) +DECLARE_INSN(divuw, MATCH_DIVUW, MASK_DIVUW) +DECLARE_INSN(remw, MATCH_REMW, MASK_REMW) +DECLARE_INSN(remuw, MATCH_REMUW, MASK_REMUW) +DECLARE_INSN(amoadd_w, MATCH_AMOADD_W, MASK_AMOADD_W) +DECLARE_INSN(amoxor_w, MATCH_AMOXOR_W, MASK_AMOXOR_W) +DECLARE_INSN(amoor_w, MATCH_AMOOR_W, MASK_AMOOR_W) +DECLARE_INSN(amoand_w, MATCH_AMOAND_W, MASK_AMOAND_W) +DECLARE_INSN(amomin_w, MATCH_AMOMIN_W, MASK_AMOMIN_W) +DECLARE_INSN(amomax_w, MATCH_AMOMAX_W, MASK_AMOMAX_W) +DECLARE_INSN(amominu_w, MATCH_AMOMINU_W, MASK_AMOMINU_W) +DECLARE_INSN(amomaxu_w, MATCH_AMOMAXU_W, MASK_AMOMAXU_W) +DECLARE_INSN(amoswap_w, MATCH_AMOSWAP_W, MASK_AMOSWAP_W) +DECLARE_INSN(lr_w, MATCH_LR_W, MASK_LR_W) +DECLARE_INSN(sc_w, MATCH_SC_W, MASK_SC_W) +DECLARE_INSN(amoadd_d, MATCH_AMOADD_D, MASK_AMOADD_D) +DECLARE_INSN(amoxor_d, MATCH_AMOXOR_D, MASK_AMOXOR_D) +DECLARE_INSN(amoor_d, MATCH_AMOOR_D, MASK_AMOOR_D) +DECLARE_INSN(amoand_d, MATCH_AMOAND_D, MASK_AMOAND_D) +DECLARE_INSN(amomin_d, MATCH_AMOMIN_D, MASK_AMOMIN_D) +DECLARE_INSN(amomax_d, MATCH_AMOMAX_D, MASK_AMOMAX_D) +DECLARE_INSN(amominu_d, MATCH_AMOMINU_D, MASK_AMOMINU_D) +DECLARE_INSN(amomaxu_d, MATCH_AMOMAXU_D, MASK_AMOMAXU_D) +DECLARE_INSN(amoswap_d, MATCH_AMOSWAP_D, MASK_AMOSWAP_D) +DECLARE_INSN(lr_d, MATCH_LR_D, MASK_LR_D) +DECLARE_INSN(sc_d, MATCH_SC_D, MASK_SC_D) +DECLARE_INSN(ecall, MATCH_ECALL, MASK_ECALL) +DECLARE_INSN(ebreak, MATCH_EBREAK, MASK_EBREAK) +DECLARE_INSN(uret, MATCH_URET, MASK_URET) +DECLARE_INSN(sret, MATCH_SRET, MASK_SRET) +DECLARE_INSN(hret, MATCH_HRET, MASK_HRET) +DECLARE_INSN(mret, MATCH_MRET, MASK_MRET) +DECLARE_INSN(dret, MATCH_DRET, MASK_DRET) +DECLARE_INSN(sfence_vm, MATCH_SFENCE_VM, MASK_SFENCE_VM) +DECLARE_INSN(wfi, MATCH_WFI, MASK_WFI) +DECLARE_INSN(csrrw, MATCH_CSRRW, MASK_CSRRW) +DECLARE_INSN(csrrs, MATCH_CSRRS, MASK_CSRRS) +DECLARE_INSN(csrrc, MATCH_CSRRC, MASK_CSRRC) +DECLARE_INSN(csrrwi, MATCH_CSRRWI, MASK_CSRRWI) +DECLARE_INSN(csrrsi, MATCH_CSRRSI, MASK_CSRRSI) +DECLARE_INSN(csrrci, MATCH_CSRRCI, MASK_CSRRCI) +DECLARE_INSN(fadd_s, MATCH_FADD_S, MASK_FADD_S) +DECLARE_INSN(fsub_s, MATCH_FSUB_S, MASK_FSUB_S) +DECLARE_INSN(fmul_s, MATCH_FMUL_S, MASK_FMUL_S) +DECLARE_INSN(fdiv_s, MATCH_FDIV_S, MASK_FDIV_S) +DECLARE_INSN(fsgnj_s, MATCH_FSGNJ_S, MASK_FSGNJ_S) +DECLARE_INSN(fsgnjn_s, MATCH_FSGNJN_S, MASK_FSGNJN_S) +DECLARE_INSN(fsgnjx_s, MATCH_FSGNJX_S, MASK_FSGNJX_S) +DECLARE_INSN(fmin_s, MATCH_FMIN_S, MASK_FMIN_S) +DECLARE_INSN(fmax_s, MATCH_FMAX_S, MASK_FMAX_S) +DECLARE_INSN(fsqrt_s, MATCH_FSQRT_S, MASK_FSQRT_S) +DECLARE_INSN(fadd_d, MATCH_FADD_D, MASK_FADD_D) +DECLARE_INSN(fsub_d, MATCH_FSUB_D, MASK_FSUB_D) +DECLARE_INSN(fmul_d, MATCH_FMUL_D, MASK_FMUL_D) +DECLARE_INSN(fdiv_d, MATCH_FDIV_D, MASK_FDIV_D) +DECLARE_INSN(fsgnj_d, MATCH_FSGNJ_D, MASK_FSGNJ_D) +DECLARE_INSN(fsgnjn_d, MATCH_FSGNJN_D, MASK_FSGNJN_D) +DECLARE_INSN(fsgnjx_d, MATCH_FSGNJX_D, MASK_FSGNJX_D) +DECLARE_INSN(fmin_d, MATCH_FMIN_D, MASK_FMIN_D) +DECLARE_INSN(fmax_d, MATCH_FMAX_D, MASK_FMAX_D) +DECLARE_INSN(fcvt_s_d, MATCH_FCVT_S_D, MASK_FCVT_S_D) +DECLARE_INSN(fcvt_d_s, MATCH_FCVT_D_S, MASK_FCVT_D_S) +DECLARE_INSN(fsqrt_d, MATCH_FSQRT_D, MASK_FSQRT_D) +DECLARE_INSN(fle_s, MATCH_FLE_S, MASK_FLE_S) +DECLARE_INSN(flt_s, MATCH_FLT_S, MASK_FLT_S) +DECLARE_INSN(feq_s, MATCH_FEQ_S, MASK_FEQ_S) +DECLARE_INSN(fle_d, MATCH_FLE_D, MASK_FLE_D) +DECLARE_INSN(flt_d, MATCH_FLT_D, MASK_FLT_D) +DECLARE_INSN(feq_d, MATCH_FEQ_D, MASK_FEQ_D) +DECLARE_INSN(fcvt_w_s, MATCH_FCVT_W_S, MASK_FCVT_W_S) +DECLARE_INSN(fcvt_wu_s, MATCH_FCVT_WU_S, MASK_FCVT_WU_S) +DECLARE_INSN(fcvt_l_s, MATCH_FCVT_L_S, MASK_FCVT_L_S) +DECLARE_INSN(fcvt_lu_s, MATCH_FCVT_LU_S, MASK_FCVT_LU_S) +DECLARE_INSN(fmv_x_s, MATCH_FMV_X_S, MASK_FMV_X_S) +DECLARE_INSN(fclass_s, MATCH_FCLASS_S, MASK_FCLASS_S) +DECLARE_INSN(fcvt_w_d, MATCH_FCVT_W_D, MASK_FCVT_W_D) +DECLARE_INSN(fcvt_wu_d, MATCH_FCVT_WU_D, MASK_FCVT_WU_D) +DECLARE_INSN(fcvt_l_d, MATCH_FCVT_L_D, MASK_FCVT_L_D) +DECLARE_INSN(fcvt_lu_d, MATCH_FCVT_LU_D, MASK_FCVT_LU_D) +DECLARE_INSN(fmv_x_d, MATCH_FMV_X_D, MASK_FMV_X_D) +DECLARE_INSN(fclass_d, MATCH_FCLASS_D, MASK_FCLASS_D) +DECLARE_INSN(fcvt_s_w, MATCH_FCVT_S_W, MASK_FCVT_S_W) +DECLARE_INSN(fcvt_s_wu, MATCH_FCVT_S_WU, MASK_FCVT_S_WU) +DECLARE_INSN(fcvt_s_l, MATCH_FCVT_S_L, MASK_FCVT_S_L) +DECLARE_INSN(fcvt_s_lu, MATCH_FCVT_S_LU, MASK_FCVT_S_LU) +DECLARE_INSN(fmv_s_x, MATCH_FMV_S_X, MASK_FMV_S_X) +DECLARE_INSN(fcvt_d_w, MATCH_FCVT_D_W, MASK_FCVT_D_W) +DECLARE_INSN(fcvt_d_wu, MATCH_FCVT_D_WU, MASK_FCVT_D_WU) +DECLARE_INSN(fcvt_d_l, MATCH_FCVT_D_L, MASK_FCVT_D_L) +DECLARE_INSN(fcvt_d_lu, MATCH_FCVT_D_LU, MASK_FCVT_D_LU) +DECLARE_INSN(fmv_d_x, MATCH_FMV_D_X, MASK_FMV_D_X) +DECLARE_INSN(flw, MATCH_FLW, MASK_FLW) +DECLARE_INSN(fld, MATCH_FLD, MASK_FLD) +DECLARE_INSN(fsw, MATCH_FSW, MASK_FSW) +DECLARE_INSN(fsd, MATCH_FSD, MASK_FSD) +DECLARE_INSN(fmadd_s, MATCH_FMADD_S, MASK_FMADD_S) +DECLARE_INSN(fmsub_s, MATCH_FMSUB_S, MASK_FMSUB_S) +DECLARE_INSN(fnmsub_s, MATCH_FNMSUB_S, MASK_FNMSUB_S) +DECLARE_INSN(fnmadd_s, MATCH_FNMADD_S, MASK_FNMADD_S) +DECLARE_INSN(fmadd_d, MATCH_FMADD_D, MASK_FMADD_D) +DECLARE_INSN(fmsub_d, MATCH_FMSUB_D, MASK_FMSUB_D) +DECLARE_INSN(fnmsub_d, MATCH_FNMSUB_D, MASK_FNMSUB_D) +DECLARE_INSN(fnmadd_d, MATCH_FNMADD_D, MASK_FNMADD_D) +DECLARE_INSN(c_addi4spn, MATCH_C_ADDI4SPN, MASK_C_ADDI4SPN) +DECLARE_INSN(c_fld, MATCH_C_FLD, MASK_C_FLD) +DECLARE_INSN(c_lw, MATCH_C_LW, MASK_C_LW) +DECLARE_INSN(c_flw, MATCH_C_FLW, MASK_C_FLW) +DECLARE_INSN(c_fsd, MATCH_C_FSD, MASK_C_FSD) +DECLARE_INSN(c_sw, MATCH_C_SW, MASK_C_SW) +DECLARE_INSN(c_fsw, MATCH_C_FSW, MASK_C_FSW) +DECLARE_INSN(c_addi, MATCH_C_ADDI, MASK_C_ADDI) +DECLARE_INSN(c_jal, MATCH_C_JAL, MASK_C_JAL) +DECLARE_INSN(c_li, MATCH_C_LI, MASK_C_LI) +DECLARE_INSN(c_lui, MATCH_C_LUI, MASK_C_LUI) +DECLARE_INSN(c_srli, MATCH_C_SRLI, MASK_C_SRLI) +DECLARE_INSN(c_srai, MATCH_C_SRAI, MASK_C_SRAI) +DECLARE_INSN(c_andi, MATCH_C_ANDI, MASK_C_ANDI) +DECLARE_INSN(c_sub, MATCH_C_SUB, MASK_C_SUB) +DECLARE_INSN(c_xor, MATCH_C_XOR, MASK_C_XOR) +DECLARE_INSN(c_or, MATCH_C_OR, MASK_C_OR) +DECLARE_INSN(c_and, MATCH_C_AND, MASK_C_AND) +DECLARE_INSN(c_subw, MATCH_C_SUBW, MASK_C_SUBW) +DECLARE_INSN(c_addw, MATCH_C_ADDW, MASK_C_ADDW) +DECLARE_INSN(c_j, MATCH_C_J, MASK_C_J) +DECLARE_INSN(c_beqz, MATCH_C_BEQZ, MASK_C_BEQZ) +DECLARE_INSN(c_bnez, MATCH_C_BNEZ, MASK_C_BNEZ) +DECLARE_INSN(c_slli, MATCH_C_SLLI, MASK_C_SLLI) +DECLARE_INSN(c_fldsp, MATCH_C_FLDSP, MASK_C_FLDSP) +DECLARE_INSN(c_lwsp, MATCH_C_LWSP, MASK_C_LWSP) +DECLARE_INSN(c_flwsp, MATCH_C_FLWSP, MASK_C_FLWSP) +DECLARE_INSN(c_mv, MATCH_C_MV, MASK_C_MV) +DECLARE_INSN(c_add, MATCH_C_ADD, MASK_C_ADD) +DECLARE_INSN(c_fsdsp, MATCH_C_FSDSP, MASK_C_FSDSP) +DECLARE_INSN(c_swsp, MATCH_C_SWSP, MASK_C_SWSP) +DECLARE_INSN(c_fswsp, MATCH_C_FSWSP, MASK_C_FSWSP) +DECLARE_INSN(c_nop, MATCH_C_NOP, MASK_C_NOP) +DECLARE_INSN(c_addi16sp, MATCH_C_ADDI16SP, MASK_C_ADDI16SP) +DECLARE_INSN(c_jr, MATCH_C_JR, MASK_C_JR) +DECLARE_INSN(c_jalr, MATCH_C_JALR, MASK_C_JALR) +DECLARE_INSN(c_ebreak, MATCH_C_EBREAK, MASK_C_EBREAK) +DECLARE_INSN(c_ld, MATCH_C_LD, MASK_C_LD) +DECLARE_INSN(c_sd, MATCH_C_SD, MASK_C_SD) +DECLARE_INSN(c_addiw, MATCH_C_ADDIW, MASK_C_ADDIW) +DECLARE_INSN(c_ldsp, MATCH_C_LDSP, MASK_C_LDSP) +DECLARE_INSN(c_sdsp, MATCH_C_SDSP, MASK_C_SDSP) +DECLARE_INSN(custom0, MATCH_CUSTOM0, MASK_CUSTOM0) +DECLARE_INSN(custom0_rs1, MATCH_CUSTOM0_RS1, MASK_CUSTOM0_RS1) +DECLARE_INSN(custom0_rs1_rs2, MATCH_CUSTOM0_RS1_RS2, MASK_CUSTOM0_RS1_RS2) +DECLARE_INSN(custom0_rd, MATCH_CUSTOM0_RD, MASK_CUSTOM0_RD) +DECLARE_INSN(custom0_rd_rs1, MATCH_CUSTOM0_RD_RS1, MASK_CUSTOM0_RD_RS1) +DECLARE_INSN(custom0_rd_rs1_rs2, MATCH_CUSTOM0_RD_RS1_RS2, MASK_CUSTOM0_RD_RS1_RS2) +DECLARE_INSN(custom1, MATCH_CUSTOM1, MASK_CUSTOM1) +DECLARE_INSN(custom1_rs1, MATCH_CUSTOM1_RS1, MASK_CUSTOM1_RS1) +DECLARE_INSN(custom1_rs1_rs2, MATCH_CUSTOM1_RS1_RS2, MASK_CUSTOM1_RS1_RS2) +DECLARE_INSN(custom1_rd, MATCH_CUSTOM1_RD, MASK_CUSTOM1_RD) +DECLARE_INSN(custom1_rd_rs1, MATCH_CUSTOM1_RD_RS1, MASK_CUSTOM1_RD_RS1) +DECLARE_INSN(custom1_rd_rs1_rs2, MATCH_CUSTOM1_RD_RS1_RS2, MASK_CUSTOM1_RD_RS1_RS2) +DECLARE_INSN(custom2, MATCH_CUSTOM2, MASK_CUSTOM2) +DECLARE_INSN(custom2_rs1, MATCH_CUSTOM2_RS1, MASK_CUSTOM2_RS1) +DECLARE_INSN(custom2_rs1_rs2, MATCH_CUSTOM2_RS1_RS2, MASK_CUSTOM2_RS1_RS2) +DECLARE_INSN(custom2_rd, MATCH_CUSTOM2_RD, MASK_CUSTOM2_RD) +DECLARE_INSN(custom2_rd_rs1, MATCH_CUSTOM2_RD_RS1, MASK_CUSTOM2_RD_RS1) +DECLARE_INSN(custom2_rd_rs1_rs2, MATCH_CUSTOM2_RD_RS1_RS2, MASK_CUSTOM2_RD_RS1_RS2) +DECLARE_INSN(custom3, MATCH_CUSTOM3, MASK_CUSTOM3) +DECLARE_INSN(custom3_rs1, MATCH_CUSTOM3_RS1, MASK_CUSTOM3_RS1) +DECLARE_INSN(custom3_rs1_rs2, MATCH_CUSTOM3_RS1_RS2, MASK_CUSTOM3_RS1_RS2) +DECLARE_INSN(custom3_rd, MATCH_CUSTOM3_RD, MASK_CUSTOM3_RD) +DECLARE_INSN(custom3_rd_rs1, MATCH_CUSTOM3_RD_RS1, MASK_CUSTOM3_RD_RS1) +DECLARE_INSN(custom3_rd_rs1_rs2, MATCH_CUSTOM3_RD_RS1_RS2, MASK_CUSTOM3_RD_RS1_RS2) +#endif +#ifdef DECLARE_CSR +DECLARE_CSR(fflags, CSR_FFLAGS) +DECLARE_CSR(frm, CSR_FRM) +DECLARE_CSR(fcsr, CSR_FCSR) +DECLARE_CSR(cycle, CSR_CYCLE) +DECLARE_CSR(time, CSR_TIME) +DECLARE_CSR(instret, CSR_INSTRET) +DECLARE_CSR(hpmcounter3, CSR_HPMCOUNTER3) +DECLARE_CSR(hpmcounter4, CSR_HPMCOUNTER4) +DECLARE_CSR(hpmcounter5, CSR_HPMCOUNTER5) +DECLARE_CSR(hpmcounter6, CSR_HPMCOUNTER6) +DECLARE_CSR(hpmcounter7, CSR_HPMCOUNTER7) +DECLARE_CSR(hpmcounter8, CSR_HPMCOUNTER8) +DECLARE_CSR(hpmcounter9, CSR_HPMCOUNTER9) +DECLARE_CSR(hpmcounter10, CSR_HPMCOUNTER10) +DECLARE_CSR(hpmcounter11, CSR_HPMCOUNTER11) +DECLARE_CSR(hpmcounter12, CSR_HPMCOUNTER12) +DECLARE_CSR(hpmcounter13, CSR_HPMCOUNTER13) +DECLARE_CSR(hpmcounter14, CSR_HPMCOUNTER14) +DECLARE_CSR(hpmcounter15, CSR_HPMCOUNTER15) +DECLARE_CSR(hpmcounter16, CSR_HPMCOUNTER16) +DECLARE_CSR(hpmcounter17, CSR_HPMCOUNTER17) +DECLARE_CSR(hpmcounter18, CSR_HPMCOUNTER18) +DECLARE_CSR(hpmcounter19, CSR_HPMCOUNTER19) +DECLARE_CSR(hpmcounter20, CSR_HPMCOUNTER20) +DECLARE_CSR(hpmcounter21, CSR_HPMCOUNTER21) +DECLARE_CSR(hpmcounter22, CSR_HPMCOUNTER22) +DECLARE_CSR(hpmcounter23, CSR_HPMCOUNTER23) +DECLARE_CSR(hpmcounter24, CSR_HPMCOUNTER24) +DECLARE_CSR(hpmcounter25, CSR_HPMCOUNTER25) +DECLARE_CSR(hpmcounter26, CSR_HPMCOUNTER26) +DECLARE_CSR(hpmcounter27, CSR_HPMCOUNTER27) +DECLARE_CSR(hpmcounter28, CSR_HPMCOUNTER28) +DECLARE_CSR(hpmcounter29, CSR_HPMCOUNTER29) +DECLARE_CSR(hpmcounter30, CSR_HPMCOUNTER30) +DECLARE_CSR(hpmcounter31, CSR_HPMCOUNTER31) +DECLARE_CSR(sstatus, CSR_SSTATUS) +DECLARE_CSR(sie, CSR_SIE) +DECLARE_CSR(stvec, CSR_STVEC) +DECLARE_CSR(sscratch, CSR_SSCRATCH) +DECLARE_CSR(sepc, CSR_SEPC) +DECLARE_CSR(scause, CSR_SCAUSE) +DECLARE_CSR(sbadaddr, CSR_SBADADDR) +DECLARE_CSR(sip, CSR_SIP) +DECLARE_CSR(sptbr, CSR_SPTBR) +DECLARE_CSR(mstatus, CSR_MSTATUS) +DECLARE_CSR(misa, CSR_MISA) +DECLARE_CSR(medeleg, CSR_MEDELEG) +DECLARE_CSR(mideleg, CSR_MIDELEG) +DECLARE_CSR(mie, CSR_MIE) +DECLARE_CSR(mtvec, CSR_MTVEC) +DECLARE_CSR(mscratch, CSR_MSCRATCH) +DECLARE_CSR(mepc, CSR_MEPC) +DECLARE_CSR(mcause, CSR_MCAUSE) +DECLARE_CSR(mbadaddr, CSR_MBADADDR) +DECLARE_CSR(mip, CSR_MIP) +DECLARE_CSR(tselect, CSR_TSELECT) +DECLARE_CSR(tdata1, CSR_TDATA1) +DECLARE_CSR(tdata2, CSR_TDATA2) +DECLARE_CSR(tdata3, CSR_TDATA3) +DECLARE_CSR(dcsr, CSR_DCSR) +DECLARE_CSR(dpc, CSR_DPC) +DECLARE_CSR(dscratch, CSR_DSCRATCH) +DECLARE_CSR(mcycle, CSR_MCYCLE) +DECLARE_CSR(minstret, CSR_MINSTRET) +DECLARE_CSR(mhpmcounter3, CSR_MHPMCOUNTER3) +DECLARE_CSR(mhpmcounter4, CSR_MHPMCOUNTER4) +DECLARE_CSR(mhpmcounter5, CSR_MHPMCOUNTER5) +DECLARE_CSR(mhpmcounter6, CSR_MHPMCOUNTER6) +DECLARE_CSR(mhpmcounter7, CSR_MHPMCOUNTER7) +DECLARE_CSR(mhpmcounter8, CSR_MHPMCOUNTER8) +DECLARE_CSR(mhpmcounter9, CSR_MHPMCOUNTER9) +DECLARE_CSR(mhpmcounter10, CSR_MHPMCOUNTER10) +DECLARE_CSR(mhpmcounter11, CSR_MHPMCOUNTER11) +DECLARE_CSR(mhpmcounter12, CSR_MHPMCOUNTER12) +DECLARE_CSR(mhpmcounter13, CSR_MHPMCOUNTER13) +DECLARE_CSR(mhpmcounter14, CSR_MHPMCOUNTER14) +DECLARE_CSR(mhpmcounter15, CSR_MHPMCOUNTER15) +DECLARE_CSR(mhpmcounter16, CSR_MHPMCOUNTER16) +DECLARE_CSR(mhpmcounter17, CSR_MHPMCOUNTER17) +DECLARE_CSR(mhpmcounter18, CSR_MHPMCOUNTER18) +DECLARE_CSR(mhpmcounter19, CSR_MHPMCOUNTER19) +DECLARE_CSR(mhpmcounter20, CSR_MHPMCOUNTER20) +DECLARE_CSR(mhpmcounter21, CSR_MHPMCOUNTER21) +DECLARE_CSR(mhpmcounter22, CSR_MHPMCOUNTER22) +DECLARE_CSR(mhpmcounter23, CSR_MHPMCOUNTER23) +DECLARE_CSR(mhpmcounter24, CSR_MHPMCOUNTER24) +DECLARE_CSR(mhpmcounter25, CSR_MHPMCOUNTER25) +DECLARE_CSR(mhpmcounter26, CSR_MHPMCOUNTER26) +DECLARE_CSR(mhpmcounter27, CSR_MHPMCOUNTER27) +DECLARE_CSR(mhpmcounter28, CSR_MHPMCOUNTER28) +DECLARE_CSR(mhpmcounter29, CSR_MHPMCOUNTER29) +DECLARE_CSR(mhpmcounter30, CSR_MHPMCOUNTER30) +DECLARE_CSR(mhpmcounter31, CSR_MHPMCOUNTER31) +DECLARE_CSR(mucounteren, CSR_MUCOUNTEREN) +DECLARE_CSR(mscounteren, CSR_MSCOUNTEREN) +DECLARE_CSR(mhpmevent3, CSR_MHPMEVENT3) +DECLARE_CSR(mhpmevent4, CSR_MHPMEVENT4) +DECLARE_CSR(mhpmevent5, CSR_MHPMEVENT5) +DECLARE_CSR(mhpmevent6, CSR_MHPMEVENT6) +DECLARE_CSR(mhpmevent7, CSR_MHPMEVENT7) +DECLARE_CSR(mhpmevent8, CSR_MHPMEVENT8) +DECLARE_CSR(mhpmevent9, CSR_MHPMEVENT9) +DECLARE_CSR(mhpmevent10, CSR_MHPMEVENT10) +DECLARE_CSR(mhpmevent11, CSR_MHPMEVENT11) +DECLARE_CSR(mhpmevent12, CSR_MHPMEVENT12) +DECLARE_CSR(mhpmevent13, CSR_MHPMEVENT13) +DECLARE_CSR(mhpmevent14, CSR_MHPMEVENT14) +DECLARE_CSR(mhpmevent15, CSR_MHPMEVENT15) +DECLARE_CSR(mhpmevent16, CSR_MHPMEVENT16) +DECLARE_CSR(mhpmevent17, CSR_MHPMEVENT17) +DECLARE_CSR(mhpmevent18, CSR_MHPMEVENT18) +DECLARE_CSR(mhpmevent19, CSR_MHPMEVENT19) +DECLARE_CSR(mhpmevent20, CSR_MHPMEVENT20) +DECLARE_CSR(mhpmevent21, CSR_MHPMEVENT21) +DECLARE_CSR(mhpmevent22, CSR_MHPMEVENT22) +DECLARE_CSR(mhpmevent23, CSR_MHPMEVENT23) +DECLARE_CSR(mhpmevent24, CSR_MHPMEVENT24) +DECLARE_CSR(mhpmevent25, CSR_MHPMEVENT25) +DECLARE_CSR(mhpmevent26, CSR_MHPMEVENT26) +DECLARE_CSR(mhpmevent27, CSR_MHPMEVENT27) +DECLARE_CSR(mhpmevent28, CSR_MHPMEVENT28) +DECLARE_CSR(mhpmevent29, CSR_MHPMEVENT29) +DECLARE_CSR(mhpmevent30, CSR_MHPMEVENT30) +DECLARE_CSR(mhpmevent31, CSR_MHPMEVENT31) +DECLARE_CSR(mvendorid, CSR_MVENDORID) +DECLARE_CSR(marchid, CSR_MARCHID) +DECLARE_CSR(mimpid, CSR_MIMPID) +DECLARE_CSR(mhartid, CSR_MHARTID) +DECLARE_CSR(cycleh, CSR_CYCLEH) +DECLARE_CSR(timeh, CSR_TIMEH) +DECLARE_CSR(instreth, CSR_INSTRETH) +DECLARE_CSR(hpmcounter3h, CSR_HPMCOUNTER3H) +DECLARE_CSR(hpmcounter4h, CSR_HPMCOUNTER4H) +DECLARE_CSR(hpmcounter5h, CSR_HPMCOUNTER5H) +DECLARE_CSR(hpmcounter6h, CSR_HPMCOUNTER6H) +DECLARE_CSR(hpmcounter7h, CSR_HPMCOUNTER7H) +DECLARE_CSR(hpmcounter8h, CSR_HPMCOUNTER8H) +DECLARE_CSR(hpmcounter9h, CSR_HPMCOUNTER9H) +DECLARE_CSR(hpmcounter10h, CSR_HPMCOUNTER10H) +DECLARE_CSR(hpmcounter11h, CSR_HPMCOUNTER11H) +DECLARE_CSR(hpmcounter12h, CSR_HPMCOUNTER12H) +DECLARE_CSR(hpmcounter13h, CSR_HPMCOUNTER13H) +DECLARE_CSR(hpmcounter14h, CSR_HPMCOUNTER14H) +DECLARE_CSR(hpmcounter15h, CSR_HPMCOUNTER15H) +DECLARE_CSR(hpmcounter16h, CSR_HPMCOUNTER16H) +DECLARE_CSR(hpmcounter17h, CSR_HPMCOUNTER17H) +DECLARE_CSR(hpmcounter18h, CSR_HPMCOUNTER18H) +DECLARE_CSR(hpmcounter19h, CSR_HPMCOUNTER19H) +DECLARE_CSR(hpmcounter20h, CSR_HPMCOUNTER20H) +DECLARE_CSR(hpmcounter21h, CSR_HPMCOUNTER21H) +DECLARE_CSR(hpmcounter22h, CSR_HPMCOUNTER22H) +DECLARE_CSR(hpmcounter23h, CSR_HPMCOUNTER23H) +DECLARE_CSR(hpmcounter24h, CSR_HPMCOUNTER24H) +DECLARE_CSR(hpmcounter25h, CSR_HPMCOUNTER25H) +DECLARE_CSR(hpmcounter26h, CSR_HPMCOUNTER26H) +DECLARE_CSR(hpmcounter27h, CSR_HPMCOUNTER27H) +DECLARE_CSR(hpmcounter28h, CSR_HPMCOUNTER28H) +DECLARE_CSR(hpmcounter29h, CSR_HPMCOUNTER29H) +DECLARE_CSR(hpmcounter30h, CSR_HPMCOUNTER30H) +DECLARE_CSR(hpmcounter31h, CSR_HPMCOUNTER31H) +DECLARE_CSR(mcycleh, CSR_MCYCLEH) +DECLARE_CSR(minstreth, CSR_MINSTRETH) +DECLARE_CSR(mhpmcounter3h, CSR_MHPMCOUNTER3H) +DECLARE_CSR(mhpmcounter4h, CSR_MHPMCOUNTER4H) +DECLARE_CSR(mhpmcounter5h, CSR_MHPMCOUNTER5H) +DECLARE_CSR(mhpmcounter6h, CSR_MHPMCOUNTER6H) +DECLARE_CSR(mhpmcounter7h, CSR_MHPMCOUNTER7H) +DECLARE_CSR(mhpmcounter8h, CSR_MHPMCOUNTER8H) +DECLARE_CSR(mhpmcounter9h, CSR_MHPMCOUNTER9H) +DECLARE_CSR(mhpmcounter10h, CSR_MHPMCOUNTER10H) +DECLARE_CSR(mhpmcounter11h, CSR_MHPMCOUNTER11H) +DECLARE_CSR(mhpmcounter12h, CSR_MHPMCOUNTER12H) +DECLARE_CSR(mhpmcounter13h, CSR_MHPMCOUNTER13H) +DECLARE_CSR(mhpmcounter14h, CSR_MHPMCOUNTER14H) +DECLARE_CSR(mhpmcounter15h, CSR_MHPMCOUNTER15H) +DECLARE_CSR(mhpmcounter16h, CSR_MHPMCOUNTER16H) +DECLARE_CSR(mhpmcounter17h, CSR_MHPMCOUNTER17H) +DECLARE_CSR(mhpmcounter18h, CSR_MHPMCOUNTER18H) +DECLARE_CSR(mhpmcounter19h, CSR_MHPMCOUNTER19H) +DECLARE_CSR(mhpmcounter20h, CSR_MHPMCOUNTER20H) +DECLARE_CSR(mhpmcounter21h, CSR_MHPMCOUNTER21H) +DECLARE_CSR(mhpmcounter22h, CSR_MHPMCOUNTER22H) +DECLARE_CSR(mhpmcounter23h, CSR_MHPMCOUNTER23H) +DECLARE_CSR(mhpmcounter24h, CSR_MHPMCOUNTER24H) +DECLARE_CSR(mhpmcounter25h, CSR_MHPMCOUNTER25H) +DECLARE_CSR(mhpmcounter26h, CSR_MHPMCOUNTER26H) +DECLARE_CSR(mhpmcounter27h, CSR_MHPMCOUNTER27H) +DECLARE_CSR(mhpmcounter28h, CSR_MHPMCOUNTER28H) +DECLARE_CSR(mhpmcounter29h, CSR_MHPMCOUNTER29H) +DECLARE_CSR(mhpmcounter30h, CSR_MHPMCOUNTER30H) +DECLARE_CSR(mhpmcounter31h, CSR_MHPMCOUNTER31H) +#endif +#ifdef DECLARE_CAUSE +DECLARE_CAUSE("misaligned fetch", CAUSE_MISALIGNED_FETCH) +DECLARE_CAUSE("fault fetch", CAUSE_FAULT_FETCH) +DECLARE_CAUSE("illegal instruction", CAUSE_ILLEGAL_INSTRUCTION) +DECLARE_CAUSE("breakpoint", CAUSE_BREAKPOINT) +DECLARE_CAUSE("misaligned load", CAUSE_MISALIGNED_LOAD) +DECLARE_CAUSE("fault load", CAUSE_FAULT_LOAD) +DECLARE_CAUSE("misaligned store", CAUSE_MISALIGNED_STORE) +DECLARE_CAUSE("fault store", CAUSE_FAULT_STORE) +DECLARE_CAUSE("user_ecall", CAUSE_USER_ECALL) +DECLARE_CAUSE("supervisor_ecall", CAUSE_SUPERVISOR_ECALL) +DECLARE_CAUSE("hypervisor_ecall", CAUSE_HYPERVISOR_ECALL) +DECLARE_CAUSE("machine_ecall", CAUSE_MACHINE_ECALL) +#endif diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h new file mode 100644 index 0000000000..8845c067fd --- /dev/null +++ b/include/opcode/riscv.h @@ -0,0 +1,342 @@ +/* riscv.h. RISC-V opcode list for GDB, the GNU debugger. + Copyright 2011-2016 Free Software Foundation, Inc. + Contributed by Andrew Waterman + + This file is part of GDB, GAS, and the GNU binutils. + + GDB, GAS, and the GNU binutils are free software; you can redistribute + them and/or modify them under the terms of the GNU General Public + License as published by the Free Software Foundation; either version + 3, or (at your option) any later version. + + GDB, GAS, and the GNU binutils are distributed in the hope that they + will be useful, but WITHOUT ANY WARRANTY; without even the implied + warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See + the GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; see the file COPYING3. If not, + see . */ + +#ifndef _RISCV_H_ +#define _RISCV_H_ + +#include "riscv-opc.h" +#include +#include + +typedef uint64_t insn_t; + +static inline unsigned int riscv_insn_length (insn_t insn) +{ + if ((insn & 0x3) != 0x3) /* RVC. */ + return 2; + if ((insn & 0x1f) != 0x1f) /* Base ISA and extensions in 32-bit space. */ + return 4; + if ((insn & 0x3f) == 0x1f) /* 48-bit extensions. */ + return 6; + if ((insn & 0x7f) == 0x3f) /* 64-bit extensions. */ + return 8; + /* Longer instructions not supported at the moment. */ + return 2; +} + +static const char * const riscv_rm[8] = +{ + "rne", "rtz", "rdn", "rup", "rmm", 0, 0, "dyn" +}; + +static const char * const riscv_pred_succ[16] = +{ + 0, "w", "r", "rw", "o", "ow", "or", "orw", + "i", "iw", "ir", "irw", "io", "iow", "ior", "iorw" +}; + +#define RVC_JUMP_BITS 11 +#define RVC_JUMP_REACH ((1ULL << RVC_JUMP_BITS) * RISCV_JUMP_ALIGN) + +#define RVC_BRANCH_BITS 8 +#define RVC_BRANCH_REACH ((1ULL << RVC_BRANCH_BITS) * RISCV_BRANCH_ALIGN) + +#define RV_X(x, s, n) (((x) >> (s)) & ((1 << (n)) - 1)) +#define RV_IMM_SIGN(x) (-(((x) >> 31) & 1)) + +#define EXTRACT_ITYPE_IMM(x) \ + (RV_X(x, 20, 12) | (RV_IMM_SIGN(x) << 12)) +#define EXTRACT_STYPE_IMM(x) \ + (RV_X(x, 7, 5) | (RV_X(x, 25, 7) << 5) | (RV_IMM_SIGN(x) << 12)) +#define EXTRACT_SBTYPE_IMM(x) \ + ((RV_X(x, 8, 4) << 1) | (RV_X(x, 25, 6) << 5) | (RV_X(x, 7, 1) << 11) | (RV_IMM_SIGN(x) << 12)) +#define EXTRACT_UTYPE_IMM(x) \ + ((RV_X(x, 12, 20) << 12) | (RV_IMM_SIGN(x) << 32)) +#define EXTRACT_UJTYPE_IMM(x) \ + ((RV_X(x, 21, 10) << 1) | (RV_X(x, 20, 1) << 11) | (RV_X(x, 12, 8) << 12) | (RV_IMM_SIGN(x) << 20)) +#define EXTRACT_RVC_IMM(x) \ + (RV_X(x, 2, 5) | (-RV_X(x, 12, 1) << 5)) +#define EXTRACT_RVC_LUI_IMM(x) \ + (EXTRACT_RVC_IMM (x) << RISCV_IMM_BITS) +#define EXTRACT_RVC_SIMM3(x) \ + (RV_X(x, 10, 2) | (-RV_X(x, 12, 1) << 2)) +#define EXTRACT_RVC_ADDI4SPN_IMM(x) \ + ((RV_X(x, 6, 1) << 2) | (RV_X(x, 5, 1) << 3) | (RV_X(x, 11, 2) << 4) | (RV_X(x, 7, 4) << 6)) +#define EXTRACT_RVC_ADDI16SP_IMM(x) \ + ((RV_X(x, 6, 1) << 4) | (RV_X(x, 2, 1) << 5) | (RV_X(x, 5, 1) << 6) | (RV_X(x, 3, 2) << 7) | (-RV_X(x, 12, 1) << 9)) +#define EXTRACT_RVC_LW_IMM(x) \ + ((RV_X(x, 6, 1) << 2) | (RV_X(x, 10, 3) << 3) | (RV_X(x, 5, 1) << 6)) +#define EXTRACT_RVC_LD_IMM(x) \ + ((RV_X(x, 10, 3) << 3) | (RV_X(x, 5, 2) << 6)) +#define EXTRACT_RVC_LWSP_IMM(x) \ + ((RV_X(x, 4, 3) << 2) | (RV_X(x, 12, 1) << 5) | (RV_X(x, 2, 2) << 6)) +#define EXTRACT_RVC_LDSP_IMM(x) \ + ((RV_X(x, 5, 2) << 3) | (RV_X(x, 12, 1) << 5) | (RV_X(x, 2, 3) << 6)) +#define EXTRACT_RVC_SWSP_IMM(x) \ + ((RV_X(x, 9, 4) << 2) | (RV_X(x, 7, 2) << 6)) +#define EXTRACT_RVC_SDSP_IMM(x) \ + ((RV_X(x, 10, 3) << 3) | (RV_X(x, 7, 3) << 6)) +#define EXTRACT_RVC_B_IMM(x) \ + ((RV_X(x, 3, 2) << 1) | (RV_X(x, 10, 2) << 3) | (RV_X(x, 2, 1) << 5) | (RV_X(x, 5, 2) << 6) | (-RV_X(x, 12, 1) << 8)) +#define EXTRACT_RVC_J_IMM(x) \ + ((RV_X(x, 3, 3) << 1) | (RV_X(x, 11, 1) << 4) | (RV_X(x, 2, 1) << 5) | (RV_X(x, 7, 1) << 6) | (RV_X(x, 6, 1) << 7) | (RV_X(x, 9, 2) << 8) | (RV_X(x, 8, 1) << 10) | (-RV_X(x, 12, 1) << 11)) + +#define ENCODE_ITYPE_IMM(x) \ + (RV_X(x, 0, 12) << 20) +#define ENCODE_STYPE_IMM(x) \ + ((RV_X(x, 0, 5) << 7) | (RV_X(x, 5, 7) << 25)) +#define ENCODE_SBTYPE_IMM(x) \ + ((RV_X(x, 1, 4) << 8) | (RV_X(x, 5, 6) << 25) | (RV_X(x, 11, 1) << 7) | (RV_X(x, 12, 1) << 31)) +#define ENCODE_UTYPE_IMM(x) \ + (RV_X(x, 12, 20) << 12) +#define ENCODE_UJTYPE_IMM(x) \ + ((RV_X(x, 1, 10) << 21) | (RV_X(x, 11, 1) << 20) | (RV_X(x, 12, 8) << 12) | (RV_X(x, 20, 1) << 31)) +#define ENCODE_RVC_IMM(x) \ + ((RV_X(x, 0, 5) << 2) | (RV_X(x, 5, 1) << 12)) +#define ENCODE_RVC_LUI_IMM(x) \ + ENCODE_RVC_IMM ((x) >> RISCV_IMM_BITS) +#define ENCODE_RVC_SIMM3(x) \ + (RV_X(x, 0, 3) << 10) +#define ENCODE_RVC_ADDI4SPN_IMM(x) \ + ((RV_X(x, 2, 1) << 6) | (RV_X(x, 3, 1) << 5) | (RV_X(x, 4, 2) << 11) | (RV_X(x, 6, 4) << 7)) +#define ENCODE_RVC_ADDI16SP_IMM(x) \ + ((RV_X(x, 4, 1) << 6) | (RV_X(x, 5, 1) << 2) | (RV_X(x, 6, 1) << 5) | (RV_X(x, 7, 2) << 3) | (RV_X(x, 9, 1) << 12)) +#define ENCODE_RVC_LW_IMM(x) \ + ((RV_X(x, 2, 1) << 6) | (RV_X(x, 3, 3) << 10) | (RV_X(x, 6, 1) << 5)) +#define ENCODE_RVC_LD_IMM(x) \ + ((RV_X(x, 3, 3) << 10) | (RV_X(x, 6, 2) << 5)) +#define ENCODE_RVC_LWSP_IMM(x) \ + ((RV_X(x, 2, 3) << 4) | (RV_X(x, 5, 1) << 12) | (RV_X(x, 6, 2) << 2)) +#define ENCODE_RVC_LDSP_IMM(x) \ + ((RV_X(x, 3, 2) << 5) | (RV_X(x, 5, 1) << 12) | (RV_X(x, 6, 3) << 2)) +#define ENCODE_RVC_SWSP_IMM(x) \ + ((RV_X(x, 2, 4) << 9) | (RV_X(x, 6, 2) << 7)) +#define ENCODE_RVC_SDSP_IMM(x) \ + ((RV_X(x, 3, 3) << 10) | (RV_X(x, 6, 3) << 7)) +#define ENCODE_RVC_B_IMM(x) \ + ((RV_X(x, 1, 2) << 3) | (RV_X(x, 3, 2) << 10) | (RV_X(x, 5, 1) << 2) | (RV_X(x, 6, 2) << 5) | (RV_X(x, 8, 1) << 12)) +#define ENCODE_RVC_J_IMM(x) \ + ((RV_X(x, 1, 3) << 3) | (RV_X(x, 4, 1) << 11) | (RV_X(x, 5, 1) << 2) | (RV_X(x, 6, 1) << 7) | (RV_X(x, 7, 1) << 6) | (RV_X(x, 8, 2) << 9) | (RV_X(x, 10, 1) << 8) | (RV_X(x, 11, 1) << 12)) + +#define VALID_ITYPE_IMM(x) (EXTRACT_ITYPE_IMM(ENCODE_ITYPE_IMM(x)) == (x)) +#define VALID_STYPE_IMM(x) (EXTRACT_STYPE_IMM(ENCODE_STYPE_IMM(x)) == (x)) +#define VALID_SBTYPE_IMM(x) (EXTRACT_SBTYPE_IMM(ENCODE_SBTYPE_IMM(x)) == (x)) +#define VALID_UTYPE_IMM(x) (EXTRACT_UTYPE_IMM(ENCODE_UTYPE_IMM(x)) == (x)) +#define VALID_UJTYPE_IMM(x) (EXTRACT_UJTYPE_IMM(ENCODE_UJTYPE_IMM(x)) == (x)) +#define VALID_RVC_IMM(x) (EXTRACT_RVC_IMM(ENCODE_RVC_IMM(x)) == (x)) +#define VALID_RVC_LUI_IMM(x) (EXTRACT_RVC_LUI_IMM(ENCODE_RVC_LUI_IMM(x)) == (x)) +#define VALID_RVC_SIMM3(x) (EXTRACT_RVC_SIMM3(ENCODE_RVC_SIMM3(x)) == (x)) +#define VALID_RVC_ADDI4SPN_IMM(x) (EXTRACT_RVC_ADDI4SPN_IMM(ENCODE_RVC_ADDI4SPN_IMM(x)) == (x)) +#define VALID_RVC_ADDI16SP_IMM(x) (EXTRACT_RVC_ADDI16SP_IMM(ENCODE_RVC_ADDI16SP_IMM(x)) == (x)) +#define VALID_RVC_LW_IMM(x) (EXTRACT_RVC_LW_IMM(ENCODE_RVC_LW_IMM(x)) == (x)) +#define VALID_RVC_LD_IMM(x) (EXTRACT_RVC_LD_IMM(ENCODE_RVC_LD_IMM(x)) == (x)) +#define VALID_RVC_LWSP_IMM(x) (EXTRACT_RVC_LWSP_IMM(ENCODE_RVC_LWSP_IMM(x)) == (x)) +#define VALID_RVC_LDSP_IMM(x) (EXTRACT_RVC_LDSP_IMM(ENCODE_RVC_LDSP_IMM(x)) == (x)) +#define VALID_RVC_SWSP_IMM(x) (EXTRACT_RVC_SWSP_IMM(ENCODE_RVC_SWSP_IMM(x)) == (x)) +#define VALID_RVC_SDSP_IMM(x) (EXTRACT_RVC_SDSP_IMM(ENCODE_RVC_SDSP_IMM(x)) == (x)) +#define VALID_RVC_B_IMM(x) (EXTRACT_RVC_B_IMM(ENCODE_RVC_B_IMM(x)) == (x)) +#define VALID_RVC_J_IMM(x) (EXTRACT_RVC_J_IMM(ENCODE_RVC_J_IMM(x)) == (x)) + +#define RISCV_RTYPE(insn, rd, rs1, rs2) \ + ((MATCH_ ## insn) | ((rd) << OP_SH_RD) | ((rs1) << OP_SH_RS1) | ((rs2) << OP_SH_RS2)) +#define RISCV_ITYPE(insn, rd, rs1, imm) \ + ((MATCH_ ## insn) | ((rd) << OP_SH_RD) | ((rs1) << OP_SH_RS1) | ENCODE_ITYPE_IMM(imm)) +#define RISCV_STYPE(insn, rs1, rs2, imm) \ + ((MATCH_ ## insn) | ((rs1) << OP_SH_RS1) | ((rs2) << OP_SH_RS2) | ENCODE_STYPE_IMM(imm)) +#define RISCV_SBTYPE(insn, rs1, rs2, target) \ + ((MATCH_ ## insn) | ((rs1) << OP_SH_RS1) | ((rs2) << OP_SH_RS2) | ENCODE_SBTYPE_IMM(target)) +#define RISCV_UTYPE(insn, rd, bigimm) \ + ((MATCH_ ## insn) | ((rd) << OP_SH_RD) | ENCODE_UTYPE_IMM(bigimm)) +#define RISCV_UJTYPE(insn, rd, target) \ + ((MATCH_ ## insn) | ((rd) << OP_SH_RD) | ENCODE_UJTYPE_IMM(target)) + +#define RISCV_NOP RISCV_ITYPE(ADDI, 0, 0, 0) +#define RVC_NOP MATCH_C_ADDI + +#define RISCV_CONST_HIGH_PART(VALUE) \ + (((VALUE) + (RISCV_IMM_REACH/2)) & ~(RISCV_IMM_REACH-1)) +#define RISCV_CONST_LOW_PART(VALUE) ((VALUE) - RISCV_CONST_HIGH_PART (VALUE)) +#define RISCV_PCREL_HIGH_PART(VALUE, PC) RISCV_CONST_HIGH_PART((VALUE) - (PC)) +#define RISCV_PCREL_LOW_PART(VALUE, PC) RISCV_CONST_LOW_PART((VALUE) - (PC)) + +#define RISCV_JUMP_BITS RISCV_BIGIMM_BITS +#define RISCV_JUMP_ALIGN_BITS 1 +#define RISCV_JUMP_ALIGN (1 << RISCV_JUMP_ALIGN_BITS) +#define RISCV_JUMP_REACH ((1ULL << RISCV_JUMP_BITS) * RISCV_JUMP_ALIGN) + +#define RISCV_IMM_BITS 12 +#define RISCV_BIGIMM_BITS (32 - RISCV_IMM_BITS) +#define RISCV_IMM_REACH (1LL << RISCV_IMM_BITS) +#define RISCV_BIGIMM_REACH (1LL << RISCV_BIGIMM_BITS) +#define RISCV_RVC_IMM_REACH (1LL << 6) +#define RISCV_BRANCH_BITS RISCV_IMM_BITS +#define RISCV_BRANCH_ALIGN_BITS RISCV_JUMP_ALIGN_BITS +#define RISCV_BRANCH_ALIGN (1 << RISCV_BRANCH_ALIGN_BITS) +#define RISCV_BRANCH_REACH (RISCV_IMM_REACH * RISCV_BRANCH_ALIGN) + +/* RV fields. */ + +#define OP_MASK_OP 0x7f +#define OP_SH_OP 0 +#define OP_MASK_RS2 0x1f +#define OP_SH_RS2 20 +#define OP_MASK_RS1 0x1f +#define OP_SH_RS1 15 +#define OP_MASK_RS3 0x1f +#define OP_SH_RS3 27 +#define OP_MASK_RD 0x1f +#define OP_SH_RD 7 +#define OP_MASK_SHAMT 0x3f +#define OP_SH_SHAMT 20 +#define OP_MASK_SHAMTW 0x1f +#define OP_SH_SHAMTW 20 +#define OP_MASK_RM 0x7 +#define OP_SH_RM 12 +#define OP_MASK_PRED 0xf +#define OP_SH_PRED 24 +#define OP_MASK_SUCC 0xf +#define OP_SH_SUCC 20 +#define OP_MASK_AQ 0x1 +#define OP_SH_AQ 26 +#define OP_MASK_RL 0x1 +#define OP_SH_RL 25 + +#define OP_MASK_CUSTOM_IMM 0x7f +#define OP_SH_CUSTOM_IMM 25 +#define OP_MASK_CSR 0xfff +#define OP_SH_CSR 20 + +/* RVC fields. */ + +#define OP_MASK_CRS2 0x1f +#define OP_SH_CRS2 2 +#define OP_MASK_CRS1S 0x7 +#define OP_SH_CRS1S 7 +#define OP_MASK_CRS2S 0x7 +#define OP_SH_CRS2S 2 + +/* ABI names for selected x-registers. */ + +#define X_RA 1 +#define X_SP 2 +#define X_GP 3 +#define X_TP 4 +#define X_T0 5 +#define X_T1 6 +#define X_T2 7 +#define X_T3 28 + +#define NGPR 32 +#define NFPR 32 + +/* Replace bits MASK << SHIFT of STRUCT with the equivalent bits in + VALUE << SHIFT. VALUE is evaluated exactly once. */ +#define INSERT_BITS(STRUCT, VALUE, MASK, SHIFT) \ + (STRUCT) = (((STRUCT) & ~((insn_t)(MASK) << (SHIFT))) \ + | ((insn_t)((VALUE) & (MASK)) << (SHIFT))) + +/* Extract bits MASK << SHIFT from STRUCT and shift them right + SHIFT places. */ +#define EXTRACT_BITS(STRUCT, MASK, SHIFT) \ + (((STRUCT) >> (SHIFT)) & (MASK)) + +/* Extract the operand given by FIELD from integer INSN. */ +#define EXTRACT_OPERAND(FIELD, INSN) \ + EXTRACT_BITS ((INSN), OP_MASK_##FIELD, OP_SH_##FIELD) + +/* This structure holds information for a particular instruction. */ + +struct riscv_opcode +{ + /* The name of the instruction. */ + const char *name; + /* The ISA subset name (I, M, A, F, D, Xextension). */ + const char *subset; + /* A string describing the arguments for this instruction. */ + const char *args; + /* The basic opcode for the instruction. When assembling, this + opcode is modified by the arguments to produce the actual opcode + that is used. If pinfo is INSN_MACRO, then this is 0. */ + insn_t match; + /* If pinfo is not INSN_MACRO, then this is a bit mask for the + relevant portions of the opcode when disassembling. If the + actual opcode anded with the match field equals the opcode field, + then we have found the correct instruction. If pinfo is + INSN_MACRO, then this field is the macro identifier. */ + insn_t mask; + /* A function to determine if a word corresponds to this instruction. + Usually, this computes ((word & mask) == match). */ + int (*match_func) (const struct riscv_opcode *op, insn_t word); + /* For a macro, this is INSN_MACRO. Otherwise, it is a collection + of bits describing the instruction, notably any relevant hazard + information. */ + unsigned long pinfo; +}; + +/* Instruction is a simple alias (e.g. "mv" for "addi"). */ +#define INSN_ALIAS 0x00000001 +/* Instruction is actually a macro. It should be ignored by the + disassembler, and requires special treatment by the assembler. */ +#define INSN_MACRO 0xffffffff + +/* This is a list of macro expanded instructions. + + _I appended means immediate + _A appended means address + _AB appended means address with base register + _D appended means 64 bit floating point constant + _S appended means 32 bit floating point constant. */ + +enum +{ + M_LA, + M_LLA, + M_LA_TLS_GD, + M_LA_TLS_IE, + M_LB, + M_LBU, + M_LH, + M_LHU, + M_LW, + M_LWU, + M_LD, + M_SB, + M_SH, + M_SW, + M_SD, + M_FLW, + M_FLD, + M_FSW, + M_FSD, + M_CALL, + M_J, + M_LI, + M_NUM_MACROS +}; + + +extern const char * const riscv_gpr_names_numeric[NGPR]; +extern const char * const riscv_gpr_names_abi[NGPR]; +extern const char * const riscv_fpr_names_numeric[NFPR]; +extern const char * const riscv_fpr_names_abi[NFPR]; + +extern const struct riscv_opcode riscv_opcodes[]; + +#endif /* _RISCV_H_ */ diff --git a/ld/ChangeLog b/ld/ChangeLog index dacdf8ee02..a2fb4a466f 100644 --- a/ld/ChangeLog +++ b/ld/ChangeLog @@ -1,3 +1,17 @@ +2016-11-01 Palmer Dabbelt + Andrew Waterman + + Add support for RISC-V architecture. + * Makefile.am: Add riscv files. + * Makefile.in: Regenerate. + * NEWS: Mention the support for this target. + * configure.tgt: Add riscv entries. + * emulparams/elf32lriscv-defs.sh: New file. + * emulparams/elf32lriscv.sh: New file. + * emulparams/elf64lriscv-defs.sh: New file. + * emulparams/elf64lriscv.sh: New file. + * emultempl/riscvelf.em: New file. + 2016-10-31 Thomas Preud'homme * ldmain.c (add_archive_element): Initialize input->header.type. diff --git a/ld/Makefile.am b/ld/Makefile.am index 1a7fc3fe67..9b3de72873 100644 --- a/ld/Makefile.am +++ b/ld/Makefile.am @@ -278,6 +278,7 @@ ALL_EMULATION_SOURCES = \ eelf32ppcsim.c \ eelf32ppcvxworks.c \ eelf32ppcwindiss.c \ + eelf32lriscv.c \ eelf32rl78.c \ eelf32rx.c \ eelf32tilegx.c \ @@ -494,6 +495,7 @@ ALL_64_EMULATION_SOURCES = \ eelf64btsmip_fbsd.c \ eelf64hppa.c \ eelf64lppc.c \ + eelf64lriscv.c \ eelf64ltsmip.c \ eelf64ltsmip_fbsd.c \ eelf64mmix.c \ @@ -1165,6 +1167,11 @@ eelf32lppcsim.c: $(srcdir)/emulparams/elf32lppcsim.sh \ $(srcdir)/emultempl/ppc32elf.em ldemul-list.h \ $(ELF_DEPS) $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} +eelf32lriscv.c: $(srcdir)/emulparams/elf32lriscv.sh \ + $(srcdir)/emulparams/elf32lriscv-defs.sh $(ELF_DEPS) \ + $(srcdir)/emultempl/riscvelf.em $(srcdir)/scripttempl/elf.sc \ + ${GEN_DEPENDS} + eelf32lsmip.c: $(srcdir)/emulparams/elf32lsmip.sh \ $(srcdir)/emulparams/elf32lmip.sh $(srcdir)/emulparams/elf32bmip.sh \ $(ELF_DEPS) $(srcdir)/emultempl/mipself.em $(srcdir)/scripttempl/elf.sc \ @@ -1959,6 +1966,12 @@ eelf64lppc.c: $(srcdir)/emulparams/elf64lppc.sh \ ldemul-list.h \ $(ELF_DEPS) $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} +eelf64lriscv.c: $(srcdir)/emulparams/elf64lriscv.sh \ + $(srcdir)/emulparams/elf64lriscv-defs.sh \ + $(srcdir)/emulparams/elf32lriscv-defs.sh $(ELF_DEPS) \ + $(srcdir)/emultempl/riscvelf.em $(srcdir)/scripttempl/elf.sc \ + ${GEN_DEPENDS} + eelf64ltsmip.c: $(srcdir)/emulparams/elf64ltsmip.sh \ $(srcdir)/emulparams/elf64btsmip.sh $(srcdir)/emulparams/elf64bmip-defs.sh \ $(srcdir)/emulparams/elf32bmipn32-defs.sh $(ELF_DEPS) \ diff --git a/ld/Makefile.in b/ld/Makefile.in index 3511e5f120..f87408e283 100644 --- a/ld/Makefile.in +++ b/ld/Makefile.in @@ -647,6 +647,7 @@ ALL_EMULATION_SOURCES = \ eelf32ppcsim.c \ eelf32ppcvxworks.c \ eelf32ppcwindiss.c \ + eelf32lriscv.c \ eelf32rl78.c \ eelf32rx.c \ eelf32tilegx.c \ @@ -862,6 +863,7 @@ ALL_64_EMULATION_SOURCES = \ eelf64btsmip_fbsd.c \ eelf64hppa.c \ eelf64lppc.c \ + eelf64lriscv.c \ eelf64ltsmip.c \ eelf64ltsmip_fbsd.c \ eelf64mmix.c \ @@ -1282,6 +1284,7 @@ distclean-compile: @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf32lppcsim.Po@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf32lr5900.Po@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf32lr5900n32.Po@am__quote@ +@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf32lriscv.Po@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf32lsmip.Po@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf32ltsmip.Po@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf32ltsmip_fbsd.Po@am__quote@ @@ -1335,6 +1338,7 @@ distclean-compile: @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf64btsmip_fbsd.Po@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf64hppa.Po@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf64lppc.Po@am__quote@ +@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf64lriscv.Po@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf64ltsmip.Po@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf64ltsmip_fbsd.Po@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf64mmix.Po@am__quote@ @@ -2754,6 +2758,11 @@ eelf32lppcsim.c: $(srcdir)/emulparams/elf32lppcsim.sh \ $(srcdir)/emultempl/ppc32elf.em ldemul-list.h \ $(ELF_DEPS) $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} +eelf32lriscv.c: $(srcdir)/emulparams/elf32lriscv.sh \ + $(srcdir)/emulparams/elf32lriscv-defs.sh $(ELF_DEPS) \ + $(srcdir)/emultempl/riscvelf.em $(srcdir)/scripttempl/elf.sc \ + ${GEN_DEPENDS} + eelf32lsmip.c: $(srcdir)/emulparams/elf32lsmip.sh \ $(srcdir)/emulparams/elf32lmip.sh $(srcdir)/emulparams/elf32bmip.sh \ $(ELF_DEPS) $(srcdir)/emultempl/mipself.em $(srcdir)/scripttempl/elf.sc \ @@ -3548,6 +3557,12 @@ eelf64lppc.c: $(srcdir)/emulparams/elf64lppc.sh \ ldemul-list.h \ $(ELF_DEPS) $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} +eelf64lriscv.c: $(srcdir)/emulparams/elf64lriscv.sh \ + $(srcdir)/emulparams/elf64lriscv-defs.sh \ + $(srcdir)/emulparams/elf32lriscv-defs.sh $(ELF_DEPS) \ + $(srcdir)/emultempl/riscvelf.em $(srcdir)/scripttempl/elf.sc \ + ${GEN_DEPENDS} + eelf64ltsmip.c: $(srcdir)/emulparams/elf64ltsmip.sh \ $(srcdir)/emulparams/elf64btsmip.sh $(srcdir)/emulparams/elf64bmip-defs.sh \ $(srcdir)/emulparams/elf32bmipn32-defs.sh $(ELF_DEPS) \ diff --git a/ld/NEWS b/ld/NEWS index 2bb429ff21..0efa411243 100644 --- a/ld/NEWS +++ b/ld/NEWS @@ -1,6 +1,6 @@ -*- text -*- -Changes in 2.28: +* Add support for the RISC-V architecture. * The command line option --no-eh-frame-hdr can now be used in ELF based linkers to disable the automatic generation of .eh_frame_hdr sections. diff --git a/ld/configure.tgt b/ld/configure.tgt index 6f3cd4fc37..c196e68480 100644 --- a/ld/configure.tgt +++ b/ld/configure.tgt @@ -679,6 +679,12 @@ powerpc-*-aix*) targ_emul=aixppc ;; powerpc-*-beos*) targ_emul=aixppc ;; powerpc-*-windiss*) targ_emul=elf32ppcwindiss ;; powerpc-*-lynxos*) targ_emul=ppclynx ;; +riscv32*-*-*) targ_emul=elf32lriscv + targ_extra_emuls="elf64lriscv" + targ_extra_libpath=$targ_extra_emuls ;; +riscv64*-*-*) targ_emul=elf64lriscv + targ_extra_emuls="elf32lriscv" + targ_extra_libpath=$targ_extra_emuls ;; rs6000-*-aix[5-9]*) targ_emul=aix5rs6 ;; rs6000-*-aix*) targ_emul=aixrs6 ;; diff --git a/ld/emulparams/elf32lriscv-defs.sh b/ld/emulparams/elf32lriscv-defs.sh new file mode 100644 index 0000000000..0e4b7237ff --- /dev/null +++ b/ld/emulparams/elf32lriscv-defs.sh @@ -0,0 +1,42 @@ +# This is an ELF platform. +SCRIPT_NAME=elf +ARCH=riscv +NO_REL_RELOCS=yes + +TEMPLATE_NAME=elf32 +EXTRA_EM_FILE=riscvelf + +ELFSIZE=32 + +if test `echo "$host" | sed -e s/64//` = `echo "$target" | sed -e s/64//`; then + case " $EMULATION_LIBPATH " in + *" ${EMULATION_NAME} "*) + NATIVE=yes + ;; + esac +fi + +GENERATE_SHLIB_SCRIPT=yes +GENERATE_PIE_SCRIPT=yes + +TEXT_START_ADDR=0x10000 +MAXPAGESIZE="CONSTANT (MAXPAGESIZE)" +COMMONPAGESIZE="CONSTANT (COMMONPAGESIZE)" + +SDATA_START_SYMBOLS="_gp = . + 0x800; + *(.srodata.cst16) *(.srodata.cst8) *(.srodata.cst4) *(.srodata.cst2) *(.srodata .srodata.*)" + +# Place the data section before text section. This enables more compact +# global variable access for RVC code via linker relaxation. +INITIAL_READONLY_SECTIONS=" + .data : { *(.data) *(.data.*) *(.gnu.linkonce.d.*) } + .rodata : { *(.rodata) *(.rodata.*) *(.gnu.linkonce.r.*) } + .srodata : { ${SDATA_START_SYMBOLS} } + .sdata : { *(.sdata .sdata.* .gnu.linkonce.s.*) } + .sbss : { *(.dynsbss) *(.sbss .sbss.* .gnu.linkonce.sb.*) } + .bss : { *(.dynbss) *(.bss .bss.* .gnu.linkonce.b.*) *(COMMON) } + . = ALIGN(${SEGMENT_SIZE}) + (. & (${MAXPAGESIZE} - 1));" +INITIAL_READONLY_SECTIONS=".interp : { *(.interp) } ${CREATE_PIE-${INITIAL_READONLY_SECTIONS}}" +INITIAL_READONLY_SECTIONS="${RELOCATING+${CREATE_SHLIB-${INITIAL_READONLY_SECTIONS}}}" + +SDATA_START_SYMBOLS="${CREATE_PIE+${SDATA_START_SYMBOLS}}" diff --git a/ld/emulparams/elf32lriscv.sh b/ld/emulparams/elf32lriscv.sh new file mode 100644 index 0000000000..aac08e78f1 --- /dev/null +++ b/ld/emulparams/elf32lriscv.sh @@ -0,0 +1,2 @@ +. ${srcdir}/emulparams/elf32lriscv-defs.sh +OUTPUT_FORMAT="elf32-littleriscv" diff --git a/ld/emulparams/elf64lriscv-defs.sh b/ld/emulparams/elf64lriscv-defs.sh new file mode 100644 index 0000000000..6308714207 --- /dev/null +++ b/ld/emulparams/elf64lriscv-defs.sh @@ -0,0 +1,13 @@ +. ${srcdir}/emulparams/elf32lriscv-defs.sh +ELFSIZE=64 + +# Look for 64 bit target libraries in /lib64, /usr/lib64 etc., first +# on Linux. +case "$target" in + riscv64*-linux*) + case "$EMULATION_NAME" in + *64*) + LIBPATH_SUFFIX=64 ;; + esac + ;; +esac diff --git a/ld/emulparams/elf64lriscv.sh b/ld/emulparams/elf64lriscv.sh new file mode 100644 index 0000000000..3a6a652c9d --- /dev/null +++ b/ld/emulparams/elf64lriscv.sh @@ -0,0 +1,2 @@ +. ${srcdir}/emulparams/elf64lriscv-defs.sh +OUTPUT_FORMAT="elf64-littleriscv" diff --git a/ld/emultempl/riscvelf.em b/ld/emultempl/riscvelf.em new file mode 100644 index 0000000000..027145f35f --- /dev/null +++ b/ld/emultempl/riscvelf.em @@ -0,0 +1,68 @@ +# This shell script emits a C file. -*- C -*- +# Copyright 2004, 2006, 2007, 2008, 2016 Free Software Foundation, Inc. +# +# This file is part of the GNU Binutils. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 3 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, +# MA 02110-1301, USA. + +fragment < + Andrew Waterman + + Add support for RISC-V architecture. + * configure.ac: Add entry for bfd_riscv_arch. + * configure: Regenerate. + * disassemble.c (disassembler): Add support for riscv. + (disassembler_usage): Likewise. + * riscv-dis.c: New file. + * riscv-opc.c: New file. + 2016-10-21 H.J. Lu * i386-dis.c (PREFIX_RM_0_0FAE_REG_7): Removed. diff --git a/opcodes/configure b/opcodes/configure index 031da2fa9c..6ef38444c1 100755 --- a/opcodes/configure +++ b/opcodes/configure @@ -12685,6 +12685,7 @@ if test x${all_targets} = xfalse ; then bfd_powerpc_64_arch) ta="$ta ppc-dis.lo ppc-opc.lo" ;; bfd_pyramid_arch) ;; bfd_romp_arch) ;; + bfd_riscv_arch) ta="$ta riscv-dis.lo riscv-opc.lo" ;; bfd_rs6000_arch) ta="$ta ppc-dis.lo ppc-opc.lo" ;; bfd_rl78_arch) ta="$ta rl78-dis.lo rl78-decode.lo";; bfd_rx_arch) ta="$ta rx-dis.lo rx-decode.lo";; diff --git a/opcodes/configure.ac b/opcodes/configure.ac index c7f4783718..3475d491c5 100644 --- a/opcodes/configure.ac +++ b/opcodes/configure.ac @@ -309,6 +309,7 @@ if test x${all_targets} = xfalse ; then bfd_powerpc_64_arch) ta="$ta ppc-dis.lo ppc-opc.lo" ;; bfd_pyramid_arch) ;; bfd_romp_arch) ;; + bfd_riscv_arch) ta="$ta riscv-dis.lo riscv-opc.lo" ;; bfd_rs6000_arch) ta="$ta ppc-dis.lo ppc-opc.lo" ;; bfd_rl78_arch) ta="$ta rl78-dis.lo rl78-decode.lo";; bfd_rx_arch) ta="$ta rx-dis.lo rx-decode.lo";; diff --git a/opcodes/disassemble.c b/opcodes/disassemble.c index 45ae34e70c..e1fb65c823 100644 --- a/opcodes/disassemble.c +++ b/opcodes/disassemble.c @@ -375,6 +375,11 @@ disassembler (bfd *abfd) disassemble = print_insn_little_powerpc; break; #endif +#ifdef ARCH_riscv + case bfd_arch_riscv: + disassemble = print_insn_riscv; + break; +#endif #ifdef ARCH_rs6000 case bfd_arch_rs6000: if (bfd_get_mach (abfd) == bfd_mach_ppc_620) @@ -559,6 +564,9 @@ disassembler_usage (FILE *stream ATTRIBUTE_UNUSED) #ifdef ARCH_powerpc print_ppc_disassembler_options (stream); #endif +#ifdef ARCH_riscv + print_riscv_disassembler_options (stream); +#endif #ifdef ARCH_i386 print_i386_disassembler_options (stream); #endif diff --git a/opcodes/riscv-dis.c b/opcodes/riscv-dis.c new file mode 100644 index 0000000000..3b4e1e01ef --- /dev/null +++ b/opcodes/riscv-dis.c @@ -0,0 +1,502 @@ +/* RISC-V disassembler + Copyright 2011-2016 Free Software Foundation, Inc. + + Contributed by Andrew Waterman (andrew@sifive.com). + Based on MIPS target. + + This file is part of the GNU opcodes library. + + This library is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. + + It is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + You should have received a copy of the GNU General Public License + along with this program; see the file COPYING3. If not, + see . */ + +#include "sysdep.h" +#include "dis-asm.h" +#include "libiberty.h" +#include "opcode/riscv.h" +#include "opintl.h" +#include "elf-bfd.h" +#include "elf/riscv.h" + +#include +#include + +struct riscv_private_data +{ + bfd_vma gp; + bfd_vma print_addr; + bfd_vma hi_addr[OP_MASK_RD + 1]; +}; + +static const char * const *riscv_gpr_names; +static const char * const *riscv_fpr_names; + +/* Other options. */ +static int no_aliases; /* If set disassemble as most general inst. */ + +static void +set_default_riscv_dis_options (void) +{ + riscv_gpr_names = riscv_gpr_names_abi; + riscv_fpr_names = riscv_fpr_names_abi; + no_aliases = 0; +} + +static void +parse_riscv_dis_option (const char *option) +{ + if (strcmp (option, "no-aliases") == 0) + no_aliases = 1; + else if (strcmp (option, "numeric") == 0) + { + riscv_gpr_names = riscv_gpr_names_numeric; + riscv_fpr_names = riscv_fpr_names_numeric; + } + else + { + /* Invalid option. */ + fprintf (stderr, _("Unrecognized disassembler option: %s\n"), option); + } +} + +static void +parse_riscv_dis_options (const char *opts_in) +{ + char *opts = xstrdup (opts_in), *opt = opts, *opt_end = opts; + + set_default_riscv_dis_options (); + + for ( ; opt_end != NULL; opt = opt_end + 1) + { + if ((opt_end = strchr (opt, ',')) != NULL) + *opt_end = 0; + parse_riscv_dis_option (opt); + } + + free (opts); +} + +/* Print one argument from an array. */ + +static void +arg_print (struct disassemble_info *info, unsigned long val, + const char* const* array, size_t size) +{ + const char *s = val >= size || array[val] == NULL ? "unknown" : array[val]; + (*info->fprintf_func) (info->stream, "%s", s); +} + +static void +maybe_print_address (struct riscv_private_data *pd, int base_reg, int offset) +{ + if (pd->hi_addr[base_reg] != (bfd_vma)-1) + { + pd->print_addr = pd->hi_addr[base_reg] + offset; + pd->hi_addr[base_reg] = -1; + } + else if (base_reg == X_GP && pd->gp != (bfd_vma)-1) + pd->print_addr = pd->gp + offset; + else if (base_reg == X_TP || base_reg == 0) + pd->print_addr = offset; +} + +/* Print insn arguments for 32/64-bit code. */ + +static void +print_insn_args (const char *d, insn_t l, bfd_vma pc, disassemble_info *info) +{ + struct riscv_private_data *pd = info->private_data; + int rs1 = (l >> OP_SH_RS1) & OP_MASK_RS1; + int rd = (l >> OP_SH_RD) & OP_MASK_RD; + fprintf_ftype print = info->fprintf_func; + + if (*d != '\0') + print (info->stream, "\t"); + + for (; *d != '\0'; d++) + { + switch (*d) + { + case 'C': /* RVC */ + switch (*++d) + { + case 's': /* RS1 x8-x15 */ + case 'w': /* RS1 x8-x15 */ + print (info->stream, "%s", + riscv_gpr_names[EXTRACT_OPERAND (CRS1S, l) + 8]); + break; + case 't': /* RS2 x8-x15 */ + case 'x': /* RS2 x8-x15 */ + print (info->stream, "%s", + riscv_gpr_names[EXTRACT_OPERAND (CRS2S, l) + 8]); + break; + case 'U': /* RS1, constrained to equal RD */ + print (info->stream, "%s", riscv_gpr_names[rd]); + break; + case 'c': /* RS1, constrained to equal sp */ + print (info->stream, "%s", riscv_gpr_names[X_SP]); + break; + case 'V': /* RS2 */ + print (info->stream, "%s", + riscv_gpr_names[EXTRACT_OPERAND (CRS2, l)]); + break; + case 'i': + print (info->stream, "%d", (int)EXTRACT_RVC_SIMM3 (l)); + break; + case 'j': + print (info->stream, "%d", (int)EXTRACT_RVC_IMM (l)); + break; + case 'k': + print (info->stream, "%d", (int)EXTRACT_RVC_LW_IMM (l)); + break; + case 'l': + print (info->stream, "%d", (int)EXTRACT_RVC_LD_IMM (l)); + break; + case 'm': + print (info->stream, "%d", (int)EXTRACT_RVC_LWSP_IMM (l)); + break; + case 'n': + print (info->stream, "%d", (int)EXTRACT_RVC_LDSP_IMM (l)); + break; + case 'K': + print (info->stream, "%d", (int)EXTRACT_RVC_ADDI4SPN_IMM (l)); + break; + case 'L': + print (info->stream, "%d", (int)EXTRACT_RVC_ADDI16SP_IMM (l)); + break; + case 'M': + print (info->stream, "%d", (int)EXTRACT_RVC_SWSP_IMM (l)); + break; + case 'N': + print (info->stream, "%d", (int)EXTRACT_RVC_SDSP_IMM (l)); + break; + case 'p': + info->target = EXTRACT_RVC_B_IMM (l) + pc; + (*info->print_address_func) (info->target, info); + break; + case 'a': + info->target = EXTRACT_RVC_J_IMM (l) + pc; + (*info->print_address_func) (info->target, info); + break; + case 'u': + print (info->stream, "0x%x", + (int)(EXTRACT_RVC_IMM (l) & (RISCV_BIGIMM_REACH-1))); + break; + case '>': + print (info->stream, "0x%x", (int)EXTRACT_RVC_IMM (l) & 0x3f); + break; + case '<': + print (info->stream, "0x%x", (int)EXTRACT_RVC_IMM (l) & 0x1f); + break; + case 'T': /* floating-point RS2 */ + print (info->stream, "%s", + riscv_fpr_names[EXTRACT_OPERAND (CRS2, l)]); + break; + case 'D': /* floating-point RS2 x8-x15 */ + print (info->stream, "%s", + riscv_fpr_names[EXTRACT_OPERAND (CRS2S, l) + 8]); + break; + } + break; + + case ',': + case '(': + case ')': + case '[': + case ']': + print (info->stream, "%c", *d); + break; + + case '0': + /* Only print constant 0 if it is the last argument */ + if (!d[1]) + print (info->stream, "0"); + break; + + case 'b': + case 's': + print (info->stream, "%s", riscv_gpr_names[rs1]); + break; + + case 't': + print (info->stream, "%s", + riscv_gpr_names[EXTRACT_OPERAND (RS2, l)]); + break; + + case 'u': + print (info->stream, "0x%x", + (unsigned)EXTRACT_UTYPE_IMM (l) >> RISCV_IMM_BITS); + break; + + case 'm': + arg_print (info, EXTRACT_OPERAND (RM, l), + riscv_rm, ARRAY_SIZE (riscv_rm)); + break; + + case 'P': + arg_print (info, EXTRACT_OPERAND (PRED, l), + riscv_pred_succ, ARRAY_SIZE (riscv_pred_succ)); + break; + + case 'Q': + arg_print (info, EXTRACT_OPERAND (SUCC, l), + riscv_pred_succ, ARRAY_SIZE (riscv_pred_succ)); + break; + + case 'o': + maybe_print_address (pd, rs1, EXTRACT_ITYPE_IMM (l)); + case 'j': + if (((l & MASK_ADDI) == MATCH_ADDI && rs1 != 0) + || (l & MASK_JALR) == MATCH_JALR) + maybe_print_address (pd, rs1, EXTRACT_ITYPE_IMM (l)); + print (info->stream, "%d", (int)EXTRACT_ITYPE_IMM (l)); + break; + + case 'q': + maybe_print_address (pd, rs1, EXTRACT_STYPE_IMM (l)); + print (info->stream, "%d", (int)EXTRACT_STYPE_IMM (l)); + break; + + case 'a': + info->target = EXTRACT_UJTYPE_IMM (l) + pc; + (*info->print_address_func) (info->target, info); + break; + + case 'p': + info->target = EXTRACT_SBTYPE_IMM (l) + pc; + (*info->print_address_func) (info->target, info); + break; + + case 'd': + if ((l & MASK_AUIPC) == MATCH_AUIPC) + pd->hi_addr[rd] = pc + EXTRACT_UTYPE_IMM (l); + else if ((l & MASK_LUI) == MATCH_LUI) + pd->hi_addr[rd] = EXTRACT_UTYPE_IMM (l); + else if ((l & MASK_C_LUI) == MATCH_C_LUI) + pd->hi_addr[rd] = EXTRACT_RVC_LUI_IMM (l); + print (info->stream, "%s", riscv_gpr_names[rd]); + break; + + case 'z': + print (info->stream, "%s", riscv_gpr_names[0]); + break; + + case '>': + print (info->stream, "0x%x", (int)EXTRACT_OPERAND (SHAMT, l)); + break; + + case '<': + print (info->stream, "0x%x", (int)EXTRACT_OPERAND (SHAMTW, l)); + break; + + case 'S': + case 'U': + print (info->stream, "%s", riscv_fpr_names[rs1]); + break; + + case 'T': + print (info->stream, "%s", riscv_fpr_names[EXTRACT_OPERAND (RS2, l)]); + break; + + case 'D': + print (info->stream, "%s", riscv_fpr_names[rd]); + break; + + case 'R': + print (info->stream, "%s", riscv_fpr_names[EXTRACT_OPERAND (RS3, l)]); + break; + + case 'E': + { + const char* csr_name = NULL; + unsigned int csr = EXTRACT_OPERAND (CSR, l); + switch (csr) + { +#define DECLARE_CSR(name, num) case num: csr_name = #name; break; +#include "opcode/riscv-opc.h" +#undef DECLARE_CSR + } + if (csr_name) + print (info->stream, "%s", csr_name); + else + print (info->stream, "0x%x", csr); + break; + } + + case 'Z': + print (info->stream, "%d", rs1); + break; + + default: + /* xgettext:c-format */ + print (info->stream, _("# internal error, undefined modifier (%c)"), + *d); + return; + } + } +} + +/* Print the RISC-V instruction at address MEMADDR in debugged memory, + on using INFO. Returns length of the instruction, in bytes. + BIGENDIAN must be 1 if this is big-endian code, 0 if + this is little-endian code. */ + +static int +riscv_disassemble_insn (bfd_vma memaddr, insn_t word, disassemble_info *info) +{ + const struct riscv_opcode *op; + static bfd_boolean init = 0; + static const struct riscv_opcode *riscv_hash[OP_MASK_OP + 1]; + struct riscv_private_data *pd; + int insnlen; + +#define OP_HASH_IDX(i) ((i) & (riscv_insn_length (i) == 2 ? 0x3 : OP_MASK_OP)) + + /* Build a hash table to shorten the search time. */ + if (! init) + { + for (op = riscv_opcodes; op->name; op++) + if (!riscv_hash[OP_HASH_IDX (op->match)]) + riscv_hash[OP_HASH_IDX (op->match)] = op; + + init = 1; + } + + if (info->private_data == NULL) + { + int i; + + pd = info->private_data = xcalloc (1, sizeof (struct riscv_private_data)); + pd->gp = -1; + pd->print_addr = -1; + for (i = 0; i < (int)ARRAY_SIZE (pd->hi_addr); i++) + pd->hi_addr[i] = -1; + + for (i = 0; i < info->symtab_size; i++) + if (strcmp (bfd_asymbol_name (info->symtab[i]), "_gp") == 0) + pd->gp = bfd_asymbol_value (info->symtab[i]); + } + else + pd = info->private_data; + + insnlen = riscv_insn_length (word); + + info->bytes_per_chunk = insnlen % 4 == 0 ? 4 : 2; + info->bytes_per_line = 8; + info->display_endian = info->endian; + info->insn_info_valid = 1; + info->branch_delay_insns = 0; + info->data_size = 0; + info->insn_type = dis_nonbranch; + info->target = 0; + info->target2 = 0; + + op = riscv_hash[OP_HASH_IDX (word)]; + if (op != NULL) + { + int xlen = 0; + + /* The incoming section might not always be complete. */ + if (info->section != NULL) + { + Elf_Internal_Ehdr *ehdr = elf_elfheader (info->section->owner); + xlen = ehdr->e_ident[EI_CLASS] == ELFCLASS64 ? 64 : 32; + } + + for (; op->name; op++) + { + /* Does the opcode match? */ + if (! (op->match_func) (op, word)) + continue; + /* Is this a pseudo-instruction and may we print it as such? */ + if (no_aliases && (op->pinfo & INSN_ALIAS)) + continue; + /* Is this instruction restricted to a certain value of XLEN? */ + if (isdigit (op->subset[0]) && atoi (op->subset) != xlen) + continue; + + /* It's a match. */ + (*info->fprintf_func) (info->stream, "%s", op->name); + print_insn_args (op->args, word, memaddr, info); + + /* Try to disassemble multi-instruction addressing sequences. */ + if (pd->print_addr != (bfd_vma)-1) + { + info->target = pd->print_addr; + (*info->fprintf_func) (info->stream, " # "); + (*info->print_address_func) (info->target, info); + pd->print_addr = -1; + } + + return insnlen; + } + } + + /* We did not find a match, so just print the instruction bits. */ + info->insn_type = dis_noninsn; + (*info->fprintf_func) (info->stream, "0x%llx", (unsigned long long)word); + return insnlen; +} + +int +print_insn_riscv (bfd_vma memaddr, struct disassemble_info *info) +{ + bfd_byte packet[2]; + insn_t insn = 0; + bfd_vma n; + int status; + + if (info->disassembler_options != NULL) + { + parse_riscv_dis_options (info->disassembler_options); + /* Avoid repeatedly parsing the options. */ + info->disassembler_options = NULL; + } + else if (riscv_gpr_names == NULL) + set_default_riscv_dis_options (); + + /* Instructions are a sequence of 2-byte packets in little-endian order. */ + for (n = 0; n < sizeof (insn) && n < riscv_insn_length (insn); n += 2) + { + status = (*info->read_memory_func) (memaddr + n, packet, 2, info); + if (status != 0) + { + /* Don't fail just because we fell off the end. */ + if (n > 0) + break; + (*info->memory_error_func) (status, memaddr, info); + return status; + } + + insn |= ((insn_t) bfd_getl16 (packet)) << (8 * n); + } + + return riscv_disassemble_insn (memaddr, insn, info); +} + +void +print_riscv_disassembler_options (FILE *stream) +{ + fprintf (stream, _("\n\ +The following RISC-V-specific disassembler options are supported for use\n\ +with the -M switch (multiple options should be separated by commas):\n")); + + fprintf (stream, _("\n\ + numeric Print numeric reigster names, rather than ABI names.\n")); + + fprintf (stream, _("\n\ + no-aliases Disassemble only into canonical instructions, rather\n\ + than into pseudoinstructions.\n")); + + fprintf (stream, _("\n")); +} diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c new file mode 100644 index 0000000000..1d8d579b4f --- /dev/null +++ b/opcodes/riscv-opc.c @@ -0,0 +1,624 @@ +/* RISC-V opcode list + Copyright 2011-2016 Free Software Foundation, Inc. + + Contributed by Andrew Waterman (andrew@sifive.com). + Based on MIPS target. + + This file is part of the GNU opcodes library. + + This library is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. + + It is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + You should have received a copy of the GNU General Public License + along with this program; see the file COPYING3. If not, + see . */ + +#include "sysdep.h" +#include "opcode/riscv.h" +#include + +/* Register names used by gas and objdump. */ + +const char * const riscv_gpr_names_numeric[NGPR] = +{ + "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7", + "x8", "x9", "x10", "x11", "x12", "x13", "x14", "x15", + "x16", "x17", "x18", "x19", "x20", "x21", "x22", "x23", + "x24", "x25", "x26", "x27", "x28", "x29", "x30", "x31" +}; + +const char * const riscv_gpr_names_abi[NGPR] = +{ + "zero", "ra", "sp", "gp", "tp", "t0", "t1", "t2", + "s0", "s1", "a0", "a1", "a2", "a3", "a4", "a5", + "a6", "a7", "s2", "s3", "s4", "s5", "s6", "s7", + "s8", "s9", "s10", "s11", "t3", "t4", "t5", "t6" +}; + +const char * const riscv_fpr_names_numeric[NFPR] = +{ + "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", + "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", + "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", + "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31" +}; + +const char * const riscv_fpr_names_abi[NFPR] = +{ + "ft0", "ft1", "ft2", "ft3", "ft4", "ft5", "ft6", "ft7", + "fs0", "fs1", "fa0", "fa1", "fa2", "fa3", "fa4", "fa5", + "fa6", "fa7", "fs2", "fs3", "fs4", "fs5", "fs6", "fs7", + "fs8", "fs9", "fs10", "fs11", "ft8", "ft9", "ft10", "ft11" +}; + +/* The order of overloaded instructions matters. Label arguments and + register arguments look the same. Instructions that can have either + for arguments must apear in the correct order in this table for the + assembler to pick the right one. In other words, entries with + immediate operands must apear after the same instruction with + registers. + + Because of the lookup algorithm used, entries with the same opcode + name must be contiguous. */ + +#define MASK_RS1 (OP_MASK_RS1 << OP_SH_RS1) +#define MASK_RS2 (OP_MASK_RS2 << OP_SH_RS2) +#define MASK_RD (OP_MASK_RD << OP_SH_RD) +#define MASK_CRS2 (OP_MASK_CRS2 << OP_SH_CRS2) +#define MASK_IMM ENCODE_ITYPE_IMM(-1U) +#define MASK_RVC_IMM ENCODE_RVC_IMM(-1U) +#define MASK_UIMM ENCODE_UTYPE_IMM(-1U) +#define MASK_RM (OP_MASK_RM << OP_SH_RM) +#define MASK_PRED (OP_MASK_PRED << OP_SH_PRED) +#define MASK_SUCC (OP_MASK_SUCC << OP_SH_SUCC) +#define MASK_AQ (OP_MASK_AQ << OP_SH_AQ) +#define MASK_RL (OP_MASK_RL << OP_SH_RL) +#define MASK_AQRL (MASK_AQ | MASK_RL) + +static int +match_opcode (const struct riscv_opcode *op, insn_t insn) +{ + return ((insn ^ op->match) & op->mask) == 0; +} + +static int +match_never (const struct riscv_opcode *op ATTRIBUTE_UNUSED, + insn_t insn ATTRIBUTE_UNUSED) +{ + return 0; +} + +static int +match_rs1_eq_rs2 (const struct riscv_opcode *op, insn_t insn) +{ + int rs1 = (insn & MASK_RS1) >> OP_SH_RS1; + int rs2 = (insn & MASK_RS2) >> OP_SH_RS2; + return match_opcode (op, insn) && rs1 == rs2; +} + +static int +match_rd_nonzero (const struct riscv_opcode *op, insn_t insn) +{ + return match_opcode (op, insn) && ((insn & MASK_RD) != 0); +} + +static int +match_c_add (const struct riscv_opcode *op, insn_t insn) +{ + return match_rd_nonzero (op, insn) && ((insn & MASK_CRS2) != 0); +} + +static int +match_c_lui (const struct riscv_opcode *op, insn_t insn) +{ + return match_rd_nonzero (op, insn) && (((insn & MASK_RD) >> OP_SH_RD) != 2); +} + +const struct riscv_opcode riscv_opcodes[] = +{ +/* name, isa, operands, match, mask, match_func, pinfo. */ +{"unimp", "C", "", 0, 0xffffU, match_opcode, 0 }, +{"unimp", "I", "", MATCH_CSRRW | (CSR_CYCLE << OP_SH_CSR), 0xffffffffU, match_opcode, 0 }, /* csrw cycle, x0 */ +{"ebreak", "C", "", MATCH_C_EBREAK, MASK_C_EBREAK, match_opcode, INSN_ALIAS }, +{"ebreak", "I", "", MATCH_EBREAK, MASK_EBREAK, match_opcode, 0 }, +{"sbreak", "C", "", MATCH_C_EBREAK, MASK_C_EBREAK, match_opcode, INSN_ALIAS }, +{"sbreak", "I", "", MATCH_EBREAK, MASK_EBREAK, match_opcode, INSN_ALIAS }, +{"ret", "C", "", MATCH_C_JR | (X_RA << OP_SH_RD), MASK_C_JR | MASK_RD, match_opcode, INSN_ALIAS }, +{"ret", "I", "", MATCH_JALR | (X_RA << OP_SH_RS1), MASK_JALR | MASK_RD | MASK_RS1 | MASK_IMM, match_opcode, INSN_ALIAS }, +{"jr", "C", "d", MATCH_C_JR, MASK_C_JR, match_rd_nonzero, INSN_ALIAS }, +{"jr", "I", "s", MATCH_JALR, MASK_JALR | MASK_RD | MASK_IMM, match_opcode, INSN_ALIAS }, +{"jr", "I", "s,j", MATCH_JALR, MASK_JALR | MASK_RD, match_opcode, INSN_ALIAS }, +{"jalr", "C", "d", MATCH_C_JALR, MASK_C_JALR, match_rd_nonzero, INSN_ALIAS }, +{"jalr", "I", "s", MATCH_JALR | (X_RA << OP_SH_RD), MASK_JALR | MASK_RD | MASK_IMM, match_opcode, INSN_ALIAS }, +{"jalr", "I", "s,j", MATCH_JALR | (X_RA << OP_SH_RD), MASK_JALR | MASK_RD, match_opcode, INSN_ALIAS }, +{"jalr", "I", "d,s", MATCH_JALR, MASK_JALR | MASK_IMM, match_opcode, INSN_ALIAS }, +{"jalr", "I", "d,s,j", MATCH_JALR, MASK_JALR, match_opcode, 0 }, +{"j", "C", "Ca", MATCH_C_J, MASK_C_J, match_opcode, INSN_ALIAS }, +{"j", "I", "a", MATCH_JAL, MASK_JAL | MASK_RD, match_opcode, INSN_ALIAS }, +{"jal", "32C", "Ca", MATCH_C_JAL, MASK_C_JAL, match_opcode, INSN_ALIAS }, +{"jal", "I", "a", MATCH_JAL | (X_RA << OP_SH_RD), MASK_JAL | MASK_RD, match_opcode, INSN_ALIAS }, +{"jal", "I", "d,a", MATCH_JAL, MASK_JAL, match_opcode, 0 }, +{"call", "I", "c", (X_T1 << OP_SH_RS1) | (X_RA << OP_SH_RD), (int) M_CALL, match_never, INSN_MACRO }, +{"call", "I", "d,c", (X_T1 << OP_SH_RS1), (int) M_CALL, match_never, INSN_MACRO }, +{"tail", "I", "c", (X_T1 << OP_SH_RS1), (int) M_CALL, match_never, INSN_MACRO }, +{"jump", "I", "c,s", 0, (int) M_CALL, match_never, INSN_MACRO }, +{"nop", "C", "", MATCH_C_ADDI, 0xffff, match_opcode, INSN_ALIAS }, +{"nop", "I", "", MATCH_ADDI, MASK_ADDI | MASK_RD | MASK_RS1 | MASK_IMM, match_opcode, INSN_ALIAS }, +{"lui", "C", "d,Cu", MATCH_C_LUI, MASK_C_LUI, match_c_lui, INSN_ALIAS }, +{"lui", "I", "d,u", MATCH_LUI, MASK_LUI, match_opcode, 0 }, +{"li", "C", "d,Cv", MATCH_C_LUI, MASK_C_LUI, match_c_lui, INSN_ALIAS }, +{"li", "C", "d,Cj", MATCH_C_LI, MASK_C_LI, match_rd_nonzero, INSN_ALIAS }, +{"li", "C", "d,0", MATCH_C_LI, MASK_C_LI | MASK_RVC_IMM, match_rd_nonzero, INSN_ALIAS }, +{"li", "I", "d,j", MATCH_ADDI, MASK_ADDI | MASK_RS1, match_opcode, INSN_ALIAS }, /* addi */ +{"li", "I", "d,I", 0, (int) M_LI, match_never, INSN_MACRO }, +{"mv", "C", "d,CV", MATCH_C_MV, MASK_C_MV, match_c_add, INSN_ALIAS }, +{"mv", "I", "d,s", MATCH_ADDI, MASK_ADDI | MASK_IMM, match_opcode, INSN_ALIAS }, +{"move", "C", "d,CV", MATCH_C_MV, MASK_C_MV, match_c_add, INSN_ALIAS }, +{"move", "I", "d,s", MATCH_ADDI, MASK_ADDI | MASK_IMM, match_opcode, INSN_ALIAS }, +{"andi", "C", "Cs,Cw,Cj", MATCH_C_ANDI, MASK_C_ANDI, match_opcode, INSN_ALIAS }, +{"andi", "I", "d,s,j", MATCH_ANDI, MASK_ANDI, match_opcode, 0 }, +{"and", "C", "Cs,Cw,Ct", MATCH_C_AND, MASK_C_AND, match_opcode, INSN_ALIAS }, +{"and", "C", "Cs,Ct,Cw", MATCH_C_AND, MASK_C_AND, match_opcode, INSN_ALIAS }, +{"and", "C", "Cs,Cw,Cj", MATCH_C_ANDI, MASK_C_ANDI, match_opcode, INSN_ALIAS }, +{"and", "I", "d,s,t", MATCH_AND, MASK_AND, match_opcode, 0 }, +{"and", "I", "d,s,j", MATCH_ANDI, MASK_ANDI, match_opcode, INSN_ALIAS }, +{"beqz", "C", "Cs,Cp", MATCH_C_BEQZ, MASK_C_BEQZ, match_opcode, INSN_ALIAS }, +{"beqz", "I", "s,p", MATCH_BEQ, MASK_BEQ | MASK_RS2, match_opcode, INSN_ALIAS }, +{"beq", "I", "s,t,p", MATCH_BEQ, MASK_BEQ, match_opcode, 0 }, +{"blez", "I", "t,p", MATCH_BGE, MASK_BGE | MASK_RS1, match_opcode, INSN_ALIAS }, +{"bgez", "I", "s,p", MATCH_BGE, MASK_BGE | MASK_RS2, match_opcode, INSN_ALIAS }, +{"ble", "I", "t,s,p", MATCH_BGE, MASK_BGE, match_opcode, INSN_ALIAS }, +{"bleu", "I", "t,s,p", MATCH_BGEU, MASK_BGEU, match_opcode, INSN_ALIAS }, +{"bge", "I", "s,t,p", MATCH_BGE, MASK_BGE, match_opcode, 0 }, +{"bgeu", "I", "s,t,p", MATCH_BGEU, MASK_BGEU, match_opcode, 0 }, +{"bltz", "I", "s,p", MATCH_BLT, MASK_BLT | MASK_RS2, match_opcode, INSN_ALIAS }, +{"bgtz", "I", "t,p", MATCH_BLT, MASK_BLT | MASK_RS1, match_opcode, INSN_ALIAS }, +{"blt", "I", "s,t,p", MATCH_BLT, MASK_BLT, match_opcode, 0 }, +{"bltu", "I", "s,t,p", MATCH_BLTU, MASK_BLTU, match_opcode, 0 }, +{"bgt", "I", "t,s,p", MATCH_BLT, MASK_BLT, match_opcode, INSN_ALIAS }, +{"bgtu", "I", "t,s,p", MATCH_BLTU, MASK_BLTU, match_opcode, INSN_ALIAS }, +{"bnez", "C", "Cs,Cp", MATCH_C_BNEZ, MASK_C_BNEZ, match_opcode, INSN_ALIAS }, +{"bnez", "I", "s,p", MATCH_BNE, MASK_BNE | MASK_RS2, match_opcode, INSN_ALIAS }, +{"bne", "I", "s,t,p", MATCH_BNE, MASK_BNE, match_opcode, 0 }, +{"addi", "C", "Ct,Cc,CK", MATCH_C_ADDI4SPN, MASK_C_ADDI4SPN, match_opcode, INSN_ALIAS }, +{"addi", "C", "d,CU,Cj", MATCH_C_ADDI, MASK_C_ADDI, match_rd_nonzero, INSN_ALIAS }, +{"addi", "C", "Cc,Cc,CL", MATCH_C_ADDI16SP, MASK_C_ADDI16SP, match_opcode, INSN_ALIAS }, +{"addi", "I", "d,s,j", MATCH_ADDI, MASK_ADDI, match_opcode, 0 }, +{"add", "C", "d,CU,CV", MATCH_C_ADD, MASK_C_ADD, match_c_add, INSN_ALIAS }, +{"add", "C", "d,CV,CU", MATCH_C_ADD, MASK_C_ADD, match_c_add, INSN_ALIAS }, +{"add", "C", "d,CU,Cj", MATCH_C_ADDI, MASK_C_ADDI, match_rd_nonzero, INSN_ALIAS }, +{"add", "C", "Ct,Cc,CK", MATCH_C_ADDI4SPN, MASK_C_ADDI4SPN, match_opcode, INSN_ALIAS }, +{"add", "C", "Cc,Cc,CL", MATCH_C_ADDI16SP, MASK_C_ADDI16SP, match_opcode, INSN_ALIAS }, +{"add", "I", "d,s,t", MATCH_ADD, MASK_ADD, match_opcode, 0 }, +{"add", "I", "d,s,t,0",MATCH_ADD, MASK_ADD, match_opcode, 0 }, +{"add", "I", "d,s,j", MATCH_ADDI, MASK_ADDI, match_opcode, INSN_ALIAS }, +{"la", "I", "d,A", 0, (int) M_LA, match_never, INSN_MACRO }, +{"lla", "I", "d,A", 0, (int) M_LLA, match_never, INSN_MACRO }, +{"la.tls.gd", "I", "d,A", 0, (int) M_LA_TLS_GD, match_never, INSN_MACRO }, +{"la.tls.ie", "I", "d,A", 0, (int) M_LA_TLS_IE, match_never, INSN_MACRO }, +{"neg", "I", "d,t", MATCH_SUB, MASK_SUB | MASK_RS1, match_opcode, INSN_ALIAS }, /* sub 0 */ +{"slli", "C", "d,CU,C>", MATCH_C_SLLI, MASK_C_SLLI, match_rd_nonzero, INSN_ALIAS }, +{"slli", "I", "d,s,>", MATCH_SLLI, MASK_SLLI, match_opcode, 0 }, +{"sll", "C", "d,CU,C>", MATCH_C_SLLI, MASK_C_SLLI, match_rd_nonzero, INSN_ALIAS }, +{"sll", "I", "d,s,t", MATCH_SLL, MASK_SLL, match_opcode, 0 }, +{"sll", "I", "d,s,>", MATCH_SLLI, MASK_SLLI, match_opcode, INSN_ALIAS }, +{"srli", "C", "Cs,Cw,C>", MATCH_C_SRLI, MASK_C_SRLI, match_rd_nonzero, INSN_ALIAS }, +{"srli", "I", "d,s,>", MATCH_SRLI, MASK_SRLI, match_opcode, 0 }, +{"srl", "C", "Cs,Cw,C>", MATCH_C_SRLI, MASK_C_SRLI, match_rd_nonzero, INSN_ALIAS }, +{"srl", "I", "d,s,t", MATCH_SRL, MASK_SRL, match_opcode, 0 }, +{"srl", "I", "d,s,>", MATCH_SRLI, MASK_SRLI, match_opcode, INSN_ALIAS }, +{"srai", "C", "Cs,Cw,C>", MATCH_C_SRAI, MASK_C_SRAI, match_rd_nonzero, INSN_ALIAS }, +{"srai", "I", "d,s,>", MATCH_SRAI, MASK_SRAI, match_opcode, 0 }, +{"sra", "C", "Cs,Cw,C>", MATCH_C_SRAI, MASK_C_SRAI, match_rd_nonzero, INSN_ALIAS }, +{"sra", "I", "d,s,t", MATCH_SRA, MASK_SRA, match_opcode, 0 }, +{"sra", "I", "d,s,>", MATCH_SRAI, MASK_SRAI, match_opcode, INSN_ALIAS }, +{"sub", "C", "Cs,Cw,Ct", MATCH_C_SUB, MASK_C_SUB, match_opcode, INSN_ALIAS }, +{"sub", "I", "d,s,t", MATCH_SUB, MASK_SUB, match_opcode, 0 }, +{"lb", "I", "d,o(s)", MATCH_LB, MASK_LB, match_opcode, 0 }, +{"lb", "I", "d,A", 0, (int) M_LB, match_never, INSN_MACRO }, +{"lbu", "I", "d,o(s)", MATCH_LBU, MASK_LBU, match_opcode, 0 }, +{"lbu", "I", "d,A", 0, (int) M_LBU, match_never, INSN_MACRO }, +{"lh", "I", "d,o(s)", MATCH_LH, MASK_LH, match_opcode, 0 }, +{"lh", "I", "d,A", 0, (int) M_LH, match_never, INSN_MACRO }, +{"lhu", "I", "d,o(s)", MATCH_LHU, MASK_LHU, match_opcode, 0 }, +{"lhu", "I", "d,A", 0, (int) M_LHU, match_never, INSN_MACRO }, +{"lw", "C", "d,Cm(Cc)", MATCH_C_LWSP, MASK_C_LWSP, match_rd_nonzero, INSN_ALIAS }, +{"lw", "C", "Ct,Ck(Cs)", MATCH_C_LW, MASK_C_LW, match_opcode, INSN_ALIAS }, +{"lw", "I", "d,o(s)", MATCH_LW, MASK_LW, match_opcode, 0 }, +{"lw", "I", "d,A", 0, (int) M_LW, match_never, INSN_MACRO }, +{"not", "I", "d,s", MATCH_XORI | MASK_IMM, MASK_XORI | MASK_IMM, match_opcode, INSN_ALIAS }, +{"ori", "I", "d,s,j", MATCH_ORI, MASK_ORI, match_opcode, 0 }, +{"or", "C", "Cs,Cw,Ct", MATCH_C_OR, MASK_C_OR, match_opcode, INSN_ALIAS }, +{"or", "C", "Cs,Ct,Cw", MATCH_C_OR, MASK_C_OR, match_opcode, INSN_ALIAS }, +{"or", "I", "d,s,t", MATCH_OR, MASK_OR, match_opcode, 0 }, +{"or", "I", "d,s,j", MATCH_ORI, MASK_ORI, match_opcode, INSN_ALIAS }, +{"auipc", "I", "d,u", MATCH_AUIPC, MASK_AUIPC, match_opcode, 0 }, +{"seqz", "I", "d,s", MATCH_SLTIU | ENCODE_ITYPE_IMM(1), MASK_SLTIU | MASK_IMM, match_opcode, INSN_ALIAS }, +{"snez", "I", "d,t", MATCH_SLTU, MASK_SLTU | MASK_RS1, match_opcode, INSN_ALIAS }, +{"sltz", "I", "d,s", MATCH_SLT, MASK_SLT | MASK_RS2, match_opcode, INSN_ALIAS }, +{"sgtz", "I", "d,t", MATCH_SLT, MASK_SLT | MASK_RS1, match_opcode, INSN_ALIAS }, +{"slti", "I", "d,s,j", MATCH_SLTI, MASK_SLTI, match_opcode, INSN_ALIAS }, +{"slt", "I", "d,s,t", MATCH_SLT, MASK_SLT, match_opcode, 0 }, +{"slt", "I", "d,s,j", MATCH_SLTI, MASK_SLTI, match_opcode, 0 }, +{"sltiu", "I", "d,s,j", MATCH_SLTIU, MASK_SLTIU, match_opcode, 0 }, +{"sltu", "I", "d,s,t", MATCH_SLTU, MASK_SLTU, match_opcode, 0 }, +{"sltu", "I", "d,s,j", MATCH_SLTIU, MASK_SLTIU, match_opcode, INSN_ALIAS }, +{"sgt", "I", "d,t,s", MATCH_SLT, MASK_SLT, match_opcode, INSN_ALIAS }, +{"sgtu", "I", "d,t,s", MATCH_SLTU, MASK_SLTU, match_opcode, INSN_ALIAS }, +{"sb", "I", "t,q(s)", MATCH_SB, MASK_SB, match_opcode, 0 }, +{"sb", "I", "t,A,s", 0, (int) M_SB, match_never, INSN_MACRO }, +{"sh", "I", "t,q(s)", MATCH_SH, MASK_SH, match_opcode, 0 }, +{"sh", "I", "t,A,s", 0, (int) M_SH, match_never, INSN_MACRO }, +{"sw", "C", "CV,CM(Cc)", MATCH_C_SWSP, MASK_C_SWSP, match_opcode, INSN_ALIAS }, +{"sw", "C", "Ct,Ck(Cs)", MATCH_C_SW, MASK_C_SW, match_opcode, INSN_ALIAS }, +{"sw", "I", "t,q(s)", MATCH_SW, MASK_SW, match_opcode, 0 }, +{"sw", "I", "t,A,s", 0, (int) M_SW, match_never, INSN_MACRO }, +{"fence", "I", "", MATCH_FENCE | MASK_PRED | MASK_SUCC, MASK_FENCE | MASK_RD | MASK_RS1 | MASK_IMM, match_opcode, INSN_ALIAS }, +{"fence", "I", "P,Q", MATCH_FENCE, MASK_FENCE | MASK_RD | MASK_RS1 | (MASK_IMM & ~MASK_PRED & ~MASK_SUCC), match_opcode, 0 }, +{"fence.i", "I", "", MATCH_FENCE_I, MASK_FENCE | MASK_RD | MASK_RS1 | MASK_IMM, match_opcode, 0 }, +{"rdcycle", "I", "d", MATCH_RDCYCLE, MASK_RDCYCLE, match_opcode, 0 }, +{"rdinstret", "I", "d", MATCH_RDINSTRET, MASK_RDINSTRET, match_opcode, 0 }, +{"rdtime", "I", "d", MATCH_RDTIME, MASK_RDTIME, match_opcode, 0 }, +{"rdcycleh", "32I", "d", MATCH_RDCYCLEH, MASK_RDCYCLEH, match_opcode, 0 }, +{"rdinstreth","32I", "d", MATCH_RDINSTRETH, MASK_RDINSTRETH, match_opcode, 0 }, +{"rdtimeh", "32I", "d", MATCH_RDTIMEH, MASK_RDTIMEH, match_opcode, 0 }, +{"ecall", "I", "", MATCH_SCALL, MASK_SCALL, match_opcode, 0 }, +{"scall", "I", "", MATCH_SCALL, MASK_SCALL, match_opcode, 0 }, +{"xori", "I", "d,s,j", MATCH_XORI, MASK_XORI, match_opcode, 0 }, +{"xor", "C", "Cs,Cw,Ct", MATCH_C_XOR, MASK_C_XOR, match_opcode, INSN_ALIAS }, +{"xor", "C", "Cs,Ct,Cw", MATCH_C_XOR, MASK_C_XOR, match_opcode, INSN_ALIAS }, +{"xor", "I", "d,s,t", MATCH_XOR, MASK_XOR, match_opcode, 0 }, +{"xor", "I", "d,s,j", MATCH_XORI, MASK_XORI, match_opcode, INSN_ALIAS }, +{"lwu", "64I", "d,o(s)", MATCH_LWU, MASK_LWU, match_opcode, 0 }, +{"lwu", "64I", "d,A", 0, (int) M_LWU, match_never, INSN_MACRO }, +{"ld", "64C", "d,Cn(Cc)", MATCH_C_LDSP, MASK_C_LDSP, match_rd_nonzero, INSN_ALIAS }, +{"ld", "64C", "Ct,Cl(Cs)", MATCH_C_LD, MASK_C_LD, match_opcode, INSN_ALIAS }, +{"ld", "64I", "d,o(s)", MATCH_LD, MASK_LD, match_opcode, 0 }, +{"ld", "64I", "d,A", 0, (int) M_LD, match_never, INSN_MACRO }, +{"sd", "64C", "CV,CN(Cc)", MATCH_C_SDSP, MASK_C_SDSP, match_opcode, INSN_ALIAS }, +{"sd", "64C", "Ct,Cl(Cs)", MATCH_C_SD, MASK_C_SD, match_opcode, INSN_ALIAS }, +{"sd", "64I", "t,q(s)", MATCH_SD, MASK_SD, match_opcode, 0 }, +{"sd", "64I", "t,A,s", 0, (int) M_SD, match_never, INSN_MACRO }, +{"sext.w", "64C", "d,CU", MATCH_C_ADDIW, MASK_C_ADDIW | MASK_RVC_IMM, match_rd_nonzero, INSN_ALIAS }, +{"sext.w", "64I", "d,s", MATCH_ADDIW, MASK_ADDIW | MASK_IMM, match_opcode, INSN_ALIAS }, +{"addiw", "64C", "d,CU,Cj", MATCH_C_ADDIW, MASK_C_ADDIW, match_rd_nonzero, INSN_ALIAS }, +{"addiw", "64I", "d,s,j", MATCH_ADDIW, MASK_ADDIW, match_opcode, 0 }, +{"addw", "64C", "Cs,Cw,Ct", MATCH_C_ADDW, MASK_C_ADDW, match_opcode, INSN_ALIAS }, +{"addw", "64C", "Cs,Ct,Cw", MATCH_C_ADDW, MASK_C_ADDW, match_opcode, INSN_ALIAS }, +{"addw", "64C", "d,CU,Cj", MATCH_C_ADDIW, MASK_C_ADDIW, match_rd_nonzero, INSN_ALIAS }, +{"addw", "64I", "d,s,t", MATCH_ADDW, MASK_ADDW, match_opcode, 0 }, +{"addw", "64I", "d,s,j", MATCH_ADDIW, MASK_ADDIW, match_opcode, INSN_ALIAS }, +{"negw", "64I", "d,t", MATCH_SUBW, MASK_SUBW | MASK_RS1, match_opcode, INSN_ALIAS }, /* sub 0 */ +{"slliw", "64I", "d,s,<", MATCH_SLLIW, MASK_SLLIW, match_opcode, 0 }, +{"sllw", "64I", "d,s,t", MATCH_SLLW, MASK_SLLW, match_opcode, 0 }, +{"sllw", "64I", "d,s,<", MATCH_SLLIW, MASK_SLLIW, match_opcode, INSN_ALIAS }, +{"srliw", "64I", "d,s,<", MATCH_SRLIW, MASK_SRLIW, match_opcode, 0 }, +{"srlw", "64I", "d,s,t", MATCH_SRLW, MASK_SRLW, match_opcode, 0 }, +{"srlw", "64I", "d,s,<", MATCH_SRLIW, MASK_SRLIW, match_opcode, INSN_ALIAS }, +{"sraiw", "64I", "d,s,<", MATCH_SRAIW, MASK_SRAIW, match_opcode, 0 }, +{"sraw", "64I", "d,s,t", MATCH_SRAW, MASK_SRAW, match_opcode, 0 }, +{"sraw", "64I", "d,s,<", MATCH_SRAIW, MASK_SRAIW, match_opcode, INSN_ALIAS }, +{"subw", "64C", "Cs,Cw,Ct", MATCH_C_SUBW, MASK_C_SUBW, match_opcode, INSN_ALIAS }, +{"subw", "64I", "d,s,t", MATCH_SUBW, MASK_SUBW, match_opcode, 0 }, + +/* Atomic memory operation instruction subset */ +{"lr.w", "A", "d,0(s)", MATCH_LR_W, MASK_LR_W | MASK_AQRL, match_opcode, 0 }, +{"sc.w", "A", "d,t,0(s)", MATCH_SC_W, MASK_SC_W | MASK_AQRL, match_opcode, 0 }, +{"amoadd.w", "A", "d,t,0(s)", MATCH_AMOADD_W, MASK_AMOADD_W | MASK_AQRL, match_opcode, 0 }, +{"amoswap.w", "A", "d,t,0(s)", MATCH_AMOSWAP_W, MASK_AMOSWAP_W | MASK_AQRL, match_opcode, 0 }, +{"amoand.w", "A", "d,t,0(s)", MATCH_AMOAND_W, MASK_AMOAND_W | MASK_AQRL, match_opcode, 0 }, +{"amoor.w", "A", "d,t,0(s)", MATCH_AMOOR_W, MASK_AMOOR_W | MASK_AQRL, match_opcode, 0 }, +{"amoxor.w", "A", "d,t,0(s)", MATCH_AMOXOR_W, MASK_AMOXOR_W | MASK_AQRL, match_opcode, 0 }, +{"amomax.w", "A", "d,t,0(s)", MATCH_AMOMAX_W, MASK_AMOMAX_W | MASK_AQRL, match_opcode, 0 }, +{"amomaxu.w", "A", "d,t,0(s)", MATCH_AMOMAXU_W, MASK_AMOMAXU_W | MASK_AQRL, match_opcode, 0 }, +{"amomin.w", "A", "d,t,0(s)", MATCH_AMOMIN_W, MASK_AMOMIN_W | MASK_AQRL, match_opcode, 0 }, +{"amominu.w", "A", "d,t,0(s)", MATCH_AMOMINU_W, MASK_AMOMINU_W | MASK_AQRL, match_opcode, 0 }, +{"lr.w.aq", "A", "d,0(s)", MATCH_LR_W | MASK_AQ, MASK_LR_W | MASK_AQRL, match_opcode, 0 }, +{"sc.w.aq", "A", "d,t,0(s)", MATCH_SC_W | MASK_AQ, MASK_SC_W | MASK_AQRL, match_opcode, 0 }, +{"amoadd.w.aq", "A", "d,t,0(s)", MATCH_AMOADD_W | MASK_AQ, MASK_AMOADD_W | MASK_AQRL, match_opcode, 0 }, +{"amoswap.w.aq", "A", "d,t,0(s)", MATCH_AMOSWAP_W | MASK_AQ, MASK_AMOSWAP_W | MASK_AQRL, match_opcode, 0 }, +{"amoand.w.aq", "A", "d,t,0(s)", MATCH_AMOAND_W | MASK_AQ, MASK_AMOAND_W | MASK_AQRL, match_opcode, 0 }, +{"amoor.w.aq", "A", "d,t,0(s)", MATCH_AMOOR_W | MASK_AQ, MASK_AMOOR_W | MASK_AQRL, match_opcode, 0 }, +{"amoxor.w.aq", "A", "d,t,0(s)", MATCH_AMOXOR_W | MASK_AQ, MASK_AMOXOR_W | MASK_AQRL, match_opcode, 0 }, +{"amomax.w.aq", "A", "d,t,0(s)", MATCH_AMOMAX_W | MASK_AQ, MASK_AMOMAX_W | MASK_AQRL, match_opcode, 0 }, +{"amomaxu.w.aq", "A", "d,t,0(s)", MATCH_AMOMAXU_W | MASK_AQ, MASK_AMOMAXU_W | MASK_AQRL, match_opcode, 0 }, +{"amomin.w.aq", "A", "d,t,0(s)", MATCH_AMOMIN_W | MASK_AQ, MASK_AMOMIN_W | MASK_AQRL, match_opcode, 0 }, +{"amominu.w.aq", "A", "d,t,0(s)", MATCH_AMOMINU_W | MASK_AQ, MASK_AMOMINU_W | MASK_AQRL, match_opcode, 0 }, +{"lr.w.rl", "A", "d,0(s)", MATCH_LR_W | MASK_RL, MASK_LR_W | MASK_AQRL, match_opcode, 0 }, +{"sc.w.rl", "A", "d,t,0(s)", MATCH_SC_W | MASK_RL, MASK_SC_W | MASK_AQRL, match_opcode, 0 }, +{"amoadd.w.rl", "A", "d,t,0(s)", MATCH_AMOADD_W | MASK_RL, MASK_AMOADD_W | MASK_AQRL, match_opcode, 0 }, +{"amoswap.w.rl", "A", "d,t,0(s)", MATCH_AMOSWAP_W | MASK_RL, MASK_AMOSWAP_W | MASK_AQRL, match_opcode, 0 }, +{"amoand.w.rl", "A", "d,t,0(s)", MATCH_AMOAND_W | MASK_RL, MASK_AMOAND_W | MASK_AQRL, match_opcode, 0 }, +{"amoor.w.rl", "A", "d,t,0(s)", MATCH_AMOOR_W | MASK_RL, MASK_AMOOR_W | MASK_AQRL, match_opcode, 0 }, +{"amoxor.w.rl", "A", "d,t,0(s)", MATCH_AMOXOR_W | MASK_RL, MASK_AMOXOR_W | MASK_AQRL, match_opcode, 0 }, +{"amomax.w.rl", "A", "d,t,0(s)", MATCH_AMOMAX_W | MASK_RL, MASK_AMOMAX_W | MASK_AQRL, match_opcode, 0 }, +{"amomaxu.w.rl", "A", "d,t,0(s)", MATCH_AMOMAXU_W | MASK_RL, MASK_AMOMAXU_W | MASK_AQRL, match_opcode, 0 }, +{"amomin.w.rl", "A", "d,t,0(s)", MATCH_AMOMIN_W | MASK_RL, MASK_AMOMIN_W | MASK_AQRL, match_opcode, 0 }, +{"amominu.w.rl", "A", "d,t,0(s)", MATCH_AMOMINU_W | MASK_RL, MASK_AMOMINU_W | MASK_AQRL, match_opcode, 0 }, +{"lr.w.sc", "A", "d,0(s)", MATCH_LR_W | MASK_AQRL, MASK_LR_W | MASK_AQRL, match_opcode, 0 }, +{"sc.w.sc", "A", "d,t,0(s)", MATCH_SC_W | MASK_AQRL, MASK_SC_W | MASK_AQRL, match_opcode, 0 }, +{"amoadd.w.sc", "A", "d,t,0(s)", MATCH_AMOADD_W | MASK_AQRL, MASK_AMOADD_W | MASK_AQRL, match_opcode, 0 }, +{"amoswap.w.sc", "A", "d,t,0(s)", MATCH_AMOSWAP_W | MASK_AQRL, MASK_AMOSWAP_W | MASK_AQRL, match_opcode, 0 }, +{"amoand.w.sc", "A", "d,t,0(s)", MATCH_AMOAND_W | MASK_AQRL, MASK_AMOAND_W | MASK_AQRL, match_opcode, 0 }, +{"amoor.w.sc", "A", "d,t,0(s)", MATCH_AMOOR_W | MASK_AQRL, MASK_AMOOR_W | MASK_AQRL, match_opcode, 0 }, +{"amoxor.w.sc", "A", "d,t,0(s)", MATCH_AMOXOR_W | MASK_AQRL, MASK_AMOXOR_W | MASK_AQRL, match_opcode, 0 }, +{"amomax.w.sc", "A", "d,t,0(s)", MATCH_AMOMAX_W | MASK_AQRL, MASK_AMOMAX_W | MASK_AQRL, match_opcode, 0 }, +{"amomaxu.w.sc", "A", "d,t,0(s)", MATCH_AMOMAXU_W | MASK_AQRL, MASK_AMOMAXU_W | MASK_AQRL, match_opcode, 0 }, +{"amomin.w.sc", "A", "d,t,0(s)", MATCH_AMOMIN_W | MASK_AQRL, MASK_AMOMIN_W | MASK_AQRL, match_opcode, 0 }, +{"amominu.w.sc", "A", "d,t,0(s)", MATCH_AMOMINU_W | MASK_AQRL, MASK_AMOMINU_W | MASK_AQRL, match_opcode, 0 }, +{"lr.d", "64A", "d,0(s)", MATCH_LR_D, MASK_LR_D | MASK_AQRL, match_opcode, 0 }, +{"sc.d", "64A", "d,t,0(s)", MATCH_SC_D, MASK_SC_D | MASK_AQRL, match_opcode, 0 }, +{"amoadd.d", "64A", "d,t,0(s)", MATCH_AMOADD_D, MASK_AMOADD_D | MASK_AQRL, match_opcode, 0 }, +{"amoswap.d", "64A", "d,t,0(s)", MATCH_AMOSWAP_D, MASK_AMOSWAP_D | MASK_AQRL, match_opcode, 0 }, +{"amoand.d", "64A", "d,t,0(s)", MATCH_AMOAND_D, MASK_AMOAND_D | MASK_AQRL, match_opcode, 0 }, +{"amoor.d", "64A", "d,t,0(s)", MATCH_AMOOR_D, MASK_AMOOR_D | MASK_AQRL, match_opcode, 0 }, +{"amoxor.d", "64A", "d,t,0(s)", MATCH_AMOXOR_D, MASK_AMOXOR_D | MASK_AQRL, match_opcode, 0 }, +{"amomax.d", "64A", "d,t,0(s)", MATCH_AMOMAX_D, MASK_AMOMAX_D | MASK_AQRL, match_opcode, 0 }, +{"amomaxu.d", "64A", "d,t,0(s)", MATCH_AMOMAXU_D, MASK_AMOMAXU_D | MASK_AQRL, match_opcode, 0 }, +{"amomin.d", "64A", "d,t,0(s)", MATCH_AMOMIN_D, MASK_AMOMIN_D | MASK_AQRL, match_opcode, 0 }, +{"amominu.d", "64A", "d,t,0(s)", MATCH_AMOMINU_D, MASK_AMOMINU_D | MASK_AQRL, match_opcode, 0 }, +{"lr.d.aq", "64A", "d,0(s)", MATCH_LR_D | MASK_AQ, MASK_LR_D | MASK_AQRL, match_opcode, 0 }, +{"sc.d.aq", "64A", "d,t,0(s)", MATCH_SC_D | MASK_AQ, MASK_SC_D | MASK_AQRL, match_opcode, 0 }, +{"amoadd.d.aq", "64A", "d,t,0(s)", MATCH_AMOADD_D | MASK_AQ, MASK_AMOADD_D | MASK_AQRL, match_opcode, 0 }, +{"amoswap.d.aq", "64A", "d,t,0(s)", MATCH_AMOSWAP_D | MASK_AQ, MASK_AMOSWAP_D | MASK_AQRL, match_opcode, 0 }, +{"amoand.d.aq", "64A", "d,t,0(s)", MATCH_AMOAND_D | MASK_AQ, MASK_AMOAND_D | MASK_AQRL, match_opcode, 0 }, +{"amoor.d.aq", "64A", "d,t,0(s)", MATCH_AMOOR_D | MASK_AQ, MASK_AMOOR_D | MASK_AQRL, match_opcode, 0 }, +{"amoxor.d.aq", "64A", "d,t,0(s)", MATCH_AMOXOR_D | MASK_AQ, MASK_AMOXOR_D | MASK_AQRL, match_opcode, 0 }, +{"amomax.d.aq", "64A", "d,t,0(s)", MATCH_AMOMAX_D | MASK_AQ, MASK_AMOMAX_D | MASK_AQRL, match_opcode, 0 }, +{"amomaxu.d.aq", "64A", "d,t,0(s)", MATCH_AMOMAXU_D | MASK_AQ, MASK_AMOMAXU_D | MASK_AQRL, match_opcode, 0 }, +{"amomin.d.aq", "64A", "d,t,0(s)", MATCH_AMOMIN_D | MASK_AQ, MASK_AMOMIN_D | MASK_AQRL, match_opcode, 0 }, +{"amominu.d.aq", "64A", "d,t,0(s)", MATCH_AMOMINU_D | MASK_AQ, MASK_AMOMINU_D | MASK_AQRL, match_opcode, 0 }, +{"lr.d.rl", "64A", "d,0(s)", MATCH_LR_D | MASK_RL, MASK_LR_D | MASK_AQRL, match_opcode, 0 }, +{"sc.d.rl", "64A", "d,t,0(s)", MATCH_SC_D | MASK_RL, MASK_SC_D | MASK_AQRL, match_opcode, 0 }, +{"amoadd.d.rl", "64A", "d,t,0(s)", MATCH_AMOADD_D | MASK_RL, MASK_AMOADD_D | MASK_AQRL, match_opcode, 0 }, +{"amoswap.d.rl", "64A", "d,t,0(s)", MATCH_AMOSWAP_D | MASK_RL, MASK_AMOSWAP_D | MASK_AQRL, match_opcode, 0 }, +{"amoand.d.rl", "64A", "d,t,0(s)", MATCH_AMOAND_D | MASK_RL, MASK_AMOAND_D | MASK_AQRL, match_opcode, 0 }, +{"amoor.d.rl", "64A", "d,t,0(s)", MATCH_AMOOR_D | MASK_RL, MASK_AMOOR_D | MASK_AQRL, match_opcode, 0 }, +{"amoxor.d.rl", "64A", "d,t,0(s)", MATCH_AMOXOR_D | MASK_RL, MASK_AMOXOR_D | MASK_AQRL, match_opcode, 0 }, +{"amomax.d.rl", "64A", "d,t,0(s)", MATCH_AMOMAX_D | MASK_RL, MASK_AMOMAX_D | MASK_AQRL, match_opcode, 0 }, +{"amomaxu.d.rl", "64A", "d,t,0(s)", MATCH_AMOMAXU_D | MASK_RL, MASK_AMOMAXU_D | MASK_AQRL, match_opcode, 0 }, +{"amomin.d.rl", "64A", "d,t,0(s)", MATCH_AMOMIN_D | MASK_RL, MASK_AMOMIN_D | MASK_AQRL, match_opcode, 0 }, +{"amominu.d.rl", "64A", "d,t,0(s)", MATCH_AMOMINU_D | MASK_RL, MASK_AMOMINU_D | MASK_AQRL, match_opcode, 0 }, +{"lr.d.sc", "64A", "d,0(s)", MATCH_LR_D | MASK_AQRL, MASK_LR_D | MASK_AQRL, match_opcode, 0 }, +{"sc.d.sc", "64A", "d,t,0(s)", MATCH_SC_D | MASK_AQRL, MASK_SC_D | MASK_AQRL, match_opcode, 0 }, +{"amoadd.d.sc", "64A", "d,t,0(s)", MATCH_AMOADD_D | MASK_AQRL, MASK_AMOADD_D | MASK_AQRL, match_opcode, 0 }, +{"amoswap.d.sc", "64A", "d,t,0(s)", MATCH_AMOSWAP_D | MASK_AQRL, MASK_AMOSWAP_D | MASK_AQRL, match_opcode, 0 }, +{"amoand.d.sc", "64A", "d,t,0(s)", MATCH_AMOAND_D | MASK_AQRL, MASK_AMOAND_D | MASK_AQRL, match_opcode, 0 }, +{"amoor.d.sc", "64A", "d,t,0(s)", MATCH_AMOOR_D | MASK_AQRL, MASK_AMOOR_D | MASK_AQRL, match_opcode, 0 }, +{"amoxor.d.sc", "64A", "d,t,0(s)", MATCH_AMOXOR_D | MASK_AQRL, MASK_AMOXOR_D | MASK_AQRL, match_opcode, 0 }, +{"amomax.d.sc", "64A", "d,t,0(s)", MATCH_AMOMAX_D | MASK_AQRL, MASK_AMOMAX_D | MASK_AQRL, match_opcode, 0 }, +{"amomaxu.d.sc", "64A", "d,t,0(s)", MATCH_AMOMAXU_D | MASK_AQRL, MASK_AMOMAXU_D | MASK_AQRL, match_opcode, 0 }, +{"amomin.d.sc", "64A", "d,t,0(s)", MATCH_AMOMIN_D | MASK_AQRL, MASK_AMOMIN_D | MASK_AQRL, match_opcode, 0 }, +{"amominu.d.sc", "64A", "d,t,0(s)", MATCH_AMOMINU_D | MASK_AQRL, MASK_AMOMINU_D | MASK_AQRL, match_opcode, 0 }, + +/* Multiply/Divide instruction subset */ +{"mul", "M", "d,s,t", MATCH_MUL, MASK_MUL, match_opcode, 0 }, +{"mulh", "M", "d,s,t", MATCH_MULH, MASK_MULH, match_opcode, 0 }, +{"mulhu", "M", "d,s,t", MATCH_MULHU, MASK_MULHU, match_opcode, 0 }, +{"mulhsu", "M", "d,s,t", MATCH_MULHSU, MASK_MULHSU, match_opcode, 0 }, +{"div", "M", "d,s,t", MATCH_DIV, MASK_DIV, match_opcode, 0 }, +{"divu", "M", "d,s,t", MATCH_DIVU, MASK_DIVU, match_opcode, 0 }, +{"rem", "M", "d,s,t", MATCH_REM, MASK_REM, match_opcode, 0 }, +{"remu", "M", "d,s,t", MATCH_REMU, MASK_REMU, match_opcode, 0 }, +{"mulw", "64M", "d,s,t", MATCH_MULW, MASK_MULW, match_opcode, 0 }, +{"divw", "64M", "d,s,t", MATCH_DIVW, MASK_DIVW, match_opcode, 0 }, +{"divuw", "64M", "d,s,t", MATCH_DIVUW, MASK_DIVUW, match_opcode, 0 }, +{"remw", "64M", "d,s,t", MATCH_REMW, MASK_REMW, match_opcode, 0 }, +{"remuw", "64M", "d,s,t", MATCH_REMUW, MASK_REMUW, match_opcode, 0 }, + +/* Single-precision floating-point instruction subset */ +{"frsr", "F", "d", MATCH_FRCSR, MASK_FRCSR, match_opcode, 0 }, +{"fssr", "F", "s", MATCH_FSCSR, MASK_FSCSR | MASK_RD, match_opcode, 0 }, +{"fssr", "F", "d,s", MATCH_FSCSR, MASK_FSCSR, match_opcode, 0 }, +{"frcsr", "F", "d", MATCH_FRCSR, MASK_FRCSR, match_opcode, 0 }, +{"fscsr", "F", "s", MATCH_FSCSR, MASK_FSCSR | MASK_RD, match_opcode, 0 }, +{"fscsr", "F", "d,s", MATCH_FSCSR, MASK_FSCSR, match_opcode, 0 }, +{"frrm", "F", "d", MATCH_FRRM, MASK_FRRM, match_opcode, 0 }, +{"fsrm", "F", "s", MATCH_FSRM, MASK_FSRM | MASK_RD, match_opcode, 0 }, +{"fsrm", "F", "d,s", MATCH_FSRM, MASK_FSRM, match_opcode, 0 }, +{"frflags", "F", "d", MATCH_FRFLAGS, MASK_FRFLAGS, match_opcode, 0 }, +{"fsflags", "F", "s", MATCH_FSFLAGS, MASK_FSFLAGS | MASK_RD, match_opcode, 0 }, +{"fsflags", "F", "d,s", MATCH_FSFLAGS, MASK_FSFLAGS, match_opcode, 0 }, +{"flw", "32C", "D,Cm(Cc)", MATCH_C_FLWSP, MASK_C_FLWSP, match_opcode, INSN_ALIAS }, +{"flw", "32C", "CD,Ck(Cs)", MATCH_C_FLW, MASK_C_FLW, match_opcode, INSN_ALIAS }, +{"flw", "F", "D,o(s)", MATCH_FLW, MASK_FLW, match_opcode, 0 }, +{"flw", "F", "D,A,s", 0, (int) M_FLW, match_never, INSN_MACRO }, +{"fsw", "32C", "CT,CM(Cc)", MATCH_C_FSWSP, MASK_C_FSWSP, match_opcode, INSN_ALIAS }, +{"fsw", "32C", "CD,Ck(Cs)", MATCH_C_FSW, MASK_C_FSW, match_opcode, INSN_ALIAS }, +{"fsw", "F", "T,q(s)", MATCH_FSW, MASK_FSW, match_opcode, 0 }, +{"fsw", "F", "T,A,s", 0, (int) M_FSW, match_never, INSN_MACRO }, +{"fmv.x.s", "F", "d,S", MATCH_FMV_X_S, MASK_FMV_X_S, match_opcode, 0 }, +{"fmv.s.x", "F", "D,s", MATCH_FMV_S_X, MASK_FMV_S_X, match_opcode, 0 }, +{"fmv.s", "F", "D,U", MATCH_FSGNJ_S, MASK_FSGNJ_S, match_rs1_eq_rs2, INSN_ALIAS }, +{"fneg.s", "F", "D,U", MATCH_FSGNJN_S, MASK_FSGNJN_S, match_rs1_eq_rs2, INSN_ALIAS }, +{"fabs.s", "F", "D,U", MATCH_FSGNJX_S, MASK_FSGNJX_S, match_rs1_eq_rs2, INSN_ALIAS }, +{"fsgnj.s", "F", "D,S,T", MATCH_FSGNJ_S, MASK_FSGNJ_S, match_opcode, 0 }, +{"fsgnjn.s", "F", "D,S,T", MATCH_FSGNJN_S, MASK_FSGNJN_S, match_opcode, 0 }, +{"fsgnjx.s", "F", "D,S,T", MATCH_FSGNJX_S, MASK_FSGNJX_S, match_opcode, 0 }, +{"fadd.s", "F", "D,S,T", MATCH_FADD_S | MASK_RM, MASK_FADD_S | MASK_RM, match_opcode, 0 }, +{"fadd.s", "F", "D,S,T,m", MATCH_FADD_S, MASK_FADD_S, match_opcode, 0 }, +{"fsub.s", "F", "D,S,T", MATCH_FSUB_S | MASK_RM, MASK_FSUB_S | MASK_RM, match_opcode, 0 }, +{"fsub.s", "F", "D,S,T,m", MATCH_FSUB_S, MASK_FSUB_S, match_opcode, 0 }, +{"fmul.s", "F", "D,S,T", MATCH_FMUL_S | MASK_RM, MASK_FMUL_S | MASK_RM, match_opcode, 0 }, +{"fmul.s", "F", "D,S,T,m", MATCH_FMUL_S, MASK_FMUL_S, match_opcode, 0 }, +{"fdiv.s", "F", "D,S,T", MATCH_FDIV_S | MASK_RM, MASK_FDIV_S | MASK_RM, match_opcode, 0 }, +{"fdiv.s", "F", "D,S,T,m", MATCH_FDIV_S, MASK_FDIV_S, match_opcode, 0 }, +{"fsqrt.s", "F", "D,S", MATCH_FSQRT_S | MASK_RM, MASK_FSQRT_S | MASK_RM, match_opcode, 0 }, +{"fsqrt.s", "F", "D,S,m", MATCH_FSQRT_S, MASK_FSQRT_S, match_opcode, 0 }, +{"fmin.s", "F", "D,S,T", MATCH_FMIN_S, MASK_FMIN_S, match_opcode, 0 }, +{"fmax.s", "F", "D,S,T", MATCH_FMAX_S, MASK_FMAX_S, match_opcode, 0 }, +{"fmadd.s", "F", "D,S,T,R", MATCH_FMADD_S | MASK_RM, MASK_FMADD_S | MASK_RM, match_opcode, 0 }, +{"fmadd.s", "F", "D,S,T,R,m", MATCH_FMADD_S, MASK_FMADD_S, match_opcode, 0 }, +{"fnmadd.s", "F", "D,S,T,R", MATCH_FNMADD_S | MASK_RM, MASK_FNMADD_S | MASK_RM, match_opcode, 0 }, +{"fnmadd.s", "F", "D,S,T,R,m", MATCH_FNMADD_S, MASK_FNMADD_S, match_opcode, 0 }, +{"fmsub.s", "F", "D,S,T,R", MATCH_FMSUB_S | MASK_RM, MASK_FMSUB_S | MASK_RM, match_opcode, 0 }, +{"fmsub.s", "F", "D,S,T,R,m", MATCH_FMSUB_S, MASK_FMSUB_S, match_opcode, 0 }, +{"fnmsub.s", "F", "D,S,T,R", MATCH_FNMSUB_S | MASK_RM, MASK_FNMSUB_S | MASK_RM, match_opcode, 0 }, +{"fnmsub.s", "F", "D,S,T,R,m", MATCH_FNMSUB_S, MASK_FNMSUB_S, match_opcode, 0 }, +{"fcvt.w.s", "F", "d,S", MATCH_FCVT_W_S | MASK_RM, MASK_FCVT_W_S | MASK_RM, match_opcode, 0 }, +{"fcvt.w.s", "F", "d,S,m", MATCH_FCVT_W_S, MASK_FCVT_W_S, match_opcode, 0 }, +{"fcvt.wu.s", "F", "d,S", MATCH_FCVT_WU_S | MASK_RM, MASK_FCVT_WU_S | MASK_RM, match_opcode, 0 }, +{"fcvt.wu.s", "F", "d,S,m", MATCH_FCVT_WU_S, MASK_FCVT_WU_S, match_opcode, 0 }, +{"fcvt.s.w", "F", "D,s", MATCH_FCVT_S_W | MASK_RM, MASK_FCVT_S_W | MASK_RM, match_opcode, 0 }, +{"fcvt.s.w", "F", "D,s,m", MATCH_FCVT_S_W, MASK_FCVT_S_W, match_opcode, 0 }, +{"fcvt.s.wu", "F", "D,s", MATCH_FCVT_S_WU | MASK_RM, MASK_FCVT_S_W | MASK_RM, match_opcode, 0 }, +{"fcvt.s.wu", "F", "D,s,m", MATCH_FCVT_S_WU, MASK_FCVT_S_WU, match_opcode, 0 }, +{"fclass.s", "F", "d,S", MATCH_FCLASS_S, MASK_FCLASS_S, match_opcode, 0 }, +{"feq.s", "F", "d,S,T", MATCH_FEQ_S, MASK_FEQ_S, match_opcode, 0 }, +{"flt.s", "F", "d,S,T", MATCH_FLT_S, MASK_FLT_S, match_opcode, 0 }, +{"fle.s", "F", "d,S,T", MATCH_FLE_S, MASK_FLE_S, match_opcode, 0 }, +{"fgt.s", "F", "d,T,S", MATCH_FLT_S, MASK_FLT_S, match_opcode, 0 }, +{"fge.s", "F", "d,T,S", MATCH_FLE_S, MASK_FLE_S, match_opcode, 0 }, +{"fcvt.l.s", "64F", "d,S", MATCH_FCVT_L_S | MASK_RM, MASK_FCVT_L_S | MASK_RM, match_opcode, 0 }, +{"fcvt.l.s", "64F", "d,S,m", MATCH_FCVT_L_S, MASK_FCVT_L_S, match_opcode, 0 }, +{"fcvt.lu.s", "64F", "d,S", MATCH_FCVT_LU_S | MASK_RM, MASK_FCVT_LU_S | MASK_RM, match_opcode, 0 }, +{"fcvt.lu.s", "64F", "d,S,m", MATCH_FCVT_LU_S, MASK_FCVT_LU_S, match_opcode, 0 }, +{"fcvt.s.l", "64F", "D,s", MATCH_FCVT_S_L | MASK_RM, MASK_FCVT_S_L | MASK_RM, match_opcode, 0 }, +{"fcvt.s.l", "64F", "D,s,m", MATCH_FCVT_S_L, MASK_FCVT_S_L, match_opcode, 0 }, +{"fcvt.s.lu", "64F", "D,s", MATCH_FCVT_S_LU | MASK_RM, MASK_FCVT_S_L | MASK_RM, match_opcode, 0 }, +{"fcvt.s.lu", "64F", "D,s,m", MATCH_FCVT_S_LU, MASK_FCVT_S_LU, match_opcode, 0 }, + +/* Double-precision floating-point instruction subset */ +{"fld", "C", "D,Cn(Cc)", MATCH_C_FLDSP, MASK_C_FLDSP, match_opcode, INSN_ALIAS }, +{"fld", "C", "CD,Cl(Cs)", MATCH_C_FLD, MASK_C_FLD, match_opcode, INSN_ALIAS }, +{"fld", "D", "D,o(s)", MATCH_FLD, MASK_FLD, match_opcode, 0 }, +{"fld", "D", "D,A,s", 0, (int) M_FLD, match_never, INSN_MACRO }, +{"fsd", "C", "CT,CN(Cc)", MATCH_C_FSDSP, MASK_C_FSDSP, match_opcode, INSN_ALIAS }, +{"fsd", "C", "CD,Cl(Cs)", MATCH_C_FSD, MASK_C_FSD, match_opcode, INSN_ALIAS }, +{"fsd", "D", "T,q(s)", MATCH_FSD, MASK_FSD, match_opcode, 0 }, +{"fsd", "D", "T,A,s", 0, (int) M_FSD, match_never, INSN_MACRO }, +{"fmv.d", "D", "D,U", MATCH_FSGNJ_D, MASK_FSGNJ_D, match_rs1_eq_rs2, INSN_ALIAS }, +{"fneg.d", "D", "D,U", MATCH_FSGNJN_D, MASK_FSGNJN_D, match_rs1_eq_rs2, INSN_ALIAS }, +{"fabs.d", "D", "D,U", MATCH_FSGNJX_D, MASK_FSGNJX_D, match_rs1_eq_rs2, INSN_ALIAS }, +{"fsgnj.d", "D", "D,S,T", MATCH_FSGNJ_D, MASK_FSGNJ_D, match_opcode, 0 }, +{"fsgnjn.d", "D", "D,S,T", MATCH_FSGNJN_D, MASK_FSGNJN_D, match_opcode, 0 }, +{"fsgnjx.d", "D", "D,S,T", MATCH_FSGNJX_D, MASK_FSGNJX_D, match_opcode, 0 }, +{"fadd.d", "D", "D,S,T", MATCH_FADD_D | MASK_RM, MASK_FADD_D | MASK_RM, match_opcode, 0 }, +{"fadd.d", "D", "D,S,T,m", MATCH_FADD_D, MASK_FADD_D, match_opcode, 0 }, +{"fsub.d", "D", "D,S,T", MATCH_FSUB_D | MASK_RM, MASK_FSUB_D | MASK_RM, match_opcode, 0 }, +{"fsub.d", "D", "D,S,T,m", MATCH_FSUB_D, MASK_FSUB_D, match_opcode, 0 }, +{"fmul.d", "D", "D,S,T", MATCH_FMUL_D | MASK_RM, MASK_FMUL_D | MASK_RM, match_opcode, 0 }, +{"fmul.d", "D", "D,S,T,m", MATCH_FMUL_D, MASK_FMUL_D, match_opcode, 0 }, +{"fdiv.d", "D", "D,S,T", MATCH_FDIV_D | MASK_RM, MASK_FDIV_D | MASK_RM, match_opcode, 0 }, +{"fdiv.d", "D", "D,S,T,m", MATCH_FDIV_D, MASK_FDIV_D, match_opcode, 0 }, +{"fsqrt.d", "D", "D,S", MATCH_FSQRT_D | MASK_RM, MASK_FSQRT_D | MASK_RM, match_opcode, 0 }, +{"fsqrt.d", "D", "D,S,m", MATCH_FSQRT_D, MASK_FSQRT_D, match_opcode, 0 }, +{"fmin.d", "D", "D,S,T", MATCH_FMIN_D, MASK_FMIN_D, match_opcode, 0 }, +{"fmax.d", "D", "D,S,T", MATCH_FMAX_D, MASK_FMAX_D, match_opcode, 0 }, +{"fmadd.d", "D", "D,S,T,R", MATCH_FMADD_D | MASK_RM, MASK_FMADD_D | MASK_RM, match_opcode, 0 }, +{"fmadd.d", "D", "D,S,T,R,m", MATCH_FMADD_D, MASK_FMADD_D, match_opcode, 0 }, +{"fnmadd.d", "D", "D,S,T,R", MATCH_FNMADD_D | MASK_RM, MASK_FNMADD_D | MASK_RM, match_opcode, 0 }, +{"fnmadd.d", "D", "D,S,T,R,m", MATCH_FNMADD_D, MASK_FNMADD_D, match_opcode, 0 }, +{"fmsub.d", "D", "D,S,T,R", MATCH_FMSUB_D | MASK_RM, MASK_FMSUB_D | MASK_RM, match_opcode, 0 }, +{"fmsub.d", "D", "D,S,T,R,m", MATCH_FMSUB_D, MASK_FMSUB_D, match_opcode, 0 }, +{"fnmsub.d", "D", "D,S,T,R", MATCH_FNMSUB_D | MASK_RM, MASK_FNMSUB_D | MASK_RM, match_opcode, 0 }, +{"fnmsub.d", "D", "D,S,T,R,m", MATCH_FNMSUB_D, MASK_FNMSUB_D, match_opcode, 0 }, +{"fcvt.w.d", "D", "d,S", MATCH_FCVT_W_D | MASK_RM, MASK_FCVT_W_D | MASK_RM, match_opcode, 0 }, +{"fcvt.w.d", "D", "d,S,m", MATCH_FCVT_W_D, MASK_FCVT_W_D, match_opcode, 0 }, +{"fcvt.wu.d", "D", "d,S", MATCH_FCVT_WU_D | MASK_RM, MASK_FCVT_WU_D | MASK_RM, match_opcode, 0 }, +{"fcvt.wu.d", "D", "d,S,m", MATCH_FCVT_WU_D, MASK_FCVT_WU_D, match_opcode, 0 }, +{"fcvt.d.w", "D", "D,s", MATCH_FCVT_D_W, MASK_FCVT_D_W | MASK_RM, match_opcode, 0 }, +{"fcvt.d.wu", "D", "D,s", MATCH_FCVT_D_WU, MASK_FCVT_D_WU | MASK_RM, match_opcode, 0 }, +{"fcvt.d.s", "D", "D,S", MATCH_FCVT_D_S, MASK_FCVT_D_S | MASK_RM, match_opcode, 0 }, +{"fcvt.s.d", "D", "D,S", MATCH_FCVT_S_D | MASK_RM, MASK_FCVT_S_D | MASK_RM, match_opcode, 0 }, +{"fcvt.s.d", "D", "D,S,m", MATCH_FCVT_S_D, MASK_FCVT_S_D, match_opcode, 0 }, +{"fclass.d", "D", "d,S", MATCH_FCLASS_D, MASK_FCLASS_D, match_opcode, 0 }, +{"feq.d", "D", "d,S,T", MATCH_FEQ_D, MASK_FEQ_D, match_opcode, 0 }, +{"flt.d", "D", "d,S,T", MATCH_FLT_D, MASK_FLT_D, match_opcode, 0 }, +{"fle.d", "D", "d,S,T", MATCH_FLE_D, MASK_FLE_D, match_opcode, 0 }, +{"fgt.d", "D", "d,T,S", MATCH_FLT_D, MASK_FLT_D, match_opcode, 0 }, +{"fge.d", "D", "d,T,S", MATCH_FLE_D, MASK_FLE_D, match_opcode, 0 }, +{"fmv.x.d", "64D", "d,S", MATCH_FMV_X_D, MASK_FMV_X_D, match_opcode, 0 }, +{"fmv.d.x", "64D", "D,s", MATCH_FMV_D_X, MASK_FMV_D_X, match_opcode, 0 }, +{"fcvt.l.d", "64D", "d,S", MATCH_FCVT_L_D | MASK_RM, MASK_FCVT_L_D | MASK_RM, match_opcode, 0 }, +{"fcvt.l.d", "64D", "d,S,m", MATCH_FCVT_L_D, MASK_FCVT_L_D, match_opcode, 0 }, +{"fcvt.lu.d", "64D", "d,S", MATCH_FCVT_LU_D | MASK_RM, MASK_FCVT_LU_D | MASK_RM, match_opcode, 0 }, +{"fcvt.lu.d", "64D", "d,S,m", MATCH_FCVT_LU_D, MASK_FCVT_LU_D, match_opcode, 0 }, +{"fcvt.d.l", "64D", "D,s", MATCH_FCVT_D_L | MASK_RM, MASK_FCVT_D_L | MASK_RM, match_opcode, 0 }, +{"fcvt.d.l", "64D", "D,s,m", MATCH_FCVT_D_L, MASK_FCVT_D_L, match_opcode, 0 }, +{"fcvt.d.lu", "64D", "D,s", MATCH_FCVT_D_LU | MASK_RM, MASK_FCVT_D_L | MASK_RM, match_opcode, 0 }, +{"fcvt.d.lu", "64D", "D,s,m", MATCH_FCVT_D_LU, MASK_FCVT_D_LU, match_opcode, 0 }, + +/* Compressed instructions. */ +{"c.ebreak", "C", "", MATCH_C_EBREAK, MASK_C_EBREAK, match_opcode, 0 }, +{"c.jr", "C", "d", MATCH_C_JR, MASK_C_JR, match_rd_nonzero, 0 }, +{"c.jalr", "C", "d", MATCH_C_JALR, MASK_C_JALR, match_rd_nonzero, 0 }, +{"c.j", "C", "Ca", MATCH_C_J, MASK_C_J, match_opcode, 0 }, +{"c.jal", "32C", "Ca", MATCH_C_JAL, MASK_C_JAL, match_opcode, 0 }, +{"c.beqz", "C", "Cs,Cp", MATCH_C_BEQZ, MASK_C_BEQZ, match_opcode, 0 }, +{"c.bnez", "C", "Cs,Cp", MATCH_C_BNEZ, MASK_C_BNEZ, match_opcode, 0 }, +{"c.lwsp", "C", "d,Cm(Cc)", MATCH_C_LWSP, MASK_C_LWSP, match_rd_nonzero, 0 }, +{"c.lw", "C", "Ct,Ck(Cs)", MATCH_C_LW, MASK_C_LW, match_opcode, 0 }, +{"c.swsp", "C", "CV,CM(Cc)", MATCH_C_SWSP, MASK_C_SWSP, match_opcode, 0 }, +{"c.sw", "C", "Ct,Ck(Cs)", MATCH_C_SW, MASK_C_SW, match_opcode, 0 }, +{"c.nop", "C", "", MATCH_C_ADDI, 0xffff, match_opcode, 0 }, +{"c.mv", "C", "d,CV", MATCH_C_MV, MASK_C_MV, match_c_add, 0 }, +{"c.lui", "C", "d,Cu", MATCH_C_LUI, MASK_C_LUI, match_c_lui, 0 }, +{"c.li", "C", "d,Cj", MATCH_C_LI, MASK_C_LI, match_rd_nonzero, 0 }, +{"c.addi4spn","C", "Ct,Cc,CK", MATCH_C_ADDI4SPN, MASK_C_ADDI4SPN, match_opcode, 0 }, +{"c.addi16sp","C", "Cc,CL", MATCH_C_ADDI16SP, MASK_C_ADDI16SP, match_opcode, 0 }, +{"c.addi", "C", "d,Cj", MATCH_C_ADDI, MASK_C_ADDI, match_rd_nonzero, 0 }, +{"c.add", "C", "d,CV", MATCH_C_ADD, MASK_C_ADD, match_c_add, 0 }, +{"c.sub", "C", "Cs,Ct", MATCH_C_SUB, MASK_C_SUB, match_opcode, 0 }, +{"c.and", "C", "Cs,Ct", MATCH_C_AND, MASK_C_AND, match_opcode, 0 }, +{"c.or", "C", "Cs,Ct", MATCH_C_OR, MASK_C_OR, match_opcode, 0 }, +{"c.xor", "C", "Cs,Ct", MATCH_C_XOR, MASK_C_XOR, match_opcode, 0 }, +{"c.slli", "C", "d,C>", MATCH_C_SLLI, MASK_C_SLLI, match_rd_nonzero, 0 }, +{"c.srli", "C", "Cs,C>", MATCH_C_SRLI, MASK_C_SRLI, match_opcode, 0 }, +{"c.srai", "C", "Cs,C>", MATCH_C_SRAI, MASK_C_SRAI, match_opcode, 0 }, +{"c.andi", "C", "Cs,Cj", MATCH_C_ANDI, MASK_C_ANDI, match_opcode, 0 }, +{"c.addiw", "64C", "d,Cj", MATCH_C_ADDIW, MASK_C_ADDIW, match_rd_nonzero, 0 }, +{"c.addw", "64C", "Cs,Ct", MATCH_C_ADDW, MASK_C_ADDW, match_opcode, 0 }, +{"c.subw", "64C", "Cs,Ct", MATCH_C_SUBW, MASK_C_SUBW, match_opcode, 0 }, +{"c.ldsp", "64C", "d,Cn(Cc)", MATCH_C_LDSP, MASK_C_LDSP, match_rd_nonzero, 0 }, +{"c.ld", "64C", "Ct,Cl(Cs)", MATCH_C_LD, MASK_C_LD, match_opcode, 0 }, +{"c.sdsp", "64C", "CV,CN(Cc)", MATCH_C_SDSP, MASK_C_SDSP, match_opcode, 0 }, +{"c.sd", "64C", "Ct,Cl(Cs)", MATCH_C_SD, MASK_C_SD, match_opcode, 0 }, +{"c.fldsp", "C", "D,Cn(Cc)", MATCH_C_FLDSP, MASK_C_FLDSP, match_opcode, 0 }, +{"c.fld", "C", "CD,Cl(Cs)", MATCH_C_FLD, MASK_C_FLD, match_opcode, 0 }, +{"c.fsdsp", "C", "CT,CN(Cc)", MATCH_C_FSDSP, MASK_C_FSDSP, match_opcode, 0 }, +{"c.fsd", "C", "CD,Cl(Cs)", MATCH_C_FSD, MASK_C_FSD, match_opcode, 0 }, +{"c.flwsp", "32C", "D,Cm(Cc)", MATCH_C_FLWSP, MASK_C_FLWSP, match_opcode, 0 }, +{"c.flw", "32C", "CD,Ck(Cs)", MATCH_C_FLW, MASK_C_FLW, match_opcode, 0 }, +{"c.fswsp", "32C", "CT,CM(Cc)", MATCH_C_FSWSP, MASK_C_FSWSP, match_opcode, 0 }, +{"c.fsw", "32C", "CD,Ck(Cs)", MATCH_C_FSW, MASK_C_FSW, match_opcode, 0 }, + +/* Supervisor instructions */ +{"csrr", "I", "d,E", MATCH_CSRRS, MASK_CSRRS | MASK_RS1, match_opcode, 0 }, +{"csrwi", "I", "E,Z", MATCH_CSRRWI, MASK_CSRRWI | MASK_RD, match_opcode, 0 }, +{"csrw", "I", "E,s", MATCH_CSRRW, MASK_CSRRW | MASK_RD, match_opcode, 0 }, +{"csrw", "I", "E,Z", MATCH_CSRRWI, MASK_CSRRWI | MASK_RD, match_opcode, 0 }, +{"csrsi", "I", "E,Z", MATCH_CSRRSI, MASK_CSRRSI | MASK_RD, match_opcode, 0 }, +{"csrs", "I", "E,s", MATCH_CSRRS, MASK_CSRRS | MASK_RD, match_opcode, 0 }, +{"csrs", "I", "E,Z", MATCH_CSRRSI, MASK_CSRRSI | MASK_RD, match_opcode, 0 }, +{"csrci", "I", "E,Z", MATCH_CSRRCI, MASK_CSRRCI | MASK_RD, match_opcode, 0 }, +{"csrc", "I", "E,s", MATCH_CSRRC, MASK_CSRRC | MASK_RD, match_opcode, 0 }, +{"csrc", "I", "E,Z", MATCH_CSRRCI, MASK_CSRRCI | MASK_RD, match_opcode, 0 }, +{"csrrw", "I", "d,E,s", MATCH_CSRRW, MASK_CSRRW, match_opcode, 0 }, +{"csrrw", "I", "d,E,Z", MATCH_CSRRWI, MASK_CSRRWI, match_opcode, 0 }, +{"csrrs", "I", "d,E,s", MATCH_CSRRS, MASK_CSRRS, match_opcode, 0 }, +{"csrrs", "I", "d,E,Z", MATCH_CSRRSI, MASK_CSRRSI, match_opcode, 0 }, +{"csrrc", "I", "d,E,s", MATCH_CSRRC, MASK_CSRRC, match_opcode, 0 }, +{"csrrc", "I", "d,E,Z", MATCH_CSRRCI, MASK_CSRRCI, match_opcode, 0 }, +{"csrrwi", "I", "d,E,Z", MATCH_CSRRWI, MASK_CSRRWI, match_opcode, 0 }, +{"csrrsi", "I", "d,E,Z", MATCH_CSRRSI, MASK_CSRRSI, match_opcode, 0 }, +{"csrrci", "I", "d,E,Z", MATCH_CSRRCI, MASK_CSRRCI, match_opcode, 0 }, +{"uret", "I", "", MATCH_URET, MASK_URET, match_opcode, 0 }, +{"sret", "I", "", MATCH_SRET, MASK_SRET, match_opcode, 0 }, +{"hret", "I", "", MATCH_HRET, MASK_HRET, match_opcode, 0 }, +{"mret", "I", "", MATCH_MRET, MASK_MRET, match_opcode, 0 }, +{"dret", "I", "", MATCH_DRET, MASK_DRET, match_opcode, 0 }, +{"sfence.vm", "I", "", MATCH_SFENCE_VM, MASK_SFENCE_VM | MASK_RS1, match_opcode, 0 }, +{"sfence.vm", "I", "s", MATCH_SFENCE_VM, MASK_SFENCE_VM, match_opcode, 0 }, +{"wfi", "I", "", MATCH_WFI, MASK_WFI, match_opcode, 0 }, + +/* Terminate the list. */ +{0, 0, 0, 0, 0, 0, 0} +}; -- 2.34.1