From 561a72d4ddf825ffaf8e88551e9bd6707cd6c59f Mon Sep 17 00:00:00 2001 From: Tamar Christina Date: Tue, 15 May 2018 16:11:42 +0100 Subject: [PATCH] Modify AArch64 Assembly and disassembly functions to be able to fail and report why. This patch if the first patch in a series to add the ability to add constraints to system registers that an instruction must adhere to in order for the register to be usable with that instruction. These constraints can also be used to disambiguate between registers with the same encoding during disassembly. This patch adds a new flags entry in the sysreg structures and ensures it is filled in and read out during assembly/disassembly. It also adds the ability for the assemble and disassemble functions to be able to gracefully fail and re-use the existing error reporting infrastructure. The return type of these functions are changed to a boolean to denote success or failure and the error structure is passed around to them. This requires aarch64-gen changes so a lot of the changes here are just mechanical. gas/ PR binutils/21446 * config/tc-aarch64.c (parse_sys_reg): Return register flags. (parse_operands): Fill in register flags. gdb/ PR binutils/21446 * aarch64-tdep.c (aarch64_analyze_prologue, aarch64_software_single_step, aarch64_displaced_step_copy_insn): Indicate not interested in errors. include/ PR binutils/21446 * opcode/aarch64.h (aarch64_opnd_info): Change sysreg to struct. (aarch64_decode_insn): Accept error struct. opcodes/ PR binutils/21446 * aarch64-asm.h (aarch64_insert_operand, aarch64_##x): Return boolean and take error struct. * aarch64-asm.c (aarch64_ext_regno, aarch64_ins_reglane, aarch64_ins_reglist, aarch64_ins_ldst_reglist, aarch64_ins_ldst_reglist_r, aarch64_ins_ldst_elemlist, aarch64_ins_advsimd_imm_shift, aarch64_ins_imm, aarch64_ins_imm_half, aarch64_ins_advsimd_imm_modified, aarch64_ins_fpimm, aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2, aarch64_ins_fbits, aarch64_ins_aimm, aarch64_ins_limm_1, aarch64_ins_limm, aarch64_ins_inv_limm, aarch64_ins_ft, aarch64_ins_addr_simple, aarch64_ins_addr_regoff, aarch64_ins_addr_offset, aarch64_ins_addr_simm, aarch64_ins_addr_simm10, aarch64_ins_addr_uimm12, aarch64_ins_simd_addr_post, aarch64_ins_cond, aarch64_ins_sysreg, aarch64_ins_pstatefield, aarch64_ins_sysins_op, aarch64_ins_barrier, aarch64_ins_prfop, aarch64_ins_hint, aarch64_ins_reg_extended, aarch64_ins_reg_shifted, aarch64_ins_sve_addr_ri_s4xvl, aarch64_ins_sve_addr_ri_s6xvl, aarch64_ins_sve_addr_ri_s9xvl, aarch64_ins_sve_addr_ri_s4, aarch64_ins_sve_addr_ri_u6, aarch64_ins_sve_addr_rr_lsl, aarch64_ins_sve_addr_rz_xtw, aarch64_ins_sve_addr_zi_u5, aarch64_ext_sve_addr_zz, aarch64_ins_sve_addr_zz_lsl, aarch64_ins_sve_addr_zz_sxtw, aarch64_ins_sve_addr_zz_uxtw, aarch64_ins_sve_aimm, aarch64_ins_sve_asimm, aarch64_ins_sve_index, aarch64_ins_sve_limm_mov, aarch64_ins_sve_quad_index, aarch64_ins_sve_reglist, aarch64_ins_sve_scale, aarch64_ins_sve_shlimm, aarch64_ins_sve_shrimm, aarch64_ins_sve_float_half_one, aarch64_ins_sve_float_half_two, aarch64_ins_sve_float_zero_one, aarch64_opcode_encode): Likewise. * aarch64-dis.h (aarch64_extract_operand, aarch64_##x): Likewise. * aarch64-dis.c (aarch64_ext_regno, aarch64_ext_reglane, aarch64_ext_reglist, aarch64_ext_ldst_reglist, aarch64_ext_ldst_reglist_r, aarch64_ext_ldst_elemlist, aarch64_ext_advsimd_imm_shift, aarch64_ext_imm, aarch64_ext_imm_half, aarch64_ext_advsimd_imm_modified, aarch64_ext_fpimm, aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2, aarch64_ext_fbits, aarch64_ext_aimm, aarch64_ext_limm_1, aarch64_ext_limm, decode_limm, aarch64_ext_inv_limm, aarch64_ext_ft, aarch64_ext_addr_simple, aarch64_ext_addr_regoff, aarch64_ext_addr_offset, aarch64_ext_addr_simm, aarch64_ext_addr_simm10, aarch64_ext_addr_uimm12, aarch64_ext_simd_addr_post, aarch64_ext_cond, aarch64_ext_sysreg, aarch64_ext_pstatefield, aarch64_ext_sysins_op, aarch64_ext_barrier, aarch64_ext_prfop, aarch64_ext_hint, aarch64_ext_reg_extended, aarch64_ext_reg_shifted, aarch64_ext_sve_addr_ri_s4xvl, aarch64_ext_sve_addr_ri_s6xvl, aarch64_ext_sve_addr_ri_s9xvl, aarch64_ext_sve_addr_ri_s4, aarch64_ext_sve_addr_ri_u6, aarch64_ext_sve_addr_rr_lsl, aarch64_ext_sve_addr_rz_xtw, aarch64_ext_sve_addr_zi_u5, aarch64_ext_sve_addr_zz, aarch64_ext_sve_addr_zz_lsl, aarch64_ext_sve_addr_zz_sxtw, aarch64_ext_sve_addr_zz_uxtw, aarch64_ext_sve_aimm, aarch64_ext_sve_asimm, aarch64_ext_sve_index, aarch64_ext_sve_limm_mov, aarch64_ext_sve_quad_index, aarch64_ext_sve_reglist, aarch64_ext_sve_scale, aarch64_ext_sve_shlimm, aarch64_ext_sve_shrimm, aarch64_ext_sve_float_half_one, aarch64_ext_sve_float_half_two, aarch64_ext_sve_float_zero_one, aarch64_opcode_decode): Likewise. (determine_disassembling_preference, aarch64_decode_insn, print_insn_aarch64_word, print_insn_data): Take errors struct. (print_insn_aarch64): Use errors. * aarch64-asm-2.c: Regenerate. * aarch64-dis-2.c: Regenerate. * aarch64-gen.c (print_operand_inserter): Use errors and change type to boolean in aarch64_insert_operan. (print_operand_extractor): Likewise. * aarch64-opc.c (aarch64_print_operand): Use sysreg struct. --- gas/ChangeLog | 6 + gas/config/tc-aarch64.c | 29 ++- gdb/ChangeLog | 7 + gdb/aarch64-tdep.c | 8 +- include/ChangeLog | 6 + include/opcode/aarch64.h | 15 +- opcodes/ChangeLog | 66 +++++ opcodes/aarch64-asm-2.c | 119 ++++----- opcodes/aarch64-asm.c | 434 ++++++++++++++++++-------------- opcodes/aarch64-asm.h | 10 +- opcodes/aarch64-dis-2.c | 125 ++++----- opcodes/aarch64-dis.c | 532 ++++++++++++++++++++++----------------- opcodes/aarch64-dis.h | 11 +- opcodes/aarch64-gen.c | 14 +- opcodes/aarch64-opc.c | 4 +- 15 files changed, 813 insertions(+), 573 deletions(-) diff --git a/gas/ChangeLog b/gas/ChangeLog index 358f033fd5..60a00f0da9 100644 --- a/gas/ChangeLog +++ b/gas/ChangeLog @@ -1,3 +1,9 @@ +2018-05-15 Tamar Christina + + PR binutils/21446 + * config/tc-aarch64.c (parse_sys_reg): Return register flags. + (parse_operands): Fill in register flags. + 2018-05-14 Nick Clifton * write.c (maybe_generate_build_notes): Generate notes on a diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c index e673e12711..750025ac11 100644 --- a/gas/config/tc-aarch64.c +++ b/gas/config/tc-aarch64.c @@ -3934,7 +3934,8 @@ parse_barrier_psb (char **str, static int parse_sys_reg (char **str, struct hash_control *sys_regs, - int imple_defined_p, int pstatefield_p) + int imple_defined_p, int pstatefield_p, + uint32_t* flags) { char *p, *q; char buf[32]; @@ -3965,6 +3966,8 @@ parse_sys_reg (char **str, struct hash_control *sys_regs, if (op0 > 3 || op1 > 7 || cn > 15 || cm > 15 || op2 > 7) return PARSE_FAIL; value = (op0 << 14) | (op1 << 11) | (cn << 7) | (cm << 3) | op2; + if (flags) + *flags = 0; } } else @@ -3979,6 +3982,8 @@ parse_sys_reg (char **str, struct hash_control *sys_regs, as_warn (_("system register name '%s' is deprecated and may be " "removed in a future release"), buf); value = o->value; + if (flags) + *flags = o->flags; } *str = q; @@ -6347,17 +6352,21 @@ parse_operands (char *str, const aarch64_opcode *opcode) goto regoff_addr; case AARCH64_OPND_SYSREG: - if ((val = parse_sys_reg (&str, aarch64_sys_regs_hsh, 1, 0)) - == PARSE_FAIL) - { - set_syntax_error (_("unknown or missing system register name")); - goto failure; - } - inst.base.operands[i].sysreg = val; - break; + { + uint32_t sysreg_flags; + if ((val = parse_sys_reg (&str, aarch64_sys_regs_hsh, 1, 0, + &sysreg_flags)) == PARSE_FAIL) + { + set_syntax_error (_("unknown or missing system register name")); + goto failure; + } + inst.base.operands[i].sysreg.value = val; + inst.base.operands[i].sysreg.flags = sysreg_flags; + break; + } case AARCH64_OPND_PSTATEFIELD: - if ((val = parse_sys_reg (&str, aarch64_pstatefield_hsh, 0, 1)) + if ((val = parse_sys_reg (&str, aarch64_pstatefield_hsh, 0, 1, NULL)) == PARSE_FAIL) { set_syntax_error (_("unknown or missing PSTATE field name")); diff --git a/gdb/ChangeLog b/gdb/ChangeLog index 8035353069..57a4075a12 100644 --- a/gdb/ChangeLog +++ b/gdb/ChangeLog @@ -1,3 +1,10 @@ +2018-05-15 Tamar Christina + + PR binutils/21446 + * aarch64-tdep.c (aarch64_analyze_prologue, + aarch64_software_single_step, aarch64_displaced_step_copy_insn): + Indicate not interested in errors. + 2018-05-15 Maciej W. Rozycki * mips-linux-nat.c (mips_linux_nat_target::fetch_registers): diff --git a/gdb/aarch64-tdep.c b/gdb/aarch64-tdep.c index 3c1f389bfa..c5ed80cdbe 100644 --- a/gdb/aarch64-tdep.c +++ b/gdb/aarch64-tdep.c @@ -244,7 +244,7 @@ aarch64_analyze_prologue (struct gdbarch *gdbarch, insn = reader.read (start, 4, byte_order_for_code); - if (aarch64_decode_insn (insn, &inst, 1) != 0) + if (aarch64_decode_insn (insn, &inst, 1, NULL) != 0) break; if (inst.opcode->iclass == addsub_imm @@ -2425,7 +2425,7 @@ aarch64_software_single_step (struct regcache *regcache) int last_breakpoint = 0; /* Defaults to 0 (no breakpoints placed). */ aarch64_inst inst; - if (aarch64_decode_insn (insn, &inst, 1) != 0) + if (aarch64_decode_insn (insn, &inst, 1, NULL) != 0) return {}; /* Look for a Load Exclusive instruction which begins the sequence. */ @@ -2438,7 +2438,7 @@ aarch64_software_single_step (struct regcache *regcache) insn = read_memory_unsigned_integer (loc, insn_size, byte_order_for_code); - if (aarch64_decode_insn (insn, &inst, 1) != 0) + if (aarch64_decode_insn (insn, &inst, 1, NULL) != 0) return {}; /* Check if the instruction is a conditional branch. */ if (inst.opcode->iclass == condbranch) @@ -2731,7 +2731,7 @@ aarch64_displaced_step_copy_insn (struct gdbarch *gdbarch, struct aarch64_displaced_step_data dsd; aarch64_inst inst; - if (aarch64_decode_insn (insn, &inst, 1) != 0) + if (aarch64_decode_insn (insn, &inst, 1, NULL) != 0) return NULL; /* Look for a Load Exclusive instruction which begins the sequence. */ diff --git a/include/ChangeLog b/include/ChangeLog index 92c80fdfbd..8c3d5df791 100644 --- a/include/ChangeLog +++ b/include/ChangeLog @@ -1,3 +1,9 @@ +2018-05-15 Tamar Christina + + PR binutils/21446 + * opcode/aarch64.h (aarch64_opnd_info): Change sysreg to struct. + (aarch64_decode_insn): Accept error struct. + 2018-05-15 Francois H. Theron * opcode/nfp.h: Use uint64_t instead of bfd_vma. diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h index 16c41bfd73..7bc88c5723 100644 --- a/include/opcode/aarch64.h +++ b/include/opcode/aarch64.h @@ -957,9 +957,17 @@ struct aarch64_opnd_info unsigned preind : 1; /* Pre-indexed. */ unsigned postind : 1; /* Post-indexed. */ } addr; + + struct + { + /* The encoding of the system register. */ + aarch64_insn value; + + /* The system register flags. */ + uint32_t flags; + } sysreg; + const aarch64_cond *cond; - /* The encoding of the system register. */ - aarch64_insn sysreg; /* The encoding of the PSTATE field. */ aarch64_insn pstatefield; const aarch64_sys_ins_reg *sysins_op; @@ -1138,7 +1146,8 @@ extern int aarch64_zero_register_p (const aarch64_opnd_info *); extern int -aarch64_decode_insn (aarch64_insn, aarch64_inst *, bfd_boolean); +aarch64_decode_insn (aarch64_insn, aarch64_inst *, bfd_boolean, + aarch64_operand_error *errors); /* Given an operand qualifier, return the expected data element size of a qualified operand. */ diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index ea407e344b..a30e823674 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,3 +1,69 @@ +2018-05-15 Tamar Christina + + PR binutils/21446 + * aarch64-asm.h (aarch64_insert_operand, aarch64_##x): Return boolean + and take error struct. + * aarch64-asm.c (aarch64_ext_regno, aarch64_ins_reglane, + aarch64_ins_reglist, aarch64_ins_ldst_reglist, + aarch64_ins_ldst_reglist_r, aarch64_ins_ldst_elemlist, + aarch64_ins_advsimd_imm_shift, aarch64_ins_imm, aarch64_ins_imm_half, + aarch64_ins_advsimd_imm_modified, aarch64_ins_fpimm, + aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2, aarch64_ins_fbits, + aarch64_ins_aimm, aarch64_ins_limm_1, aarch64_ins_limm, + aarch64_ins_inv_limm, aarch64_ins_ft, aarch64_ins_addr_simple, + aarch64_ins_addr_regoff, aarch64_ins_addr_offset, aarch64_ins_addr_simm, + aarch64_ins_addr_simm10, aarch64_ins_addr_uimm12, + aarch64_ins_simd_addr_post, aarch64_ins_cond, aarch64_ins_sysreg, + aarch64_ins_pstatefield, aarch64_ins_sysins_op, aarch64_ins_barrier, + aarch64_ins_prfop, aarch64_ins_hint, aarch64_ins_reg_extended, + aarch64_ins_reg_shifted, aarch64_ins_sve_addr_ri_s4xvl, + aarch64_ins_sve_addr_ri_s6xvl, aarch64_ins_sve_addr_ri_s9xvl, + aarch64_ins_sve_addr_ri_s4, aarch64_ins_sve_addr_ri_u6, + aarch64_ins_sve_addr_rr_lsl, aarch64_ins_sve_addr_rz_xtw, + aarch64_ins_sve_addr_zi_u5, aarch64_ext_sve_addr_zz, + aarch64_ins_sve_addr_zz_lsl, aarch64_ins_sve_addr_zz_sxtw, + aarch64_ins_sve_addr_zz_uxtw, aarch64_ins_sve_aimm, + aarch64_ins_sve_asimm, aarch64_ins_sve_index, aarch64_ins_sve_limm_mov, + aarch64_ins_sve_quad_index, aarch64_ins_sve_reglist, + aarch64_ins_sve_scale, aarch64_ins_sve_shlimm, aarch64_ins_sve_shrimm, + aarch64_ins_sve_float_half_one, aarch64_ins_sve_float_half_two, + aarch64_ins_sve_float_zero_one, aarch64_opcode_encode): Likewise. + * aarch64-dis.h (aarch64_extract_operand, aarch64_##x): Likewise. + * aarch64-dis.c (aarch64_ext_regno, aarch64_ext_reglane, + aarch64_ext_reglist, aarch64_ext_ldst_reglist, + aarch64_ext_ldst_reglist_r, aarch64_ext_ldst_elemlist, + aarch64_ext_advsimd_imm_shift, aarch64_ext_imm, aarch64_ext_imm_half, + aarch64_ext_advsimd_imm_modified, aarch64_ext_fpimm, + aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2, aarch64_ext_fbits, + aarch64_ext_aimm, aarch64_ext_limm_1, aarch64_ext_limm, decode_limm, + aarch64_ext_inv_limm, aarch64_ext_ft, aarch64_ext_addr_simple, + aarch64_ext_addr_regoff, aarch64_ext_addr_offset, aarch64_ext_addr_simm, + aarch64_ext_addr_simm10, aarch64_ext_addr_uimm12, + aarch64_ext_simd_addr_post, aarch64_ext_cond, aarch64_ext_sysreg, + aarch64_ext_pstatefield, aarch64_ext_sysins_op, aarch64_ext_barrier, + aarch64_ext_prfop, aarch64_ext_hint, aarch64_ext_reg_extended, + aarch64_ext_reg_shifted, aarch64_ext_sve_addr_ri_s4xvl, + aarch64_ext_sve_addr_ri_s6xvl, aarch64_ext_sve_addr_ri_s9xvl, + aarch64_ext_sve_addr_ri_s4, aarch64_ext_sve_addr_ri_u6, + aarch64_ext_sve_addr_rr_lsl, aarch64_ext_sve_addr_rz_xtw, + aarch64_ext_sve_addr_zi_u5, aarch64_ext_sve_addr_zz, + aarch64_ext_sve_addr_zz_lsl, aarch64_ext_sve_addr_zz_sxtw, + aarch64_ext_sve_addr_zz_uxtw, aarch64_ext_sve_aimm, + aarch64_ext_sve_asimm, aarch64_ext_sve_index, aarch64_ext_sve_limm_mov, + aarch64_ext_sve_quad_index, aarch64_ext_sve_reglist, + aarch64_ext_sve_scale, aarch64_ext_sve_shlimm, aarch64_ext_sve_shrimm, + aarch64_ext_sve_float_half_one, aarch64_ext_sve_float_half_two, + aarch64_ext_sve_float_zero_one, aarch64_opcode_decode): Likewise. + (determine_disassembling_preference, aarch64_decode_insn, + print_insn_aarch64_word, print_insn_data): Take errors struct. + (print_insn_aarch64): Use errors. + * aarch64-asm-2.c: Regenerate. + * aarch64-dis-2.c: Regenerate. + * aarch64-gen.c (print_operand_inserter): Use errors and change type to + boolean in aarch64_insert_operan. + (print_operand_extractor): Likewise. + * aarch64-opc.c (aarch64_print_operand): Use sysreg struct. + 2018-05-15 Francois H. Theron * nfp-dis.c: Use uint64_t for instruction variables, not bfd_vma. diff --git a/opcodes/aarch64-asm-2.c b/opcodes/aarch64-asm-2.c index 7987384a2c..01bc0e1363 100644 --- a/opcodes/aarch64-asm-2.c +++ b/opcodes/aarch64-asm-2.c @@ -579,10 +579,11 @@ aarch64_find_real_opcode (const aarch64_opcode *opcode) return aarch64_opcode_table + value; } -const char* +bfd_boolean aarch64_insert_operand (const aarch64_operand *self, const aarch64_opnd_info *info, - aarch64_insn *code, const aarch64_inst *inst) + aarch64_insn *code, const aarch64_inst *inst, + aarch64_operand_error *errors) { /* Use the index as the key. */ int key = self - aarch64_operands; @@ -634,26 +635,26 @@ aarch64_insert_operand (const aarch64_operand *self, case 182: case 186: case 189: - return aarch64_ins_regno (self, info, code, inst); + return aarch64_ins_regno (self, info, code, inst, errors); case 13: - return aarch64_ins_reg_extended (self, info, code, inst); + return aarch64_ins_reg_extended (self, info, code, inst, errors); case 14: - return aarch64_ins_reg_shifted (self, info, code, inst); + return aarch64_ins_reg_shifted (self, info, code, inst, errors); case 19: - return aarch64_ins_ft (self, info, code, inst); + return aarch64_ins_ft (self, info, code, inst, errors); case 30: case 31: case 32: case 191: - return aarch64_ins_reglane (self, info, code, inst); + return aarch64_ins_reglane (self, info, code, inst, errors); case 33: - return aarch64_ins_reglist (self, info, code, inst); + return aarch64_ins_reglist (self, info, code, inst, errors); case 34: - return aarch64_ins_ldst_reglist (self, info, code, inst); + return aarch64_ins_ldst_reglist (self, info, code, inst, errors); case 35: - return aarch64_ins_ldst_reglist_r (self, info, code, inst); + return aarch64_ins_ldst_reglist_r (self, info, code, inst, errors); case 36: - return aarch64_ins_ldst_elemlist (self, info, code, inst); + return aarch64_ins_ldst_elemlist (self, info, code, inst, errors); case 37: case 38: case 39: @@ -686,85 +687,85 @@ aarch64_insert_operand (const aarch64_operand *self, case 171: case 172: case 173: - return aarch64_ins_imm (self, info, code, inst); + return aarch64_ins_imm (self, info, code, inst, errors); case 41: case 42: - return aarch64_ins_advsimd_imm_shift (self, info, code, inst); + return aarch64_ins_advsimd_imm_shift (self, info, code, inst, errors); case 43: case 44: case 45: - return aarch64_ins_advsimd_imm_modified (self, info, code, inst); + return aarch64_ins_advsimd_imm_modified (self, info, code, inst, errors); case 49: case 140: - return aarch64_ins_fpimm (self, info, code, inst); + return aarch64_ins_fpimm (self, info, code, inst, errors); case 64: case 147: - return aarch64_ins_limm (self, info, code, inst); + return aarch64_ins_limm (self, info, code, inst, errors); case 65: - return aarch64_ins_aimm (self, info, code, inst); + return aarch64_ins_aimm (self, info, code, inst, errors); case 66: - return aarch64_ins_imm_half (self, info, code, inst); + return aarch64_ins_imm_half (self, info, code, inst, errors); case 67: - return aarch64_ins_fbits (self, info, code, inst); + return aarch64_ins_fbits (self, info, code, inst, errors); case 69: case 70: case 145: - return aarch64_ins_imm_rotate2 (self, info, code, inst); + return aarch64_ins_imm_rotate2 (self, info, code, inst, errors); case 71: case 144: - return aarch64_ins_imm_rotate1 (self, info, code, inst); + return aarch64_ins_imm_rotate1 (self, info, code, inst, errors); case 72: case 73: - return aarch64_ins_cond (self, info, code, inst); + return aarch64_ins_cond (self, info, code, inst, errors); case 79: case 86: - return aarch64_ins_addr_simple (self, info, code, inst); + return aarch64_ins_addr_simple (self, info, code, inst, errors); case 80: - return aarch64_ins_addr_regoff (self, info, code, inst); + return aarch64_ins_addr_regoff (self, info, code, inst, errors); case 81: case 82: case 83: - return aarch64_ins_addr_simm (self, info, code, inst); + return aarch64_ins_addr_simm (self, info, code, inst, errors); case 84: - return aarch64_ins_addr_simm10 (self, info, code, inst); + return aarch64_ins_addr_simm10 (self, info, code, inst, errors); case 85: - return aarch64_ins_addr_uimm12 (self, info, code, inst); + return aarch64_ins_addr_uimm12 (self, info, code, inst, errors); case 87: - return aarch64_ins_addr_offset (self, info, code, inst); + return aarch64_ins_addr_offset (self, info, code, inst, errors); case 88: - return aarch64_ins_simd_addr_post (self, info, code, inst); + return aarch64_ins_simd_addr_post (self, info, code, inst, errors); case 89: - return aarch64_ins_sysreg (self, info, code, inst); + return aarch64_ins_sysreg (self, info, code, inst, errors); case 90: - return aarch64_ins_pstatefield (self, info, code, inst); + return aarch64_ins_pstatefield (self, info, code, inst, errors); case 91: case 92: case 93: case 94: - return aarch64_ins_sysins_op (self, info, code, inst); + return aarch64_ins_sysins_op (self, info, code, inst, errors); case 95: case 96: - return aarch64_ins_barrier (self, info, code, inst); + return aarch64_ins_barrier (self, info, code, inst, errors); case 97: - return aarch64_ins_prfop (self, info, code, inst); + return aarch64_ins_prfop (self, info, code, inst, errors); case 98: - return aarch64_ins_hint (self, info, code, inst); + return aarch64_ins_hint (self, info, code, inst, errors); case 99: - return aarch64_ins_sve_addr_ri_s4 (self, info, code, inst); + return aarch64_ins_sve_addr_ri_s4 (self, info, code, inst, errors); case 100: case 101: case 102: case 103: - return aarch64_ins_sve_addr_ri_s4xvl (self, info, code, inst); + return aarch64_ins_sve_addr_ri_s4xvl (self, info, code, inst, errors); case 104: - return aarch64_ins_sve_addr_ri_s6xvl (self, info, code, inst); + return aarch64_ins_sve_addr_ri_s6xvl (self, info, code, inst, errors); case 105: - return aarch64_ins_sve_addr_ri_s9xvl (self, info, code, inst); + return aarch64_ins_sve_addr_ri_s9xvl (self, info, code, inst, errors); case 106: case 107: case 108: case 109: - return aarch64_ins_sve_addr_ri_u6 (self, info, code, inst); + return aarch64_ins_sve_addr_ri_u6 (self, info, code, inst, errors); case 110: case 111: case 112: @@ -778,7 +779,7 @@ aarch64_insert_operand (const aarch64_operand *self, case 120: case 121: case 122: - return aarch64_ins_sve_addr_rr_lsl (self, info, code, inst); + return aarch64_ins_sve_addr_rr_lsl (self, info, code, inst, errors); case 123: case 124: case 125: @@ -787,49 +788,49 @@ aarch64_insert_operand (const aarch64_operand *self, case 128: case 129: case 130: - return aarch64_ins_sve_addr_rz_xtw (self, info, code, inst); + return aarch64_ins_sve_addr_rz_xtw (self, info, code, inst, errors); case 131: case 132: case 133: case 134: - return aarch64_ins_sve_addr_zi_u5 (self, info, code, inst); + return aarch64_ins_sve_addr_zi_u5 (self, info, code, inst, errors); case 135: - return aarch64_ins_sve_addr_zz_lsl (self, info, code, inst); + return aarch64_ins_sve_addr_zz_lsl (self, info, code, inst, errors); case 136: - return aarch64_ins_sve_addr_zz_sxtw (self, info, code, inst); + return aarch64_ins_sve_addr_zz_sxtw (self, info, code, inst, errors); case 137: - return aarch64_ins_sve_addr_zz_uxtw (self, info, code, inst); + return aarch64_ins_sve_addr_zz_uxtw (self, info, code, inst, errors); case 138: - return aarch64_ins_sve_aimm (self, info, code, inst); + return aarch64_ins_sve_aimm (self, info, code, inst, errors); case 139: - return aarch64_ins_sve_asimm (self, info, code, inst); + return aarch64_ins_sve_asimm (self, info, code, inst, errors); case 141: - return aarch64_ins_sve_float_half_one (self, info, code, inst); + return aarch64_ins_sve_float_half_one (self, info, code, inst, errors); case 142: - return aarch64_ins_sve_float_half_two (self, info, code, inst); + return aarch64_ins_sve_float_half_two (self, info, code, inst, errors); case 143: - return aarch64_ins_sve_float_zero_one (self, info, code, inst); + return aarch64_ins_sve_float_zero_one (self, info, code, inst, errors); case 146: - return aarch64_ins_inv_limm (self, info, code, inst); + return aarch64_ins_inv_limm (self, info, code, inst, errors); case 148: - return aarch64_ins_sve_limm_mov (self, info, code, inst); + return aarch64_ins_sve_limm_mov (self, info, code, inst, errors); case 150: - return aarch64_ins_sve_scale (self, info, code, inst); + return aarch64_ins_sve_scale (self, info, code, inst, errors); case 162: case 163: - return aarch64_ins_sve_shlimm (self, info, code, inst); + return aarch64_ins_sve_shlimm (self, info, code, inst, errors); case 164: case 165: - return aarch64_ins_sve_shrimm (self, info, code, inst); + return aarch64_ins_sve_shrimm (self, info, code, inst, errors); case 183: case 184: case 185: - return aarch64_ins_sve_quad_index (self, info, code, inst); + return aarch64_ins_sve_quad_index (self, info, code, inst, errors); case 187: - return aarch64_ins_sve_index (self, info, code, inst); + return aarch64_ins_sve_index (self, info, code, inst, errors); case 188: case 190: - return aarch64_ins_sve_reglist (self, info, code, inst); + return aarch64_ins_sve_reglist (self, info, code, inst, errors); default: assert (0); abort (); } } diff --git a/opcodes/aarch64-asm.c b/opcodes/aarch64-asm.c index a4c6a27726..67c9b6e5d9 100644 --- a/opcodes/aarch64-asm.c +++ b/opcodes/aarch64-asm.c @@ -78,21 +78,23 @@ insert_all_fields (const aarch64_operand *self, aarch64_insn *code, /* Operand inserters. */ /* Insert register number. */ -const char * +bfd_boolean aarch64_ins_regno (const aarch64_operand *self, const aarch64_opnd_info *info, aarch64_insn *code, - const aarch64_inst *inst ATTRIBUTE_UNUSED) + const aarch64_inst *inst ATTRIBUTE_UNUSED, + aarch64_operand_error *errors ATTRIBUTE_UNUSED) { insert_field (self->fields[0], code, info->reg.regno, 0); - return NULL; + return TRUE; } /* Insert register number, index and/or other data for SIMD register element operand, e.g. the last source operand in SQDMLAL , , .[]. */ -const char * +bfd_boolean aarch64_ins_reglane (const aarch64_operand *self, const aarch64_opnd_info *info, - aarch64_insn *code, const aarch64_inst *inst) + aarch64_insn *code, const aarch64_inst *inst, + aarch64_operand_error *errors ATTRIBUTE_UNUSED) { /* regno */ insert_field (self->fields[0], code, info->reglane.regno, inst->opcode->mask); @@ -173,28 +175,30 @@ aarch64_ins_reglane (const aarch64_operand *self, const aarch64_opnd_info *info, assert (0); } } - return NULL; + return TRUE; } /* Insert regno and len field of a register list operand, e.g. Vn in TBL. */ -const char * +bfd_boolean aarch64_ins_reglist (const aarch64_operand *self, const aarch64_opnd_info *info, aarch64_insn *code, - const aarch64_inst *inst ATTRIBUTE_UNUSED) + const aarch64_inst *inst ATTRIBUTE_UNUSED, + aarch64_operand_error *errors ATTRIBUTE_UNUSED) { /* R */ insert_field (self->fields[0], code, info->reglist.first_regno, 0); /* len */ insert_field (FLD_len, code, info->reglist.num_regs - 1, 0); - return NULL; + return TRUE; } /* Insert Rt and opcode fields for a register list operand, e.g. Vt in AdvSIMD load/store instructions. */ -const char * +bfd_boolean aarch64_ins_ldst_reglist (const aarch64_operand *self ATTRIBUTE_UNUSED, const aarch64_opnd_info *info, aarch64_insn *code, - const aarch64_inst *inst) + const aarch64_inst *inst, + aarch64_operand_error *errors ATTRIBUTE_UNUSED) { aarch64_insn value = 0; /* Number of elements in each structure to be loaded/stored. */ @@ -229,15 +233,16 @@ aarch64_ins_ldst_reglist (const aarch64_operand *self ATTRIBUTE_UNUSED, } insert_field (FLD_opcode, code, value, 0); - return NULL; + return TRUE; } /* Insert Rt and S fields for a register list operand, e.g. Vt in AdvSIMD load single structure to all lanes instructions. */ -const char * +bfd_boolean aarch64_ins_ldst_reglist_r (const aarch64_operand *self ATTRIBUTE_UNUSED, const aarch64_opnd_info *info, aarch64_insn *code, - const aarch64_inst *inst) + const aarch64_inst *inst, + aarch64_operand_error *errors ATTRIBUTE_UNUSED) { aarch64_insn value; /* The opcode dependent area stores the number of elements in @@ -254,15 +259,16 @@ aarch64_ins_ldst_reglist_r (const aarch64_operand *self ATTRIBUTE_UNUSED, value = (aarch64_insn) 1; insert_field (FLD_S, code, value, 0); - return NULL; + return TRUE; } /* Insert Q, opcode<2:1>, S, size and Rt fields for a register element list operand e.g. Vt in AdvSIMD load/store single element instructions. */ -const char * +bfd_boolean aarch64_ins_ldst_elemlist (const aarch64_operand *self ATTRIBUTE_UNUSED, const aarch64_opnd_info *info, aarch64_insn *code, - const aarch64_inst *inst ATTRIBUTE_UNUSED) + const aarch64_inst *inst ATTRIBUTE_UNUSED, + aarch64_operand_error *errors ATTRIBUTE_UNUSED) { aarch64_field field = {0, 0}; aarch64_insn QSsize = 0; /* fields Q:S:size. */ @@ -302,16 +308,17 @@ aarch64_ins_ldst_elemlist (const aarch64_operand *self ATTRIBUTE_UNUSED, gen_sub_field (FLD_asisdlso_opcode, 1, 2, &field); insert_field_2 (&field, code, opcodeh2, 0); - return NULL; + return TRUE; } /* Insert fields immh:immb and/or Q for e.g. the shift immediate in SSHR ., ., # or SSHR , , #. */ -const char * +bfd_boolean aarch64_ins_advsimd_imm_shift (const aarch64_operand *self ATTRIBUTE_UNUSED, const aarch64_opnd_info *info, - aarch64_insn *code, const aarch64_inst *inst) + aarch64_insn *code, const aarch64_inst *inst, + aarch64_operand_error *errors ATTRIBUTE_UNUSED) { unsigned val = aarch64_get_qualifier_standard_value (info->qualifier); aarch64_insn Q, imm; @@ -357,15 +364,16 @@ aarch64_ins_advsimd_imm_shift (const aarch64_operand *self ATTRIBUTE_UNUSED, imm = info->imm.value + (8 << (unsigned)val); insert_fields (code, imm, 0, 2, FLD_immb, FLD_immh); - return NULL; + return TRUE; } /* Insert fields for e.g. the immediate operands in BFM , , #, #. */ -const char * +bfd_boolean aarch64_ins_imm (const aarch64_operand *self, const aarch64_opnd_info *info, aarch64_insn *code, - const aarch64_inst *inst ATTRIBUTE_UNUSED) + const aarch64_inst *inst ATTRIBUTE_UNUSED, + aarch64_operand_error *errors ATTRIBUTE_UNUSED) { int64_t imm; @@ -373,29 +381,32 @@ aarch64_ins_imm (const aarch64_operand *self, const aarch64_opnd_info *info, if (operand_need_shift_by_two (self)) imm >>= 2; insert_all_fields (self, code, imm); - return NULL; + return TRUE; } /* Insert immediate and its shift amount for e.g. the last operand in MOVZ , #{, LSL #}. */ -const char * +bfd_boolean aarch64_ins_imm_half (const aarch64_operand *self, const aarch64_opnd_info *info, - aarch64_insn *code, const aarch64_inst *inst) + aarch64_insn *code, const aarch64_inst *inst, + aarch64_operand_error *errors) { /* imm16 */ - aarch64_ins_imm (self, info, code, inst); + aarch64_ins_imm (self, info, code, inst, errors); /* hw */ insert_field (FLD_hw, code, info->shifter.amount >> 4, 0); - return NULL; + return TRUE; } /* Insert cmode and "a:b:c:d:e:f:g:h" fields for e.g. the last operand in MOVI ., # {, LSL #}. */ -const char * +bfd_boolean aarch64_ins_advsimd_imm_modified (const aarch64_operand *self ATTRIBUTE_UNUSED, const aarch64_opnd_info *info, aarch64_insn *code, - const aarch64_inst *inst ATTRIBUTE_UNUSED) + const aarch64_inst *inst ATTRIBUTE_UNUSED, + aarch64_operand_error *errors + ATTRIBUTE_UNUSED) { enum aarch64_opnd_qualifier opnd0_qualifier = inst->operands[0].qualifier; uint64_t imm = info->imm.value; @@ -417,7 +428,7 @@ aarch64_ins_advsimd_imm_modified (const aarch64_operand *self ATTRIBUTE_UNUSED, insert_fields (code, imm, 0, 2, FLD_defgh, FLD_abc); if (kind == AARCH64_MOD_NONE) - return NULL; + return TRUE; /* shift amount partially in cmode */ assert (kind == AARCH64_MOD_LSL || kind == AARCH64_MOD_MSL); @@ -429,7 +440,7 @@ aarch64_ins_advsimd_imm_modified (const aarch64_operand *self ATTRIBUTE_UNUSED, /* For 8-bit move immediate, the optional LSL #0 does not require encoding. */ if (esize == 1) - return NULL; + return TRUE; amount >>= 3; if (esize == 4) gen_sub_field (FLD_cmode, 1, 2, &field); /* per word */ @@ -444,74 +455,80 @@ aarch64_ins_advsimd_imm_modified (const aarch64_operand *self ATTRIBUTE_UNUSED, } insert_field_2 (&field, code, amount, 0); - return NULL; + return TRUE; } /* Insert fields for an 8-bit floating-point immediate. */ -const char * +bfd_boolean aarch64_ins_fpimm (const aarch64_operand *self, const aarch64_opnd_info *info, aarch64_insn *code, - const aarch64_inst *inst ATTRIBUTE_UNUSED) + const aarch64_inst *inst ATTRIBUTE_UNUSED, + aarch64_operand_error *errors ATTRIBUTE_UNUSED) { insert_all_fields (self, code, info->imm.value); - return NULL; + return TRUE; } /* Insert 1-bit rotation immediate (#90 or #270). */ -const char * +bfd_boolean aarch64_ins_imm_rotate1 (const aarch64_operand *self, const aarch64_opnd_info *info, - aarch64_insn *code, const aarch64_inst *inst) + aarch64_insn *code, const aarch64_inst *inst, + aarch64_operand_error *errors ATTRIBUTE_UNUSED) { uint64_t rot = (info->imm.value - 90) / 180; assert (rot < 2U); insert_field (self->fields[0], code, rot, inst->opcode->mask); - return NULL; + return TRUE; } /* Insert 2-bit rotation immediate (#0, #90, #180 or #270). */ -const char * +bfd_boolean aarch64_ins_imm_rotate2 (const aarch64_operand *self, const aarch64_opnd_info *info, - aarch64_insn *code, const aarch64_inst *inst) + aarch64_insn *code, const aarch64_inst *inst, + aarch64_operand_error *errors ATTRIBUTE_UNUSED) { uint64_t rot = info->imm.value / 90; assert (rot < 4U); insert_field (self->fields[0], code, rot, inst->opcode->mask); - return NULL; + return TRUE; } /* Insert # for the immediate operand in fp fix-point instructions, e.g. SCVTF
, , #. */ -const char * +bfd_boolean aarch64_ins_fbits (const aarch64_operand *self, const aarch64_opnd_info *info, aarch64_insn *code, - const aarch64_inst *inst ATTRIBUTE_UNUSED) + const aarch64_inst *inst ATTRIBUTE_UNUSED, + aarch64_operand_error *errors ATTRIBUTE_UNUSED) { insert_field (self->fields[0], code, 64 - info->imm.value, 0); - return NULL; + return TRUE; } /* Insert arithmetic immediate for e.g. the last operand in SUBS , , # {, }. */ -const char * +bfd_boolean aarch64_ins_aimm (const aarch64_operand *self, const aarch64_opnd_info *info, - aarch64_insn *code, const aarch64_inst *inst ATTRIBUTE_UNUSED) + aarch64_insn *code, const aarch64_inst *inst ATTRIBUTE_UNUSED, + aarch64_operand_error *errors ATTRIBUTE_UNUSED) { /* shift */ aarch64_insn value = info->shifter.amount ? 1 : 0; insert_field (self->fields[0], code, value, 0); /* imm12 (unsigned) */ insert_field (self->fields[1], code, info->imm.value, 0); - return NULL; + return TRUE; } /* Common routine shared by aarch64_ins{,_inv}_limm. INVERT_P says whether the operand should be inverted before encoding. */ -static const char * +static bfd_boolean aarch64_ins_limm_1 (const aarch64_operand *self, const aarch64_opnd_info *info, aarch64_insn *code, - const aarch64_inst *inst, bfd_boolean invert_p) + const aarch64_inst *inst, bfd_boolean invert_p, + aarch64_operand_error *errors ATTRIBUTE_UNUSED) { aarch64_insn value; uint64_t imm = info->imm.value; @@ -524,40 +541,43 @@ aarch64_ins_limm_1 (const aarch64_operand *self, insert_fields (code, value, 0, 3, self->fields[2], self->fields[1], self->fields[0]); - return NULL; + return TRUE; } /* Insert logical/bitmask immediate for e.g. the last operand in ORR , , #. */ -const char * +bfd_boolean aarch64_ins_limm (const aarch64_operand *self, const aarch64_opnd_info *info, - aarch64_insn *code, const aarch64_inst *inst) + aarch64_insn *code, const aarch64_inst *inst, + aarch64_operand_error *errors ATTRIBUTE_UNUSED) { return aarch64_ins_limm_1 (self, info, code, inst, - inst->opcode->op == OP_BIC); + inst->opcode->op == OP_BIC, errors); } /* Insert a logical/bitmask immediate for the BIC alias of AND (etc.). */ -const char * +bfd_boolean aarch64_ins_inv_limm (const aarch64_operand *self, const aarch64_opnd_info *info, aarch64_insn *code, - const aarch64_inst *inst) + const aarch64_inst *inst, + aarch64_operand_error *errors ATTRIBUTE_UNUSED) { - return aarch64_ins_limm_1 (self, info, code, inst, TRUE); + return aarch64_ins_limm_1 (self, info, code, inst, TRUE, errors); } /* Encode Ft for e.g. STR , [, {, {}}] or LDP , , [], #. */ -const char * +bfd_boolean aarch64_ins_ft (const aarch64_operand *self, const aarch64_opnd_info *info, - aarch64_insn *code, const aarch64_inst *inst) + aarch64_insn *code, const aarch64_inst *inst, + aarch64_operand_error *errors) { aarch64_insn value = 0; assert (info->idx == 0); /* Rt */ - aarch64_ins_regno (self, info, code, inst); + aarch64_ins_regno (self, info, code, inst, errors); if (inst->opcode->iclass == ldstpair_indexed || inst->opcode->iclass == ldstnapair_offs || inst->opcode->iclass == ldstpair_off @@ -580,26 +600,28 @@ aarch64_ins_ft (const aarch64_operand *self, const aarch64_opnd_info *info, insert_fields (code, value, 0, 2, FLD_ldst_size, FLD_opc1); } - return NULL; + return TRUE; } /* Encode the address operand for e.g. STXRB , , [{,#0}]. */ -const char * +bfd_boolean aarch64_ins_addr_simple (const aarch64_operand *self ATTRIBUTE_UNUSED, const aarch64_opnd_info *info, aarch64_insn *code, - const aarch64_inst *inst ATTRIBUTE_UNUSED) + const aarch64_inst *inst ATTRIBUTE_UNUSED, + aarch64_operand_error *errors ATTRIBUTE_UNUSED) { /* Rn */ insert_field (FLD_Rn, code, info->addr.base_regno, 0); - return NULL; + return TRUE; } /* Encode the address operand for e.g. STR , [, {, {}}]. */ -const char * +bfd_boolean aarch64_ins_addr_regoff (const aarch64_operand *self ATTRIBUTE_UNUSED, const aarch64_opnd_info *info, aarch64_insn *code, - const aarch64_inst *inst ATTRIBUTE_UNUSED) + const aarch64_inst *inst ATTRIBUTE_UNUSED, + aarch64_operand_error *errors ATTRIBUTE_UNUSED) { aarch64_insn S; enum aarch64_modifier_kind kind = info->shifter.kind; @@ -624,15 +646,16 @@ aarch64_ins_addr_regoff (const aarch64_operand *self ATTRIBUTE_UNUSED, S = info->shifter.operator_present && info->shifter.amount_present; insert_field (FLD_S, code, S, 0); - return NULL; + return TRUE; } /* Encode the address operand for e.g. stlur , [{, }]. */ -const char * +bfd_boolean aarch64_ins_addr_offset (const aarch64_operand *self ATTRIBUTE_UNUSED, const aarch64_opnd_info *info, aarch64_insn *code, - const aarch64_inst *inst ATTRIBUTE_UNUSED) + const aarch64_inst *inst ATTRIBUTE_UNUSED, + aarch64_operand_error *errors ATTRIBUTE_UNUSED) { /* Rn */ insert_field (self->fields[0], code, info->addr.base_regno, 0); @@ -647,15 +670,16 @@ aarch64_ins_addr_offset (const aarch64_operand *self ATTRIBUTE_UNUSED, assert (info->addr.preind == 1 && info->addr.postind == 0); insert_field (self->fields[2], code, 1, 0); } - return NULL; + return TRUE; } /* Encode the address operand for e.g. LDRSW , [, #]!. */ -const char * +bfd_boolean aarch64_ins_addr_simm (const aarch64_operand *self, const aarch64_opnd_info *info, aarch64_insn *code, - const aarch64_inst *inst ATTRIBUTE_UNUSED) + const aarch64_inst *inst ATTRIBUTE_UNUSED, + aarch64_operand_error *errors ATTRIBUTE_UNUSED) { int imm; @@ -679,15 +703,16 @@ aarch64_ins_addr_simm (const aarch64_operand *self, insert_field (self->fields[1], code, 1, 0); } - return NULL; + return TRUE; } /* Encode the address operand for e.g. LDRAA , [{, #}]. */ -const char * +bfd_boolean aarch64_ins_addr_simm10 (const aarch64_operand *self, const aarch64_opnd_info *info, aarch64_insn *code, - const aarch64_inst *inst ATTRIBUTE_UNUSED) + const aarch64_inst *inst ATTRIBUTE_UNUSED, + aarch64_operand_error *errors ATTRIBUTE_UNUSED) { int imm; @@ -703,15 +728,16 @@ aarch64_ins_addr_simm10 (const aarch64_operand *self, assert (info->addr.preind == 1 && info->addr.postind == 0); insert_field (self->fields[3], code, 1, 0); } - return NULL; + return TRUE; } /* Encode the address operand for e.g. LDRSW , [{, #}]. */ -const char * +bfd_boolean aarch64_ins_addr_uimm12 (const aarch64_operand *self, const aarch64_opnd_info *info, aarch64_insn *code, - const aarch64_inst *inst ATTRIBUTE_UNUSED) + const aarch64_inst *inst ATTRIBUTE_UNUSED, + aarch64_operand_error *errors ATTRIBUTE_UNUSED) { int shift = get_logsz (aarch64_get_qualifier_esize (info->qualifier)); @@ -719,15 +745,16 @@ aarch64_ins_addr_uimm12 (const aarch64_operand *self, insert_field (self->fields[0], code, info->addr.base_regno, 0); /* uimm12 */ insert_field (self->fields[1], code,info->addr.offset.imm >> shift, 0); - return NULL; + return TRUE; } /* Encode the address operand for e.g. LD1 {., ., .}, [], >. */ -const char * +bfd_boolean aarch64_ins_simd_addr_post (const aarch64_operand *self ATTRIBUTE_UNUSED, const aarch64_opnd_info *info, aarch64_insn *code, - const aarch64_inst *inst ATTRIBUTE_UNUSED) + const aarch64_inst *inst ATTRIBUTE_UNUSED, + aarch64_operand_error *errors ATTRIBUTE_UNUSED) { /* Rn */ insert_field (FLD_Rn, code, info->addr.base_regno, 0); @@ -736,100 +763,108 @@ aarch64_ins_simd_addr_post (const aarch64_operand *self ATTRIBUTE_UNUSED, insert_field (FLD_Rm, code, info->addr.offset.regno, 0); else insert_field (FLD_Rm, code, 0x1f, 0); - return NULL; + return TRUE; } /* Encode the condition operand for e.g. CSEL , , , . */ -const char * +bfd_boolean aarch64_ins_cond (const aarch64_operand *self ATTRIBUTE_UNUSED, const aarch64_opnd_info *info, aarch64_insn *code, - const aarch64_inst *inst ATTRIBUTE_UNUSED) + const aarch64_inst *inst ATTRIBUTE_UNUSED, + aarch64_operand_error *errors ATTRIBUTE_UNUSED) { /* cond */ insert_field (FLD_cond, code, info->cond->value, 0); - return NULL; + return TRUE; } /* Encode the system register operand for e.g. MRS , . */ -const char * +bfd_boolean aarch64_ins_sysreg (const aarch64_operand *self ATTRIBUTE_UNUSED, const aarch64_opnd_info *info, aarch64_insn *code, - const aarch64_inst *inst ATTRIBUTE_UNUSED) + const aarch64_inst *inst, + aarch64_operand_error *detail ATTRIBUTE_UNUSED) { /* op0:op1:CRn:CRm:op2 */ - insert_fields (code, info->sysreg, inst->opcode->mask, 5, + insert_fields (code, info->sysreg.value, inst->opcode->mask, 5, FLD_op2, FLD_CRm, FLD_CRn, FLD_op1, FLD_op0); - return NULL; + return TRUE; } /* Encode the PSTATE field operand for e.g. MSR , #. */ -const char * +bfd_boolean aarch64_ins_pstatefield (const aarch64_operand *self ATTRIBUTE_UNUSED, const aarch64_opnd_info *info, aarch64_insn *code, - const aarch64_inst *inst ATTRIBUTE_UNUSED) + const aarch64_inst *inst ATTRIBUTE_UNUSED, + aarch64_operand_error *errors ATTRIBUTE_UNUSED) { /* op1:op2 */ insert_fields (code, info->pstatefield, inst->opcode->mask, 2, FLD_op2, FLD_op1); - return NULL; + return TRUE; } /* Encode the system instruction op operand for e.g. AT , . */ -const char * +bfd_boolean aarch64_ins_sysins_op (const aarch64_operand *self ATTRIBUTE_UNUSED, const aarch64_opnd_info *info, aarch64_insn *code, - const aarch64_inst *inst ATTRIBUTE_UNUSED) + const aarch64_inst *inst ATTRIBUTE_UNUSED, + aarch64_operand_error *errors ATTRIBUTE_UNUSED) { /* op1:CRn:CRm:op2 */ insert_fields (code, info->sysins_op->value, inst->opcode->mask, 4, FLD_op2, FLD_CRm, FLD_CRn, FLD_op1); - return NULL; + return TRUE; } /* Encode the memory barrier option operand for e.g. DMB
, , #. */ -int +bfd_boolean aarch64_ext_fbits (const aarch64_operand *self ATTRIBUTE_UNUSED, aarch64_opnd_info *info, const aarch64_insn code, - const aarch64_inst *inst ATTRIBUTE_UNUSED) + const aarch64_inst *inst ATTRIBUTE_UNUSED, + aarch64_operand_error *errors ATTRIBUTE_UNUSED) { info->imm.value = 64- extract_field (FLD_scale, code, 0); - return 1; + return TRUE; } /* Decode arithmetic immediate for e.g. SUBS , , # {, }. */ -int +bfd_boolean aarch64_ext_aimm (const aarch64_operand *self ATTRIBUTE_UNUSED, aarch64_opnd_info *info, const aarch64_insn code, - const aarch64_inst *inst ATTRIBUTE_UNUSED) + const aarch64_inst *inst ATTRIBUTE_UNUSED, + aarch64_operand_error *errors ATTRIBUTE_UNUSED) { aarch64_insn value; @@ -781,18 +799,18 @@ aarch64_ext_aimm (const aarch64_operand *self ATTRIBUTE_UNUSED, /* shift */ value = extract_field (FLD_shift, code, 0); if (value >= 2) - return 0; + return FALSE; info->shifter.amount = value ? 12 : 0; /* imm12 (unsigned) */ info->imm.value = extract_field (FLD_imm12, code, 0); - return 1; + return TRUE; } /* Return true if VALUE is a valid logical immediate encoding, storing the decoded value in *RESULT if so. ESIZE is the number of bytes in the decoded immediate. */ -static int +static bfd_boolean decode_limm (uint32_t esize, aarch64_insn value, int64_t *result) { uint64_t imm, mask; @@ -820,7 +838,7 @@ decode_limm (uint32_t esize, aarch64_insn value, int64_t *result) case 0x30 ... 0x37: /* 110xxx */ simd_size = 8; S &= 0x7; break; case 0x38 ... 0x3b: /* 1110xx */ simd_size = 4; S &= 0x3; break; case 0x3c ... 0x3d: /* 11110x */ simd_size = 2; S &= 0x1; break; - default: return 0; + default: return FALSE; } mask = (1ull << simd_size) - 1; /* Top bits are IGNORED. */ @@ -828,11 +846,11 @@ decode_limm (uint32_t esize, aarch64_insn value, int64_t *result) } if (simd_size > esize * 8) - return 0; + return FALSE; /* NOTE: if S = simd_size - 1 we get 0xf..f which is rejected. */ if (S == simd_size - 1) - return 0; + return FALSE; /* S+1 consecutive bits to 1. */ /* NOTE: S can't be 63 due to detection above. */ imm = (1ull << (S + 1)) - 1; @@ -858,14 +876,15 @@ decode_limm (uint32_t esize, aarch64_insn value, int64_t *result) *result = imm & ~((uint64_t) -1 << (esize * 4) << (esize * 4)); - return 1; + return TRUE; } /* Decode a logical immediate for e.g. ORR , , #. */ -int +bfd_boolean aarch64_ext_limm (const aarch64_operand *self, aarch64_opnd_info *info, const aarch64_insn code, - const aarch64_inst *inst) + const aarch64_inst *inst, + aarch64_operand_error *errors ATTRIBUTE_UNUSED) { uint32_t esize; aarch64_insn value; @@ -877,23 +896,25 @@ aarch64_ext_limm (const aarch64_operand *self, } /* Decode a logical immediate for the BIC alias of AND (etc.). */ -int +bfd_boolean aarch64_ext_inv_limm (const aarch64_operand *self, aarch64_opnd_info *info, const aarch64_insn code, - const aarch64_inst *inst) + const aarch64_inst *inst, + aarch64_operand_error *errors) { - if (!aarch64_ext_limm (self, info, code, inst)) - return 0; + if (!aarch64_ext_limm (self, info, code, inst, errors)) + return FALSE; info->imm.value = ~info->imm.value; - return 1; + return TRUE; } /* Decode Ft for e.g. STR , [, {, {}}] or LDP , , [], #. */ -int +bfd_boolean aarch64_ext_ft (const aarch64_operand *self ATTRIBUTE_UNUSED, aarch64_opnd_info *info, - const aarch64_insn code, const aarch64_inst *inst) + const aarch64_insn code, const aarch64_inst *inst, + aarch64_operand_error *errors ATTRIBUTE_UNUSED) { aarch64_insn value; @@ -913,7 +934,7 @@ aarch64_ext_ft (const aarch64_operand *self ATTRIBUTE_UNUSED, case 0: qualifier = AARCH64_OPND_QLF_S_S; break; case 1: qualifier = AARCH64_OPND_QLF_S_D; break; case 2: qualifier = AARCH64_OPND_QLF_S_Q; break; - default: return 0; + default: return FALSE; } info->qualifier = qualifier; } @@ -922,31 +943,33 @@ aarch64_ext_ft (const aarch64_operand *self ATTRIBUTE_UNUSED, /* opc1:size */ value = extract_fields (code, 0, 2, FLD_opc1, FLD_ldst_size); if (value > 0x4) - return 0; + return FALSE; info->qualifier = get_sreg_qualifier_from_value (value); } - return 1; + return TRUE; } /* Decode the address operand for e.g. STXRB , , [{,#0}]. */ -int +bfd_boolean aarch64_ext_addr_simple (const aarch64_operand *self ATTRIBUTE_UNUSED, aarch64_opnd_info *info, aarch64_insn code, - const aarch64_inst *inst ATTRIBUTE_UNUSED) + const aarch64_inst *inst ATTRIBUTE_UNUSED, + aarch64_operand_error *errors ATTRIBUTE_UNUSED) { /* Rn */ info->addr.base_regno = extract_field (FLD_Rn, code, 0); - return 1; + return TRUE; } /* Decode the address operand for e.g. stlur , [{, }]. */ -int +bfd_boolean aarch64_ext_addr_offset (const aarch64_operand *self ATTRIBUTE_UNUSED, aarch64_opnd_info *info, - aarch64_insn code, const aarch64_inst *inst) + aarch64_insn code, const aarch64_inst *inst, + aarch64_operand_error *errors ATTRIBUTE_UNUSED) { info->qualifier = get_expected_qualifier (inst, info->idx); @@ -960,15 +983,16 @@ aarch64_ext_addr_offset (const aarch64_operand *self ATTRIBUTE_UNUSED, info->addr.writeback = 1; info->addr.preind = 1; } - return 1; + return TRUE; } /* Decode the address operand for e.g. STR , [, {, {}}]. */ -int +bfd_boolean aarch64_ext_addr_regoff (const aarch64_operand *self ATTRIBUTE_UNUSED, aarch64_opnd_info *info, - aarch64_insn code, const aarch64_inst *inst) + aarch64_insn code, const aarch64_inst *inst, + aarch64_operand_error *errors ATTRIBUTE_UNUSED) { aarch64_insn S, value; @@ -1004,13 +1028,14 @@ aarch64_ext_addr_regoff (const aarch64_operand *self ATTRIBUTE_UNUSED, info->shifter.amount_present = 1; } - return 1; + return TRUE; } /* Decode the address operand for e.g. LDRSW , [], #. */ -int +bfd_boolean aarch64_ext_addr_simm (const aarch64_operand *self, aarch64_opnd_info *info, - aarch64_insn code, const aarch64_inst *inst) + aarch64_insn code, const aarch64_inst *inst, + aarch64_operand_error *errors ATTRIBUTE_UNUSED) { aarch64_insn imm; info->qualifier = get_expected_qualifier (inst, info->idx); @@ -1039,14 +1064,15 @@ aarch64_ext_addr_simm (const aarch64_operand *self, aarch64_opnd_info *info, info->addr.postind = 1; } - return 1; + return TRUE; } /* Decode the address operand for e.g. LDRSW , [{, #}]. */ -int +bfd_boolean aarch64_ext_addr_uimm12 (const aarch64_operand *self, aarch64_opnd_info *info, aarch64_insn code, - const aarch64_inst *inst ATTRIBUTE_UNUSED) + const aarch64_inst *inst ATTRIBUTE_UNUSED, + aarch64_operand_error *errors ATTRIBUTE_UNUSED) { int shift; info->qualifier = get_expected_qualifier (inst, info->idx); @@ -1055,14 +1081,15 @@ aarch64_ext_addr_uimm12 (const aarch64_operand *self, aarch64_opnd_info *info, info->addr.base_regno = extract_field (self->fields[0], code, 0); /* uimm12 */ info->addr.offset.imm = extract_field (self->fields[1], code, 0) << shift; - return 1; + return TRUE; } /* Decode the address operand for e.g. LDRAA , [{, #}]. */ -int +bfd_boolean aarch64_ext_addr_simm10 (const aarch64_operand *self, aarch64_opnd_info *info, aarch64_insn code, - const aarch64_inst *inst ATTRIBUTE_UNUSED) + const aarch64_inst *inst ATTRIBUTE_UNUSED, + aarch64_operand_error *errors ATTRIBUTE_UNUSED) { aarch64_insn imm; @@ -1076,15 +1103,16 @@ aarch64_ext_addr_simm10 (const aarch64_operand *self, aarch64_opnd_info *info, info->addr.writeback = 1; info->addr.preind = 1; } - return 1; + return TRUE; } /* Decode the address operand for e.g. LD1 {., ., .}, [], >. */ -int +bfd_boolean aarch64_ext_simd_addr_post (const aarch64_operand *self ATTRIBUTE_UNUSED, aarch64_opnd_info *info, - aarch64_insn code, const aarch64_inst *inst) + aarch64_insn code, const aarch64_inst *inst, + aarch64_operand_error *errors ATTRIBUTE_UNUSED) { /* The opcode dependent area stores the number of elements in each structure to be loaded/stored. */ @@ -1110,57 +1138,61 @@ aarch64_ext_simd_addr_post (const aarch64_operand *self ATTRIBUTE_UNUSED, info->addr.offset.is_reg = 1; info->addr.writeback = 1; - return 1; + return TRUE; } /* Decode the condition operand for e.g. CSEL , , , . */ -int +bfd_boolean aarch64_ext_cond (const aarch64_operand *self ATTRIBUTE_UNUSED, aarch64_opnd_info *info, - aarch64_insn code, const aarch64_inst *inst ATTRIBUTE_UNUSED) + aarch64_insn code, const aarch64_inst *inst ATTRIBUTE_UNUSED, + aarch64_operand_error *errors ATTRIBUTE_UNUSED) { aarch64_insn value; /* cond */ value = extract_field (FLD_cond, code, 0); info->cond = get_cond_from_value (value); - return 1; + return TRUE; } /* Decode the system register operand for e.g. MRS , . */ -int +bfd_boolean aarch64_ext_sysreg (const aarch64_operand *self ATTRIBUTE_UNUSED, aarch64_opnd_info *info, aarch64_insn code, - const aarch64_inst *inst ATTRIBUTE_UNUSED) + const aarch64_inst *inst ATTRIBUTE_UNUSED, + aarch64_operand_error *errors ATTRIBUTE_UNUSED) { /* op0:op1:CRn:CRm:op2 */ - info->sysreg = extract_fields (code, 0, 5, FLD_op0, FLD_op1, FLD_CRn, - FLD_CRm, FLD_op2); + info->sysreg.value = extract_fields (code, 0, 5, FLD_op0, FLD_op1, FLD_CRn, + FLD_CRm, FLD_op2); return 1; } /* Decode the PSTATE field operand for e.g. MSR , #. */ -int +bfd_boolean aarch64_ext_pstatefield (const aarch64_operand *self ATTRIBUTE_UNUSED, aarch64_opnd_info *info, aarch64_insn code, - const aarch64_inst *inst ATTRIBUTE_UNUSED) + const aarch64_inst *inst ATTRIBUTE_UNUSED, + aarch64_operand_error *errors ATTRIBUTE_UNUSED) { int i; /* op1:op2 */ info->pstatefield = extract_fields (code, 0, 2, FLD_op1, FLD_op2); for (i = 0; aarch64_pstatefields[i].name != NULL; ++i) if (aarch64_pstatefields[i].value == (aarch64_insn)info->pstatefield) - return 1; + return TRUE; /* Reserved value in . */ - return 0; + return FALSE; } /* Decode the system instruction op operand for e.g. AT , . */ -int +bfd_boolean aarch64_ext_sysins_op (const aarch64_operand *self ATTRIBUTE_UNUSED, aarch64_opnd_info *info, aarch64_insn code, - const aarch64_inst *inst ATTRIBUTE_UNUSED) + const aarch64_inst *inst ATTRIBUTE_UNUSED, + aarch64_operand_error *errors ATTRIBUTE_UNUSED) { int i; aarch64_insn value; @@ -1176,7 +1208,7 @@ aarch64_ext_sysins_op (const aarch64_operand *self ATTRIBUTE_UNUSED, case AARCH64_OPND_SYSREG_DC: sysins_ops = aarch64_sys_regs_dc; break; case AARCH64_OPND_SYSREG_IC: sysins_ops = aarch64_sys_regs_ic; break; case AARCH64_OPND_SYSREG_TLBI: sysins_ops = aarch64_sys_regs_tlbi; break; - default: assert (0); return 0; + default: assert (0); return FALSE; } for (i = 0; sysins_ops[i].name != NULL; ++i) @@ -1187,46 +1219,49 @@ aarch64_ext_sysins_op (const aarch64_operand *self ATTRIBUTE_UNUSED, info->sysins_op->name, (unsigned)info->sysins_op->value, aarch64_sys_ins_reg_has_xt (info->sysins_op), i); - return 1; + return TRUE; } - return 0; + return FALSE; } /* Decode the memory barrier option operand for e.g. DMB