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Fix the cast used to prevent compile time warning about an always false test.
[deliverable/binutils-gdb.git] / bfd / coff-sh.c
CommitLineData
c2dcd04e 1/* BFD back-end for Renesas Super-H COFF binaries.
b3adc24a 2 Copyright (C) 1993-2020 Free Software Foundation, Inc.
252b5132
RH		 3 Contributed by Cygnus Support.
4 Written by Steve Chamberlain, <sac@cygnus.com>.
5 Relaxing code written by Ian Lance Taylor, <ian@cygnus.com>.
6
c2dcd04e 7 This file is part of BFD, the Binary File Descriptor library.
252b5132 8
c2dcd04e
NC		 9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
cd123cb7 11 the Free Software Foundation; either version 3 of the License, or
c2dcd04e 12 (at your option) any later version.
252b5132 13
c2dcd04e
NC		 14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
252b5132 18
c2dcd04e
NC		 19 You should have received a copy of the GNU General Public License
20 along with this program; if not, write to the Free Software
cd123cb7
NC		 21 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
22 MA 02110-1301, USA. */
252b5132 23
252b5132 24#include "sysdep.h"
3db64b00 25#include "bfd.h"
993e9275 26#include "libiberty.h"
252b5132
RH		 27#include "libbfd.h"
28#include "bfdlink.h"
29#include "coff/sh.h"
30#include "coff/internal.h"
17505c5c 31
799c00e0
NC		 32#undef bfd_pe_print_pdata
33
17505c5c
NC		 34#ifdef COFF_WITH_PE
35#include "coff/pe.h"
86033394
NC		 36
37#ifndef COFF_IMAGE_WITH_PE
b34976b6 38static bfd_boolean sh_align_load_span
2c3fc389
NC		 39 (bfd *, asection *, bfd_byte *,
40 bfd_boolean (*) (bfd *, asection *, void *, bfd_byte *, bfd_vma),
41 void *, bfd_vma **, bfd_vma *, bfd_vma, bfd_vma, bfd_boolean *);
86033394
NC		 42
43#define _bfd_sh_align_load_span sh_align_load_span
44#endif
17505c5c 45
799c00e0
NC		 46#define bfd_pe_print_pdata _bfd_pe_print_ce_compressed_pdata
47
48#else
49
50#define bfd_pe_print_pdata NULL
51
52#endif /* COFF_WITH_PE. */
2b5c217d 53
252b5132
RH		 54#include "libcoff.h"
55
56/* Internal functions. */
252b5132 57
17505c5c
NC		 58#ifdef COFF_WITH_PE
59/* Can't build import tables with 2**4 alignment. */
60#define COFF_DEFAULT_SECTION_ALIGNMENT_POWER 2
61#else
252b5132 62/* Default section alignment to 2**4. */
17505c5c
NC		 63#define COFF_DEFAULT_SECTION_ALIGNMENT_POWER 4
64#endif
65
66#ifdef COFF_IMAGE_WITH_PE
67/* Align PE executables. */
68#define COFF_PAGE_SIZE 0x1000
69#endif
252b5132
RH		 70
71/* Generate long file names. */
72#define COFF_LONG_FILENAMES
73
17505c5c 74#ifdef COFF_WITH_PE
b34976b6 75/* Return TRUE if this relocation should
17505c5c 76 appear in the output .reloc section. */
2c3fc389
NC		 77
78static bfd_boolean
79in_reloc_p (bfd * abfd ATTRIBUTE_UNUSED,
80 reloc_howto_type * howto)
17505c5c
NC		 81{
82 return ! howto->pc_relative && howto->type != R_SH_IMAGEBASE;
cbfe05c4 83}
17505c5c
NC		 84#endif
85
2c3fc389
NC		 86static bfd_reloc_status_type
87sh_reloc (bfd *, arelent *, asymbol *, void *, asection *, bfd *, char **);
88static bfd_boolean
89sh_relocate_section (bfd *, struct bfd_link_info *, bfd *, asection *,
90 bfd_byte *, struct internal_reloc *,
91 struct internal_syment *, asection **);
92static bfd_boolean
93sh_align_loads (bfd *, asection *, struct internal_reloc *,
94 bfd_byte *, bfd_boolean *);
95
252b5132
RH		 96/* The supported relocations. There are a lot of relocations defined
97 in coff/internal.h which we do not expect to ever see. */
98static reloc_howto_type sh_coff_howtos[] =
99{
5f771d47
ILT		 100 EMPTY_HOWTO (0),
101 EMPTY_HOWTO (1),
17505c5c
NC		 102#ifdef COFF_WITH_PE
103 /* Windows CE */
104 HOWTO (R_SH_IMM32CE, /* type */
105 0, /* rightshift */
106 2, /* size (0 = byte, 1 = short, 2 = long) */
107 32, /* bitsize */
b34976b6 108 FALSE, /* pc_relative */
17505c5c
NC		 109 0, /* bitpos */
110 complain_overflow_bitfield, /* complain_on_overflow */
111 sh_reloc, /* special_function */
112 "r_imm32ce", /* name */
b34976b6 113 TRUE, /* partial_inplace */
17505c5c
NC		 114 0xffffffff, /* src_mask */
115 0xffffffff, /* dst_mask */
b34976b6 116 FALSE), /* pcrel_offset */
17505c5c 117#else
5f771d47 118 EMPTY_HOWTO (2),
17505c5c 119#endif
5f771d47
ILT		 120 EMPTY_HOWTO (3), /* R_SH_PCREL8 */
121 EMPTY_HOWTO (4), /* R_SH_PCREL16 */
122 EMPTY_HOWTO (5), /* R_SH_HIGH8 */
123 EMPTY_HOWTO (6), /* R_SH_IMM24 */
124 EMPTY_HOWTO (7), /* R_SH_LOW16 */
125 EMPTY_HOWTO (8),
126 EMPTY_HOWTO (9), /* R_SH_PCDISP8BY4 */
252b5132
RH		 127
128 HOWTO (R_SH_PCDISP8BY2, /* type */
129 1, /* rightshift */
130 1, /* size (0 = byte, 1 = short, 2 = long) */
131 8, /* bitsize */
b34976b6 132 TRUE, /* pc_relative */
252b5132
RH		 133 0, /* bitpos */
134 complain_overflow_signed, /* complain_on_overflow */
135 sh_reloc, /* special_function */
136 "r_pcdisp8by2", /* name */
b34976b6 137 TRUE, /* partial_inplace */
252b5132
RH		 138 0xff, /* src_mask */
139 0xff, /* dst_mask */
b34976b6 140 TRUE), /* pcrel_offset */
252b5132 141
5f771d47 142 EMPTY_HOWTO (11), /* R_SH_PCDISP8 */
252b5132
RH		 143
144 HOWTO (R_SH_PCDISP, /* type */
145 1, /* rightshift */
146 1, /* size (0 = byte, 1 = short, 2 = long) */
147 12, /* bitsize */
b34976b6 148 TRUE, /* pc_relative */
252b5132
RH		 149 0, /* bitpos */
150 complain_overflow_signed, /* complain_on_overflow */
151 sh_reloc, /* special_function */
152 "r_pcdisp12by2", /* name */
b34976b6 153 TRUE, /* partial_inplace */
252b5132
RH		 154 0xfff, /* src_mask */
155 0xfff, /* dst_mask */
b34976b6 156 TRUE), /* pcrel_offset */
252b5132 157
5f771d47 158 EMPTY_HOWTO (13),
252b5132
RH		 159
160 HOWTO (R_SH_IMM32, /* type */
161 0, /* rightshift */
162 2, /* size (0 = byte, 1 = short, 2 = long) */
163 32, /* bitsize */
b34976b6 164 FALSE, /* pc_relative */
252b5132
RH		 165 0, /* bitpos */
166 complain_overflow_bitfield, /* complain_on_overflow */
167 sh_reloc, /* special_function */
168 "r_imm32", /* name */
b34976b6 169 TRUE, /* partial_inplace */
252b5132
RH		 170 0xffffffff, /* src_mask */
171 0xffffffff, /* dst_mask */
b34976b6 172 FALSE), /* pcrel_offset */
252b5132 173
5f771d47 174 EMPTY_HOWTO (15),
17505c5c 175#ifdef COFF_WITH_PE
07d6d2b8
AM		 176 HOWTO (R_SH_IMAGEBASE, /* type */
177 0, /* rightshift */
178 2, /* size (0 = byte, 1 = short, 2 = long) */
179 32, /* bitsize */
180 FALSE, /* pc_relative */
181 0, /* bitpos */
17505c5c 182 complain_overflow_bitfield, /* complain_on_overflow */
07d6d2b8
AM		 183 sh_reloc, /* special_function */
184 "rva32", /* name */
185 TRUE, /* partial_inplace */
186 0xffffffff, /* src_mask */
187 0xffffffff, /* dst_mask */
188 FALSE), /* pcrel_offset */
17505c5c 189#else
5f771d47 190 EMPTY_HOWTO (16), /* R_SH_IMM8 */
17505c5c 191#endif
5f771d47
ILT		 192 EMPTY_HOWTO (17), /* R_SH_IMM8BY2 */
193 EMPTY_HOWTO (18), /* R_SH_IMM8BY4 */
194 EMPTY_HOWTO (19), /* R_SH_IMM4 */
195 EMPTY_HOWTO (20), /* R_SH_IMM4BY2 */
196 EMPTY_HOWTO (21), /* R_SH_IMM4BY4 */
252b5132
RH		 197
198 HOWTO (R_SH_PCRELIMM8BY2, /* type */
199 1, /* rightshift */
200 1, /* size (0 = byte, 1 = short, 2 = long) */
201 8, /* bitsize */
b34976b6 202 TRUE, /* pc_relative */
252b5132
RH		 203 0, /* bitpos */
204 complain_overflow_unsigned, /* complain_on_overflow */
205 sh_reloc, /* special_function */
206 "r_pcrelimm8by2", /* name */
b34976b6 207 TRUE, /* partial_inplace */
252b5132
RH		 208 0xff, /* src_mask */
209 0xff, /* dst_mask */
b34976b6 210 TRUE), /* pcrel_offset */
252b5132
RH		 211
212 HOWTO (R_SH_PCRELIMM8BY4, /* type */
213 2, /* rightshift */
214 1, /* size (0 = byte, 1 = short, 2 = long) */
215 8, /* bitsize */
b34976b6 216 TRUE, /* pc_relative */
252b5132
RH		 217 0, /* bitpos */
218 complain_overflow_unsigned, /* complain_on_overflow */
219 sh_reloc, /* special_function */
220 "r_pcrelimm8by4", /* name */
b34976b6 221 TRUE, /* partial_inplace */
252b5132
RH		 222 0xff, /* src_mask */
223 0xff, /* dst_mask */
b34976b6 224 TRUE), /* pcrel_offset */
252b5132
RH		 225
226 HOWTO (R_SH_IMM16, /* type */
227 0, /* rightshift */
228 1, /* size (0 = byte, 1 = short, 2 = long) */
229 16, /* bitsize */
b34976b6 230 FALSE, /* pc_relative */
252b5132
RH		 231 0, /* bitpos */
232 complain_overflow_bitfield, /* complain_on_overflow */
233 sh_reloc, /* special_function */
234 "r_imm16", /* name */
b34976b6 235 TRUE, /* partial_inplace */
252b5132
RH		 236 0xffff, /* src_mask */
237 0xffff, /* dst_mask */
b34976b6 238 FALSE), /* pcrel_offset */
252b5132
RH		 239
240 HOWTO (R_SH_SWITCH16, /* type */
241 0, /* rightshift */
242 1, /* size (0 = byte, 1 = short, 2 = long) */
243 16, /* bitsize */
b34976b6 244 FALSE, /* pc_relative */
252b5132
RH		 245 0, /* bitpos */
246 complain_overflow_bitfield, /* complain_on_overflow */
247 sh_reloc, /* special_function */
248 "r_switch16", /* name */
b34976b6 249 TRUE, /* partial_inplace */
252b5132
RH		 250 0xffff, /* src_mask */
251 0xffff, /* dst_mask */
b34976b6 252 FALSE), /* pcrel_offset */
252b5132
RH		 253
254 HOWTO (R_SH_SWITCH32, /* type */
255 0, /* rightshift */
256 2, /* size (0 = byte, 1 = short, 2 = long) */
257 32, /* bitsize */
b34976b6 258 FALSE, /* pc_relative */
252b5132
RH		 259 0, /* bitpos */
260 complain_overflow_bitfield, /* complain_on_overflow */
261 sh_reloc, /* special_function */
262 "r_switch32", /* name */
b34976b6 263 TRUE, /* partial_inplace */
252b5132
RH		 264 0xffffffff, /* src_mask */
265 0xffffffff, /* dst_mask */
b34976b6 266 FALSE), /* pcrel_offset */
252b5132
RH		 267
268 HOWTO (R_SH_USES, /* type */
269 0, /* rightshift */
270 1, /* size (0 = byte, 1 = short, 2 = long) */
271 16, /* bitsize */
b34976b6 272 FALSE, /* pc_relative */
252b5132
RH		 273 0, /* bitpos */
274 complain_overflow_bitfield, /* complain_on_overflow */
275 sh_reloc, /* special_function */
276 "r_uses", /* name */
b34976b6 277 TRUE, /* partial_inplace */
252b5132
RH		 278 0xffff, /* src_mask */
279 0xffff, /* dst_mask */
b34976b6 280 FALSE), /* pcrel_offset */
252b5132
RH		 281
282 HOWTO (R_SH_COUNT, /* type */
283 0, /* rightshift */
284 2, /* size (0 = byte, 1 = short, 2 = long) */
285 32, /* bitsize */
b34976b6 286 FALSE, /* pc_relative */
252b5132
RH		 287 0, /* bitpos */
288 complain_overflow_bitfield, /* complain_on_overflow */
289 sh_reloc, /* special_function */
290 "r_count", /* name */
b34976b6 291 TRUE, /* partial_inplace */
252b5132
RH		 292 0xffffffff, /* src_mask */
293 0xffffffff, /* dst_mask */
b34976b6 294 FALSE), /* pcrel_offset */
252b5132
RH		 295
296 HOWTO (R_SH_ALIGN, /* type */
297 0, /* rightshift */
298 2, /* size (0 = byte, 1 = short, 2 = long) */
299 32, /* bitsize */
b34976b6 300 FALSE, /* pc_relative */
252b5132
RH		 301 0, /* bitpos */
302 complain_overflow_bitfield, /* complain_on_overflow */
303 sh_reloc, /* special_function */
304 "r_align", /* name */
b34976b6 305 TRUE, /* partial_inplace */
252b5132
RH		 306 0xffffffff, /* src_mask */
307 0xffffffff, /* dst_mask */
b34976b6 308 FALSE), /* pcrel_offset */
252b5132
RH		 309
310 HOWTO (R_SH_CODE, /* type */
311 0, /* rightshift */
312 2, /* size (0 = byte, 1 = short, 2 = long) */
313 32, /* bitsize */
b34976b6 314 FALSE, /* pc_relative */
252b5132
RH		 315 0, /* bitpos */
316 complain_overflow_bitfield, /* complain_on_overflow */
317 sh_reloc, /* special_function */
318 "r_code", /* name */
b34976b6 319 TRUE, /* partial_inplace */
252b5132
RH		 320 0xffffffff, /* src_mask */
321 0xffffffff, /* dst_mask */
b34976b6 322 FALSE), /* pcrel_offset */
252b5132
RH		 323
324 HOWTO (R_SH_DATA, /* type */
325 0, /* rightshift */
326 2, /* size (0 = byte, 1 = short, 2 = long) */
327 32, /* bitsize */
b34976b6 328 FALSE, /* pc_relative */
252b5132
RH		 329 0, /* bitpos */
330 complain_overflow_bitfield, /* complain_on_overflow */
331 sh_reloc, /* special_function */
332 "r_data", /* name */
b34976b6 333 TRUE, /* partial_inplace */
252b5132
RH		 334 0xffffffff, /* src_mask */
335 0xffffffff, /* dst_mask */
b34976b6 336 FALSE), /* pcrel_offset */
252b5132
RH		 337
338 HOWTO (R_SH_LABEL, /* type */
339 0, /* rightshift */
340 2, /* size (0 = byte, 1 = short, 2 = long) */
341 32, /* bitsize */
b34976b6 342 FALSE, /* pc_relative */
252b5132
RH		 343 0, /* bitpos */
344 complain_overflow_bitfield, /* complain_on_overflow */
345 sh_reloc, /* special_function */
346 "r_label", /* name */
b34976b6 347 TRUE, /* partial_inplace */
252b5132
RH		 348 0xffffffff, /* src_mask */
349 0xffffffff, /* dst_mask */
b34976b6 350 FALSE), /* pcrel_offset */
252b5132
RH		 351
352 HOWTO (R_SH_SWITCH8, /* type */
353 0, /* rightshift */
354 0, /* size (0 = byte, 1 = short, 2 = long) */
355 8, /* bitsize */
b34976b6 356 FALSE, /* pc_relative */
252b5132
RH		 357 0, /* bitpos */
358 complain_overflow_bitfield, /* complain_on_overflow */
359 sh_reloc, /* special_function */
360 "r_switch8", /* name */
b34976b6 361 TRUE, /* partial_inplace */
252b5132
RH		 362 0xff, /* src_mask */
363 0xff, /* dst_mask */
b34976b6 364 FALSE) /* pcrel_offset */
252b5132
RH		 365};
366
367#define SH_COFF_HOWTO_COUNT (sizeof sh_coff_howtos / sizeof sh_coff_howtos[0])
368
369/* Check for a bad magic number. */
370#define BADMAG(x) SHBADMAG(x)
371
372/* Customize coffcode.h (this is not currently used). */
373#define SH 1
374
375/* FIXME: This should not be set here. */
376#define __A_MAGIC_SET__
377
17505c5c 378#ifndef COFF_WITH_PE
252b5132 379/* Swap the r_offset field in and out. */
dc810e39
AM		 380#define SWAP_IN_RELOC_OFFSET H_GET_32
381#define SWAP_OUT_RELOC_OFFSET H_PUT_32
252b5132
RH		 382
383/* Swap out extra information in the reloc structure. */
384#define SWAP_OUT_RELOC_EXTRA(abfd, src, dst) \
385 do \
386 { \
387 dst->r_stuff[0] = 'S'; \
388 dst->r_stuff[1] = 'C'; \
389 } \
390 while (0)
17505c5c 391#endif
252b5132
RH		 392
393/* Get the value of a symbol, when performing a relocation. */
394
395static long
2c3fc389 396get_symbol_value (asymbol *symbol)
cbfe05c4 397{
252b5132
RH		 398 bfd_vma relocation;
399
400 if (bfd_is_com_section (symbol->section))
cbfe05c4
KH		 401 relocation = 0;
402 else
252b5132
RH		 403 relocation = (symbol->value +
404 symbol->section->output_section->vma +
405 symbol->section->output_offset);
406
407 return relocation;
408}
409
17505c5c
NC		 410#ifdef COFF_WITH_PE
411/* Convert an rtype to howto for the COFF backend linker.
412 Copied from coff-i386. */
413#define coff_rtype_to_howto coff_sh_rtype_to_howto
2c3fc389 414
17505c5c
NC		 415
416static reloc_howto_type *
2c3fc389
NC		 417coff_sh_rtype_to_howto (bfd * abfd ATTRIBUTE_UNUSED,
418 asection * sec,
419 struct internal_reloc * rel,
420 struct coff_link_hash_entry * h,
421 struct internal_syment * sym,
422 bfd_vma * addendp)
17505c5c
NC		 423{
424 reloc_howto_type * howto;
425
426 howto = sh_coff_howtos + rel->r_type;
427
428 *addendp = 0;
429
430 if (howto->pc_relative)
431 *addendp += sec->vma;
432
433 if (sym != NULL && sym->n_scnum == 0 && sym->n_value != 0)
434 {
435 /* This is a common symbol. The section contents include the
436 size (sym->n_value) as an addend. The relocate_section
437 function will be adding in the final value of the symbol. We
438 need to subtract out the current size in order to get the
439 correct result. */
440 BFD_ASSERT (h != NULL);
441 }
442
443 if (howto->pc_relative)
444 {
445 *addendp -= 4;
446
447 /* If the symbol is defined, then the generic code is going to
07d6d2b8
AM		 448 add back the symbol value in order to cancel out an
449 adjustment it made to the addend. However, we set the addend
450 to 0 at the start of this function. We need to adjust here,
451 to avoid the adjustment the generic code will make. FIXME:
452 This is getting a bit hackish. */
17505c5c
NC		 453 if (sym != NULL && sym->n_scnum != 0)
454 *addendp -= sym->n_value;
455 }
456
457 if (rel->r_type == R_SH_IMAGEBASE)
458 *addendp -= pe_data (sec->output_section->owner)->pe_opthdr.ImageBase;
459
460 return howto;
461}
462
993e9275
NC		 463#endif /* COFF_WITH_PE */
464
17505c5c
NC		 465/* This structure is used to map BFD reloc codes to SH PE relocs. */
466struct shcoff_reloc_map
467{
aa066ac8 468 bfd_reloc_code_real_type bfd_reloc_val;
17505c5c
NC		 469 unsigned char shcoff_reloc_val;
470};
471
a9a32010 472#ifdef COFF_WITH_PE
17505c5c
NC		 473/* An array mapping BFD reloc codes to SH PE relocs. */
474static const struct shcoff_reloc_map sh_reloc_map[] =
475{
476 { BFD_RELOC_32, R_SH_IMM32CE },
477 { BFD_RELOC_RVA, R_SH_IMAGEBASE },
478 { BFD_RELOC_CTOR, R_SH_IMM32CE },
479};
a9a32010
DJ		 480#else
481/* An array mapping BFD reloc codes to SH PE relocs. */
482static const struct shcoff_reloc_map sh_reloc_map[] =
483{
484 { BFD_RELOC_32, R_SH_IMM32 },
485 { BFD_RELOC_CTOR, R_SH_IMM32 },
486};
487#endif
17505c5c
NC		 488
489/* Given a BFD reloc code, return the howto structure for the
490 corresponding SH PE reloc. */
491#define coff_bfd_reloc_type_lookup sh_coff_reloc_type_lookup
157090f7 492#define coff_bfd_reloc_name_lookup sh_coff_reloc_name_lookup
17505c5c
NC		 493
494static reloc_howto_type *
0aa13fee 495sh_coff_reloc_type_lookup (bfd *abfd,
2c3fc389 496 bfd_reloc_code_real_type code)
17505c5c
NC		 497{
498 unsigned int i;
499
993e9275
NC		 500 for (i = ARRAY_SIZE (sh_reloc_map); i--;)
501 if (sh_reloc_map[i].bfd_reloc_val == code)
502 return &sh_coff_howtos[(int) sh_reloc_map[i].shcoff_reloc_val];
17505c5c 503
0aa13fee
AM		 504 _bfd_error_handler (_("%pB: unsupported relocation type %#x"),
505 abfd, (unsigned int) code);
17505c5c
NC		 506 return NULL;
507}
17505c5c 508
157090f7
AM		 509static reloc_howto_type *
510sh_coff_reloc_name_lookup (bfd *abfd ATTRIBUTE_UNUSED,
511 const char *r_name)
512{
513 unsigned int i;
514
515 for (i = 0; i < sizeof (sh_coff_howtos) / sizeof (sh_coff_howtos[0]); i++)
516 if (sh_coff_howtos[i].name != NULL
517 && strcasecmp (sh_coff_howtos[i].name, r_name) == 0)
518 return &sh_coff_howtos[i];
519
520 return NULL;
521}
522
252b5132
RH		 523/* This macro is used in coffcode.h to get the howto corresponding to
524 an internal reloc. */
525
526#define RTYPE2HOWTO(relent, internal) \
527 ((relent)->howto = \
528 ((internal)->r_type < SH_COFF_HOWTO_COUNT \
529 ? &sh_coff_howtos[(internal)->r_type] \
530 : (reloc_howto_type *) NULL))
531
532/* This is the same as the macro in coffcode.h, except that it copies
533 r_offset into reloc_entry->addend for some relocs. */
f4943d82
AM		 534#define CALC_ADDEND(abfd, ptr, reloc, cache_ptr) \
535 { \
536 coff_symbol_type *coffsym = (coff_symbol_type *) NULL; \
537 if (ptr && bfd_asymbol_bfd (ptr) != abfd) \
538 coffsym = (obj_symbols (abfd) \
539 + (cache_ptr->sym_ptr_ptr - symbols)); \
540 else if (ptr) \
541 coffsym = coff_symbol_from (ptr); \
542 if (coffsym != (coff_symbol_type *) NULL \
543 && coffsym->native->u.syment.n_scnum == 0) \
544 cache_ptr->addend = 0; \
545 else if (ptr && bfd_asymbol_bfd (ptr) == abfd \
546 && ptr->section != (asection *) NULL) \
547 cache_ptr->addend = - (ptr->section->vma + ptr->value); \
548 else \
549 cache_ptr->addend = 0; \
252b5132
RH		 550 if ((reloc).r_type == R_SH_SWITCH8 \
551 || (reloc).r_type == R_SH_SWITCH16 \
552 || (reloc).r_type == R_SH_SWITCH32 \
553 || (reloc).r_type == R_SH_USES \
554 || (reloc).r_type == R_SH_COUNT \
555 || (reloc).r_type == R_SH_ALIGN) \
556 cache_ptr->addend = (reloc).r_offset; \
557 }
558
559/* This is the howto function for the SH relocations. */
560
561static bfd_reloc_status_type
2c3fc389
NC		 562sh_reloc (bfd * abfd,
563 arelent * reloc_entry,
564 asymbol * symbol_in,
565 void * data,
566 asection * input_section,
567 bfd * output_bfd,
568 char ** error_message ATTRIBUTE_UNUSED)
252b5132 569{
96e2dbda 570 bfd_vma insn;
252b5132
RH		 571 bfd_vma sym_value;
572 unsigned short r_type;
573 bfd_vma addr = reloc_entry->address;
574 bfd_byte *hit_data = addr + (bfd_byte *) data;
575
576 r_type = reloc_entry->howto->type;
577
578 if (output_bfd != NULL)
579 {
580 /* Partial linking--do nothing. */
581 reloc_entry->address += input_section->output_offset;
582 return bfd_reloc_ok;
583 }
584
585 /* Almost all relocs have to do with relaxing. If any work must be
586 done for them, it has been done in sh_relax_section. */
587 if (r_type != R_SH_IMM32
17505c5c
NC		 588#ifdef COFF_WITH_PE
589 && r_type != R_SH_IMM32CE
590 && r_type != R_SH_IMAGEBASE
591#endif
252b5132
RH		 592 && (r_type != R_SH_PCDISP
593 || (symbol_in->flags & BSF_LOCAL) != 0))
594 return bfd_reloc_ok;
595
596 if (symbol_in != NULL
597 && bfd_is_und_section (symbol_in->section))
598 return bfd_reloc_undefined;
599
6879f5a9
NC		 600 if (addr > input_section->size)
601 return bfd_reloc_outofrange;
602
252b5132
RH		 603 sym_value = get_symbol_value (symbol_in);
604
605 switch (r_type)
606 {
607 case R_SH_IMM32:
17505c5c
NC		 608#ifdef COFF_WITH_PE
609 case R_SH_IMM32CE:
610#endif
252b5132
RH		 611 insn = bfd_get_32 (abfd, hit_data);
612 insn += sym_value + reloc_entry->addend;
96e2dbda 613 bfd_put_32 (abfd, insn, hit_data);
252b5132 614 break;
17505c5c
NC		 615#ifdef COFF_WITH_PE
616 case R_SH_IMAGEBASE:
617 insn = bfd_get_32 (abfd, hit_data);
dc810e39
AM		 618 insn += sym_value + reloc_entry->addend;
619 insn -= pe_data (input_section->output_section->owner)->pe_opthdr.ImageBase;
96e2dbda 620 bfd_put_32 (abfd, insn, hit_data);
17505c5c
NC		 621 break;
622#endif
252b5132
RH		 623 case R_SH_PCDISP:
624 insn = bfd_get_16 (abfd, hit_data);
625 sym_value += reloc_entry->addend;
626 sym_value -= (input_section->output_section->vma
627 + input_section->output_offset
628 + addr
629 + 4);
96e2dbda
AM		 630 sym_value += (((insn & 0xfff) ^ 0x800) - 0x800) << 1;
631 insn = (insn & 0xf000) | ((sym_value >> 1) & 0xfff);
632 bfd_put_16 (abfd, insn, hit_data);
633 if (sym_value + 0x1000 >= 0x2000 || (sym_value & 1) != 0)
252b5132
RH		 634 return bfd_reloc_overflow;
635 break;
636 default:
637 abort ();
638 break;
639 }
640
641 return bfd_reloc_ok;
642}
643
875f7f69 644#define coff_bfd_merge_private_bfd_data _bfd_generic_verify_endian_match
252b5132
RH		 645
646/* We can do relaxing. */
647#define coff_bfd_relax_section sh_relax_section
648
649/* We use the special COFF backend linker. */
650#define coff_relocate_section sh_relocate_section
651
652/* When relaxing, we need to use special code to get the relocated
653 section contents. */
654#define coff_bfd_get_relocated_section_contents \
655 sh_coff_get_relocated_section_contents
656
657#include "coffcode.h"
658\f
2c3fc389
NC		 659static bfd_boolean
660sh_relax_delete_bytes (bfd *, asection *, bfd_vma, int);
661
252b5132
RH		 662/* This function handles relaxing on the SH.
663
664 Function calls on the SH look like this:
665
666 movl L1,r0
667 ...
668 jsr @r0
669 ...
670 L1:
671 .long function
672
673 The compiler and assembler will cooperate to create R_SH_USES
674 relocs on the jsr instructions. The r_offset field of the
675 R_SH_USES reloc is the PC relative offset to the instruction which
676 loads the register (the r_offset field is computed as though it
677 were a jump instruction, so the offset value is actually from four
678 bytes past the instruction). The linker can use this reloc to
679 determine just which function is being called, and thus decide
680 whether it is possible to replace the jsr with a bsr.
681
682 If multiple function calls are all based on a single register load
683 (i.e., the same function is called multiple times), the compiler
684 guarantees that each function call will have an R_SH_USES reloc.
685 Therefore, if the linker is able to convert each R_SH_USES reloc
686 which refers to that address, it can safely eliminate the register
687 load.
688
689 When the assembler creates an R_SH_USES reloc, it examines it to
690 determine which address is being loaded (L1 in the above example).
691 It then counts the number of references to that address, and
692 creates an R_SH_COUNT reloc at that address. The r_offset field of
693 the R_SH_COUNT reloc will be the number of references. If the
694 linker is able to eliminate a register load, it can use the
695 R_SH_COUNT reloc to see whether it can also eliminate the function
696 address.
697
698 SH relaxing also handles another, unrelated, matter. On the SH, if
699 a load or store instruction is not aligned on a four byte boundary,
700 the memory cycle interferes with the 32 bit instruction fetch,
701 causing a one cycle bubble in the pipeline. Therefore, we try to
702 align load and store instructions on four byte boundaries if we
703 can, by swapping them with one of the adjacent instructions. */
704
b34976b6 705static bfd_boolean
2c3fc389
NC		 706sh_relax_section (bfd *abfd,
707 asection *sec,
708 struct bfd_link_info *link_info,
709 bfd_boolean *again)
252b5132
RH		 710{
711 struct internal_reloc *internal_relocs;
b34976b6 712 bfd_boolean have_code;
252b5132
RH		 713 struct internal_reloc *irel, *irelend;
714 bfd_byte *contents = NULL;
252b5132 715
b34976b6 716 *again = FALSE;
252b5132 717
0e1862bb 718 if (bfd_link_relocatable (link_info)
252b5132
RH		 719 || (sec->flags & SEC_RELOC) == 0
720 || sec->reloc_count == 0)
b34976b6 721 return TRUE;
252b5132 722
eea6121a
AM		 723 if (coff_section_data (abfd, sec) == NULL)
724 {
725 bfd_size_type amt = sizeof (struct coff_section_tdata);
2c3fc389 726 sec->used_by_bfd = bfd_zalloc (abfd, amt);
eea6121a
AM		 727 if (sec->used_by_bfd == NULL)
728 return FALSE;
729 }
252b5132
RH		 730
731 internal_relocs = (_bfd_coff_read_internal_relocs
732 (abfd, sec, link_info->keep_memory,
b34976b6 733 (bfd_byte *) NULL, FALSE,
252b5132
RH		 734 (struct internal_reloc *) NULL));
735 if (internal_relocs == NULL)
736 goto error_return;
252b5132 737
b34976b6 738 have_code = FALSE;
252b5132
RH		 739
740 irelend = internal_relocs + sec->reloc_count;
741 for (irel = internal_relocs; irel < irelend; irel++)
742 {
743 bfd_vma laddr, paddr, symval;
744 unsigned short insn;
745 struct internal_reloc *irelfn, *irelscan, *irelcount;
746 struct internal_syment sym;
747 bfd_signed_vma foff;
748
749 if (irel->r_type == R_SH_CODE)
b34976b6 750 have_code = TRUE;
252b5132
RH		 751
752 if (irel->r_type != R_SH_USES)
753 continue;
754
755 /* Get the section contents. */
756 if (contents == NULL)
757 {
eea6121a 758 if (coff_section_data (abfd, sec)->contents != NULL)
252b5132
RH		 759 contents = coff_section_data (abfd, sec)->contents;
760 else
761 {
eea6121a 762 if (!bfd_malloc_and_get_section (abfd, sec, &contents))
252b5132
RH		 763 goto error_return;
764 }
765 }
766
767 /* The r_offset field of the R_SH_USES reloc will point us to
07d6d2b8
AM		 768 the register load. The 4 is because the r_offset field is
769 computed as though it were a jump offset, which are based
770 from 4 bytes after the jump instruction. */
252b5132
RH		 771 laddr = irel->r_vaddr - sec->vma + 4;
772 /* Careful to sign extend the 32-bit offset. */
773 laddr += ((irel->r_offset & 0xffffffff) ^ 0x80000000) - 0x80000000;
eea6121a 774 if (laddr >= sec->size)
252b5132 775 {
695344c0 776 /* xgettext: c-format */
2dcf00ce
AM		 777 _bfd_error_handler
778 (_("%pB: %#" PRIx64 ": warning: bad R_SH_USES offset"),
779 abfd, (uint64_t) irel->r_vaddr);
252b5132
RH		 780 continue;
781 }
782 insn = bfd_get_16 (abfd, contents + laddr);
783
784 /* If the instruction is not mov.l NN,rN, we don't know what to do. */
785 if ((insn & 0xf000) != 0xd000)
786 {
4eca0228 787 _bfd_error_handler
695344c0 788 /* xgettext: c-format */
2dcf00ce
AM		 789 (_("%pB: %#" PRIx64 ": warning: R_SH_USES points to unrecognized insn %#x"),
790 abfd, (uint64_t) irel->r_vaddr, insn);
252b5132
RH		 791 continue;
792 }
793
794 /* Get the address from which the register is being loaded. The
07d6d2b8
AM		 795 displacement in the mov.l instruction is quadrupled. It is a
796 displacement from four bytes after the movl instruction, but,
797 before adding in the PC address, two least significant bits
798 of the PC are cleared. We assume that the section is aligned
799 on a four byte boundary. */
252b5132
RH		 800 paddr = insn & 0xff;
801 paddr *= 4;
dc810e39 802 paddr += (laddr + 4) &~ (bfd_vma) 3;
eea6121a 803 if (paddr >= sec->size)
252b5132 804 {
4eca0228 805 _bfd_error_handler
695344c0 806 /* xgettext: c-format */
2dcf00ce
AM		 807 (_("%pB: %#" PRIx64 ": warning: bad R_SH_USES load offset"),
808 abfd, (uint64_t) irel->r_vaddr);
252b5132
RH		 809 continue;
810 }
811
812 /* Get the reloc for the address from which the register is
07d6d2b8
AM		 813 being loaded. This reloc will tell us which function is
814 actually being called. */
252b5132
RH		 815 paddr += sec->vma;
816 for (irelfn = internal_relocs; irelfn < irelend; irelfn++)
817 if (irelfn->r_vaddr == paddr
17505c5c
NC		 818#ifdef COFF_WITH_PE
819 && (irelfn->r_type == R_SH_IMM32
820 || irelfn->r_type == R_SH_IMM32CE
eea6121a 821 || irelfn->r_type == R_SH_IMAGEBASE)
17505c5c
NC		 822
823#else
eea6121a 824 && irelfn->r_type == R_SH_IMM32
17505c5c 825#endif
eea6121a 826 )
252b5132
RH		 827 break;
828 if (irelfn >= irelend)
829 {
4eca0228 830 _bfd_error_handler
695344c0 831 /* xgettext: c-format */
2dcf00ce
AM		 832 (_("%pB: %#" PRIx64 ": warning: could not find expected reloc"),
833 abfd, (uint64_t) paddr);
252b5132
RH		 834 continue;
835 }
836
837 /* Get the value of the symbol referred to by the reloc. */
838 if (! _bfd_coff_get_external_symbols (abfd))
839 goto error_return;
840 bfd_coff_swap_sym_in (abfd,
841 ((bfd_byte *) obj_coff_external_syms (abfd)
842 + (irelfn->r_symndx
843 * bfd_coff_symesz (abfd))),
844 &sym);
845 if (sym.n_scnum != 0 && sym.n_scnum != sec->target_index)
846 {
4eca0228 847 _bfd_error_handler
695344c0 848 /* xgettext: c-format */
2dcf00ce
AM		 849 (_("%pB: %#" PRIx64 ": warning: symbol in unexpected section"),
850 abfd, (uint64_t) paddr);
252b5132
RH		 851 continue;
852 }
853
854 if (sym.n_sclass != C_EXT)
855 {
856 symval = (sym.n_value
857 - sec->vma
858 + sec->output_section->vma
859 + sec->output_offset);
860 }
861 else
862 {
863 struct coff_link_hash_entry *h;
864
865 h = obj_coff_sym_hashes (abfd)[irelfn->r_symndx];
866 BFD_ASSERT (h != NULL);
867 if (h->root.type != bfd_link_hash_defined
868 && h->root.type != bfd_link_hash_defweak)
869 {
870 /* This appears to be a reference to an undefined
07d6d2b8
AM		 871 symbol. Just ignore it--it will be caught by the
872 regular reloc processing. */
252b5132
RH		 873 continue;
874 }
875
876 symval = (h->root.u.def.value
877 + h->root.u.def.section->output_section->vma
878 + h->root.u.def.section->output_offset);
879 }
880
881 symval += bfd_get_32 (abfd, contents + paddr - sec->vma);
882
883 /* See if this function call can be shortened. */
884 foff = (symval
885 - (irel->r_vaddr
886 - sec->vma
887 + sec->output_section->vma
888 + sec->output_offset
889 + 4));
890 if (foff < -0x1000 || foff >= 0x1000)
891 {
892 /* After all that work, we can't shorten this function call. */
893 continue;
894 }
895
896 /* Shorten the function call. */
897
898 /* For simplicity of coding, we are going to modify the section
899 contents, the section relocs, and the BFD symbol table. We
900 must tell the rest of the code not to free up this
901 information. It would be possible to instead create a table
902 of changes which have to be made, as is done in coff-mips.c;
903 that would be more work, but would require less memory when
904 the linker is run. */
905
252b5132 906 coff_section_data (abfd, sec)->relocs = internal_relocs;
b34976b6 907 coff_section_data (abfd, sec)->keep_relocs = TRUE;
252b5132
RH		 908
909 coff_section_data (abfd, sec)->contents = contents;
b34976b6 910 coff_section_data (abfd, sec)->keep_contents = TRUE;
252b5132 911
b34976b6 912 obj_coff_keep_syms (abfd) = TRUE;
252b5132
RH		 913
914 /* Replace the jsr with a bsr. */
915
916 /* Change the R_SH_USES reloc into an R_SH_PCDISP reloc, and
07d6d2b8 917 replace the jsr with a bsr. */
252b5132
RH		 918 irel->r_type = R_SH_PCDISP;
919 irel->r_symndx = irelfn->r_symndx;
920 if (sym.n_sclass != C_EXT)
921 {
922 /* If this needs to be changed because of future relaxing,
07d6d2b8
AM		 923 it will be handled here like other internal PCDISP
924 relocs. */
252b5132 925 bfd_put_16 (abfd,
dc810e39 926 (bfd_vma) 0xb000 | ((foff >> 1) & 0xfff),
252b5132
RH		 927 contents + irel->r_vaddr - sec->vma);
928 }
929 else
930 {
931 /* We can't fully resolve this yet, because the external
07d6d2b8
AM		 932 symbol value may be changed by future relaxing. We let
933 the final link phase handle it. */
dc810e39
AM		 934 bfd_put_16 (abfd, (bfd_vma) 0xb000,
935 contents + irel->r_vaddr - sec->vma);
252b5132
RH		 936 }
937
938 /* See if there is another R_SH_USES reloc referring to the same
07d6d2b8 939 register load. */
252b5132
RH		 940 for (irelscan = internal_relocs; irelscan < irelend; irelscan++)
941 if (irelscan->r_type == R_SH_USES
942 && laddr == irelscan->r_vaddr - sec->vma + 4 + irelscan->r_offset)
943 break;
944 if (irelscan < irelend)
945 {
946 /* Some other function call depends upon this register load,
947 and we have not yet converted that function call.
948 Indeed, we may never be able to convert it. There is
949 nothing else we can do at this point. */
950 continue;
951 }
952
953 /* Look for a R_SH_COUNT reloc on the location where the
07d6d2b8
AM		 954 function address is stored. Do this before deleting any
955 bytes, to avoid confusion about the address. */
252b5132
RH		 956 for (irelcount = internal_relocs; irelcount < irelend; irelcount++)
957 if (irelcount->r_vaddr == paddr
958 && irelcount->r_type == R_SH_COUNT)
959 break;
960
961 /* Delete the register load. */
962 if (! sh_relax_delete_bytes (abfd, sec, laddr, 2))
963 goto error_return;
964
965 /* That will change things, so, just in case it permits some
07d6d2b8
AM		 966 other function call to come within range, we should relax
967 again. Note that this is not required, and it may be slow. */
b34976b6 968 *again = TRUE;
252b5132
RH		 969
970 /* Now check whether we got a COUNT reloc. */
971 if (irelcount >= irelend)
972 {
4eca0228 973 _bfd_error_handler
695344c0 974 /* xgettext: c-format */
2dcf00ce
AM		 975 (_("%pB: %#" PRIx64 ": warning: could not find expected COUNT reloc"),
976 abfd, (uint64_t) paddr);
252b5132
RH		 977 continue;
978 }
979
980 /* The number of uses is stored in the r_offset field. We've
07d6d2b8 981 just deleted one. */
252b5132
RH		 982 if (irelcount->r_offset == 0)
983 {
695344c0 984 /* xgettext: c-format */
2dcf00ce
AM		 985 _bfd_error_handler (_("%pB: %#" PRIx64 ": warning: bad count"),
986 abfd, (uint64_t) paddr);
252b5132
RH		 987 continue;
988 }
989
990 --irelcount->r_offset;
991
992 /* If there are no more uses, we can delete the address. Reload
07d6d2b8
AM		 993 the address from irelfn, in case it was changed by the
994 previous call to sh_relax_delete_bytes. */
252b5132
RH		 995 if (irelcount->r_offset == 0)
996 {
997 if (! sh_relax_delete_bytes (abfd, sec,
998 irelfn->r_vaddr - sec->vma, 4))
999 goto error_return;
1000 }
1001
1002 /* We've done all we can with that function call. */
1003 }
1004
1005 /* Look for load and store instructions that we can align on four
1006 byte boundaries. */
1007 if (have_code)
1008 {
b34976b6 1009 bfd_boolean swapped;
252b5132
RH		 1010
1011 /* Get the section contents. */
1012 if (contents == NULL)
1013 {
eea6121a 1014 if (coff_section_data (abfd, sec)->contents != NULL)
252b5132
RH		 1015 contents = coff_section_data (abfd, sec)->contents;
1016 else
1017 {
eea6121a 1018 if (!bfd_malloc_and_get_section (abfd, sec, &contents))
252b5132
RH		 1019 goto error_return;
1020 }
1021 }
1022
1023 if (! sh_align_loads (abfd, sec, internal_relocs, contents, &swapped))
1024 goto error_return;
1025
1026 if (swapped)
1027 {
252b5132 1028 coff_section_data (abfd, sec)->relocs = internal_relocs;
b34976b6 1029 coff_section_data (abfd, sec)->keep_relocs = TRUE;
252b5132
RH		 1030
1031 coff_section_data (abfd, sec)->contents = contents;
b34976b6 1032 coff_section_data (abfd, sec)->keep_contents = TRUE;
252b5132 1033
b34976b6 1034 obj_coff_keep_syms (abfd) = TRUE;
252b5132
RH		 1035 }
1036 }
1037
eea6121a
AM		 1038 if (internal_relocs != NULL
1039 && internal_relocs != coff_section_data (abfd, sec)->relocs)
252b5132 1040 {
eea6121a
AM		 1041 if (! link_info->keep_memory)
1042 free (internal_relocs);
1043 else
1044 coff_section_data (abfd, sec)->relocs = internal_relocs;
252b5132
RH		 1045 }
1046
eea6121a 1047 if (contents != NULL && contents != coff_section_data (abfd, sec)->contents)
252b5132
RH		 1048 {
1049 if (! link_info->keep_memory)
eea6121a 1050 free (contents);
252b5132 1051 else
eea6121a
AM		 1052 /* Cache the section contents for coff_link_input_bfd. */
1053 coff_section_data (abfd, sec)->contents = contents;
252b5132
RH		 1054 }
1055
b34976b6 1056 return TRUE;
252b5132
RH		 1057
1058 error_return:
eea6121a
AM		 1059 if (internal_relocs != NULL
1060 && internal_relocs != coff_section_data (abfd, sec)->relocs)
1061 free (internal_relocs);
1062 if (contents != NULL && contents != coff_section_data (abfd, sec)->contents)
1063 free (contents);
b34976b6 1064 return FALSE;
252b5132
RH		 1065}
1066
1067/* Delete some bytes from a section while relaxing. */
1068
b34976b6 1069static bfd_boolean
2c3fc389
NC		 1070sh_relax_delete_bytes (bfd *abfd,
1071 asection *sec,
1072 bfd_vma addr,
1073 int count)
252b5132
RH		 1074{
1075 bfd_byte *contents;
1076 struct internal_reloc *irel, *irelend;
1077 struct internal_reloc *irelalign;
1078 bfd_vma toaddr;
1079 bfd_byte *esym, *esymend;
1080 bfd_size_type symesz;
1081 struct coff_link_hash_entry **sym_hash;
1082 asection *o;
1083
1084 contents = coff_section_data (abfd, sec)->contents;
1085
de194d85 1086 /* The deletion must stop at the next ALIGN reloc for an alignment
252b5132
RH		 1087 power larger than the number of bytes we are deleting. */
1088
1089 irelalign = NULL;
eea6121a 1090 toaddr = sec->size;
252b5132
RH		 1091
1092 irel = coff_section_data (abfd, sec)->relocs;
1093 irelend = irel + sec->reloc_count;
1094 for (; irel < irelend; irel++)
1095 {
1096 if (irel->r_type == R_SH_ALIGN
1097 && irel->r_vaddr - sec->vma > addr
1098 && count < (1 << irel->r_offset))
1099 {
1100 irelalign = irel;
1101 toaddr = irel->r_vaddr - sec->vma;
1102 break;
1103 }
1104 }
1105
1106 /* Actually delete the bytes. */
dc810e39
AM		 1107 memmove (contents + addr, contents + addr + count,
1108 (size_t) (toaddr - addr - count));
252b5132 1109 if (irelalign == NULL)
eea6121a 1110 sec->size -= count;
252b5132
RH		 1111 else
1112 {
1113 int i;
1114
1115#define NOP_OPCODE (0x0009)
1116
1117 BFD_ASSERT ((count & 1) == 0);
1118 for (i = 0; i < count; i += 2)
dc810e39 1119 bfd_put_16 (abfd, (bfd_vma) NOP_OPCODE, contents + toaddr - count + i);
252b5132
RH		 1120 }
1121
1122 /* Adjust all the relocs. */
1123 for (irel = coff_section_data (abfd, sec)->relocs; irel < irelend; irel++)
1124 {
1125 bfd_vma nraddr, stop;
1126 bfd_vma start = 0;
1127 int insn = 0;
1128 struct internal_syment sym;
1129 int off, adjust, oinsn;
1130 bfd_signed_vma voff = 0;
b34976b6 1131 bfd_boolean overflow;
252b5132
RH		 1132
1133 /* Get the new reloc address. */
1134 nraddr = irel->r_vaddr - sec->vma;
1135 if ((irel->r_vaddr - sec->vma > addr
1136 && irel->r_vaddr - sec->vma < toaddr)
1137 || (irel->r_type == R_SH_ALIGN
1138 && irel->r_vaddr - sec->vma == toaddr))
1139 nraddr -= count;
1140
1141 /* See if this reloc was for the bytes we have deleted, in which
1142 case we no longer care about it. Don't delete relocs which
1143 represent addresses, though. */
1144 if (irel->r_vaddr - sec->vma >= addr
1145 && irel->r_vaddr - sec->vma < addr + count
1146 && irel->r_type != R_SH_ALIGN
1147 && irel->r_type != R_SH_CODE
1148 && irel->r_type != R_SH_DATA
1149 && irel->r_type != R_SH_LABEL)
1150 irel->r_type = R_SH_UNUSED;
1151
1152 /* If this is a PC relative reloc, see if the range it covers
07d6d2b8 1153 includes the bytes we have deleted. */
252b5132
RH		 1154 switch (irel->r_type)
1155 {
1156 default:
1157 break;
1158
1159 case R_SH_PCDISP8BY2:
1160 case R_SH_PCDISP:
1161 case R_SH_PCRELIMM8BY2:
1162 case R_SH_PCRELIMM8BY4:
1163 start = irel->r_vaddr - sec->vma;
1164 insn = bfd_get_16 (abfd, contents + nraddr);
1165 break;
1166 }
1167
1168 switch (irel->r_type)
1169 {
1170 default:
1171 start = stop = addr;
1172 break;
1173
1174 case R_SH_IMM32:
17505c5c
NC		 1175#ifdef COFF_WITH_PE
1176 case R_SH_IMM32CE:
1177 case R_SH_IMAGEBASE:
1178#endif
252b5132 1179 /* If this reloc is against a symbol defined in this
07d6d2b8
AM		 1180 section, and the symbol will not be adjusted below, we
1181 must check the addend to see it will put the value in
1182 range to be adjusted, and hence must be changed. */
252b5132
RH		 1183 bfd_coff_swap_sym_in (abfd,
1184 ((bfd_byte *) obj_coff_external_syms (abfd)
1185 + (irel->r_symndx
1186 * bfd_coff_symesz (abfd))),
1187 &sym);
1188 if (sym.n_sclass != C_EXT
1189 && sym.n_scnum == sec->target_index
1190 && ((bfd_vma) sym.n_value <= addr
1191 || (bfd_vma) sym.n_value >= toaddr))
1192 {
1193 bfd_vma val;
1194
1195 val = bfd_get_32 (abfd, contents + nraddr);
1196 val += sym.n_value;
1197 if (val > addr && val < toaddr)
1198 bfd_put_32 (abfd, val - count, contents + nraddr);
1199 }
1200 start = stop = addr;
1201 break;
1202
1203 case R_SH_PCDISP8BY2:
1204 off = insn & 0xff;
1205 if (off & 0x80)
1206 off -= 0x100;
1207 stop = (bfd_vma) ((bfd_signed_vma) start + 4 + off * 2);
1208 break;
1209
1210 case R_SH_PCDISP:
1211 bfd_coff_swap_sym_in (abfd,
1212 ((bfd_byte *) obj_coff_external_syms (abfd)
1213 + (irel->r_symndx
1214 * bfd_coff_symesz (abfd))),
1215 &sym);
1216 if (sym.n_sclass == C_EXT)
1217 start = stop = addr;
1218 else
1219 {
1220 off = insn & 0xfff;
1221 if (off & 0x800)
1222 off -= 0x1000;
1223 stop = (bfd_vma) ((bfd_signed_vma) start + 4 + off * 2);
1224 }
1225 break;
1226
1227 case R_SH_PCRELIMM8BY2:
1228 off = insn & 0xff;
1229 stop = start + 4 + off * 2;
1230 break;
1231
1232 case R_SH_PCRELIMM8BY4:
1233 off = insn & 0xff;
1234 stop = (start &~ (bfd_vma) 3) + 4 + off * 4;
1235 break;
1236
1237 case R_SH_SWITCH8:
1238 case R_SH_SWITCH16:
1239 case R_SH_SWITCH32:
1240 /* These relocs types represent
1241 .word L2-L1
1242 The r_offset field holds the difference between the reloc
1243 address and L1. That is the start of the reloc, and
1244 adding in the contents gives us the top. We must adjust
1245 both the r_offset field and the section contents. */
1246
1247 start = irel->r_vaddr - sec->vma;
1248 stop = (bfd_vma) ((bfd_signed_vma) start - (long) irel->r_offset);
1249
1250 if (start > addr
1251 && start < toaddr
1252 && (stop <= addr || stop >= toaddr))
1253 irel->r_offset += count;
1254 else if (stop > addr
1255 && stop < toaddr
1256 && (start <= addr || start >= toaddr))
1257 irel->r_offset -= count;
1258
1259 start = stop;
1260
1261 if (irel->r_type == R_SH_SWITCH16)
1262 voff = bfd_get_signed_16 (abfd, contents + nraddr);
1263 else if (irel->r_type == R_SH_SWITCH8)
1264 voff = bfd_get_8 (abfd, contents + nraddr);
1265 else
1266 voff = bfd_get_signed_32 (abfd, contents + nraddr);
1267 stop = (bfd_vma) ((bfd_signed_vma) start + voff);
1268
1269 break;
1270
1271 case R_SH_USES:
1272 start = irel->r_vaddr - sec->vma;
1273 stop = (bfd_vma) ((bfd_signed_vma) start
1274 + (long) irel->r_offset
1275 + 4);
1276 break;
1277 }
1278
1279 if (start > addr
1280 && start < toaddr
1281 && (stop <= addr || stop >= toaddr))
1282 adjust = count;
1283 else if (stop > addr
1284 && stop < toaddr
1285 && (start <= addr || start >= toaddr))
1286 adjust = - count;
1287 else
1288 adjust = 0;
1289
1290 if (adjust != 0)
1291 {
1292 oinsn = insn;
b34976b6 1293 overflow = FALSE;
252b5132
RH		 1294 switch (irel->r_type)
1295 {
1296 default:
1297 abort ();
1298 break;
1299
1300 case R_SH_PCDISP8BY2:
1301 case R_SH_PCRELIMM8BY2:
1302 insn += adjust / 2;
1303 if ((oinsn & 0xff00) != (insn & 0xff00))
b34976b6 1304 overflow = TRUE;
dc810e39 1305 bfd_put_16 (abfd, (bfd_vma) insn, contents + nraddr);
252b5132
RH		 1306 break;
1307
1308 case R_SH_PCDISP:
1309 insn += adjust / 2;
1310 if ((oinsn & 0xf000) != (insn & 0xf000))
b34976b6 1311 overflow = TRUE;
dc810e39 1312 bfd_put_16 (abfd, (bfd_vma) insn, contents + nraddr);
252b5132
RH		 1313 break;
1314
1315 case R_SH_PCRELIMM8BY4:
1316 BFD_ASSERT (adjust == count || count >= 4);
1317 if (count >= 4)
1318 insn += adjust / 4;
1319 else
1320 {
1321 if ((irel->r_vaddr & 3) == 0)
1322 ++insn;
1323 }
1324 if ((oinsn & 0xff00) != (insn & 0xff00))
b34976b6 1325 overflow = TRUE;
dc810e39 1326 bfd_put_16 (abfd, (bfd_vma) insn, contents + nraddr);
252b5132
RH		 1327 break;
1328
1329 case R_SH_SWITCH8:
1330 voff += adjust;
1331 if (voff < 0 || voff >= 0xff)
b34976b6 1332 overflow = TRUE;
dc810e39 1333 bfd_put_8 (abfd, (bfd_vma) voff, contents + nraddr);
252b5132
RH		 1334 break;
1335
1336 case R_SH_SWITCH16:
1337 voff += adjust;
1338 if (voff < - 0x8000 || voff >= 0x8000)
b34976b6 1339 overflow = TRUE;
dc810e39 1340 bfd_put_signed_16 (abfd, (bfd_vma) voff, contents + nraddr);
252b5132
RH		 1341 break;
1342
1343 case R_SH_SWITCH32:
1344 voff += adjust;
dc810e39 1345 bfd_put_signed_32 (abfd, (bfd_vma) voff, contents + nraddr);
252b5132
RH		 1346 break;
1347
1348 case R_SH_USES:
1349 irel->r_offset += adjust;
1350 break;
1351 }
1352
1353 if (overflow)
1354 {
4eca0228 1355 _bfd_error_handler
695344c0 1356 /* xgettext: c-format */
2dcf00ce
AM		 1357 (_("%pB: %#" PRIx64 ": fatal: reloc overflow while relaxing"),
1358 abfd, (uint64_t) irel->r_vaddr);
252b5132 1359 bfd_set_error (bfd_error_bad_value);
b34976b6 1360 return FALSE;
252b5132
RH		 1361 }
1362 }
1363
1364 irel->r_vaddr = nraddr + sec->vma;
1365 }
1366
1367 /* Look through all the other sections. If there contain any IMM32
1368 relocs against internal symbols which we are not going to adjust
1369 below, we may need to adjust the addends. */
1370 for (o = abfd->sections; o != NULL; o = o->next)
1371 {
1372 struct internal_reloc *internal_relocs;
1373 struct internal_reloc *irelscan, *irelscanend;
1374 bfd_byte *ocontents;
1375
1376 if (o == sec
1377 || (o->flags & SEC_RELOC) == 0
1378 || o->reloc_count == 0)
1379 continue;
1380
1381 /* We always cache the relocs. Perhaps, if info->keep_memory is
07d6d2b8
AM		 1382 FALSE, we should free them, if we are permitted to, when we
1383 leave sh_coff_relax_section. */
252b5132 1384 internal_relocs = (_bfd_coff_read_internal_relocs
b34976b6 1385 (abfd, o, TRUE, (bfd_byte *) NULL, FALSE,
252b5132
RH		 1386 (struct internal_reloc *) NULL));
1387 if (internal_relocs == NULL)
b34976b6 1388 return FALSE;
252b5132
RH		 1389
1390 ocontents = NULL;
1391 irelscanend = internal_relocs + o->reloc_count;
1392 for (irelscan = internal_relocs; irelscan < irelscanend; irelscan++)
1393 {
1394 struct internal_syment sym;
1395
17505c5c
NC		 1396#ifdef COFF_WITH_PE
1397 if (irelscan->r_type != R_SH_IMM32
1398 && irelscan->r_type != R_SH_IMAGEBASE
1399 && irelscan->r_type != R_SH_IMM32CE)
1400#else
252b5132 1401 if (irelscan->r_type != R_SH_IMM32)
17505c5c 1402#endif
252b5132
RH		 1403 continue;
1404
1405 bfd_coff_swap_sym_in (abfd,
1406 ((bfd_byte *) obj_coff_external_syms (abfd)
1407 + (irelscan->r_symndx
1408 * bfd_coff_symesz (abfd))),
1409 &sym);
1410 if (sym.n_sclass != C_EXT
1411 && sym.n_scnum == sec->target_index
1412 && ((bfd_vma) sym.n_value <= addr
1413 || (bfd_vma) sym.n_value >= toaddr))
1414 {
1415 bfd_vma val;
1416
1417 if (ocontents == NULL)
1418 {
1419 if (coff_section_data (abfd, o)->contents != NULL)
1420 ocontents = coff_section_data (abfd, o)->contents;
1421 else
1422 {
eea6121a
AM		 1423 if (!bfd_malloc_and_get_section (abfd, o, &ocontents))
1424 return FALSE;
252b5132 1425 /* We always cache the section contents.
07d6d2b8
AM		 1426 Perhaps, if info->keep_memory is FALSE, we
1427 should free them, if we are permitted to,
1428 when we leave sh_coff_relax_section. */
252b5132
RH		 1429 coff_section_data (abfd, o)->contents = ocontents;
1430 }
1431 }
1432
1433 val = bfd_get_32 (abfd, ocontents + irelscan->r_vaddr - o->vma);
1434 val += sym.n_value;
1435 if (val > addr && val < toaddr)
1436 bfd_put_32 (abfd, val - count,
1437 ocontents + irelscan->r_vaddr - o->vma);
1438
b34976b6 1439 coff_section_data (abfd, o)->keep_contents = TRUE;
252b5132
RH		 1440 }
1441 }
1442 }
1443
1444 /* Adjusting the internal symbols will not work if something has
1445 already retrieved the generic symbols. It would be possible to
1446 make this work by adjusting the generic symbols at the same time.
1447 However, this case should not arise in normal usage. */
1448 if (obj_symbols (abfd) != NULL
1449 || obj_raw_syments (abfd) != NULL)
1450 {
4eca0228 1451 _bfd_error_handler
871b3ab2 1452 (_("%pB: fatal: generic symbols retrieved before relaxing"), abfd);
252b5132 1453 bfd_set_error (bfd_error_invalid_operation);
b34976b6 1454 return FALSE;
252b5132
RH		 1455 }
1456
1457 /* Adjust all the symbols. */
1458 sym_hash = obj_coff_sym_hashes (abfd);
1459 symesz = bfd_coff_symesz (abfd);
1460 esym = (bfd_byte *) obj_coff_external_syms (abfd);
1461 esymend = esym + obj_raw_syment_count (abfd) * symesz;
1462 while (esym < esymend)
1463 {
1464 struct internal_syment isym;
1465
2c3fc389 1466 bfd_coff_swap_sym_in (abfd, esym, &isym);
252b5132
RH		 1467
1468 if (isym.n_scnum == sec->target_index
1469 && (bfd_vma) isym.n_value > addr
1470 && (bfd_vma) isym.n_value < toaddr)
1471 {
1472 isym.n_value -= count;
1473
2c3fc389 1474 bfd_coff_swap_sym_out (abfd, &isym, esym);
252b5132
RH		 1475
1476 if (*sym_hash != NULL)
1477 {
1478 BFD_ASSERT ((*sym_hash)->root.type == bfd_link_hash_defined
1479 || (*sym_hash)->root.type == bfd_link_hash_defweak);
1480 BFD_ASSERT ((*sym_hash)->root.u.def.value >= addr
1481 && (*sym_hash)->root.u.def.value < toaddr);
1482 (*sym_hash)->root.u.def.value -= count;
1483 }
1484 }
1485
1486 esym += (isym.n_numaux + 1) * symesz;
1487 sym_hash += isym.n_numaux + 1;
1488 }
1489
1490 /* See if we can move the ALIGN reloc forward. We have adjusted
1491 r_vaddr for it already. */
1492 if (irelalign != NULL)
1493 {
1494 bfd_vma alignto, alignaddr;
1495
1496 alignto = BFD_ALIGN (toaddr, 1 << irelalign->r_offset);
1497 alignaddr = BFD_ALIGN (irelalign->r_vaddr - sec->vma,
1498 1 << irelalign->r_offset);
1499 if (alignto != alignaddr)
1500 {
1501 /* Tail recursion. */
1502 return sh_relax_delete_bytes (abfd, sec, alignaddr,
dc810e39 1503 (int) (alignto - alignaddr));
252b5132
RH		 1504 }
1505 }
1506
b34976b6 1507 return TRUE;
252b5132
RH		 1508}
1509\f
1510/* This is yet another version of the SH opcode table, used to rapidly
1511 get information about a particular instruction. */
1512
1513/* The opcode map is represented by an array of these structures. The
1514 array is indexed by the high order four bits in the instruction. */
1515
1516struct sh_major_opcode
1517{
1518 /* A pointer to the instruction list. This is an array which
1519 contains all the instructions with this major opcode. */
1520 const struct sh_minor_opcode *minor_opcodes;
1521 /* The number of elements in minor_opcodes. */
1522 unsigned short count;
1523};
1524
1525/* This structure holds information for a set of SH opcodes. The
1526 instruction code is anded with the mask value, and the resulting
1527 value is used to search the order opcode list. */
1528
1529struct sh_minor_opcode
1530{
1531 /* The sorted opcode list. */
1532 const struct sh_opcode *opcodes;
1533 /* The number of elements in opcodes. */
1534 unsigned short count;
1535 /* The mask value to use when searching the opcode list. */
1536 unsigned short mask;
1537};
1538
1539/* This structure holds information for an SH instruction. An array
1540 of these structures is sorted in order by opcode. */
1541
1542struct sh_opcode
1543{
1544 /* The code for this instruction, after it has been anded with the
1545 mask value in the sh_major_opcode structure. */
1546 unsigned short opcode;
1547 /* Flags for this instruction. */
86033394 1548 unsigned long flags;
252b5132
RH		 1549};
1550
1551/* Flag which appear in the sh_opcode structure. */
1552
1553/* This instruction loads a value from memory. */
1554#define LOAD (0x1)
1555
1556/* This instruction stores a value to memory. */
1557#define STORE (0x2)
1558
1559/* This instruction is a branch. */
1560#define BRANCH (0x4)
1561
1562/* This instruction has a delay slot. */
1563#define DELAY (0x8)
1564
1565/* This instruction uses the value in the register in the field at
1566 mask 0x0f00 of the instruction. */
1567#define USES1 (0x10)
84dcfba7 1568#define USES1_REG(x) ((x & 0x0f00) >> 8)
252b5132
RH		 1569
1570/* This instruction uses the value in the register in the field at
1571 mask 0x00f0 of the instruction. */
1572#define USES2 (0x20)
84dcfba7 1573#define USES2_REG(x) ((x & 0x00f0) >> 4)
252b5132
RH		 1574
1575/* This instruction uses the value in register 0. */
1576#define USESR0 (0x40)
1577
1578/* This instruction sets the value in the register in the field at
1579 mask 0x0f00 of the instruction. */
1580#define SETS1 (0x80)
84dcfba7 1581#define SETS1_REG(x) ((x & 0x0f00) >> 8)
252b5132
RH		 1582
1583/* This instruction sets the value in the register in the field at
1584 mask 0x00f0 of the instruction. */
1585#define SETS2 (0x100)
84dcfba7 1586#define SETS2_REG(x) ((x & 0x00f0) >> 4)
252b5132
RH		 1587
1588/* This instruction sets register 0. */
1589#define SETSR0 (0x200)
1590
1591/* This instruction sets a special register. */
1592#define SETSSP (0x400)
1593
1594/* This instruction uses a special register. */
1595#define USESSP (0x800)
1596
1597/* This instruction uses the floating point register in the field at
1598 mask 0x0f00 of the instruction. */
1599#define USESF1 (0x1000)
84dcfba7 1600#define USESF1_REG(x) ((x & 0x0f00) >> 8)
252b5132
RH		 1601
1602/* This instruction uses the floating point register in the field at
1603 mask 0x00f0 of the instruction. */
1604#define USESF2 (0x2000)
84dcfba7 1605#define USESF2_REG(x) ((x & 0x00f0) >> 4)
252b5132
RH		 1606
1607/* This instruction uses floating point register 0. */
1608#define USESF0 (0x4000)
1609
1610/* This instruction sets the floating point register in the field at
1611 mask 0x0f00 of the instruction. */
1612#define SETSF1 (0x8000)
84dcfba7 1613#define SETSF1_REG(x) ((x & 0x0f00) >> 8)
252b5132 1614
d4845d57
JR		 1615#define USESAS (0x10000)
1616#define USESAS_REG(x) (((((x) >> 8) - 2) & 3) + 2)
1617#define USESR8 (0x20000)
1618#define SETSAS (0x40000)
1619#define SETSAS_REG(x) USESAS_REG (x)
1620
8d6ad26e
AM		 1621#define MAP(a) a, sizeof a / sizeof a[0]
1622
86033394 1623#ifndef COFF_IMAGE_WITH_PE
252b5132 1624
8d6ad26e 1625/* The opcode maps. */
252b5132
RH		 1626
1627static const struct sh_opcode sh_opcode00[] =
1628{
1629 { 0x0008, SETSSP }, /* clrt */
1630 { 0x0009, 0 }, /* nop */
1631 { 0x000b, BRANCH | DELAY | USESSP }, /* rts */
1632 { 0x0018, SETSSP }, /* sett */
1633 { 0x0019, SETSSP }, /* div0u */
1634 { 0x001b, 0 }, /* sleep */
1635 { 0x0028, SETSSP }, /* clrmac */
1636 { 0x002b, BRANCH | DELAY | SETSSP }, /* rte */
1637 { 0x0038, USESSP | SETSSP }, /* ldtlb */
1638 { 0x0048, SETSSP }, /* clrs */
1639 { 0x0058, SETSSP } /* sets */
1640};
1641
1642static const struct sh_opcode sh_opcode01[] =
1643{
252b5132
RH		 1644 { 0x0003, BRANCH | DELAY | USES1 | SETSSP }, /* bsrf rn */
1645 { 0x000a, SETS1 | USESSP }, /* sts mach,rn */
252b5132 1646 { 0x001a, SETS1 | USESSP }, /* sts macl,rn */
252b5132
RH		 1647 { 0x0023, BRANCH | DELAY | USES1 }, /* braf rn */
1648 { 0x0029, SETS1 | USESSP }, /* movt rn */
1649 { 0x002a, SETS1 | USESSP }, /* sts pr,rn */
d4845d57
JR		 1650 { 0x005a, SETS1 | USESSP }, /* sts fpul,rn */
1651 { 0x006a, SETS1 | USESSP }, /* sts fpscr,rn / sts dsr,rn */
1652 { 0x0083, LOAD | USES1 }, /* pref @rn */
1653 { 0x007a, SETS1 | USESSP }, /* sts a0,rn */
1654 { 0x008a, SETS1 | USESSP }, /* sts x0,rn */
1655 { 0x009a, SETS1 | USESSP }, /* sts x1,rn */
1656 { 0x00aa, SETS1 | USESSP }, /* sts y0,rn */
1657 { 0x00ba, SETS1 | USESSP } /* sts y1,rn */
1658};
1659
252b5132
RH		 1660static const struct sh_opcode sh_opcode02[] =
1661{
d4845d57 1662 { 0x0002, SETS1 | USESSP }, /* stc <special_reg>,rn */
252b5132
RH		 1663 { 0x0004, STORE | USES1 | USES2 | USESR0 }, /* mov.b rm,@(r0,rn) */
1664 { 0x0005, STORE | USES1 | USES2 | USESR0 }, /* mov.w rm,@(r0,rn) */
1665 { 0x0006, STORE | USES1 | USES2 | USESR0 }, /* mov.l rm,@(r0,rn) */
1666 { 0x0007, SETSSP | USES1 | USES2 }, /* mul.l rm,rn */
1667 { 0x000c, LOAD | SETS1 | USES2 | USESR0 }, /* mov.b @(r0,rm),rn */
1668 { 0x000d, LOAD | SETS1 | USES2 | USESR0 }, /* mov.w @(r0,rm),rn */
1669 { 0x000e, LOAD | SETS1 | USES2 | USESR0 }, /* mov.l @(r0,rm),rn */
1670 { 0x000f, LOAD|SETS1|SETS2|SETSSP|USES1|USES2|USESSP }, /* mac.l @rm+,@rn+ */
1671};
1672
1673static const struct sh_minor_opcode sh_opcode0[] =
1674{
1675 { MAP (sh_opcode00), 0xffff },
1676 { MAP (sh_opcode01), 0xf0ff },
1677 { MAP (sh_opcode02), 0xf00f }
1678};
1679
1680static const struct sh_opcode sh_opcode10[] =
1681{
1682 { 0x1000, STORE | USES1 | USES2 } /* mov.l rm,@(disp,rn) */
1683};
1684
1685static const struct sh_minor_opcode sh_opcode1[] =
1686{
1687 { MAP (sh_opcode10), 0xf000 }
1688};
1689
1690static const struct sh_opcode sh_opcode20[] =
1691{
1692 { 0x2000, STORE | USES1 | USES2 }, /* mov.b rm,@rn */
1693 { 0x2001, STORE | USES1 | USES2 }, /* mov.w rm,@rn */
1694 { 0x2002, STORE | USES1 | USES2 }, /* mov.l rm,@rn */
1695 { 0x2004, STORE | SETS1 | USES1 | USES2 }, /* mov.b rm,@-rn */
1696 { 0x2005, STORE | SETS1 | USES1 | USES2 }, /* mov.w rm,@-rn */
1697 { 0x2006, STORE | SETS1 | USES1 | USES2 }, /* mov.l rm,@-rn */
1698 { 0x2007, SETSSP | USES1 | USES2 | USESSP }, /* div0s */
1699 { 0x2008, SETSSP | USES1 | USES2 }, /* tst rm,rn */
1700 { 0x2009, SETS1 | USES1 | USES2 }, /* and rm,rn */
1701 { 0x200a, SETS1 | USES1 | USES2 }, /* xor rm,rn */
1702 { 0x200b, SETS1 | USES1 | USES2 }, /* or rm,rn */
1703 { 0x200c, SETSSP | USES1 | USES2 }, /* cmp/str rm,rn */
1704 { 0x200d, SETS1 | USES1 | USES2 }, /* xtrct rm,rn */
1705 { 0x200e, SETSSP | USES1 | USES2 }, /* mulu.w rm,rn */
1706 { 0x200f, SETSSP | USES1 | USES2 } /* muls.w rm,rn */
1707};
1708
1709static const struct sh_minor_opcode sh_opcode2[] =
1710{
1711 { MAP (sh_opcode20), 0xf00f }
1712};
1713
1714static const struct sh_opcode sh_opcode30[] =
1715{
1716 { 0x3000, SETSSP | USES1 | USES2 }, /* cmp/eq rm,rn */
1717 { 0x3002, SETSSP | USES1 | USES2 }, /* cmp/hs rm,rn */
1718 { 0x3003, SETSSP | USES1 | USES2 }, /* cmp/ge rm,rn */
1719 { 0x3004, SETSSP | USESSP | USES1 | USES2 }, /* div1 rm,rn */
1720 { 0x3005, SETSSP | USES1 | USES2 }, /* dmulu.l rm,rn */
1721 { 0x3006, SETSSP | USES1 | USES2 }, /* cmp/hi rm,rn */
1722 { 0x3007, SETSSP | USES1 | USES2 }, /* cmp/gt rm,rn */
1723 { 0x3008, SETS1 | USES1 | USES2 }, /* sub rm,rn */
1724 { 0x300a, SETS1 | SETSSP | USES1 | USES2 | USESSP }, /* subc rm,rn */
1725 { 0x300b, SETS1 | SETSSP | USES1 | USES2 }, /* subv rm,rn */
1726 { 0x300c, SETS1 | USES1 | USES2 }, /* add rm,rn */
1727 { 0x300d, SETSSP | USES1 | USES2 }, /* dmuls.l rm,rn */
1728 { 0x300e, SETS1 | SETSSP | USES1 | USES2 | USESSP }, /* addc rm,rn */
1729 { 0x300f, SETS1 | SETSSP | USES1 | USES2 } /* addv rm,rn */
1730};
1731
1732static const struct sh_minor_opcode sh_opcode3[] =
1733{
1734 { MAP (sh_opcode30), 0xf00f }
1735};
1736
1737static const struct sh_opcode sh_opcode40[] =
1738{
1739 { 0x4000, SETS1 | SETSSP | USES1 }, /* shll rn */
1740 { 0x4001, SETS1 | SETSSP | USES1 }, /* shlr rn */
1741 { 0x4002, STORE | SETS1 | USES1 | USESSP }, /* sts.l mach,@-rn */
252b5132
RH		 1742 { 0x4004, SETS1 | SETSSP | USES1 }, /* rotl rn */
1743 { 0x4005, SETS1 | SETSSP | USES1 }, /* rotr rn */
1744 { 0x4006, LOAD | SETS1 | SETSSP | USES1 }, /* lds.l @rm+,mach */
252b5132
RH		 1745 { 0x4008, SETS1 | USES1 }, /* shll2 rn */
1746 { 0x4009, SETS1 | USES1 }, /* shlr2 rn */
1747 { 0x400a, SETSSP | USES1 }, /* lds rm,mach */
1748 { 0x400b, BRANCH | DELAY | USES1 }, /* jsr @rn */
252b5132
RH		 1749 { 0x4010, SETS1 | SETSSP | USES1 }, /* dt rn */
1750 { 0x4011, SETSSP | USES1 }, /* cmp/pz rn */
1751 { 0x4012, STORE | SETS1 | USES1 | USESSP }, /* sts.l macl,@-rn */
d4845d57 1752 { 0x4014, SETSSP | USES1 }, /* setrc rm */
252b5132
RH		 1753 { 0x4015, SETSSP | USES1 }, /* cmp/pl rn */
1754 { 0x4016, LOAD | SETS1 | SETSSP | USES1 }, /* lds.l @rm+,macl */
252b5132
RH		 1755 { 0x4018, SETS1 | USES1 }, /* shll8 rn */
1756 { 0x4019, SETS1 | USES1 }, /* shlr8 rn */
1757 { 0x401a, SETSSP | USES1 }, /* lds rm,macl */
1758 { 0x401b, LOAD | SETSSP | USES1 }, /* tas.b @rn */
252b5132
RH		 1759 { 0x4020, SETS1 | SETSSP | USES1 }, /* shal rn */
1760 { 0x4021, SETS1 | SETSSP | USES1 }, /* shar rn */
1761 { 0x4022, STORE | SETS1 | USES1 | USESSP }, /* sts.l pr,@-rn */
252b5132
RH		 1762 { 0x4024, SETS1 | SETSSP | USES1 | USESSP }, /* rotcl rn */
1763 { 0x4025, SETS1 | SETSSP | USES1 | USESSP }, /* rotcr rn */
1764 { 0x4026, LOAD | SETS1 | SETSSP | USES1 }, /* lds.l @rm+,pr */
252b5132
RH		 1765 { 0x4028, SETS1 | USES1 }, /* shll16 rn */
1766 { 0x4029, SETS1 | USES1 }, /* shlr16 rn */
1767 { 0x402a, SETSSP | USES1 }, /* lds rm,pr */
1768 { 0x402b, BRANCH | DELAY | USES1 }, /* jmp @rn */
d4845d57
JR		 1769 { 0x4052, STORE | SETS1 | USES1 | USESSP }, /* sts.l fpul,@-rn */
1770 { 0x4056, LOAD | SETS1 | SETSSP | USES1 }, /* lds.l @rm+,fpul */
1771 { 0x405a, SETSSP | USES1 }, /* lds.l rm,fpul */
1772 { 0x4062, STORE | SETS1 | USES1 | USESSP }, /* sts.l fpscr / dsr,@-rn */
1773 { 0x4066, LOAD | SETS1 | SETSSP | USES1 }, /* lds.l @rm+,fpscr / dsr */
1774 { 0x406a, SETSSP | USES1 }, /* lds rm,fpscr / lds rm,dsr */
1775 { 0x4072, STORE | SETS1 | USES1 | USESSP }, /* sts.l a0,@-rn */
1776 { 0x4076, LOAD | SETS1 | SETSSP | USES1 }, /* lds.l @rm+,a0 */
1777 { 0x407a, SETSSP | USES1 }, /* lds.l rm,a0 */
1778 { 0x4082, STORE | SETS1 | USES1 | USESSP }, /* sts.l x0,@-rn */
1779 { 0x4086, LOAD | SETS1 | SETSSP | USES1 }, /* lds.l @rm+,x0 */
1780 { 0x408a, SETSSP | USES1 }, /* lds.l rm,x0 */
1781 { 0x4092, STORE | SETS1 | USES1 | USESSP }, /* sts.l x1,@-rn */
1782 { 0x4096, LOAD | SETS1 | SETSSP | USES1 }, /* lds.l @rm+,x1 */
1783 { 0x409a, SETSSP | USES1 }, /* lds.l rm,x1 */
1784 { 0x40a2, STORE | SETS1 | USES1 | USESSP }, /* sts.l y0,@-rn */
1785 { 0x40a6, LOAD | SETS1 | SETSSP | USES1 }, /* lds.l @rm+,y0 */
1786 { 0x40aa, SETSSP | USES1 }, /* lds.l rm,y0 */
1787 { 0x40b2, STORE | SETS1 | USES1 | USESSP }, /* sts.l y1,@-rn */
1788 { 0x40b6, LOAD | SETS1 | SETSSP | USES1 }, /* lds.l @rm+,y1 */
1789 { 0x40ba, SETSSP | USES1 } /* lds.l rm,y1 */
252b5132
RH		 1790};
1791
1792static const struct sh_opcode sh_opcode41[] =
1793{
d4845d57
JR		 1794 { 0x4003, STORE | SETS1 | USES1 | USESSP }, /* stc.l <special_reg>,@-rn */
1795 { 0x4007, LOAD | SETS1 | SETSSP | USES1 }, /* ldc.l @rm+,<special_reg> */
1796 { 0x400c, SETS1 | USES1 | USES2 }, /* shad rm,rn */
1797 { 0x400d, SETS1 | USES1 | USES2 }, /* shld rm,rn */
1798 { 0x400e, SETSSP | USES1 }, /* ldc rm,<special_reg> */
252b5132
RH		 1799 { 0x400f, LOAD|SETS1|SETS2|SETSSP|USES1|USES2|USESSP }, /* mac.w @rm+,@rn+ */
1800};
1801
1802static const struct sh_minor_opcode sh_opcode4[] =
1803{
1804 { MAP (sh_opcode40), 0xf0ff },
d4845d57 1805 { MAP (sh_opcode41), 0xf00f }
252b5132
RH		 1806};
1807
1808static const struct sh_opcode sh_opcode50[] =
1809{
1810 { 0x5000, LOAD | SETS1 | USES2 } /* mov.l @(disp,rm),rn */
1811};
1812
1813static const struct sh_minor_opcode sh_opcode5[] =
1814{
1815 { MAP (sh_opcode50), 0xf000 }
1816};
1817
1818static const struct sh_opcode sh_opcode60[] =
1819{
1820 { 0x6000, LOAD | SETS1 | USES2 }, /* mov.b @rm,rn */
1821 { 0x6001, LOAD | SETS1 | USES2 }, /* mov.w @rm,rn */
1822 { 0x6002, LOAD | SETS1 | USES2 }, /* mov.l @rm,rn */
1823 { 0x6003, SETS1 | USES2 }, /* mov rm,rn */
1824 { 0x6004, LOAD | SETS1 | SETS2 | USES2 }, /* mov.b @rm+,rn */
1825 { 0x6005, LOAD | SETS1 | SETS2 | USES2 }, /* mov.w @rm+,rn */
1826 { 0x6006, LOAD | SETS1 | SETS2 | USES2 }, /* mov.l @rm+,rn */
1827 { 0x6007, SETS1 | USES2 }, /* not rm,rn */
1828 { 0x6008, SETS1 | USES2 }, /* swap.b rm,rn */
1829 { 0x6009, SETS1 | USES2 }, /* swap.w rm,rn */
1830 { 0x600a, SETS1 | SETSSP | USES2 | USESSP }, /* negc rm,rn */
1831 { 0x600b, SETS1 | USES2 }, /* neg rm,rn */
1832 { 0x600c, SETS1 | USES2 }, /* extu.b rm,rn */
1833 { 0x600d, SETS1 | USES2 }, /* extu.w rm,rn */
1834 { 0x600e, SETS1 | USES2 }, /* exts.b rm,rn */
1835 { 0x600f, SETS1 | USES2 } /* exts.w rm,rn */
1836};
1837
1838static const struct sh_minor_opcode sh_opcode6[] =
1839{
1840 { MAP (sh_opcode60), 0xf00f }
1841};
1842
1843static const struct sh_opcode sh_opcode70[] =
1844{
1845 { 0x7000, SETS1 | USES1 } /* add #imm,rn */
1846};
1847
1848static const struct sh_minor_opcode sh_opcode7[] =
1849{
1850 { MAP (sh_opcode70), 0xf000 }
1851};
1852
1853static const struct sh_opcode sh_opcode80[] =
1854{
1855 { 0x8000, STORE | USES2 | USESR0 }, /* mov.b r0,@(disp,rn) */
1856 { 0x8100, STORE | USES2 | USESR0 }, /* mov.w r0,@(disp,rn) */
d4845d57 1857 { 0x8200, SETSSP }, /* setrc #imm */
252b5132
RH		 1858 { 0x8400, LOAD | SETSR0 | USES2 }, /* mov.b @(disp,rm),r0 */
1859 { 0x8500, LOAD | SETSR0 | USES2 }, /* mov.w @(disp,rn),r0 */
1860 { 0x8800, SETSSP | USESR0 }, /* cmp/eq #imm,r0 */
1861 { 0x8900, BRANCH | USESSP }, /* bt label */
1862 { 0x8b00, BRANCH | USESSP }, /* bf label */
d4845d57 1863 { 0x8c00, SETSSP }, /* ldrs @(disp,pc) */
252b5132 1864 { 0x8d00, BRANCH | DELAY | USESSP }, /* bt/s label */
d4845d57 1865 { 0x8e00, SETSSP }, /* ldre @(disp,pc) */
252b5132
RH		 1866 { 0x8f00, BRANCH | DELAY | USESSP } /* bf/s label */
1867};
1868
1869static const struct sh_minor_opcode sh_opcode8[] =
1870{
1871 { MAP (sh_opcode80), 0xff00 }
1872};
1873
1874static const struct sh_opcode sh_opcode90[] =
1875{
1876 { 0x9000, LOAD | SETS1 } /* mov.w @(disp,pc),rn */
1877};
1878
1879static const struct sh_minor_opcode sh_opcode9[] =
1880{
1881 { MAP (sh_opcode90), 0xf000 }
1882};
1883
1884static const struct sh_opcode sh_opcodea0[] =
1885{
1886 { 0xa000, BRANCH | DELAY } /* bra label */
1887};
1888
1889static const struct sh_minor_opcode sh_opcodea[] =
1890{
1891 { MAP (sh_opcodea0), 0xf000 }
1892};
1893
1894static const struct sh_opcode sh_opcodeb0[] =
1895{
1896 { 0xb000, BRANCH | DELAY } /* bsr label */
1897};
1898
1899static const struct sh_minor_opcode sh_opcodeb[] =
1900{
1901 { MAP (sh_opcodeb0), 0xf000 }
1902};
1903
1904static const struct sh_opcode sh_opcodec0[] =
1905{
1906 { 0xc000, STORE | USESR0 | USESSP }, /* mov.b r0,@(disp,gbr) */
1907 { 0xc100, STORE | USESR0 | USESSP }, /* mov.w r0,@(disp,gbr) */
1908 { 0xc200, STORE | USESR0 | USESSP }, /* mov.l r0,@(disp,gbr) */
1909 { 0xc300, BRANCH | USESSP }, /* trapa #imm */
1910 { 0xc400, LOAD | SETSR0 | USESSP }, /* mov.b @(disp,gbr),r0 */
1911 { 0xc500, LOAD | SETSR0 | USESSP }, /* mov.w @(disp,gbr),r0 */
1912 { 0xc600, LOAD | SETSR0 | USESSP }, /* mov.l @(disp,gbr),r0 */
1913 { 0xc700, SETSR0 }, /* mova @(disp,pc),r0 */
1914 { 0xc800, SETSSP | USESR0 }, /* tst #imm,r0 */
1915 { 0xc900, SETSR0 | USESR0 }, /* and #imm,r0 */
1916 { 0xca00, SETSR0 | USESR0 }, /* xor #imm,r0 */
1917 { 0xcb00, SETSR0 | USESR0 }, /* or #imm,r0 */
1918 { 0xcc00, LOAD | SETSSP | USESR0 | USESSP }, /* tst.b #imm,@(r0,gbr) */
1919 { 0xcd00, LOAD | STORE | USESR0 | USESSP }, /* and.b #imm,@(r0,gbr) */
1920 { 0xce00, LOAD | STORE | USESR0 | USESSP }, /* xor.b #imm,@(r0,gbr) */
1921 { 0xcf00, LOAD | STORE | USESR0 | USESSP } /* or.b #imm,@(r0,gbr) */
1922};
1923
1924static const struct sh_minor_opcode sh_opcodec[] =
1925{
1926 { MAP (sh_opcodec0), 0xff00 }
1927};
1928
1929static const struct sh_opcode sh_opcoded0[] =
1930{
1931 { 0xd000, LOAD | SETS1 } /* mov.l @(disp,pc),rn */
1932};
1933
1934static const struct sh_minor_opcode sh_opcoded[] =
1935{
1936 { MAP (sh_opcoded0), 0xf000 }
1937};
1938
1939static const struct sh_opcode sh_opcodee0[] =
1940{
1941 { 0xe000, SETS1 } /* mov #imm,rn */
1942};
1943
1944static const struct sh_minor_opcode sh_opcodee[] =
1945{
1946 { MAP (sh_opcodee0), 0xf000 }
1947};
1948
1949static const struct sh_opcode sh_opcodef0[] =
1950{
1951 { 0xf000, SETSF1 | USESF1 | USESF2 }, /* fadd fm,fn */
1952 { 0xf001, SETSF1 | USESF1 | USESF2 }, /* fsub fm,fn */
1953 { 0xf002, SETSF1 | USESF1 | USESF2 }, /* fmul fm,fn */
1954 { 0xf003, SETSF1 | USESF1 | USESF2 }, /* fdiv fm,fn */
1955 { 0xf004, SETSSP | USESF1 | USESF2 }, /* fcmp/eq fm,fn */
1956 { 0xf005, SETSSP | USESF1 | USESF2 }, /* fcmp/gt fm,fn */
1957 { 0xf006, LOAD | SETSF1 | USES2 | USESR0 }, /* fmov.s @(r0,rm),fn */
1958 { 0xf007, STORE | USES1 | USESF2 | USESR0 }, /* fmov.s fm,@(r0,rn) */
1959 { 0xf008, LOAD | SETSF1 | USES2 }, /* fmov.s @rm,fn */
1960 { 0xf009, LOAD | SETS2 | SETSF1 | USES2 }, /* fmov.s @rm+,fn */
1961 { 0xf00a, STORE | USES1 | USESF2 }, /* fmov.s fm,@rn */
1962 { 0xf00b, STORE | SETS1 | USES1 | USESF2 }, /* fmov.s fm,@-rn */
1963 { 0xf00c, SETSF1 | USESF2 }, /* fmov fm,fn */
1964 { 0xf00e, SETSF1 | USESF1 | USESF2 | USESF0 } /* fmac f0,fm,fn */
1965};
1966
1967static const struct sh_opcode sh_opcodef1[] =
1968{
1969 { 0xf00d, SETSF1 | USESSP }, /* fsts fpul,fn */
1970 { 0xf01d, SETSSP | USESF1 }, /* flds fn,fpul */
1971 { 0xf02d, SETSF1 | USESSP }, /* float fpul,fn */
1972 { 0xf03d, SETSSP | USESF1 }, /* ftrc fn,fpul */
1973 { 0xf04d, SETSF1 | USESF1 }, /* fneg fn */
1974 { 0xf05d, SETSF1 | USESF1 }, /* fabs fn */
1975 { 0xf06d, SETSF1 | USESF1 }, /* fsqrt fn */
1976 { 0xf07d, SETSSP | USESF1 }, /* ftst/nan fn */
1977 { 0xf08d, SETSF1 }, /* fldi0 fn */
1978 { 0xf09d, SETSF1 } /* fldi1 fn */
1979};
1980
1981static const struct sh_minor_opcode sh_opcodef[] =
1982{
1983 { MAP (sh_opcodef0), 0xf00f },
1984 { MAP (sh_opcodef1), 0xf0ff }
1985};
1986
d4845d57 1987static struct sh_major_opcode sh_opcodes[] =
252b5132
RH		 1988{
1989 { MAP (sh_opcode0) },
1990 { MAP (sh_opcode1) },
1991 { MAP (sh_opcode2) },
1992 { MAP (sh_opcode3) },
1993 { MAP (sh_opcode4) },
1994 { MAP (sh_opcode5) },
1995 { MAP (sh_opcode6) },
1996 { MAP (sh_opcode7) },
1997 { MAP (sh_opcode8) },
1998 { MAP (sh_opcode9) },
1999 { MAP (sh_opcodea) },
2000 { MAP (sh_opcodeb) },
2001 { MAP (sh_opcodec) },
2002 { MAP (sh_opcoded) },
2003 { MAP (sh_opcodee) },
2004 { MAP (sh_opcodef) }
2005};
2006
d4845d57
JR		 2007/* The double data transfer / parallel processing insns are not
2008 described here. This will cause sh_align_load_span to leave them alone. */
2009
2010static const struct sh_opcode sh_dsp_opcodef0[] =
2011{
2012 { 0xf400, USESAS | SETSAS | LOAD | SETSSP }, /* movs.x @-as,ds */
2013 { 0xf401, USESAS | SETSAS | STORE | USESSP }, /* movs.x ds,@-as */
2014 { 0xf404, USESAS | LOAD | SETSSP }, /* movs.x @as,ds */
2015 { 0xf405, USESAS | STORE | USESSP }, /* movs.x ds,@as */
2016 { 0xf408, USESAS | SETSAS | LOAD | SETSSP }, /* movs.x @as+,ds */
2017 { 0xf409, USESAS | SETSAS | STORE | USESSP }, /* movs.x ds,@as+ */
2018 { 0xf40c, USESAS | SETSAS | LOAD | SETSSP | USESR8 }, /* movs.x @as+r8,ds */
2019 { 0xf40d, USESAS | SETSAS | STORE | USESSP | USESR8 } /* movs.x ds,@as+r8 */
2020};
2021
2022static const struct sh_minor_opcode sh_dsp_opcodef[] =
2023{
2024 { MAP (sh_dsp_opcodef0), 0xfc0d }
2025};
2026
252b5132
RH		 2027/* Given an instruction, return a pointer to the corresponding
2028 sh_opcode structure. Return NULL if the instruction is not
2029 recognized. */
2030
2031static const struct sh_opcode *
2c3fc389 2032sh_insn_info (unsigned int insn)
252b5132
RH		 2033{
2034 const struct sh_major_opcode *maj;
2035 const struct sh_minor_opcode *min, *minend;
2036
2037 maj = &sh_opcodes[(insn & 0xf000) >> 12];
2038 min = maj->minor_opcodes;
2039 minend = min + maj->count;
2040 for (; min < minend; min++)
2041 {
2042 unsigned int l;
2043 const struct sh_opcode *op, *opend;
2044
2045 l = insn & min->mask;
2046 op = min->opcodes;
2047 opend = op + min->count;
2048
2049 /* Since the opcodes tables are sorted, we could use a binary
07d6d2b8 2050 search here if the count were above some cutoff value. */
252b5132
RH		 2051 for (; op < opend; op++)
2052 if (op->opcode == l)
2053 return op;
2054 }
2055
cbfe05c4 2056 return NULL;
252b5132
RH		 2057}
2058
2059/* See whether an instruction uses a general purpose register. */
2060
b34976b6 2061static bfd_boolean
2c3fc389
NC		 2062sh_insn_uses_reg (unsigned int insn,
2063 const struct sh_opcode *op,
2064 unsigned int reg)
252b5132
RH		 2065{
2066 unsigned int f;
2067
2068 f = op->flags;
2069
2070 if ((f & USES1) != 0
84dcfba7 2071 && USES1_REG (insn) == reg)
b34976b6 2072 return TRUE;
252b5132 2073 if ((f & USES2) != 0
84dcfba7 2074 && USES2_REG (insn) == reg)
b34976b6 2075 return TRUE;
252b5132
RH		 2076 if ((f & USESR0) != 0
2077 && reg == 0)
b34976b6 2078 return TRUE;
d4845d57 2079 if ((f & USESAS) && reg == USESAS_REG (insn))
b34976b6 2080 return TRUE;
d4845d57 2081 if ((f & USESR8) && reg == 8)
b34976b6 2082 return TRUE;
252b5132 2083
b34976b6 2084 return FALSE;
252b5132 2085}
17505c5c 2086
84dcfba7
JR		 2087/* See whether an instruction sets a general purpose register. */
2088
b34976b6 2089static bfd_boolean
2c3fc389
NC		 2090sh_insn_sets_reg (unsigned int insn,
2091 const struct sh_opcode *op,
2092 unsigned int reg)
84dcfba7
JR		 2093{
2094 unsigned int f;
2095
2096 f = op->flags;
2097
2098 if ((f & SETS1) != 0
2099 && SETS1_REG (insn) == reg)
b34976b6 2100 return TRUE;
84dcfba7
JR		 2101 if ((f & SETS2) != 0
2102 && SETS2_REG (insn) == reg)
b34976b6 2103 return TRUE;
84dcfba7
JR		 2104 if ((f & SETSR0) != 0
2105 && reg == 0)
b34976b6 2106 return TRUE;
d4845d57 2107 if ((f & SETSAS) && reg == SETSAS_REG (insn))
b34976b6 2108 return TRUE;
84dcfba7 2109
b34976b6 2110 return FALSE;
84dcfba7
JR		 2111}
2112
2c3fc389 2113/* See whether an instruction uses or sets a general purpose register */
84dcfba7 2114
b34976b6 2115static bfd_boolean
2c3fc389
NC		 2116sh_insn_uses_or_sets_reg (unsigned int insn,
2117 const struct sh_opcode *op,
2118 unsigned int reg)
84dcfba7 2119{
2c3fc389 2120 if (sh_insn_uses_reg (insn, op, reg))
b34976b6 2121 return TRUE;
84dcfba7 2122
2c3fc389 2123 return sh_insn_sets_reg (insn, op, reg);
84dcfba7 2124}
252b5132
RH		 2125
2126/* See whether an instruction uses a floating point register. */
2127
b34976b6 2128static bfd_boolean
2c3fc389
NC		 2129sh_insn_uses_freg (unsigned int insn,
2130 const struct sh_opcode *op,
2131 unsigned int freg)
252b5132
RH		 2132{
2133 unsigned int f;
2134
2135 f = op->flags;
2136
2137 /* We can't tell if this is a double-precision insn, so just play safe
2138 and assume that it might be. So not only have we test FREG against
2139 itself, but also even FREG against FREG+1 - if the using insn uses
2140 just the low part of a double precision value - but also an odd
2141 FREG against FREG-1 - if the setting insn sets just the low part
2142 of a double precision value.
2143 So what this all boils down to is that we have to ignore the lowest
2144 bit of the register number. */
cbfe05c4 2145
252b5132 2146 if ((f & USESF1) != 0
84dcfba7 2147 && (USESF1_REG (insn) & 0xe) == (freg & 0xe))
b34976b6 2148 return TRUE;
252b5132 2149 if ((f & USESF2) != 0
84dcfba7 2150 && (USESF2_REG (insn) & 0xe) == (freg & 0xe))
b34976b6 2151 return TRUE;
252b5132
RH		 2152 if ((f & USESF0) != 0
2153 && freg == 0)
b34976b6 2154 return TRUE;
252b5132 2155
b34976b6 2156 return FALSE;
252b5132
RH		 2157}
2158
84dcfba7
JR		 2159/* See whether an instruction sets a floating point register. */
2160
b34976b6 2161static bfd_boolean
2c3fc389
NC		 2162sh_insn_sets_freg (unsigned int insn,
2163 const struct sh_opcode *op,
2164 unsigned int freg)
84dcfba7
JR		 2165{
2166 unsigned int f;
2167
2168 f = op->flags;
2169
2170 /* We can't tell if this is a double-precision insn, so just play safe
2171 and assume that it might be. So not only have we test FREG against
2172 itself, but also even FREG against FREG+1 - if the using insn uses
2173 just the low part of a double precision value - but also an odd
2174 FREG against FREG-1 - if the setting insn sets just the low part
2175 of a double precision value.
2176 So what this all boils down to is that we have to ignore the lowest
2177 bit of the register number. */
cbfe05c4 2178
84dcfba7
JR		 2179 if ((f & SETSF1) != 0
2180 && (SETSF1_REG (insn) & 0xe) == (freg & 0xe))
b34976b6 2181 return TRUE;
84dcfba7 2182
b34976b6 2183 return FALSE;
84dcfba7
JR		 2184}
2185
2c3fc389
NC		 2186/* See whether an instruction uses or sets a floating point register */
2187
2188static bfd_boolean
2189sh_insn_uses_or_sets_freg (unsigned int insn,
2190 const struct sh_opcode *op,
2191 unsigned int reg)
2192{
2193 if (sh_insn_uses_freg (insn, op, reg))
2194 return TRUE;
2195
2196 return sh_insn_sets_freg (insn, op, reg);
2197}
2198
252b5132
RH		 2199/* See whether instructions I1 and I2 conflict, assuming I1 comes
2200 before I2. OP1 and OP2 are the corresponding sh_opcode structures.
b34976b6 2201 This should return TRUE if there is a conflict, or FALSE if the
252b5132
RH		 2202 instructions can be swapped safely. */
2203
b34976b6 2204static bfd_boolean
2c3fc389
NC		 2205sh_insns_conflict (unsigned int i1,
2206 const struct sh_opcode *op1,
2207 unsigned int i2,
2208 const struct sh_opcode *op2)
252b5132
RH		 2209{
2210 unsigned int f1, f2;
2211
2212 f1 = op1->flags;
2213 f2 = op2->flags;
2214
2215 /* Load of fpscr conflicts with floating point operations.
2216 FIXME: shouldn't test raw opcodes here. */
2217 if (((i1 & 0xf0ff) == 0x4066 && (i2 & 0xf000) == 0xf000)
2218 || ((i2 & 0xf0ff) == 0x4066 && (i1 & 0xf000) == 0xf000))
b34976b6 2219 return TRUE;
252b5132
RH		 2220
2221 if ((f1 & (BRANCH | DELAY)) != 0
2222 || (f2 & (BRANCH | DELAY)) != 0)
b34976b6 2223 return TRUE;
252b5132 2224
84dcfba7
JR		 2225 if (((f1 | f2) & SETSSP)
2226 && (f1 & (SETSSP | USESSP))
2227 && (f2 & (SETSSP | USESSP)))
b34976b6 2228 return TRUE;
252b5132
RH		 2229
2230 if ((f1 & SETS1) != 0
84dcfba7 2231 && sh_insn_uses_or_sets_reg (i2, op2, SETS1_REG (i1)))
b34976b6 2232 return TRUE;
252b5132 2233 if ((f1 & SETS2) != 0
84dcfba7 2234 && sh_insn_uses_or_sets_reg (i2, op2, SETS2_REG (i1)))
b34976b6 2235 return TRUE;
252b5132 2236 if ((f1 & SETSR0) != 0
84dcfba7 2237 && sh_insn_uses_or_sets_reg (i2, op2, 0))
b34976b6 2238 return TRUE;
d4845d57
JR		 2239 if ((f1 & SETSAS)
2240 && sh_insn_uses_or_sets_reg (i2, op2, SETSAS_REG (i1)))
b34976b6 2241 return TRUE;
252b5132 2242 if ((f1 & SETSF1) != 0
84dcfba7 2243 && sh_insn_uses_or_sets_freg (i2, op2, SETSF1_REG (i1)))
b34976b6 2244 return TRUE;
252b5132
RH		 2245
2246 if ((f2 & SETS1) != 0
84dcfba7 2247 && sh_insn_uses_or_sets_reg (i1, op1, SETS1_REG (i2)))
b34976b6 2248 return TRUE;
252b5132 2249 if ((f2 & SETS2) != 0
84dcfba7 2250 && sh_insn_uses_or_sets_reg (i1, op1, SETS2_REG (i2)))
b34976b6 2251 return TRUE;
252b5132 2252 if ((f2 & SETSR0) != 0
84dcfba7 2253 && sh_insn_uses_or_sets_reg (i1, op1, 0))
b34976b6 2254 return TRUE;
d4845d57
JR		 2255 if ((f2 & SETSAS)
2256 && sh_insn_uses_or_sets_reg (i1, op1, SETSAS_REG (i2)))
b34976b6 2257 return TRUE;
252b5132 2258 if ((f2 & SETSF1) != 0
84dcfba7 2259 && sh_insn_uses_or_sets_freg (i1, op1, SETSF1_REG (i2)))
b34976b6 2260 return TRUE;
252b5132
RH		 2261
2262 /* The instructions do not conflict. */
b34976b6 2263 return FALSE;
252b5132
RH		 2264}
2265
2266/* I1 is a load instruction, and I2 is some other instruction. Return
b34976b6 2267 TRUE if I1 loads a register which I2 uses. */
252b5132 2268
b34976b6 2269static bfd_boolean
2c3fc389
NC		 2270sh_load_use (unsigned int i1,
2271 const struct sh_opcode *op1,
2272 unsigned int i2,
2273 const struct sh_opcode *op2)
252b5132
RH		 2274{
2275 unsigned int f1;
2276
2277 f1 = op1->flags;
2278
2279 if ((f1 & LOAD) == 0)
b34976b6 2280 return FALSE;
252b5132
RH		 2281
2282 /* If both SETS1 and SETSSP are set, that means a load to a special
2283 register using postincrement addressing mode, which we don't care
2284 about here. */
2285 if ((f1 & SETS1) != 0
2286 && (f1 & SETSSP) == 0
2287 && sh_insn_uses_reg (i2, op2, (i1 & 0x0f00) >> 8))
b34976b6 2288 return TRUE;
252b5132
RH		 2289
2290 if ((f1 & SETSR0) != 0
2291 && sh_insn_uses_reg (i2, op2, 0))
b34976b6 2292 return TRUE;
252b5132
RH		 2293
2294 if ((f1 & SETSF1) != 0
2295 && sh_insn_uses_freg (i2, op2, (i1 & 0x0f00) >> 8))
b34976b6 2296 return TRUE;
252b5132 2297
b34976b6 2298 return FALSE;
252b5132
RH		 2299}
2300
2301/* Try to align loads and stores within a span of memory. This is
2302 called by both the ELF and the COFF sh targets. ABFD and SEC are
2303 the BFD and section we are examining. CONTENTS is the contents of
2304 the section. SWAP is the routine to call to swap two instructions.
2305 RELOCS is a pointer to the internal relocation information, to be
2306 passed to SWAP. PLABEL is a pointer to the current label in a
2307 sorted list of labels; LABEL_END is the end of the list. START and
2308 STOP are the range of memory to examine. If a swap is made,
b34976b6 2309 *PSWAPPED is set to TRUE. */
252b5132 2310
86033394
NC		 2311#ifdef COFF_WITH_PE
2312static
2313#endif
b34976b6 2314bfd_boolean
2c3fc389
NC		 2315_bfd_sh_align_load_span (bfd *abfd,
2316 asection *sec,
2317 bfd_byte *contents,
2318 bfd_boolean (*swap) (bfd *, asection *, void *, bfd_byte *, bfd_vma),
2319 void * relocs,
2320 bfd_vma **plabel,
2321 bfd_vma *label_end,
2322 bfd_vma start,
2323 bfd_vma stop,
2324 bfd_boolean *pswapped)
252b5132 2325{
d4845d57
JR		 2326 int dsp = (abfd->arch_info->mach == bfd_mach_sh_dsp
2327 || abfd->arch_info->mach == bfd_mach_sh3_dsp);
252b5132
RH		 2328 bfd_vma i;
2329
d4845d57
JR		 2330 /* The SH4 has a Harvard architecture, hence aligning loads is not
2331 desirable. In fact, it is counter-productive, since it interferes
2332 with the schedules generated by the compiler. */
2333 if (abfd->arch_info->mach == bfd_mach_sh4)
b34976b6 2334 return TRUE;
d4845d57
JR		 2335
2336 /* If we are linking sh[3]-dsp code, swap the FPU instructions for DSP
2337 instructions. */
2338 if (dsp)
2339 {
2340 sh_opcodes[0xf].minor_opcodes = sh_dsp_opcodef;
4c0160b8 2341 sh_opcodes[0xf].count = sizeof sh_dsp_opcodef / sizeof sh_dsp_opcodef [0];
d4845d57
JR		 2342 }
2343
252b5132
RH		 2344 /* Instructions should be aligned on 2 byte boundaries. */
2345 if ((start & 1) == 1)
2346 ++start;
2347
2348 /* Now look through the unaligned addresses. */
2349 i = start;
2350 if ((i & 2) == 0)
2351 i += 2;
2352 for (; i < stop; i += 4)
2353 {
2354 unsigned int insn;
2355 const struct sh_opcode *op;
2356 unsigned int prev_insn = 0;
2357 const struct sh_opcode *prev_op = NULL;
2358
2359 insn = bfd_get_16 (abfd, contents + i);
2360 op = sh_insn_info (insn);
2361 if (op == NULL
2362 || (op->flags & (LOAD | STORE)) == 0)
2363 continue;
2364
2365 /* This is a load or store which is not on a four byte boundary. */
2366
2367 while (*plabel < label_end && **plabel < i)
2368 ++*plabel;
2369
2370 if (i > start)
2371 {
2372 prev_insn = bfd_get_16 (abfd, contents + i - 2);
d4845d57
JR		 2373 /* If INSN is the field b of a parallel processing insn, it is not
2374 a load / store after all. Note that the test here might mistake
2375 the field_b of a pcopy insn for the starting code of a parallel
2376 processing insn; this might miss a swapping opportunity, but at
2377 least we're on the safe side. */
2378 if (dsp && (prev_insn & 0xfc00) == 0xf800)
2379 continue;
2380
2381 /* Check if prev_insn is actually the field b of a parallel
2382 processing insn. Again, this can give a spurious match
2383 after a pcopy. */
2384 if (dsp && i - 2 > start)
2385 {
2386 unsigned pprev_insn = bfd_get_16 (abfd, contents + i - 4);
cbfe05c4 2387
d4845d57
JR		 2388 if ((pprev_insn & 0xfc00) == 0xf800)
2389 prev_op = NULL;
2390 else
2391 prev_op = sh_insn_info (prev_insn);
2392 }
2393 else
2394 prev_op = sh_insn_info (prev_insn);
252b5132
RH		 2395
2396 /* If the load/store instruction is in a delay slot, we
2397 can't swap. */
2398 if (prev_op == NULL
2399 || (prev_op->flags & DELAY) != 0)
2400 continue;
2401 }
2402 if (i > start
2403 && (*plabel >= label_end || **plabel != i)
2404 && prev_op != NULL
2405 && (prev_op->flags & (LOAD | STORE)) == 0
2406 && ! sh_insns_conflict (prev_insn, prev_op, insn, op))
2407 {
b34976b6 2408 bfd_boolean ok;
252b5132
RH		 2409
2410 /* The load/store instruction does not have a label, and
2411 there is a previous instruction; PREV_INSN is not
2412 itself a load/store instruction, and PREV_INSN and
2413 INSN do not conflict. */
2414
b34976b6 2415 ok = TRUE;
252b5132
RH		 2416
2417 if (i >= start + 4)
2418 {
2419 unsigned int prev2_insn;
2420 const struct sh_opcode *prev2_op;
2421
2422 prev2_insn = bfd_get_16 (abfd, contents + i - 4);
2423 prev2_op = sh_insn_info (prev2_insn);
2424
2425 /* If the instruction before PREV_INSN has a delay
2426 slot--that is, PREV_INSN is in a delay slot--we
2427 can not swap. */
2428 if (prev2_op == NULL
2429 || (prev2_op->flags & DELAY) != 0)
b34976b6 2430 ok = FALSE;
252b5132
RH		 2431
2432 /* If the instruction before PREV_INSN is a load,
2433 and it sets a register which INSN uses, then
2434 putting INSN immediately after PREV_INSN will
2435 cause a pipeline bubble, so there is no point to
2436 making the swap. */
2437 if (ok
2438 && (prev2_op->flags & LOAD) != 0
2439 && sh_load_use (prev2_insn, prev2_op, insn, op))
b34976b6 2440 ok = FALSE;
252b5132
RH		 2441 }
2442
2443 if (ok)
2444 {
2445 if (! (*swap) (abfd, sec, relocs, contents, i - 2))
b34976b6
AM		 2446 return FALSE;
2447 *pswapped = TRUE;
252b5132
RH		 2448 continue;
2449 }
2450 }
2451
2452 while (*plabel < label_end && **plabel < i + 2)
2453 ++*plabel;
2454
2455 if (i + 2 < stop
2456 && (*plabel >= label_end || **plabel != i + 2))
2457 {
2458 unsigned int next_insn;
2459 const struct sh_opcode *next_op;
2460
2461 /* There is an instruction after the load/store
2462 instruction, and it does not have a label. */
2463 next_insn = bfd_get_16 (abfd, contents + i + 2);
2464 next_op = sh_insn_info (next_insn);
2465 if (next_op != NULL
2466 && (next_op->flags & (LOAD | STORE)) == 0
2467 && ! sh_insns_conflict (insn, op, next_insn, next_op))
2468 {
b34976b6 2469 bfd_boolean ok;
252b5132
RH		 2470
2471 /* NEXT_INSN is not itself a load/store instruction,
2472 and it does not conflict with INSN. */
2473
b34976b6 2474 ok = TRUE;
252b5132
RH		 2475
2476 /* If PREV_INSN is a load, and it sets a register
2477 which NEXT_INSN uses, then putting NEXT_INSN
2478 immediately after PREV_INSN will cause a pipeline
2479 bubble, so there is no reason to make this swap. */
2480 if (prev_op != NULL
2481 && (prev_op->flags & LOAD) != 0
2482 && sh_load_use (prev_insn, prev_op, next_insn, next_op))
b34976b6 2483 ok = FALSE;
252b5132
RH		 2484
2485 /* If INSN is a load, and it sets a register which
2486 the insn after NEXT_INSN uses, then doing the
2487 swap will cause a pipeline bubble, so there is no
2488 reason to make the swap. However, if the insn
2489 after NEXT_INSN is itself a load or store
2490 instruction, then it is misaligned, so
2491 optimistically hope that it will be swapped
2492 itself, and just live with the pipeline bubble if
2493 it isn't. */
2494 if (ok
2495 && i + 4 < stop
2496 && (op->flags & LOAD) != 0)
2497 {
2498 unsigned int next2_insn;
2499 const struct sh_opcode *next2_op;
2500
2501 next2_insn = bfd_get_16 (abfd, contents + i + 4);
2502 next2_op = sh_insn_info (next2_insn);
230d6d81
NC		 2503 if (next2_op == NULL
2504 || ((next2_op->flags & (LOAD | STORE)) == 0
2505 && sh_load_use (insn, op, next2_insn, next2_op)))
b34976b6 2506 ok = FALSE;
252b5132
RH		 2507 }
2508
2509 if (ok)
2510 {
2511 if (! (*swap) (abfd, sec, relocs, contents, i))
b34976b6
AM		 2512 return FALSE;
2513 *pswapped = TRUE;
252b5132
RH		 2514 continue;
2515 }
2516 }
2517 }
2518 }
2519
b34976b6 2520 return TRUE;
252b5132 2521}
86033394 2522#endif /* not COFF_IMAGE_WITH_PE */
252b5132 2523
252b5132
RH		 2524/* Swap two SH instructions. */
2525
b34976b6 2526static bfd_boolean
2c3fc389
NC		 2527sh_swap_insns (bfd * abfd,
2528 asection * sec,
2529 void * relocs,
2530 bfd_byte * contents,
2531 bfd_vma addr)
252b5132
RH		 2532{
2533 struct internal_reloc *internal_relocs = (struct internal_reloc *) relocs;
2534 unsigned short i1, i2;
2535 struct internal_reloc *irel, *irelend;
2536
2537 /* Swap the instructions themselves. */
2538 i1 = bfd_get_16 (abfd, contents + addr);
2539 i2 = bfd_get_16 (abfd, contents + addr + 2);
dc810e39
AM		 2540 bfd_put_16 (abfd, (bfd_vma) i2, contents + addr);
2541 bfd_put_16 (abfd, (bfd_vma) i1, contents + addr + 2);
252b5132
RH		 2542
2543 /* Adjust all reloc addresses. */
2544 irelend = internal_relocs + sec->reloc_count;
2545 for (irel = internal_relocs; irel < irelend; irel++)
2546 {
2547 int type, add;
2548
2549 /* There are a few special types of relocs that we don't want to
07d6d2b8
AM		 2550 adjust. These relocs do not apply to the instruction itself,
2551 but are only associated with the address. */
252b5132
RH		 2552 type = irel->r_type;
2553 if (type == R_SH_ALIGN
2554 || type == R_SH_CODE
2555 || type == R_SH_DATA
2556 || type == R_SH_LABEL)
2557 continue;
2558
2559 /* If an R_SH_USES reloc points to one of the addresses being
07d6d2b8
AM		 2560 swapped, we must adjust it. It would be incorrect to do this
2561 for a jump, though, since we want to execute both
2562 instructions after the jump. (We have avoided swapping
2563 around a label, so the jump will not wind up executing an
2564 instruction it shouldn't). */
252b5132
RH		 2565 if (type == R_SH_USES)
2566 {
2567 bfd_vma off;
2568
2569 off = irel->r_vaddr - sec->vma + 4 + irel->r_offset;
2570 if (off == addr)
2571 irel->r_offset += 2;
2572 else if (off == addr + 2)
2573 irel->r_offset -= 2;
2574 }
2575
2576 if (irel->r_vaddr - sec->vma == addr)
2577 {
2578 irel->r_vaddr += 2;
2579 add = -2;
2580 }
2581 else if (irel->r_vaddr - sec->vma == addr + 2)
2582 {
2583 irel->r_vaddr -= 2;
2584 add = 2;
2585 }
2586 else
2587 add = 0;
2588
2589 if (add != 0)
2590 {
2591 bfd_byte *loc;
2592 unsigned short insn, oinsn;
b34976b6 2593 bfd_boolean overflow;
252b5132
RH		 2594
2595 loc = contents + irel->r_vaddr - sec->vma;
b34976b6 2596 overflow = FALSE;
252b5132
RH		 2597 switch (type)
2598 {
2599 default:
2600 break;
2601
2602 case R_SH_PCDISP8BY2:
2603 case R_SH_PCRELIMM8BY2:
2604 insn = bfd_get_16 (abfd, loc);
2605 oinsn = insn;
2606 insn += add / 2;
2607 if ((oinsn & 0xff00) != (insn & 0xff00))
b34976b6 2608 overflow = TRUE;
dc810e39 2609 bfd_put_16 (abfd, (bfd_vma) insn, loc);
252b5132
RH		 2610 break;
2611
2612 case R_SH_PCDISP:
2613 insn = bfd_get_16 (abfd, loc);
2614 oinsn = insn;
2615 insn += add / 2;
2616 if ((oinsn & 0xf000) != (insn & 0xf000))
b34976b6 2617 overflow = TRUE;
dc810e39 2618 bfd_put_16 (abfd, (bfd_vma) insn, loc);
252b5132
RH		 2619 break;
2620
2621 case R_SH_PCRELIMM8BY4:
2622 /* This reloc ignores the least significant 3 bits of
07d6d2b8
AM		 2623 the program counter before adding in the offset.
2624 This means that if ADDR is at an even address, the
2625 swap will not affect the offset. If ADDR is an at an
2626 odd address, then the instruction will be crossing a
2627 four byte boundary, and must be adjusted. */
252b5132
RH		 2628 if ((addr & 3) != 0)
2629 {
2630 insn = bfd_get_16 (abfd, loc);
2631 oinsn = insn;
2632 insn += add / 2;
2633 if ((oinsn & 0xff00) != (insn & 0xff00))
b34976b6 2634 overflow = TRUE;
dc810e39 2635 bfd_put_16 (abfd, (bfd_vma) insn, loc);
252b5132
RH		 2636 }
2637
2638 break;
2639 }
2640
2641 if (overflow)
2642 {
4eca0228 2643 _bfd_error_handler
695344c0 2644 /* xgettext: c-format */
2dcf00ce
AM		 2645 (_("%pB: %#" PRIx64 ": fatal: reloc overflow while relaxing"),
2646 abfd, (uint64_t) irel->r_vaddr);
252b5132 2647 bfd_set_error (bfd_error_bad_value);
b34976b6 2648 return FALSE;
252b5132
RH		 2649 }
2650 }
2651 }
2652
b34976b6 2653 return TRUE;
252b5132 2654}
2c3fc389
NC		 2655
2656/* Look for loads and stores which we can align to four byte
2657 boundaries. See the longer comment above sh_relax_section for why
2658 this is desirable. This sets *PSWAPPED if some instruction was
2659 swapped. */
2660
2661static bfd_boolean
2662sh_align_loads (bfd *abfd,
2663 asection *sec,
2664 struct internal_reloc *internal_relocs,
2665 bfd_byte *contents,
2666 bfd_boolean *pswapped)
2667{
2668 struct internal_reloc *irel, *irelend;
2669 bfd_vma *labels = NULL;
2670 bfd_vma *label, *label_end;
2671 bfd_size_type amt;
2672
2673 *pswapped = FALSE;
2674
2675 irelend = internal_relocs + sec->reloc_count;
2676
2677 /* Get all the addresses with labels on them. */
2678 amt = (bfd_size_type) sec->reloc_count * sizeof (bfd_vma);
2679 labels = (bfd_vma *) bfd_malloc (amt);
2680 if (labels == NULL)
2681 goto error_return;
2682 label_end = labels;
2683 for (irel = internal_relocs; irel < irelend; irel++)
2684 {
2685 if (irel->r_type == R_SH_LABEL)
2686 {
2687 *label_end = irel->r_vaddr - sec->vma;
2688 ++label_end;
2689 }
2690 }
2691
2692 /* Note that the assembler currently always outputs relocs in
2693 address order. If that ever changes, this code will need to sort
2694 the label values and the relocs. */
2695
2696 label = labels;
2697
2698 for (irel = internal_relocs; irel < irelend; irel++)
2699 {
2700 bfd_vma start, stop;
2701
2702 if (irel->r_type != R_SH_CODE)
2703 continue;
2704
2705 start = irel->r_vaddr - sec->vma;
2706
2707 for (irel++; irel < irelend; irel++)
2708 if (irel->r_type == R_SH_DATA)
2709 break;
2710 if (irel < irelend)
2711 stop = irel->r_vaddr - sec->vma;
2712 else
2713 stop = sec->size;
2714
2715 if (! _bfd_sh_align_load_span (abfd, sec, contents, sh_swap_insns,
2716 internal_relocs, &label,
2717 label_end, start, stop, pswapped))
2718 goto error_return;
2719 }
2720
2721 free (labels);
2722
2723 return TRUE;
2724
2725 error_return:
2726 if (labels != NULL)
2727 free (labels);
2728 return FALSE;
2729}
252b5132
RH		 2730\f
2731/* This is a modification of _bfd_coff_generic_relocate_section, which
2732 will handle SH relaxing. */
2733
b34976b6 2734static bfd_boolean
2c3fc389
NC		 2735sh_relocate_section (bfd *output_bfd ATTRIBUTE_UNUSED,
2736 struct bfd_link_info *info,
2737 bfd *input_bfd,
2738 asection *input_section,
2739 bfd_byte *contents,
2740 struct internal_reloc *relocs,
2741 struct internal_syment *syms,
2742 asection **sections)
252b5132
RH		 2743{
2744 struct internal_reloc *rel;
2745 struct internal_reloc *relend;
2746
2747 rel = relocs;
2748 relend = rel + input_section->reloc_count;
2749 for (; rel < relend; rel++)
2750 {
2751 long symndx;
2752 struct coff_link_hash_entry *h;
2753 struct internal_syment *sym;
2754 bfd_vma addend;
2755 bfd_vma val;
2756 reloc_howto_type *howto;
2757 bfd_reloc_status_type rstat;
2758
2759 /* Almost all relocs have to do with relaxing. If any work must
07d6d2b8 2760 be done for them, it has been done in sh_relax_section. */
252b5132 2761 if (rel->r_type != R_SH_IMM32
17505c5c
NC		 2762#ifdef COFF_WITH_PE
2763 && rel->r_type != R_SH_IMM32CE
2764 && rel->r_type != R_SH_IMAGEBASE
2765#endif
252b5132
RH		 2766 && rel->r_type != R_SH_PCDISP)
2767 continue;
2768
2769 symndx = rel->r_symndx;
2770
2771 if (symndx == -1)
2772 {
2773 h = NULL;
2774 sym = NULL;
2775 }
2776 else
cbfe05c4 2777 {
252b5132
RH		 2778 if (symndx < 0
2779 || (unsigned long) symndx >= obj_raw_syment_count (input_bfd))
2780 {
4eca0228 2781 _bfd_error_handler
695344c0 2782 /* xgettext: c-format */
871b3ab2 2783 (_("%pB: illegal symbol index %ld in relocs"),
d003868e 2784 input_bfd, symndx);
252b5132 2785 bfd_set_error (bfd_error_bad_value);
b34976b6 2786 return FALSE;
252b5132
RH		 2787 }
2788 h = obj_coff_sym_hashes (input_bfd)[symndx];
2789 sym = syms + symndx;
2790 }
2791
2792 if (sym != NULL && sym->n_scnum != 0)
2793 addend = - sym->n_value;
2794 else
2795 addend = 0;
2796
2797 if (rel->r_type == R_SH_PCDISP)
2798 addend -= 4;
2799
2800 if (rel->r_type >= SH_COFF_HOWTO_COUNT)
2801 howto = NULL;
2802 else
2803 howto = &sh_coff_howtos[rel->r_type];
2804
2805 if (howto == NULL)
2806 {
2807 bfd_set_error (bfd_error_bad_value);
b34976b6 2808 return FALSE;
252b5132
RH		 2809 }
2810
17505c5c
NC		 2811#ifdef COFF_WITH_PE
2812 if (rel->r_type == R_SH_IMAGEBASE)
2813 addend -= pe_data (input_section->output_section->owner)->pe_opthdr.ImageBase;
2814#endif
cbfe05c4 2815
252b5132
RH		 2816 val = 0;
2817
2818 if (h == NULL)
2819 {
2820 asection *sec;
2821
2822 /* There is nothing to do for an internal PCDISP reloc. */
2823 if (rel->r_type == R_SH_PCDISP)
2824 continue;
2825
2826 if (symndx == -1)
2827 {
2828 sec = bfd_abs_section_ptr;
2829 val = 0;
2830 }
2831 else
2832 {
2833 sec = sections[symndx];
07d6d2b8 2834 val = (sec->output_section->vma
252b5132
RH		 2835 + sec->output_offset
2836 + sym->n_value
2837 - sec->vma);
2838 }
2839 }
2840 else
2841 {
2842 if (h->root.type == bfd_link_hash_defined
2843 || h->root.type == bfd_link_hash_defweak)
2844 {
2845 asection *sec;
2846
2847 sec = h->root.u.def.section;
2848 val = (h->root.u.def.value
2849 + sec->output_section->vma
2850 + sec->output_offset);
2851 }
0e1862bb 2852 else if (! bfd_link_relocatable (info))
1a72702b
AM		 2853 (*info->callbacks->undefined_symbol)
2854 (info, h->root.root.string, input_bfd, input_section,
2855 rel->r_vaddr - input_section->vma, TRUE);
252b5132
RH		 2856 }
2857
2858 rstat = _bfd_final_link_relocate (howto, input_bfd, input_section,
2859 contents,
2860 rel->r_vaddr - input_section->vma,
2861 val, addend);
2862
2863 switch (rstat)
2864 {
2865 default:
2866 abort ();
2867 case bfd_reloc_ok:
2868 break;
2869 case bfd_reloc_overflow:
2870 {
2871 const char *name;
2872 char buf[SYMNMLEN + 1];
2873
2874 if (symndx == -1)
2875 name = "*ABS*";
2876 else if (h != NULL)
dfeffb9f 2877 name = NULL;
252b5132
RH		 2878 else if (sym->_n._n_n._n_zeroes == 0
2879 && sym->_n._n_n._n_offset != 0)
2880 name = obj_coff_strings (input_bfd) + sym->_n._n_n._n_offset;
2881 else
2882 {
07d6d2b8 2883 strncpy (buf, sym->_n._n_name, SYMNMLEN);
252b5132
RH		 2884 buf[SYMNMLEN] = '\0';
2885 name = buf;
2886 }
2887
1a72702b
AM		 2888 (*info->callbacks->reloc_overflow)
2889 (info, (h ? &h->root : NULL), name, howto->name,
2890 (bfd_vma) 0, input_bfd, input_section,
2891 rel->r_vaddr - input_section->vma);
252b5132
RH		 2892 }
2893 }
2894 }
2895
b34976b6 2896 return TRUE;
252b5132
RH		 2897}
2898
2899/* This is a version of bfd_generic_get_relocated_section_contents
2900 which uses sh_relocate_section. */
2901
2902static bfd_byte *
2c3fc389
NC		 2903sh_coff_get_relocated_section_contents (bfd *output_bfd,
2904 struct bfd_link_info *link_info,
2905 struct bfd_link_order *link_order,
2906 bfd_byte *data,
2907 bfd_boolean relocatable,
2908 asymbol **symbols)
252b5132
RH		 2909{
2910 asection *input_section = link_order->u.indirect.section;
2911 bfd *input_bfd = input_section->owner;
2912 asection **sections = NULL;
2913 struct internal_reloc *internal_relocs = NULL;
2914 struct internal_syment *internal_syms = NULL;
2915
2916 /* We only need to handle the case of relaxing, or of having a
2917 particular set of section contents, specially. */
1049f94e 2918 if (relocatable
252b5132
RH		 2919 || coff_section_data (input_bfd, input_section) == NULL
2920 || coff_section_data (input_bfd, input_section)->contents == NULL)
2921 return bfd_generic_get_relocated_section_contents (output_bfd, link_info,
2922 link_order, data,
1049f94e 2923 relocatable,
252b5132
RH		 2924 symbols);
2925
2926 memcpy (data, coff_section_data (input_bfd, input_section)->contents,
eea6121a 2927 (size_t) input_section->size);
252b5132
RH		 2928
2929 if ((input_section->flags & SEC_RELOC) != 0
2930 && input_section->reloc_count > 0)
2931 {
2932 bfd_size_type symesz = bfd_coff_symesz (input_bfd);
2933 bfd_byte *esym, *esymend;
2934 struct internal_syment *isymp;
2935 asection **secpp;
dc810e39 2936 bfd_size_type amt;
252b5132
RH		 2937
2938 if (! _bfd_coff_get_external_symbols (input_bfd))
2939 goto error_return;
2940
2941 internal_relocs = (_bfd_coff_read_internal_relocs
b34976b6
AM		 2942 (input_bfd, input_section, FALSE, (bfd_byte *) NULL,
2943 FALSE, (struct internal_reloc *) NULL));
252b5132
RH		 2944 if (internal_relocs == NULL)
2945 goto error_return;
2946
dc810e39
AM		 2947 amt = obj_raw_syment_count (input_bfd);
2948 amt *= sizeof (struct internal_syment);
2949 internal_syms = (struct internal_syment *) bfd_malloc (amt);
252b5132
RH		 2950 if (internal_syms == NULL)
2951 goto error_return;
2952
dc810e39
AM		 2953 amt = obj_raw_syment_count (input_bfd);
2954 amt *= sizeof (asection *);
2955 sections = (asection **) bfd_malloc (amt);
252b5132
RH		 2956 if (sections == NULL)
2957 goto error_return;
2958
2959 isymp = internal_syms;
2960 secpp = sections;
2961 esym = (bfd_byte *) obj_coff_external_syms (input_bfd);
2962 esymend = esym + obj_raw_syment_count (input_bfd) * symesz;
2963 while (esym < esymend)
2964 {
2c3fc389 2965 bfd_coff_swap_sym_in (input_bfd, esym, isymp);
252b5132
RH		 2966
2967 if (isymp->n_scnum != 0)
2968 *secpp = coff_section_from_bfd_index (input_bfd, isymp->n_scnum);
2969 else
2970 {
2971 if (isymp->n_value == 0)
2972 *secpp = bfd_und_section_ptr;
2973 else
2974 *secpp = bfd_com_section_ptr;
2975 }
2976
2977 esym += (isymp->n_numaux + 1) * symesz;
2978 secpp += isymp->n_numaux + 1;
2979 isymp += isymp->n_numaux + 1;
2980 }
2981
2982 if (! sh_relocate_section (output_bfd, link_info, input_bfd,
2983 input_section, data, internal_relocs,
2984 internal_syms, sections))
2985 goto error_return;
2986
2987 free (sections);
2988 sections = NULL;
2989 free (internal_syms);
2990 internal_syms = NULL;
2991 free (internal_relocs);
2992 internal_relocs = NULL;
2993 }
2994
2995 return data;
2996
2997 error_return:
2998 if (internal_relocs != NULL)
2999 free (internal_relocs);
3000 if (internal_syms != NULL)
3001 free (internal_syms);
3002 if (sections != NULL)
3003 free (sections);
3004 return NULL;
3005}
3006
3007/* The target vectors. */
3008
17505c5c 3009#ifndef TARGET_SHL_SYM
6d00b590 3010CREATE_BIG_COFF_TARGET_VEC (sh_coff_vec, "coff-sh", BFD_IS_RELAXABLE, 0, '_', NULL, COFF_SWAP_TABLE)
17505c5c 3011#endif
252b5132 3012
c3c89269
NC		 3013#ifdef TARGET_SHL_SYM
3014#define TARGET_SYM TARGET_SHL_SYM
3015#else
6d00b590 3016#define TARGET_SYM sh_coff_le_vec
c3c89269 3017#endif
cbfe05c4 3018
c3c89269
NC		 3019#ifndef TARGET_SHL_NAME
3020#define TARGET_SHL_NAME "coff-shl"
3021#endif
252b5132 3022
17505c5c
NC		 3023#ifdef COFF_WITH_PE
3024CREATE_LITTLE_COFF_TARGET_VEC (TARGET_SYM, TARGET_SHL_NAME, BFD_IS_RELAXABLE,
3fa78519 3025 SEC_CODE | SEC_DATA, '_', NULL, COFF_SWAP_TABLE);
17505c5c 3026#else
86033394 3027CREATE_LITTLE_COFF_TARGET_VEC (TARGET_SYM, TARGET_SHL_NAME, BFD_IS_RELAXABLE,
3fa78519 3028 0, '_', NULL, COFF_SWAP_TABLE)
17505c5c 3029#endif
86033394 3030
17505c5c 3031#ifndef TARGET_SHL_SYM
2c3fc389 3032
252b5132
RH		 3033/* Some people want versions of the SH COFF target which do not align
3034 to 16 byte boundaries. We implement that by adding a couple of new
3035 target vectors. These are just like the ones above, but they
3036 change the default section alignment. To generate them in the
3037 assembler, use -small. To use them in the linker, use -b
3038 coff-sh{l}-small and -oformat coff-sh{l}-small.
3039
3040 Yes, this is a horrible hack. A general solution for setting
3041 section alignment in COFF is rather complex. ELF handles this
3042 correctly. */
3043
3044/* Only recognize the small versions if the target was not defaulted.
3045 Otherwise we won't recognize the non default endianness. */
3046
3047static const bfd_target *
2c3fc389 3048coff_small_object_p (bfd *abfd)
252b5132
RH		 3049{
3050 if (abfd->target_defaulted)
3051 {
3052 bfd_set_error (bfd_error_wrong_format);
3053 return NULL;
3054 }
3055 return coff_object_p (abfd);
3056}
3057
3058/* Set the section alignment for the small versions. */
3059
b34976b6 3060static bfd_boolean
2c3fc389 3061coff_small_new_section_hook (bfd *abfd, asection *section)
252b5132
RH		 3062{
3063 if (! coff_new_section_hook (abfd, section))
b34976b6 3064 return FALSE;
252b5132
RH		 3065
3066 /* We must align to at least a four byte boundary, because longword
3067 accesses must be on a four byte boundary. */
3068 if (section->alignment_power == COFF_DEFAULT_SECTION_ALIGNMENT_POWER)
3069 section->alignment_power = 2;
3070
b34976b6 3071 return TRUE;
252b5132
RH		 3072}
3073
3074/* This is copied from bfd_coff_std_swap_table so that we can change
3075 the default section alignment power. */
3076
88183869 3077static bfd_coff_backend_data bfd_coff_small_swap_table =
252b5132
RH		 3078{
3079 coff_swap_aux_in, coff_swap_sym_in, coff_swap_lineno_in,
3080 coff_swap_aux_out, coff_swap_sym_out,
3081 coff_swap_lineno_out, coff_swap_reloc_out,
3082 coff_swap_filehdr_out, coff_swap_aouthdr_out,
3083 coff_swap_scnhdr_out,
692b7d62 3084 FILHSZ, AOUTSZ, SCNHSZ, SYMESZ, AUXESZ, RELSZ, LINESZ, FILNMLEN,
252b5132 3085#ifdef COFF_LONG_FILENAMES
b34976b6 3086 TRUE,
252b5132 3087#else
b34976b6 3088 FALSE,
252b5132 3089#endif
88183869 3090 COFF_DEFAULT_LONG_SECTION_NAMES,
252b5132 3091 2,
ecefdb58 3092#ifdef COFF_FORCE_SYMBOLS_IN_STRINGS
b34976b6 3093 TRUE,
ecefdb58 3094#else
b34976b6 3095 FALSE,
ecefdb58
CP		 3096#endif
3097#ifdef COFF_DEBUG_STRING_WIDE_PREFIX
3098 4,
3099#else
3100 2,
3101#endif
167ad85b 3102 32768,
252b5132
RH		 3103 coff_swap_filehdr_in, coff_swap_aouthdr_in, coff_swap_scnhdr_in,
3104 coff_swap_reloc_in, coff_bad_format_hook, coff_set_arch_mach_hook,
3105 coff_mkobject_hook, styp_to_sec_flags, coff_set_alignment_hook,
3106 coff_slurp_symbol_table, symname_in_debug_hook, coff_pointerize_aux_hook,
3107 coff_print_aux, coff_reloc16_extra_cases, coff_reloc16_estimate,
5d54c628 3108 coff_classify_symbol, coff_compute_section_file_positions,
252b5132
RH		 3109 coff_start_final_link, coff_relocate_section, coff_rtype_to_howto,
3110 coff_adjust_symndx, coff_link_add_one_symbol,
2b5c217d
NC		 3111 coff_link_output_has_begun, coff_final_link_postscript,
3112 bfd_pe_print_pdata
252b5132
RH		 3113};
3114
3115#define coff_small_close_and_cleanup \
3116 coff_close_and_cleanup
3117#define coff_small_bfd_free_cached_info \
3118 coff_bfd_free_cached_info
3119#define coff_small_get_section_contents \
3120 coff_get_section_contents
3121#define coff_small_get_section_contents_in_window \
3122 coff_get_section_contents_in_window
3123
6d00b590 3124extern const bfd_target sh_coff_small_le_vec;
c3c89269 3125
6d00b590 3126const bfd_target sh_coff_small_vec =
252b5132
RH		 3127{
3128 "coff-sh-small", /* name */
3129 bfd_target_coff_flavour,
3130 BFD_ENDIAN_BIG, /* data byte order is big */
3131 BFD_ENDIAN_BIG, /* header byte order is big */
3132
d00dd7dc
AM		 3133 (HAS_RELOC | EXEC_P /* object flags */
3134 | HAS_LINENO | HAS_DEBUG
3135 | HAS_SYMS | HAS_LOCALS | WP_TEXT | BFD_IS_RELAXABLE),
252b5132
RH		 3136
3137 (SEC_HAS_CONTENTS | SEC_ALLOC | SEC_LOAD | SEC_RELOC),
3138 '_', /* leading symbol underscore */
3139 '/', /* ar_pad_char */
3140 15, /* ar_max_namelen */
0aabe54e 3141 0, /* match priority. */
252b5132
RH		 3142 bfd_getb64, bfd_getb_signed_64, bfd_putb64,
3143 bfd_getb32, bfd_getb_signed_32, bfd_putb32,
3144 bfd_getb16, bfd_getb_signed_16, bfd_putb16, /* data */
3145 bfd_getb64, bfd_getb_signed_64, bfd_putb64,
3146 bfd_getb32, bfd_getb_signed_32, bfd_putb32,
3147 bfd_getb16, bfd_getb_signed_16, bfd_putb16, /* hdrs */
3148
d00dd7dc
AM		 3149 { /* bfd_check_format */
3150 _bfd_dummy_target,
3151 coff_small_object_p,
3152 bfd_generic_archive_p,
3153 _bfd_dummy_target
3154 },
3155 { /* bfd_set_format */
3156 _bfd_bool_bfd_false_error,
3157 coff_mkobject,
3158 _bfd_generic_mkarchive,
3159 _bfd_bool_bfd_false_error
3160 },
3161 { /* bfd_write_contents */
3162 _bfd_bool_bfd_false_error,
3163 coff_write_object_contents,
3164 _bfd_write_archive_contents,
3165 _bfd_bool_bfd_false_error
3166 },
252b5132
RH		 3167
3168 BFD_JUMP_TABLE_GENERIC (coff_small),
3169 BFD_JUMP_TABLE_COPY (coff),
3170 BFD_JUMP_TABLE_CORE (_bfd_nocore),
3171 BFD_JUMP_TABLE_ARCHIVE (_bfd_archive_coff),
3172 BFD_JUMP_TABLE_SYMBOLS (coff),
3173 BFD_JUMP_TABLE_RELOCS (coff),
3174 BFD_JUMP_TABLE_WRITE (coff),
3175 BFD_JUMP_TABLE_LINK (coff),
3176 BFD_JUMP_TABLE_DYNAMIC (_bfd_nodynamic),
3177
d00dd7dc 3178 &sh_coff_small_le_vec,
cbfe05c4 3179
d00dd7dc 3180 &bfd_coff_small_swap_table
252b5132
RH		 3181};
3182
6d00b590 3183const bfd_target sh_coff_small_le_vec =
252b5132
RH		 3184{
3185 "coff-shl-small", /* name */
3186 bfd_target_coff_flavour,
3187 BFD_ENDIAN_LITTLE, /* data byte order is little */
3188 BFD_ENDIAN_LITTLE, /* header byte order is little endian too*/
3189
d00dd7dc
AM		 3190 (HAS_RELOC | EXEC_P /* object flags */
3191 | HAS_LINENO | HAS_DEBUG
3192 | HAS_SYMS | HAS_LOCALS | WP_TEXT | BFD_IS_RELAXABLE),
252b5132
RH		 3193
3194 (SEC_HAS_CONTENTS | SEC_ALLOC | SEC_LOAD | SEC_RELOC),
3195 '_', /* leading symbol underscore */
3196 '/', /* ar_pad_char */
3197 15, /* ar_max_namelen */
0aabe54e 3198 0, /* match priority. */
252b5132
RH		 3199 bfd_getl64, bfd_getl_signed_64, bfd_putl64,
3200 bfd_getl32, bfd_getl_signed_32, bfd_putl32,
3201 bfd_getl16, bfd_getl_signed_16, bfd_putl16, /* data */
3202 bfd_getl64, bfd_getl_signed_64, bfd_putl64,
3203 bfd_getl32, bfd_getl_signed_32, bfd_putl32,
3204 bfd_getl16, bfd_getl_signed_16, bfd_putl16, /* hdrs */
3205
d00dd7dc
AM		 3206 { /* bfd_check_format */
3207 _bfd_dummy_target,
3208 coff_small_object_p,
3209 bfd_generic_archive_p,
3210 _bfd_dummy_target
3211 },
3212 { /* bfd_set_format */
3213 _bfd_bool_bfd_false_error,
3214 coff_mkobject,
3215 _bfd_generic_mkarchive,
3216 _bfd_bool_bfd_false_error
3217 },
3218 { /* bfd_write_contents */
3219 _bfd_bool_bfd_false_error,
3220 coff_write_object_contents,
3221 _bfd_write_archive_contents,
3222 _bfd_bool_bfd_false_error
3223 },
252b5132
RH		 3224
3225 BFD_JUMP_TABLE_GENERIC (coff_small),
3226 BFD_JUMP_TABLE_COPY (coff),
3227 BFD_JUMP_TABLE_CORE (_bfd_nocore),
3228 BFD_JUMP_TABLE_ARCHIVE (_bfd_archive_coff),
3229 BFD_JUMP_TABLE_SYMBOLS (coff),
3230 BFD_JUMP_TABLE_RELOCS (coff),
3231 BFD_JUMP_TABLE_WRITE (coff),
3232 BFD_JUMP_TABLE_LINK (coff),
3233 BFD_JUMP_TABLE_DYNAMIC (_bfd_nodynamic),
3234
d00dd7dc 3235 &sh_coff_small_vec,
cbfe05c4 3236
d00dd7dc 3237 &bfd_coff_small_swap_table
252b5132 3238};
17505c5c 3239#endif
GDB Binutils - Deliverables
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