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gdb: add target_ops::supports_displaced_step
[deliverable/binutils-gdb.git] / bfd / elf32-arm.c
CommitLineData
252b5132 1/* 32-bit ELF support for ARM
b3adc24a 2 Copyright (C) 1998-2020 Free Software Foundation, Inc.
252b5132
RH		 3
4 This file is part of BFD, the Binary File Descriptor library.
5
6 This program is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
cd123cb7 8 the Free Software Foundation; either version 3 of the License, or
252b5132
RH		 9 (at your option) any later version.
10
11 This program is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
15
16 You should have received a copy of the GNU General Public License
17 along with this program; if not, write to the Free Software
cd123cb7
NC		 18 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
19 MA 02110-1301, USA. */
252b5132 20
6e6718a3 21#include "sysdep.h"
2468f9c9
PB		 22#include <limits.h>
23
3db64b00 24#include "bfd.h"
00a97672 25#include "libiberty.h"
7f266840
DJ		 26#include "libbfd.h"
27#include "elf-bfd.h"
b38cadfb 28#include "elf-nacl.h"
00a97672 29#include "elf-vxworks.h"
ee065d83 30#include "elf/arm.h"
f37164d7
AM		 31#include "elf32-arm.h"
32#include "cpu-arm.h"
7f266840 33
00a97672
RS		 34/* Return the relocation section associated with NAME. HTAB is the
35 bfd's elf32_arm_link_hash_entry. */
36#define RELOC_SECTION(HTAB, NAME) \
37 ((HTAB)->use_rel ? ".rel" NAME : ".rela" NAME)
38
39/* Return size of a relocation entry. HTAB is the bfd's
40 elf32_arm_link_hash_entry. */
41#define RELOC_SIZE(HTAB) \
42 ((HTAB)->use_rel \
43 ? sizeof (Elf32_External_Rel) \
44 : sizeof (Elf32_External_Rela))
45
46/* Return function to swap relocations in. HTAB is the bfd's
47 elf32_arm_link_hash_entry. */
48#define SWAP_RELOC_IN(HTAB) \
49 ((HTAB)->use_rel \
50 ? bfd_elf32_swap_reloc_in \
51 : bfd_elf32_swap_reloca_in)
52
53/* Return function to swap relocations out. HTAB is the bfd's
54 elf32_arm_link_hash_entry. */
55#define SWAP_RELOC_OUT(HTAB) \
56 ((HTAB)->use_rel \
57 ? bfd_elf32_swap_reloc_out \
58 : bfd_elf32_swap_reloca_out)
59
f3185997 60#define elf_info_to_howto NULL
07d6d2b8 61#define elf_info_to_howto_rel elf32_arm_info_to_howto
7f266840
DJ		 62
63#define ARM_ELF_ABI_VERSION 0
64#define ARM_ELF_OS_ABI_VERSION ELFOSABI_ARM
65
79f08007
YZ		 66/* The Adjusted Place, as defined by AAELF. */
67#define Pa(X) ((X) & 0xfffffffc)
68
3e6b1042
DJ		 69static bfd_boolean elf32_arm_write_section (bfd *output_bfd,
70 struct bfd_link_info *link_info,
71 asection *sec,
72 bfd_byte *contents);
73
7f266840
DJ		 74/* Note: code such as elf32_arm_reloc_type_lookup expect to use e.g.
75 R_ARM_PC24 as an index into this, and find the R_ARM_PC24 HOWTO
76 in that slot. */
77
c19d1205 78static reloc_howto_type elf32_arm_howto_table_1[] =
7f266840 79{
8029a119 80 /* No relocation. */
7f266840
DJ		 81 HOWTO (R_ARM_NONE, /* type */
82 0, /* rightshift */
6346d5ca 83 3, /* size (0 = byte, 1 = short, 2 = long) */
7f266840
DJ		 84 0, /* bitsize */
85 FALSE, /* pc_relative */
86 0, /* bitpos */
87 complain_overflow_dont,/* complain_on_overflow */
88 bfd_elf_generic_reloc, /* special_function */
89 "R_ARM_NONE", /* name */
90 FALSE, /* partial_inplace */
91 0, /* src_mask */
92 0, /* dst_mask */
93 FALSE), /* pcrel_offset */
94
95 HOWTO (R_ARM_PC24, /* type */
96 2, /* rightshift */
97 2, /* size (0 = byte, 1 = short, 2 = long) */
98 24, /* bitsize */
99 TRUE, /* pc_relative */
100 0, /* bitpos */
101 complain_overflow_signed,/* complain_on_overflow */
102 bfd_elf_generic_reloc, /* special_function */
103 "R_ARM_PC24", /* name */
104 FALSE, /* partial_inplace */
105 0x00ffffff, /* src_mask */
106 0x00ffffff, /* dst_mask */
107 TRUE), /* pcrel_offset */
108
109 /* 32 bit absolute */
110 HOWTO (R_ARM_ABS32, /* type */
111 0, /* rightshift */
112 2, /* size (0 = byte, 1 = short, 2 = long) */
113 32, /* bitsize */
114 FALSE, /* pc_relative */
115 0, /* bitpos */
116 complain_overflow_bitfield,/* complain_on_overflow */
117 bfd_elf_generic_reloc, /* special_function */
118 "R_ARM_ABS32", /* name */
119 FALSE, /* partial_inplace */
120 0xffffffff, /* src_mask */
121 0xffffffff, /* dst_mask */
122 FALSE), /* pcrel_offset */
123
124 /* standard 32bit pc-relative reloc */
125 HOWTO (R_ARM_REL32, /* type */
126 0, /* rightshift */
127 2, /* size (0 = byte, 1 = short, 2 = long) */
128 32, /* bitsize */
129 TRUE, /* pc_relative */
130 0, /* bitpos */
131 complain_overflow_bitfield,/* complain_on_overflow */
132 bfd_elf_generic_reloc, /* special_function */
133 "R_ARM_REL32", /* name */
134 FALSE, /* partial_inplace */
135 0xffffffff, /* src_mask */
136 0xffffffff, /* dst_mask */
137 TRUE), /* pcrel_offset */
138
c19d1205 139 /* 8 bit absolute - R_ARM_LDR_PC_G0 in AAELF */
4962c51a 140 HOWTO (R_ARM_LDR_PC_G0, /* type */
7f266840
DJ		 141 0, /* rightshift */
142 0, /* size (0 = byte, 1 = short, 2 = long) */
4962c51a
MS		 143 32, /* bitsize */
144 TRUE, /* pc_relative */
7f266840 145 0, /* bitpos */
4962c51a 146 complain_overflow_dont,/* complain_on_overflow */
7f266840 147 bfd_elf_generic_reloc, /* special_function */
4962c51a 148 "R_ARM_LDR_PC_G0", /* name */
7f266840 149 FALSE, /* partial_inplace */
4962c51a
MS		 150 0xffffffff, /* src_mask */
151 0xffffffff, /* dst_mask */
152 TRUE), /* pcrel_offset */
7f266840
DJ		 153
154 /* 16 bit absolute */
155 HOWTO (R_ARM_ABS16, /* type */
156 0, /* rightshift */
157 1, /* size (0 = byte, 1 = short, 2 = long) */
158 16, /* bitsize */
159 FALSE, /* pc_relative */
160 0, /* bitpos */
161 complain_overflow_bitfield,/* complain_on_overflow */
162 bfd_elf_generic_reloc, /* special_function */
163 "R_ARM_ABS16", /* name */
164 FALSE, /* partial_inplace */
165 0x0000ffff, /* src_mask */
166 0x0000ffff, /* dst_mask */
167 FALSE), /* pcrel_offset */
168
169 /* 12 bit absolute */
170 HOWTO (R_ARM_ABS12, /* type */
171 0, /* rightshift */
172 2, /* size (0 = byte, 1 = short, 2 = long) */
173 12, /* bitsize */
174 FALSE, /* pc_relative */
175 0, /* bitpos */
176 complain_overflow_bitfield,/* complain_on_overflow */
177 bfd_elf_generic_reloc, /* special_function */
178 "R_ARM_ABS12", /* name */
179 FALSE, /* partial_inplace */
00a97672
RS		 180 0x00000fff, /* src_mask */
181 0x00000fff, /* dst_mask */
7f266840
DJ		 182 FALSE), /* pcrel_offset */
183
184 HOWTO (R_ARM_THM_ABS5, /* type */
185 6, /* rightshift */
186 1, /* size (0 = byte, 1 = short, 2 = long) */
187 5, /* bitsize */
188 FALSE, /* pc_relative */
189 0, /* bitpos */
190 complain_overflow_bitfield,/* complain_on_overflow */
191 bfd_elf_generic_reloc, /* special_function */
192 "R_ARM_THM_ABS5", /* name */
193 FALSE, /* partial_inplace */
194 0x000007e0, /* src_mask */
195 0x000007e0, /* dst_mask */
196 FALSE), /* pcrel_offset */
197
198 /* 8 bit absolute */
199 HOWTO (R_ARM_ABS8, /* type */
200 0, /* rightshift */
201 0, /* size (0 = byte, 1 = short, 2 = long) */
202 8, /* bitsize */
203 FALSE, /* pc_relative */
204 0, /* bitpos */
205 complain_overflow_bitfield,/* complain_on_overflow */
206 bfd_elf_generic_reloc, /* special_function */
207 "R_ARM_ABS8", /* name */
208 FALSE, /* partial_inplace */
209 0x000000ff, /* src_mask */
210 0x000000ff, /* dst_mask */
211 FALSE), /* pcrel_offset */
212
213 HOWTO (R_ARM_SBREL32, /* type */
214 0, /* rightshift */
215 2, /* size (0 = byte, 1 = short, 2 = long) */
216 32, /* bitsize */
217 FALSE, /* pc_relative */
218 0, /* bitpos */
219 complain_overflow_dont,/* complain_on_overflow */
220 bfd_elf_generic_reloc, /* special_function */
221 "R_ARM_SBREL32", /* name */
222 FALSE, /* partial_inplace */
223 0xffffffff, /* src_mask */
224 0xffffffff, /* dst_mask */
225 FALSE), /* pcrel_offset */
226
c19d1205 227 HOWTO (R_ARM_THM_CALL, /* type */
7f266840
DJ		 228 1, /* rightshift */
229 2, /* size (0 = byte, 1 = short, 2 = long) */
f6ebfac0 230 24, /* bitsize */
7f266840
DJ		 231 TRUE, /* pc_relative */
232 0, /* bitpos */
233 complain_overflow_signed,/* complain_on_overflow */
234 bfd_elf_generic_reloc, /* special_function */
c19d1205 235 "R_ARM_THM_CALL", /* name */
7f266840 236 FALSE, /* partial_inplace */
7f6ab9f8
AM		 237 0x07ff2fff, /* src_mask */
238 0x07ff2fff, /* dst_mask */
7f266840
DJ		 239 TRUE), /* pcrel_offset */
240
07d6d2b8 241 HOWTO (R_ARM_THM_PC8, /* type */
7f266840
DJ		 242 1, /* rightshift */
243 1, /* size (0 = byte, 1 = short, 2 = long) */
244 8, /* bitsize */
245 TRUE, /* pc_relative */
246 0, /* bitpos */
247 complain_overflow_signed,/* complain_on_overflow */
248 bfd_elf_generic_reloc, /* special_function */
249 "R_ARM_THM_PC8", /* name */
250 FALSE, /* partial_inplace */
251 0x000000ff, /* src_mask */
252 0x000000ff, /* dst_mask */
253 TRUE), /* pcrel_offset */
254
c19d1205 255 HOWTO (R_ARM_BREL_ADJ, /* type */
7f266840
DJ		 256 1, /* rightshift */
257 1, /* size (0 = byte, 1 = short, 2 = long) */
c19d1205
ZW		 258 32, /* bitsize */
259 FALSE, /* pc_relative */
7f266840
DJ		 260 0, /* bitpos */
261 complain_overflow_signed,/* complain_on_overflow */
262 bfd_elf_generic_reloc, /* special_function */
c19d1205 263 "R_ARM_BREL_ADJ", /* name */
7f266840 264 FALSE, /* partial_inplace */
c19d1205
ZW		 265 0xffffffff, /* src_mask */
266 0xffffffff, /* dst_mask */
267 FALSE), /* pcrel_offset */
7f266840 268
0855e32b 269 HOWTO (R_ARM_TLS_DESC, /* type */
7f266840 270 0, /* rightshift */
0855e32b
NS		 271 2, /* size (0 = byte, 1 = short, 2 = long) */
272 32, /* bitsize */
7f266840
DJ		 273 FALSE, /* pc_relative */
274 0, /* bitpos */
0855e32b 275 complain_overflow_bitfield,/* complain_on_overflow */
7f266840 276 bfd_elf_generic_reloc, /* special_function */
0855e32b 277 "R_ARM_TLS_DESC", /* name */
7f266840 278 FALSE, /* partial_inplace */
0855e32b
NS		 279 0xffffffff, /* src_mask */
280 0xffffffff, /* dst_mask */
7f266840
DJ		 281 FALSE), /* pcrel_offset */
282
283 HOWTO (R_ARM_THM_SWI8, /* type */
284 0, /* rightshift */
285 0, /* size (0 = byte, 1 = short, 2 = long) */
286 0, /* bitsize */
287 FALSE, /* pc_relative */
288 0, /* bitpos */
289 complain_overflow_signed,/* complain_on_overflow */
290 bfd_elf_generic_reloc, /* special_function */
291 "R_ARM_SWI8", /* name */
292 FALSE, /* partial_inplace */
293 0x00000000, /* src_mask */
294 0x00000000, /* dst_mask */
295 FALSE), /* pcrel_offset */
296
297 /* BLX instruction for the ARM. */
298 HOWTO (R_ARM_XPC25, /* type */
299 2, /* rightshift */
300 2, /* size (0 = byte, 1 = short, 2 = long) */
7f6ab9f8 301 24, /* bitsize */
7f266840
DJ		 302 TRUE, /* pc_relative */
303 0, /* bitpos */
304 complain_overflow_signed,/* complain_on_overflow */
305 bfd_elf_generic_reloc, /* special_function */
306 "R_ARM_XPC25", /* name */
307 FALSE, /* partial_inplace */
308 0x00ffffff, /* src_mask */
309 0x00ffffff, /* dst_mask */
310 TRUE), /* pcrel_offset */
311
312 /* BLX instruction for the Thumb. */
313 HOWTO (R_ARM_THM_XPC22, /* type */
314 2, /* rightshift */
315 2, /* size (0 = byte, 1 = short, 2 = long) */
7f6ab9f8 316 24, /* bitsize */
7f266840
DJ		 317 TRUE, /* pc_relative */
318 0, /* bitpos */
319 complain_overflow_signed,/* complain_on_overflow */
320 bfd_elf_generic_reloc, /* special_function */
321 "R_ARM_THM_XPC22", /* name */
322 FALSE, /* partial_inplace */
7f6ab9f8
AM		 323 0x07ff2fff, /* src_mask */
324 0x07ff2fff, /* dst_mask */
7f266840
DJ		 325 TRUE), /* pcrel_offset */
326
ba93b8ac 327 /* Dynamic TLS relocations. */
7f266840 328
ba93b8ac 329 HOWTO (R_ARM_TLS_DTPMOD32, /* type */
07d6d2b8
AM		 330 0, /* rightshift */
331 2, /* size (0 = byte, 1 = short, 2 = long) */
332 32, /* bitsize */
333 FALSE, /* pc_relative */
334 0, /* bitpos */
99059e56
RM		 335 complain_overflow_bitfield,/* complain_on_overflow */
336 bfd_elf_generic_reloc, /* special_function */
337 "R_ARM_TLS_DTPMOD32", /* name */
338 TRUE, /* partial_inplace */
339 0xffffffff, /* src_mask */
340 0xffffffff, /* dst_mask */
07d6d2b8 341 FALSE), /* pcrel_offset */
7f266840 342
ba93b8ac 343 HOWTO (R_ARM_TLS_DTPOFF32, /* type */
07d6d2b8
AM		 344 0, /* rightshift */
345 2, /* size (0 = byte, 1 = short, 2 = long) */
346 32, /* bitsize */
347 FALSE, /* pc_relative */
348 0, /* bitpos */
99059e56
RM		 349 complain_overflow_bitfield,/* complain_on_overflow */
350 bfd_elf_generic_reloc, /* special_function */
351 "R_ARM_TLS_DTPOFF32", /* name */
352 TRUE, /* partial_inplace */
353 0xffffffff, /* src_mask */
354 0xffffffff, /* dst_mask */
07d6d2b8 355 FALSE), /* pcrel_offset */
7f266840 356
ba93b8ac 357 HOWTO (R_ARM_TLS_TPOFF32, /* type */
07d6d2b8
AM		 358 0, /* rightshift */
359 2, /* size (0 = byte, 1 = short, 2 = long) */
360 32, /* bitsize */
361 FALSE, /* pc_relative */
362 0, /* bitpos */
99059e56
RM		 363 complain_overflow_bitfield,/* complain_on_overflow */
364 bfd_elf_generic_reloc, /* special_function */
365 "R_ARM_TLS_TPOFF32", /* name */
366 TRUE, /* partial_inplace */
367 0xffffffff, /* src_mask */
368 0xffffffff, /* dst_mask */
07d6d2b8 369 FALSE), /* pcrel_offset */
7f266840
DJ		 370
371 /* Relocs used in ARM Linux */
372
373 HOWTO (R_ARM_COPY, /* type */
07d6d2b8
AM		 374 0, /* rightshift */
375 2, /* size (0 = byte, 1 = short, 2 = long) */
376 32, /* bitsize */
377 FALSE, /* pc_relative */
378 0, /* bitpos */
99059e56
RM		 379 complain_overflow_bitfield,/* complain_on_overflow */
380 bfd_elf_generic_reloc, /* special_function */
381 "R_ARM_COPY", /* name */
382 TRUE, /* partial_inplace */
383 0xffffffff, /* src_mask */
384 0xffffffff, /* dst_mask */
07d6d2b8 385 FALSE), /* pcrel_offset */
7f266840
DJ		 386
387 HOWTO (R_ARM_GLOB_DAT, /* type */
07d6d2b8
AM		 388 0, /* rightshift */
389 2, /* size (0 = byte, 1 = short, 2 = long) */
390 32, /* bitsize */
391 FALSE, /* pc_relative */
392 0, /* bitpos */
99059e56
RM		 393 complain_overflow_bitfield,/* complain_on_overflow */
394 bfd_elf_generic_reloc, /* special_function */
395 "R_ARM_GLOB_DAT", /* name */
396 TRUE, /* partial_inplace */
397 0xffffffff, /* src_mask */
398 0xffffffff, /* dst_mask */
07d6d2b8 399 FALSE), /* pcrel_offset */
7f266840
DJ		 400
401 HOWTO (R_ARM_JUMP_SLOT, /* type */
07d6d2b8
AM		 402 0, /* rightshift */
403 2, /* size (0 = byte, 1 = short, 2 = long) */
404 32, /* bitsize */
405 FALSE, /* pc_relative */
406 0, /* bitpos */
99059e56
RM		 407 complain_overflow_bitfield,/* complain_on_overflow */
408 bfd_elf_generic_reloc, /* special_function */
409 "R_ARM_JUMP_SLOT", /* name */
410 TRUE, /* partial_inplace */
411 0xffffffff, /* src_mask */
412 0xffffffff, /* dst_mask */
07d6d2b8 413 FALSE), /* pcrel_offset */
7f266840
DJ		 414
415 HOWTO (R_ARM_RELATIVE, /* type */
07d6d2b8
AM		 416 0, /* rightshift */
417 2, /* size (0 = byte, 1 = short, 2 = long) */
418 32, /* bitsize */
419 FALSE, /* pc_relative */
420 0, /* bitpos */
99059e56
RM		 421 complain_overflow_bitfield,/* complain_on_overflow */
422 bfd_elf_generic_reloc, /* special_function */
423 "R_ARM_RELATIVE", /* name */
424 TRUE, /* partial_inplace */
425 0xffffffff, /* src_mask */
426 0xffffffff, /* dst_mask */
07d6d2b8 427 FALSE), /* pcrel_offset */
7f266840 428
c19d1205 429 HOWTO (R_ARM_GOTOFF32, /* type */
07d6d2b8
AM		 430 0, /* rightshift */
431 2, /* size (0 = byte, 1 = short, 2 = long) */
432 32, /* bitsize */
433 FALSE, /* pc_relative */
434 0, /* bitpos */
99059e56
RM		 435 complain_overflow_bitfield,/* complain_on_overflow */
436 bfd_elf_generic_reloc, /* special_function */
437 "R_ARM_GOTOFF32", /* name */
438 TRUE, /* partial_inplace */
439 0xffffffff, /* src_mask */
440 0xffffffff, /* dst_mask */
07d6d2b8 441 FALSE), /* pcrel_offset */
7f266840
DJ		 442
443 HOWTO (R_ARM_GOTPC, /* type */
07d6d2b8
AM		 444 0, /* rightshift */
445 2, /* size (0 = byte, 1 = short, 2 = long) */
446 32, /* bitsize */
99059e56 447 TRUE, /* pc_relative */
07d6d2b8 448 0, /* bitpos */
99059e56
RM		 449 complain_overflow_bitfield,/* complain_on_overflow */
450 bfd_elf_generic_reloc, /* special_function */
451 "R_ARM_GOTPC", /* name */
452 TRUE, /* partial_inplace */
453 0xffffffff, /* src_mask */
454 0xffffffff, /* dst_mask */
455 TRUE), /* pcrel_offset */
7f266840
DJ		 456
457 HOWTO (R_ARM_GOT32, /* type */
07d6d2b8
AM		 458 0, /* rightshift */
459 2, /* size (0 = byte, 1 = short, 2 = long) */
460 32, /* bitsize */
99059e56 461 FALSE, /* pc_relative */
07d6d2b8 462 0, /* bitpos */
99059e56
RM		 463 complain_overflow_bitfield,/* complain_on_overflow */
464 bfd_elf_generic_reloc, /* special_function */
465 "R_ARM_GOT32", /* name */
466 TRUE, /* partial_inplace */
467 0xffffffff, /* src_mask */
468 0xffffffff, /* dst_mask */
469 FALSE), /* pcrel_offset */
7f266840
DJ		 470
471 HOWTO (R_ARM_PLT32, /* type */
07d6d2b8
AM		 472 2, /* rightshift */
473 2, /* size (0 = byte, 1 = short, 2 = long) */
474 24, /* bitsize */
99059e56 475 TRUE, /* pc_relative */
07d6d2b8 476 0, /* bitpos */
99059e56
RM		 477 complain_overflow_bitfield,/* complain_on_overflow */
478 bfd_elf_generic_reloc, /* special_function */
479 "R_ARM_PLT32", /* name */
480 FALSE, /* partial_inplace */
481 0x00ffffff, /* src_mask */
482 0x00ffffff, /* dst_mask */
483 TRUE), /* pcrel_offset */
7f266840
DJ		 484
485 HOWTO (R_ARM_CALL, /* type */
486 2, /* rightshift */
487 2, /* size (0 = byte, 1 = short, 2 = long) */
488 24, /* bitsize */
489 TRUE, /* pc_relative */
490 0, /* bitpos */
491 complain_overflow_signed,/* complain_on_overflow */
492 bfd_elf_generic_reloc, /* special_function */
493 "R_ARM_CALL", /* name */
494 FALSE, /* partial_inplace */
495 0x00ffffff, /* src_mask */
496 0x00ffffff, /* dst_mask */
497 TRUE), /* pcrel_offset */
498
499 HOWTO (R_ARM_JUMP24, /* type */
500 2, /* rightshift */
501 2, /* size (0 = byte, 1 = short, 2 = long) */
502 24, /* bitsize */
503 TRUE, /* pc_relative */
504 0, /* bitpos */
505 complain_overflow_signed,/* complain_on_overflow */
506 bfd_elf_generic_reloc, /* special_function */
507 "R_ARM_JUMP24", /* name */
508 FALSE, /* partial_inplace */
509 0x00ffffff, /* src_mask */
510 0x00ffffff, /* dst_mask */
511 TRUE), /* pcrel_offset */
512
c19d1205
ZW		 513 HOWTO (R_ARM_THM_JUMP24, /* type */
514 1, /* rightshift */
515 2, /* size (0 = byte, 1 = short, 2 = long) */
516 24, /* bitsize */
517 TRUE, /* pc_relative */
7f266840 518 0, /* bitpos */
c19d1205 519 complain_overflow_signed,/* complain_on_overflow */
7f266840 520 bfd_elf_generic_reloc, /* special_function */
c19d1205 521 "R_ARM_THM_JUMP24", /* name */
7f266840 522 FALSE, /* partial_inplace */
c19d1205
ZW		 523 0x07ff2fff, /* src_mask */
524 0x07ff2fff, /* dst_mask */
525 TRUE), /* pcrel_offset */
7f266840 526
c19d1205 527 HOWTO (R_ARM_BASE_ABS, /* type */
7f266840 528 0, /* rightshift */
c19d1205
ZW		 529 2, /* size (0 = byte, 1 = short, 2 = long) */
530 32, /* bitsize */
7f266840
DJ		 531 FALSE, /* pc_relative */
532 0, /* bitpos */
533 complain_overflow_dont,/* complain_on_overflow */
534 bfd_elf_generic_reloc, /* special_function */
c19d1205 535 "R_ARM_BASE_ABS", /* name */
7f266840 536 FALSE, /* partial_inplace */
c19d1205
ZW		 537 0xffffffff, /* src_mask */
538 0xffffffff, /* dst_mask */
7f266840
DJ		 539 FALSE), /* pcrel_offset */
540
541 HOWTO (R_ARM_ALU_PCREL7_0, /* type */
542 0, /* rightshift */
543 2, /* size (0 = byte, 1 = short, 2 = long) */
544 12, /* bitsize */
545 TRUE, /* pc_relative */
546 0, /* bitpos */
547 complain_overflow_dont,/* complain_on_overflow */
548 bfd_elf_generic_reloc, /* special_function */
549 "R_ARM_ALU_PCREL_7_0", /* name */
550 FALSE, /* partial_inplace */
551 0x00000fff, /* src_mask */
552 0x00000fff, /* dst_mask */
553 TRUE), /* pcrel_offset */
554
555 HOWTO (R_ARM_ALU_PCREL15_8, /* type */
556 0, /* rightshift */
557 2, /* size (0 = byte, 1 = short, 2 = long) */
558 12, /* bitsize */
559 TRUE, /* pc_relative */
560 8, /* bitpos */
561 complain_overflow_dont,/* complain_on_overflow */
562 bfd_elf_generic_reloc, /* special_function */
563 "R_ARM_ALU_PCREL_15_8",/* name */
564 FALSE, /* partial_inplace */
565 0x00000fff, /* src_mask */
566 0x00000fff, /* dst_mask */
567 TRUE), /* pcrel_offset */
568
569 HOWTO (R_ARM_ALU_PCREL23_15, /* type */
570 0, /* rightshift */
571 2, /* size (0 = byte, 1 = short, 2 = long) */
572 12, /* bitsize */
573 TRUE, /* pc_relative */
574 16, /* bitpos */
575 complain_overflow_dont,/* complain_on_overflow */
576 bfd_elf_generic_reloc, /* special_function */
577 "R_ARM_ALU_PCREL_23_15",/* name */
578 FALSE, /* partial_inplace */
579 0x00000fff, /* src_mask */
580 0x00000fff, /* dst_mask */
581 TRUE), /* pcrel_offset */
582
583 HOWTO (R_ARM_LDR_SBREL_11_0, /* type */
584 0, /* rightshift */
585 2, /* size (0 = byte, 1 = short, 2 = long) */
586 12, /* bitsize */
587 FALSE, /* pc_relative */
588 0, /* bitpos */
589 complain_overflow_dont,/* complain_on_overflow */
590 bfd_elf_generic_reloc, /* special_function */
591 "R_ARM_LDR_SBREL_11_0",/* name */
592 FALSE, /* partial_inplace */
593 0x00000fff, /* src_mask */
594 0x00000fff, /* dst_mask */
595 FALSE), /* pcrel_offset */
596
597 HOWTO (R_ARM_ALU_SBREL_19_12, /* type */
598 0, /* rightshift */
599 2, /* size (0 = byte, 1 = short, 2 = long) */
600 8, /* bitsize */
601 FALSE, /* pc_relative */
602 12, /* bitpos */
603 complain_overflow_dont,/* complain_on_overflow */
604 bfd_elf_generic_reloc, /* special_function */
605 "R_ARM_ALU_SBREL_19_12",/* name */
606 FALSE, /* partial_inplace */
607 0x000ff000, /* src_mask */
608 0x000ff000, /* dst_mask */
609 FALSE), /* pcrel_offset */
610
611 HOWTO (R_ARM_ALU_SBREL_27_20, /* type */
612 0, /* rightshift */
613 2, /* size (0 = byte, 1 = short, 2 = long) */
614 8, /* bitsize */
615 FALSE, /* pc_relative */
616 20, /* bitpos */
617 complain_overflow_dont,/* complain_on_overflow */
618 bfd_elf_generic_reloc, /* special_function */
619 "R_ARM_ALU_SBREL_27_20",/* name */
620 FALSE, /* partial_inplace */
621 0x0ff00000, /* src_mask */
622 0x0ff00000, /* dst_mask */
623 FALSE), /* pcrel_offset */
624
625 HOWTO (R_ARM_TARGET1, /* type */
626 0, /* rightshift */
627 2, /* size (0 = byte, 1 = short, 2 = long) */
628 32, /* bitsize */
629 FALSE, /* pc_relative */
630 0, /* bitpos */
631 complain_overflow_dont,/* complain_on_overflow */
632 bfd_elf_generic_reloc, /* special_function */
633 "R_ARM_TARGET1", /* name */
634 FALSE, /* partial_inplace */
635 0xffffffff, /* src_mask */
636 0xffffffff, /* dst_mask */
637 FALSE), /* pcrel_offset */
638
639 HOWTO (R_ARM_ROSEGREL32, /* type */
640 0, /* rightshift */
641 2, /* size (0 = byte, 1 = short, 2 = long) */
642 32, /* bitsize */
643 FALSE, /* pc_relative */
644 0, /* bitpos */
645 complain_overflow_dont,/* complain_on_overflow */
646 bfd_elf_generic_reloc, /* special_function */
647 "R_ARM_ROSEGREL32", /* name */
648 FALSE, /* partial_inplace */
649 0xffffffff, /* src_mask */
650 0xffffffff, /* dst_mask */
651 FALSE), /* pcrel_offset */
652
653 HOWTO (R_ARM_V4BX, /* type */
654 0, /* rightshift */
655 2, /* size (0 = byte, 1 = short, 2 = long) */
656 32, /* bitsize */
657 FALSE, /* pc_relative */
658 0, /* bitpos */
659 complain_overflow_dont,/* complain_on_overflow */
660 bfd_elf_generic_reloc, /* special_function */
661 "R_ARM_V4BX", /* name */
662 FALSE, /* partial_inplace */
663 0xffffffff, /* src_mask */
664 0xffffffff, /* dst_mask */
665 FALSE), /* pcrel_offset */
666
667 HOWTO (R_ARM_TARGET2, /* type */
668 0, /* rightshift */
669 2, /* size (0 = byte, 1 = short, 2 = long) */
670 32, /* bitsize */
671 FALSE, /* pc_relative */
672 0, /* bitpos */
673 complain_overflow_signed,/* complain_on_overflow */
674 bfd_elf_generic_reloc, /* special_function */
675 "R_ARM_TARGET2", /* name */
676 FALSE, /* partial_inplace */
677 0xffffffff, /* src_mask */
678 0xffffffff, /* dst_mask */
679 TRUE), /* pcrel_offset */
680
681 HOWTO (R_ARM_PREL31, /* type */
682 0, /* rightshift */
683 2, /* size (0 = byte, 1 = short, 2 = long) */
684 31, /* bitsize */
685 TRUE, /* pc_relative */
686 0, /* bitpos */
687 complain_overflow_signed,/* complain_on_overflow */
688 bfd_elf_generic_reloc, /* special_function */
689 "R_ARM_PREL31", /* name */
690 FALSE, /* partial_inplace */
691 0x7fffffff, /* src_mask */
692 0x7fffffff, /* dst_mask */
693 TRUE), /* pcrel_offset */
c19d1205
ZW		 694
695 HOWTO (R_ARM_MOVW_ABS_NC, /* type */
696 0, /* rightshift */
697 2, /* size (0 = byte, 1 = short, 2 = long) */
698 16, /* bitsize */
699 FALSE, /* pc_relative */
700 0, /* bitpos */
701 complain_overflow_dont,/* complain_on_overflow */
702 bfd_elf_generic_reloc, /* special_function */
703 "R_ARM_MOVW_ABS_NC", /* name */
704 FALSE, /* partial_inplace */
39623e12
PB		 705 0x000f0fff, /* src_mask */
706 0x000f0fff, /* dst_mask */
c19d1205
ZW		 707 FALSE), /* pcrel_offset */
708
709 HOWTO (R_ARM_MOVT_ABS, /* type */
710 0, /* rightshift */
711 2, /* size (0 = byte, 1 = short, 2 = long) */
712 16, /* bitsize */
713 FALSE, /* pc_relative */
714 0, /* bitpos */
715 complain_overflow_bitfield,/* complain_on_overflow */
716 bfd_elf_generic_reloc, /* special_function */
717 "R_ARM_MOVT_ABS", /* name */
718 FALSE, /* partial_inplace */
39623e12
PB		 719 0x000f0fff, /* src_mask */
720 0x000f0fff, /* dst_mask */
c19d1205
ZW		 721 FALSE), /* pcrel_offset */
722
723 HOWTO (R_ARM_MOVW_PREL_NC, /* type */
724 0, /* rightshift */
725 2, /* size (0 = byte, 1 = short, 2 = long) */
726 16, /* bitsize */
727 TRUE, /* pc_relative */
728 0, /* bitpos */
729 complain_overflow_dont,/* complain_on_overflow */
730 bfd_elf_generic_reloc, /* special_function */
731 "R_ARM_MOVW_PREL_NC", /* name */
732 FALSE, /* partial_inplace */
39623e12
PB		 733 0x000f0fff, /* src_mask */
734 0x000f0fff, /* dst_mask */
c19d1205
ZW		 735 TRUE), /* pcrel_offset */
736
737 HOWTO (R_ARM_MOVT_PREL, /* type */
738 0, /* rightshift */
739 2, /* size (0 = byte, 1 = short, 2 = long) */
740 16, /* bitsize */
741 TRUE, /* pc_relative */
742 0, /* bitpos */
743 complain_overflow_bitfield,/* complain_on_overflow */
744 bfd_elf_generic_reloc, /* special_function */
745 "R_ARM_MOVT_PREL", /* name */
746 FALSE, /* partial_inplace */
39623e12
PB		 747 0x000f0fff, /* src_mask */
748 0x000f0fff, /* dst_mask */
c19d1205
ZW		 749 TRUE), /* pcrel_offset */
750
751 HOWTO (R_ARM_THM_MOVW_ABS_NC, /* type */
752 0, /* rightshift */
753 2, /* size (0 = byte, 1 = short, 2 = long) */
754 16, /* bitsize */
755 FALSE, /* pc_relative */
756 0, /* bitpos */
757 complain_overflow_dont,/* complain_on_overflow */
758 bfd_elf_generic_reloc, /* special_function */
759 "R_ARM_THM_MOVW_ABS_NC",/* name */
760 FALSE, /* partial_inplace */
761 0x040f70ff, /* src_mask */
762 0x040f70ff, /* dst_mask */
763 FALSE), /* pcrel_offset */
764
765 HOWTO (R_ARM_THM_MOVT_ABS, /* type */
766 0, /* rightshift */
767 2, /* size (0 = byte, 1 = short, 2 = long) */
768 16, /* bitsize */
769 FALSE, /* pc_relative */
770 0, /* bitpos */
771 complain_overflow_bitfield,/* complain_on_overflow */
772 bfd_elf_generic_reloc, /* special_function */
773 "R_ARM_THM_MOVT_ABS", /* name */
774 FALSE, /* partial_inplace */
775 0x040f70ff, /* src_mask */
776 0x040f70ff, /* dst_mask */
777 FALSE), /* pcrel_offset */
778
779 HOWTO (R_ARM_THM_MOVW_PREL_NC,/* type */
780 0, /* rightshift */
781 2, /* size (0 = byte, 1 = short, 2 = long) */
782 16, /* bitsize */
783 TRUE, /* pc_relative */
784 0, /* bitpos */
785 complain_overflow_dont,/* complain_on_overflow */
786 bfd_elf_generic_reloc, /* special_function */
787 "R_ARM_THM_MOVW_PREL_NC",/* name */
788 FALSE, /* partial_inplace */
789 0x040f70ff, /* src_mask */
790 0x040f70ff, /* dst_mask */
791 TRUE), /* pcrel_offset */
792
793 HOWTO (R_ARM_THM_MOVT_PREL, /* type */
794 0, /* rightshift */
795 2, /* size (0 = byte, 1 = short, 2 = long) */
796 16, /* bitsize */
797 TRUE, /* pc_relative */
798 0, /* bitpos */
799 complain_overflow_bitfield,/* complain_on_overflow */
800 bfd_elf_generic_reloc, /* special_function */
801 "R_ARM_THM_MOVT_PREL", /* name */
802 FALSE, /* partial_inplace */
803 0x040f70ff, /* src_mask */
804 0x040f70ff, /* dst_mask */
805 TRUE), /* pcrel_offset */
806
807 HOWTO (R_ARM_THM_JUMP19, /* type */
808 1, /* rightshift */
809 2, /* size (0 = byte, 1 = short, 2 = long) */
810 19, /* bitsize */
811 TRUE, /* pc_relative */
812 0, /* bitpos */
813 complain_overflow_signed,/* complain_on_overflow */
814 bfd_elf_generic_reloc, /* special_function */
815 "R_ARM_THM_JUMP19", /* name */
816 FALSE, /* partial_inplace */
817 0x043f2fff, /* src_mask */
818 0x043f2fff, /* dst_mask */
819 TRUE), /* pcrel_offset */
820
821 HOWTO (R_ARM_THM_JUMP6, /* type */
822 1, /* rightshift */
823 1, /* size (0 = byte, 1 = short, 2 = long) */
824 6, /* bitsize */
825 TRUE, /* pc_relative */
826 0, /* bitpos */
827 complain_overflow_unsigned,/* complain_on_overflow */
828 bfd_elf_generic_reloc, /* special_function */
829 "R_ARM_THM_JUMP6", /* name */
830 FALSE, /* partial_inplace */
831 0x02f8, /* src_mask */
832 0x02f8, /* dst_mask */
833 TRUE), /* pcrel_offset */
834
835 /* These are declared as 13-bit signed relocations because we can
836 address -4095 .. 4095(base) by altering ADDW to SUBW or vice
837 versa. */
838 HOWTO (R_ARM_THM_ALU_PREL_11_0,/* type */
839 0, /* rightshift */
840 2, /* size (0 = byte, 1 = short, 2 = long) */
841 13, /* bitsize */
842 TRUE, /* pc_relative */
843 0, /* bitpos */
2cab6cc3 844 complain_overflow_dont,/* complain_on_overflow */
c19d1205
ZW		 845 bfd_elf_generic_reloc, /* special_function */
846 "R_ARM_THM_ALU_PREL_11_0",/* name */
847 FALSE, /* partial_inplace */
2cab6cc3
MS		 848 0xffffffff, /* src_mask */
849 0xffffffff, /* dst_mask */
c19d1205
ZW		 850 TRUE), /* pcrel_offset */
851
852 HOWTO (R_ARM_THM_PC12, /* type */
853 0, /* rightshift */
854 2, /* size (0 = byte, 1 = short, 2 = long) */
855 13, /* bitsize */
856 TRUE, /* pc_relative */
857 0, /* bitpos */
2cab6cc3 858 complain_overflow_dont,/* complain_on_overflow */
c19d1205
ZW		 859 bfd_elf_generic_reloc, /* special_function */
860 "R_ARM_THM_PC12", /* name */
861 FALSE, /* partial_inplace */
2cab6cc3
MS		 862 0xffffffff, /* src_mask */
863 0xffffffff, /* dst_mask */
c19d1205
ZW		 864 TRUE), /* pcrel_offset */
865
866 HOWTO (R_ARM_ABS32_NOI, /* type */
867 0, /* rightshift */
868 2, /* size (0 = byte, 1 = short, 2 = long) */
869 32, /* bitsize */
870 FALSE, /* pc_relative */
871 0, /* bitpos */
872 complain_overflow_dont,/* complain_on_overflow */
873 bfd_elf_generic_reloc, /* special_function */
874 "R_ARM_ABS32_NOI", /* name */
875 FALSE, /* partial_inplace */
876 0xffffffff, /* src_mask */
877 0xffffffff, /* dst_mask */
878 FALSE), /* pcrel_offset */
879
880 HOWTO (R_ARM_REL32_NOI, /* type */
881 0, /* rightshift */
882 2, /* size (0 = byte, 1 = short, 2 = long) */
883 32, /* bitsize */
884 TRUE, /* pc_relative */
885 0, /* bitpos */
886 complain_overflow_dont,/* complain_on_overflow */
887 bfd_elf_generic_reloc, /* special_function */
888 "R_ARM_REL32_NOI", /* name */
889 FALSE, /* partial_inplace */
890 0xffffffff, /* src_mask */
891 0xffffffff, /* dst_mask */
892 FALSE), /* pcrel_offset */
7f266840 893
4962c51a
MS		 894 /* Group relocations. */
895
896 HOWTO (R_ARM_ALU_PC_G0_NC, /* type */
897 0, /* rightshift */
898 2, /* size (0 = byte, 1 = short, 2 = long) */
899 32, /* bitsize */
900 TRUE, /* pc_relative */
901 0, /* bitpos */
902 complain_overflow_dont,/* complain_on_overflow */
903 bfd_elf_generic_reloc, /* special_function */
904 "R_ARM_ALU_PC_G0_NC", /* name */
905 FALSE, /* partial_inplace */
906 0xffffffff, /* src_mask */
907 0xffffffff, /* dst_mask */
908 TRUE), /* pcrel_offset */
909
07d6d2b8 910 HOWTO (R_ARM_ALU_PC_G0, /* type */
4962c51a
MS		 911 0, /* rightshift */
912 2, /* size (0 = byte, 1 = short, 2 = long) */
913 32, /* bitsize */
914 TRUE, /* pc_relative */
915 0, /* bitpos */
916 complain_overflow_dont,/* complain_on_overflow */
917 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 918 "R_ARM_ALU_PC_G0", /* name */
4962c51a
MS		 919 FALSE, /* partial_inplace */
920 0xffffffff, /* src_mask */
921 0xffffffff, /* dst_mask */
922 TRUE), /* pcrel_offset */
923
924 HOWTO (R_ARM_ALU_PC_G1_NC, /* type */
925 0, /* rightshift */
926 2, /* size (0 = byte, 1 = short, 2 = long) */
927 32, /* bitsize */
928 TRUE, /* pc_relative */
929 0, /* bitpos */
930 complain_overflow_dont,/* complain_on_overflow */
931 bfd_elf_generic_reloc, /* special_function */
932 "R_ARM_ALU_PC_G1_NC", /* name */
933 FALSE, /* partial_inplace */
934 0xffffffff, /* src_mask */
935 0xffffffff, /* dst_mask */
936 TRUE), /* pcrel_offset */
937
07d6d2b8 938 HOWTO (R_ARM_ALU_PC_G1, /* type */
4962c51a
MS		 939 0, /* rightshift */
940 2, /* size (0 = byte, 1 = short, 2 = long) */
941 32, /* bitsize */
942 TRUE, /* pc_relative */
943 0, /* bitpos */
944 complain_overflow_dont,/* complain_on_overflow */
945 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 946 "R_ARM_ALU_PC_G1", /* name */
4962c51a
MS		 947 FALSE, /* partial_inplace */
948 0xffffffff, /* src_mask */
949 0xffffffff, /* dst_mask */
950 TRUE), /* pcrel_offset */
951
07d6d2b8 952 HOWTO (R_ARM_ALU_PC_G2, /* type */
4962c51a
MS		 953 0, /* rightshift */
954 2, /* size (0 = byte, 1 = short, 2 = long) */
955 32, /* bitsize */
956 TRUE, /* pc_relative */
957 0, /* bitpos */
958 complain_overflow_dont,/* complain_on_overflow */
959 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 960 "R_ARM_ALU_PC_G2", /* name */
4962c51a
MS		 961 FALSE, /* partial_inplace */
962 0xffffffff, /* src_mask */
963 0xffffffff, /* dst_mask */
964 TRUE), /* pcrel_offset */
965
07d6d2b8 966 HOWTO (R_ARM_LDR_PC_G1, /* type */
4962c51a
MS		 967 0, /* rightshift */
968 2, /* size (0 = byte, 1 = short, 2 = long) */
969 32, /* bitsize */
970 TRUE, /* pc_relative */
971 0, /* bitpos */
972 complain_overflow_dont,/* complain_on_overflow */
973 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 974 "R_ARM_LDR_PC_G1", /* name */
4962c51a
MS		 975 FALSE, /* partial_inplace */
976 0xffffffff, /* src_mask */
977 0xffffffff, /* dst_mask */
978 TRUE), /* pcrel_offset */
979
07d6d2b8 980 HOWTO (R_ARM_LDR_PC_G2, /* type */
4962c51a
MS		 981 0, /* rightshift */
982 2, /* size (0 = byte, 1 = short, 2 = long) */
983 32, /* bitsize */
984 TRUE, /* pc_relative */
985 0, /* bitpos */
986 complain_overflow_dont,/* complain_on_overflow */
987 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 988 "R_ARM_LDR_PC_G2", /* name */
4962c51a
MS		 989 FALSE, /* partial_inplace */
990 0xffffffff, /* src_mask */
991 0xffffffff, /* dst_mask */
992 TRUE), /* pcrel_offset */
993
07d6d2b8 994 HOWTO (R_ARM_LDRS_PC_G0, /* type */
4962c51a
MS		 995 0, /* rightshift */
996 2, /* size (0 = byte, 1 = short, 2 = long) */
997 32, /* bitsize */
998 TRUE, /* pc_relative */
999 0, /* bitpos */
1000 complain_overflow_dont,/* complain_on_overflow */
1001 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1002 "R_ARM_LDRS_PC_G0", /* name */
4962c51a
MS		 1003 FALSE, /* partial_inplace */
1004 0xffffffff, /* src_mask */
1005 0xffffffff, /* dst_mask */
1006 TRUE), /* pcrel_offset */
1007
07d6d2b8 1008 HOWTO (R_ARM_LDRS_PC_G1, /* type */
4962c51a
MS		 1009 0, /* rightshift */
1010 2, /* size (0 = byte, 1 = short, 2 = long) */
1011 32, /* bitsize */
1012 TRUE, /* pc_relative */
1013 0, /* bitpos */
1014 complain_overflow_dont,/* complain_on_overflow */
1015 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1016 "R_ARM_LDRS_PC_G1", /* name */
4962c51a
MS		 1017 FALSE, /* partial_inplace */
1018 0xffffffff, /* src_mask */
1019 0xffffffff, /* dst_mask */
1020 TRUE), /* pcrel_offset */
1021
07d6d2b8 1022 HOWTO (R_ARM_LDRS_PC_G2, /* type */
4962c51a
MS		 1023 0, /* rightshift */
1024 2, /* size (0 = byte, 1 = short, 2 = long) */
1025 32, /* bitsize */
1026 TRUE, /* pc_relative */
1027 0, /* bitpos */
1028 complain_overflow_dont,/* complain_on_overflow */
1029 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1030 "R_ARM_LDRS_PC_G2", /* name */
4962c51a
MS		 1031 FALSE, /* partial_inplace */
1032 0xffffffff, /* src_mask */
1033 0xffffffff, /* dst_mask */
1034 TRUE), /* pcrel_offset */
1035
07d6d2b8 1036 HOWTO (R_ARM_LDC_PC_G0, /* type */
4962c51a
MS		 1037 0, /* rightshift */
1038 2, /* size (0 = byte, 1 = short, 2 = long) */
1039 32, /* bitsize */
1040 TRUE, /* pc_relative */
1041 0, /* bitpos */
1042 complain_overflow_dont,/* complain_on_overflow */
1043 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1044 "R_ARM_LDC_PC_G0", /* name */
4962c51a
MS		 1045 FALSE, /* partial_inplace */
1046 0xffffffff, /* src_mask */
1047 0xffffffff, /* dst_mask */
1048 TRUE), /* pcrel_offset */
1049
07d6d2b8 1050 HOWTO (R_ARM_LDC_PC_G1, /* type */
4962c51a
MS		 1051 0, /* rightshift */
1052 2, /* size (0 = byte, 1 = short, 2 = long) */
1053 32, /* bitsize */
1054 TRUE, /* pc_relative */
1055 0, /* bitpos */
1056 complain_overflow_dont,/* complain_on_overflow */
1057 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1058 "R_ARM_LDC_PC_G1", /* name */
4962c51a
MS		 1059 FALSE, /* partial_inplace */
1060 0xffffffff, /* src_mask */
1061 0xffffffff, /* dst_mask */
1062 TRUE), /* pcrel_offset */
1063
07d6d2b8 1064 HOWTO (R_ARM_LDC_PC_G2, /* type */
4962c51a
MS		 1065 0, /* rightshift */
1066 2, /* size (0 = byte, 1 = short, 2 = long) */
1067 32, /* bitsize */
1068 TRUE, /* pc_relative */
1069 0, /* bitpos */
1070 complain_overflow_dont,/* complain_on_overflow */
1071 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1072 "R_ARM_LDC_PC_G2", /* name */
4962c51a
MS		 1073 FALSE, /* partial_inplace */
1074 0xffffffff, /* src_mask */
1075 0xffffffff, /* dst_mask */
1076 TRUE), /* pcrel_offset */
1077
07d6d2b8 1078 HOWTO (R_ARM_ALU_SB_G0_NC, /* type */
4962c51a
MS		 1079 0, /* rightshift */
1080 2, /* size (0 = byte, 1 = short, 2 = long) */
1081 32, /* bitsize */
1082 TRUE, /* pc_relative */
1083 0, /* bitpos */
1084 complain_overflow_dont,/* complain_on_overflow */
1085 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1086 "R_ARM_ALU_SB_G0_NC", /* name */
4962c51a
MS		 1087 FALSE, /* partial_inplace */
1088 0xffffffff, /* src_mask */
1089 0xffffffff, /* dst_mask */
1090 TRUE), /* pcrel_offset */
1091
07d6d2b8 1092 HOWTO (R_ARM_ALU_SB_G0, /* type */
4962c51a
MS		 1093 0, /* rightshift */
1094 2, /* size (0 = byte, 1 = short, 2 = long) */
1095 32, /* bitsize */
1096 TRUE, /* pc_relative */
1097 0, /* bitpos */
1098 complain_overflow_dont,/* complain_on_overflow */
1099 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1100 "R_ARM_ALU_SB_G0", /* name */
4962c51a
MS		 1101 FALSE, /* partial_inplace */
1102 0xffffffff, /* src_mask */
1103 0xffffffff, /* dst_mask */
1104 TRUE), /* pcrel_offset */
1105
07d6d2b8 1106 HOWTO (R_ARM_ALU_SB_G1_NC, /* type */
4962c51a
MS		 1107 0, /* rightshift */
1108 2, /* size (0 = byte, 1 = short, 2 = long) */
1109 32, /* bitsize */
1110 TRUE, /* pc_relative */
1111 0, /* bitpos */
1112 complain_overflow_dont,/* complain_on_overflow */
1113 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1114 "R_ARM_ALU_SB_G1_NC", /* name */
4962c51a
MS		 1115 FALSE, /* partial_inplace */
1116 0xffffffff, /* src_mask */
1117 0xffffffff, /* dst_mask */
1118 TRUE), /* pcrel_offset */
1119
07d6d2b8 1120 HOWTO (R_ARM_ALU_SB_G1, /* type */
4962c51a
MS		 1121 0, /* rightshift */
1122 2, /* size (0 = byte, 1 = short, 2 = long) */
1123 32, /* bitsize */
1124 TRUE, /* pc_relative */
1125 0, /* bitpos */
1126 complain_overflow_dont,/* complain_on_overflow */
1127 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1128 "R_ARM_ALU_SB_G1", /* name */
4962c51a
MS		 1129 FALSE, /* partial_inplace */
1130 0xffffffff, /* src_mask */
1131 0xffffffff, /* dst_mask */
1132 TRUE), /* pcrel_offset */
1133
07d6d2b8 1134 HOWTO (R_ARM_ALU_SB_G2, /* type */
4962c51a
MS		 1135 0, /* rightshift */
1136 2, /* size (0 = byte, 1 = short, 2 = long) */
1137 32, /* bitsize */
1138 TRUE, /* pc_relative */
1139 0, /* bitpos */
1140 complain_overflow_dont,/* complain_on_overflow */
1141 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1142 "R_ARM_ALU_SB_G2", /* name */
4962c51a
MS		 1143 FALSE, /* partial_inplace */
1144 0xffffffff, /* src_mask */
1145 0xffffffff, /* dst_mask */
1146 TRUE), /* pcrel_offset */
1147
07d6d2b8 1148 HOWTO (R_ARM_LDR_SB_G0, /* type */
4962c51a
MS		 1149 0, /* rightshift */
1150 2, /* size (0 = byte, 1 = short, 2 = long) */
1151 32, /* bitsize */
1152 TRUE, /* pc_relative */
1153 0, /* bitpos */
1154 complain_overflow_dont,/* complain_on_overflow */
1155 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1156 "R_ARM_LDR_SB_G0", /* name */
4962c51a
MS		 1157 FALSE, /* partial_inplace */
1158 0xffffffff, /* src_mask */
1159 0xffffffff, /* dst_mask */
1160 TRUE), /* pcrel_offset */
1161
07d6d2b8 1162 HOWTO (R_ARM_LDR_SB_G1, /* type */
4962c51a
MS		 1163 0, /* rightshift */
1164 2, /* size (0 = byte, 1 = short, 2 = long) */
1165 32, /* bitsize */
1166 TRUE, /* pc_relative */
1167 0, /* bitpos */
1168 complain_overflow_dont,/* complain_on_overflow */
1169 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1170 "R_ARM_LDR_SB_G1", /* name */
4962c51a
MS		 1171 FALSE, /* partial_inplace */
1172 0xffffffff, /* src_mask */
1173 0xffffffff, /* dst_mask */
1174 TRUE), /* pcrel_offset */
1175
07d6d2b8 1176 HOWTO (R_ARM_LDR_SB_G2, /* type */
4962c51a
MS		 1177 0, /* rightshift */
1178 2, /* size (0 = byte, 1 = short, 2 = long) */
1179 32, /* bitsize */
1180 TRUE, /* pc_relative */
1181 0, /* bitpos */
1182 complain_overflow_dont,/* complain_on_overflow */
1183 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1184 "R_ARM_LDR_SB_G2", /* name */
4962c51a
MS		 1185 FALSE, /* partial_inplace */
1186 0xffffffff, /* src_mask */
1187 0xffffffff, /* dst_mask */
1188 TRUE), /* pcrel_offset */
1189
07d6d2b8 1190 HOWTO (R_ARM_LDRS_SB_G0, /* type */
4962c51a
MS		 1191 0, /* rightshift */
1192 2, /* size (0 = byte, 1 = short, 2 = long) */
1193 32, /* bitsize */
1194 TRUE, /* pc_relative */
1195 0, /* bitpos */
1196 complain_overflow_dont,/* complain_on_overflow */
1197 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1198 "R_ARM_LDRS_SB_G0", /* name */
4962c51a
MS		 1199 FALSE, /* partial_inplace */
1200 0xffffffff, /* src_mask */
1201 0xffffffff, /* dst_mask */
1202 TRUE), /* pcrel_offset */
1203
07d6d2b8 1204 HOWTO (R_ARM_LDRS_SB_G1, /* type */
4962c51a
MS		 1205 0, /* rightshift */
1206 2, /* size (0 = byte, 1 = short, 2 = long) */
1207 32, /* bitsize */
1208 TRUE, /* pc_relative */
1209 0, /* bitpos */
1210 complain_overflow_dont,/* complain_on_overflow */
1211 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1212 "R_ARM_LDRS_SB_G1", /* name */
4962c51a
MS		 1213 FALSE, /* partial_inplace */
1214 0xffffffff, /* src_mask */
1215 0xffffffff, /* dst_mask */
1216 TRUE), /* pcrel_offset */
1217
07d6d2b8 1218 HOWTO (R_ARM_LDRS_SB_G2, /* type */
4962c51a
MS		 1219 0, /* rightshift */
1220 2, /* size (0 = byte, 1 = short, 2 = long) */
1221 32, /* bitsize */
1222 TRUE, /* pc_relative */
1223 0, /* bitpos */
1224 complain_overflow_dont,/* complain_on_overflow */
1225 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1226 "R_ARM_LDRS_SB_G2", /* name */
4962c51a
MS		 1227 FALSE, /* partial_inplace */
1228 0xffffffff, /* src_mask */
1229 0xffffffff, /* dst_mask */
1230 TRUE), /* pcrel_offset */
1231
07d6d2b8 1232 HOWTO (R_ARM_LDC_SB_G0, /* type */
4962c51a
MS		 1233 0, /* rightshift */
1234 2, /* size (0 = byte, 1 = short, 2 = long) */
1235 32, /* bitsize */
1236 TRUE, /* pc_relative */
1237 0, /* bitpos */
1238 complain_overflow_dont,/* complain_on_overflow */
1239 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1240 "R_ARM_LDC_SB_G0", /* name */
4962c51a
MS		 1241 FALSE, /* partial_inplace */
1242 0xffffffff, /* src_mask */
1243 0xffffffff, /* dst_mask */
1244 TRUE), /* pcrel_offset */
1245
07d6d2b8 1246 HOWTO (R_ARM_LDC_SB_G1, /* type */
4962c51a
MS		 1247 0, /* rightshift */
1248 2, /* size (0 = byte, 1 = short, 2 = long) */
1249 32, /* bitsize */
1250 TRUE, /* pc_relative */
1251 0, /* bitpos */
1252 complain_overflow_dont,/* complain_on_overflow */
1253 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1254 "R_ARM_LDC_SB_G1", /* name */
4962c51a
MS		 1255 FALSE, /* partial_inplace */
1256 0xffffffff, /* src_mask */
1257 0xffffffff, /* dst_mask */
1258 TRUE), /* pcrel_offset */
1259
07d6d2b8 1260 HOWTO (R_ARM_LDC_SB_G2, /* type */
4962c51a
MS		 1261 0, /* rightshift */
1262 2, /* size (0 = byte, 1 = short, 2 = long) */
1263 32, /* bitsize */
1264 TRUE, /* pc_relative */
1265 0, /* bitpos */
1266 complain_overflow_dont,/* complain_on_overflow */
1267 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1268 "R_ARM_LDC_SB_G2", /* name */
4962c51a
MS		 1269 FALSE, /* partial_inplace */
1270 0xffffffff, /* src_mask */
1271 0xffffffff, /* dst_mask */
1272 TRUE), /* pcrel_offset */
1273
1274 /* End of group relocations. */
c19d1205 1275
c19d1205
ZW		 1276 HOWTO (R_ARM_MOVW_BREL_NC, /* type */
1277 0, /* rightshift */
1278 2, /* size (0 = byte, 1 = short, 2 = long) */
1279 16, /* bitsize */
1280 FALSE, /* pc_relative */
1281 0, /* bitpos */
1282 complain_overflow_dont,/* complain_on_overflow */
1283 bfd_elf_generic_reloc, /* special_function */
1284 "R_ARM_MOVW_BREL_NC", /* name */
1285 FALSE, /* partial_inplace */
1286 0x0000ffff, /* src_mask */
1287 0x0000ffff, /* dst_mask */
1288 FALSE), /* pcrel_offset */
1289
1290 HOWTO (R_ARM_MOVT_BREL, /* type */
1291 0, /* rightshift */
1292 2, /* size (0 = byte, 1 = short, 2 = long) */
1293 16, /* bitsize */
1294 FALSE, /* pc_relative */
1295 0, /* bitpos */
1296 complain_overflow_bitfield,/* complain_on_overflow */
1297 bfd_elf_generic_reloc, /* special_function */
1298 "R_ARM_MOVT_BREL", /* name */
1299 FALSE, /* partial_inplace */
1300 0x0000ffff, /* src_mask */
1301 0x0000ffff, /* dst_mask */
1302 FALSE), /* pcrel_offset */
1303
1304 HOWTO (R_ARM_MOVW_BREL, /* type */
1305 0, /* rightshift */
1306 2, /* size (0 = byte, 1 = short, 2 = long) */
1307 16, /* bitsize */
1308 FALSE, /* pc_relative */
1309 0, /* bitpos */
1310 complain_overflow_dont,/* complain_on_overflow */
1311 bfd_elf_generic_reloc, /* special_function */
1312 "R_ARM_MOVW_BREL", /* name */
1313 FALSE, /* partial_inplace */
1314 0x0000ffff, /* src_mask */
1315 0x0000ffff, /* dst_mask */
1316 FALSE), /* pcrel_offset */
1317
1318 HOWTO (R_ARM_THM_MOVW_BREL_NC,/* type */
1319 0, /* rightshift */
1320 2, /* size (0 = byte, 1 = short, 2 = long) */
1321 16, /* bitsize */
1322 FALSE, /* pc_relative */
1323 0, /* bitpos */
1324 complain_overflow_dont,/* complain_on_overflow */
1325 bfd_elf_generic_reloc, /* special_function */
1326 "R_ARM_THM_MOVW_BREL_NC",/* name */
1327 FALSE, /* partial_inplace */
1328 0x040f70ff, /* src_mask */
1329 0x040f70ff, /* dst_mask */
1330 FALSE), /* pcrel_offset */
1331
1332 HOWTO (R_ARM_THM_MOVT_BREL, /* type */
1333 0, /* rightshift */
1334 2, /* size (0 = byte, 1 = short, 2 = long) */
1335 16, /* bitsize */
1336 FALSE, /* pc_relative */
1337 0, /* bitpos */
1338 complain_overflow_bitfield,/* complain_on_overflow */
1339 bfd_elf_generic_reloc, /* special_function */
1340 "R_ARM_THM_MOVT_BREL", /* name */
1341 FALSE, /* partial_inplace */
1342 0x040f70ff, /* src_mask */
1343 0x040f70ff, /* dst_mask */
1344 FALSE), /* pcrel_offset */
1345
1346 HOWTO (R_ARM_THM_MOVW_BREL, /* type */
1347 0, /* rightshift */
1348 2, /* size (0 = byte, 1 = short, 2 = long) */
1349 16, /* bitsize */
1350 FALSE, /* pc_relative */
1351 0, /* bitpos */
1352 complain_overflow_dont,/* complain_on_overflow */
1353 bfd_elf_generic_reloc, /* special_function */
1354 "R_ARM_THM_MOVW_BREL", /* name */
1355 FALSE, /* partial_inplace */
1356 0x040f70ff, /* src_mask */
1357 0x040f70ff, /* dst_mask */
1358 FALSE), /* pcrel_offset */
1359
0855e32b
NS		 1360 HOWTO (R_ARM_TLS_GOTDESC, /* type */
1361 0, /* rightshift */
1362 2, /* size (0 = byte, 1 = short, 2 = long) */
1363 32, /* bitsize */
1364 FALSE, /* pc_relative */
1365 0, /* bitpos */
1366 complain_overflow_bitfield,/* complain_on_overflow */
1367 NULL, /* special_function */
1368 "R_ARM_TLS_GOTDESC", /* name */
1369 TRUE, /* partial_inplace */
1370 0xffffffff, /* src_mask */
1371 0xffffffff, /* dst_mask */
1372 FALSE), /* pcrel_offset */
1373
1374 HOWTO (R_ARM_TLS_CALL, /* type */
1375 0, /* rightshift */
1376 2, /* size (0 = byte, 1 = short, 2 = long) */
1377 24, /* bitsize */
1378 FALSE, /* pc_relative */
1379 0, /* bitpos */
1380 complain_overflow_dont,/* complain_on_overflow */
1381 bfd_elf_generic_reloc, /* special_function */
1382 "R_ARM_TLS_CALL", /* name */
1383 FALSE, /* partial_inplace */
1384 0x00ffffff, /* src_mask */
1385 0x00ffffff, /* dst_mask */
1386 FALSE), /* pcrel_offset */
1387
1388 HOWTO (R_ARM_TLS_DESCSEQ, /* type */
1389 0, /* rightshift */
1390 2, /* size (0 = byte, 1 = short, 2 = long) */
1391 0, /* bitsize */
1392 FALSE, /* pc_relative */
1393 0, /* bitpos */
1394 complain_overflow_bitfield,/* complain_on_overflow */
1395 bfd_elf_generic_reloc, /* special_function */
1396 "R_ARM_TLS_DESCSEQ", /* name */
1397 FALSE, /* partial_inplace */
1398 0x00000000, /* src_mask */
1399 0x00000000, /* dst_mask */
1400 FALSE), /* pcrel_offset */
1401
1402 HOWTO (R_ARM_THM_TLS_CALL, /* type */
1403 0, /* rightshift */
1404 2, /* size (0 = byte, 1 = short, 2 = long) */
1405 24, /* bitsize */
1406 FALSE, /* pc_relative */
1407 0, /* bitpos */
1408 complain_overflow_dont,/* complain_on_overflow */
1409 bfd_elf_generic_reloc, /* special_function */
1410 "R_ARM_THM_TLS_CALL", /* name */
1411 FALSE, /* partial_inplace */
1412 0x07ff07ff, /* src_mask */
1413 0x07ff07ff, /* dst_mask */
1414 FALSE), /* pcrel_offset */
c19d1205
ZW		 1415
1416 HOWTO (R_ARM_PLT32_ABS, /* type */
1417 0, /* rightshift */
1418 2, /* size (0 = byte, 1 = short, 2 = long) */
1419 32, /* bitsize */
1420 FALSE, /* pc_relative */
1421 0, /* bitpos */
1422 complain_overflow_dont,/* complain_on_overflow */
1423 bfd_elf_generic_reloc, /* special_function */
1424 "R_ARM_PLT32_ABS", /* name */
1425 FALSE, /* partial_inplace */
1426 0xffffffff, /* src_mask */
1427 0xffffffff, /* dst_mask */
1428 FALSE), /* pcrel_offset */
1429
1430 HOWTO (R_ARM_GOT_ABS, /* type */
1431 0, /* rightshift */
1432 2, /* size (0 = byte, 1 = short, 2 = long) */
1433 32, /* bitsize */
1434 FALSE, /* pc_relative */
1435 0, /* bitpos */
1436 complain_overflow_dont,/* complain_on_overflow */
1437 bfd_elf_generic_reloc, /* special_function */
1438 "R_ARM_GOT_ABS", /* name */
1439 FALSE, /* partial_inplace */
1440 0xffffffff, /* src_mask */
1441 0xffffffff, /* dst_mask */
1442 FALSE), /* pcrel_offset */
1443
1444 HOWTO (R_ARM_GOT_PREL, /* type */
1445 0, /* rightshift */
1446 2, /* size (0 = byte, 1 = short, 2 = long) */
1447 32, /* bitsize */
1448 TRUE, /* pc_relative */
1449 0, /* bitpos */
1450 complain_overflow_dont, /* complain_on_overflow */
1451 bfd_elf_generic_reloc, /* special_function */
1452 "R_ARM_GOT_PREL", /* name */
1453 FALSE, /* partial_inplace */
1454 0xffffffff, /* src_mask */
1455 0xffffffff, /* dst_mask */
1456 TRUE), /* pcrel_offset */
1457
1458 HOWTO (R_ARM_GOT_BREL12, /* type */
1459 0, /* rightshift */
1460 2, /* size (0 = byte, 1 = short, 2 = long) */
1461 12, /* bitsize */
1462 FALSE, /* pc_relative */
1463 0, /* bitpos */
1464 complain_overflow_bitfield,/* complain_on_overflow */
1465 bfd_elf_generic_reloc, /* special_function */
1466 "R_ARM_GOT_BREL12", /* name */
1467 FALSE, /* partial_inplace */
1468 0x00000fff, /* src_mask */
1469 0x00000fff, /* dst_mask */
1470 FALSE), /* pcrel_offset */
1471
1472 HOWTO (R_ARM_GOTOFF12, /* type */
1473 0, /* rightshift */
1474 2, /* size (0 = byte, 1 = short, 2 = long) */
1475 12, /* bitsize */
1476 FALSE, /* pc_relative */
1477 0, /* bitpos */
1478 complain_overflow_bitfield,/* complain_on_overflow */
1479 bfd_elf_generic_reloc, /* special_function */
1480 "R_ARM_GOTOFF12", /* name */
1481 FALSE, /* partial_inplace */
1482 0x00000fff, /* src_mask */
1483 0x00000fff, /* dst_mask */
1484 FALSE), /* pcrel_offset */
1485
07d6d2b8 1486 EMPTY_HOWTO (R_ARM_GOTRELAX), /* reserved for future GOT-load optimizations */
c19d1205
ZW		 1487
1488 /* GNU extension to record C++ vtable member usage */
07d6d2b8
AM		 1489 HOWTO (R_ARM_GNU_VTENTRY, /* type */
1490 0, /* rightshift */
1491 2, /* size (0 = byte, 1 = short, 2 = long) */
1492 0, /* bitsize */
1493 FALSE, /* pc_relative */
1494 0, /* bitpos */
99059e56 1495 complain_overflow_dont, /* complain_on_overflow */
07d6d2b8
AM		 1496 _bfd_elf_rel_vtable_reloc_fn, /* special_function */
1497 "R_ARM_GNU_VTENTRY", /* name */
1498 FALSE, /* partial_inplace */
1499 0, /* src_mask */
1500 0, /* dst_mask */
1501 FALSE), /* pcrel_offset */
c19d1205
ZW		 1502
1503 /* GNU extension to record C++ vtable hierarchy */
1504 HOWTO (R_ARM_GNU_VTINHERIT, /* type */
07d6d2b8
AM		 1505 0, /* rightshift */
1506 2, /* size (0 = byte, 1 = short, 2 = long) */
1507 0, /* bitsize */
1508 FALSE, /* pc_relative */
1509 0, /* bitpos */
99059e56 1510 complain_overflow_dont, /* complain_on_overflow */
07d6d2b8 1511 NULL, /* special_function */
99059e56 1512 "R_ARM_GNU_VTINHERIT", /* name */
07d6d2b8
AM		 1513 FALSE, /* partial_inplace */
1514 0, /* src_mask */
1515 0, /* dst_mask */
1516 FALSE), /* pcrel_offset */
c19d1205
ZW		 1517
1518 HOWTO (R_ARM_THM_JUMP11, /* type */
1519 1, /* rightshift */
1520 1, /* size (0 = byte, 1 = short, 2 = long) */
1521 11, /* bitsize */
1522 TRUE, /* pc_relative */
1523 0, /* bitpos */
1524 complain_overflow_signed, /* complain_on_overflow */
1525 bfd_elf_generic_reloc, /* special_function */
1526 "R_ARM_THM_JUMP11", /* name */
1527 FALSE, /* partial_inplace */
1528 0x000007ff, /* src_mask */
1529 0x000007ff, /* dst_mask */
1530 TRUE), /* pcrel_offset */
1531
1532 HOWTO (R_ARM_THM_JUMP8, /* type */
1533 1, /* rightshift */
1534 1, /* size (0 = byte, 1 = short, 2 = long) */
1535 8, /* bitsize */
1536 TRUE, /* pc_relative */
1537 0, /* bitpos */
1538 complain_overflow_signed, /* complain_on_overflow */
1539 bfd_elf_generic_reloc, /* special_function */
1540 "R_ARM_THM_JUMP8", /* name */
1541 FALSE, /* partial_inplace */
1542 0x000000ff, /* src_mask */
1543 0x000000ff, /* dst_mask */
1544 TRUE), /* pcrel_offset */
ba93b8ac 1545
c19d1205
ZW		 1546 /* TLS relocations */
1547 HOWTO (R_ARM_TLS_GD32, /* type */
07d6d2b8
AM		 1548 0, /* rightshift */
1549 2, /* size (0 = byte, 1 = short, 2 = long) */
1550 32, /* bitsize */
1551 FALSE, /* pc_relative */
1552 0, /* bitpos */
99059e56
RM		 1553 complain_overflow_bitfield,/* complain_on_overflow */
1554 NULL, /* special_function */
1555 "R_ARM_TLS_GD32", /* name */
1556 TRUE, /* partial_inplace */
1557 0xffffffff, /* src_mask */
1558 0xffffffff, /* dst_mask */
07d6d2b8 1559 FALSE), /* pcrel_offset */
ba93b8ac 1560
ba93b8ac 1561 HOWTO (R_ARM_TLS_LDM32, /* type */
07d6d2b8
AM		 1562 0, /* rightshift */
1563 2, /* size (0 = byte, 1 = short, 2 = long) */
1564 32, /* bitsize */
1565 FALSE, /* pc_relative */
1566 0, /* bitpos */
99059e56
RM		 1567 complain_overflow_bitfield,/* complain_on_overflow */
1568 bfd_elf_generic_reloc, /* special_function */
1569 "R_ARM_TLS_LDM32", /* name */
1570 TRUE, /* partial_inplace */
1571 0xffffffff, /* src_mask */
1572 0xffffffff, /* dst_mask */
07d6d2b8 1573 FALSE), /* pcrel_offset */
ba93b8ac 1574
c19d1205 1575 HOWTO (R_ARM_TLS_LDO32, /* type */
07d6d2b8
AM		 1576 0, /* rightshift */
1577 2, /* size (0 = byte, 1 = short, 2 = long) */
1578 32, /* bitsize */
1579 FALSE, /* pc_relative */
1580 0, /* bitpos */
99059e56
RM		 1581 complain_overflow_bitfield,/* complain_on_overflow */
1582 bfd_elf_generic_reloc, /* special_function */
1583 "R_ARM_TLS_LDO32", /* name */
1584 TRUE, /* partial_inplace */
1585 0xffffffff, /* src_mask */
1586 0xffffffff, /* dst_mask */
07d6d2b8 1587 FALSE), /* pcrel_offset */
ba93b8ac 1588
ba93b8ac 1589 HOWTO (R_ARM_TLS_IE32, /* type */
07d6d2b8
AM		 1590 0, /* rightshift */
1591 2, /* size (0 = byte, 1 = short, 2 = long) */
1592 32, /* bitsize */
1593 FALSE, /* pc_relative */
1594 0, /* bitpos */
99059e56
RM		 1595 complain_overflow_bitfield,/* complain_on_overflow */
1596 NULL, /* special_function */
1597 "R_ARM_TLS_IE32", /* name */
1598 TRUE, /* partial_inplace */
1599 0xffffffff, /* src_mask */
1600 0xffffffff, /* dst_mask */
07d6d2b8 1601 FALSE), /* pcrel_offset */
7f266840 1602
c19d1205 1603 HOWTO (R_ARM_TLS_LE32, /* type */
07d6d2b8
AM		 1604 0, /* rightshift */
1605 2, /* size (0 = byte, 1 = short, 2 = long) */
1606 32, /* bitsize */
1607 FALSE, /* pc_relative */
1608 0, /* bitpos */
99059e56 1609 complain_overflow_bitfield,/* complain_on_overflow */
07d6d2b8 1610 NULL, /* special_function */
99059e56
RM		 1611 "R_ARM_TLS_LE32", /* name */
1612 TRUE, /* partial_inplace */
1613 0xffffffff, /* src_mask */
1614 0xffffffff, /* dst_mask */
07d6d2b8 1615 FALSE), /* pcrel_offset */
7f266840 1616
c19d1205
ZW		 1617 HOWTO (R_ARM_TLS_LDO12, /* type */
1618 0, /* rightshift */
1619 2, /* size (0 = byte, 1 = short, 2 = long) */
1620 12, /* bitsize */
1621 FALSE, /* pc_relative */
7f266840 1622 0, /* bitpos */
c19d1205 1623 complain_overflow_bitfield,/* complain_on_overflow */
7f266840 1624 bfd_elf_generic_reloc, /* special_function */
c19d1205 1625 "R_ARM_TLS_LDO12", /* name */
7f266840 1626 FALSE, /* partial_inplace */
c19d1205
ZW		 1627 0x00000fff, /* src_mask */
1628 0x00000fff, /* dst_mask */
1629 FALSE), /* pcrel_offset */
7f266840 1630
c19d1205
ZW		 1631 HOWTO (R_ARM_TLS_LE12, /* type */
1632 0, /* rightshift */
1633 2, /* size (0 = byte, 1 = short, 2 = long) */
1634 12, /* bitsize */
1635 FALSE, /* pc_relative */
7f266840 1636 0, /* bitpos */
c19d1205 1637 complain_overflow_bitfield,/* complain_on_overflow */
7f266840 1638 bfd_elf_generic_reloc, /* special_function */
c19d1205 1639 "R_ARM_TLS_LE12", /* name */
7f266840 1640 FALSE, /* partial_inplace */
c19d1205
ZW		 1641 0x00000fff, /* src_mask */
1642 0x00000fff, /* dst_mask */
1643 FALSE), /* pcrel_offset */
7f266840 1644
c19d1205 1645 HOWTO (R_ARM_TLS_IE12GP, /* type */
7f266840
DJ		 1646 0, /* rightshift */
1647 2, /* size (0 = byte, 1 = short, 2 = long) */
c19d1205
ZW		 1648 12, /* bitsize */
1649 FALSE, /* pc_relative */
7f266840 1650 0, /* bitpos */
c19d1205 1651 complain_overflow_bitfield,/* complain_on_overflow */
7f266840 1652 bfd_elf_generic_reloc, /* special_function */
c19d1205 1653 "R_ARM_TLS_IE12GP", /* name */
7f266840 1654 FALSE, /* partial_inplace */
c19d1205
ZW		 1655 0x00000fff, /* src_mask */
1656 0x00000fff, /* dst_mask */
1657 FALSE), /* pcrel_offset */
0855e32b 1658
34e77a92 1659 /* 112-127 private relocations. */
0855e32b
NS		 1660 EMPTY_HOWTO (112),
1661 EMPTY_HOWTO (113),
1662 EMPTY_HOWTO (114),
1663 EMPTY_HOWTO (115),
1664 EMPTY_HOWTO (116),
1665 EMPTY_HOWTO (117),
1666 EMPTY_HOWTO (118),
1667 EMPTY_HOWTO (119),
1668 EMPTY_HOWTO (120),
1669 EMPTY_HOWTO (121),
1670 EMPTY_HOWTO (122),
1671 EMPTY_HOWTO (123),
1672 EMPTY_HOWTO (124),
1673 EMPTY_HOWTO (125),
1674 EMPTY_HOWTO (126),
1675 EMPTY_HOWTO (127),
34e77a92
RS		 1676
1677 /* R_ARM_ME_TOO, obsolete. */
0855e32b
NS		 1678 EMPTY_HOWTO (128),
1679
1680 HOWTO (R_ARM_THM_TLS_DESCSEQ, /* type */
1681 0, /* rightshift */
1682 1, /* size (0 = byte, 1 = short, 2 = long) */
1683 0, /* bitsize */
1684 FALSE, /* pc_relative */
1685 0, /* bitpos */
1686 complain_overflow_bitfield,/* complain_on_overflow */
1687 bfd_elf_generic_reloc, /* special_function */
1688 "R_ARM_THM_TLS_DESCSEQ",/* name */
1689 FALSE, /* partial_inplace */
1690 0x00000000, /* src_mask */
1691 0x00000000, /* dst_mask */
1692 FALSE), /* pcrel_offset */
72d98d16
MG		 1693 EMPTY_HOWTO (130),
1694 EMPTY_HOWTO (131),
1695 HOWTO (R_ARM_THM_ALU_ABS_G0_NC,/* type. */
1696 0, /* rightshift. */
1697 1, /* size (0 = byte, 1 = short, 2 = long). */
1698 16, /* bitsize. */
1699 FALSE, /* pc_relative. */
1700 0, /* bitpos. */
1701 complain_overflow_bitfield,/* complain_on_overflow. */
1702 bfd_elf_generic_reloc, /* special_function. */
1703 "R_ARM_THM_ALU_ABS_G0_NC",/* name. */
1704 FALSE, /* partial_inplace. */
1705 0x00000000, /* src_mask. */
1706 0x00000000, /* dst_mask. */
1707 FALSE), /* pcrel_offset. */
1708 HOWTO (R_ARM_THM_ALU_ABS_G1_NC,/* type. */
1709 0, /* rightshift. */
1710 1, /* size (0 = byte, 1 = short, 2 = long). */
1711 16, /* bitsize. */
1712 FALSE, /* pc_relative. */
1713 0, /* bitpos. */
1714 complain_overflow_bitfield,/* complain_on_overflow. */
1715 bfd_elf_generic_reloc, /* special_function. */
1716 "R_ARM_THM_ALU_ABS_G1_NC",/* name. */
1717 FALSE, /* partial_inplace. */
1718 0x00000000, /* src_mask. */
1719 0x00000000, /* dst_mask. */
1720 FALSE), /* pcrel_offset. */
1721 HOWTO (R_ARM_THM_ALU_ABS_G2_NC,/* type. */
1722 0, /* rightshift. */
1723 1, /* size (0 = byte, 1 = short, 2 = long). */
1724 16, /* bitsize. */
1725 FALSE, /* pc_relative. */
1726 0, /* bitpos. */
1727 complain_overflow_bitfield,/* complain_on_overflow. */
1728 bfd_elf_generic_reloc, /* special_function. */
1729 "R_ARM_THM_ALU_ABS_G2_NC",/* name. */
1730 FALSE, /* partial_inplace. */
1731 0x00000000, /* src_mask. */
1732 0x00000000, /* dst_mask. */
1733 FALSE), /* pcrel_offset. */
1734 HOWTO (R_ARM_THM_ALU_ABS_G3_NC,/* type. */
1735 0, /* rightshift. */
1736 1, /* size (0 = byte, 1 = short, 2 = long). */
1737 16, /* bitsize. */
1738 FALSE, /* pc_relative. */
1739 0, /* bitpos. */
1740 complain_overflow_bitfield,/* complain_on_overflow. */
1741 bfd_elf_generic_reloc, /* special_function. */
1742 "R_ARM_THM_ALU_ABS_G3_NC",/* name. */
1743 FALSE, /* partial_inplace. */
1744 0x00000000, /* src_mask. */
1745 0x00000000, /* dst_mask. */
1746 FALSE), /* pcrel_offset. */
e5d6e09e
AV		 1747 /* Relocations for Armv8.1-M Mainline. */
1748 HOWTO (R_ARM_THM_BF16, /* type. */
1749 0, /* rightshift. */
1750 1, /* size (0 = byte, 1 = short, 2 = long). */
1751 16, /* bitsize. */
1752 TRUE, /* pc_relative. */
1753 0, /* bitpos. */
1754 complain_overflow_dont,/* do not complain_on_overflow. */
1755 bfd_elf_generic_reloc, /* special_function. */
1756 "R_ARM_THM_BF16", /* name. */
1757 FALSE, /* partial_inplace. */
1758 0x001f0ffe, /* src_mask. */
1759 0x001f0ffe, /* dst_mask. */
1760 TRUE), /* pcrel_offset. */
1889da70
AV		 1761 HOWTO (R_ARM_THM_BF12, /* type. */
1762 0, /* rightshift. */
1763 1, /* size (0 = byte, 1 = short, 2 = long). */
1764 12, /* bitsize. */
1765 TRUE, /* pc_relative. */
1766 0, /* bitpos. */
1767 complain_overflow_dont,/* do not complain_on_overflow. */
1768 bfd_elf_generic_reloc, /* special_function. */
1769 "R_ARM_THM_BF12", /* name. */
1770 FALSE, /* partial_inplace. */
1771 0x00010ffe, /* src_mask. */
1772 0x00010ffe, /* dst_mask. */
1773 TRUE), /* pcrel_offset. */
1caf72a5
AV		 1774 HOWTO (R_ARM_THM_BF18, /* type. */
1775 0, /* rightshift. */
1776 1, /* size (0 = byte, 1 = short, 2 = long). */
1777 18, /* bitsize. */
1778 TRUE, /* pc_relative. */
1779 0, /* bitpos. */
1780 complain_overflow_dont,/* do not complain_on_overflow. */
1781 bfd_elf_generic_reloc, /* special_function. */
1782 "R_ARM_THM_BF18", /* name. */
1783 FALSE, /* partial_inplace. */
1784 0x007f0ffe, /* src_mask. */
1785 0x007f0ffe, /* dst_mask. */
1786 TRUE), /* pcrel_offset. */
c19d1205
ZW		 1787};
1788
34e77a92 1789/* 160 onwards: */
5c5a4843 1790static reloc_howto_type elf32_arm_howto_table_2[8] =
34e77a92
RS		 1791{
1792 HOWTO (R_ARM_IRELATIVE, /* type */
07d6d2b8
AM		 1793 0, /* rightshift */
1794 2, /* size (0 = byte, 1 = short, 2 = long) */
1795 32, /* bitsize */
1796 FALSE, /* pc_relative */
1797 0, /* bitpos */
99059e56
RM		 1798 complain_overflow_bitfield,/* complain_on_overflow */
1799 bfd_elf_generic_reloc, /* special_function */
1800 "R_ARM_IRELATIVE", /* name */
1801 TRUE, /* partial_inplace */
1802 0xffffffff, /* src_mask */
1803 0xffffffff, /* dst_mask */
188fd7ae
CL		 1804 FALSE), /* pcrel_offset */
1805 HOWTO (R_ARM_GOTFUNCDESC, /* type */
1806 0, /* rightshift */
1807 2, /* size (0 = byte, 1 = short, 2 = long) */
1808 32, /* bitsize */
1809 FALSE, /* pc_relative */
1810 0, /* bitpos */
1811 complain_overflow_bitfield,/* complain_on_overflow */
1812 bfd_elf_generic_reloc, /* special_function */
1813 "R_ARM_GOTFUNCDESC", /* name */
1814 FALSE, /* partial_inplace */
1815 0, /* src_mask */
1816 0xffffffff, /* dst_mask */
1817 FALSE), /* pcrel_offset */
1818 HOWTO (R_ARM_GOTOFFFUNCDESC, /* type */
1819 0, /* rightshift */
1820 2, /* size (0 = byte, 1 = short, 2 = long) */
1821 32, /* bitsize */
1822 FALSE, /* pc_relative */
1823 0, /* bitpos */
1824 complain_overflow_bitfield,/* complain_on_overflow */
1825 bfd_elf_generic_reloc, /* special_function */
1826 "R_ARM_GOTOFFFUNCDESC",/* name */
1827 FALSE, /* partial_inplace */
1828 0, /* src_mask */
1829 0xffffffff, /* dst_mask */
1830 FALSE), /* pcrel_offset */
1831 HOWTO (R_ARM_FUNCDESC, /* type */
1832 0, /* rightshift */
1833 2, /* size (0 = byte, 1 = short, 2 = long) */
1834 32, /* bitsize */
1835 FALSE, /* pc_relative */
1836 0, /* bitpos */
1837 complain_overflow_bitfield,/* complain_on_overflow */
1838 bfd_elf_generic_reloc, /* special_function */
1839 "R_ARM_FUNCDESC", /* name */
1840 FALSE, /* partial_inplace */
1841 0, /* src_mask */
1842 0xffffffff, /* dst_mask */
1843 FALSE), /* pcrel_offset */
1844 HOWTO (R_ARM_FUNCDESC_VALUE, /* type */
1845 0, /* rightshift */
1846 2, /* size (0 = byte, 1 = short, 2 = long) */
1847 64, /* bitsize */
1848 FALSE, /* pc_relative */
1849 0, /* bitpos */
1850 complain_overflow_bitfield,/* complain_on_overflow */
1851 bfd_elf_generic_reloc, /* special_function */
1852 "R_ARM_FUNCDESC_VALUE",/* name */
1853 FALSE, /* partial_inplace */
1854 0, /* src_mask */
1855 0xffffffff, /* dst_mask */
1856 FALSE), /* pcrel_offset */
5c5a4843
CL		 1857 HOWTO (R_ARM_TLS_GD32_FDPIC, /* type */
1858 0, /* rightshift */
1859 2, /* size (0 = byte, 1 = short, 2 = long) */
1860 32, /* bitsize */
1861 FALSE, /* pc_relative */
1862 0, /* bitpos */
1863 complain_overflow_bitfield,/* complain_on_overflow */
1864 bfd_elf_generic_reloc, /* special_function */
1865 "R_ARM_TLS_GD32_FDPIC",/* name */
1866 FALSE, /* partial_inplace */
1867 0, /* src_mask */
1868 0xffffffff, /* dst_mask */
1869 FALSE), /* pcrel_offset */
1870 HOWTO (R_ARM_TLS_LDM32_FDPIC, /* type */
1871 0, /* rightshift */
1872 2, /* size (0 = byte, 1 = short, 2 = long) */
1873 32, /* bitsize */
1874 FALSE, /* pc_relative */
1875 0, /* bitpos */
1876 complain_overflow_bitfield,/* complain_on_overflow */
1877 bfd_elf_generic_reloc, /* special_function */
1878 "R_ARM_TLS_LDM32_FDPIC",/* name */
1879 FALSE, /* partial_inplace */
1880 0, /* src_mask */
1881 0xffffffff, /* dst_mask */
1882 FALSE), /* pcrel_offset */
1883 HOWTO (R_ARM_TLS_IE32_FDPIC, /* type */
1884 0, /* rightshift */
1885 2, /* size (0 = byte, 1 = short, 2 = long) */
1886 32, /* bitsize */
1887 FALSE, /* pc_relative */
1888 0, /* bitpos */
1889 complain_overflow_bitfield,/* complain_on_overflow */
1890 bfd_elf_generic_reloc, /* special_function */
1891 "R_ARM_TLS_IE32_FDPIC",/* name */
1892 FALSE, /* partial_inplace */
1893 0, /* src_mask */
1894 0xffffffff, /* dst_mask */
1895 FALSE), /* pcrel_offset */
34e77a92 1896};
c19d1205 1897
34e77a92
RS		 1898/* 249-255 extended, currently unused, relocations: */
1899static reloc_howto_type elf32_arm_howto_table_3[4] =
7f266840
DJ		 1900{
1901 HOWTO (R_ARM_RREL32, /* type */
1902 0, /* rightshift */
1903 0, /* size (0 = byte, 1 = short, 2 = long) */
1904 0, /* bitsize */
1905 FALSE, /* pc_relative */
1906 0, /* bitpos */
1907 complain_overflow_dont,/* complain_on_overflow */
1908 bfd_elf_generic_reloc, /* special_function */
1909 "R_ARM_RREL32", /* name */
1910 FALSE, /* partial_inplace */
1911 0, /* src_mask */
1912 0, /* dst_mask */
1913 FALSE), /* pcrel_offset */
1914
1915 HOWTO (R_ARM_RABS32, /* type */
1916 0, /* rightshift */
1917 0, /* size (0 = byte, 1 = short, 2 = long) */
1918 0, /* bitsize */
1919 FALSE, /* pc_relative */
1920 0, /* bitpos */
1921 complain_overflow_dont,/* complain_on_overflow */
1922 bfd_elf_generic_reloc, /* special_function */
1923 "R_ARM_RABS32", /* name */
1924 FALSE, /* partial_inplace */
1925 0, /* src_mask */
1926 0, /* dst_mask */
1927 FALSE), /* pcrel_offset */
1928
1929 HOWTO (R_ARM_RPC24, /* type */
1930 0, /* rightshift */
1931 0, /* size (0 = byte, 1 = short, 2 = long) */
1932 0, /* bitsize */
1933 FALSE, /* pc_relative */
1934 0, /* bitpos */
1935 complain_overflow_dont,/* complain_on_overflow */
1936 bfd_elf_generic_reloc, /* special_function */
1937 "R_ARM_RPC24", /* name */
1938 FALSE, /* partial_inplace */
1939 0, /* src_mask */
1940 0, /* dst_mask */
1941 FALSE), /* pcrel_offset */
1942
1943 HOWTO (R_ARM_RBASE, /* type */
1944 0, /* rightshift */
1945 0, /* size (0 = byte, 1 = short, 2 = long) */
1946 0, /* bitsize */
1947 FALSE, /* pc_relative */
1948 0, /* bitpos */
1949 complain_overflow_dont,/* complain_on_overflow */
1950 bfd_elf_generic_reloc, /* special_function */
1951 "R_ARM_RBASE", /* name */
1952 FALSE, /* partial_inplace */
1953 0, /* src_mask */
1954 0, /* dst_mask */
1955 FALSE) /* pcrel_offset */
1956};
1957
1958static reloc_howto_type *
1959elf32_arm_howto_from_type (unsigned int r_type)
1960{
906e58ca 1961 if (r_type < ARRAY_SIZE (elf32_arm_howto_table_1))
c19d1205 1962 return &elf32_arm_howto_table_1[r_type];
ba93b8ac 1963
188fd7ae
CL		 1964 if (r_type >= R_ARM_IRELATIVE
1965 && r_type < R_ARM_IRELATIVE + ARRAY_SIZE (elf32_arm_howto_table_2))
34e77a92
RS		 1966 return &elf32_arm_howto_table_2[r_type - R_ARM_IRELATIVE];
1967
c19d1205 1968 if (r_type >= R_ARM_RREL32
34e77a92
RS		 1969 && r_type < R_ARM_RREL32 + ARRAY_SIZE (elf32_arm_howto_table_3))
1970 return &elf32_arm_howto_table_3[r_type - R_ARM_RREL32];
7f266840 1971
c19d1205 1972 return NULL;
7f266840
DJ		 1973}
1974
f3185997
NC		 1975static bfd_boolean
1976elf32_arm_info_to_howto (bfd * abfd, arelent * bfd_reloc,
7f266840
DJ		 1977 Elf_Internal_Rela * elf_reloc)
1978{
1979 unsigned int r_type;
1980
1981 r_type = ELF32_R_TYPE (elf_reloc->r_info);
f3185997
NC		 1982 if ((bfd_reloc->howto = elf32_arm_howto_from_type (r_type)) == NULL)
1983 {
1984 /* xgettext:c-format */
1985 _bfd_error_handler (_("%pB: unsupported relocation type %#x"),
1986 abfd, r_type);
1987 bfd_set_error (bfd_error_bad_value);
1988 return FALSE;
1989 }
1990 return TRUE;
7f266840
DJ		 1991}
1992
1993struct elf32_arm_reloc_map
1994 {
1995 bfd_reloc_code_real_type bfd_reloc_val;
07d6d2b8 1996 unsigned char elf_reloc_val;
7f266840
DJ		 1997 };
1998
1999/* All entries in this list must also be present in elf32_arm_howto_table. */
2000static const struct elf32_arm_reloc_map elf32_arm_reloc_map[] =
2001 {
07d6d2b8 2002 {BFD_RELOC_NONE, R_ARM_NONE},
7f266840 2003 {BFD_RELOC_ARM_PCREL_BRANCH, R_ARM_PC24},
39b41c9c
PB		 2004 {BFD_RELOC_ARM_PCREL_CALL, R_ARM_CALL},
2005 {BFD_RELOC_ARM_PCREL_JUMP, R_ARM_JUMP24},
07d6d2b8
AM		 2006 {BFD_RELOC_ARM_PCREL_BLX, R_ARM_XPC25},
2007 {BFD_RELOC_THUMB_PCREL_BLX, R_ARM_THM_XPC22},
2008 {BFD_RELOC_32, R_ARM_ABS32},
2009 {BFD_RELOC_32_PCREL, R_ARM_REL32},
2010 {BFD_RELOC_8, R_ARM_ABS8},
2011 {BFD_RELOC_16, R_ARM_ABS16},
2012 {BFD_RELOC_ARM_OFFSET_IMM, R_ARM_ABS12},
7f266840 2013 {BFD_RELOC_ARM_THUMB_OFFSET, R_ARM_THM_ABS5},
c19d1205
ZW		 2014 {BFD_RELOC_THUMB_PCREL_BRANCH25, R_ARM_THM_JUMP24},
2015 {BFD_RELOC_THUMB_PCREL_BRANCH23, R_ARM_THM_CALL},
2016 {BFD_RELOC_THUMB_PCREL_BRANCH12, R_ARM_THM_JUMP11},
2017 {BFD_RELOC_THUMB_PCREL_BRANCH20, R_ARM_THM_JUMP19},
2018 {BFD_RELOC_THUMB_PCREL_BRANCH9, R_ARM_THM_JUMP8},
2019 {BFD_RELOC_THUMB_PCREL_BRANCH7, R_ARM_THM_JUMP6},
07d6d2b8
AM		 2020 {BFD_RELOC_ARM_GLOB_DAT, R_ARM_GLOB_DAT},
2021 {BFD_RELOC_ARM_JUMP_SLOT, R_ARM_JUMP_SLOT},
2022 {BFD_RELOC_ARM_RELATIVE, R_ARM_RELATIVE},
2023 {BFD_RELOC_ARM_GOTOFF, R_ARM_GOTOFF32},
2024 {BFD_RELOC_ARM_GOTPC, R_ARM_GOTPC},
2025 {BFD_RELOC_ARM_GOT_PREL, R_ARM_GOT_PREL},
2026 {BFD_RELOC_ARM_GOT32, R_ARM_GOT32},
2027 {BFD_RELOC_ARM_PLT32, R_ARM_PLT32},
7f266840
DJ		 2028 {BFD_RELOC_ARM_TARGET1, R_ARM_TARGET1},
2029 {BFD_RELOC_ARM_ROSEGREL32, R_ARM_ROSEGREL32},
2030 {BFD_RELOC_ARM_SBREL32, R_ARM_SBREL32},
2031 {BFD_RELOC_ARM_PREL31, R_ARM_PREL31},
ba93b8ac 2032 {BFD_RELOC_ARM_TARGET2, R_ARM_TARGET2},
07d6d2b8
AM		 2033 {BFD_RELOC_ARM_PLT32, R_ARM_PLT32},
2034 {BFD_RELOC_ARM_TLS_GOTDESC, R_ARM_TLS_GOTDESC},
2035 {BFD_RELOC_ARM_TLS_CALL, R_ARM_TLS_CALL},
0855e32b 2036 {BFD_RELOC_ARM_THM_TLS_CALL, R_ARM_THM_TLS_CALL},
07d6d2b8 2037 {BFD_RELOC_ARM_TLS_DESCSEQ, R_ARM_TLS_DESCSEQ},
0855e32b 2038 {BFD_RELOC_ARM_THM_TLS_DESCSEQ, R_ARM_THM_TLS_DESCSEQ},
07d6d2b8 2039 {BFD_RELOC_ARM_TLS_DESC, R_ARM_TLS_DESC},
ba93b8ac
DJ		 2040 {BFD_RELOC_ARM_TLS_GD32, R_ARM_TLS_GD32},
2041 {BFD_RELOC_ARM_TLS_LDO32, R_ARM_TLS_LDO32},
2042 {BFD_RELOC_ARM_TLS_LDM32, R_ARM_TLS_LDM32},
2043 {BFD_RELOC_ARM_TLS_DTPMOD32, R_ARM_TLS_DTPMOD32},
2044 {BFD_RELOC_ARM_TLS_DTPOFF32, R_ARM_TLS_DTPOFF32},
07d6d2b8
AM		 2045 {BFD_RELOC_ARM_TLS_TPOFF32, R_ARM_TLS_TPOFF32},
2046 {BFD_RELOC_ARM_TLS_IE32, R_ARM_TLS_IE32},
2047 {BFD_RELOC_ARM_TLS_LE32, R_ARM_TLS_LE32},
2048 {BFD_RELOC_ARM_IRELATIVE, R_ARM_IRELATIVE},
188fd7ae
CL		 2049 {BFD_RELOC_ARM_GOTFUNCDESC, R_ARM_GOTFUNCDESC},
2050 {BFD_RELOC_ARM_GOTOFFFUNCDESC, R_ARM_GOTOFFFUNCDESC},
2051 {BFD_RELOC_ARM_FUNCDESC, R_ARM_FUNCDESC},
2052 {BFD_RELOC_ARM_FUNCDESC_VALUE, R_ARM_FUNCDESC_VALUE},
5c5a4843
CL		 2053 {BFD_RELOC_ARM_TLS_GD32_FDPIC, R_ARM_TLS_GD32_FDPIC},
2054 {BFD_RELOC_ARM_TLS_LDM32_FDPIC, R_ARM_TLS_LDM32_FDPIC},
2055 {BFD_RELOC_ARM_TLS_IE32_FDPIC, R_ARM_TLS_IE32_FDPIC},
c19d1205
ZW		 2056 {BFD_RELOC_VTABLE_INHERIT, R_ARM_GNU_VTINHERIT},
2057 {BFD_RELOC_VTABLE_ENTRY, R_ARM_GNU_VTENTRY},
b6895b4f
PB		 2058 {BFD_RELOC_ARM_MOVW, R_ARM_MOVW_ABS_NC},
2059 {BFD_RELOC_ARM_MOVT, R_ARM_MOVT_ABS},
2060 {BFD_RELOC_ARM_MOVW_PCREL, R_ARM_MOVW_PREL_NC},
2061 {BFD_RELOC_ARM_MOVT_PCREL, R_ARM_MOVT_PREL},
2062 {BFD_RELOC_ARM_THUMB_MOVW, R_ARM_THM_MOVW_ABS_NC},
2063 {BFD_RELOC_ARM_THUMB_MOVT, R_ARM_THM_MOVT_ABS},
2064 {BFD_RELOC_ARM_THUMB_MOVW_PCREL, R_ARM_THM_MOVW_PREL_NC},
2065 {BFD_RELOC_ARM_THUMB_MOVT_PCREL, R_ARM_THM_MOVT_PREL},
4962c51a
MS		 2066 {BFD_RELOC_ARM_ALU_PC_G0_NC, R_ARM_ALU_PC_G0_NC},
2067 {BFD_RELOC_ARM_ALU_PC_G0, R_ARM_ALU_PC_G0},
2068 {BFD_RELOC_ARM_ALU_PC_G1_NC, R_ARM_ALU_PC_G1_NC},
2069 {BFD_RELOC_ARM_ALU_PC_G1, R_ARM_ALU_PC_G1},
2070 {BFD_RELOC_ARM_ALU_PC_G2, R_ARM_ALU_PC_G2},
2071 {BFD_RELOC_ARM_LDR_PC_G0, R_ARM_LDR_PC_G0},
2072 {BFD_RELOC_ARM_LDR_PC_G1, R_ARM_LDR_PC_G1},
2073 {BFD_RELOC_ARM_LDR_PC_G2, R_ARM_LDR_PC_G2},
2074 {BFD_RELOC_ARM_LDRS_PC_G0, R_ARM_LDRS_PC_G0},
2075 {BFD_RELOC_ARM_LDRS_PC_G1, R_ARM_LDRS_PC_G1},
2076 {BFD_RELOC_ARM_LDRS_PC_G2, R_ARM_LDRS_PC_G2},
2077 {BFD_RELOC_ARM_LDC_PC_G0, R_ARM_LDC_PC_G0},
2078 {BFD_RELOC_ARM_LDC_PC_G1, R_ARM_LDC_PC_G1},
2079 {BFD_RELOC_ARM_LDC_PC_G2, R_ARM_LDC_PC_G2},
2080 {BFD_RELOC_ARM_ALU_SB_G0_NC, R_ARM_ALU_SB_G0_NC},
2081 {BFD_RELOC_ARM_ALU_SB_G0, R_ARM_ALU_SB_G0},
2082 {BFD_RELOC_ARM_ALU_SB_G1_NC, R_ARM_ALU_SB_G1_NC},
2083 {BFD_RELOC_ARM_ALU_SB_G1, R_ARM_ALU_SB_G1},
2084 {BFD_RELOC_ARM_ALU_SB_G2, R_ARM_ALU_SB_G2},
2085 {BFD_RELOC_ARM_LDR_SB_G0, R_ARM_LDR_SB_G0},
2086 {BFD_RELOC_ARM_LDR_SB_G1, R_ARM_LDR_SB_G1},
2087 {BFD_RELOC_ARM_LDR_SB_G2, R_ARM_LDR_SB_G2},
2088 {BFD_RELOC_ARM_LDRS_SB_G0, R_ARM_LDRS_SB_G0},
2089 {BFD_RELOC_ARM_LDRS_SB_G1, R_ARM_LDRS_SB_G1},
2090 {BFD_RELOC_ARM_LDRS_SB_G2, R_ARM_LDRS_SB_G2},
2091 {BFD_RELOC_ARM_LDC_SB_G0, R_ARM_LDC_SB_G0},
2092 {BFD_RELOC_ARM_LDC_SB_G1, R_ARM_LDC_SB_G1},
845b51d6 2093 {BFD_RELOC_ARM_LDC_SB_G2, R_ARM_LDC_SB_G2},
72d98d16
MG		 2094 {BFD_RELOC_ARM_V4BX, R_ARM_V4BX},
2095 {BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC, R_ARM_THM_ALU_ABS_G3_NC},
2096 {BFD_RELOC_ARM_THUMB_ALU_ABS_G2_NC, R_ARM_THM_ALU_ABS_G2_NC},
2097 {BFD_RELOC_ARM_THUMB_ALU_ABS_G1_NC, R_ARM_THM_ALU_ABS_G1_NC},
e5d6e09e 2098 {BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC, R_ARM_THM_ALU_ABS_G0_NC},
1caf72a5 2099 {BFD_RELOC_ARM_THUMB_BF17, R_ARM_THM_BF16},
1889da70 2100 {BFD_RELOC_ARM_THUMB_BF13, R_ARM_THM_BF12},
1caf72a5 2101 {BFD_RELOC_ARM_THUMB_BF19, R_ARM_THM_BF18}
7f266840
DJ		 2102 };
2103
2104static reloc_howto_type *
f1c71a59
ZW		 2105elf32_arm_reloc_type_lookup (bfd *abfd ATTRIBUTE_UNUSED,
2106 bfd_reloc_code_real_type code)
7f266840
DJ		 2107{
2108 unsigned int i;
8029a119 2109
906e58ca 2110 for (i = 0; i < ARRAY_SIZE (elf32_arm_reloc_map); i ++)
c19d1205
ZW		 2111 if (elf32_arm_reloc_map[i].bfd_reloc_val == code)
2112 return elf32_arm_howto_from_type (elf32_arm_reloc_map[i].elf_reloc_val);
7f266840 2113
c19d1205 2114 return NULL;
7f266840
DJ		 2115}
2116
157090f7
AM		 2117static reloc_howto_type *
2118elf32_arm_reloc_name_lookup (bfd *abfd ATTRIBUTE_UNUSED,
2119 const char *r_name)
2120{
2121 unsigned int i;
2122
906e58ca 2123 for (i = 0; i < ARRAY_SIZE (elf32_arm_howto_table_1); i++)
157090f7
AM		 2124 if (elf32_arm_howto_table_1[i].name != NULL
2125 && strcasecmp (elf32_arm_howto_table_1[i].name, r_name) == 0)
2126 return &elf32_arm_howto_table_1[i];
2127
906e58ca 2128 for (i = 0; i < ARRAY_SIZE (elf32_arm_howto_table_2); i++)
157090f7
AM		 2129 if (elf32_arm_howto_table_2[i].name != NULL
2130 && strcasecmp (elf32_arm_howto_table_2[i].name, r_name) == 0)
2131 return &elf32_arm_howto_table_2[i];
2132
34e77a92
RS		 2133 for (i = 0; i < ARRAY_SIZE (elf32_arm_howto_table_3); i++)
2134 if (elf32_arm_howto_table_3[i].name != NULL
2135 && strcasecmp (elf32_arm_howto_table_3[i].name, r_name) == 0)
2136 return &elf32_arm_howto_table_3[i];
2137
157090f7
AM		 2138 return NULL;
2139}
2140
906e58ca
NC		 2141/* Support for core dump NOTE sections. */
2142
7f266840 2143static bfd_boolean
f1c71a59 2144elf32_arm_nabi_grok_prstatus (bfd *abfd, Elf_Internal_Note *note)
7f266840
DJ		 2145{
2146 int offset;
2147 size_t size;
2148
2149 switch (note->descsz)
2150 {
2151 default:
2152 return FALSE;
2153
8029a119 2154 case 148: /* Linux/ARM 32-bit. */
7f266840 2155 /* pr_cursig */
228e534f 2156 elf_tdata (abfd)->core->signal = bfd_get_16 (abfd, note->descdata + 12);
7f266840
DJ		 2157
2158 /* pr_pid */
228e534f 2159 elf_tdata (abfd)->core->lwpid = bfd_get_32 (abfd, note->descdata + 24);
7f266840
DJ		 2160
2161 /* pr_reg */
2162 offset = 72;
2163 size = 72;
2164
2165 break;
2166 }
2167
2168 /* Make a ".reg/999" section. */
2169 return _bfd_elfcore_make_pseudosection (abfd, ".reg",
2170 size, note->descpos + offset);
2171}
2172
2173static bfd_boolean
f1c71a59 2174elf32_arm_nabi_grok_psinfo (bfd *abfd, Elf_Internal_Note *note)
7f266840
DJ		 2175{
2176 switch (note->descsz)
2177 {
2178 default:
2179 return FALSE;
2180
8029a119 2181 case 124: /* Linux/ARM elf_prpsinfo. */
228e534f 2182 elf_tdata (abfd)->core->pid
4395ee08 2183 = bfd_get_32 (abfd, note->descdata + 12);
228e534f 2184 elf_tdata (abfd)->core->program
7f266840 2185 = _bfd_elfcore_strndup (abfd, note->descdata + 28, 16);
228e534f 2186 elf_tdata (abfd)->core->command
7f266840
DJ		 2187 = _bfd_elfcore_strndup (abfd, note->descdata + 44, 80);
2188 }
2189
2190 /* Note that for some reason, a spurious space is tacked
2191 onto the end of the args in some (at least one anyway)
2192 implementations, so strip it off if it exists. */
7f266840 2193 {
228e534f 2194 char *command = elf_tdata (abfd)->core->command;
7f266840
DJ		 2195 int n = strlen (command);
2196
2197 if (0 < n && command[n - 1] == ' ')
2198 command[n - 1] = '\0';
2199 }
2200
2201 return TRUE;
2202}
2203
1f20dca5
UW		 2204static char *
2205elf32_arm_nabi_write_core_note (bfd *abfd, char *buf, int *bufsiz,
2206 int note_type, ...)
2207{
2208 switch (note_type)
2209 {
2210 default:
2211 return NULL;
2212
2213 case NT_PRPSINFO:
2214 {
602f1657 2215 char data[124] ATTRIBUTE_NONSTRING;
1f20dca5
UW		 2216 va_list ap;
2217
2218 va_start (ap, note_type);
2219 memset (data, 0, sizeof (data));
2220 strncpy (data + 28, va_arg (ap, const char *), 16);
be3e27bb 2221#if GCC_VERSION == 8000 || GCC_VERSION == 8001
95da9854 2222 DIAGNOSTIC_PUSH;
be3e27bb 2223 /* GCC 8.0 and 8.1 warn about 80 equals destination size with
95da9854
L		 2224 -Wstringop-truncation:
2225 https://gcc.gnu.org/bugzilla/show_bug.cgi?id=85643
2226 */
95da9854
L		 2227 DIAGNOSTIC_IGNORE_STRINGOP_TRUNCATION;
2228#endif
1f20dca5 2229 strncpy (data + 44, va_arg (ap, const char *), 80);
be3e27bb 2230#if GCC_VERSION == 8000 || GCC_VERSION == 8001
95da9854 2231 DIAGNOSTIC_POP;
fe75810f 2232#endif
1f20dca5
UW		 2233 va_end (ap);
2234
2235 return elfcore_write_note (abfd, buf, bufsiz,
2236 "CORE", note_type, data, sizeof (data));
2237 }
2238
2239 case NT_PRSTATUS:
2240 {
2241 char data[148];
2242 va_list ap;
2243 long pid;
2244 int cursig;
2245 const void *greg;
2246
2247 va_start (ap, note_type);
2248 memset (data, 0, sizeof (data));
2249 pid = va_arg (ap, long);
2250 bfd_put_32 (abfd, pid, data + 24);
2251 cursig = va_arg (ap, int);
2252 bfd_put_16 (abfd, cursig, data + 12);
2253 greg = va_arg (ap, const void *);
2254 memcpy (data + 72, greg, 72);
2255 va_end (ap);
2256
2257 return elfcore_write_note (abfd, buf, bufsiz,
2258 "CORE", note_type, data, sizeof (data));
2259 }
2260 }
2261}
2262
07d6d2b8
AM		 2263#define TARGET_LITTLE_SYM arm_elf32_le_vec
2264#define TARGET_LITTLE_NAME "elf32-littlearm"
2265#define TARGET_BIG_SYM arm_elf32_be_vec
2266#define TARGET_BIG_NAME "elf32-bigarm"
7f266840
DJ		 2267
2268#define elf_backend_grok_prstatus elf32_arm_nabi_grok_prstatus
2269#define elf_backend_grok_psinfo elf32_arm_nabi_grok_psinfo
1f20dca5 2270#define elf_backend_write_core_note elf32_arm_nabi_write_core_note
7f266840 2271
252b5132
RH		 2272typedef unsigned long int insn32;
2273typedef unsigned short int insn16;
2274
3a4a14e9
PB		 2275/* In lieu of proper flags, assume all EABIv4 or later objects are
2276 interworkable. */
57e8b36a 2277#define INTERWORK_FLAG(abfd) \
3a4a14e9 2278 (EF_ARM_EABI_VERSION (elf_elfheader (abfd)->e_flags) >= EF_ARM_EABI_VER4 \
3e6b1042
DJ		 2279 || (elf_elfheader (abfd)->e_flags & EF_ARM_INTERWORK) \
2280 || ((abfd)->flags & BFD_LINKER_CREATED))
9b485d32 2281
252b5132
RH		 2282/* The linker script knows the section names for placement.
2283 The entry_names are used to do simple name mangling on the stubs.
2284 Given a function name, and its type, the stub can be found. The
9b485d32 2285 name can be changed. The only requirement is the %s be present. */
252b5132
RH		 2286#define THUMB2ARM_GLUE_SECTION_NAME ".glue_7t"
2287#define THUMB2ARM_GLUE_ENTRY_NAME "__%s_from_thumb"
2288
2289#define ARM2THUMB_GLUE_SECTION_NAME ".glue_7"
2290#define ARM2THUMB_GLUE_ENTRY_NAME "__%s_from_arm"
2291
c7b8f16e
JB		 2292#define VFP11_ERRATUM_VENEER_SECTION_NAME ".vfp11_veneer"
2293#define VFP11_ERRATUM_VENEER_ENTRY_NAME "__vfp11_veneer_%x"
2294
a504d23a
LA		 2295#define STM32L4XX_ERRATUM_VENEER_SECTION_NAME ".text.stm32l4xx_veneer"
2296#define STM32L4XX_ERRATUM_VENEER_ENTRY_NAME "__stm32l4xx_veneer_%x"
2297
845b51d6
PB		 2298#define ARM_BX_GLUE_SECTION_NAME ".v4_bx"
2299#define ARM_BX_GLUE_ENTRY_NAME "__bx_r%d"
2300
7413f23f
DJ		 2301#define STUB_ENTRY_NAME "__%s_veneer"
2302
4ba2ef8f
TP		 2303#define CMSE_PREFIX "__acle_se_"
2304
4d83e8d9
CL		 2305#define CMSE_STUB_NAME ".gnu.sgstubs"
2306
252b5132
RH		 2307/* The name of the dynamic interpreter. This is put in the .interp
2308 section. */
2309#define ELF_DYNAMIC_INTERPRETER "/usr/lib/ld.so.1"
2310
cb10292c
CL		 2311/* FDPIC default stack size. */
2312#define DEFAULT_STACK_SIZE 0x8000
2313
0855e32b 2314static const unsigned long tls_trampoline [] =
b38cadfb
NC		 2315{
2316 0xe08e0000, /* add r0, lr, r0 */
2317 0xe5901004, /* ldr r1, [r0,#4] */
2318 0xe12fff11, /* bx r1 */
2319};
0855e32b
NS		 2320
2321static const unsigned long dl_tlsdesc_lazy_trampoline [] =
b38cadfb
NC		 2322{
2323 0xe52d2004, /* push {r2} */
2324 0xe59f200c, /* ldr r2, [pc, #3f - . - 8] */
2325 0xe59f100c, /* ldr r1, [pc, #4f - . - 8] */
2326 0xe79f2002, /* 1: ldr r2, [pc, r2] */
2327 0xe081100f, /* 2: add r1, pc */
2328 0xe12fff12, /* bx r2 */
2329 0x00000014, /* 3: .word _GLOBAL_OFFSET_TABLE_ - 1b - 8
99059e56 2330 + dl_tlsdesc_lazy_resolver(GOT) */
b38cadfb
NC		 2331 0x00000018, /* 4: .word _GLOBAL_OFFSET_TABLE_ - 2b - 8 */
2332};
0855e32b 2333
b4e87f2c
TC		 2334/* NOTE: [Thumb nop sequence]
2335 When adding code that transitions from Thumb to Arm the instruction that
2336 should be used for the alignment padding should be 0xe7fd (b .-2) instead of
2337 a nop for performance reasons. */
2338
7801f98f
CL		 2339/* ARM FDPIC PLT entry. */
2340/* The last 5 words contain PLT lazy fragment code and data. */
2341static const bfd_vma elf32_arm_fdpic_plt_entry [] =
2342 {
2343 0xe59fc008, /* ldr r12, .L1 */
2344 0xe08cc009, /* add r12, r12, r9 */
2345 0xe59c9004, /* ldr r9, [r12, #4] */
2346 0xe59cf000, /* ldr pc, [r12] */
2347 0x00000000, /* L1. .word foo(GOTOFFFUNCDESC) */
2348 0x00000000, /* L1. .word foo(funcdesc_value_reloc_offset) */
2349 0xe51fc00c, /* ldr r12, [pc, #-12] */
2350 0xe92d1000, /* push {r12} */
2351 0xe599c004, /* ldr r12, [r9, #4] */
2352 0xe599f000, /* ldr pc, [r9] */
2353 };
2354
59029f57
CL		 2355/* Thumb FDPIC PLT entry. */
2356/* The last 5 words contain PLT lazy fragment code and data. */
2357static const bfd_vma elf32_arm_fdpic_thumb_plt_entry [] =
2358 {
2359 0xc00cf8df, /* ldr.w r12, .L1 */
2360 0x0c09eb0c, /* add.w r12, r12, r9 */
2361 0x9004f8dc, /* ldr.w r9, [r12, #4] */
2362 0xf000f8dc, /* ldr.w pc, [r12] */
2363 0x00000000, /* .L1 .word foo(GOTOFFFUNCDESC) */
2364 0x00000000, /* .L2 .word foo(funcdesc_value_reloc_offset) */
2365 0xc008f85f, /* ldr.w r12, .L2 */
2366 0xcd04f84d, /* push {r12} */
2367 0xc004f8d9, /* ldr.w r12, [r9, #4] */
2368 0xf000f8d9, /* ldr.w pc, [r9] */
2369 };
2370
5e681ec4
PB		 2371#ifdef FOUR_WORD_PLT
2372
252b5132
RH		 2373/* The first entry in a procedure linkage table looks like
2374 this. It is set up so that any shared library function that is
59f2c4e7 2375 called before the relocation has been set up calls the dynamic
9b485d32 2376 linker first. */
e5a52504 2377static const bfd_vma elf32_arm_plt0_entry [] =
b38cadfb
NC		 2378{
2379 0xe52de004, /* str lr, [sp, #-4]! */
2380 0xe59fe010, /* ldr lr, [pc, #16] */
2381 0xe08fe00e, /* add lr, pc, lr */
2382 0xe5bef008, /* ldr pc, [lr, #8]! */
2383};
5e681ec4
PB		 2384
2385/* Subsequent entries in a procedure linkage table look like
2386 this. */
e5a52504 2387static const bfd_vma elf32_arm_plt_entry [] =
b38cadfb
NC		 2388{
2389 0xe28fc600, /* add ip, pc, #NN */
2390 0xe28cca00, /* add ip, ip, #NN */
2391 0xe5bcf000, /* ldr pc, [ip, #NN]! */
2392 0x00000000, /* unused */
2393};
5e681ec4 2394
eed94f8f 2395#else /* not FOUR_WORD_PLT */
5e681ec4 2396
5e681ec4
PB		 2397/* The first entry in a procedure linkage table looks like
2398 this. It is set up so that any shared library function that is
2399 called before the relocation has been set up calls the dynamic
2400 linker first. */
e5a52504 2401static const bfd_vma elf32_arm_plt0_entry [] =
b38cadfb 2402{
07d6d2b8
AM		 2403 0xe52de004, /* str lr, [sp, #-4]! */
2404 0xe59fe004, /* ldr lr, [pc, #4] */
2405 0xe08fe00e, /* add lr, pc, lr */
2406 0xe5bef008, /* ldr pc, [lr, #8]! */
2407 0x00000000, /* &GOT[0] - . */
b38cadfb 2408};
252b5132 2409
1db37fe6
YG		 2410/* By default subsequent entries in a procedure linkage table look like
2411 this. Offsets that don't fit into 28 bits will cause link error. */
2412static const bfd_vma elf32_arm_plt_entry_short [] =
b38cadfb
NC		 2413{
2414 0xe28fc600, /* add ip, pc, #0xNN00000 */
2415 0xe28cca00, /* add ip, ip, #0xNN000 */
2416 0xe5bcf000, /* ldr pc, [ip, #0xNNN]! */
2417};
5e681ec4 2418
1db37fe6
YG		 2419/* When explicitly asked, we'll use this "long" entry format
2420 which can cope with arbitrary displacements. */
2421static const bfd_vma elf32_arm_plt_entry_long [] =
2422{
07d6d2b8
AM		 2423 0xe28fc200, /* add ip, pc, #0xN0000000 */
2424 0xe28cc600, /* add ip, ip, #0xNN00000 */
1db37fe6
YG		 2425 0xe28cca00, /* add ip, ip, #0xNN000 */
2426 0xe5bcf000, /* ldr pc, [ip, #0xNNN]! */
2427};
2428
2429static bfd_boolean elf32_arm_use_long_plt_entry = FALSE;
2430
eed94f8f
NC		 2431#endif /* not FOUR_WORD_PLT */
2432
2433/* The first entry in a procedure linkage table looks like this.
2434 It is set up so that any shared library function that is called before the
2435 relocation has been set up calls the dynamic linker first. */
2436static const bfd_vma elf32_thumb2_plt0_entry [] =
2437{
2438 /* NOTE: As this is a mixture of 16-bit and 32-bit instructions,
2439 an instruction maybe encoded to one or two array elements. */
07d6d2b8
AM		 2440 0xf8dfb500, /* push {lr} */
2441 0x44fee008, /* ldr.w lr, [pc, #8] */
2442 /* add lr, pc */
eed94f8f 2443 0xff08f85e, /* ldr.w pc, [lr, #8]! */
07d6d2b8 2444 0x00000000, /* &GOT[0] - . */
eed94f8f
NC		 2445};
2446
2447/* Subsequent entries in a procedure linkage table for thumb only target
2448 look like this. */
2449static const bfd_vma elf32_thumb2_plt_entry [] =
2450{
2451 /* NOTE: As this is a mixture of 16-bit and 32-bit instructions,
2452 an instruction maybe encoded to one or two array elements. */
07d6d2b8
AM		 2453 0x0c00f240, /* movw ip, #0xNNNN */
2454 0x0c00f2c0, /* movt ip, #0xNNNN */
2455 0xf8dc44fc, /* add ip, pc */
15ccbdd7
TC		 2456 0xe7fcf000 /* ldr.w pc, [ip] */
2457 /* b .-4 */
eed94f8f 2458};
252b5132 2459
00a97672
RS		 2460/* The format of the first entry in the procedure linkage table
2461 for a VxWorks executable. */
2462static const bfd_vma elf32_arm_vxworks_exec_plt0_entry[] =
b38cadfb 2463{
07d6d2b8
AM		 2464 0xe52dc008, /* str ip,[sp,#-8]! */
2465 0xe59fc000, /* ldr ip,[pc] */
2466 0xe59cf008, /* ldr pc,[ip,#8] */
2467 0x00000000, /* .long _GLOBAL_OFFSET_TABLE_ */
b38cadfb 2468};
00a97672
RS		 2469
2470/* The format of subsequent entries in a VxWorks executable. */
2471static const bfd_vma elf32_arm_vxworks_exec_plt_entry[] =
b38cadfb 2472{
07d6d2b8
AM		 2473 0xe59fc000, /* ldr ip,[pc] */
2474 0xe59cf000, /* ldr pc,[ip] */
2475 0x00000000, /* .long @got */
2476 0xe59fc000, /* ldr ip,[pc] */
2477 0xea000000, /* b _PLT */
2478 0x00000000, /* .long @pltindex*sizeof(Elf32_Rela) */
b38cadfb 2479};
00a97672
RS		 2480
2481/* The format of entries in a VxWorks shared library. */
2482static const bfd_vma elf32_arm_vxworks_shared_plt_entry[] =
b38cadfb 2483{
07d6d2b8
AM		 2484 0xe59fc000, /* ldr ip,[pc] */
2485 0xe79cf009, /* ldr pc,[ip,r9] */
2486 0x00000000, /* .long @got */
2487 0xe59fc000, /* ldr ip,[pc] */
2488 0xe599f008, /* ldr pc,[r9,#8] */
2489 0x00000000, /* .long @pltindex*sizeof(Elf32_Rela) */
b38cadfb 2490};
00a97672 2491
b7693d02
DJ		 2492/* An initial stub used if the PLT entry is referenced from Thumb code. */
2493#define PLT_THUMB_STUB_SIZE 4
2494static const bfd_vma elf32_arm_plt_thumb_stub [] =
b38cadfb
NC		 2495{
2496 0x4778, /* bx pc */
b4e87f2c 2497 0xe7fd /* b .-2 */
b38cadfb 2498};
b7693d02 2499
e5a52504
MM		 2500/* The entries in a PLT when using a DLL-based target with multiple
2501 address spaces. */
906e58ca 2502static const bfd_vma elf32_arm_symbian_plt_entry [] =
b38cadfb 2503{
07d6d2b8
AM		 2504 0xe51ff004, /* ldr pc, [pc, #-4] */
2505 0x00000000, /* dcd R_ARM_GLOB_DAT(X) */
b38cadfb
NC		 2506};
2507
2508/* The first entry in a procedure linkage table looks like
2509 this. It is set up so that any shared library function that is
2510 called before the relocation has been set up calls the dynamic
2511 linker first. */
2512static const bfd_vma elf32_arm_nacl_plt0_entry [] =
2513{
2514 /* First bundle: */
2515 0xe300c000, /* movw ip, #:lower16:&GOT[2]-.+8 */
2516 0xe340c000, /* movt ip, #:upper16:&GOT[2]-.+8 */
2517 0xe08cc00f, /* add ip, ip, pc */
2518 0xe52dc008, /* str ip, [sp, #-8]! */
2519 /* Second bundle: */
edccdf7c
RM		 2520 0xe3ccc103, /* bic ip, ip, #0xc0000000 */
2521 0xe59cc000, /* ldr ip, [ip] */
b38cadfb 2522 0xe3ccc13f, /* bic ip, ip, #0xc000000f */
edccdf7c 2523 0xe12fff1c, /* bx ip */
b38cadfb 2524 /* Third bundle: */
edccdf7c
RM		 2525 0xe320f000, /* nop */
2526 0xe320f000, /* nop */
2527 0xe320f000, /* nop */
b38cadfb
NC		 2528 /* .Lplt_tail: */
2529 0xe50dc004, /* str ip, [sp, #-4] */
2530 /* Fourth bundle: */
edccdf7c
RM		 2531 0xe3ccc103, /* bic ip, ip, #0xc0000000 */
2532 0xe59cc000, /* ldr ip, [ip] */
b38cadfb 2533 0xe3ccc13f, /* bic ip, ip, #0xc000000f */
edccdf7c 2534 0xe12fff1c, /* bx ip */
b38cadfb
NC		 2535};
2536#define ARM_NACL_PLT_TAIL_OFFSET (11 * 4)
2537
2538/* Subsequent entries in a procedure linkage table look like this. */
2539static const bfd_vma elf32_arm_nacl_plt_entry [] =
2540{
2541 0xe300c000, /* movw ip, #:lower16:&GOT[n]-.+8 */
2542 0xe340c000, /* movt ip, #:upper16:&GOT[n]-.+8 */
2543 0xe08cc00f, /* add ip, ip, pc */
2544 0xea000000, /* b .Lplt_tail */
2545};
e5a52504 2546
906e58ca
NC		 2547#define ARM_MAX_FWD_BRANCH_OFFSET ((((1 << 23) - 1) << 2) + 8)
2548#define ARM_MAX_BWD_BRANCH_OFFSET ((-((1 << 23) << 2)) + 8)
2549#define THM_MAX_FWD_BRANCH_OFFSET ((1 << 22) -2 + 4)
2550#define THM_MAX_BWD_BRANCH_OFFSET (-(1 << 22) + 4)
2551#define THM2_MAX_FWD_BRANCH_OFFSET (((1 << 24) - 2) + 4)
2552#define THM2_MAX_BWD_BRANCH_OFFSET (-(1 << 24) + 4)
c5423981
TG		 2553#define THM2_MAX_FWD_COND_BRANCH_OFFSET (((1 << 20) -2) + 4)
2554#define THM2_MAX_BWD_COND_BRANCH_OFFSET (-(1 << 20) + 4)
906e58ca 2555
461a49ca 2556enum stub_insn_type
b38cadfb
NC		 2557{
2558 THUMB16_TYPE = 1,
2559 THUMB32_TYPE,
2560 ARM_TYPE,
2561 DATA_TYPE
2562};
461a49ca 2563
48229727
JB		 2564#define THUMB16_INSN(X) {(X), THUMB16_TYPE, R_ARM_NONE, 0}
2565/* A bit of a hack. A Thumb conditional branch, in which the proper condition
2566 is inserted in arm_build_one_stub(). */
2567#define THUMB16_BCOND_INSN(X) {(X), THUMB16_TYPE, R_ARM_NONE, 1}
2568#define THUMB32_INSN(X) {(X), THUMB32_TYPE, R_ARM_NONE, 0}
d5a67c02
AV		 2569#define THUMB32_MOVT(X) {(X), THUMB32_TYPE, R_ARM_THM_MOVT_ABS, 0}
2570#define THUMB32_MOVW(X) {(X), THUMB32_TYPE, R_ARM_THM_MOVW_ABS_NC, 0}
48229727
JB		 2571#define THUMB32_B_INSN(X, Z) {(X), THUMB32_TYPE, R_ARM_THM_JUMP24, (Z)}
2572#define ARM_INSN(X) {(X), ARM_TYPE, R_ARM_NONE, 0}
2573#define ARM_REL_INSN(X, Z) {(X), ARM_TYPE, R_ARM_JUMP24, (Z)}
2574#define DATA_WORD(X,Y,Z) {(X), DATA_TYPE, (Y), (Z)}
461a49ca
DJ		 2575
2576typedef struct
2577{
07d6d2b8 2578 bfd_vma data;
b38cadfb 2579 enum stub_insn_type type;
07d6d2b8
AM		 2580 unsigned int r_type;
2581 int reloc_addend;
461a49ca
DJ		 2582} insn_sequence;
2583
b4e87f2c
TC		 2584/* See note [Thumb nop sequence] when adding a veneer. */
2585
fea2b4d6
CL		 2586/* Arm/Thumb -> Arm/Thumb long branch stub. On V5T and above, use blx
2587 to reach the stub if necessary. */
461a49ca 2588static const insn_sequence elf32_arm_stub_long_branch_any_any[] =
b38cadfb 2589{
07d6d2b8 2590 ARM_INSN (0xe51ff004), /* ldr pc, [pc, #-4] */
b38cadfb
NC		 2591 DATA_WORD (0, R_ARM_ABS32, 0), /* dcd R_ARM_ABS32(X) */
2592};
906e58ca 2593
fea2b4d6
CL		 2594/* V4T Arm -> Thumb long branch stub. Used on V4T where blx is not
2595 available. */
461a49ca 2596static const insn_sequence elf32_arm_stub_long_branch_v4t_arm_thumb[] =
b38cadfb 2597{
07d6d2b8
AM		 2598 ARM_INSN (0xe59fc000), /* ldr ip, [pc, #0] */
2599 ARM_INSN (0xe12fff1c), /* bx ip */
b38cadfb
NC		 2600 DATA_WORD (0, R_ARM_ABS32, 0), /* dcd R_ARM_ABS32(X) */
2601};
906e58ca 2602
d3626fb0 2603/* Thumb -> Thumb long branch stub. Used on M-profile architectures. */
461a49ca 2604static const insn_sequence elf32_arm_stub_long_branch_thumb_only[] =
b38cadfb 2605{
07d6d2b8
AM		 2606 THUMB16_INSN (0xb401), /* push {r0} */
2607 THUMB16_INSN (0x4802), /* ldr r0, [pc, #8] */
2608 THUMB16_INSN (0x4684), /* mov ip, r0 */
2609 THUMB16_INSN (0xbc01), /* pop {r0} */
2610 THUMB16_INSN (0x4760), /* bx ip */
2611 THUMB16_INSN (0xbf00), /* nop */
b38cadfb
NC		 2612 DATA_WORD (0, R_ARM_ABS32, 0), /* dcd R_ARM_ABS32(X) */
2613};
906e58ca 2614
80c135e5
TP		 2615/* Thumb -> Thumb long branch stub in thumb2 encoding. Used on armv7. */
2616static const insn_sequence elf32_arm_stub_long_branch_thumb2_only[] =
2617{
07d6d2b8 2618 THUMB32_INSN (0xf85ff000), /* ldr.w pc, [pc, #-0] */
80c135e5
TP		 2619 DATA_WORD (0, R_ARM_ABS32, 0), /* dcd R_ARM_ABS32(x) */
2620};
2621
d5a67c02
AV		 2622/* Thumb -> Thumb long branch stub. Used for PureCode sections on Thumb2
2623 M-profile architectures. */
2624static const insn_sequence elf32_arm_stub_long_branch_thumb2_only_pure[] =
2625{
2626 THUMB32_MOVW (0xf2400c00), /* mov.w ip, R_ARM_MOVW_ABS_NC */
2627 THUMB32_MOVT (0xf2c00c00), /* movt ip, R_ARM_MOVT_ABS << 16 */
07d6d2b8 2628 THUMB16_INSN (0x4760), /* bx ip */
d5a67c02
AV		 2629};
2630
d3626fb0
CL		 2631/* V4T Thumb -> Thumb long branch stub. Using the stack is not
2632 allowed. */
2633static const insn_sequence elf32_arm_stub_long_branch_v4t_thumb_thumb[] =
b38cadfb 2634{
07d6d2b8 2635 THUMB16_INSN (0x4778), /* bx pc */
b4e87f2c 2636 THUMB16_INSN (0xe7fd), /* b .-2 */
07d6d2b8
AM		 2637 ARM_INSN (0xe59fc000), /* ldr ip, [pc, #0] */
2638 ARM_INSN (0xe12fff1c), /* bx ip */
b38cadfb
NC		 2639 DATA_WORD (0, R_ARM_ABS32, 0), /* dcd R_ARM_ABS32(X) */
2640};
d3626fb0 2641
fea2b4d6
CL		 2642/* V4T Thumb -> ARM long branch stub. Used on V4T where blx is not
2643 available. */
461a49ca 2644static const insn_sequence elf32_arm_stub_long_branch_v4t_thumb_arm[] =
b38cadfb 2645{
07d6d2b8 2646 THUMB16_INSN (0x4778), /* bx pc */
b4e87f2c 2647 THUMB16_INSN (0xe7fd), /* b .-2 */
07d6d2b8 2648 ARM_INSN (0xe51ff004), /* ldr pc, [pc, #-4] */
b38cadfb
NC		 2649 DATA_WORD (0, R_ARM_ABS32, 0), /* dcd R_ARM_ABS32(X) */
2650};
906e58ca 2651
fea2b4d6
CL		 2652/* V4T Thumb -> ARM short branch stub. Shorter variant of the above
2653 one, when the destination is close enough. */
461a49ca 2654static const insn_sequence elf32_arm_stub_short_branch_v4t_thumb_arm[] =
b38cadfb 2655{
07d6d2b8 2656 THUMB16_INSN (0x4778), /* bx pc */
b4e87f2c 2657 THUMB16_INSN (0xe7fd), /* b .-2 */
b38cadfb
NC		 2658 ARM_REL_INSN (0xea000000, -8), /* b (X-8) */
2659};
c820be07 2660
cf3eccff 2661/* ARM/Thumb -> ARM long branch stub, PIC. On V5T and above, use
fea2b4d6 2662 blx to reach the stub if necessary. */
cf3eccff 2663static const insn_sequence elf32_arm_stub_long_branch_any_arm_pic[] =
b38cadfb 2664{
07d6d2b8
AM		 2665 ARM_INSN (0xe59fc000), /* ldr ip, [pc] */
2666 ARM_INSN (0xe08ff00c), /* add pc, pc, ip */
b38cadfb
NC		 2667 DATA_WORD (0, R_ARM_REL32, -4), /* dcd R_ARM_REL32(X-4) */
2668};
906e58ca 2669
cf3eccff
DJ		 2670/* ARM/Thumb -> Thumb long branch stub, PIC. On V5T and above, use
2671 blx to reach the stub if necessary. We can not add into pc;
2672 it is not guaranteed to mode switch (different in ARMv6 and
2673 ARMv7). */
2674static const insn_sequence elf32_arm_stub_long_branch_any_thumb_pic[] =
b38cadfb 2675{
07d6d2b8
AM		 2676 ARM_INSN (0xe59fc004), /* ldr ip, [pc, #4] */
2677 ARM_INSN (0xe08fc00c), /* add ip, pc, ip */
2678 ARM_INSN (0xe12fff1c), /* bx ip */
b38cadfb
NC		 2679 DATA_WORD (0, R_ARM_REL32, 0), /* dcd R_ARM_REL32(X) */
2680};
cf3eccff 2681
ebe24dd4
CL		 2682/* V4T ARM -> ARM long branch stub, PIC. */
2683static const insn_sequence elf32_arm_stub_long_branch_v4t_arm_thumb_pic[] =
b38cadfb 2684{
07d6d2b8
AM		 2685 ARM_INSN (0xe59fc004), /* ldr ip, [pc, #4] */
2686 ARM_INSN (0xe08fc00c), /* add ip, pc, ip */
2687 ARM_INSN (0xe12fff1c), /* bx ip */
b38cadfb
NC		 2688 DATA_WORD (0, R_ARM_REL32, 0), /* dcd R_ARM_REL32(X) */
2689};
ebe24dd4
CL		 2690
2691/* V4T Thumb -> ARM long branch stub, PIC. */
2692static const insn_sequence elf32_arm_stub_long_branch_v4t_thumb_arm_pic[] =
b38cadfb 2693{
07d6d2b8 2694 THUMB16_INSN (0x4778), /* bx pc */
b4e87f2c 2695 THUMB16_INSN (0xe7fd), /* b .-2 */
07d6d2b8
AM		 2696 ARM_INSN (0xe59fc000), /* ldr ip, [pc, #0] */
2697 ARM_INSN (0xe08cf00f), /* add pc, ip, pc */
b38cadfb
NC		 2698 DATA_WORD (0, R_ARM_REL32, -4), /* dcd R_ARM_REL32(X) */
2699};
ebe24dd4 2700
d3626fb0
CL		 2701/* Thumb -> Thumb long branch stub, PIC. Used on M-profile
2702 architectures. */
ebe24dd4 2703static const insn_sequence elf32_arm_stub_long_branch_thumb_only_pic[] =
b38cadfb 2704{
07d6d2b8
AM		 2705 THUMB16_INSN (0xb401), /* push {r0} */
2706 THUMB16_INSN (0x4802), /* ldr r0, [pc, #8] */
2707 THUMB16_INSN (0x46fc), /* mov ip, pc */
2708 THUMB16_INSN (0x4484), /* add ip, r0 */
2709 THUMB16_INSN (0xbc01), /* pop {r0} */
2710 THUMB16_INSN (0x4760), /* bx ip */
b38cadfb
NC		 2711 DATA_WORD (0, R_ARM_REL32, 4), /* dcd R_ARM_REL32(X) */
2712};
ebe24dd4 2713
d3626fb0
CL		 2714/* V4T Thumb -> Thumb long branch stub, PIC. Using the stack is not
2715 allowed. */
2716static const insn_sequence elf32_arm_stub_long_branch_v4t_thumb_thumb_pic[] =
b38cadfb 2717{
07d6d2b8 2718 THUMB16_INSN (0x4778), /* bx pc */
b4e87f2c 2719 THUMB16_INSN (0xe7fd), /* b .-2 */
07d6d2b8
AM		 2720 ARM_INSN (0xe59fc004), /* ldr ip, [pc, #4] */
2721 ARM_INSN (0xe08fc00c), /* add ip, pc, ip */
2722 ARM_INSN (0xe12fff1c), /* bx ip */
b38cadfb
NC		 2723 DATA_WORD (0, R_ARM_REL32, 0), /* dcd R_ARM_REL32(X) */
2724};
d3626fb0 2725
0855e32b
NS		 2726/* Thumb2/ARM -> TLS trampoline. Lowest common denominator, which is a
2727 long PIC stub. We can use r1 as a scratch -- and cannot use ip. */
2728static const insn_sequence elf32_arm_stub_long_branch_any_tls_pic[] =
2729{
07d6d2b8
AM		 2730 ARM_INSN (0xe59f1000), /* ldr r1, [pc] */
2731 ARM_INSN (0xe08ff001), /* add pc, pc, r1 */
b38cadfb 2732 DATA_WORD (0, R_ARM_REL32, -4), /* dcd R_ARM_REL32(X-4) */
0855e32b
NS		 2733};
2734
2735/* V4T Thumb -> TLS trampoline. lowest common denominator, which is a
2736 long PIC stub. We can use r1 as a scratch -- and cannot use ip. */
2737static const insn_sequence elf32_arm_stub_long_branch_v4t_thumb_tls_pic[] =
2738{
07d6d2b8 2739 THUMB16_INSN (0x4778), /* bx pc */
b4e87f2c 2740 THUMB16_INSN (0xe7fd), /* b .-2 */
07d6d2b8
AM		 2741 ARM_INSN (0xe59f1000), /* ldr r1, [pc, #0] */
2742 ARM_INSN (0xe081f00f), /* add pc, r1, pc */
b38cadfb 2743 DATA_WORD (0, R_ARM_REL32, -4), /* dcd R_ARM_REL32(X) */
0855e32b
NS		 2744};
2745
7a89b94e
NC		 2746/* NaCl ARM -> ARM long branch stub. */
2747static const insn_sequence elf32_arm_stub_long_branch_arm_nacl[] =
2748{
2749 ARM_INSN (0xe59fc00c), /* ldr ip, [pc, #12] */
2750 ARM_INSN (0xe3ccc13f), /* bic ip, ip, #0xc000000f */
07d6d2b8
AM		 2751 ARM_INSN (0xe12fff1c), /* bx ip */
2752 ARM_INSN (0xe320f000), /* nop */
2753 ARM_INSN (0xe125be70), /* bkpt 0x5be0 */
2754 DATA_WORD (0, R_ARM_ABS32, 0), /* dcd R_ARM_ABS32(X) */
2755 DATA_WORD (0, R_ARM_NONE, 0), /* .word 0 */
2756 DATA_WORD (0, R_ARM_NONE, 0), /* .word 0 */
7a89b94e
NC		 2757};
2758
2759/* NaCl ARM -> ARM long branch stub, PIC. */
2760static const insn_sequence elf32_arm_stub_long_branch_arm_nacl_pic[] =
2761{
2762 ARM_INSN (0xe59fc00c), /* ldr ip, [pc, #12] */
07d6d2b8 2763 ARM_INSN (0xe08cc00f), /* add ip, ip, pc */
7a89b94e 2764 ARM_INSN (0xe3ccc13f), /* bic ip, ip, #0xc000000f */
07d6d2b8
AM		 2765 ARM_INSN (0xe12fff1c), /* bx ip */
2766 ARM_INSN (0xe125be70), /* bkpt 0x5be0 */
2767 DATA_WORD (0, R_ARM_REL32, 8), /* dcd R_ARM_REL32(X+8) */
2768 DATA_WORD (0, R_ARM_NONE, 0), /* .word 0 */
2769 DATA_WORD (0, R_ARM_NONE, 0), /* .word 0 */
7a89b94e
NC		 2770};
2771
4ba2ef8f
TP		 2772/* Stub used for transition to secure state (aka SG veneer). */
2773static const insn_sequence elf32_arm_stub_cmse_branch_thumb_only[] =
2774{
2775 THUMB32_INSN (0xe97fe97f), /* sg. */
2776 THUMB32_B_INSN (0xf000b800, -4), /* b.w original_branch_dest. */
2777};
2778
7a89b94e 2779
48229727
JB		 2780/* Cortex-A8 erratum-workaround stubs. */
2781
2782/* Stub used for conditional branches (which may be beyond +/-1MB away, so we
2783 can't use a conditional branch to reach this stub). */
2784
2785static const insn_sequence elf32_arm_stub_a8_veneer_b_cond[] =
b38cadfb 2786{
07d6d2b8 2787 THUMB16_BCOND_INSN (0xd001), /* b<cond>.n true. */
b38cadfb
NC		 2788 THUMB32_B_INSN (0xf000b800, -4), /* b.w insn_after_original_branch. */
2789 THUMB32_B_INSN (0xf000b800, -4) /* true: b.w original_branch_dest. */
2790};
48229727
JB		 2791
2792/* Stub used for b.w and bl.w instructions. */
2793
2794static const insn_sequence elf32_arm_stub_a8_veneer_b[] =
b38cadfb
NC		 2795{
2796 THUMB32_B_INSN (0xf000b800, -4) /* b.w original_branch_dest. */
2797};
48229727
JB		 2798
2799static const insn_sequence elf32_arm_stub_a8_veneer_bl[] =
b38cadfb
NC		 2800{
2801 THUMB32_B_INSN (0xf000b800, -4) /* b.w original_branch_dest. */
2802};
48229727
JB		 2803
2804/* Stub used for Thumb-2 blx.w instructions. We modified the original blx.w
2805 instruction (which switches to ARM mode) to point to this stub. Jump to the
2806 real destination using an ARM-mode branch. */
2807
2808static const insn_sequence elf32_arm_stub_a8_veneer_blx[] =
b38cadfb
NC		 2809{
2810 ARM_REL_INSN (0xea000000, -8) /* b original_branch_dest. */
2811};
48229727 2812
9553db3c
NC		 2813/* For each section group there can be a specially created linker section
2814 to hold the stubs for that group. The name of the stub section is based
2815 upon the name of another section within that group with the suffix below
2816 applied.
2817
2818 PR 13049: STUB_SUFFIX used to be ".stub", but this allowed the user to
2819 create what appeared to be a linker stub section when it actually
2820 contained user code/data. For example, consider this fragment:
b38cadfb 2821
9553db3c
NC		 2822 const char * stubborn_problems[] = { "np" };
2823
2824 If this is compiled with "-fPIC -fdata-sections" then gcc produces a
2825 section called:
2826
2827 .data.rel.local.stubborn_problems
2828
2829 This then causes problems in arm32_arm_build_stubs() as it triggers:
2830
2831 // Ignore non-stub sections.
2832 if (!strstr (stub_sec->name, STUB_SUFFIX))
2833 continue;
2834
2835 And so the section would be ignored instead of being processed. Hence
2836 the change in definition of STUB_SUFFIX to a name that cannot be a valid
2837 C identifier. */
2838#define STUB_SUFFIX ".__stub"
906e58ca 2839
738a79f6
CL		 2840/* One entry per long/short branch stub defined above. */
2841#define DEF_STUBS \
2842 DEF_STUB(long_branch_any_any) \
2843 DEF_STUB(long_branch_v4t_arm_thumb) \
2844 DEF_STUB(long_branch_thumb_only) \
2845 DEF_STUB(long_branch_v4t_thumb_thumb) \
2846 DEF_STUB(long_branch_v4t_thumb_arm) \
2847 DEF_STUB(short_branch_v4t_thumb_arm) \
2848 DEF_STUB(long_branch_any_arm_pic) \
2849 DEF_STUB(long_branch_any_thumb_pic) \
2850 DEF_STUB(long_branch_v4t_thumb_thumb_pic) \
2851 DEF_STUB(long_branch_v4t_arm_thumb_pic) \
2852 DEF_STUB(long_branch_v4t_thumb_arm_pic) \
48229727 2853 DEF_STUB(long_branch_thumb_only_pic) \
0855e32b
NS		 2854 DEF_STUB(long_branch_any_tls_pic) \
2855 DEF_STUB(long_branch_v4t_thumb_tls_pic) \
7a89b94e
NC		 2856 DEF_STUB(long_branch_arm_nacl) \
2857 DEF_STUB(long_branch_arm_nacl_pic) \
4ba2ef8f 2858 DEF_STUB(cmse_branch_thumb_only) \
48229727
JB		 2859 DEF_STUB(a8_veneer_b_cond) \
2860 DEF_STUB(a8_veneer_b) \
2861 DEF_STUB(a8_veneer_bl) \
80c135e5
TP		 2862 DEF_STUB(a8_veneer_blx) \
2863 DEF_STUB(long_branch_thumb2_only) \
d5a67c02 2864 DEF_STUB(long_branch_thumb2_only_pure)
738a79f6
CL		 2865
2866#define DEF_STUB(x) arm_stub_##x,
b38cadfb
NC		 2867enum elf32_arm_stub_type
2868{
906e58ca 2869 arm_stub_none,
738a79f6 2870 DEF_STUBS
4f4faa4d 2871 max_stub_type
738a79f6
CL		 2872};
2873#undef DEF_STUB
2874
8d9d9490
TP		 2875/* Note the first a8_veneer type. */
2876const unsigned arm_stub_a8_veneer_lwm = arm_stub_a8_veneer_b_cond;
2877
738a79f6
CL		 2878typedef struct
2879{
d3ce72d0 2880 const insn_sequence* template_sequence;
738a79f6
CL		 2881 int template_size;
2882} stub_def;
2883
2884#define DEF_STUB(x) {elf32_arm_stub_##x, ARRAY_SIZE(elf32_arm_stub_##x)},
b38cadfb
NC		 2885static const stub_def stub_definitions[] =
2886{
738a79f6
CL		 2887 {NULL, 0},
2888 DEF_STUBS
906e58ca
NC		 2889};
2890
2891struct elf32_arm_stub_hash_entry
2892{
2893 /* Base hash table entry structure. */
2894 struct bfd_hash_entry root;
2895
2896 /* The stub section. */
2897 asection *stub_sec;
2898
2899 /* Offset within stub_sec of the beginning of this stub. */
2900 bfd_vma stub_offset;
2901
2902 /* Given the symbol's value and its section we can determine its final
2903 value when building the stubs (so the stub knows where to jump). */
2904 bfd_vma target_value;
2905 asection *target_section;
2906
8d9d9490
TP		 2907 /* Same as above but for the source of the branch to the stub. Used for
2908 Cortex-A8 erratum workaround to patch it to branch to the stub. As
2909 such, source section does not need to be recorded since Cortex-A8 erratum
2910 workaround stubs are only generated when both source and target are in the
2911 same section. */
2912 bfd_vma source_value;
48229727
JB		 2913
2914 /* The instruction which caused this stub to be generated (only valid for
2915 Cortex-A8 erratum workaround stubs at present). */
2916 unsigned long orig_insn;
2917
461a49ca 2918 /* The stub type. */
906e58ca 2919 enum elf32_arm_stub_type stub_type;
461a49ca
DJ		 2920 /* Its encoding size in bytes. */
2921 int stub_size;
2922 /* Its template. */
2923 const insn_sequence *stub_template;
2924 /* The size of the template (number of entries). */
2925 int stub_template_size;
906e58ca
NC		 2926
2927 /* The symbol table entry, if any, that this was derived from. */
2928 struct elf32_arm_link_hash_entry *h;
2929
35fc36a8
RS		 2930 /* Type of branch. */
2931 enum arm_st_branch_type branch_type;
906e58ca
NC		 2932
2933 /* Where this stub is being called from, or, in the case of combined
2934 stub sections, the first input section in the group. */
2935 asection *id_sec;
7413f23f
DJ		 2936
2937 /* The name for the local symbol at the start of this stub. The
2938 stub name in the hash table has to be unique; this does not, so
2939 it can be friendlier. */
2940 char *output_name;
906e58ca
NC		 2941};
2942
e489d0ae
PB		 2943/* Used to build a map of a section. This is required for mixed-endian
2944 code/data. */
2945
2946typedef struct elf32_elf_section_map
2947{
2948 bfd_vma vma;
2949 char type;
2950}
2951elf32_arm_section_map;
2952
c7b8f16e
JB		 2953/* Information about a VFP11 erratum veneer, or a branch to such a veneer. */
2954
2955typedef enum
2956{
2957 VFP11_ERRATUM_BRANCH_TO_ARM_VENEER,
2958 VFP11_ERRATUM_BRANCH_TO_THUMB_VENEER,
2959 VFP11_ERRATUM_ARM_VENEER,
2960 VFP11_ERRATUM_THUMB_VENEER
2961}
2962elf32_vfp11_erratum_type;
2963
2964typedef struct elf32_vfp11_erratum_list
2965{
2966 struct elf32_vfp11_erratum_list *next;
2967 bfd_vma vma;
2968 union
2969 {
2970 struct
2971 {
2972 struct elf32_vfp11_erratum_list *veneer;
2973 unsigned int vfp_insn;
2974 } b;
2975 struct
2976 {
2977 struct elf32_vfp11_erratum_list *branch;
2978 unsigned int id;
2979 } v;
2980 } u;
2981 elf32_vfp11_erratum_type type;
2982}
2983elf32_vfp11_erratum_list;
2984
a504d23a
LA		 2985/* Information about a STM32L4XX erratum veneer, or a branch to such a
2986 veneer. */
2987typedef enum
2988{
2989 STM32L4XX_ERRATUM_BRANCH_TO_VENEER,
2990 STM32L4XX_ERRATUM_VENEER
2991}
2992elf32_stm32l4xx_erratum_type;
2993
2994typedef struct elf32_stm32l4xx_erratum_list
2995{
2996 struct elf32_stm32l4xx_erratum_list *next;
2997 bfd_vma vma;
2998 union
2999 {
3000 struct
3001 {
3002 struct elf32_stm32l4xx_erratum_list *veneer;
3003 unsigned int insn;
3004 } b;
3005 struct
3006 {
3007 struct elf32_stm32l4xx_erratum_list *branch;
3008 unsigned int id;
3009 } v;
3010 } u;
3011 elf32_stm32l4xx_erratum_type type;
3012}
3013elf32_stm32l4xx_erratum_list;
3014
2468f9c9
PB		 3015typedef enum
3016{
3017 DELETE_EXIDX_ENTRY,
3018 INSERT_EXIDX_CANTUNWIND_AT_END
3019}
3020arm_unwind_edit_type;
3021
3022/* A (sorted) list of edits to apply to an unwind table. */
3023typedef struct arm_unwind_table_edit
3024{
3025 arm_unwind_edit_type type;
3026 /* Note: we sometimes want to insert an unwind entry corresponding to a
3027 section different from the one we're currently writing out, so record the
3028 (text) section this edit relates to here. */
3029 asection *linked_section;
3030 unsigned int index;
3031 struct arm_unwind_table_edit *next;
3032}
3033arm_unwind_table_edit;
3034
8e3de13a 3035typedef struct _arm_elf_section_data
e489d0ae 3036{
2468f9c9 3037 /* Information about mapping symbols. */
e489d0ae 3038 struct bfd_elf_section_data elf;
8e3de13a 3039 unsigned int mapcount;
c7b8f16e 3040 unsigned int mapsize;
e489d0ae 3041 elf32_arm_section_map *map;
2468f9c9 3042 /* Information about CPU errata. */
c7b8f16e
JB		 3043 unsigned int erratumcount;
3044 elf32_vfp11_erratum_list *erratumlist;
a504d23a
LA		 3045 unsigned int stm32l4xx_erratumcount;
3046 elf32_stm32l4xx_erratum_list *stm32l4xx_erratumlist;
491d01d3 3047 unsigned int additional_reloc_count;
2468f9c9
PB		 3048 /* Information about unwind tables. */
3049 union
3050 {
3051 /* Unwind info attached to a text section. */
3052 struct
3053 {
3054 asection *arm_exidx_sec;
3055 } text;
3056
3057 /* Unwind info attached to an .ARM.exidx section. */
3058 struct
3059 {
3060 arm_unwind_table_edit *unwind_edit_list;
3061 arm_unwind_table_edit *unwind_edit_tail;
3062 } exidx;
3063 } u;
8e3de13a
NC		 3064}
3065_arm_elf_section_data;
e489d0ae
PB		 3066
3067#define elf32_arm_section_data(sec) \
8e3de13a 3068 ((_arm_elf_section_data *) elf_section_data (sec))
e489d0ae 3069
48229727
JB		 3070/* A fix which might be required for Cortex-A8 Thumb-2 branch/TLB erratum.
3071 These fixes are subject to a relaxation procedure (in elf32_arm_size_stubs),
3072 so may be created multiple times: we use an array of these entries whilst
3073 relaxing which we can refresh easily, then create stubs for each potentially
3074 erratum-triggering instruction once we've settled on a solution. */
3075
b38cadfb
NC		 3076struct a8_erratum_fix
3077{
48229727
JB		 3078 bfd *input_bfd;
3079 asection *section;
3080 bfd_vma offset;
8d9d9490 3081 bfd_vma target_offset;
48229727
JB		 3082 unsigned long orig_insn;
3083 char *stub_name;
3084 enum elf32_arm_stub_type stub_type;
35fc36a8 3085 enum arm_st_branch_type branch_type;
48229727
JB		 3086};
3087
3088/* A table of relocs applied to branches which might trigger Cortex-A8
3089 erratum. */
3090
b38cadfb
NC		 3091struct a8_erratum_reloc
3092{
48229727
JB		 3093 bfd_vma from;
3094 bfd_vma destination;
92750f34
DJ		 3095 struct elf32_arm_link_hash_entry *hash;
3096 const char *sym_name;
48229727 3097 unsigned int r_type;
35fc36a8 3098 enum arm_st_branch_type branch_type;
48229727
JB		 3099 bfd_boolean non_a8_stub;
3100};
3101
ba93b8ac
DJ		 3102/* The size of the thread control block. */
3103#define TCB_SIZE 8
3104
34e77a92
RS		 3105/* ARM-specific information about a PLT entry, over and above the usual
3106 gotplt_union. */
b38cadfb
NC		 3107struct arm_plt_info
3108{
34e77a92
RS		 3109 /* We reference count Thumb references to a PLT entry separately,
3110 so that we can emit the Thumb trampoline only if needed. */
3111 bfd_signed_vma thumb_refcount;
3112
3113 /* Some references from Thumb code may be eliminated by BL->BLX
3114 conversion, so record them separately. */
3115 bfd_signed_vma maybe_thumb_refcount;
3116
3117 /* How many of the recorded PLT accesses were from non-call relocations.
3118 This information is useful when deciding whether anything takes the
3119 address of an STT_GNU_IFUNC PLT. A value of 0 means that all
3120 non-call references to the function should resolve directly to the
3121 real runtime target. */
3122 unsigned int noncall_refcount;
3123
3124 /* Since PLT entries have variable size if the Thumb prologue is
3125 used, we need to record the index into .got.plt instead of
3126 recomputing it from the PLT offset. */
3127 bfd_signed_vma got_offset;
3128};
3129
3130/* Information about an .iplt entry for a local STT_GNU_IFUNC symbol. */
b38cadfb
NC		 3131struct arm_local_iplt_info
3132{
34e77a92
RS		 3133 /* The information that is usually found in the generic ELF part of
3134 the hash table entry. */
3135 union gotplt_union root;
3136
3137 /* The information that is usually found in the ARM-specific part of
3138 the hash table entry. */
3139 struct arm_plt_info arm;
3140
3141 /* A list of all potential dynamic relocations against this symbol. */
3142 struct elf_dyn_relocs *dyn_relocs;
3143};
3144
e8b09b87
CL		 3145/* Structure to handle FDPIC support for local functions. */
3146struct fdpic_local {
3147 unsigned int funcdesc_cnt;
3148 unsigned int gotofffuncdesc_cnt;
3149 int funcdesc_offset;
3150};
3151
0ffa91dd 3152struct elf_arm_obj_tdata
ba93b8ac
DJ		 3153{
3154 struct elf_obj_tdata root;
3155
3156 /* tls_type for each local got entry. */
3157 char *local_got_tls_type;
ee065d83 3158
0855e32b
NS		 3159 /* GOTPLT entries for TLS descriptors. */
3160 bfd_vma *local_tlsdesc_gotent;
3161
34e77a92
RS		 3162 /* Information for local symbols that need entries in .iplt. */
3163 struct arm_local_iplt_info **local_iplt;
3164
bf21ed78
MS		 3165 /* Zero to warn when linking objects with incompatible enum sizes. */
3166 int no_enum_size_warning;
a9dc9481
JM		 3167
3168 /* Zero to warn when linking objects with incompatible wchar_t sizes. */
3169 int no_wchar_size_warning;
e8b09b87
CL		 3170
3171 /* Maintains FDPIC counters and funcdesc info. */
3172 struct fdpic_local *local_fdpic_cnts;
ba93b8ac
DJ		 3173};
3174
0ffa91dd
NC		 3175#define elf_arm_tdata(bfd) \
3176 ((struct elf_arm_obj_tdata *) (bfd)->tdata.any)
ba93b8ac 3177
0ffa91dd
NC		 3178#define elf32_arm_local_got_tls_type(bfd) \
3179 (elf_arm_tdata (bfd)->local_got_tls_type)
3180
0855e32b
NS		 3181#define elf32_arm_local_tlsdesc_gotent(bfd) \
3182 (elf_arm_tdata (bfd)->local_tlsdesc_gotent)
3183
34e77a92
RS		 3184#define elf32_arm_local_iplt(bfd) \
3185 (elf_arm_tdata (bfd)->local_iplt)
3186
e8b09b87
CL		 3187#define elf32_arm_local_fdpic_cnts(bfd) \
3188 (elf_arm_tdata (bfd)->local_fdpic_cnts)
3189
0ffa91dd
NC		 3190#define is_arm_elf(bfd) \
3191 (bfd_get_flavour (bfd) == bfd_target_elf_flavour \
3192 && elf_tdata (bfd) != NULL \
4dfe6ac6 3193 && elf_object_id (bfd) == ARM_ELF_DATA)
ba93b8ac
DJ		 3194
3195static bfd_boolean
3196elf32_arm_mkobject (bfd *abfd)
3197{
0ffa91dd 3198 return bfd_elf_allocate_object (abfd, sizeof (struct elf_arm_obj_tdata),
4dfe6ac6 3199 ARM_ELF_DATA);
ba93b8ac
DJ		 3200}
3201
ba93b8ac
DJ		 3202#define elf32_arm_hash_entry(ent) ((struct elf32_arm_link_hash_entry *)(ent))
3203
e8b09b87
CL		 3204/* Structure to handle FDPIC support for extern functions. */
3205struct fdpic_global {
3206 unsigned int gotofffuncdesc_cnt;
3207 unsigned int gotfuncdesc_cnt;
3208 unsigned int funcdesc_cnt;
3209 int funcdesc_offset;
3210 int gotfuncdesc_offset;
3211};
3212
ba96a88f 3213/* Arm ELF linker hash entry. */
252b5132 3214struct elf32_arm_link_hash_entry
b38cadfb
NC		 3215{
3216 struct elf_link_hash_entry root;
252b5132 3217
b38cadfb
NC		 3218 /* ARM-specific PLT information. */
3219 struct arm_plt_info plt;
ba93b8ac
DJ		 3220
3221#define GOT_UNKNOWN 0
3222#define GOT_NORMAL 1
3223#define GOT_TLS_GD 2
3224#define GOT_TLS_IE 4
0855e32b
NS		 3225#define GOT_TLS_GDESC 8
3226#define GOT_TLS_GD_ANY_P(type) ((type & GOT_TLS_GD) || (type & GOT_TLS_GDESC))
b38cadfb 3227 unsigned int tls_type : 8;
34e77a92 3228
b38cadfb
NC		 3229 /* True if the symbol's PLT entry is in .iplt rather than .plt. */
3230 unsigned int is_iplt : 1;
34e77a92 3231
b38cadfb 3232 unsigned int unused : 23;
a4fd1a8e 3233
b38cadfb
NC		 3234 /* Offset of the GOTPLT entry reserved for the TLS descriptor,
3235 starting at the end of the jump table. */
3236 bfd_vma tlsdesc_got;
0855e32b 3237
b38cadfb
NC		 3238 /* The symbol marking the real symbol location for exported thumb
3239 symbols with Arm stubs. */
3240 struct elf_link_hash_entry *export_glue;
906e58ca 3241
b38cadfb 3242 /* A pointer to the most recently used stub hash entry against this
8029a119 3243 symbol. */
b38cadfb 3244 struct elf32_arm_stub_hash_entry *stub_cache;
e8b09b87
CL		 3245
3246 /* Counter for FDPIC relocations against this symbol. */
3247 struct fdpic_global fdpic_cnts;
b38cadfb 3248};
252b5132 3249
252b5132 3250/* Traverse an arm ELF linker hash table. */
252b5132
RH		 3251#define elf32_arm_link_hash_traverse(table, func, info) \
3252 (elf_link_hash_traverse \
3253 (&(table)->root, \
b7693d02 3254 (bfd_boolean (*) (struct elf_link_hash_entry *, void *)) (func), \
252b5132
RH		 3255 (info)))
3256
3257/* Get the ARM elf linker hash table from a link_info structure. */
3258#define elf32_arm_hash_table(info) \
4dfe6ac6
NC		 3259 (elf_hash_table_id ((struct elf_link_hash_table *) ((info)->hash)) \
3260 == ARM_ELF_DATA ? ((struct elf32_arm_link_hash_table *) ((info)->hash)) : NULL)
252b5132 3261
906e58ca
NC		 3262#define arm_stub_hash_lookup(table, string, create, copy) \
3263 ((struct elf32_arm_stub_hash_entry *) \
3264 bfd_hash_lookup ((table), (string), (create), (copy)))
3265
21d799b5
NC		 3266/* Array to keep track of which stub sections have been created, and
3267 information on stub grouping. */
3268struct map_stub
3269{
3270 /* This is the section to which stubs in the group will be
3271 attached. */
3272 asection *link_sec;
3273 /* The stub section. */
3274 asection *stub_sec;
3275};
3276
0855e32b
NS		 3277#define elf32_arm_compute_jump_table_size(htab) \
3278 ((htab)->next_tls_desc_index * 4)
3279
9b485d32 3280/* ARM ELF linker hash table. */
252b5132 3281struct elf32_arm_link_hash_table
906e58ca
NC		 3282{
3283 /* The main hash table. */
3284 struct elf_link_hash_table root;
252b5132 3285
906e58ca
NC		 3286 /* The size in bytes of the section containing the Thumb-to-ARM glue. */
3287 bfd_size_type thumb_glue_size;
252b5132 3288
906e58ca
NC		 3289 /* The size in bytes of the section containing the ARM-to-Thumb glue. */
3290 bfd_size_type arm_glue_size;
252b5132 3291
906e58ca
NC		 3292 /* The size in bytes of section containing the ARMv4 BX veneers. */
3293 bfd_size_type bx_glue_size;
845b51d6 3294
906e58ca
NC		 3295 /* Offsets of ARMv4 BX veneers. Bit1 set if present, and Bit0 set when
3296 veneer has been populated. */
3297 bfd_vma bx_glue_offset[15];
845b51d6 3298
906e58ca
NC		 3299 /* The size in bytes of the section containing glue for VFP11 erratum
3300 veneers. */
3301 bfd_size_type vfp11_erratum_glue_size;
c7b8f16e 3302
a504d23a
LA		 3303 /* The size in bytes of the section containing glue for STM32L4XX erratum
3304 veneers. */
3305 bfd_size_type stm32l4xx_erratum_glue_size;
3306
48229727
JB		 3307 /* A table of fix locations for Cortex-A8 Thumb-2 branch/TLB erratum. This
3308 holds Cortex-A8 erratum fix locations between elf32_arm_size_stubs() and
3309 elf32_arm_write_section(). */
3310 struct a8_erratum_fix *a8_erratum_fixes;
3311 unsigned int num_a8_erratum_fixes;
3312
906e58ca
NC		 3313 /* An arbitrary input BFD chosen to hold the glue sections. */
3314 bfd * bfd_of_glue_owner;
ba96a88f 3315
906e58ca
NC		 3316 /* Nonzero to output a BE8 image. */
3317 int byteswap_code;
e489d0ae 3318
906e58ca
NC		 3319 /* Zero if R_ARM_TARGET1 means R_ARM_ABS32.
3320 Nonzero if R_ARM_TARGET1 means R_ARM_REL32. */
3321 int target1_is_rel;
9c504268 3322
906e58ca
NC		 3323 /* The relocation to use for R_ARM_TARGET2 relocations. */
3324 int target2_reloc;
eb043451 3325
906e58ca
NC		 3326 /* 0 = Ignore R_ARM_V4BX.
3327 1 = Convert BX to MOV PC.
3328 2 = Generate v4 interworing stubs. */
3329 int fix_v4bx;
319850b4 3330
48229727
JB		 3331 /* Whether we should fix the Cortex-A8 Thumb-2 branch/TLB erratum. */
3332 int fix_cortex_a8;
3333
2de70689
MGD		 3334 /* Whether we should fix the ARM1176 BLX immediate issue. */
3335 int fix_arm1176;
3336
906e58ca
NC		 3337 /* Nonzero if the ARM/Thumb BLX instructions are available for use. */
3338 int use_blx;
33bfe774 3339
906e58ca
NC		 3340 /* What sort of code sequences we should look for which may trigger the
3341 VFP11 denorm erratum. */
3342 bfd_arm_vfp11_fix vfp11_fix;
c7b8f16e 3343
906e58ca
NC		 3344 /* Global counter for the number of fixes we have emitted. */
3345 int num_vfp11_fixes;
c7b8f16e 3346
a504d23a
LA		 3347 /* What sort of code sequences we should look for which may trigger the
3348 STM32L4XX erratum. */
3349 bfd_arm_stm32l4xx_fix stm32l4xx_fix;
3350
3351 /* Global counter for the number of fixes we have emitted. */
3352 int num_stm32l4xx_fixes;
3353
906e58ca
NC		 3354 /* Nonzero to force PIC branch veneers. */
3355 int pic_veneer;
27e55c4d 3356
906e58ca
NC		 3357 /* The number of bytes in the initial entry in the PLT. */
3358 bfd_size_type plt_header_size;
e5a52504 3359
906e58ca
NC		 3360 /* The number of bytes in the subsequent PLT etries. */
3361 bfd_size_type plt_entry_size;
e5a52504 3362
906e58ca
NC		 3363 /* True if the target system is VxWorks. */
3364 int vxworks_p;
00a97672 3365
906e58ca
NC		 3366 /* True if the target system is Symbian OS. */
3367 int symbian_p;
e5a52504 3368
b38cadfb
NC		 3369 /* True if the target system is Native Client. */
3370 int nacl_p;
3371
906e58ca 3372 /* True if the target uses REL relocations. */
f3185997 3373 bfd_boolean use_rel;
4e7fd91e 3374
54ddd295
TP		 3375 /* Nonzero if import library must be a secure gateway import library
3376 as per ARMv8-M Security Extensions. */
3377 int cmse_implib;
3378
0955507f
TP		 3379 /* The import library whose symbols' address must remain stable in
3380 the import library generated. */
3381 bfd *in_implib_bfd;
3382
0855e32b
NS		 3383 /* The index of the next unused R_ARM_TLS_DESC slot in .rel.plt. */
3384 bfd_vma next_tls_desc_index;
3385
3386 /* How many R_ARM_TLS_DESC relocations were generated so far. */
3387 bfd_vma num_tls_desc;
3388
906e58ca
NC		 3389 /* The (unloaded but important) VxWorks .rela.plt.unloaded section. */
3390 asection *srelplt2;
00a97672 3391
0855e32b
NS		 3392 /* The offset into splt of the PLT entry for the TLS descriptor
3393 resolver. Special values are 0, if not necessary (or not found
3394 to be necessary yet), and -1 if needed but not determined
3395 yet. */
3396 bfd_vma dt_tlsdesc_plt;
3397
3398 /* The offset into sgot of the GOT entry used by the PLT entry
3399 above. */
b38cadfb 3400 bfd_vma dt_tlsdesc_got;
0855e32b
NS		 3401
3402 /* Offset in .plt section of tls_arm_trampoline. */
3403 bfd_vma tls_trampoline;
3404
5c5a4843 3405 /* Data for R_ARM_TLS_LDM32/R_ARM_TLS_LDM32_FDPIC relocations. */
906e58ca
NC		 3406 union
3407 {
3408 bfd_signed_vma refcount;
3409 bfd_vma offset;
3410 } tls_ldm_got;
b7693d02 3411
87d72d41
AM		 3412 /* Small local sym cache. */
3413 struct sym_cache sym_cache;
906e58ca
NC		 3414
3415 /* For convenience in allocate_dynrelocs. */
3416 bfd * obfd;
3417
0855e32b
NS		 3418 /* The amount of space used by the reserved portion of the sgotplt
3419 section, plus whatever space is used by the jump slots. */
3420 bfd_vma sgotplt_jump_table_size;
3421
906e58ca
NC		 3422 /* The stub hash table. */
3423 struct bfd_hash_table stub_hash_table;
3424
3425 /* Linker stub bfd. */
3426 bfd *stub_bfd;
3427
3428 /* Linker call-backs. */
6bde4c52
TP		 3429 asection * (*add_stub_section) (const char *, asection *, asection *,
3430 unsigned int);
906e58ca
NC		 3431 void (*layout_sections_again) (void);
3432
3433 /* Array to keep track of which stub sections have been created, and
3434 information on stub grouping. */
21d799b5 3435 struct map_stub *stub_group;
906e58ca 3436
4ba2ef8f
TP		 3437 /* Input stub section holding secure gateway veneers. */
3438 asection *cmse_stub_sec;
3439
0955507f
TP		 3440 /* Offset in cmse_stub_sec where new SG veneers (not in input import library)
3441 start to be allocated. */
3442 bfd_vma new_cmse_stub_offset;
3443
fe33d2fa 3444 /* Number of elements in stub_group. */
7292b3ac 3445 unsigned int top_id;
fe33d2fa 3446
906e58ca
NC		 3447 /* Assorted information used by elf32_arm_size_stubs. */
3448 unsigned int bfd_count;
7292b3ac 3449 unsigned int top_index;
906e58ca 3450 asection **input_list;
617a5ada
CL		 3451
3452 /* True if the target system uses FDPIC. */
3453 int fdpic_p;
e8b09b87
CL		 3454
3455 /* Fixup section. Used for FDPIC. */
3456 asection *srofixup;
906e58ca 3457};
252b5132 3458
e8b09b87
CL		 3459/* Add an FDPIC read-only fixup. */
3460static void
3461arm_elf_add_rofixup (bfd *output_bfd, asection *srofixup, bfd_vma offset)
3462{
3463 bfd_vma fixup_offset;
3464
3465 fixup_offset = srofixup->reloc_count++ * 4;
3466 BFD_ASSERT (fixup_offset < srofixup->size);
3467 bfd_put_32 (output_bfd, offset, srofixup->contents + fixup_offset);
3468}
3469
a504d23a
LA		 3470static inline int
3471ctz (unsigned int mask)
3472{
3473#if GCC_VERSION >= 3004
3474 return __builtin_ctz (mask);
3475#else
3476 unsigned int i;
3477
3478 for (i = 0; i < 8 * sizeof (mask); i++)
3479 {
3480 if (mask & 0x1)
3481 break;
3482 mask = (mask >> 1);
3483 }
3484 return i;
3485#endif
3486}
3487
3488static inline int
b25e998d 3489elf32_arm_popcount (unsigned int mask)
a504d23a
LA		 3490{
3491#if GCC_VERSION >= 3004
3492 return __builtin_popcount (mask);
3493#else
b25e998d
CG		 3494 unsigned int i;
3495 int sum = 0;
a504d23a
LA		 3496
3497 for (i = 0; i < 8 * sizeof (mask); i++)
3498 {
3499 if (mask & 0x1)
3500 sum++;
3501 mask = (mask >> 1);
3502 }
3503 return sum;
3504#endif
3505}
3506
e8b09b87
CL		 3507static void elf32_arm_add_dynreloc (bfd *output_bfd, struct bfd_link_info *info,
3508 asection *sreloc, Elf_Internal_Rela *rel);
3509
3510static void
3511arm_elf_fill_funcdesc(bfd *output_bfd,
3512 struct bfd_link_info *info,
3513 int *funcdesc_offset,
3514 int dynindx,
3515 int offset,
3516 bfd_vma addr,
3517 bfd_vma dynreloc_value,
3518 bfd_vma seg)
3519{
3520 if ((*funcdesc_offset & 1) == 0)
3521 {
3522 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (info);
3523 asection *sgot = globals->root.sgot;
3524
3525 if (bfd_link_pic(info))
3526 {
3527 asection *srelgot = globals->root.srelgot;
3528 Elf_Internal_Rela outrel;
3529
3530 outrel.r_info = ELF32_R_INFO (dynindx, R_ARM_FUNCDESC_VALUE);
3531 outrel.r_offset = sgot->output_section->vma + sgot->output_offset + offset;
3532 outrel.r_addend = 0;
3533
3534 elf32_arm_add_dynreloc (output_bfd, info, srelgot, &outrel);
3535 bfd_put_32 (output_bfd, addr, sgot->contents + offset);
3536 bfd_put_32 (output_bfd, seg, sgot->contents + offset + 4);
3537 }
3538 else
3539 {
3540 struct elf_link_hash_entry *hgot = globals->root.hgot;
3541 bfd_vma got_value = hgot->root.u.def.value
3542 + hgot->root.u.def.section->output_section->vma
3543 + hgot->root.u.def.section->output_offset;
3544
3545 arm_elf_add_rofixup(output_bfd, globals->srofixup,
3546 sgot->output_section->vma + sgot->output_offset
3547 + offset);
3548 arm_elf_add_rofixup(output_bfd, globals->srofixup,
3549 sgot->output_section->vma + sgot->output_offset
3550 + offset + 4);
3551 bfd_put_32 (output_bfd, dynreloc_value, sgot->contents + offset);
3552 bfd_put_32 (output_bfd, got_value, sgot->contents + offset + 4);
3553 }
3554 *funcdesc_offset |= 1;
3555 }
3556}
3557
780a67af
NC		 3558/* Create an entry in an ARM ELF linker hash table. */
3559
3560static struct bfd_hash_entry *
57e8b36a 3561elf32_arm_link_hash_newfunc (struct bfd_hash_entry * entry,
99059e56
RM		 3562 struct bfd_hash_table * table,
3563 const char * string)
780a67af
NC		 3564{
3565 struct elf32_arm_link_hash_entry * ret =
3566 (struct elf32_arm_link_hash_entry *) entry;
3567
3568 /* Allocate the structure if it has not already been allocated by a
3569 subclass. */
906e58ca 3570 if (ret == NULL)
21d799b5 3571 ret = (struct elf32_arm_link_hash_entry *)
99059e56 3572 bfd_hash_allocate (table, sizeof (struct elf32_arm_link_hash_entry));
57e8b36a 3573 if (ret == NULL)
780a67af
NC		 3574 return (struct bfd_hash_entry *) ret;
3575
3576 /* Call the allocation method of the superclass. */
3577 ret = ((struct elf32_arm_link_hash_entry *)
3578 _bfd_elf_link_hash_newfunc ((struct bfd_hash_entry *) ret,
3579 table, string));
57e8b36a 3580 if (ret != NULL)
b7693d02 3581 {
ba93b8ac 3582 ret->tls_type = GOT_UNKNOWN;
0855e32b 3583 ret->tlsdesc_got = (bfd_vma) -1;
34e77a92
RS		 3584 ret->plt.thumb_refcount = 0;
3585 ret->plt.maybe_thumb_refcount = 0;
3586 ret->plt.noncall_refcount = 0;
3587 ret->plt.got_offset = -1;
3588 ret->is_iplt = FALSE;
a4fd1a8e 3589 ret->export_glue = NULL;
906e58ca
NC		 3590
3591 ret->stub_cache = NULL;
e8b09b87
CL		 3592
3593 ret->fdpic_cnts.gotofffuncdesc_cnt = 0;
3594 ret->fdpic_cnts.gotfuncdesc_cnt = 0;
3595 ret->fdpic_cnts.funcdesc_cnt = 0;
3596 ret->fdpic_cnts.funcdesc_offset = -1;
3597 ret->fdpic_cnts.gotfuncdesc_offset = -1;
b7693d02 3598 }
780a67af
NC		 3599
3600 return (struct bfd_hash_entry *) ret;
3601}
3602
34e77a92
RS		 3603/* Ensure that we have allocated bookkeeping structures for ABFD's local
3604 symbols. */
3605
3606static bfd_boolean
3607elf32_arm_allocate_local_sym_info (bfd *abfd)
3608{
3609 if (elf_local_got_refcounts (abfd) == NULL)
3610 {
3611 bfd_size_type num_syms;
3612 bfd_size_type size;
3613 char *data;
3614
3615 num_syms = elf_tdata (abfd)->symtab_hdr.sh_info;
3616 size = num_syms * (sizeof (bfd_signed_vma)
3617 + sizeof (struct arm_local_iplt_info *)
3618 + sizeof (bfd_vma)
e8b09b87
CL		 3619 + sizeof (char)
3620 + sizeof (struct fdpic_local));
34e77a92
RS		 3621 data = bfd_zalloc (abfd, size);
3622 if (data == NULL)
3623 return FALSE;
3624
e8b09b87
CL		 3625 elf32_arm_local_fdpic_cnts (abfd) = (struct fdpic_local *) data;
3626 data += num_syms * sizeof (struct fdpic_local);
3627
34e77a92
RS		 3628 elf_local_got_refcounts (abfd) = (bfd_signed_vma *) data;
3629 data += num_syms * sizeof (bfd_signed_vma);
3630
3631 elf32_arm_local_iplt (abfd) = (struct arm_local_iplt_info **) data;
3632 data += num_syms * sizeof (struct arm_local_iplt_info *);
3633
3634 elf32_arm_local_tlsdesc_gotent (abfd) = (bfd_vma *) data;
3635 data += num_syms * sizeof (bfd_vma);
3636
3637 elf32_arm_local_got_tls_type (abfd) = data;
3638 }
3639 return TRUE;
3640}
3641
3642/* Return the .iplt information for local symbol R_SYMNDX, which belongs
3643 to input bfd ABFD. Create the information if it doesn't already exist.
3644 Return null if an allocation fails. */
3645
3646static struct arm_local_iplt_info *
3647elf32_arm_create_local_iplt (bfd *abfd, unsigned long r_symndx)
3648{
3649 struct arm_local_iplt_info **ptr;
3650
3651 if (!elf32_arm_allocate_local_sym_info (abfd))
3652 return NULL;
3653
3654 BFD_ASSERT (r_symndx < elf_tdata (abfd)->symtab_hdr.sh_info);
3655 ptr = &elf32_arm_local_iplt (abfd)[r_symndx];
3656 if (*ptr == NULL)
3657 *ptr = bfd_zalloc (abfd, sizeof (**ptr));
3658 return *ptr;
3659}
3660
3661/* Try to obtain PLT information for the symbol with index R_SYMNDX
3662 in ABFD's symbol table. If the symbol is global, H points to its
3663 hash table entry, otherwise H is null.
3664
3665 Return true if the symbol does have PLT information. When returning
3666 true, point *ROOT_PLT at the target-independent reference count/offset
3667 union and *ARM_PLT at the ARM-specific information. */
3668
3669static bfd_boolean
4ba2ef8f
TP		 3670elf32_arm_get_plt_info (bfd *abfd, struct elf32_arm_link_hash_table *globals,
3671 struct elf32_arm_link_hash_entry *h,
34e77a92
RS		 3672 unsigned long r_symndx, union gotplt_union **root_plt,
3673 struct arm_plt_info **arm_plt)
3674{
3675 struct arm_local_iplt_info *local_iplt;
3676
4ba2ef8f
TP		 3677 if (globals->root.splt == NULL && globals->root.iplt == NULL)
3678 return FALSE;
3679
34e77a92
RS		 3680 if (h != NULL)
3681 {
3682 *root_plt = &h->root.plt;
3683 *arm_plt = &h->plt;
3684 return TRUE;
3685 }
3686
3687 if (elf32_arm_local_iplt (abfd) == NULL)
3688 return FALSE;
3689
3690 local_iplt = elf32_arm_local_iplt (abfd)[r_symndx];
3691 if (local_iplt == NULL)
3692 return FALSE;
3693
3694 *root_plt = &local_iplt->root;
3695 *arm_plt = &local_iplt->arm;
3696 return TRUE;
3697}
3698
59029f57
CL		 3699static bfd_boolean using_thumb_only (struct elf32_arm_link_hash_table *globals);
3700
34e77a92
RS		 3701/* Return true if the PLT described by ARM_PLT requires a Thumb stub
3702 before it. */
3703
3704static bfd_boolean
3705elf32_arm_plt_needs_thumb_stub_p (struct bfd_link_info *info,
3706 struct arm_plt_info *arm_plt)
3707{
3708 struct elf32_arm_link_hash_table *htab;
3709
3710 htab = elf32_arm_hash_table (info);
59029f57
CL		 3711
3712 return (!using_thumb_only(htab) && (arm_plt->thumb_refcount != 0
3713 || (!htab->use_blx && arm_plt->maybe_thumb_refcount != 0)));
34e77a92
RS		 3714}
3715
3716/* Return a pointer to the head of the dynamic reloc list that should
3717 be used for local symbol ISYM, which is symbol number R_SYMNDX in
3718 ABFD's symbol table. Return null if an error occurs. */
3719
3720static struct elf_dyn_relocs **
3721elf32_arm_get_local_dynreloc_list (bfd *abfd, unsigned long r_symndx,
3722 Elf_Internal_Sym *isym)
3723{
3724 if (ELF32_ST_TYPE (isym->st_info) == STT_GNU_IFUNC)
3725 {
3726 struct arm_local_iplt_info *local_iplt;
3727
3728 local_iplt = elf32_arm_create_local_iplt (abfd, r_symndx);
3729 if (local_iplt == NULL)
3730 return NULL;
3731 return &local_iplt->dyn_relocs;
3732 }
3733 else
3734 {
3735 /* Track dynamic relocs needed for local syms too.
3736 We really need local syms available to do this
3737 easily. Oh well. */
3738 asection *s;
3739 void *vpp;
3740
3741 s = bfd_section_from_elf_index (abfd, isym->st_shndx);
3742 if (s == NULL)
3743 abort ();
3744
3745 vpp = &elf_section_data (s)->local_dynrel;
3746 return (struct elf_dyn_relocs **) vpp;
3747 }
3748}
3749
906e58ca
NC		 3750/* Initialize an entry in the stub hash table. */
3751
3752static struct bfd_hash_entry *
3753stub_hash_newfunc (struct bfd_hash_entry *entry,
3754 struct bfd_hash_table *table,
3755 const char *string)
3756{
3757 /* Allocate the structure if it has not already been allocated by a
3758 subclass. */
3759 if (entry == NULL)
3760 {
21d799b5 3761 entry = (struct bfd_hash_entry *)
99059e56 3762 bfd_hash_allocate (table, sizeof (struct elf32_arm_stub_hash_entry));
906e58ca
NC		 3763 if (entry == NULL)
3764 return entry;
3765 }
3766
3767 /* Call the allocation method of the superclass. */
3768 entry = bfd_hash_newfunc (entry, table, string);
3769 if (entry != NULL)
3770 {
3771 struct elf32_arm_stub_hash_entry *eh;
3772
3773 /* Initialize the local fields. */
3774 eh = (struct elf32_arm_stub_hash_entry *) entry;
3775 eh->stub_sec = NULL;
0955507f 3776 eh->stub_offset = (bfd_vma) -1;
8d9d9490 3777 eh->source_value = 0;
906e58ca
NC		 3778 eh->target_value = 0;
3779 eh->target_section = NULL;
cedfb179 3780 eh->orig_insn = 0;
906e58ca 3781 eh->stub_type = arm_stub_none;
461a49ca
DJ		 3782 eh->stub_size = 0;
3783 eh->stub_template = NULL;
0955507f 3784 eh->stub_template_size = -1;
906e58ca
NC		 3785 eh->h = NULL;
3786 eh->id_sec = NULL;
d8d2f433 3787 eh->output_name = NULL;
906e58ca
NC		 3788 }
3789
3790 return entry;
3791}
3792
00a97672 3793/* Create .got, .gotplt, and .rel(a).got sections in DYNOBJ, and set up
5e681ec4
PB		 3794 shortcuts to them in our hash table. */
3795
3796static bfd_boolean
57e8b36a 3797create_got_section (bfd *dynobj, struct bfd_link_info *info)
5e681ec4
PB		 3798{
3799 struct elf32_arm_link_hash_table *htab;
3800
e5a52504 3801 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 3802 if (htab == NULL)
3803 return FALSE;
3804
e5a52504
MM		 3805 /* BPABI objects never have a GOT, or associated sections. */
3806 if (htab->symbian_p)
3807 return TRUE;
3808
5e681ec4
PB		 3809 if (! _bfd_elf_create_got_section (dynobj, info))
3810 return FALSE;
3811
e8b09b87
CL		 3812 /* Also create .rofixup. */
3813 if (htab->fdpic_p)
3814 {
3815 htab->srofixup = bfd_make_section_with_flags (dynobj, ".rofixup",
3816 (SEC_ALLOC | SEC_LOAD | SEC_HAS_CONTENTS
3817 | SEC_IN_MEMORY | SEC_LINKER_CREATED | SEC_READONLY));
fd361982
AM		 3818 if (htab->srofixup == NULL
3819 || !bfd_set_section_alignment (htab->srofixup, 2))
e8b09b87
CL		 3820 return FALSE;
3821 }
3822
5e681ec4
PB		 3823 return TRUE;
3824}
3825
34e77a92
RS		 3826/* Create the .iplt, .rel(a).iplt and .igot.plt sections. */
3827
3828static bfd_boolean
3829create_ifunc_sections (struct bfd_link_info *info)
3830{
3831 struct elf32_arm_link_hash_table *htab;
3832 const struct elf_backend_data *bed;
3833 bfd *dynobj;
3834 asection *s;
3835 flagword flags;
b38cadfb 3836
34e77a92
RS		 3837 htab = elf32_arm_hash_table (info);
3838 dynobj = htab->root.dynobj;
3839 bed = get_elf_backend_data (dynobj);
3840 flags = bed->dynamic_sec_flags;
3841
3842 if (htab->root.iplt == NULL)
3843 {
3d4d4302
AM		 3844 s = bfd_make_section_anyway_with_flags (dynobj, ".iplt",
3845 flags | SEC_READONLY | SEC_CODE);
34e77a92 3846 if (s == NULL
fd361982 3847 || !bfd_set_section_alignment (s, bed->plt_alignment))
34e77a92
RS		 3848 return FALSE;
3849 htab->root.iplt = s;
3850 }
3851
3852 if (htab->root.irelplt == NULL)
3853 {
3d4d4302
AM		 3854 s = bfd_make_section_anyway_with_flags (dynobj,
3855 RELOC_SECTION (htab, ".iplt"),
3856 flags | SEC_READONLY);
34e77a92 3857 if (s == NULL
fd361982 3858 || !bfd_set_section_alignment (s, bed->s->log_file_align))
34e77a92
RS		 3859 return FALSE;
3860 htab->root.irelplt = s;
3861 }
3862
3863 if (htab->root.igotplt == NULL)
3864 {
3d4d4302 3865 s = bfd_make_section_anyway_with_flags (dynobj, ".igot.plt", flags);
34e77a92 3866 if (s == NULL
fd361982 3867 || !bfd_set_section_alignment (s, bed->s->log_file_align))
34e77a92
RS		 3868 return FALSE;
3869 htab->root.igotplt = s;
3870 }
3871 return TRUE;
3872}
3873
eed94f8f
NC		 3874/* Determine if we're dealing with a Thumb only architecture. */
3875
3876static bfd_boolean
3877using_thumb_only (struct elf32_arm_link_hash_table *globals)
3878{
2fd158eb
TP		 3879 int arch;
3880 int profile = bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC,
3881 Tag_CPU_arch_profile);
eed94f8f 3882
2fd158eb
TP		 3883 if (profile)
3884 return profile == 'M';
eed94f8f 3885
2fd158eb 3886 arch = bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC, Tag_CPU_arch);
eed94f8f 3887
60a019a0 3888 /* Force return logic to be reviewed for each new architecture. */
031254f2 3889 BFD_ASSERT (arch <= TAG_CPU_ARCH_V8_1M_MAIN);
60a019a0 3890
2fd158eb
TP		 3891 if (arch == TAG_CPU_ARCH_V6_M
3892 || arch == TAG_CPU_ARCH_V6S_M
3893 || arch == TAG_CPU_ARCH_V7E_M
3894 || arch == TAG_CPU_ARCH_V8M_BASE
031254f2
AV		 3895 || arch == TAG_CPU_ARCH_V8M_MAIN
3896 || arch == TAG_CPU_ARCH_V8_1M_MAIN)
2fd158eb 3897 return TRUE;
eed94f8f 3898
2fd158eb 3899 return FALSE;
eed94f8f
NC		 3900}
3901
3902/* Determine if we're dealing with a Thumb-2 object. */
3903
3904static bfd_boolean
3905using_thumb2 (struct elf32_arm_link_hash_table *globals)
3906{
60a019a0
TP		 3907 int arch;
3908 int thumb_isa = bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC,
3909 Tag_THUMB_ISA_use);
3910
3911 if (thumb_isa)
3912 return thumb_isa == 2;
3913
3914 arch = bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC, Tag_CPU_arch);
3915
3916 /* Force return logic to be reviewed for each new architecture. */
031254f2 3917 BFD_ASSERT (arch <= TAG_CPU_ARCH_V8_1M_MAIN);
60a019a0
TP		 3918
3919 return (arch == TAG_CPU_ARCH_V6T2
3920 || arch == TAG_CPU_ARCH_V7
3921 || arch == TAG_CPU_ARCH_V7E_M
3922 || arch == TAG_CPU_ARCH_V8
bff0500d 3923 || arch == TAG_CPU_ARCH_V8R
031254f2
AV		 3924 || arch == TAG_CPU_ARCH_V8M_MAIN
3925 || arch == TAG_CPU_ARCH_V8_1M_MAIN);
eed94f8f
NC		 3926}
3927
5e866f5a
TP		 3928/* Determine whether Thumb-2 BL instruction is available. */
3929
3930static bfd_boolean
3931using_thumb2_bl (struct elf32_arm_link_hash_table *globals)
3932{
3933 int arch =
3934 bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC, Tag_CPU_arch);
3935
3936 /* Force return logic to be reviewed for each new architecture. */
031254f2 3937 BFD_ASSERT (arch <= TAG_CPU_ARCH_V8_1M_MAIN);
5e866f5a
TP		 3938
3939 /* Architecture was introduced after ARMv6T2 (eg. ARMv6-M). */
3940 return (arch == TAG_CPU_ARCH_V6T2
3941 || arch >= TAG_CPU_ARCH_V7);
3942}
3943
00a97672
RS		 3944/* Create .plt, .rel(a).plt, .got, .got.plt, .rel(a).got, .dynbss, and
3945 .rel(a).bss sections in DYNOBJ, and set up shortcuts to them in our
5e681ec4
PB		 3946 hash table. */
3947
3948static bfd_boolean
57e8b36a 3949elf32_arm_create_dynamic_sections (bfd *dynobj, struct bfd_link_info *info)
5e681ec4
PB		 3950{
3951 struct elf32_arm_link_hash_table *htab;
3952
3953 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 3954 if (htab == NULL)
3955 return FALSE;
3956
362d30a1 3957 if (!htab->root.sgot && !create_got_section (dynobj, info))
5e681ec4
PB		 3958 return FALSE;
3959
3960 if (!_bfd_elf_create_dynamic_sections (dynobj, info))
3961 return FALSE;
3962
00a97672
RS		 3963 if (htab->vxworks_p)
3964 {
3965 if (!elf_vxworks_create_dynamic_sections (dynobj, info, &htab->srelplt2))
3966 return FALSE;
3967
0e1862bb 3968 if (bfd_link_pic (info))
00a97672
RS		 3969 {
3970 htab->plt_header_size = 0;
3971 htab->plt_entry_size
3972 = 4 * ARRAY_SIZE (elf32_arm_vxworks_shared_plt_entry);
3973 }
3974 else
3975 {
3976 htab->plt_header_size
3977 = 4 * ARRAY_SIZE (elf32_arm_vxworks_exec_plt0_entry);
3978 htab->plt_entry_size
3979 = 4 * ARRAY_SIZE (elf32_arm_vxworks_exec_plt_entry);
3980 }
aebf9be7
NC		 3981
3982 if (elf_elfheader (dynobj))
3983 elf_elfheader (dynobj)->e_ident[EI_CLASS] = ELFCLASS32;
00a97672 3984 }
eed94f8f
NC		 3985 else
3986 {
3987 /* PR ld/16017
3988 Test for thumb only architectures. Note - we cannot just call
3989 using_thumb_only() as the attributes in the output bfd have not been
3990 initialised at this point, so instead we use the input bfd. */
3991 bfd * saved_obfd = htab->obfd;
3992
3993 htab->obfd = dynobj;
3994 if (using_thumb_only (htab))
3995 {
3996 htab->plt_header_size = 4 * ARRAY_SIZE (elf32_thumb2_plt0_entry);
3997 htab->plt_entry_size = 4 * ARRAY_SIZE (elf32_thumb2_plt_entry);
3998 }
3999 htab->obfd = saved_obfd;
4000 }
5e681ec4 4001
7801f98f
CL		 4002 if (htab->fdpic_p) {
4003 htab->plt_header_size = 0;
4004 if (info->flags & DF_BIND_NOW)
4005 htab->plt_entry_size = 4 * (ARRAY_SIZE(elf32_arm_fdpic_plt_entry) - 5);
4006 else
4007 htab->plt_entry_size = 4 * ARRAY_SIZE(elf32_arm_fdpic_plt_entry);
4008 }
4009
362d30a1
RS		 4010 if (!htab->root.splt
4011 || !htab->root.srelplt
9d19e4fd
AM		 4012 || !htab->root.sdynbss
4013 || (!bfd_link_pic (info) && !htab->root.srelbss))
5e681ec4
PB		 4014 abort ();
4015
4016 return TRUE;
4017}
4018
906e58ca
NC		 4019/* Copy the extra info we tack onto an elf_link_hash_entry. */
4020
4021static void
4022elf32_arm_copy_indirect_symbol (struct bfd_link_info *info,
4023 struct elf_link_hash_entry *dir,
4024 struct elf_link_hash_entry *ind)
4025{
4026 struct elf32_arm_link_hash_entry *edir, *eind;
4027
4028 edir = (struct elf32_arm_link_hash_entry *) dir;
4029 eind = (struct elf32_arm_link_hash_entry *) ind;
4030
906e58ca
NC		 4031 if (ind->root.type == bfd_link_hash_indirect)
4032 {
4033 /* Copy over PLT info. */
34e77a92
RS		 4034 edir->plt.thumb_refcount += eind->plt.thumb_refcount;
4035 eind->plt.thumb_refcount = 0;
4036 edir->plt.maybe_thumb_refcount += eind->plt.maybe_thumb_refcount;
4037 eind->plt.maybe_thumb_refcount = 0;
4038 edir->plt.noncall_refcount += eind->plt.noncall_refcount;
4039 eind->plt.noncall_refcount = 0;
4040
e8b09b87
CL		 4041 /* Copy FDPIC counters. */
4042 edir->fdpic_cnts.gotofffuncdesc_cnt += eind->fdpic_cnts.gotofffuncdesc_cnt;
4043 edir->fdpic_cnts.gotfuncdesc_cnt += eind->fdpic_cnts.gotfuncdesc_cnt;
4044 edir->fdpic_cnts.funcdesc_cnt += eind->fdpic_cnts.funcdesc_cnt;
4045
34e77a92
RS		 4046 /* We should only allocate a function to .iplt once the final
4047 symbol information is known. */
4048 BFD_ASSERT (!eind->is_iplt);
906e58ca
NC		 4049
4050 if (dir->got.refcount <= 0)
4051 {
4052 edir->tls_type = eind->tls_type;
4053 eind->tls_type = GOT_UNKNOWN;
4054 }
4055 }
4056
4057 _bfd_elf_link_hash_copy_indirect (info, dir, ind);
4058}
4059
68faa637
AM		 4060/* Destroy an ARM elf linker hash table. */
4061
4062static void
d495ab0d 4063elf32_arm_link_hash_table_free (bfd *obfd)
68faa637
AM		 4064{
4065 struct elf32_arm_link_hash_table *ret
d495ab0d 4066 = (struct elf32_arm_link_hash_table *) obfd->link.hash;
68faa637
AM		 4067
4068 bfd_hash_table_free (&ret->stub_hash_table);
d495ab0d 4069 _bfd_elf_link_hash_table_free (obfd);
68faa637
AM		 4070}
4071
906e58ca
NC		 4072/* Create an ARM elf linker hash table. */
4073
4074static struct bfd_link_hash_table *
4075elf32_arm_link_hash_table_create (bfd *abfd)
4076{
4077 struct elf32_arm_link_hash_table *ret;
986f0783 4078 size_t amt = sizeof (struct elf32_arm_link_hash_table);
906e58ca 4079
7bf52ea2 4080 ret = (struct elf32_arm_link_hash_table *) bfd_zmalloc (amt);
906e58ca
NC		 4081 if (ret == NULL)
4082 return NULL;
4083
4084 if (!_bfd_elf_link_hash_table_init (& ret->root, abfd,
4085 elf32_arm_link_hash_newfunc,
4dfe6ac6
NC		 4086 sizeof (struct elf32_arm_link_hash_entry),
4087 ARM_ELF_DATA))
906e58ca
NC		 4088 {
4089 free (ret);
4090 return NULL;
4091 }
4092
906e58ca 4093 ret->vfp11_fix = BFD_ARM_VFP11_FIX_NONE;
a504d23a 4094 ret->stm32l4xx_fix = BFD_ARM_STM32L4XX_FIX_NONE;
906e58ca
NC		 4095#ifdef FOUR_WORD_PLT
4096 ret->plt_header_size = 16;
4097 ret->plt_entry_size = 16;
4098#else
4099 ret->plt_header_size = 20;
1db37fe6 4100 ret->plt_entry_size = elf32_arm_use_long_plt_entry ? 16 : 12;
906e58ca 4101#endif
f3185997 4102 ret->use_rel = TRUE;
906e58ca 4103 ret->obfd = abfd;
617a5ada 4104 ret->fdpic_p = 0;
906e58ca
NC		 4105
4106 if (!bfd_hash_table_init (&ret->stub_hash_table, stub_hash_newfunc,
4107 sizeof (struct elf32_arm_stub_hash_entry)))
4108 {
d495ab0d 4109 _bfd_elf_link_hash_table_free (abfd);
906e58ca
NC		 4110 return NULL;
4111 }
d495ab0d 4112 ret->root.root.hash_table_free = elf32_arm_link_hash_table_free;
906e58ca
NC		 4113
4114 return &ret->root.root;
4115}
4116
cd1dac3d
DG		 4117/* Determine what kind of NOPs are available. */
4118
4119static bfd_boolean
4120arch_has_arm_nop (struct elf32_arm_link_hash_table *globals)
4121{
4122 const int arch = bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC,
4123 Tag_CPU_arch);
cd1dac3d 4124
60a019a0 4125 /* Force return logic to be reviewed for each new architecture. */
031254f2 4126 BFD_ASSERT (arch <= TAG_CPU_ARCH_V8_1M_MAIN);
60a019a0
TP		 4127
4128 return (arch == TAG_CPU_ARCH_V6T2
4129 || arch == TAG_CPU_ARCH_V6K
4130 || arch == TAG_CPU_ARCH_V7
bff0500d
TP		 4131 || arch == TAG_CPU_ARCH_V8
4132 || arch == TAG_CPU_ARCH_V8R);
cd1dac3d
DG		 4133}
4134
f4ac8484
DJ		 4135static bfd_boolean
4136arm_stub_is_thumb (enum elf32_arm_stub_type stub_type)
4137{
4138 switch (stub_type)
4139 {
fea2b4d6 4140 case arm_stub_long_branch_thumb_only:
80c135e5 4141 case arm_stub_long_branch_thumb2_only:
d5a67c02 4142 case arm_stub_long_branch_thumb2_only_pure:
fea2b4d6
CL		 4143 case arm_stub_long_branch_v4t_thumb_arm:
4144 case arm_stub_short_branch_v4t_thumb_arm:
ebe24dd4 4145 case arm_stub_long_branch_v4t_thumb_arm_pic:
12352d3f 4146 case arm_stub_long_branch_v4t_thumb_tls_pic:
ebe24dd4 4147 case arm_stub_long_branch_thumb_only_pic:
4ba2ef8f 4148 case arm_stub_cmse_branch_thumb_only:
f4ac8484
DJ		 4149 return TRUE;
4150 case arm_stub_none:
4151 BFD_FAIL ();
4152 return FALSE;
4153 break;
4154 default:
4155 return FALSE;
4156 }
4157}
4158
906e58ca
NC		 4159/* Determine the type of stub needed, if any, for a call. */
4160
4161static enum elf32_arm_stub_type
4162arm_type_of_stub (struct bfd_link_info *info,
4163 asection *input_sec,
4164 const Elf_Internal_Rela *rel,
34e77a92 4165 unsigned char st_type,
35fc36a8 4166 enum arm_st_branch_type *actual_branch_type,
906e58ca 4167 struct elf32_arm_link_hash_entry *hash,
c820be07
NC		 4168 bfd_vma destination,
4169 asection *sym_sec,
4170 bfd *input_bfd,
4171 const char *name)
906e58ca
NC		 4172{
4173 bfd_vma location;
4174 bfd_signed_vma branch_offset;
4175 unsigned int r_type;
4176 struct elf32_arm_link_hash_table * globals;
5e866f5a 4177 bfd_boolean thumb2, thumb2_bl, thumb_only;
906e58ca 4178 enum elf32_arm_stub_type stub_type = arm_stub_none;
5fa9e92f 4179 int use_plt = 0;
35fc36a8 4180 enum arm_st_branch_type branch_type = *actual_branch_type;
34e77a92
RS		 4181 union gotplt_union *root_plt;
4182 struct arm_plt_info *arm_plt;
d5a67c02
AV		 4183 int arch;
4184 int thumb2_movw;
906e58ca 4185
35fc36a8 4186 if (branch_type == ST_BRANCH_LONG)
da5938a2
NC		 4187 return stub_type;
4188
906e58ca 4189 globals = elf32_arm_hash_table (info);
4dfe6ac6
NC		 4190 if (globals == NULL)
4191 return stub_type;
906e58ca
NC		 4192
4193 thumb_only = using_thumb_only (globals);
906e58ca 4194 thumb2 = using_thumb2 (globals);
5e866f5a 4195 thumb2_bl = using_thumb2_bl (globals);
906e58ca 4196
d5a67c02
AV		 4197 arch = bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC, Tag_CPU_arch);
4198
4199 /* True for architectures that implement the thumb2 movw instruction. */
4200 thumb2_movw = thumb2 || (arch == TAG_CPU_ARCH_V8M_BASE);
4201
906e58ca
NC		 4202 /* Determine where the call point is. */
4203 location = (input_sec->output_offset
4204 + input_sec->output_section->vma
4205 + rel->r_offset);
4206
906e58ca
NC		 4207 r_type = ELF32_R_TYPE (rel->r_info);
4208
39f21624
NC		 4209 /* ST_BRANCH_TO_ARM is nonsense to thumb-only targets when we
4210 are considering a function call relocation. */
c5423981 4211 if (thumb_only && (r_type == R_ARM_THM_CALL || r_type == R_ARM_THM_JUMP24
07d6d2b8 4212 || r_type == R_ARM_THM_JUMP19)
39f21624
NC		 4213 && branch_type == ST_BRANCH_TO_ARM)
4214 branch_type = ST_BRANCH_TO_THUMB;
4215
34e77a92
RS		 4216 /* For TLS call relocs, it is the caller's responsibility to provide
4217 the address of the appropriate trampoline. */
4218 if (r_type != R_ARM_TLS_CALL
4219 && r_type != R_ARM_THM_TLS_CALL
4ba2ef8f
TP		 4220 && elf32_arm_get_plt_info (input_bfd, globals, hash,
4221 ELF32_R_SYM (rel->r_info), &root_plt,
4222 &arm_plt)
34e77a92 4223 && root_plt->offset != (bfd_vma) -1)
5fa9e92f 4224 {
34e77a92 4225 asection *splt;
fe33d2fa 4226
34e77a92
RS		 4227 if (hash == NULL || hash->is_iplt)
4228 splt = globals->root.iplt;
4229 else
4230 splt = globals->root.splt;
4231 if (splt != NULL)
b38cadfb 4232 {
34e77a92
RS		 4233 use_plt = 1;
4234
4235 /* Note when dealing with PLT entries: the main PLT stub is in
4236 ARM mode, so if the branch is in Thumb mode, another
4237 Thumb->ARM stub will be inserted later just before the ARM
2df2751d
CL		 4238 PLT stub. If a long branch stub is needed, we'll add a
4239 Thumb->Arm one and branch directly to the ARM PLT entry.
4240 Here, we have to check if a pre-PLT Thumb->ARM stub
4241 is needed and if it will be close enough. */
34e77a92
RS		 4242
4243 destination = (splt->output_section->vma
4244 + splt->output_offset
4245 + root_plt->offset);
4246 st_type = STT_FUNC;
2df2751d
CL		 4247
4248 /* Thumb branch/call to PLT: it can become a branch to ARM
4249 or to Thumb. We must perform the same checks and
4250 corrections as in elf32_arm_final_link_relocate. */
4251 if ((r_type == R_ARM_THM_CALL)
4252 || (r_type == R_ARM_THM_JUMP24))
4253 {
4254 if (globals->use_blx
4255 && r_type == R_ARM_THM_CALL
4256 && !thumb_only)
4257 {
4258 /* If the Thumb BLX instruction is available, convert
4259 the BL to a BLX instruction to call the ARM-mode
4260 PLT entry. */
4261 branch_type = ST_BRANCH_TO_ARM;
4262 }
4263 else
4264 {
4265 if (!thumb_only)
4266 /* Target the Thumb stub before the ARM PLT entry. */
4267 destination -= PLT_THUMB_STUB_SIZE;
4268 branch_type = ST_BRANCH_TO_THUMB;
4269 }
4270 }
4271 else
4272 {
4273 branch_type = ST_BRANCH_TO_ARM;
4274 }
34e77a92 4275 }
5fa9e92f 4276 }
34e77a92
RS		 4277 /* Calls to STT_GNU_IFUNC symbols should go through a PLT. */
4278 BFD_ASSERT (st_type != STT_GNU_IFUNC);
906e58ca 4279
fe33d2fa
CL		 4280 branch_offset = (bfd_signed_vma)(destination - location);
4281
0855e32b 4282 if (r_type == R_ARM_THM_CALL || r_type == R_ARM_THM_JUMP24
c5423981 4283 || r_type == R_ARM_THM_TLS_CALL || r_type == R_ARM_THM_JUMP19)
906e58ca 4284 {
5fa9e92f
CL		 4285 /* Handle cases where:
4286 - this call goes too far (different Thumb/Thumb2 max
99059e56 4287 distance)
155d87d7 4288 - it's a Thumb->Arm call and blx is not available, or it's a
99059e56
RM		 4289 Thumb->Arm branch (not bl). A stub is needed in this case,
4290 but only if this call is not through a PLT entry. Indeed,
695344c0 4291 PLT stubs handle mode switching already. */
5e866f5a 4292 if ((!thumb2_bl
906e58ca
NC		 4293 && (branch_offset > THM_MAX_FWD_BRANCH_OFFSET
4294 || (branch_offset < THM_MAX_BWD_BRANCH_OFFSET)))
5e866f5a 4295 || (thumb2_bl
906e58ca
NC		 4296 && (branch_offset > THM2_MAX_FWD_BRANCH_OFFSET
4297 || (branch_offset < THM2_MAX_BWD_BRANCH_OFFSET)))
c5423981
TG		 4298 || (thumb2
4299 && (branch_offset > THM2_MAX_FWD_COND_BRANCH_OFFSET
4300 || (branch_offset < THM2_MAX_BWD_COND_BRANCH_OFFSET))
4301 && (r_type == R_ARM_THM_JUMP19))
35fc36a8 4302 || (branch_type == ST_BRANCH_TO_ARM
0855e32b
NS		 4303 && (((r_type == R_ARM_THM_CALL
4304 || r_type == R_ARM_THM_TLS_CALL) && !globals->use_blx)
c5423981 4305 || (r_type == R_ARM_THM_JUMP24)
07d6d2b8 4306 || (r_type == R_ARM_THM_JUMP19))
5fa9e92f 4307 && !use_plt))
906e58ca 4308 {
2df2751d
CL		 4309 /* If we need to insert a Thumb-Thumb long branch stub to a
4310 PLT, use one that branches directly to the ARM PLT
4311 stub. If we pretended we'd use the pre-PLT Thumb->ARM
4312 stub, undo this now. */
695344c0
NC		 4313 if ((branch_type == ST_BRANCH_TO_THUMB) && use_plt && !thumb_only)
4314 {
4315 branch_type = ST_BRANCH_TO_ARM;
4316 branch_offset += PLT_THUMB_STUB_SIZE;
4317 }
2df2751d 4318
35fc36a8 4319 if (branch_type == ST_BRANCH_TO_THUMB)
906e58ca
NC		 4320 {
4321 /* Thumb to thumb. */
4322 if (!thumb_only)
4323 {
d5a67c02 4324 if (input_sec->flags & SEC_ELF_PURECODE)
10463f39 4325 _bfd_error_handler
871b3ab2 4326 (_("%pB(%pA): warning: long branch veneers used in"
10463f39
AM		 4327 " section with SHF_ARM_PURECODE section"
4328 " attribute is only supported for M-profile"
90b6238f 4329 " targets that implement the movw instruction"),
10463f39 4330 input_bfd, input_sec);
d5a67c02 4331
0e1862bb 4332 stub_type = (bfd_link_pic (info) | globals->pic_veneer)
c2b4a39d 4333 /* PIC stubs. */
155d87d7 4334 ? ((globals->use_blx
9553db3c 4335 && (r_type == R_ARM_THM_CALL))
155d87d7
CL		 4336 /* V5T and above. Stub starts with ARM code, so
4337 we must be able to switch mode before
4338 reaching it, which is only possible for 'bl'
4339 (ie R_ARM_THM_CALL relocation). */
cf3eccff 4340 ? arm_stub_long_branch_any_thumb_pic
ebe24dd4 4341 /* On V4T, use Thumb code only. */
d3626fb0 4342 : arm_stub_long_branch_v4t_thumb_thumb_pic)
c2b4a39d
CL		 4343
4344 /* non-PIC stubs. */
155d87d7 4345 : ((globals->use_blx
9553db3c 4346 && (r_type == R_ARM_THM_CALL))
c2b4a39d
CL		 4347 /* V5T and above. */
4348 ? arm_stub_long_branch_any_any
4349 /* V4T. */
d3626fb0 4350 : arm_stub_long_branch_v4t_thumb_thumb);
906e58ca
NC		 4351 }
4352 else
4353 {
d5a67c02
AV		 4354 if (thumb2_movw && (input_sec->flags & SEC_ELF_PURECODE))
4355 stub_type = arm_stub_long_branch_thumb2_only_pure;
4356 else
4357 {
4358 if (input_sec->flags & SEC_ELF_PURECODE)
10463f39 4359 _bfd_error_handler
871b3ab2 4360 (_("%pB(%pA): warning: long branch veneers used in"
10463f39
AM		 4361 " section with SHF_ARM_PURECODE section"
4362 " attribute is only supported for M-profile"
90b6238f 4363 " targets that implement the movw instruction"),
10463f39 4364 input_bfd, input_sec);
d5a67c02
AV		 4365
4366 stub_type = (bfd_link_pic (info) | globals->pic_veneer)
4367 /* PIC stub. */
4368 ? arm_stub_long_branch_thumb_only_pic
4369 /* non-PIC stub. */
4370 : (thumb2 ? arm_stub_long_branch_thumb2_only
4371 : arm_stub_long_branch_thumb_only);
4372 }
906e58ca
NC		 4373 }
4374 }
4375 else
4376 {
d5a67c02 4377 if (input_sec->flags & SEC_ELF_PURECODE)
10463f39 4378 _bfd_error_handler
871b3ab2 4379 (_("%pB(%pA): warning: long branch veneers used in"
10463f39
AM		 4380 " section with SHF_ARM_PURECODE section"
4381 " attribute is only supported" " for M-profile"
90b6238f 4382 " targets that implement the movw instruction"),
10463f39 4383 input_bfd, input_sec);
d5a67c02 4384
906e58ca 4385 /* Thumb to arm. */
c820be07
NC		 4386 if (sym_sec != NULL
4387 && sym_sec->owner != NULL
4388 && !INTERWORK_FLAG (sym_sec->owner))
4389 {
4eca0228 4390 _bfd_error_handler
90b6238f
AM		 4391 (_("%pB(%s): warning: interworking not enabled;"
4392 " first occurrence: %pB: %s call to %s"),
4393 sym_sec->owner, name, input_bfd, "Thumb", "ARM");
c820be07
NC		 4394 }
4395
0855e32b 4396 stub_type =
0e1862bb 4397 (bfd_link_pic (info) | globals->pic_veneer)
c2b4a39d 4398 /* PIC stubs. */
0855e32b 4399 ? (r_type == R_ARM_THM_TLS_CALL
6a631e86 4400 /* TLS PIC stubs. */
0855e32b
NS		 4401 ? (globals->use_blx ? arm_stub_long_branch_any_tls_pic
4402 : arm_stub_long_branch_v4t_thumb_tls_pic)
4403 : ((globals->use_blx && r_type == R_ARM_THM_CALL)
4404 /* V5T PIC and above. */
4405 ? arm_stub_long_branch_any_arm_pic
4406 /* V4T PIC stub. */
4407 : arm_stub_long_branch_v4t_thumb_arm_pic))
c2b4a39d
CL		 4408
4409 /* non-PIC stubs. */
0855e32b 4410 : ((globals->use_blx && r_type == R_ARM_THM_CALL)
c2b4a39d
CL		 4411 /* V5T and above. */
4412 ? arm_stub_long_branch_any_any
4413 /* V4T. */
4414 : arm_stub_long_branch_v4t_thumb_arm);
c820be07
NC		 4415
4416 /* Handle v4t short branches. */
fea2b4d6 4417 if ((stub_type == arm_stub_long_branch_v4t_thumb_arm)
c820be07
NC		 4418 && (branch_offset <= THM_MAX_FWD_BRANCH_OFFSET)
4419 && (branch_offset >= THM_MAX_BWD_BRANCH_OFFSET))
fea2b4d6 4420 stub_type = arm_stub_short_branch_v4t_thumb_arm;
906e58ca
NC		 4421 }
4422 }
4423 }
fe33d2fa
CL		 4424 else if (r_type == R_ARM_CALL
4425 || r_type == R_ARM_JUMP24
0855e32b
NS		 4426 || r_type == R_ARM_PLT32
4427 || r_type == R_ARM_TLS_CALL)
906e58ca 4428 {
d5a67c02 4429 if (input_sec->flags & SEC_ELF_PURECODE)
10463f39 4430 _bfd_error_handler
871b3ab2 4431 (_("%pB(%pA): warning: long branch veneers used in"
10463f39
AM		 4432 " section with SHF_ARM_PURECODE section"
4433 " attribute is only supported for M-profile"
90b6238f 4434 " targets that implement the movw instruction"),
10463f39 4435 input_bfd, input_sec);
35fc36a8 4436 if (branch_type == ST_BRANCH_TO_THUMB)
906e58ca
NC		 4437 {
4438 /* Arm to thumb. */
c820be07
NC		 4439
4440 if (sym_sec != NULL
4441 && sym_sec->owner != NULL
4442 && !INTERWORK_FLAG (sym_sec->owner))
4443 {
4eca0228 4444 _bfd_error_handler
90b6238f
AM		 4445 (_("%pB(%s): warning: interworking not enabled;"
4446 " first occurrence: %pB: %s call to %s"),
4447 sym_sec->owner, name, input_bfd, "ARM", "Thumb");
c820be07
NC		 4448 }
4449
4450 /* We have an extra 2-bytes reach because of
4451 the mode change (bit 24 (H) of BLX encoding). */
4116d8d7
PB		 4452 if (branch_offset > (ARM_MAX_FWD_BRANCH_OFFSET + 2)
4453 || (branch_offset < ARM_MAX_BWD_BRANCH_OFFSET)
0855e32b 4454 || (r_type == R_ARM_CALL && !globals->use_blx)
4116d8d7
PB		 4455 || (r_type == R_ARM_JUMP24)
4456 || (r_type == R_ARM_PLT32))
906e58ca 4457 {
0e1862bb 4458 stub_type = (bfd_link_pic (info) | globals->pic_veneer)
c2b4a39d 4459 /* PIC stubs. */
ebe24dd4
CL		 4460 ? ((globals->use_blx)
4461 /* V5T and above. */
4462 ? arm_stub_long_branch_any_thumb_pic
4463 /* V4T stub. */
4464 : arm_stub_long_branch_v4t_arm_thumb_pic)
4465
c2b4a39d
CL		 4466 /* non-PIC stubs. */
4467 : ((globals->use_blx)
4468 /* V5T and above. */
4469 ? arm_stub_long_branch_any_any
4470 /* V4T. */
4471 : arm_stub_long_branch_v4t_arm_thumb);
906e58ca
NC		 4472 }
4473 }
4474 else
4475 {
4476 /* Arm to arm. */
4477 if (branch_offset > ARM_MAX_FWD_BRANCH_OFFSET
4478 || (branch_offset < ARM_MAX_BWD_BRANCH_OFFSET))
4479 {
0855e32b 4480 stub_type =
0e1862bb 4481 (bfd_link_pic (info) | globals->pic_veneer)
c2b4a39d 4482 /* PIC stubs. */
0855e32b 4483 ? (r_type == R_ARM_TLS_CALL
6a631e86 4484 /* TLS PIC Stub. */
0855e32b 4485 ? arm_stub_long_branch_any_tls_pic
7a89b94e
NC		 4486 : (globals->nacl_p
4487 ? arm_stub_long_branch_arm_nacl_pic
4488 : arm_stub_long_branch_any_arm_pic))
c2b4a39d 4489 /* non-PIC stubs. */
7a89b94e
NC		 4490 : (globals->nacl_p
4491 ? arm_stub_long_branch_arm_nacl
4492 : arm_stub_long_branch_any_any);
906e58ca
NC		 4493 }
4494 }
4495 }
4496
fe33d2fa
CL		 4497 /* If a stub is needed, record the actual destination type. */
4498 if (stub_type != arm_stub_none)
35fc36a8 4499 *actual_branch_type = branch_type;
fe33d2fa 4500
906e58ca
NC		 4501 return stub_type;
4502}
4503
4504/* Build a name for an entry in the stub hash table. */
4505
4506static char *
4507elf32_arm_stub_name (const asection *input_section,
4508 const asection *sym_sec,
4509 const struct elf32_arm_link_hash_entry *hash,
fe33d2fa
CL		 4510 const Elf_Internal_Rela *rel,
4511 enum elf32_arm_stub_type stub_type)
906e58ca
NC		 4512{
4513 char *stub_name;
4514 bfd_size_type len;
4515
4516 if (hash)
4517 {
fe33d2fa 4518 len = 8 + 1 + strlen (hash->root.root.root.string) + 1 + 8 + 1 + 2 + 1;
21d799b5 4519 stub_name = (char *) bfd_malloc (len);
906e58ca 4520 if (stub_name != NULL)
fe33d2fa 4521 sprintf (stub_name, "%08x_%s+%x_%d",
906e58ca
NC		 4522 input_section->id & 0xffffffff,
4523 hash->root.root.root.string,
fe33d2fa
CL		 4524 (int) rel->r_addend & 0xffffffff,
4525 (int) stub_type);
906e58ca
NC		 4526 }
4527 else
4528 {
fe33d2fa 4529 len = 8 + 1 + 8 + 1 + 8 + 1 + 8 + 1 + 2 + 1;
21d799b5 4530 stub_name = (char *) bfd_malloc (len);
906e58ca 4531 if (stub_name != NULL)
fe33d2fa 4532 sprintf (stub_name, "%08x_%x:%x+%x_%d",
906e58ca
NC		 4533 input_section->id & 0xffffffff,
4534 sym_sec->id & 0xffffffff,
0855e32b
NS		 4535 ELF32_R_TYPE (rel->r_info) == R_ARM_TLS_CALL
4536 || ELF32_R_TYPE (rel->r_info) == R_ARM_THM_TLS_CALL
4537 ? 0 : (int) ELF32_R_SYM (rel->r_info) & 0xffffffff,
fe33d2fa
CL		 4538 (int) rel->r_addend & 0xffffffff,
4539 (int) stub_type);
906e58ca
NC		 4540 }
4541
4542 return stub_name;
4543}
4544
4545/* Look up an entry in the stub hash. Stub entries are cached because
4546 creating the stub name takes a bit of time. */
4547
4548static struct elf32_arm_stub_hash_entry *
4549elf32_arm_get_stub_entry (const asection *input_section,
4550 const asection *sym_sec,
4551 struct elf_link_hash_entry *hash,
4552 const Elf_Internal_Rela *rel,
fe33d2fa
CL		 4553 struct elf32_arm_link_hash_table *htab,
4554 enum elf32_arm_stub_type stub_type)
906e58ca
NC		 4555{
4556 struct elf32_arm_stub_hash_entry *stub_entry;
4557 struct elf32_arm_link_hash_entry *h = (struct elf32_arm_link_hash_entry *) hash;
4558 const asection *id_sec;
4559
4560 if ((input_section->flags & SEC_CODE) == 0)
4561 return NULL;
4562
4d83e8d9
CL		 4563 /* If the input section is the CMSE stubs one and it needs a long
4564 branch stub to reach it's final destination, give up with an
4565 error message: this is not supported. See PR ld/24709. */
4566 if (!strncmp (input_section->name, CMSE_STUB_NAME, strlen(CMSE_STUB_NAME)))
4567 {
4568 bfd *output_bfd = htab->obfd;
4569 asection *out_sec = bfd_get_section_by_name (output_bfd, CMSE_STUB_NAME);
4570
4571 _bfd_error_handler (_("ERROR: CMSE stub (%s section) too far "
4572 "(%#" PRIx64 ") from destination (%#" PRIx64 ")"),
4573 CMSE_STUB_NAME,
4574 (uint64_t)out_sec->output_section->vma
4575 + out_sec->output_offset,
4576 (uint64_t)sym_sec->output_section->vma
4577 + sym_sec->output_offset
4578 + h->root.root.u.def.value);
4579 /* Exit, rather than leave incompletely processed
4580 relocations. */
4581 xexit(1);
4582 }
4583
906e58ca
NC		 4584 /* If this input section is part of a group of sections sharing one
4585 stub section, then use the id of the first section in the group.
4586 Stub names need to include a section id, as there may well be
4587 more than one stub used to reach say, printf, and we need to
4588 distinguish between them. */
c2abbbeb 4589 BFD_ASSERT (input_section->id <= htab->top_id);
906e58ca
NC		 4590 id_sec = htab->stub_group[input_section->id].link_sec;
4591
4592 if (h != NULL && h->stub_cache != NULL
4593 && h->stub_cache->h == h
fe33d2fa
CL		 4594 && h->stub_cache->id_sec == id_sec
4595 && h->stub_cache->stub_type == stub_type)
906e58ca
NC		 4596 {
4597 stub_entry = h->stub_cache;
4598 }
4599 else
4600 {
4601 char *stub_name;
4602
fe33d2fa 4603 stub_name = elf32_arm_stub_name (id_sec, sym_sec, h, rel, stub_type);
906e58ca
NC		 4604 if (stub_name == NULL)
4605 return NULL;
4606
4607 stub_entry = arm_stub_hash_lookup (&htab->stub_hash_table,
4608 stub_name, FALSE, FALSE);
4609 if (h != NULL)
4610 h->stub_cache = stub_entry;
4611
4612 free (stub_name);
4613 }
4614
4615 return stub_entry;
4616}
4617
daa4adae
TP		 4618/* Whether veneers of type STUB_TYPE require to be in a dedicated output
4619 section. */
4620
4621static bfd_boolean
4622arm_dedicated_stub_output_section_required (enum elf32_arm_stub_type stub_type)
4623{
4624 if (stub_type >= max_stub_type)
4625 abort (); /* Should be unreachable. */
4626
4ba2ef8f
TP		 4627 switch (stub_type)
4628 {
4629 case arm_stub_cmse_branch_thumb_only:
4630 return TRUE;
4631
4632 default:
4633 return FALSE;
4634 }
4635
4636 abort (); /* Should be unreachable. */
daa4adae
TP		 4637}
4638
4639/* Required alignment (as a power of 2) for the dedicated section holding
4640 veneers of type STUB_TYPE, or 0 if veneers of this type are interspersed
4641 with input sections. */
4642
4643static int
4644arm_dedicated_stub_output_section_required_alignment
4645 (enum elf32_arm_stub_type stub_type)
4646{
4647 if (stub_type >= max_stub_type)
4648 abort (); /* Should be unreachable. */
4649
4ba2ef8f
TP		 4650 switch (stub_type)
4651 {
4652 /* Vectors of Secure Gateway veneers must be aligned on 32byte
4653 boundary. */
4654 case arm_stub_cmse_branch_thumb_only:
4655 return 5;
4656
4657 default:
4658 BFD_ASSERT (!arm_dedicated_stub_output_section_required (stub_type));
4659 return 0;
4660 }
4661
4662 abort (); /* Should be unreachable. */
daa4adae
TP		 4663}
4664
4665/* Name of the dedicated output section to put veneers of type STUB_TYPE, or
4666 NULL if veneers of this type are interspersed with input sections. */
4667
4668static const char *
4669arm_dedicated_stub_output_section_name (enum elf32_arm_stub_type stub_type)
4670{
4671 if (stub_type >= max_stub_type)
4672 abort (); /* Should be unreachable. */
4673
4ba2ef8f
TP		 4674 switch (stub_type)
4675 {
4676 case arm_stub_cmse_branch_thumb_only:
4d83e8d9 4677 return CMSE_STUB_NAME;
4ba2ef8f
TP		 4678
4679 default:
4680 BFD_ASSERT (!arm_dedicated_stub_output_section_required (stub_type));
4681 return NULL;
4682 }
4683
4684 abort (); /* Should be unreachable. */
daa4adae
TP		 4685}
4686
4687/* If veneers of type STUB_TYPE should go in a dedicated output section,
4688 returns the address of the hash table field in HTAB holding a pointer to the
4689 corresponding input section. Otherwise, returns NULL. */
4690
4691static asection **
4ba2ef8f
TP		 4692arm_dedicated_stub_input_section_ptr (struct elf32_arm_link_hash_table *htab,
4693 enum elf32_arm_stub_type stub_type)
daa4adae
TP		 4694{
4695 if (stub_type >= max_stub_type)
4696 abort (); /* Should be unreachable. */
4697
4ba2ef8f
TP		 4698 switch (stub_type)
4699 {
4700 case arm_stub_cmse_branch_thumb_only:
4701 return &htab->cmse_stub_sec;
4702
4703 default:
4704 BFD_ASSERT (!arm_dedicated_stub_output_section_required (stub_type));
4705 return NULL;
4706 }
4707
4708 abort (); /* Should be unreachable. */
daa4adae
TP		 4709}
4710
4711/* Find or create a stub section to contain a stub of type STUB_TYPE. SECTION
4712 is the section that branch into veneer and can be NULL if stub should go in
4713 a dedicated output section. Returns a pointer to the stub section, and the
4714 section to which the stub section will be attached (in *LINK_SEC_P).
48229727 4715 LINK_SEC_P may be NULL. */
906e58ca 4716
48229727
JB		 4717static asection *
4718elf32_arm_create_or_find_stub_sec (asection **link_sec_p, asection *section,
daa4adae
TP		 4719 struct elf32_arm_link_hash_table *htab,
4720 enum elf32_arm_stub_type stub_type)
906e58ca 4721{
daa4adae
TP		 4722 asection *link_sec, *out_sec, **stub_sec_p;
4723 const char *stub_sec_prefix;
4724 bfd_boolean dedicated_output_section =
4725 arm_dedicated_stub_output_section_required (stub_type);
4726 int align;
906e58ca 4727
daa4adae 4728 if (dedicated_output_section)
906e58ca 4729 {
daa4adae
TP		 4730 bfd *output_bfd = htab->obfd;
4731 const char *out_sec_name =
4732 arm_dedicated_stub_output_section_name (stub_type);
4733 link_sec = NULL;
4734 stub_sec_p = arm_dedicated_stub_input_section_ptr (htab, stub_type);
4735 stub_sec_prefix = out_sec_name;
4736 align = arm_dedicated_stub_output_section_required_alignment (stub_type);
4737 out_sec = bfd_get_section_by_name (output_bfd, out_sec_name);
4738 if (out_sec == NULL)
906e58ca 4739 {
90b6238f 4740 _bfd_error_handler (_("no address assigned to the veneers output "
4eca0228 4741 "section %s"), out_sec_name);
daa4adae 4742 return NULL;
906e58ca 4743 }
daa4adae
TP		 4744 }
4745 else
4746 {
c2abbbeb 4747 BFD_ASSERT (section->id <= htab->top_id);
daa4adae
TP		 4748 link_sec = htab->stub_group[section->id].link_sec;
4749 BFD_ASSERT (link_sec != NULL);
4750 stub_sec_p = &htab->stub_group[section->id].stub_sec;
4751 if (*stub_sec_p == NULL)
4752 stub_sec_p = &htab->stub_group[link_sec->id].stub_sec;
4753 stub_sec_prefix = link_sec->name;
4754 out_sec = link_sec->output_section;
4755 align = htab->nacl_p ? 4 : 3;
906e58ca 4756 }
b38cadfb 4757
daa4adae
TP		 4758 if (*stub_sec_p == NULL)
4759 {
4760 size_t namelen;
4761 bfd_size_type len;
4762 char *s_name;
4763
4764 namelen = strlen (stub_sec_prefix);
4765 len = namelen + sizeof (STUB_SUFFIX);
4766 s_name = (char *) bfd_alloc (htab->stub_bfd, len);
4767 if (s_name == NULL)
4768 return NULL;
4769
4770 memcpy (s_name, stub_sec_prefix, namelen);
4771 memcpy (s_name + namelen, STUB_SUFFIX, sizeof (STUB_SUFFIX));
4772 *stub_sec_p = (*htab->add_stub_section) (s_name, out_sec, link_sec,
4773 align);
4774 if (*stub_sec_p == NULL)
4775 return NULL;
4776
4777 out_sec->flags |= SEC_ALLOC | SEC_LOAD | SEC_READONLY | SEC_CODE
4778 | SEC_HAS_CONTENTS | SEC_RELOC | SEC_IN_MEMORY
4779 | SEC_KEEP;
4780 }
4781
4782 if (!dedicated_output_section)
4783 htab->stub_group[section->id].stub_sec = *stub_sec_p;
4784
48229727
JB		 4785 if (link_sec_p)
4786 *link_sec_p = link_sec;
b38cadfb 4787
daa4adae 4788 return *stub_sec_p;
48229727
JB		 4789}
4790
4791/* Add a new stub entry to the stub hash. Not all fields of the new
4792 stub entry are initialised. */
4793
4794static struct elf32_arm_stub_hash_entry *
daa4adae
TP		 4795elf32_arm_add_stub (const char *stub_name, asection *section,
4796 struct elf32_arm_link_hash_table *htab,
4797 enum elf32_arm_stub_type stub_type)
48229727
JB		 4798{
4799 asection *link_sec;
4800 asection *stub_sec;
4801 struct elf32_arm_stub_hash_entry *stub_entry;
4802
daa4adae
TP		 4803 stub_sec = elf32_arm_create_or_find_stub_sec (&link_sec, section, htab,
4804 stub_type);
48229727
JB		 4805 if (stub_sec == NULL)
4806 return NULL;
906e58ca
NC		 4807
4808 /* Enter this entry into the linker stub hash table. */
4809 stub_entry = arm_stub_hash_lookup (&htab->stub_hash_table, stub_name,
4810 TRUE, FALSE);
4811 if (stub_entry == NULL)
4812 {
6bde4c52
TP		 4813 if (section == NULL)
4814 section = stub_sec;
871b3ab2 4815 _bfd_error_handler (_("%pB: cannot create stub entry %s"),
4eca0228 4816 section->owner, stub_name);
906e58ca
NC		 4817 return NULL;
4818 }
4819
4820 stub_entry->stub_sec = stub_sec;
0955507f 4821 stub_entry->stub_offset = (bfd_vma) -1;
906e58ca
NC		 4822 stub_entry->id_sec = link_sec;
4823
906e58ca
NC		 4824 return stub_entry;
4825}
4826
4827/* Store an Arm insn into an output section not processed by
4828 elf32_arm_write_section. */
4829
4830static void
8029a119
NC		 4831put_arm_insn (struct elf32_arm_link_hash_table * htab,
4832 bfd * output_bfd, bfd_vma val, void * ptr)
906e58ca
NC		 4833{
4834 if (htab->byteswap_code != bfd_little_endian (output_bfd))
4835 bfd_putl32 (val, ptr);
4836 else
4837 bfd_putb32 (val, ptr);
4838}
4839
4840/* Store a 16-bit Thumb insn into an output section not processed by
4841 elf32_arm_write_section. */
4842
4843static void
8029a119
NC		 4844put_thumb_insn (struct elf32_arm_link_hash_table * htab,
4845 bfd * output_bfd, bfd_vma val, void * ptr)
906e58ca
NC		 4846{
4847 if (htab->byteswap_code != bfd_little_endian (output_bfd))
4848 bfd_putl16 (val, ptr);
4849 else
4850 bfd_putb16 (val, ptr);
4851}
4852
a504d23a
LA		 4853/* Store a Thumb2 insn into an output section not processed by
4854 elf32_arm_write_section. */
4855
4856static void
4857put_thumb2_insn (struct elf32_arm_link_hash_table * htab,
b98e6871 4858 bfd * output_bfd, bfd_vma val, bfd_byte * ptr)
a504d23a
LA		 4859{
4860 /* T2 instructions are 16-bit streamed. */
4861 if (htab->byteswap_code != bfd_little_endian (output_bfd))
4862 {
4863 bfd_putl16 ((val >> 16) & 0xffff, ptr);
4864 bfd_putl16 ((val & 0xffff), ptr + 2);
4865 }
4866 else
4867 {
4868 bfd_putb16 ((val >> 16) & 0xffff, ptr);
4869 bfd_putb16 ((val & 0xffff), ptr + 2);
4870 }
4871}
4872
0855e32b
NS		 4873/* If it's possible to change R_TYPE to a more efficient access
4874 model, return the new reloc type. */
4875
4876static unsigned
b38cadfb 4877elf32_arm_tls_transition (struct bfd_link_info *info, int r_type,
0855e32b
NS		 4878 struct elf_link_hash_entry *h)
4879{
4880 int is_local = (h == NULL);
4881
9cb09e33 4882 if (bfd_link_dll (info)
0e1862bb 4883 || (h && h->root.type == bfd_link_hash_undefweak))
0855e32b
NS		 4884 return r_type;
4885
b38cadfb 4886 /* We do not support relaxations for Old TLS models. */
0855e32b
NS		 4887 switch (r_type)
4888 {
4889 case R_ARM_TLS_GOTDESC:
4890 case R_ARM_TLS_CALL:
4891 case R_ARM_THM_TLS_CALL:
4892 case R_ARM_TLS_DESCSEQ:
4893 case R_ARM_THM_TLS_DESCSEQ:
4894 return is_local ? R_ARM_TLS_LE32 : R_ARM_TLS_IE32;
4895 }
4896
4897 return r_type;
4898}
4899
48229727
JB		 4900static bfd_reloc_status_type elf32_arm_final_link_relocate
4901 (reloc_howto_type *, bfd *, bfd *, asection *, bfd_byte *,
4902 Elf_Internal_Rela *, bfd_vma, struct bfd_link_info *, asection *,
34e77a92
RS		 4903 const char *, unsigned char, enum arm_st_branch_type,
4904 struct elf_link_hash_entry *, bfd_boolean *, char **);
48229727 4905
4563a860
JB		 4906static unsigned int
4907arm_stub_required_alignment (enum elf32_arm_stub_type stub_type)
4908{
4909 switch (stub_type)
4910 {
4911 case arm_stub_a8_veneer_b_cond:
4912 case arm_stub_a8_veneer_b:
4913 case arm_stub_a8_veneer_bl:
4914 return 2;
4915
4916 case arm_stub_long_branch_any_any:
4917 case arm_stub_long_branch_v4t_arm_thumb:
4918 case arm_stub_long_branch_thumb_only:
80c135e5 4919 case arm_stub_long_branch_thumb2_only:
d5a67c02 4920 case arm_stub_long_branch_thumb2_only_pure:
4563a860
JB		 4921 case arm_stub_long_branch_v4t_thumb_thumb:
4922 case arm_stub_long_branch_v4t_thumb_arm:
4923 case arm_stub_short_branch_v4t_thumb_arm:
4924 case arm_stub_long_branch_any_arm_pic:
4925 case arm_stub_long_branch_any_thumb_pic:
4926 case arm_stub_long_branch_v4t_thumb_thumb_pic:
4927 case arm_stub_long_branch_v4t_arm_thumb_pic:
4928 case arm_stub_long_branch_v4t_thumb_arm_pic:
4929 case arm_stub_long_branch_thumb_only_pic:
0855e32b
NS		 4930 case arm_stub_long_branch_any_tls_pic:
4931 case arm_stub_long_branch_v4t_thumb_tls_pic:
4ba2ef8f 4932 case arm_stub_cmse_branch_thumb_only:
4563a860
JB		 4933 case arm_stub_a8_veneer_blx:
4934 return 4;
b38cadfb 4935
7a89b94e
NC		 4936 case arm_stub_long_branch_arm_nacl:
4937 case arm_stub_long_branch_arm_nacl_pic:
4938 return 16;
4939
4563a860
JB		 4940 default:
4941 abort (); /* Should be unreachable. */
4942 }
4943}
4944
4f4faa4d
TP		 4945/* Returns whether stubs of type STUB_TYPE take over the symbol they are
4946 veneering (TRUE) or have their own symbol (FALSE). */
4947
4948static bfd_boolean
4949arm_stub_sym_claimed (enum elf32_arm_stub_type stub_type)
4950{
4951 if (stub_type >= max_stub_type)
4952 abort (); /* Should be unreachable. */
4953
4ba2ef8f
TP		 4954 switch (stub_type)
4955 {
4956 case arm_stub_cmse_branch_thumb_only:
4957 return TRUE;
4958
4959 default:
4960 return FALSE;
4961 }
4962
4963 abort (); /* Should be unreachable. */
4f4faa4d
TP		 4964}
4965
d7c5bd02
TP		 4966/* Returns the padding needed for the dedicated section used stubs of type
4967 STUB_TYPE. */
4968
4969static int
4970arm_dedicated_stub_section_padding (enum elf32_arm_stub_type stub_type)
4971{
4972 if (stub_type >= max_stub_type)
4973 abort (); /* Should be unreachable. */
4974
4ba2ef8f
TP		 4975 switch (stub_type)
4976 {
4977 case arm_stub_cmse_branch_thumb_only:
4978 return 32;
4979
4980 default:
4981 return 0;
4982 }
4983
4984 abort (); /* Should be unreachable. */
d7c5bd02
TP		 4985}
4986
0955507f
TP		 4987/* If veneers of type STUB_TYPE should go in a dedicated output section,
4988 returns the address of the hash table field in HTAB holding the offset at
4989 which new veneers should be layed out in the stub section. */
4990
4991static bfd_vma*
4992arm_new_stubs_start_offset_ptr (struct elf32_arm_link_hash_table *htab,
4993 enum elf32_arm_stub_type stub_type)
4994{
4995 switch (stub_type)
4996 {
4997 case arm_stub_cmse_branch_thumb_only:
4998 return &htab->new_cmse_stub_offset;
4999
5000 default:
5001 BFD_ASSERT (!arm_dedicated_stub_output_section_required (stub_type));
5002 return NULL;
5003 }
5004}
5005
906e58ca
NC		 5006static bfd_boolean
5007arm_build_one_stub (struct bfd_hash_entry *gen_entry,
5008 void * in_arg)
5009{
7a89b94e 5010#define MAXRELOCS 3
0955507f 5011 bfd_boolean removed_sg_veneer;
906e58ca 5012 struct elf32_arm_stub_hash_entry *stub_entry;
4dfe6ac6 5013 struct elf32_arm_link_hash_table *globals;
906e58ca 5014 struct bfd_link_info *info;
906e58ca
NC		 5015 asection *stub_sec;
5016 bfd *stub_bfd;
906e58ca
NC		 5017 bfd_byte *loc;
5018 bfd_vma sym_value;
5019 int template_size;
5020 int size;
d3ce72d0 5021 const insn_sequence *template_sequence;
906e58ca 5022 int i;
48229727
JB		 5023 int stub_reloc_idx[MAXRELOCS] = {-1, -1};
5024 int stub_reloc_offset[MAXRELOCS] = {0, 0};
5025 int nrelocs = 0;
0955507f 5026 int just_allocated = 0;
906e58ca
NC		 5027
5028 /* Massage our args to the form they really have. */
5029 stub_entry = (struct elf32_arm_stub_hash_entry *) gen_entry;
5030 info = (struct bfd_link_info *) in_arg;
5031
abf874aa
CL		 5032 /* Fail if the target section could not be assigned to an output
5033 section. The user should fix his linker script. */
5034 if (stub_entry->target_section->output_section == NULL
5035 && info->non_contiguous_regions)
53215f21
CL		 5036 info->callbacks->einfo (_("%F%P: Could not assign '%pA' to an output section. "
5037 "Retry without --enable-non-contiguous-regions.\n"),
5038 stub_entry->target_section);
abf874aa 5039
906e58ca 5040 globals = elf32_arm_hash_table (info);
4dfe6ac6
NC		 5041 if (globals == NULL)
5042 return FALSE;
906e58ca 5043
906e58ca
NC		 5044 stub_sec = stub_entry->stub_sec;
5045
4dfe6ac6 5046 if ((globals->fix_cortex_a8 < 0)
4563a860
JB		 5047 != (arm_stub_required_alignment (stub_entry->stub_type) == 2))
5048 /* We have to do less-strictly-aligned fixes last. */
eb7c4339 5049 return TRUE;
fe33d2fa 5050
0955507f
TP		 5051 /* Assign a slot at the end of section if none assigned yet. */
5052 if (stub_entry->stub_offset == (bfd_vma) -1)
5053 {
5054 stub_entry->stub_offset = stub_sec->size;
5055 just_allocated = 1;
5056 }
906e58ca
NC		 5057 loc = stub_sec->contents + stub_entry->stub_offset;
5058
5059 stub_bfd = stub_sec->owner;
5060
906e58ca
NC		 5061 /* This is the address of the stub destination. */
5062 sym_value = (stub_entry->target_value
5063 + stub_entry->target_section->output_offset
5064 + stub_entry->target_section->output_section->vma);
5065
d3ce72d0 5066 template_sequence = stub_entry->stub_template;
461a49ca 5067 template_size = stub_entry->stub_template_size;
906e58ca
NC		 5068
5069 size = 0;
461a49ca 5070 for (i = 0; i < template_size; i++)
906e58ca 5071 {
d3ce72d0 5072 switch (template_sequence[i].type)
461a49ca
DJ		 5073 {
5074 case THUMB16_TYPE:
48229727 5075 {
d3ce72d0
NC		 5076 bfd_vma data = (bfd_vma) template_sequence[i].data;
5077 if (template_sequence[i].reloc_addend != 0)
48229727 5078 {
99059e56
RM		 5079 /* We've borrowed the reloc_addend field to mean we should
5080 insert a condition code into this (Thumb-1 branch)
5081 instruction. See THUMB16_BCOND_INSN. */
5082 BFD_ASSERT ((data & 0xff00) == 0xd000);
5083 data |= ((stub_entry->orig_insn >> 22) & 0xf) << 8;
48229727 5084 }
fe33d2fa 5085 bfd_put_16 (stub_bfd, data, loc + size);
48229727
JB		 5086 size += 2;
5087 }
461a49ca 5088 break;
906e58ca 5089
48229727 5090 case THUMB32_TYPE:
fe33d2fa
CL		 5091 bfd_put_16 (stub_bfd,
5092 (template_sequence[i].data >> 16) & 0xffff,
5093 loc + size);
5094 bfd_put_16 (stub_bfd, template_sequence[i].data & 0xffff,
5095 loc + size + 2);
99059e56
RM		 5096 if (template_sequence[i].r_type != R_ARM_NONE)
5097 {
5098 stub_reloc_idx[nrelocs] = i;
5099 stub_reloc_offset[nrelocs++] = size;
5100 }
5101 size += 4;
5102 break;
48229727 5103
461a49ca 5104 case ARM_TYPE:
fe33d2fa
CL		 5105 bfd_put_32 (stub_bfd, template_sequence[i].data,
5106 loc + size);
461a49ca
DJ		 5107 /* Handle cases where the target is encoded within the
5108 instruction. */
d3ce72d0 5109 if (template_sequence[i].r_type == R_ARM_JUMP24)
461a49ca 5110 {
48229727
JB		 5111 stub_reloc_idx[nrelocs] = i;
5112 stub_reloc_offset[nrelocs++] = size;
461a49ca
DJ		 5113 }
5114 size += 4;
5115 break;
5116
5117 case DATA_TYPE:
d3ce72d0 5118 bfd_put_32 (stub_bfd, template_sequence[i].data, loc + size);
48229727
JB		 5119 stub_reloc_idx[nrelocs] = i;
5120 stub_reloc_offset[nrelocs++] = size;
461a49ca
DJ		 5121 size += 4;
5122 break;
5123
5124 default:
5125 BFD_FAIL ();
5126 return FALSE;
5127 }
906e58ca 5128 }
461a49ca 5129
0955507f
TP		 5130 if (just_allocated)
5131 stub_sec->size += size;
906e58ca 5132
461a49ca
DJ		 5133 /* Stub size has already been computed in arm_size_one_stub. Check
5134 consistency. */
5135 BFD_ASSERT (size == stub_entry->stub_size);
5136
906e58ca 5137 /* Destination is Thumb. Force bit 0 to 1 to reflect this. */
35fc36a8 5138 if (stub_entry->branch_type == ST_BRANCH_TO_THUMB)
906e58ca
NC		 5139 sym_value |= 1;
5140
0955507f
TP		 5141 /* Assume non empty slots have at least one and at most MAXRELOCS entries
5142 to relocate in each stub. */
5143 removed_sg_veneer =
5144 (size == 0 && stub_entry->stub_type == arm_stub_cmse_branch_thumb_only);
5145 BFD_ASSERT (removed_sg_veneer || (nrelocs != 0 && nrelocs <= MAXRELOCS));
c820be07 5146
48229727 5147 for (i = 0; i < nrelocs; i++)
8d9d9490
TP		 5148 {
5149 Elf_Internal_Rela rel;
5150 bfd_boolean unresolved_reloc;
5151 char *error_message;
5152 bfd_vma points_to =
5153 sym_value + template_sequence[stub_reloc_idx[i]].reloc_addend;
5154
5155 rel.r_offset = stub_entry->stub_offset + stub_reloc_offset[i];
5156 rel.r_info = ELF32_R_INFO (0,
5157 template_sequence[stub_reloc_idx[i]].r_type);
5158 rel.r_addend = 0;
5159
5160 if (stub_entry->stub_type == arm_stub_a8_veneer_b_cond && i == 0)
5161 /* The first relocation in the elf32_arm_stub_a8_veneer_b_cond[]
5162 template should refer back to the instruction after the original
5163 branch. We use target_section as Cortex-A8 erratum workaround stubs
5164 are only generated when both source and target are in the same
5165 section. */
5166 points_to = stub_entry->target_section->output_section->vma
5167 + stub_entry->target_section->output_offset
5168 + stub_entry->source_value;
5169
5170 elf32_arm_final_link_relocate (elf32_arm_howto_from_type
5171 (template_sequence[stub_reloc_idx[i]].r_type),
5172 stub_bfd, info->output_bfd, stub_sec, stub_sec->contents, &rel,
5173 points_to, info, stub_entry->target_section, "", STT_FUNC,
5174 stub_entry->branch_type,
5175 (struct elf_link_hash_entry *) stub_entry->h, &unresolved_reloc,
5176 &error_message);
5177 }
906e58ca
NC		 5178
5179 return TRUE;
48229727 5180#undef MAXRELOCS
906e58ca
NC		 5181}
5182
48229727
JB		 5183/* Calculate the template, template size and instruction size for a stub.
5184 Return value is the instruction size. */
906e58ca 5185
48229727
JB		 5186static unsigned int
5187find_stub_size_and_template (enum elf32_arm_stub_type stub_type,
5188 const insn_sequence **stub_template,
5189 int *stub_template_size)
906e58ca 5190{
d3ce72d0 5191 const insn_sequence *template_sequence = NULL;
48229727
JB		 5192 int template_size = 0, i;
5193 unsigned int size;
906e58ca 5194
d3ce72d0 5195 template_sequence = stub_definitions[stub_type].template_sequence;
2a229407
AM		 5196 if (stub_template)
5197 *stub_template = template_sequence;
5198
48229727 5199 template_size = stub_definitions[stub_type].template_size;
2a229407
AM		 5200 if (stub_template_size)
5201 *stub_template_size = template_size;
906e58ca
NC		 5202
5203 size = 0;
461a49ca
DJ		 5204 for (i = 0; i < template_size; i++)
5205 {
d3ce72d0 5206 switch (template_sequence[i].type)
461a49ca
DJ		 5207 {
5208 case THUMB16_TYPE:
5209 size += 2;
5210 break;
5211
5212 case ARM_TYPE:
48229727 5213 case THUMB32_TYPE:
461a49ca
DJ		 5214 case DATA_TYPE:
5215 size += 4;
5216 break;
5217
5218 default:
5219 BFD_FAIL ();
2a229407 5220 return 0;
461a49ca
DJ		 5221 }
5222 }
5223
48229727
JB		 5224 return size;
5225}
5226
5227/* As above, but don't actually build the stub. Just bump offset so
5228 we know stub section sizes. */
5229
5230static bfd_boolean
5231arm_size_one_stub (struct bfd_hash_entry *gen_entry,
c7e2358a 5232 void *in_arg ATTRIBUTE_UNUSED)
48229727
JB		 5233{
5234 struct elf32_arm_stub_hash_entry *stub_entry;
d3ce72d0 5235 const insn_sequence *template_sequence;
48229727
JB		 5236 int template_size, size;
5237
5238 /* Massage our args to the form they really have. */
5239 stub_entry = (struct elf32_arm_stub_hash_entry *) gen_entry;
48229727
JB		 5240
5241 BFD_ASSERT((stub_entry->stub_type > arm_stub_none)
5242 && stub_entry->stub_type < ARRAY_SIZE(stub_definitions));
5243
d3ce72d0 5244 size = find_stub_size_and_template (stub_entry->stub_type, &template_sequence,
48229727
JB		 5245 &template_size);
5246
0955507f
TP		 5247 /* Initialized to -1. Null size indicates an empty slot full of zeros. */
5248 if (stub_entry->stub_template_size)
5249 {
5250 stub_entry->stub_size = size;
5251 stub_entry->stub_template = template_sequence;
5252 stub_entry->stub_template_size = template_size;
5253 }
5254
5255 /* Already accounted for. */
5256 if (stub_entry->stub_offset != (bfd_vma) -1)
5257 return TRUE;
461a49ca 5258
906e58ca
NC		 5259 size = (size + 7) & ~7;
5260 stub_entry->stub_sec->size += size;
461a49ca 5261
906e58ca
NC		 5262 return TRUE;
5263}
5264
5265/* External entry points for sizing and building linker stubs. */
5266
5267/* Set up various things so that we can make a list of input sections
5268 for each output section included in the link. Returns -1 on error,
5269 0 when no stubs will be needed, and 1 on success. */
5270
5271int
5272elf32_arm_setup_section_lists (bfd *output_bfd,
5273 struct bfd_link_info *info)
5274{
5275 bfd *input_bfd;
5276 unsigned int bfd_count;
7292b3ac 5277 unsigned int top_id, top_index;
906e58ca
NC		 5278 asection *section;
5279 asection **input_list, **list;
986f0783 5280 size_t amt;
906e58ca
NC		 5281 struct elf32_arm_link_hash_table *htab = elf32_arm_hash_table (info);
5282
4dfe6ac6
NC		 5283 if (htab == NULL)
5284 return 0;
906e58ca
NC		 5285 if (! is_elf_hash_table (htab))
5286 return 0;
5287
5288 /* Count the number of input BFDs and find the top input section id. */
5289 for (input_bfd = info->input_bfds, bfd_count = 0, top_id = 0;
5290 input_bfd != NULL;
c72f2fb2 5291 input_bfd = input_bfd->link.next)
906e58ca
NC		 5292 {
5293 bfd_count += 1;
5294 for (section = input_bfd->sections;
5295 section != NULL;
5296 section = section->next)
5297 {
5298 if (top_id < section->id)
5299 top_id = section->id;
5300 }
5301 }
5302 htab->bfd_count = bfd_count;
5303
5304 amt = sizeof (struct map_stub) * (top_id + 1);
21d799b5 5305 htab->stub_group = (struct map_stub *) bfd_zmalloc (amt);
906e58ca
NC		 5306 if (htab->stub_group == NULL)
5307 return -1;
fe33d2fa 5308 htab->top_id = top_id;
906e58ca
NC		 5309
5310 /* We can't use output_bfd->section_count here to find the top output
5311 section index as some sections may have been removed, and
5312 _bfd_strip_section_from_output doesn't renumber the indices. */
5313 for (section = output_bfd->sections, top_index = 0;
5314 section != NULL;
5315 section = section->next)
5316 {
5317 if (top_index < section->index)
5318 top_index = section->index;
5319 }
5320
5321 htab->top_index = top_index;
5322 amt = sizeof (asection *) * (top_index + 1);
21d799b5 5323 input_list = (asection **) bfd_malloc (amt);
906e58ca
NC		 5324 htab->input_list = input_list;
5325 if (input_list == NULL)
5326 return -1;
5327
5328 /* For sections we aren't interested in, mark their entries with a
5329 value we can check later. */
5330 list = input_list + top_index;
5331 do
5332 *list = bfd_abs_section_ptr;
5333 while (list-- != input_list);
5334
5335 for (section = output_bfd->sections;
5336 section != NULL;
5337 section = section->next)
5338 {
5339 if ((section->flags & SEC_CODE) != 0)
5340 input_list[section->index] = NULL;
5341 }
5342
5343 return 1;
5344}
5345
5346/* The linker repeatedly calls this function for each input section,
5347 in the order that input sections are linked into output sections.
5348 Build lists of input sections to determine groupings between which
5349 we may insert linker stubs. */
5350
5351void
5352elf32_arm_next_input_section (struct bfd_link_info *info,
5353 asection *isec)
5354{
5355 struct elf32_arm_link_hash_table *htab = elf32_arm_hash_table (info);
5356
4dfe6ac6
NC		 5357 if (htab == NULL)
5358 return;
5359
906e58ca
NC		 5360 if (isec->output_section->index <= htab->top_index)
5361 {
5362 asection **list = htab->input_list + isec->output_section->index;
5363
a7470592 5364 if (*list != bfd_abs_section_ptr && (isec->flags & SEC_CODE) != 0)
906e58ca
NC		 5365 {
5366 /* Steal the link_sec pointer for our list. */
5367#define PREV_SEC(sec) (htab->stub_group[(sec)->id].link_sec)
5368 /* This happens to make the list in reverse order,
07d72278 5369 which we reverse later. */
906e58ca
NC		 5370 PREV_SEC (isec) = *list;
5371 *list = isec;
5372 }
5373 }
5374}
5375
5376/* See whether we can group stub sections together. Grouping stub
5377 sections may result in fewer stubs. More importantly, we need to
07d72278 5378 put all .init* and .fini* stubs at the end of the .init or
906e58ca
NC		 5379 .fini output sections respectively, because glibc splits the
5380 _init and _fini functions into multiple parts. Putting a stub in
5381 the middle of a function is not a good idea. */
5382
5383static void
5384group_sections (struct elf32_arm_link_hash_table *htab,
5385 bfd_size_type stub_group_size,
07d72278 5386 bfd_boolean stubs_always_after_branch)
906e58ca 5387{
07d72278 5388 asection **list = htab->input_list;
906e58ca
NC		 5389
5390 do
5391 {
5392 asection *tail = *list;
07d72278 5393 asection *head;
906e58ca
NC		 5394
5395 if (tail == bfd_abs_section_ptr)
5396 continue;
5397
07d72278
DJ		 5398 /* Reverse the list: we must avoid placing stubs at the
5399 beginning of the section because the beginning of the text
5400 section may be required for an interrupt vector in bare metal
5401 code. */
5402#define NEXT_SEC PREV_SEC
e780aef2
CL		 5403 head = NULL;
5404 while (tail != NULL)
99059e56
RM		 5405 {
5406 /* Pop from tail. */
5407 asection *item = tail;
5408 tail = PREV_SEC (item);
e780aef2 5409
99059e56
RM		 5410 /* Push on head. */
5411 NEXT_SEC (item) = head;
5412 head = item;
5413 }
07d72278
DJ		 5414
5415 while (head != NULL)
906e58ca
NC		 5416 {
5417 asection *curr;
07d72278 5418 asection *next;
e780aef2
CL		 5419 bfd_vma stub_group_start = head->output_offset;
5420 bfd_vma end_of_next;
906e58ca 5421
07d72278 5422 curr = head;
e780aef2 5423 while (NEXT_SEC (curr) != NULL)
8cd931b7 5424 {
e780aef2
CL		 5425 next = NEXT_SEC (curr);
5426 end_of_next = next->output_offset + next->size;
5427 if (end_of_next - stub_group_start >= stub_group_size)
5428 /* End of NEXT is too far from start, so stop. */
8cd931b7 5429 break;
e780aef2
CL		 5430 /* Add NEXT to the group. */
5431 curr = next;
8cd931b7 5432 }
906e58ca 5433
07d72278 5434 /* OK, the size from the start to the start of CURR is less
906e58ca 5435 than stub_group_size and thus can be handled by one stub
07d72278 5436 section. (Or the head section is itself larger than
906e58ca
NC		 5437 stub_group_size, in which case we may be toast.)
5438 We should really be keeping track of the total size of
5439 stubs added here, as stubs contribute to the final output
7fb9f789 5440 section size. */
906e58ca
NC		 5441 do
5442 {
07d72278 5443 next = NEXT_SEC (head);
906e58ca 5444 /* Set up this stub group. */
07d72278 5445 htab->stub_group[head->id].link_sec = curr;
906e58ca 5446 }
07d72278 5447 while (head != curr && (head = next) != NULL);
906e58ca
NC		 5448
5449 /* But wait, there's more! Input sections up to stub_group_size
07d72278
DJ		 5450 bytes after the stub section can be handled by it too. */
5451 if (!stubs_always_after_branch)
906e58ca 5452 {
e780aef2
CL		 5453 stub_group_start = curr->output_offset + curr->size;
5454
8cd931b7 5455 while (next != NULL)
906e58ca 5456 {
e780aef2
CL		 5457 end_of_next = next->output_offset + next->size;
5458 if (end_of_next - stub_group_start >= stub_group_size)
5459 /* End of NEXT is too far from stubs, so stop. */
8cd931b7 5460 break;
e780aef2 5461 /* Add NEXT to the stub group. */
07d72278
DJ		 5462 head = next;
5463 next = NEXT_SEC (head);
5464 htab->stub_group[head->id].link_sec = curr;
906e58ca
NC		 5465 }
5466 }
07d72278 5467 head = next;
906e58ca
NC		 5468 }
5469 }
07d72278 5470 while (list++ != htab->input_list + htab->top_index);
906e58ca
NC		 5471
5472 free (htab->input_list);
5473#undef PREV_SEC
07d72278 5474#undef NEXT_SEC
906e58ca
NC		 5475}
5476
48229727
JB		 5477/* Comparison function for sorting/searching relocations relating to Cortex-A8
5478 erratum fix. */
5479
5480static int
5481a8_reloc_compare (const void *a, const void *b)
5482{
21d799b5
NC		 5483 const struct a8_erratum_reloc *ra = (const struct a8_erratum_reloc *) a;
5484 const struct a8_erratum_reloc *rb = (const struct a8_erratum_reloc *) b;
48229727
JB		 5485
5486 if (ra->from < rb->from)
5487 return -1;
5488 else if (ra->from > rb->from)
5489 return 1;
5490 else
5491 return 0;
5492}
5493
5494static struct elf_link_hash_entry *find_thumb_glue (struct bfd_link_info *,
5495 const char *, char **);
5496
5497/* Helper function to scan code for sequences which might trigger the Cortex-A8
5498 branch/TLB erratum. Fill in the table described by A8_FIXES_P,
81694485 5499 NUM_A8_FIXES_P, A8_FIX_TABLE_SIZE_P. Returns true if an error occurs, false
48229727
JB		 5500 otherwise. */
5501
81694485
NC		 5502static bfd_boolean
5503cortex_a8_erratum_scan (bfd *input_bfd,
5504 struct bfd_link_info *info,
48229727
JB		 5505 struct a8_erratum_fix **a8_fixes_p,
5506 unsigned int *num_a8_fixes_p,
5507 unsigned int *a8_fix_table_size_p,
5508 struct a8_erratum_reloc *a8_relocs,
eb7c4339
NS		 5509 unsigned int num_a8_relocs,
5510 unsigned prev_num_a8_fixes,
5511 bfd_boolean *stub_changed_p)
48229727
JB		 5512{
5513 asection *section;
5514 struct elf32_arm_link_hash_table *htab = elf32_arm_hash_table (info);
5515 struct a8_erratum_fix *a8_fixes = *a8_fixes_p;
5516 unsigned int num_a8_fixes = *num_a8_fixes_p;
5517 unsigned int a8_fix_table_size = *a8_fix_table_size_p;
5518
4dfe6ac6
NC		 5519 if (htab == NULL)
5520 return FALSE;
5521
48229727
JB		 5522 for (section = input_bfd->sections;
5523 section != NULL;
5524 section = section->next)
5525 {
5526 bfd_byte *contents = NULL;
5527 struct _arm_elf_section_data *sec_data;
5528 unsigned int span;
5529 bfd_vma base_vma;
5530
5531 if (elf_section_type (section) != SHT_PROGBITS
99059e56
RM		 5532 || (elf_section_flags (section) & SHF_EXECINSTR) == 0
5533 || (section->flags & SEC_EXCLUDE) != 0
5534 || (section->sec_info_type == SEC_INFO_TYPE_JUST_SYMS)
5535 || (section->output_section == bfd_abs_section_ptr))
5536 continue;
48229727
JB		 5537
5538 base_vma = section->output_section->vma + section->output_offset;
5539
5540 if (elf_section_data (section)->this_hdr.contents != NULL)
99059e56 5541 contents = elf_section_data (section)->this_hdr.contents;
48229727 5542 else if (! bfd_malloc_and_get_section (input_bfd, section, &contents))
99059e56 5543 return TRUE;
48229727
JB		 5544
5545 sec_data = elf32_arm_section_data (section);
5546
5547 for (span = 0; span < sec_data->mapcount; span++)
99059e56
RM		 5548 {
5549 unsigned int span_start = sec_data->map[span].vma;
5550 unsigned int span_end = (span == sec_data->mapcount - 1)
5551 ? section->size : sec_data->map[span + 1].vma;
5552 unsigned int i;
5553 char span_type = sec_data->map[span].type;
5554 bfd_boolean last_was_32bit = FALSE, last_was_branch = FALSE;
5555
5556 if (span_type != 't')
5557 continue;
5558
5559 /* Span is entirely within a single 4KB region: skip scanning. */
5560 if (((base_vma + span_start) & ~0xfff)
48229727 5561 == ((base_vma + span_end) & ~0xfff))
99059e56
RM		 5562 continue;
5563
5564 /* Scan for 32-bit Thumb-2 branches which span two 4K regions, where:
5565
5566 * The opcode is BLX.W, BL.W, B.W, Bcc.W
5567 * The branch target is in the same 4KB region as the
5568 first half of the branch.
5569 * The instruction before the branch is a 32-bit
5570 length non-branch instruction. */
5571 for (i = span_start; i < span_end;)
5572 {
5573 unsigned int insn = bfd_getl16 (&contents[i]);
5574 bfd_boolean insn_32bit = FALSE, is_blx = FALSE, is_b = FALSE;
48229727
JB		 5575 bfd_boolean is_bl = FALSE, is_bcc = FALSE, is_32bit_branch;
5576
99059e56
RM		 5577 if ((insn & 0xe000) == 0xe000 && (insn & 0x1800) != 0x0000)
5578 insn_32bit = TRUE;
48229727
JB		 5579
5580 if (insn_32bit)
99059e56
RM		 5581 {
5582 /* Load the rest of the insn (in manual-friendly order). */
5583 insn = (insn << 16) | bfd_getl16 (&contents[i + 2]);
5584
5585 /* Encoding T4: B<c>.W. */
5586 is_b = (insn & 0xf800d000) == 0xf0009000;
5587 /* Encoding T1: BL<c>.W. */
5588 is_bl = (insn & 0xf800d000) == 0xf000d000;
5589 /* Encoding T2: BLX<c>.W. */
5590 is_blx = (insn & 0xf800d000) == 0xf000c000;
48229727
JB		 5591 /* Encoding T3: B<c>.W (not permitted in IT block). */
5592 is_bcc = (insn & 0xf800d000) == 0xf0008000
5593 && (insn & 0x07f00000) != 0x03800000;
5594 }
5595
5596 is_32bit_branch = is_b || is_bl || is_blx || is_bcc;
fe33d2fa 5597
99059e56 5598 if (((base_vma + i) & 0xfff) == 0xffe
81694485
NC		 5599 && insn_32bit
5600 && is_32bit_branch
5601 && last_was_32bit
5602 && ! last_was_branch)
99059e56
RM		 5603 {
5604 bfd_signed_vma offset = 0;
5605 bfd_boolean force_target_arm = FALSE;
48229727 5606 bfd_boolean force_target_thumb = FALSE;
99059e56
RM		 5607 bfd_vma target;
5608 enum elf32_arm_stub_type stub_type = arm_stub_none;
5609 struct a8_erratum_reloc key, *found;
5610 bfd_boolean use_plt = FALSE;
48229727 5611
99059e56
RM		 5612 key.from = base_vma + i;
5613 found = (struct a8_erratum_reloc *)
5614 bsearch (&key, a8_relocs, num_a8_relocs,
5615 sizeof (struct a8_erratum_reloc),
5616 &a8_reloc_compare);
48229727
JB		 5617
5618 if (found)
5619 {
5620 char *error_message = NULL;
5621 struct elf_link_hash_entry *entry;
5622
5623 /* We don't care about the error returned from this
99059e56 5624 function, only if there is glue or not. */
48229727
JB		 5625 entry = find_thumb_glue (info, found->sym_name,
5626 &error_message);
5627
5628 if (entry)
5629 found->non_a8_stub = TRUE;
5630
92750f34 5631 /* Keep a simpler condition, for the sake of clarity. */
362d30a1 5632 if (htab->root.splt != NULL && found->hash != NULL
92750f34
DJ		 5633 && found->hash->root.plt.offset != (bfd_vma) -1)
5634 use_plt = TRUE;
5635
5636 if (found->r_type == R_ARM_THM_CALL)
5637 {
35fc36a8
RS		 5638 if (found->branch_type == ST_BRANCH_TO_ARM
5639 || use_plt)
92750f34
DJ		 5640 force_target_arm = TRUE;
5641 else
5642 force_target_thumb = TRUE;
5643 }
48229727
JB		 5644 }
5645
99059e56 5646 /* Check if we have an offending branch instruction. */
48229727
JB		 5647
5648 if (found && found->non_a8_stub)
5649 /* We've already made a stub for this instruction, e.g.
5650 it's a long branch or a Thumb->ARM stub. Assume that
5651 stub will suffice to work around the A8 erratum (see
5652 setting of always_after_branch above). */
5653 ;
99059e56
RM		 5654 else if (is_bcc)
5655 {
5656 offset = (insn & 0x7ff) << 1;
5657 offset |= (insn & 0x3f0000) >> 4;
5658 offset |= (insn & 0x2000) ? 0x40000 : 0;
5659 offset |= (insn & 0x800) ? 0x80000 : 0;
5660 offset |= (insn & 0x4000000) ? 0x100000 : 0;
5661 if (offset & 0x100000)
5662 offset |= ~ ((bfd_signed_vma) 0xfffff);
5663 stub_type = arm_stub_a8_veneer_b_cond;
5664 }
5665 else if (is_b || is_bl || is_blx)
5666 {
5667 int s = (insn & 0x4000000) != 0;
5668 int j1 = (insn & 0x2000) != 0;
5669 int j2 = (insn & 0x800) != 0;
5670 int i1 = !(j1 ^ s);
5671 int i2 = !(j2 ^ s);
5672
5673 offset = (insn & 0x7ff) << 1;
5674 offset |= (insn & 0x3ff0000) >> 4;
5675 offset |= i2 << 22;
5676 offset |= i1 << 23;
5677 offset |= s << 24;
5678 if (offset & 0x1000000)
5679 offset |= ~ ((bfd_signed_vma) 0xffffff);
5680
5681 if (is_blx)
5682 offset &= ~ ((bfd_signed_vma) 3);
5683
5684 stub_type = is_blx ? arm_stub_a8_veneer_blx :
5685 is_bl ? arm_stub_a8_veneer_bl : arm_stub_a8_veneer_b;
5686 }
5687
5688 if (stub_type != arm_stub_none)
5689 {
5690 bfd_vma pc_for_insn = base_vma + i + 4;
48229727
JB		 5691
5692 /* The original instruction is a BL, but the target is
99059e56 5693 an ARM instruction. If we were not making a stub,
48229727
JB		 5694 the BL would have been converted to a BLX. Use the
5695 BLX stub instead in that case. */
5696 if (htab->use_blx && force_target_arm
5697 && stub_type == arm_stub_a8_veneer_bl)
5698 {
5699 stub_type = arm_stub_a8_veneer_blx;
5700 is_blx = TRUE;
5701 is_bl = FALSE;
5702 }
5703 /* Conversely, if the original instruction was
5704 BLX but the target is Thumb mode, use the BL
5705 stub. */
5706 else if (force_target_thumb
5707 && stub_type == arm_stub_a8_veneer_blx)
5708 {
5709 stub_type = arm_stub_a8_veneer_bl;
5710 is_blx = FALSE;
5711 is_bl = TRUE;
5712 }
5713
99059e56
RM		 5714 if (is_blx)
5715 pc_for_insn &= ~ ((bfd_vma) 3);
48229727 5716
99059e56
RM		 5717 /* If we found a relocation, use the proper destination,
5718 not the offset in the (unrelocated) instruction.
48229727
JB		 5719 Note this is always done if we switched the stub type
5720 above. */
99059e56
RM		 5721 if (found)
5722 offset =
81694485 5723 (bfd_signed_vma) (found->destination - pc_for_insn);
48229727 5724
99059e56
RM		 5725 /* If the stub will use a Thumb-mode branch to a
5726 PLT target, redirect it to the preceding Thumb
5727 entry point. */
5728 if (stub_type != arm_stub_a8_veneer_blx && use_plt)
5729 offset -= PLT_THUMB_STUB_SIZE;
7d24e6a6 5730
99059e56 5731 target = pc_for_insn + offset;
48229727 5732
99059e56
RM		 5733 /* The BLX stub is ARM-mode code. Adjust the offset to
5734 take the different PC value (+8 instead of +4) into
48229727 5735 account. */
99059e56
RM		 5736 if (stub_type == arm_stub_a8_veneer_blx)
5737 offset += 4;
5738
5739 if (((base_vma + i) & ~0xfff) == (target & ~0xfff))
5740 {
5741 char *stub_name = NULL;
5742
5743 if (num_a8_fixes == a8_fix_table_size)
5744 {
5745 a8_fix_table_size *= 2;
5746 a8_fixes = (struct a8_erratum_fix *)
5747 bfd_realloc (a8_fixes,
5748 sizeof (struct a8_erratum_fix)
5749 * a8_fix_table_size);
5750 }
48229727 5751
eb7c4339
NS		 5752 if (num_a8_fixes < prev_num_a8_fixes)
5753 {
5754 /* If we're doing a subsequent scan,
5755 check if we've found the same fix as
5756 before, and try and reuse the stub
5757 name. */
5758 stub_name = a8_fixes[num_a8_fixes].stub_name;
5759 if ((a8_fixes[num_a8_fixes].section != section)
5760 || (a8_fixes[num_a8_fixes].offset != i))
5761 {
5762 free (stub_name);
5763 stub_name = NULL;
5764 *stub_changed_p = TRUE;
5765 }
5766 }
5767
5768 if (!stub_name)
5769 {
21d799b5 5770 stub_name = (char *) bfd_malloc (8 + 1 + 8 + 1);
eb7c4339
NS		 5771 if (stub_name != NULL)
5772 sprintf (stub_name, "%x:%x", section->id, i);
5773 }
48229727 5774
99059e56
RM		 5775 a8_fixes[num_a8_fixes].input_bfd = input_bfd;
5776 a8_fixes[num_a8_fixes].section = section;
5777 a8_fixes[num_a8_fixes].offset = i;
8d9d9490
TP		 5778 a8_fixes[num_a8_fixes].target_offset =
5779 target - base_vma;
99059e56
RM		 5780 a8_fixes[num_a8_fixes].orig_insn = insn;
5781 a8_fixes[num_a8_fixes].stub_name = stub_name;
5782 a8_fixes[num_a8_fixes].stub_type = stub_type;
5783 a8_fixes[num_a8_fixes].branch_type =
35fc36a8 5784 is_blx ? ST_BRANCH_TO_ARM : ST_BRANCH_TO_THUMB;
48229727 5785
99059e56
RM		 5786 num_a8_fixes++;
5787 }
5788 }
5789 }
48229727 5790
99059e56
RM		 5791 i += insn_32bit ? 4 : 2;
5792 last_was_32bit = insn_32bit;
48229727 5793 last_was_branch = is_32bit_branch;
99059e56
RM		 5794 }
5795 }
48229727
JB		 5796
5797 if (elf_section_data (section)->this_hdr.contents == NULL)
99059e56 5798 free (contents);
48229727 5799 }
fe33d2fa 5800
48229727
JB		 5801 *a8_fixes_p = a8_fixes;
5802 *num_a8_fixes_p = num_a8_fixes;
5803 *a8_fix_table_size_p = a8_fix_table_size;
fe33d2fa 5804
81694485 5805 return FALSE;
48229727
JB		 5806}
5807
b715f643
TP		 5808/* Create or update a stub entry depending on whether the stub can already be
5809 found in HTAB. The stub is identified by:
5810 - its type STUB_TYPE
5811 - its source branch (note that several can share the same stub) whose
5812 section and relocation (if any) are given by SECTION and IRELA
5813 respectively
5814 - its target symbol whose input section, hash, name, value and branch type
5815 are given in SYM_SEC, HASH, SYM_NAME, SYM_VALUE and BRANCH_TYPE
5816 respectively
5817
5818 If found, the value of the stub's target symbol is updated from SYM_VALUE
5819 and *NEW_STUB is set to FALSE. Otherwise, *NEW_STUB is set to
5820 TRUE and the stub entry is initialized.
5821
0955507f
TP		 5822 Returns the stub that was created or updated, or NULL if an error
5823 occurred. */
b715f643 5824
0955507f 5825static struct elf32_arm_stub_hash_entry *
b715f643
TP		 5826elf32_arm_create_stub (struct elf32_arm_link_hash_table *htab,
5827 enum elf32_arm_stub_type stub_type, asection *section,
5828 Elf_Internal_Rela *irela, asection *sym_sec,
5829 struct elf32_arm_link_hash_entry *hash, char *sym_name,
5830 bfd_vma sym_value, enum arm_st_branch_type branch_type,
5831 bfd_boolean *new_stub)
5832{
5833 const asection *id_sec;
5834 char *stub_name;
5835 struct elf32_arm_stub_hash_entry *stub_entry;
5836 unsigned int r_type;
4f4faa4d 5837 bfd_boolean sym_claimed = arm_stub_sym_claimed (stub_type);
b715f643
TP		 5838
5839 BFD_ASSERT (stub_type != arm_stub_none);
5840 *new_stub = FALSE;
5841
4f4faa4d
TP		 5842 if (sym_claimed)
5843 stub_name = sym_name;
5844 else
5845 {
5846 BFD_ASSERT (irela);
5847 BFD_ASSERT (section);
c2abbbeb 5848 BFD_ASSERT (section->id <= htab->top_id);
b715f643 5849
4f4faa4d
TP		 5850 /* Support for grouping stub sections. */
5851 id_sec = htab->stub_group[section->id].link_sec;
b715f643 5852
4f4faa4d
TP		 5853 /* Get the name of this stub. */
5854 stub_name = elf32_arm_stub_name (id_sec, sym_sec, hash, irela,
5855 stub_type);
5856 if (!stub_name)
0955507f 5857 return NULL;
4f4faa4d 5858 }
b715f643
TP		 5859
5860 stub_entry = arm_stub_hash_lookup (&htab->stub_hash_table, stub_name, FALSE,
5861 FALSE);
5862 /* The proper stub has already been created, just update its value. */
5863 if (stub_entry != NULL)
5864 {
4f4faa4d
TP		 5865 if (!sym_claimed)
5866 free (stub_name);
b715f643 5867 stub_entry->target_value = sym_value;
0955507f 5868 return stub_entry;
b715f643
TP		 5869 }
5870
daa4adae 5871 stub_entry = elf32_arm_add_stub (stub_name, section, htab, stub_type);
b715f643
TP		 5872 if (stub_entry == NULL)
5873 {
4f4faa4d
TP		 5874 if (!sym_claimed)
5875 free (stub_name);
0955507f 5876 return NULL;
b715f643
TP		 5877 }
5878
5879 stub_entry->target_value = sym_value;
5880 stub_entry->target_section = sym_sec;
5881 stub_entry->stub_type = stub_type;
5882 stub_entry->h = hash;
5883 stub_entry->branch_type = branch_type;
5884
4f4faa4d
TP		 5885 if (sym_claimed)
5886 stub_entry->output_name = sym_name;
5887 else
b715f643 5888 {
4f4faa4d
TP		 5889 if (sym_name == NULL)
5890 sym_name = "unnamed";
5891 stub_entry->output_name = (char *)
5892 bfd_alloc (htab->stub_bfd, sizeof (THUMB2ARM_GLUE_ENTRY_NAME)
5893 + strlen (sym_name));
5894 if (stub_entry->output_name == NULL)
5895 {
5896 free (stub_name);
0955507f 5897 return NULL;
4f4faa4d 5898 }
b715f643 5899
4f4faa4d
TP		 5900 /* For historical reasons, use the existing names for ARM-to-Thumb and
5901 Thumb-to-ARM stubs. */
5902 r_type = ELF32_R_TYPE (irela->r_info);
5903 if ((r_type == (unsigned int) R_ARM_THM_CALL
5904 || r_type == (unsigned int) R_ARM_THM_JUMP24
5905 || r_type == (unsigned int) R_ARM_THM_JUMP19)
5906 && branch_type == ST_BRANCH_TO_ARM)
5907 sprintf (stub_entry->output_name, THUMB2ARM_GLUE_ENTRY_NAME, sym_name);
5908 else if ((r_type == (unsigned int) R_ARM_CALL
5909 || r_type == (unsigned int) R_ARM_JUMP24)
5910 && branch_type == ST_BRANCH_TO_THUMB)
5911 sprintf (stub_entry->output_name, ARM2THUMB_GLUE_ENTRY_NAME, sym_name);
5912 else
5913 sprintf (stub_entry->output_name, STUB_ENTRY_NAME, sym_name);
5914 }
b715f643
TP		 5915
5916 *new_stub = TRUE;
0955507f 5917 return stub_entry;
b715f643
TP		 5918}
5919
4ba2ef8f
TP		 5920/* Scan symbols in INPUT_BFD to identify secure entry functions needing a
5921 gateway veneer to transition from non secure to secure state and create them
5922 accordingly.
5923
5924 "ARMv8-M Security Extensions: Requirements on Development Tools" document
5925 defines the conditions that govern Secure Gateway veneer creation for a
5926 given symbol <SYM> as follows:
5927 - it has function type
5928 - it has non local binding
5929 - a symbol named __acle_se_<SYM> (called special symbol) exists with the
5930 same type, binding and value as <SYM> (called normal symbol).
5931 An entry function can handle secure state transition itself in which case
5932 its special symbol would have a different value from the normal symbol.
5933
5934 OUT_ATTR gives the output attributes, SYM_HASHES the symbol index to hash
5935 entry mapping while HTAB gives the name to hash entry mapping.
0955507f
TP		 5936 *CMSE_STUB_CREATED is increased by the number of secure gateway veneer
5937 created.
4ba2ef8f 5938
0955507f 5939 The return value gives whether a stub failed to be allocated. */
4ba2ef8f
TP		 5940
5941static bfd_boolean
5942cmse_scan (bfd *input_bfd, struct elf32_arm_link_hash_table *htab,
5943 obj_attribute *out_attr, struct elf_link_hash_entry **sym_hashes,
0955507f 5944 int *cmse_stub_created)
4ba2ef8f
TP		 5945{
5946 const struct elf_backend_data *bed;
5947 Elf_Internal_Shdr *symtab_hdr;
5948 unsigned i, j, sym_count, ext_start;
5949 Elf_Internal_Sym *cmse_sym, *local_syms;
5950 struct elf32_arm_link_hash_entry *hash, *cmse_hash = NULL;
5951 enum arm_st_branch_type branch_type;
5952 char *sym_name, *lsym_name;
5953 bfd_vma sym_value;
5954 asection *section;
0955507f
TP		 5955 struct elf32_arm_stub_hash_entry *stub_entry;
5956 bfd_boolean is_v8m, new_stub, cmse_invalid, ret = TRUE;
4ba2ef8f
TP		 5957
5958 bed = get_elf_backend_data (input_bfd);
5959 symtab_hdr = &elf_tdata (input_bfd)->symtab_hdr;
5960 sym_count = symtab_hdr->sh_size / bed->s->sizeof_sym;
5961 ext_start = symtab_hdr->sh_info;
5962 is_v8m = (out_attr[Tag_CPU_arch].i >= TAG_CPU_ARCH_V8M_BASE
5963 && out_attr[Tag_CPU_arch_profile].i == 'M');
5964
5965 local_syms = (Elf_Internal_Sym *) symtab_hdr->contents;
5966 if (local_syms == NULL)
5967 local_syms = bfd_elf_get_elf_syms (input_bfd, symtab_hdr,
5968 symtab_hdr->sh_info, 0, NULL, NULL,
5969 NULL);
5970 if (symtab_hdr->sh_info && local_syms == NULL)
5971 return FALSE;
5972
5973 /* Scan symbols. */
5974 for (i = 0; i < sym_count; i++)
5975 {
5976 cmse_invalid = FALSE;
5977
5978 if (i < ext_start)
5979 {
5980 cmse_sym = &local_syms[i];
4ba2ef8f
TP		 5981 sym_name = bfd_elf_string_from_elf_section (input_bfd,
5982 symtab_hdr->sh_link,
5983 cmse_sym->st_name);
baf46cd7
AM		 5984 if (!sym_name || !CONST_STRNEQ (sym_name, CMSE_PREFIX))
5985 continue;
5986
4ba2ef8f
TP		 5987 /* Special symbol with local binding. */
5988 cmse_invalid = TRUE;
5989 }
5990 else
5991 {
5992 cmse_hash = elf32_arm_hash_entry (sym_hashes[i - ext_start]);
5993 sym_name = (char *) cmse_hash->root.root.root.string;
baf46cd7 5994 if (!CONST_STRNEQ (sym_name, CMSE_PREFIX))
4ba2ef8f
TP		 5995 continue;
5996
5997 /* Special symbol has incorrect binding or type. */
5998 if ((cmse_hash->root.root.type != bfd_link_hash_defined
5999 && cmse_hash->root.root.type != bfd_link_hash_defweak)
6000 || cmse_hash->root.type != STT_FUNC)
6001 cmse_invalid = TRUE;
6002 }
6003
6004 if (!is_v8m)
6005 {
90b6238f
AM		 6006 _bfd_error_handler (_("%pB: special symbol `%s' only allowed for "
6007 "ARMv8-M architecture or later"),
4eca0228 6008 input_bfd, sym_name);
4ba2ef8f
TP		 6009 is_v8m = TRUE; /* Avoid multiple warning. */
6010 ret = FALSE;
6011 }
6012
6013 if (cmse_invalid)
6014 {
90b6238f
AM		 6015 _bfd_error_handler (_("%pB: invalid special symbol `%s'; it must be"
6016 " a global or weak function symbol"),
4eca0228 6017 input_bfd, sym_name);
4ba2ef8f
TP		 6018 ret = FALSE;
6019 if (i < ext_start)
6020 continue;
6021 }
6022
6023 sym_name += strlen (CMSE_PREFIX);
6024 hash = (struct elf32_arm_link_hash_entry *)
6025 elf_link_hash_lookup (&(htab)->root, sym_name, FALSE, FALSE, TRUE);
6026
6027 /* No associated normal symbol or it is neither global nor weak. */
6028 if (!hash
6029 || (hash->root.root.type != bfd_link_hash_defined
6030 && hash->root.root.type != bfd_link_hash_defweak)
6031 || hash->root.type != STT_FUNC)
6032 {
6033 /* Initialize here to avoid warning about use of possibly
6034 uninitialized variable. */
6035 j = 0;
6036
6037 if (!hash)
6038 {
6039 /* Searching for a normal symbol with local binding. */
6040 for (; j < ext_start; j++)
6041 {
6042 lsym_name =
6043 bfd_elf_string_from_elf_section (input_bfd,
6044 symtab_hdr->sh_link,
6045 local_syms[j].st_name);
6046 if (!strcmp (sym_name, lsym_name))
6047 break;
6048 }
6049 }
6050
6051 if (hash || j < ext_start)
6052 {
4eca0228 6053 _bfd_error_handler
90b6238f
AM		 6054 (_("%pB: invalid standard symbol `%s'; it must be "
6055 "a global or weak function symbol"),
6056 input_bfd, sym_name);
4ba2ef8f
TP		 6057 }
6058 else
4eca0228 6059 _bfd_error_handler
90b6238f 6060 (_("%pB: absent standard symbol `%s'"), input_bfd, sym_name);
4ba2ef8f
TP		 6061 ret = FALSE;
6062 if (!hash)
6063 continue;
6064 }
6065
6066 sym_value = hash->root.root.u.def.value;
6067 section = hash->root.root.u.def.section;
6068
6069 if (cmse_hash->root.root.u.def.section != section)
6070 {
4eca0228 6071 _bfd_error_handler
90b6238f 6072 (_("%pB: `%s' and its special symbol are in different sections"),
4ba2ef8f
TP		 6073 input_bfd, sym_name);
6074 ret = FALSE;
6075 }
6076 if (cmse_hash->root.root.u.def.value != sym_value)
6077 continue; /* Ignore: could be an entry function starting with SG. */
6078
6079 /* If this section is a link-once section that will be discarded, then
6080 don't create any stubs. */
6081 if (section->output_section == NULL)
6082 {
4eca0228 6083 _bfd_error_handler
90b6238f 6084 (_("%pB: entry function `%s' not output"), input_bfd, sym_name);
4ba2ef8f
TP		 6085 continue;
6086 }
6087
6088 if (hash->root.size == 0)
6089 {
4eca0228 6090 _bfd_error_handler
90b6238f 6091 (_("%pB: entry function `%s' is empty"), input_bfd, sym_name);
4ba2ef8f
TP		 6092 ret = FALSE;
6093 }
6094
6095 if (!ret)
6096 continue;
6097 branch_type = ARM_GET_SYM_BRANCH_TYPE (hash->root.target_internal);
0955507f 6098 stub_entry
4ba2ef8f
TP		 6099 = elf32_arm_create_stub (htab, arm_stub_cmse_branch_thumb_only,
6100 NULL, NULL, section, hash, sym_name,
6101 sym_value, branch_type, &new_stub);
6102
0955507f 6103 if (stub_entry == NULL)
4ba2ef8f
TP		 6104 ret = FALSE;
6105 else
6106 {
6107 BFD_ASSERT (new_stub);
0955507f 6108 (*cmse_stub_created)++;
4ba2ef8f
TP		 6109 }
6110 }
6111
6112 if (!symtab_hdr->contents)
6113 free (local_syms);
6114 return ret;
6115}
6116
0955507f
TP		 6117/* Return TRUE iff a symbol identified by its linker HASH entry is a secure
6118 code entry function, ie can be called from non secure code without using a
6119 veneer. */
6120
6121static bfd_boolean
6122cmse_entry_fct_p (struct elf32_arm_link_hash_entry *hash)
6123{
42484486 6124 bfd_byte contents[4];
0955507f
TP		 6125 uint32_t first_insn;
6126 asection *section;
6127 file_ptr offset;
6128 bfd *abfd;
6129
6130 /* Defined symbol of function type. */
6131 if (hash->root.root.type != bfd_link_hash_defined
6132 && hash->root.root.type != bfd_link_hash_defweak)
6133 return FALSE;
6134 if (hash->root.type != STT_FUNC)
6135 return FALSE;
6136
6137 /* Read first instruction. */
6138 section = hash->root.root.u.def.section;
6139 abfd = section->owner;
6140 offset = hash->root.root.u.def.value - section->vma;
42484486
TP		 6141 if (!bfd_get_section_contents (abfd, section, contents, offset,
6142 sizeof (contents)))
0955507f
TP		 6143 return FALSE;
6144
42484486
TP		 6145 first_insn = bfd_get_32 (abfd, contents);
6146
6147 /* Starts by SG instruction. */
0955507f
TP		 6148 return first_insn == 0xe97fe97f;
6149}
6150
6151/* Output the name (in symbol table) of the veneer GEN_ENTRY if it is a new
6152 secure gateway veneers (ie. the veneers was not in the input import library)
6153 and there is no output import library (GEN_INFO->out_implib_bfd is NULL. */
6154
6155static bfd_boolean
6156arm_list_new_cmse_stub (struct bfd_hash_entry *gen_entry, void *gen_info)
6157{
6158 struct elf32_arm_stub_hash_entry *stub_entry;
6159 struct bfd_link_info *info;
6160
6161 /* Massage our args to the form they really have. */
6162 stub_entry = (struct elf32_arm_stub_hash_entry *) gen_entry;
6163 info = (struct bfd_link_info *) gen_info;
6164
6165 if (info->out_implib_bfd)
6166 return TRUE;
6167
6168 if (stub_entry->stub_type != arm_stub_cmse_branch_thumb_only)
6169 return TRUE;
6170
6171 if (stub_entry->stub_offset == (bfd_vma) -1)
4eca0228 6172 _bfd_error_handler (" %s", stub_entry->output_name);
0955507f
TP		 6173
6174 return TRUE;
6175}
6176
6177/* Set offset of each secure gateway veneers so that its address remain
6178 identical to the one in the input import library referred by
6179 HTAB->in_implib_bfd. A warning is issued for veneers that disappeared
6180 (present in input import library but absent from the executable being
6181 linked) or if new veneers appeared and there is no output import library
6182 (INFO->out_implib_bfd is NULL and *CMSE_STUB_CREATED is bigger than the
6183 number of secure gateway veneers found in the input import library.
6184
6185 The function returns whether an error occurred. If no error occurred,
6186 *CMSE_STUB_CREATED gives the number of SG veneers created by both cmse_scan
6187 and this function and HTAB->new_cmse_stub_offset is set to the biggest
6188 veneer observed set for new veneers to be layed out after. */
6189
6190static bfd_boolean
6191set_cmse_veneer_addr_from_implib (struct bfd_link_info *info,
6192 struct elf32_arm_link_hash_table *htab,
6193 int *cmse_stub_created)
6194{
6195 long symsize;
6196 char *sym_name;
6197 flagword flags;
6198 long i, symcount;
6199 bfd *in_implib_bfd;
6200 asection *stub_out_sec;
6201 bfd_boolean ret = TRUE;
6202 Elf_Internal_Sym *intsym;
6203 const char *out_sec_name;
6204 bfd_size_type cmse_stub_size;
6205 asymbol **sympp = NULL, *sym;
6206 struct elf32_arm_link_hash_entry *hash;
6207 const insn_sequence *cmse_stub_template;
6208 struct elf32_arm_stub_hash_entry *stub_entry;
6209 int cmse_stub_template_size, new_cmse_stubs_created = *cmse_stub_created;
6210 bfd_vma veneer_value, stub_offset, next_cmse_stub_offset;
6211 bfd_vma cmse_stub_array_start = (bfd_vma) -1, cmse_stub_sec_vma = 0;
6212
6213 /* No input secure gateway import library. */
6214 if (!htab->in_implib_bfd)
6215 return TRUE;
6216
6217 in_implib_bfd = htab->in_implib_bfd;
6218 if (!htab->cmse_implib)
6219 {
871b3ab2 6220 _bfd_error_handler (_("%pB: --in-implib only supported for Secure "
90b6238f 6221 "Gateway import libraries"), in_implib_bfd);
0955507f
TP		 6222 return FALSE;
6223 }
6224
6225 /* Get symbol table size. */
6226 symsize = bfd_get_symtab_upper_bound (in_implib_bfd);
6227 if (symsize < 0)
6228 return FALSE;
6229
6230 /* Read in the input secure gateway import library's symbol table. */
9a733151
AM		 6231 sympp = (asymbol **) bfd_malloc (symsize);
6232 if (sympp == NULL)
6233 return FALSE;
6234
0955507f
TP		 6235 symcount = bfd_canonicalize_symtab (in_implib_bfd, sympp);
6236 if (symcount < 0)
6237 {
6238 ret = FALSE;
6239 goto free_sym_buf;
6240 }
6241
6242 htab->new_cmse_stub_offset = 0;
6243 cmse_stub_size =
6244 find_stub_size_and_template (arm_stub_cmse_branch_thumb_only,
6245 &cmse_stub_template,
6246 &cmse_stub_template_size);
6247 out_sec_name =
6248 arm_dedicated_stub_output_section_name (arm_stub_cmse_branch_thumb_only);
6249 stub_out_sec =
6250 bfd_get_section_by_name (htab->obfd, out_sec_name);
6251 if (stub_out_sec != NULL)
6252 cmse_stub_sec_vma = stub_out_sec->vma;
6253
6254 /* Set addresses of veneers mentionned in input secure gateway import
6255 library's symbol table. */
6256 for (i = 0; i < symcount; i++)
6257 {
6258 sym = sympp[i];
6259 flags = sym->flags;
6260 sym_name = (char *) bfd_asymbol_name (sym);
6261 intsym = &((elf_symbol_type *) sym)->internal_elf_sym;
6262
6263 if (sym->section != bfd_abs_section_ptr
6264 || !(flags & (BSF_GLOBAL | BSF_WEAK))
6265 || (flags & BSF_FUNCTION) != BSF_FUNCTION
6266 || (ARM_GET_SYM_BRANCH_TYPE (intsym->st_target_internal)
6267 != ST_BRANCH_TO_THUMB))
6268 {
90b6238f
AM		 6269 _bfd_error_handler (_("%pB: invalid import library entry: `%s'; "
6270 "symbol should be absolute, global and "
6271 "refer to Thumb functions"),
4eca0228 6272 in_implib_bfd, sym_name);
0955507f
TP		 6273 ret = FALSE;
6274 continue;
6275 }
6276
6277 veneer_value = bfd_asymbol_value (sym);
6278 stub_offset = veneer_value - cmse_stub_sec_vma;
6279 stub_entry = arm_stub_hash_lookup (&htab->stub_hash_table, sym_name,
6280 FALSE, FALSE);
6281 hash = (struct elf32_arm_link_hash_entry *)
6282 elf_link_hash_lookup (&(htab)->root, sym_name, FALSE, FALSE, TRUE);
6283
6284 /* Stub entry should have been created by cmse_scan or the symbol be of
6285 a secure function callable from non secure code. */
6286 if (!stub_entry && !hash)
6287 {
6288 bfd_boolean new_stub;
6289
4eca0228 6290 _bfd_error_handler
90b6238f 6291 (_("entry function `%s' disappeared from secure code"), sym_name);
0955507f
TP		 6292 hash = (struct elf32_arm_link_hash_entry *)
6293 elf_link_hash_lookup (&(htab)->root, sym_name, TRUE, TRUE, TRUE);
6294 stub_entry
6295 = elf32_arm_create_stub (htab, arm_stub_cmse_branch_thumb_only,
6296 NULL, NULL, bfd_abs_section_ptr, hash,
6297 sym_name, veneer_value,
6298 ST_BRANCH_TO_THUMB, &new_stub);
6299 if (stub_entry == NULL)
6300 ret = FALSE;
6301 else
6302 {
6303 BFD_ASSERT (new_stub);
6304 new_cmse_stubs_created++;
6305 (*cmse_stub_created)++;
6306 }
6307 stub_entry->stub_template_size = stub_entry->stub_size = 0;
6308 stub_entry->stub_offset = stub_offset;
6309 }
6310 /* Symbol found is not callable from non secure code. */
6311 else if (!stub_entry)
6312 {
6313 if (!cmse_entry_fct_p (hash))
6314 {
90b6238f 6315 _bfd_error_handler (_("`%s' refers to a non entry function"),
4eca0228 6316 sym_name);
0955507f
TP		 6317 ret = FALSE;
6318 }
6319 continue;
6320 }
6321 else
6322 {
6323 /* Only stubs for SG veneers should have been created. */
6324 BFD_ASSERT (stub_entry->stub_type == arm_stub_cmse_branch_thumb_only);
6325
6326 /* Check visibility hasn't changed. */
6327 if (!!(flags & BSF_GLOBAL)
6328 != (hash->root.root.type == bfd_link_hash_defined))
4eca0228 6329 _bfd_error_handler
90b6238f 6330 (_("%pB: visibility of symbol `%s' has changed"), in_implib_bfd,
0955507f
TP		 6331 sym_name);
6332
6333 stub_entry->stub_offset = stub_offset;
6334 }
6335
6336 /* Size should match that of a SG veneer. */
6337 if (intsym->st_size != cmse_stub_size)
6338 {
90b6238f 6339 _bfd_error_handler (_("%pB: incorrect size for symbol `%s'"),
4eca0228 6340 in_implib_bfd, sym_name);
0955507f
TP		 6341 ret = FALSE;
6342 }
6343
6344 /* Previous veneer address is before current SG veneer section. */
6345 if (veneer_value < cmse_stub_sec_vma)
6346 {
6347 /* Avoid offset underflow. */
6348 if (stub_entry)
6349 stub_entry->stub_offset = 0;
6350 stub_offset = 0;
6351 ret = FALSE;
6352 }
6353
6354 /* Complain if stub offset not a multiple of stub size. */
6355 if (stub_offset % cmse_stub_size)
6356 {
4eca0228 6357 _bfd_error_handler
90b6238f
AM		 6358 (_("offset of veneer for entry function `%s' not a multiple of "
6359 "its size"), sym_name);
0955507f
TP		 6360 ret = FALSE;
6361 }
6362
6363 if (!ret)
6364 continue;
6365
6366 new_cmse_stubs_created--;
6367 if (veneer_value < cmse_stub_array_start)
6368 cmse_stub_array_start = veneer_value;
6369 next_cmse_stub_offset = stub_offset + ((cmse_stub_size + 7) & ~7);
6370 if (next_cmse_stub_offset > htab->new_cmse_stub_offset)
6371 htab->new_cmse_stub_offset = next_cmse_stub_offset;
6372 }
6373
6374 if (!info->out_implib_bfd && new_cmse_stubs_created != 0)
6375 {
6376 BFD_ASSERT (new_cmse_stubs_created > 0);
4eca0228 6377 _bfd_error_handler
0955507f
TP		 6378 (_("new entry function(s) introduced but no output import library "
6379 "specified:"));
6380 bfd_hash_traverse (&htab->stub_hash_table, arm_list_new_cmse_stub, info);
6381 }
6382
6383 if (cmse_stub_array_start != cmse_stub_sec_vma)
6384 {
4eca0228 6385 _bfd_error_handler
90b6238f 6386 (_("start address of `%s' is different from previous link"),
0955507f
TP		 6387 out_sec_name);
6388 ret = FALSE;
6389 }
6390
dc1e8a47 6391 free_sym_buf:
0955507f
TP		 6392 free (sympp);
6393 return ret;
6394}
6395
906e58ca
NC		 6396/* Determine and set the size of the stub section for a final link.
6397
6398 The basic idea here is to examine all the relocations looking for
6399 PC-relative calls to a target that is unreachable with a "bl"
6400 instruction. */
6401
6402bfd_boolean
6403elf32_arm_size_stubs (bfd *output_bfd,
6404 bfd *stub_bfd,
6405 struct bfd_link_info *info,
6406 bfd_signed_vma group_size,
7a89b94e 6407 asection * (*add_stub_section) (const char *, asection *,
6bde4c52 6408 asection *,
7a89b94e 6409 unsigned int),
906e58ca
NC		 6410 void (*layout_sections_again) (void))
6411{
0955507f 6412 bfd_boolean ret = TRUE;
4ba2ef8f 6413 obj_attribute *out_attr;
0955507f 6414 int cmse_stub_created = 0;
906e58ca 6415 bfd_size_type stub_group_size;
4ba2ef8f 6416 bfd_boolean m_profile, stubs_always_after_branch, first_veneer_scan = TRUE;
906e58ca 6417 struct elf32_arm_link_hash_table *htab = elf32_arm_hash_table (info);
48229727 6418 struct a8_erratum_fix *a8_fixes = NULL;
eb7c4339 6419 unsigned int num_a8_fixes = 0, a8_fix_table_size = 10;
48229727
JB		 6420 struct a8_erratum_reloc *a8_relocs = NULL;
6421 unsigned int num_a8_relocs = 0, a8_reloc_table_size = 10, i;
6422
4dfe6ac6
NC		 6423 if (htab == NULL)
6424 return FALSE;
6425
48229727
JB		 6426 if (htab->fix_cortex_a8)
6427 {
21d799b5 6428 a8_fixes = (struct a8_erratum_fix *)
99059e56 6429 bfd_zmalloc (sizeof (struct a8_erratum_fix) * a8_fix_table_size);
21d799b5 6430 a8_relocs = (struct a8_erratum_reloc *)
99059e56 6431 bfd_zmalloc (sizeof (struct a8_erratum_reloc) * a8_reloc_table_size);
48229727 6432 }
906e58ca
NC		 6433
6434 /* Propagate mach to stub bfd, because it may not have been
6435 finalized when we created stub_bfd. */
6436 bfd_set_arch_mach (stub_bfd, bfd_get_arch (output_bfd),
6437 bfd_get_mach (output_bfd));
6438
6439 /* Stash our params away. */
6440 htab->stub_bfd = stub_bfd;
6441 htab->add_stub_section = add_stub_section;
6442 htab->layout_sections_again = layout_sections_again;
07d72278 6443 stubs_always_after_branch = group_size < 0;
48229727 6444
4ba2ef8f
TP		 6445 out_attr = elf_known_obj_attributes_proc (output_bfd);
6446 m_profile = out_attr[Tag_CPU_arch_profile].i == 'M';
0955507f 6447
48229727
JB		 6448 /* The Cortex-A8 erratum fix depends on stubs not being in the same 4K page
6449 as the first half of a 32-bit branch straddling two 4K pages. This is a
6450 crude way of enforcing that. */
6451 if (htab->fix_cortex_a8)
6452 stubs_always_after_branch = 1;
6453
906e58ca
NC		 6454 if (group_size < 0)
6455 stub_group_size = -group_size;
6456 else
6457 stub_group_size = group_size;
6458
6459 if (stub_group_size == 1)
6460 {
6461 /* Default values. */
6462 /* Thumb branch range is +-4MB has to be used as the default
6463 maximum size (a given section can contain both ARM and Thumb
6464 code, so the worst case has to be taken into account).
6465
6466 This value is 24K less than that, which allows for 2025
6467 12-byte stubs. If we exceed that, then we will fail to link.
6468 The user will have to relink with an explicit group size
6469 option. */
6470 stub_group_size = 4170000;
6471 }
6472
07d72278 6473 group_sections (htab, stub_group_size, stubs_always_after_branch);
906e58ca 6474
3ae046cc
NS		 6475 /* If we're applying the cortex A8 fix, we need to determine the
6476 program header size now, because we cannot change it later --
6477 that could alter section placements. Notice the A8 erratum fix
6478 ends up requiring the section addresses to remain unchanged
6479 modulo the page size. That's something we cannot represent
6480 inside BFD, and we don't want to force the section alignment to
6481 be the page size. */
6482 if (htab->fix_cortex_a8)
6483 (*htab->layout_sections_again) ();
6484
906e58ca
NC		 6485 while (1)
6486 {
6487 bfd *input_bfd;
6488 unsigned int bfd_indx;
6489 asection *stub_sec;
d7c5bd02 6490 enum elf32_arm_stub_type stub_type;
eb7c4339
NS		 6491 bfd_boolean stub_changed = FALSE;
6492 unsigned prev_num_a8_fixes = num_a8_fixes;
906e58ca 6493
48229727 6494 num_a8_fixes = 0;
906e58ca
NC		 6495 for (input_bfd = info->input_bfds, bfd_indx = 0;
6496 input_bfd != NULL;
c72f2fb2 6497 input_bfd = input_bfd->link.next, bfd_indx++)
906e58ca
NC		 6498 {
6499 Elf_Internal_Shdr *symtab_hdr;
6500 asection *section;
6501 Elf_Internal_Sym *local_syms = NULL;
6502
73d5efd7
AM		 6503 if (!is_arm_elf (input_bfd))
6504 continue;
6505 if ((input_bfd->flags & DYNAMIC) != 0
6506 && (elf_sym_hashes (input_bfd) == NULL
6507 || (elf_dyn_lib_class (input_bfd) & DYN_AS_NEEDED) != 0))
99059e56 6508 continue;
adbcc655 6509
48229727
JB		 6510 num_a8_relocs = 0;
6511
906e58ca
NC		 6512 /* We'll need the symbol table in a second. */
6513 symtab_hdr = &elf_tdata (input_bfd)->symtab_hdr;
6514 if (symtab_hdr->sh_info == 0)
6515 continue;
6516
4ba2ef8f
TP		 6517 /* Limit scan of symbols to object file whose profile is
6518 Microcontroller to not hinder performance in the general case. */
6519 if (m_profile && first_veneer_scan)
6520 {
6521 struct elf_link_hash_entry **sym_hashes;
6522
6523 sym_hashes = elf_sym_hashes (input_bfd);
6524 if (!cmse_scan (input_bfd, htab, out_attr, sym_hashes,
0955507f 6525 &cmse_stub_created))
4ba2ef8f 6526 goto error_ret_free_local;
0955507f
TP		 6527
6528 if (cmse_stub_created != 0)
6529 stub_changed = TRUE;
4ba2ef8f
TP		 6530 }
6531
906e58ca
NC		 6532 /* Walk over each section attached to the input bfd. */
6533 for (section = input_bfd->sections;
6534 section != NULL;
6535 section = section->next)
6536 {
6537 Elf_Internal_Rela *internal_relocs, *irelaend, *irela;
6538
6539 /* If there aren't any relocs, then there's nothing more
6540 to do. */
6541 if ((section->flags & SEC_RELOC) == 0
6542 || section->reloc_count == 0
6543 || (section->flags & SEC_CODE) == 0)
6544 continue;
6545
6546 /* If this section is a link-once section that will be
6547 discarded, then don't create any stubs. */
6548 if (section->output_section == NULL
6549 || section->output_section->owner != output_bfd)
6550 continue;
6551
6552 /* Get the relocs. */
6553 internal_relocs
6554 = _bfd_elf_link_read_relocs (input_bfd, section, NULL,
6555 NULL, info->keep_memory);
6556 if (internal_relocs == NULL)
6557 goto error_ret_free_local;
6558
6559 /* Now examine each relocation. */
6560 irela = internal_relocs;
6561 irelaend = irela + section->reloc_count;
6562 for (; irela < irelaend; irela++)
6563 {
6564 unsigned int r_type, r_indx;
906e58ca
NC		 6565 asection *sym_sec;
6566 bfd_vma sym_value;
6567 bfd_vma destination;
6568 struct elf32_arm_link_hash_entry *hash;
7413f23f 6569 const char *sym_name;
34e77a92 6570 unsigned char st_type;
35fc36a8 6571 enum arm_st_branch_type branch_type;
48229727 6572 bfd_boolean created_stub = FALSE;
906e58ca
NC		 6573
6574 r_type = ELF32_R_TYPE (irela->r_info);
6575 r_indx = ELF32_R_SYM (irela->r_info);
6576
6577 if (r_type >= (unsigned int) R_ARM_max)
6578 {
6579 bfd_set_error (bfd_error_bad_value);
6580 error_ret_free_internal:
6581 if (elf_section_data (section)->relocs == NULL)
6582 free (internal_relocs);
15dd01b1
TP		 6583 /* Fall through. */
6584 error_ret_free_local:
c9594989 6585 if (symtab_hdr->contents != (unsigned char *) local_syms)
15dd01b1
TP		 6586 free (local_syms);
6587 return FALSE;
906e58ca 6588 }
b38cadfb 6589
0855e32b
NS		 6590 hash = NULL;
6591 if (r_indx >= symtab_hdr->sh_info)
6592 hash = elf32_arm_hash_entry
6593 (elf_sym_hashes (input_bfd)
6594 [r_indx - symtab_hdr->sh_info]);
b38cadfb 6595
0855e32b
NS		 6596 /* Only look for stubs on branch instructions, or
6597 non-relaxed TLSCALL */
906e58ca 6598 if ((r_type != (unsigned int) R_ARM_CALL)
155d87d7
CL		 6599 && (r_type != (unsigned int) R_ARM_THM_CALL)
6600 && (r_type != (unsigned int) R_ARM_JUMP24)
48229727
JB		 6601 && (r_type != (unsigned int) R_ARM_THM_JUMP19)
6602 && (r_type != (unsigned int) R_ARM_THM_XPC22)
155d87d7 6603 && (r_type != (unsigned int) R_ARM_THM_JUMP24)
0855e32b
NS		 6604 && (r_type != (unsigned int) R_ARM_PLT32)
6605 && !((r_type == (unsigned int) R_ARM_TLS_CALL
6606 || r_type == (unsigned int) R_ARM_THM_TLS_CALL)
6607 && r_type == elf32_arm_tls_transition
6608 (info, r_type, &hash->root)
6609 && ((hash ? hash->tls_type
6610 : (elf32_arm_local_got_tls_type
6611 (input_bfd)[r_indx]))
6612 & GOT_TLS_GDESC) != 0))
906e58ca
NC		 6613 continue;
6614
6615 /* Now determine the call target, its name, value,
6616 section. */
6617 sym_sec = NULL;
6618 sym_value = 0;
6619 destination = 0;
7413f23f 6620 sym_name = NULL;
b38cadfb 6621
0855e32b
NS		 6622 if (r_type == (unsigned int) R_ARM_TLS_CALL
6623 || r_type == (unsigned int) R_ARM_THM_TLS_CALL)
6624 {
6625 /* A non-relaxed TLS call. The target is the
6626 plt-resident trampoline and nothing to do
6627 with the symbol. */
6628 BFD_ASSERT (htab->tls_trampoline > 0);
6629 sym_sec = htab->root.splt;
6630 sym_value = htab->tls_trampoline;
6631 hash = 0;
34e77a92 6632 st_type = STT_FUNC;
35fc36a8 6633 branch_type = ST_BRANCH_TO_ARM;
0855e32b
NS		 6634 }
6635 else if (!hash)
906e58ca
NC		 6636 {
6637 /* It's a local symbol. */
6638 Elf_Internal_Sym *sym;
906e58ca
NC		 6639
6640 if (local_syms == NULL)
6641 {
6642 local_syms
6643 = (Elf_Internal_Sym *) symtab_hdr->contents;
6644 if (local_syms == NULL)
6645 local_syms
6646 = bfd_elf_get_elf_syms (input_bfd, symtab_hdr,
6647 symtab_hdr->sh_info, 0,
6648 NULL, NULL, NULL);
6649 if (local_syms == NULL)
6650 goto error_ret_free_internal;
6651 }
6652
6653 sym = local_syms + r_indx;
f6d250ce
TS		 6654 if (sym->st_shndx == SHN_UNDEF)
6655 sym_sec = bfd_und_section_ptr;
6656 else if (sym->st_shndx == SHN_ABS)
6657 sym_sec = bfd_abs_section_ptr;
6658 else if (sym->st_shndx == SHN_COMMON)
6659 sym_sec = bfd_com_section_ptr;
6660 else
6661 sym_sec =
6662 bfd_section_from_elf_index (input_bfd, sym->st_shndx);
6663
ffcb4889
NS		 6664 if (!sym_sec)
6665 /* This is an undefined symbol. It can never
6a631e86 6666 be resolved. */
ffcb4889 6667 continue;
fe33d2fa 6668
906e58ca
NC		 6669 if (ELF_ST_TYPE (sym->st_info) != STT_SECTION)
6670 sym_value = sym->st_value;
6671 destination = (sym_value + irela->r_addend
6672 + sym_sec->output_offset
6673 + sym_sec->output_section->vma);
34e77a92 6674 st_type = ELF_ST_TYPE (sym->st_info);
39d911fc
TP		 6675 branch_type =
6676 ARM_GET_SYM_BRANCH_TYPE (sym->st_target_internal);
7413f23f
DJ		 6677 sym_name
6678 = bfd_elf_string_from_elf_section (input_bfd,
6679 symtab_hdr->sh_link,
6680 sym->st_name);
906e58ca
NC		 6681 }
6682 else
6683 {
6684 /* It's an external symbol. */
906e58ca
NC		 6685 while (hash->root.root.type == bfd_link_hash_indirect
6686 || hash->root.root.type == bfd_link_hash_warning)
6687 hash = ((struct elf32_arm_link_hash_entry *)
6688 hash->root.root.u.i.link);
6689
6690 if (hash->root.root.type == bfd_link_hash_defined
6691 || hash->root.root.type == bfd_link_hash_defweak)
6692 {
6693 sym_sec = hash->root.root.u.def.section;
6694 sym_value = hash->root.root.u.def.value;
022f8312
CL		 6695
6696 struct elf32_arm_link_hash_table *globals =
6697 elf32_arm_hash_table (info);
6698
6699 /* For a destination in a shared library,
6700 use the PLT stub as target address to
6701 decide whether a branch stub is
6702 needed. */
4dfe6ac6 6703 if (globals != NULL
362d30a1 6704 && globals->root.splt != NULL
4dfe6ac6 6705 && hash != NULL
022f8312
CL		 6706 && hash->root.plt.offset != (bfd_vma) -1)
6707 {
362d30a1 6708 sym_sec = globals->root.splt;
022f8312
CL		 6709 sym_value = hash->root.plt.offset;
6710 if (sym_sec->output_section != NULL)
6711 destination = (sym_value
6712 + sym_sec->output_offset
6713 + sym_sec->output_section->vma);
6714 }
6715 else if (sym_sec->output_section != NULL)
906e58ca
NC		 6716 destination = (sym_value + irela->r_addend
6717 + sym_sec->output_offset
6718 + sym_sec->output_section->vma);
6719 }
69c5861e
CL		 6720 else if ((hash->root.root.type == bfd_link_hash_undefined)
6721 || (hash->root.root.type == bfd_link_hash_undefweak))
6722 {
6723 /* For a shared library, use the PLT stub as
6724 target address to decide whether a long
6725 branch stub is needed.
6726 For absolute code, they cannot be handled. */
6727 struct elf32_arm_link_hash_table *globals =
6728 elf32_arm_hash_table (info);
6729
4dfe6ac6 6730 if (globals != NULL
362d30a1 6731 && globals->root.splt != NULL
4dfe6ac6 6732 && hash != NULL
69c5861e
CL		 6733 && hash->root.plt.offset != (bfd_vma) -1)
6734 {
362d30a1 6735 sym_sec = globals->root.splt;
69c5861e
CL		 6736 sym_value = hash->root.plt.offset;
6737 if (sym_sec->output_section != NULL)
6738 destination = (sym_value
6739 + sym_sec->output_offset
6740 + sym_sec->output_section->vma);
6741 }
6742 else
6743 continue;
6744 }
906e58ca
NC		 6745 else
6746 {
6747 bfd_set_error (bfd_error_bad_value);
6748 goto error_ret_free_internal;
6749 }
34e77a92 6750 st_type = hash->root.type;
39d911fc
TP		 6751 branch_type =
6752 ARM_GET_SYM_BRANCH_TYPE (hash->root.target_internal);
7413f23f 6753 sym_name = hash->root.root.root.string;
906e58ca
NC		 6754 }
6755
48229727 6756 do
7413f23f 6757 {
b715f643 6758 bfd_boolean new_stub;
0955507f 6759 struct elf32_arm_stub_hash_entry *stub_entry;
b715f643 6760
48229727
JB		 6761 /* Determine what (if any) linker stub is needed. */
6762 stub_type = arm_type_of_stub (info, section, irela,
34e77a92
RS		 6763 st_type, &branch_type,
6764 hash, destination, sym_sec,
48229727
JB		 6765 input_bfd, sym_name);
6766 if (stub_type == arm_stub_none)
6767 break;
6768
48229727
JB		 6769 /* We've either created a stub for this reloc already,
6770 or we are about to. */
0955507f 6771 stub_entry =
b715f643
TP		 6772 elf32_arm_create_stub (htab, stub_type, section, irela,
6773 sym_sec, hash,
6774 (char *) sym_name, sym_value,
6775 branch_type, &new_stub);
7413f23f 6776
0955507f 6777 created_stub = stub_entry != NULL;
b715f643
TP		 6778 if (!created_stub)
6779 goto error_ret_free_internal;
6780 else if (!new_stub)
6781 break;
99059e56 6782 else
b715f643 6783 stub_changed = TRUE;
99059e56
RM		 6784 }
6785 while (0);
6786
6787 /* Look for relocations which might trigger Cortex-A8
6788 erratum. */
6789 if (htab->fix_cortex_a8
6790 && (r_type == (unsigned int) R_ARM_THM_JUMP24
6791 || r_type == (unsigned int) R_ARM_THM_JUMP19
6792 || r_type == (unsigned int) R_ARM_THM_CALL
6793 || r_type == (unsigned int) R_ARM_THM_XPC22))
6794 {
6795 bfd_vma from = section->output_section->vma
6796 + section->output_offset
6797 + irela->r_offset;
6798
6799 if ((from & 0xfff) == 0xffe)
6800 {
6801 /* Found a candidate. Note we haven't checked the
6802 destination is within 4K here: if we do so (and
6803 don't create an entry in a8_relocs) we can't tell
6804 that a branch should have been relocated when
6805 scanning later. */
6806 if (num_a8_relocs == a8_reloc_table_size)
6807 {
6808 a8_reloc_table_size *= 2;
6809 a8_relocs = (struct a8_erratum_reloc *)
6810 bfd_realloc (a8_relocs,
6811 sizeof (struct a8_erratum_reloc)
6812 * a8_reloc_table_size);
6813 }
6814
6815 a8_relocs[num_a8_relocs].from = from;
6816 a8_relocs[num_a8_relocs].destination = destination;
6817 a8_relocs[num_a8_relocs].r_type = r_type;
6818 a8_relocs[num_a8_relocs].branch_type = branch_type;
6819 a8_relocs[num_a8_relocs].sym_name = sym_name;
6820 a8_relocs[num_a8_relocs].non_a8_stub = created_stub;
6821 a8_relocs[num_a8_relocs].hash = hash;
6822
6823 num_a8_relocs++;
6824 }
6825 }
906e58ca
NC		 6826 }
6827
99059e56
RM		 6828 /* We're done with the internal relocs, free them. */
6829 if (elf_section_data (section)->relocs == NULL)
6830 free (internal_relocs);
6831 }
48229727 6832
99059e56 6833 if (htab->fix_cortex_a8)
48229727 6834 {
99059e56
RM		 6835 /* Sort relocs which might apply to Cortex-A8 erratum. */
6836 qsort (a8_relocs, num_a8_relocs,
eb7c4339 6837 sizeof (struct a8_erratum_reloc),
99059e56 6838 &a8_reloc_compare);
48229727 6839
99059e56
RM		 6840 /* Scan for branches which might trigger Cortex-A8 erratum. */
6841 if (cortex_a8_erratum_scan (input_bfd, info, &a8_fixes,
48229727 6842 &num_a8_fixes, &a8_fix_table_size,
eb7c4339
NS		 6843 a8_relocs, num_a8_relocs,
6844 prev_num_a8_fixes, &stub_changed)
6845 != 0)
48229727 6846 goto error_ret_free_local;
5e681ec4 6847 }
7f991970
AM		 6848
6849 if (local_syms != NULL
6850 && symtab_hdr->contents != (unsigned char *) local_syms)
6851 {
6852 if (!info->keep_memory)
6853 free (local_syms);
6854 else
6855 symtab_hdr->contents = (unsigned char *) local_syms;
6856 }
5e681ec4
PB		 6857 }
6858
0955507f
TP		 6859 if (first_veneer_scan
6860 && !set_cmse_veneer_addr_from_implib (info, htab,
6861 &cmse_stub_created))
6862 ret = FALSE;
6863
eb7c4339 6864 if (prev_num_a8_fixes != num_a8_fixes)
99059e56 6865 stub_changed = TRUE;
48229727 6866
906e58ca
NC		 6867 if (!stub_changed)
6868 break;
5e681ec4 6869
906e58ca
NC		 6870 /* OK, we've added some stubs. Find out the new size of the
6871 stub sections. */
6872 for (stub_sec = htab->stub_bfd->sections;
6873 stub_sec != NULL;
6874 stub_sec = stub_sec->next)
3e6b1042
DJ		 6875 {
6876 /* Ignore non-stub sections. */
6877 if (!strstr (stub_sec->name, STUB_SUFFIX))
6878 continue;
6879
6880 stub_sec->size = 0;
6881 }
b34b2d70 6882
0955507f
TP		 6883 /* Add new SG veneers after those already in the input import
6884 library. */
6885 for (stub_type = arm_stub_none + 1; stub_type < max_stub_type;
6886 stub_type++)
6887 {
6888 bfd_vma *start_offset_p;
6889 asection **stub_sec_p;
6890
6891 start_offset_p = arm_new_stubs_start_offset_ptr (htab, stub_type);
6892 stub_sec_p = arm_dedicated_stub_input_section_ptr (htab, stub_type);
6893 if (start_offset_p == NULL)
6894 continue;
6895
6896 BFD_ASSERT (stub_sec_p != NULL);
6897 if (*stub_sec_p != NULL)
6898 (*stub_sec_p)->size = *start_offset_p;
6899 }
6900
d7c5bd02 6901 /* Compute stub section size, considering padding. */
906e58ca 6902 bfd_hash_traverse (&htab->stub_hash_table, arm_size_one_stub, htab);
d7c5bd02
TP		 6903 for (stub_type = arm_stub_none + 1; stub_type < max_stub_type;
6904 stub_type++)
6905 {
6906 int size, padding;
6907 asection **stub_sec_p;
6908
6909 padding = arm_dedicated_stub_section_padding (stub_type);
6910 stub_sec_p = arm_dedicated_stub_input_section_ptr (htab, stub_type);
6911 /* Skip if no stub input section or no stub section padding
6912 required. */
6913 if ((stub_sec_p != NULL && *stub_sec_p == NULL) || padding == 0)
6914 continue;
6915 /* Stub section padding required but no dedicated section. */
6916 BFD_ASSERT (stub_sec_p);
6917
6918 size = (*stub_sec_p)->size;
6919 size = (size + padding - 1) & ~(padding - 1);
6920 (*stub_sec_p)->size = size;
6921 }
906e58ca 6922
48229727
JB		 6923 /* Add Cortex-A8 erratum veneers to stub section sizes too. */
6924 if (htab->fix_cortex_a8)
99059e56
RM		 6925 for (i = 0; i < num_a8_fixes; i++)
6926 {
48229727 6927 stub_sec = elf32_arm_create_or_find_stub_sec (NULL,
daa4adae 6928 a8_fixes[i].section, htab, a8_fixes[i].stub_type);
48229727
JB		 6929
6930 if (stub_sec == NULL)
7f991970 6931 return FALSE;
48229727 6932
99059e56
RM		 6933 stub_sec->size
6934 += find_stub_size_and_template (a8_fixes[i].stub_type, NULL,
6935 NULL);
6936 }
48229727
JB		 6937
6938
906e58ca
NC		 6939 /* Ask the linker to do its stuff. */
6940 (*htab->layout_sections_again) ();
4ba2ef8f 6941 first_veneer_scan = FALSE;
ba93b8ac
DJ		 6942 }
6943
48229727
JB		 6944 /* Add stubs for Cortex-A8 erratum fixes now. */
6945 if (htab->fix_cortex_a8)
6946 {
6947 for (i = 0; i < num_a8_fixes; i++)
99059e56
RM		 6948 {
6949 struct elf32_arm_stub_hash_entry *stub_entry;
6950 char *stub_name = a8_fixes[i].stub_name;
6951 asection *section = a8_fixes[i].section;
6952 unsigned int section_id = a8_fixes[i].section->id;
6953 asection *link_sec = htab->stub_group[section_id].link_sec;
6954 asection *stub_sec = htab->stub_group[section_id].stub_sec;
6955 const insn_sequence *template_sequence;
6956 int template_size, size = 0;
6957
6958 stub_entry = arm_stub_hash_lookup (&htab->stub_hash_table, stub_name,
6959 TRUE, FALSE);
6960 if (stub_entry == NULL)
6961 {
871b3ab2 6962 _bfd_error_handler (_("%pB: cannot create stub entry %s"),
4eca0228 6963 section->owner, stub_name);
99059e56
RM		 6964 return FALSE;
6965 }
6966
6967 stub_entry->stub_sec = stub_sec;
0955507f 6968 stub_entry->stub_offset = (bfd_vma) -1;
99059e56
RM		 6969 stub_entry->id_sec = link_sec;
6970 stub_entry->stub_type = a8_fixes[i].stub_type;
8d9d9490 6971 stub_entry->source_value = a8_fixes[i].offset;
99059e56 6972 stub_entry->target_section = a8_fixes[i].section;
8d9d9490 6973 stub_entry->target_value = a8_fixes[i].target_offset;
99059e56 6974 stub_entry->orig_insn = a8_fixes[i].orig_insn;
35fc36a8 6975 stub_entry->branch_type = a8_fixes[i].branch_type;
48229727 6976
99059e56
RM		 6977 size = find_stub_size_and_template (a8_fixes[i].stub_type,
6978 &template_sequence,
6979 &template_size);
48229727 6980
99059e56
RM		 6981 stub_entry->stub_size = size;
6982 stub_entry->stub_template = template_sequence;
6983 stub_entry->stub_template_size = template_size;
6984 }
48229727
JB		 6985
6986 /* Stash the Cortex-A8 erratum fix array for use later in
99059e56 6987 elf32_arm_write_section(). */
48229727
JB		 6988 htab->a8_erratum_fixes = a8_fixes;
6989 htab->num_a8_erratum_fixes = num_a8_fixes;
6990 }
6991 else
6992 {
6993 htab->a8_erratum_fixes = NULL;
6994 htab->num_a8_erratum_fixes = 0;
6995 }
0955507f 6996 return ret;
5e681ec4
PB		 6997}
6998
906e58ca
NC		 6999/* Build all the stubs associated with the current output file. The
7000 stubs are kept in a hash table attached to the main linker hash
7001 table. We also set up the .plt entries for statically linked PIC
7002 functions here. This function is called via arm_elf_finish in the
7003 linker. */
252b5132 7004
906e58ca
NC		 7005bfd_boolean
7006elf32_arm_build_stubs (struct bfd_link_info *info)
252b5132 7007{
906e58ca
NC		 7008 asection *stub_sec;
7009 struct bfd_hash_table *table;
0955507f 7010 enum elf32_arm_stub_type stub_type;
906e58ca 7011 struct elf32_arm_link_hash_table *htab;
252b5132 7012
906e58ca 7013 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 7014 if (htab == NULL)
7015 return FALSE;
252b5132 7016
906e58ca
NC		 7017 for (stub_sec = htab->stub_bfd->sections;
7018 stub_sec != NULL;
7019 stub_sec = stub_sec->next)
252b5132 7020 {
906e58ca
NC		 7021 bfd_size_type size;
7022
8029a119 7023 /* Ignore non-stub sections. */
906e58ca
NC		 7024 if (!strstr (stub_sec->name, STUB_SUFFIX))
7025 continue;
7026
d7c5bd02 7027 /* Allocate memory to hold the linker stubs. Zeroing the stub sections
0955507f
TP		 7028 must at least be done for stub section requiring padding and for SG
7029 veneers to ensure that a non secure code branching to a removed SG
7030 veneer causes an error. */
906e58ca 7031 size = stub_sec->size;
21d799b5 7032 stub_sec->contents = (unsigned char *) bfd_zalloc (htab->stub_bfd, size);
906e58ca
NC		 7033 if (stub_sec->contents == NULL && size != 0)
7034 return FALSE;
0955507f 7035
906e58ca 7036 stub_sec->size = 0;
252b5132
RH		 7037 }
7038
0955507f
TP		 7039 /* Add new SG veneers after those already in the input import library. */
7040 for (stub_type = arm_stub_none + 1; stub_type < max_stub_type; stub_type++)
7041 {
7042 bfd_vma *start_offset_p;
7043 asection **stub_sec_p;
7044
7045 start_offset_p = arm_new_stubs_start_offset_ptr (htab, stub_type);
7046 stub_sec_p = arm_dedicated_stub_input_section_ptr (htab, stub_type);
7047 if (start_offset_p == NULL)
7048 continue;
7049
7050 BFD_ASSERT (stub_sec_p != NULL);
7051 if (*stub_sec_p != NULL)
7052 (*stub_sec_p)->size = *start_offset_p;
7053 }
7054
906e58ca
NC		 7055 /* Build the stubs as directed by the stub hash table. */
7056 table = &htab->stub_hash_table;
7057 bfd_hash_traverse (table, arm_build_one_stub, info);
eb7c4339
NS		 7058 if (htab->fix_cortex_a8)
7059 {
7060 /* Place the cortex a8 stubs last. */
7061 htab->fix_cortex_a8 = -1;
7062 bfd_hash_traverse (table, arm_build_one_stub, info);
7063 }
252b5132 7064
906e58ca 7065 return TRUE;
252b5132
RH		 7066}
7067
9b485d32
NC		 7068/* Locate the Thumb encoded calling stub for NAME. */
7069
252b5132 7070static struct elf_link_hash_entry *
57e8b36a
NC		 7071find_thumb_glue (struct bfd_link_info *link_info,
7072 const char *name,
f2a9dd69 7073 char **error_message)
252b5132
RH		 7074{
7075 char *tmp_name;
7076 struct elf_link_hash_entry *hash;
7077 struct elf32_arm_link_hash_table *hash_table;
7078
7079 /* We need a pointer to the armelf specific hash table. */
7080 hash_table = elf32_arm_hash_table (link_info);
4dfe6ac6
NC		 7081 if (hash_table == NULL)
7082 return NULL;
252b5132 7083
21d799b5 7084 tmp_name = (char *) bfd_malloc ((bfd_size_type) strlen (name)
99059e56 7085 + strlen (THUMB2ARM_GLUE_ENTRY_NAME) + 1);
252b5132
RH		 7086
7087 BFD_ASSERT (tmp_name);
7088
7089 sprintf (tmp_name, THUMB2ARM_GLUE_ENTRY_NAME, name);
7090
7091 hash = elf_link_hash_lookup
b34976b6 7092 (&(hash_table)->root, tmp_name, FALSE, FALSE, TRUE);
252b5132 7093
b1657152 7094 if (hash == NULL
90b6238f
AM		 7095 && asprintf (error_message, _("unable to find %s glue '%s' for '%s'"),
7096 "Thumb", tmp_name, name) == -1)
b1657152 7097 *error_message = (char *) bfd_errmsg (bfd_error_system_call);
252b5132
RH		 7098
7099 free (tmp_name);
7100
7101 return hash;
7102}
7103
9b485d32
NC		 7104/* Locate the ARM encoded calling stub for NAME. */
7105
252b5132 7106static struct elf_link_hash_entry *
57e8b36a
NC		 7107find_arm_glue (struct bfd_link_info *link_info,
7108 const char *name,
f2a9dd69 7109 char **error_message)
252b5132
RH		 7110{
7111 char *tmp_name;
7112 struct elf_link_hash_entry *myh;
7113 struct elf32_arm_link_hash_table *hash_table;
7114
7115 /* We need a pointer to the elfarm specific hash table. */
7116 hash_table = elf32_arm_hash_table (link_info);
4dfe6ac6
NC		 7117 if (hash_table == NULL)
7118 return NULL;
252b5132 7119
21d799b5 7120 tmp_name = (char *) bfd_malloc ((bfd_size_type) strlen (name)
99059e56 7121 + strlen (ARM2THUMB_GLUE_ENTRY_NAME) + 1);
252b5132
RH		 7122 BFD_ASSERT (tmp_name);
7123
7124 sprintf (tmp_name, ARM2THUMB_GLUE_ENTRY_NAME, name);
7125
7126 myh = elf_link_hash_lookup
b34976b6 7127 (&(hash_table)->root, tmp_name, FALSE, FALSE, TRUE);
252b5132 7128
b1657152 7129 if (myh == NULL
90b6238f
AM		 7130 && asprintf (error_message, _("unable to find %s glue '%s' for '%s'"),
7131 "ARM", tmp_name, name) == -1)
b1657152 7132 *error_message = (char *) bfd_errmsg (bfd_error_system_call);
252b5132
RH		 7133
7134 free (tmp_name);
7135
7136 return myh;
7137}
7138
8f6277f5 7139/* ARM->Thumb glue (static images):
252b5132
RH		 7140
7141 .arm
7142 __func_from_arm:
7143 ldr r12, __func_addr
7144 bx r12
7145 __func_addr:
906e58ca 7146 .word func @ behave as if you saw a ARM_32 reloc.
252b5132 7147
26079076
PB		 7148 (v5t static images)
7149 .arm
7150 __func_from_arm:
7151 ldr pc, __func_addr
7152 __func_addr:
906e58ca 7153 .word func @ behave as if you saw a ARM_32 reloc.
26079076 7154
8f6277f5
PB		 7155 (relocatable images)
7156 .arm
7157 __func_from_arm:
7158 ldr r12, __func_offset
7159 add r12, r12, pc
7160 bx r12
7161 __func_offset:
8029a119 7162 .word func - . */
8f6277f5
PB		 7163
7164#define ARM2THUMB_STATIC_GLUE_SIZE 12
252b5132
RH		 7165static const insn32 a2t1_ldr_insn = 0xe59fc000;
7166static const insn32 a2t2_bx_r12_insn = 0xe12fff1c;
7167static const insn32 a2t3_func_addr_insn = 0x00000001;
7168
26079076
PB		 7169#define ARM2THUMB_V5_STATIC_GLUE_SIZE 8
7170static const insn32 a2t1v5_ldr_insn = 0xe51ff004;
7171static const insn32 a2t2v5_func_addr_insn = 0x00000001;
7172
8f6277f5
PB		 7173#define ARM2THUMB_PIC_GLUE_SIZE 16
7174static const insn32 a2t1p_ldr_insn = 0xe59fc004;
7175static const insn32 a2t2p_add_pc_insn = 0xe08cc00f;
7176static const insn32 a2t3p_bx_r12_insn = 0xe12fff1c;
7177
07d6d2b8 7178/* Thumb->ARM: Thumb->(non-interworking aware) ARM
252b5132 7179
07d6d2b8
AM		 7180 .thumb .thumb
7181 .align 2 .align 2
7182 __func_from_thumb: __func_from_thumb:
7183 bx pc push {r6, lr}
7184 nop ldr r6, __func_addr
7185 .arm mov lr, pc
7186 b func bx r6
99059e56
RM		 7187 .arm
7188 ;; back_to_thumb
7189 ldmia r13! {r6, lr}
7190 bx lr
7191 __func_addr:
07d6d2b8 7192 .word func */
252b5132
RH		 7193
7194#define THUMB2ARM_GLUE_SIZE 8
7195static const insn16 t2a1_bx_pc_insn = 0x4778;
7196static const insn16 t2a2_noop_insn = 0x46c0;
7197static const insn32 t2a3_b_insn = 0xea000000;
7198
c7b8f16e 7199#define VFP11_ERRATUM_VENEER_SIZE 8
a504d23a
LA		 7200#define STM32L4XX_ERRATUM_LDM_VENEER_SIZE 16
7201#define STM32L4XX_ERRATUM_VLDM_VENEER_SIZE 24
c7b8f16e 7202
845b51d6
PB		 7203#define ARM_BX_VENEER_SIZE 12
7204static const insn32 armbx1_tst_insn = 0xe3100001;
7205static const insn32 armbx2_moveq_insn = 0x01a0f000;
7206static const insn32 armbx3_bx_insn = 0xe12fff10;
7207
7e392df6 7208#ifndef ELFARM_NABI_C_INCLUDED
8029a119
NC		 7209static void
7210arm_allocate_glue_section_space (bfd * abfd, bfd_size_type size, const char * name)
252b5132
RH		 7211{
7212 asection * s;
8029a119 7213 bfd_byte * contents;
252b5132 7214
8029a119 7215 if (size == 0)
3e6b1042
DJ		 7216 {
7217 /* Do not include empty glue sections in the output. */
7218 if (abfd != NULL)
7219 {
3d4d4302 7220 s = bfd_get_linker_section (abfd, name);
3e6b1042
DJ		 7221 if (s != NULL)
7222 s->flags |= SEC_EXCLUDE;
7223 }
7224 return;
7225 }
252b5132 7226
8029a119 7227 BFD_ASSERT (abfd != NULL);
252b5132 7228
3d4d4302 7229 s = bfd_get_linker_section (abfd, name);
8029a119 7230 BFD_ASSERT (s != NULL);
252b5132 7231
b0f4fbf8 7232 contents = (bfd_byte *) bfd_zalloc (abfd, size);
252b5132 7233
8029a119
NC		 7234 BFD_ASSERT (s->size == size);
7235 s->contents = contents;
7236}
906e58ca 7237
8029a119
NC		 7238bfd_boolean
7239bfd_elf32_arm_allocate_interworking_sections (struct bfd_link_info * info)
7240{
7241 struct elf32_arm_link_hash_table * globals;
906e58ca 7242
8029a119
NC		 7243 globals = elf32_arm_hash_table (info);
7244 BFD_ASSERT (globals != NULL);
906e58ca 7245
8029a119
NC		 7246 arm_allocate_glue_section_space (globals->bfd_of_glue_owner,
7247 globals->arm_glue_size,
7248 ARM2THUMB_GLUE_SECTION_NAME);
906e58ca 7249
8029a119
NC		 7250 arm_allocate_glue_section_space (globals->bfd_of_glue_owner,
7251 globals->thumb_glue_size,
7252 THUMB2ARM_GLUE_SECTION_NAME);
252b5132 7253
8029a119
NC		 7254 arm_allocate_glue_section_space (globals->bfd_of_glue_owner,
7255 globals->vfp11_erratum_glue_size,
7256 VFP11_ERRATUM_VENEER_SECTION_NAME);
845b51d6 7257
a504d23a
LA		 7258 arm_allocate_glue_section_space (globals->bfd_of_glue_owner,
7259 globals->stm32l4xx_erratum_glue_size,
7260 STM32L4XX_ERRATUM_VENEER_SECTION_NAME);
7261
8029a119
NC		 7262 arm_allocate_glue_section_space (globals->bfd_of_glue_owner,
7263 globals->bx_glue_size,
845b51d6
PB		 7264 ARM_BX_GLUE_SECTION_NAME);
7265
b34976b6 7266 return TRUE;
252b5132
RH		 7267}
7268
a4fd1a8e 7269/* Allocate space and symbols for calling a Thumb function from Arm mode.
906e58ca
NC		 7270 returns the symbol identifying the stub. */
7271
a4fd1a8e 7272static struct elf_link_hash_entry *
57e8b36a
NC		 7273record_arm_to_thumb_glue (struct bfd_link_info * link_info,
7274 struct elf_link_hash_entry * h)
252b5132
RH		 7275{
7276 const char * name = h->root.root.string;
63b0f745 7277 asection * s;
252b5132
RH		 7278 char * tmp_name;
7279 struct elf_link_hash_entry * myh;
14a793b2 7280 struct bfd_link_hash_entry * bh;
252b5132 7281 struct elf32_arm_link_hash_table * globals;
dc810e39 7282 bfd_vma val;
2f475487 7283 bfd_size_type size;
252b5132
RH		 7284
7285 globals = elf32_arm_hash_table (link_info);
252b5132
RH		 7286 BFD_ASSERT (globals != NULL);
7287 BFD_ASSERT (globals->bfd_of_glue_owner != NULL);
7288
3d4d4302 7289 s = bfd_get_linker_section
252b5132
RH		 7290 (globals->bfd_of_glue_owner, ARM2THUMB_GLUE_SECTION_NAME);
7291
252b5132
RH		 7292 BFD_ASSERT (s != NULL);
7293
21d799b5 7294 tmp_name = (char *) bfd_malloc ((bfd_size_type) strlen (name)
99059e56 7295 + strlen (ARM2THUMB_GLUE_ENTRY_NAME) + 1);
252b5132
RH		 7296 BFD_ASSERT (tmp_name);
7297
7298 sprintf (tmp_name, ARM2THUMB_GLUE_ENTRY_NAME, name);
7299
7300 myh = elf_link_hash_lookup
b34976b6 7301 (&(globals)->root, tmp_name, FALSE, FALSE, TRUE);
252b5132
RH		 7302
7303 if (myh != NULL)
7304 {
9b485d32 7305 /* We've already seen this guy. */
252b5132 7306 free (tmp_name);
a4fd1a8e 7307 return myh;
252b5132
RH		 7308 }
7309
57e8b36a
NC		 7310 /* The only trick here is using hash_table->arm_glue_size as the value.
7311 Even though the section isn't allocated yet, this is where we will be
3dccd7b7
DJ		 7312 putting it. The +1 on the value marks that the stub has not been
7313 output yet - not that it is a Thumb function. */
14a793b2 7314 bh = NULL;
dc810e39
AM		 7315 val = globals->arm_glue_size + 1;
7316 _bfd_generic_link_add_one_symbol (link_info, globals->bfd_of_glue_owner,
7317 tmp_name, BSF_GLOBAL, s, val,
b34976b6 7318 NULL, TRUE, FALSE, &bh);
252b5132 7319
b7693d02
DJ		 7320 myh = (struct elf_link_hash_entry *) bh;
7321 myh->type = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
7322 myh->forced_local = 1;
7323
252b5132
RH		 7324 free (tmp_name);
7325
0e1862bb
L		 7326 if (bfd_link_pic (link_info)
7327 || globals->root.is_relocatable_executable
27e55c4d 7328 || globals->pic_veneer)
2f475487 7329 size = ARM2THUMB_PIC_GLUE_SIZE;
26079076
PB		 7330 else if (globals->use_blx)
7331 size = ARM2THUMB_V5_STATIC_GLUE_SIZE;
8f6277f5 7332 else
2f475487
AM		 7333 size = ARM2THUMB_STATIC_GLUE_SIZE;
7334
7335 s->size += size;
7336 globals->arm_glue_size += size;
252b5132 7337
a4fd1a8e 7338 return myh;
252b5132
RH		 7339}
7340
845b51d6
PB		 7341/* Allocate space for ARMv4 BX veneers. */
7342
7343static void
7344record_arm_bx_glue (struct bfd_link_info * link_info, int reg)
7345{
7346 asection * s;
7347 struct elf32_arm_link_hash_table *globals;
7348 char *tmp_name;
7349 struct elf_link_hash_entry *myh;
7350 struct bfd_link_hash_entry *bh;
7351 bfd_vma val;
7352
7353 /* BX PC does not need a veneer. */
7354 if (reg == 15)
7355 return;
7356
7357 globals = elf32_arm_hash_table (link_info);
845b51d6
PB		 7358 BFD_ASSERT (globals != NULL);
7359 BFD_ASSERT (globals->bfd_of_glue_owner != NULL);
7360
7361 /* Check if this veneer has already been allocated. */
7362 if (globals->bx_glue_offset[reg])
7363 return;
7364
3d4d4302 7365 s = bfd_get_linker_section
845b51d6
PB		 7366 (globals->bfd_of_glue_owner, ARM_BX_GLUE_SECTION_NAME);
7367
7368 BFD_ASSERT (s != NULL);
7369
7370 /* Add symbol for veneer. */
21d799b5
NC		 7371 tmp_name = (char *)
7372 bfd_malloc ((bfd_size_type) strlen (ARM_BX_GLUE_ENTRY_NAME) + 1);
845b51d6 7373 BFD_ASSERT (tmp_name);
906e58ca 7374
845b51d6 7375 sprintf (tmp_name, ARM_BX_GLUE_ENTRY_NAME, reg);
906e58ca 7376
845b51d6
PB		 7377 myh = elf_link_hash_lookup
7378 (&(globals)->root, tmp_name, FALSE, FALSE, FALSE);
906e58ca 7379
845b51d6 7380 BFD_ASSERT (myh == NULL);
906e58ca 7381
845b51d6
PB		 7382 bh = NULL;
7383 val = globals->bx_glue_size;
7384 _bfd_generic_link_add_one_symbol (link_info, globals->bfd_of_glue_owner,
99059e56
RM		 7385 tmp_name, BSF_FUNCTION | BSF_LOCAL, s, val,
7386 NULL, TRUE, FALSE, &bh);
845b51d6
PB		 7387
7388 myh = (struct elf_link_hash_entry *) bh;
7389 myh->type = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
7390 myh->forced_local = 1;
7391
7392 s->size += ARM_BX_VENEER_SIZE;
7393 globals->bx_glue_offset[reg] = globals->bx_glue_size | 2;
7394 globals->bx_glue_size += ARM_BX_VENEER_SIZE;
7395}
7396
7397
c7b8f16e
JB		 7398/* Add an entry to the code/data map for section SEC. */
7399
7400static void
7401elf32_arm_section_map_add (asection *sec, char type, bfd_vma vma)
7402{
7403 struct _arm_elf_section_data *sec_data = elf32_arm_section_data (sec);
7404 unsigned int newidx;
906e58ca 7405
c7b8f16e
JB		 7406 if (sec_data->map == NULL)
7407 {
21d799b5 7408 sec_data->map = (elf32_arm_section_map *)
99059e56 7409 bfd_malloc (sizeof (elf32_arm_section_map));
c7b8f16e
JB		 7410 sec_data->mapcount = 0;
7411 sec_data->mapsize = 1;
7412 }
906e58ca 7413
c7b8f16e 7414 newidx = sec_data->mapcount++;
906e58ca 7415
c7b8f16e
JB		 7416 if (sec_data->mapcount > sec_data->mapsize)
7417 {
7418 sec_data->mapsize *= 2;
21d799b5 7419 sec_data->map = (elf32_arm_section_map *)
99059e56
RM		 7420 bfd_realloc_or_free (sec_data->map, sec_data->mapsize
7421 * sizeof (elf32_arm_section_map));
515ef31d
NC		 7422 }
7423
7424 if (sec_data->map)
7425 {
7426 sec_data->map[newidx].vma = vma;
7427 sec_data->map[newidx].type = type;
c7b8f16e 7428 }
c7b8f16e
JB		 7429}
7430
7431
7432/* Record information about a VFP11 denorm-erratum veneer. Only ARM-mode
7433 veneers are handled for now. */
7434
7435static bfd_vma
7436record_vfp11_erratum_veneer (struct bfd_link_info *link_info,
99059e56
RM		 7437 elf32_vfp11_erratum_list *branch,
7438 bfd *branch_bfd,
7439 asection *branch_sec,
7440 unsigned int offset)
c7b8f16e
JB		 7441{
7442 asection *s;
7443 struct elf32_arm_link_hash_table *hash_table;
7444 char *tmp_name;
7445 struct elf_link_hash_entry *myh;
7446 struct bfd_link_hash_entry *bh;
7447 bfd_vma val;
7448 struct _arm_elf_section_data *sec_data;
c7b8f16e 7449 elf32_vfp11_erratum_list *newerr;
906e58ca 7450
c7b8f16e 7451 hash_table = elf32_arm_hash_table (link_info);
c7b8f16e
JB		 7452 BFD_ASSERT (hash_table != NULL);
7453 BFD_ASSERT (hash_table->bfd_of_glue_owner != NULL);
906e58ca 7454
3d4d4302 7455 s = bfd_get_linker_section
c7b8f16e 7456 (hash_table->bfd_of_glue_owner, VFP11_ERRATUM_VENEER_SECTION_NAME);
906e58ca 7457
c7b8f16e 7458 sec_data = elf32_arm_section_data (s);
906e58ca 7459
c7b8f16e 7460 BFD_ASSERT (s != NULL);
906e58ca 7461
21d799b5 7462 tmp_name = (char *) bfd_malloc ((bfd_size_type) strlen
99059e56 7463 (VFP11_ERRATUM_VENEER_ENTRY_NAME) + 10);
c7b8f16e 7464 BFD_ASSERT (tmp_name);
906e58ca 7465
c7b8f16e
JB		 7466 sprintf (tmp_name, VFP11_ERRATUM_VENEER_ENTRY_NAME,
7467 hash_table->num_vfp11_fixes);
906e58ca 7468
c7b8f16e
JB		 7469 myh = elf_link_hash_lookup
7470 (&(hash_table)->root, tmp_name, FALSE, FALSE, FALSE);
906e58ca 7471
c7b8f16e 7472 BFD_ASSERT (myh == NULL);
906e58ca 7473
c7b8f16e
JB		 7474 bh = NULL;
7475 val = hash_table->vfp11_erratum_glue_size;
7476 _bfd_generic_link_add_one_symbol (link_info, hash_table->bfd_of_glue_owner,
99059e56
RM		 7477 tmp_name, BSF_FUNCTION | BSF_LOCAL, s, val,
7478 NULL, TRUE, FALSE, &bh);
c7b8f16e
JB		 7479
7480 myh = (struct elf_link_hash_entry *) bh;
7481 myh->type = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
7482 myh->forced_local = 1;
7483
7484 /* Link veneer back to calling location. */
c7e2358a 7485 sec_data->erratumcount += 1;
21d799b5
NC		 7486 newerr = (elf32_vfp11_erratum_list *)
7487 bfd_zmalloc (sizeof (elf32_vfp11_erratum_list));
906e58ca 7488
c7b8f16e
JB		 7489 newerr->type = VFP11_ERRATUM_ARM_VENEER;
7490 newerr->vma = -1;
7491 newerr->u.v.branch = branch;
7492 newerr->u.v.id = hash_table->num_vfp11_fixes;
7493 branch->u.b.veneer = newerr;
7494
7495 newerr->next = sec_data->erratumlist;
7496 sec_data->erratumlist = newerr;
7497
7498 /* A symbol for the return from the veneer. */
7499 sprintf (tmp_name, VFP11_ERRATUM_VENEER_ENTRY_NAME "_r",
7500 hash_table->num_vfp11_fixes);
7501
7502 myh = elf_link_hash_lookup
7503 (&(hash_table)->root, tmp_name, FALSE, FALSE, FALSE);
906e58ca 7504
c7b8f16e
JB		 7505 if (myh != NULL)
7506 abort ();
7507
7508 bh = NULL;
7509 val = offset + 4;
7510 _bfd_generic_link_add_one_symbol (link_info, branch_bfd, tmp_name, BSF_LOCAL,
7511 branch_sec, val, NULL, TRUE, FALSE, &bh);
906e58ca 7512
c7b8f16e
JB		 7513 myh = (struct elf_link_hash_entry *) bh;
7514 myh->type = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
7515 myh->forced_local = 1;
7516
7517 free (tmp_name);
906e58ca 7518
c7b8f16e
JB		 7519 /* Generate a mapping symbol for the veneer section, and explicitly add an
7520 entry for that symbol to the code/data map for the section. */
7521 if (hash_table->vfp11_erratum_glue_size == 0)
7522 {
7523 bh = NULL;
7524 /* FIXME: Creates an ARM symbol. Thumb mode will need attention if it
99059e56 7525 ever requires this erratum fix. */
c7b8f16e
JB		 7526 _bfd_generic_link_add_one_symbol (link_info,
7527 hash_table->bfd_of_glue_owner, "$a",
7528 BSF_LOCAL, s, 0, NULL,
99059e56 7529 TRUE, FALSE, &bh);
c7b8f16e
JB		 7530
7531 myh = (struct elf_link_hash_entry *) bh;
7532 myh->type = ELF_ST_INFO (STB_LOCAL, STT_NOTYPE);
7533 myh->forced_local = 1;
906e58ca 7534
c7b8f16e 7535 /* The elf32_arm_init_maps function only cares about symbols from input
99059e56
RM		 7536 BFDs. We must make a note of this generated mapping symbol
7537 ourselves so that code byteswapping works properly in
7538 elf32_arm_write_section. */
c7b8f16e
JB		 7539 elf32_arm_section_map_add (s, 'a', 0);
7540 }
906e58ca 7541
c7b8f16e
JB		 7542 s->size += VFP11_ERRATUM_VENEER_SIZE;
7543 hash_table->vfp11_erratum_glue_size += VFP11_ERRATUM_VENEER_SIZE;
7544 hash_table->num_vfp11_fixes++;
906e58ca 7545
c7b8f16e
JB		 7546 /* The offset of the veneer. */
7547 return val;
7548}
7549
a504d23a
LA		 7550/* Record information about a STM32L4XX STM erratum veneer. Only THUMB-mode
7551 veneers need to be handled because used only in Cortex-M. */
7552
7553static bfd_vma
7554record_stm32l4xx_erratum_veneer (struct bfd_link_info *link_info,
7555 elf32_stm32l4xx_erratum_list *branch,
7556 bfd *branch_bfd,
7557 asection *branch_sec,
7558 unsigned int offset,
7559 bfd_size_type veneer_size)
7560{
7561 asection *s;
7562 struct elf32_arm_link_hash_table *hash_table;
7563 char *tmp_name;
7564 struct elf_link_hash_entry *myh;
7565 struct bfd_link_hash_entry *bh;
7566 bfd_vma val;
7567 struct _arm_elf_section_data *sec_data;
7568 elf32_stm32l4xx_erratum_list *newerr;
7569
7570 hash_table = elf32_arm_hash_table (link_info);
7571 BFD_ASSERT (hash_table != NULL);
7572 BFD_ASSERT (hash_table->bfd_of_glue_owner != NULL);
7573
7574 s = bfd_get_linker_section
7575 (hash_table->bfd_of_glue_owner, STM32L4XX_ERRATUM_VENEER_SECTION_NAME);
7576
7577 BFD_ASSERT (s != NULL);
7578
7579 sec_data = elf32_arm_section_data (s);
7580
7581 tmp_name = (char *) bfd_malloc ((bfd_size_type) strlen
7582 (STM32L4XX_ERRATUM_VENEER_ENTRY_NAME) + 10);
a504d23a
LA		 7583 BFD_ASSERT (tmp_name);
7584
7585 sprintf (tmp_name, STM32L4XX_ERRATUM_VENEER_ENTRY_NAME,
7586 hash_table->num_stm32l4xx_fixes);
7587
7588 myh = elf_link_hash_lookup
7589 (&(hash_table)->root, tmp_name, FALSE, FALSE, FALSE);
7590
7591 BFD_ASSERT (myh == NULL);
7592
7593 bh = NULL;
7594 val = hash_table->stm32l4xx_erratum_glue_size;
7595 _bfd_generic_link_add_one_symbol (link_info, hash_table->bfd_of_glue_owner,
7596 tmp_name, BSF_FUNCTION | BSF_LOCAL, s, val,
7597 NULL, TRUE, FALSE, &bh);
7598
7599 myh = (struct elf_link_hash_entry *) bh;
7600 myh->type = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
7601 myh->forced_local = 1;
7602
7603 /* Link veneer back to calling location. */
7604 sec_data->stm32l4xx_erratumcount += 1;
7605 newerr = (elf32_stm32l4xx_erratum_list *)
7606 bfd_zmalloc (sizeof (elf32_stm32l4xx_erratum_list));
7607
7608 newerr->type = STM32L4XX_ERRATUM_VENEER;
7609 newerr->vma = -1;
7610 newerr->u.v.branch = branch;
7611 newerr->u.v.id = hash_table->num_stm32l4xx_fixes;
7612 branch->u.b.veneer = newerr;
7613
7614 newerr->next = sec_data->stm32l4xx_erratumlist;
7615 sec_data->stm32l4xx_erratumlist = newerr;
7616
7617 /* A symbol for the return from the veneer. */
7618 sprintf (tmp_name, STM32L4XX_ERRATUM_VENEER_ENTRY_NAME "_r",
7619 hash_table->num_stm32l4xx_fixes);
7620
7621 myh = elf_link_hash_lookup
7622 (&(hash_table)->root, tmp_name, FALSE, FALSE, FALSE);
7623
7624 if (myh != NULL)
7625 abort ();
7626
7627 bh = NULL;
7628 val = offset + 4;
7629 _bfd_generic_link_add_one_symbol (link_info, branch_bfd, tmp_name, BSF_LOCAL,
7630 branch_sec, val, NULL, TRUE, FALSE, &bh);
7631
7632 myh = (struct elf_link_hash_entry *) bh;
7633 myh->type = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
7634 myh->forced_local = 1;
7635
7636 free (tmp_name);
7637
7638 /* Generate a mapping symbol for the veneer section, and explicitly add an
7639 entry for that symbol to the code/data map for the section. */
7640 if (hash_table->stm32l4xx_erratum_glue_size == 0)
7641 {
7642 bh = NULL;
7643 /* Creates a THUMB symbol since there is no other choice. */
7644 _bfd_generic_link_add_one_symbol (link_info,
7645 hash_table->bfd_of_glue_owner, "$t",
7646 BSF_LOCAL, s, 0, NULL,
7647 TRUE, FALSE, &bh);
7648
7649 myh = (struct elf_link_hash_entry *) bh;
7650 myh->type = ELF_ST_INFO (STB_LOCAL, STT_NOTYPE);
7651 myh->forced_local = 1;
7652
7653 /* The elf32_arm_init_maps function only cares about symbols from input
7654 BFDs. We must make a note of this generated mapping symbol
7655 ourselves so that code byteswapping works properly in
7656 elf32_arm_write_section. */
7657 elf32_arm_section_map_add (s, 't', 0);
7658 }
7659
7660 s->size += veneer_size;
7661 hash_table->stm32l4xx_erratum_glue_size += veneer_size;
7662 hash_table->num_stm32l4xx_fixes++;
7663
7664 /* The offset of the veneer. */
7665 return val;
7666}
7667
8029a119 7668#define ARM_GLUE_SECTION_FLAGS \
3e6b1042
DJ		 7669 (SEC_ALLOC | SEC_LOAD | SEC_HAS_CONTENTS | SEC_IN_MEMORY | SEC_CODE \
7670 | SEC_READONLY | SEC_LINKER_CREATED)
8029a119
NC		 7671
7672/* Create a fake section for use by the ARM backend of the linker. */
7673
7674static bfd_boolean
7675arm_make_glue_section (bfd * abfd, const char * name)
7676{
7677 asection * sec;
7678
3d4d4302 7679 sec = bfd_get_linker_section (abfd, name);
8029a119
NC		 7680 if (sec != NULL)
7681 /* Already made. */
7682 return TRUE;
7683
3d4d4302 7684 sec = bfd_make_section_anyway_with_flags (abfd, name, ARM_GLUE_SECTION_FLAGS);
8029a119
NC		 7685
7686 if (sec == NULL
fd361982 7687 || !bfd_set_section_alignment (sec, 2))
8029a119
NC		 7688 return FALSE;
7689
7690 /* Set the gc mark to prevent the section from being removed by garbage
7691 collection, despite the fact that no relocs refer to this section. */
7692 sec->gc_mark = 1;
7693
7694 return TRUE;
7695}
7696
1db37fe6
YG		 7697/* Set size of .plt entries. This function is called from the
7698 linker scripts in ld/emultempl/{armelf}.em. */
7699
7700void
7701bfd_elf32_arm_use_long_plt (void)
7702{
7703 elf32_arm_use_long_plt_entry = TRUE;
7704}
7705
8afb0e02
NC		 7706/* Add the glue sections to ABFD. This function is called from the
7707 linker scripts in ld/emultempl/{armelf}.em. */
9b485d32 7708
b34976b6 7709bfd_boolean
57e8b36a
NC		 7710bfd_elf32_arm_add_glue_sections_to_bfd (bfd *abfd,
7711 struct bfd_link_info *info)
252b5132 7712{
a504d23a
LA		 7713 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (info);
7714 bfd_boolean dostm32l4xx = globals
7715 && globals->stm32l4xx_fix != BFD_ARM_STM32L4XX_FIX_NONE;
7716 bfd_boolean addglue;
7717
8afb0e02
NC		 7718 /* If we are only performing a partial
7719 link do not bother adding the glue. */
0e1862bb 7720 if (bfd_link_relocatable (info))
b34976b6 7721 return TRUE;
252b5132 7722
a504d23a 7723 addglue = arm_make_glue_section (abfd, ARM2THUMB_GLUE_SECTION_NAME)
8029a119
NC		 7724 && arm_make_glue_section (abfd, THUMB2ARM_GLUE_SECTION_NAME)
7725 && arm_make_glue_section (abfd, VFP11_ERRATUM_VENEER_SECTION_NAME)
7726 && arm_make_glue_section (abfd, ARM_BX_GLUE_SECTION_NAME);
a504d23a
LA		 7727
7728 if (!dostm32l4xx)
7729 return addglue;
7730
7731 return addglue
7732 && arm_make_glue_section (abfd, STM32L4XX_ERRATUM_VENEER_SECTION_NAME);
8afb0e02
NC		 7733}
7734
daa4adae
TP		 7735/* Mark output sections of veneers needing a dedicated one with SEC_KEEP. This
7736 ensures they are not marked for deletion by
7737 strip_excluded_output_sections () when veneers are going to be created
7738 later. Not doing so would trigger assert on empty section size in
7739 lang_size_sections_1 (). */
7740
7741void
7742bfd_elf32_arm_keep_private_stub_output_sections (struct bfd_link_info *info)
7743{
7744 enum elf32_arm_stub_type stub_type;
7745
7746 /* If we are only performing a partial
7747 link do not bother adding the glue. */
7748 if (bfd_link_relocatable (info))
7749 return;
7750
7751 for (stub_type = arm_stub_none + 1; stub_type < max_stub_type; stub_type++)
7752 {
7753 asection *out_sec;
7754 const char *out_sec_name;
7755
7756 if (!arm_dedicated_stub_output_section_required (stub_type))
7757 continue;
7758
7759 out_sec_name = arm_dedicated_stub_output_section_name (stub_type);
7760 out_sec = bfd_get_section_by_name (info->output_bfd, out_sec_name);
7761 if (out_sec != NULL)
7762 out_sec->flags |= SEC_KEEP;
7763 }
7764}
7765
8afb0e02
NC		 7766/* Select a BFD to be used to hold the sections used by the glue code.
7767 This function is called from the linker scripts in ld/emultempl/
8029a119 7768 {armelf/pe}.em. */
8afb0e02 7769
b34976b6 7770bfd_boolean
57e8b36a 7771bfd_elf32_arm_get_bfd_for_interworking (bfd *abfd, struct bfd_link_info *info)
8afb0e02
NC		 7772{
7773 struct elf32_arm_link_hash_table *globals;
7774
7775 /* If we are only performing a partial link
7776 do not bother getting a bfd to hold the glue. */
0e1862bb 7777 if (bfd_link_relocatable (info))
b34976b6 7778 return TRUE;
8afb0e02 7779
b7693d02
DJ		 7780 /* Make sure we don't attach the glue sections to a dynamic object. */
7781 BFD_ASSERT (!(abfd->flags & DYNAMIC));
7782
8afb0e02 7783 globals = elf32_arm_hash_table (info);
8afb0e02
NC		 7784 BFD_ASSERT (globals != NULL);
7785
7786 if (globals->bfd_of_glue_owner != NULL)
b34976b6 7787 return TRUE;
8afb0e02 7788
252b5132
RH		 7789 /* Save the bfd for later use. */
7790 globals->bfd_of_glue_owner = abfd;
cedb70c5 7791
b34976b6 7792 return TRUE;
252b5132
RH		 7793}
7794
906e58ca
NC		 7795static void
7796check_use_blx (struct elf32_arm_link_hash_table *globals)
39b41c9c 7797{
2de70689
MGD		 7798 int cpu_arch;
7799
b38cadfb 7800 cpu_arch = bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC,
2de70689
MGD		 7801 Tag_CPU_arch);
7802
7803 if (globals->fix_arm1176)
7804 {
7805 if (cpu_arch == TAG_CPU_ARCH_V6T2 || cpu_arch > TAG_CPU_ARCH_V6K)
7806 globals->use_blx = 1;
7807 }
7808 else
7809 {
7810 if (cpu_arch > TAG_CPU_ARCH_V4T)
7811 globals->use_blx = 1;
7812 }
39b41c9c
PB		 7813}
7814
b34976b6 7815bfd_boolean
57e8b36a 7816bfd_elf32_arm_process_before_allocation (bfd *abfd,
d504ffc8 7817 struct bfd_link_info *link_info)
252b5132
RH		 7818{
7819 Elf_Internal_Shdr *symtab_hdr;
6cdc0ccc 7820 Elf_Internal_Rela *internal_relocs = NULL;
252b5132
RH		 7821 Elf_Internal_Rela *irel, *irelend;
7822 bfd_byte *contents = NULL;
252b5132
RH		 7823
7824 asection *sec;
7825 struct elf32_arm_link_hash_table *globals;
7826
7827 /* If we are only performing a partial link do not bother
7828 to construct any glue. */
0e1862bb 7829 if (bfd_link_relocatable (link_info))
b34976b6 7830 return TRUE;
252b5132 7831
39ce1a6a
NC		 7832 /* Here we have a bfd that is to be included on the link. We have a
7833 hook to do reloc rummaging, before section sizes are nailed down. */
252b5132 7834 globals = elf32_arm_hash_table (link_info);
252b5132 7835 BFD_ASSERT (globals != NULL);
39ce1a6a
NC		 7836
7837 check_use_blx (globals);
252b5132 7838
d504ffc8 7839 if (globals->byteswap_code && !bfd_big_endian (abfd))
e489d0ae 7840 {
90b6238f 7841 _bfd_error_handler (_("%pB: BE8 images only valid in big-endian mode"),
d003868e 7842 abfd);
e489d0ae
PB		 7843 return FALSE;
7844 }
f21f3fe0 7845
39ce1a6a
NC		 7846 /* PR 5398: If we have not decided to include any loadable sections in
7847 the output then we will not have a glue owner bfd. This is OK, it
7848 just means that there is nothing else for us to do here. */
7849 if (globals->bfd_of_glue_owner == NULL)
7850 return TRUE;
7851
252b5132
RH		 7852 /* Rummage around all the relocs and map the glue vectors. */
7853 sec = abfd->sections;
7854
7855 if (sec == NULL)
b34976b6 7856 return TRUE;
252b5132
RH		 7857
7858 for (; sec != NULL; sec = sec->next)
7859 {
7860 if (sec->reloc_count == 0)
7861 continue;
7862
2f475487
AM		 7863 if ((sec->flags & SEC_EXCLUDE) != 0)
7864 continue;
7865
0ffa91dd 7866 symtab_hdr = & elf_symtab_hdr (abfd);
252b5132 7867
9b485d32 7868 /* Load the relocs. */
6cdc0ccc 7869 internal_relocs
906e58ca 7870 = _bfd_elf_link_read_relocs (abfd, sec, NULL, NULL, FALSE);
252b5132 7871
6cdc0ccc
AM		 7872 if (internal_relocs == NULL)
7873 goto error_return;
252b5132 7874
6cdc0ccc
AM		 7875 irelend = internal_relocs + sec->reloc_count;
7876 for (irel = internal_relocs; irel < irelend; irel++)
252b5132
RH		 7877 {
7878 long r_type;
7879 unsigned long r_index;
252b5132
RH		 7880
7881 struct elf_link_hash_entry *h;
7882
7883 r_type = ELF32_R_TYPE (irel->r_info);
7884 r_index = ELF32_R_SYM (irel->r_info);
7885
9b485d32 7886 /* These are the only relocation types we care about. */
ba96a88f 7887 if ( r_type != R_ARM_PC24
845b51d6 7888 && (r_type != R_ARM_V4BX || globals->fix_v4bx < 2))
252b5132
RH		 7889 continue;
7890
7891 /* Get the section contents if we haven't done so already. */
7892 if (contents == NULL)
7893 {
7894 /* Get cached copy if it exists. */
7895 if (elf_section_data (sec)->this_hdr.contents != NULL)
7896 contents = elf_section_data (sec)->this_hdr.contents;
7897 else
7898 {
7899 /* Go get them off disk. */
57e8b36a 7900 if (! bfd_malloc_and_get_section (abfd, sec, &contents))
252b5132
RH		 7901 goto error_return;
7902 }
7903 }
7904
845b51d6
PB		 7905 if (r_type == R_ARM_V4BX)
7906 {
7907 int reg;
7908
7909 reg = bfd_get_32 (abfd, contents + irel->r_offset) & 0xf;
7910 record_arm_bx_glue (link_info, reg);
7911 continue;
7912 }
7913
a7c10850 7914 /* If the relocation is not against a symbol it cannot concern us. */
252b5132
RH		 7915 h = NULL;
7916
9b485d32 7917 /* We don't care about local symbols. */
252b5132
RH		 7918 if (r_index < symtab_hdr->sh_info)
7919 continue;
7920
9b485d32 7921 /* This is an external symbol. */
252b5132
RH		 7922 r_index -= symtab_hdr->sh_info;
7923 h = (struct elf_link_hash_entry *)
7924 elf_sym_hashes (abfd)[r_index];
7925
7926 /* If the relocation is against a static symbol it must be within
7927 the current section and so cannot be a cross ARM/Thumb relocation. */
7928 if (h == NULL)
7929 continue;
7930
d504ffc8
DJ		 7931 /* If the call will go through a PLT entry then we do not need
7932 glue. */
362d30a1 7933 if (globals->root.splt != NULL && h->plt.offset != (bfd_vma) -1)
b7693d02
DJ		 7934 continue;
7935
252b5132
RH		 7936 switch (r_type)
7937 {
7938 case R_ARM_PC24:
7939 /* This one is a call from arm code. We need to look up
99059e56
RM		 7940 the target of the call. If it is a thumb target, we
7941 insert glue. */
39d911fc
TP		 7942 if (ARM_GET_SYM_BRANCH_TYPE (h->target_internal)
7943 == ST_BRANCH_TO_THUMB)
252b5132
RH		 7944 record_arm_to_thumb_glue (link_info, h);
7945 break;
7946
252b5132 7947 default:
c6596c5e 7948 abort ();
252b5132
RH		 7949 }
7950 }
6cdc0ccc 7951
c9594989 7952 if (elf_section_data (sec)->this_hdr.contents != contents)
6cdc0ccc
AM		 7953 free (contents);
7954 contents = NULL;
7955
c9594989 7956 if (elf_section_data (sec)->relocs != internal_relocs)
6cdc0ccc
AM		 7957 free (internal_relocs);
7958 internal_relocs = NULL;
252b5132
RH		 7959 }
7960
b34976b6 7961 return TRUE;
9a5aca8c 7962
dc1e8a47 7963 error_return:
c9594989 7964 if (elf_section_data (sec)->this_hdr.contents != contents)
6cdc0ccc 7965 free (contents);
c9594989 7966 if (elf_section_data (sec)->relocs != internal_relocs)
6cdc0ccc 7967 free (internal_relocs);
9a5aca8c 7968
b34976b6 7969 return FALSE;
252b5132 7970}
7e392df6 7971#endif
252b5132 7972
eb043451 7973
c7b8f16e
JB		 7974/* Initialise maps of ARM/Thumb/data for input BFDs. */
7975
7976void
7977bfd_elf32_arm_init_maps (bfd *abfd)
7978{
7979 Elf_Internal_Sym *isymbuf;
7980 Elf_Internal_Shdr *hdr;
7981 unsigned int i, localsyms;
7982
af1f4419
NC		 7983 /* PR 7093: Make sure that we are dealing with an arm elf binary. */
7984 if (! is_arm_elf (abfd))
7985 return;
7986
c7b8f16e
JB		 7987 if ((abfd->flags & DYNAMIC) != 0)
7988 return;
7989
0ffa91dd 7990 hdr = & elf_symtab_hdr (abfd);
c7b8f16e
JB		 7991 localsyms = hdr->sh_info;
7992
7993 /* Obtain a buffer full of symbols for this BFD. The hdr->sh_info field
7994 should contain the number of local symbols, which should come before any
7995 global symbols. Mapping symbols are always local. */
7996 isymbuf = bfd_elf_get_elf_syms (abfd, hdr, localsyms, 0, NULL, NULL,
7997 NULL);
7998
7999 /* No internal symbols read? Skip this BFD. */
8000 if (isymbuf == NULL)
8001 return;
8002
8003 for (i = 0; i < localsyms; i++)
8004 {
8005 Elf_Internal_Sym *isym = &isymbuf[i];
8006 asection *sec = bfd_section_from_elf_index (abfd, isym->st_shndx);
8007 const char *name;
906e58ca 8008
c7b8f16e 8009 if (sec != NULL
99059e56
RM		 8010 && ELF_ST_BIND (isym->st_info) == STB_LOCAL)
8011 {
8012 name = bfd_elf_string_from_elf_section (abfd,
8013 hdr->sh_link, isym->st_name);
906e58ca 8014
99059e56 8015 if (bfd_is_arm_special_symbol_name (name,
c7b8f16e 8016 BFD_ARM_SPECIAL_SYM_TYPE_MAP))
99059e56
RM		 8017 elf32_arm_section_map_add (sec, name[1], isym->st_value);
8018 }
c7b8f16e
JB		 8019 }
8020}
8021
8022
48229727
JB		 8023/* Auto-select enabling of Cortex-A8 erratum fix if the user didn't explicitly
8024 say what they wanted. */
8025
8026void
8027bfd_elf32_arm_set_cortex_a8_fix (bfd *obfd, struct bfd_link_info *link_info)
8028{
8029 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (link_info);
8030 obj_attribute *out_attr = elf_known_obj_attributes_proc (obfd);
8031
4dfe6ac6
NC		 8032 if (globals == NULL)
8033 return;
8034
48229727
JB		 8035 if (globals->fix_cortex_a8 == -1)
8036 {
8037 /* Turn on Cortex-A8 erratum workaround for ARMv7-A. */
8038 if (out_attr[Tag_CPU_arch].i == TAG_CPU_ARCH_V7
8039 && (out_attr[Tag_CPU_arch_profile].i == 'A'
8040 || out_attr[Tag_CPU_arch_profile].i == 0))
8041 globals->fix_cortex_a8 = 1;
8042 else
8043 globals->fix_cortex_a8 = 0;
8044 }
8045}
8046
8047
c7b8f16e
JB		 8048void
8049bfd_elf32_arm_set_vfp11_fix (bfd *obfd, struct bfd_link_info *link_info)
8050{
8051 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (link_info);
104d59d1 8052 obj_attribute *out_attr = elf_known_obj_attributes_proc (obfd);
906e58ca 8053
4dfe6ac6
NC		 8054 if (globals == NULL)
8055 return;
c7b8f16e
JB		 8056 /* We assume that ARMv7+ does not need the VFP11 denorm erratum fix. */
8057 if (out_attr[Tag_CPU_arch].i >= TAG_CPU_ARCH_V7)
8058 {
8059 switch (globals->vfp11_fix)
99059e56
RM		 8060 {
8061 case BFD_ARM_VFP11_FIX_DEFAULT:
8062 case BFD_ARM_VFP11_FIX_NONE:
8063 globals->vfp11_fix = BFD_ARM_VFP11_FIX_NONE;
8064 break;
8065
8066 default:
8067 /* Give a warning, but do as the user requests anyway. */
871b3ab2 8068 _bfd_error_handler (_("%pB: warning: selected VFP11 erratum "
99059e56
RM		 8069 "workaround is not necessary for target architecture"), obfd);
8070 }
c7b8f16e
JB		 8071 }
8072 else if (globals->vfp11_fix == BFD_ARM_VFP11_FIX_DEFAULT)
8073 /* For earlier architectures, we might need the workaround, but do not
8074 enable it by default. If users is running with broken hardware, they
8075 must enable the erratum fix explicitly. */
8076 globals->vfp11_fix = BFD_ARM_VFP11_FIX_NONE;
8077}
8078
a504d23a
LA		 8079void
8080bfd_elf32_arm_set_stm32l4xx_fix (bfd *obfd, struct bfd_link_info *link_info)
8081{
8082 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (link_info);
8083 obj_attribute *out_attr = elf_known_obj_attributes_proc (obfd);
8084
8085 if (globals == NULL)
8086 return;
8087
8088 /* We assume only Cortex-M4 may require the fix. */
8089 if (out_attr[Tag_CPU_arch].i != TAG_CPU_ARCH_V7E_M
8090 || out_attr[Tag_CPU_arch_profile].i != 'M')
8091 {
8092 if (globals->stm32l4xx_fix != BFD_ARM_STM32L4XX_FIX_NONE)
8093 /* Give a warning, but do as the user requests anyway. */
4eca0228 8094 _bfd_error_handler
871b3ab2 8095 (_("%pB: warning: selected STM32L4XX erratum "
a504d23a
LA		 8096 "workaround is not necessary for target architecture"), obfd);
8097 }
8098}
c7b8f16e 8099
906e58ca
NC		 8100enum bfd_arm_vfp11_pipe
8101{
c7b8f16e
JB		 8102 VFP11_FMAC,
8103 VFP11_LS,
8104 VFP11_DS,
8105 VFP11_BAD
8106};
8107
8108/* Return a VFP register number. This is encoded as RX:X for single-precision
8109 registers, or X:RX for double-precision registers, where RX is the group of
8110 four bits in the instruction encoding and X is the single extension bit.
8111 RX and X fields are specified using their lowest (starting) bit. The return
8112 value is:
8113
8114 0...31: single-precision registers s0...s31
8115 32...63: double-precision registers d0...d31.
906e58ca 8116
c7b8f16e
JB		 8117 Although X should be zero for VFP11 (encoding d0...d15 only), we might
8118 encounter VFP3 instructions, so we allow the full range for DP registers. */
906e58ca 8119
c7b8f16e
JB		 8120static unsigned int
8121bfd_arm_vfp11_regno (unsigned int insn, bfd_boolean is_double, unsigned int rx,
99059e56 8122 unsigned int x)
c7b8f16e
JB		 8123{
8124 if (is_double)
8125 return (((insn >> rx) & 0xf) | (((insn >> x) & 1) << 4)) + 32;
8126 else
8127 return (((insn >> rx) & 0xf) << 1) | ((insn >> x) & 1);
8128}
8129
8130/* Set bits in *WMASK according to a register number REG as encoded by
8131 bfd_arm_vfp11_regno(). Ignore d16-d31. */
8132
8133static void
8134bfd_arm_vfp11_write_mask (unsigned int *wmask, unsigned int reg)
8135{
8136 if (reg < 32)
8137 *wmask |= 1 << reg;
8138 else if (reg < 48)
8139 *wmask |= 3 << ((reg - 32) * 2);
8140}
8141
8142/* Return TRUE if WMASK overwrites anything in REGS. */
8143
8144static bfd_boolean
8145bfd_arm_vfp11_antidependency (unsigned int wmask, int *regs, int numregs)
8146{
8147 int i;
906e58ca 8148
c7b8f16e
JB		 8149 for (i = 0; i < numregs; i++)
8150 {
8151 unsigned int reg = regs[i];
8152
8153 if (reg < 32 && (wmask & (1 << reg)) != 0)
99059e56 8154 return TRUE;
906e58ca 8155
c7b8f16e
JB		 8156 reg -= 32;
8157
8158 if (reg >= 16)
99059e56 8159 continue;
906e58ca 8160
c7b8f16e 8161 if ((wmask & (3 << (reg * 2))) != 0)
99059e56 8162 return TRUE;
c7b8f16e 8163 }
906e58ca 8164
c7b8f16e
JB		 8165 return FALSE;
8166}
8167
8168/* In this function, we're interested in two things: finding input registers
8169 for VFP data-processing instructions, and finding the set of registers which
8170 arbitrary VFP instructions may write to. We use a 32-bit unsigned int to
8171 hold the written set, so FLDM etc. are easy to deal with (we're only
8172 interested in 32 SP registers or 16 dp registers, due to the VFP version
8173 implemented by the chip in question). DP registers are marked by setting
8174 both SP registers in the write mask). */
8175
8176static enum bfd_arm_vfp11_pipe
8177bfd_arm_vfp11_insn_decode (unsigned int insn, unsigned int *destmask, int *regs,
99059e56 8178 int *numregs)
c7b8f16e 8179{
91d6fa6a 8180 enum bfd_arm_vfp11_pipe vpipe = VFP11_BAD;
c7b8f16e
JB		 8181 bfd_boolean is_double = ((insn & 0xf00) == 0xb00) ? 1 : 0;
8182
8183 if ((insn & 0x0f000e10) == 0x0e000a00) /* A data-processing insn. */
8184 {
8185 unsigned int pqrs;
8186 unsigned int fd = bfd_arm_vfp11_regno (insn, is_double, 12, 22);
8187 unsigned int fm = bfd_arm_vfp11_regno (insn, is_double, 0, 5);
8188
8189 pqrs = ((insn & 0x00800000) >> 20)
99059e56
RM		 8190 | ((insn & 0x00300000) >> 19)
8191 | ((insn & 0x00000040) >> 6);
c7b8f16e
JB		 8192
8193 switch (pqrs)
99059e56
RM		 8194 {
8195 case 0: /* fmac[sd]. */
8196 case 1: /* fnmac[sd]. */
8197 case 2: /* fmsc[sd]. */
8198 case 3: /* fnmsc[sd]. */
8199 vpipe = VFP11_FMAC;
8200 bfd_arm_vfp11_write_mask (destmask, fd);
8201 regs[0] = fd;
8202 regs[1] = bfd_arm_vfp11_regno (insn, is_double, 16, 7); /* Fn. */
8203 regs[2] = fm;
8204 *numregs = 3;
8205 break;
8206
8207 case 4: /* fmul[sd]. */
8208 case 5: /* fnmul[sd]. */
8209 case 6: /* fadd[sd]. */
8210 case 7: /* fsub[sd]. */
8211 vpipe = VFP11_FMAC;
8212 goto vfp_binop;
8213
8214 case 8: /* fdiv[sd]. */
8215 vpipe = VFP11_DS;
8216 vfp_binop:
8217 bfd_arm_vfp11_write_mask (destmask, fd);
8218 regs[0] = bfd_arm_vfp11_regno (insn, is_double, 16, 7); /* Fn. */
8219 regs[1] = fm;
8220 *numregs = 2;
8221 break;
8222
8223 case 15: /* extended opcode. */
8224 {
8225 unsigned int extn = ((insn >> 15) & 0x1e)
8226 | ((insn >> 7) & 1);
8227
8228 switch (extn)
8229 {
8230 case 0: /* fcpy[sd]. */
8231 case 1: /* fabs[sd]. */
8232 case 2: /* fneg[sd]. */
8233 case 8: /* fcmp[sd]. */
8234 case 9: /* fcmpe[sd]. */
8235 case 10: /* fcmpz[sd]. */
8236 case 11: /* fcmpez[sd]. */
8237 case 16: /* fuito[sd]. */
8238 case 17: /* fsito[sd]. */
8239 case 24: /* ftoui[sd]. */
8240 case 25: /* ftouiz[sd]. */
8241 case 26: /* ftosi[sd]. */
8242 case 27: /* ftosiz[sd]. */
8243 /* These instructions will not bounce due to underflow. */
8244 *numregs = 0;
8245 vpipe = VFP11_FMAC;
8246 break;
8247
8248 case 3: /* fsqrt[sd]. */
8249 /* fsqrt cannot underflow, but it can (perhaps) overwrite
8250 registers to cause the erratum in previous instructions. */
8251 bfd_arm_vfp11_write_mask (destmask, fd);
8252 vpipe = VFP11_DS;
8253 break;
8254
8255 case 15: /* fcvt{ds,sd}. */
8256 {
8257 int rnum = 0;
8258
8259 bfd_arm_vfp11_write_mask (destmask, fd);
c7b8f16e
JB		 8260
8261 /* Only FCVTSD can underflow. */
99059e56
RM		 8262 if ((insn & 0x100) != 0)
8263 regs[rnum++] = fm;
c7b8f16e 8264
99059e56 8265 *numregs = rnum;
c7b8f16e 8266
99059e56
RM		 8267 vpipe = VFP11_FMAC;
8268 }
8269 break;
c7b8f16e 8270
99059e56
RM		 8271 default:
8272 return VFP11_BAD;
8273 }
8274 }
8275 break;
c7b8f16e 8276
99059e56
RM		 8277 default:
8278 return VFP11_BAD;
8279 }
c7b8f16e
JB		 8280 }
8281 /* Two-register transfer. */
8282 else if ((insn & 0x0fe00ed0) == 0x0c400a10)
8283 {
8284 unsigned int fm = bfd_arm_vfp11_regno (insn, is_double, 0, 5);
906e58ca 8285
c7b8f16e
JB		 8286 if ((insn & 0x100000) == 0)
8287 {
99059e56
RM		 8288 if (is_double)
8289 bfd_arm_vfp11_write_mask (destmask, fm);
8290 else
8291 {
8292 bfd_arm_vfp11_write_mask (destmask, fm);
8293 bfd_arm_vfp11_write_mask (destmask, fm + 1);
8294 }
c7b8f16e
JB		 8295 }
8296
91d6fa6a 8297 vpipe = VFP11_LS;
c7b8f16e
JB		 8298 }
8299 else if ((insn & 0x0e100e00) == 0x0c100a00) /* A load insn. */
8300 {
8301 int fd = bfd_arm_vfp11_regno (insn, is_double, 12, 22);
8302 unsigned int puw = ((insn >> 21) & 0x1) | (((insn >> 23) & 3) << 1);
906e58ca 8303
c7b8f16e 8304 switch (puw)
99059e56
RM		 8305 {
8306 case 0: /* Two-reg transfer. We should catch these above. */
8307 abort ();
906e58ca 8308
99059e56
RM		 8309 case 2: /* fldm[sdx]. */
8310 case 3:
8311 case 5:
8312 {
8313 unsigned int i, offset = insn & 0xff;
c7b8f16e 8314
99059e56
RM		 8315 if (is_double)
8316 offset >>= 1;
c7b8f16e 8317
99059e56
RM		 8318 for (i = fd; i < fd + offset; i++)
8319 bfd_arm_vfp11_write_mask (destmask, i);
8320 }
8321 break;
906e58ca 8322
99059e56
RM		 8323 case 4: /* fld[sd]. */
8324 case 6:
8325 bfd_arm_vfp11_write_mask (destmask, fd);
8326 break;
906e58ca 8327
99059e56
RM		 8328 default:
8329 return VFP11_BAD;
8330 }
c7b8f16e 8331
91d6fa6a 8332 vpipe = VFP11_LS;
c7b8f16e
JB		 8333 }
8334 /* Single-register transfer. Note L==0. */
8335 else if ((insn & 0x0f100e10) == 0x0e000a10)
8336 {
8337 unsigned int opcode = (insn >> 21) & 7;
8338 unsigned int fn = bfd_arm_vfp11_regno (insn, is_double, 16, 7);
8339
8340 switch (opcode)
99059e56
RM		 8341 {
8342 case 0: /* fmsr/fmdlr. */
8343 case 1: /* fmdhr. */
8344 /* Mark fmdhr and fmdlr as writing to the whole of the DP
8345 destination register. I don't know if this is exactly right,
8346 but it is the conservative choice. */
8347 bfd_arm_vfp11_write_mask (destmask, fn);
8348 break;
8349
8350 case 7: /* fmxr. */
8351 break;
8352 }
c7b8f16e 8353
91d6fa6a 8354 vpipe = VFP11_LS;
c7b8f16e
JB		 8355 }
8356
91d6fa6a 8357 return vpipe;
c7b8f16e
JB		 8358}
8359
8360
8361static int elf32_arm_compare_mapping (const void * a, const void * b);
8362
8363
8364/* Look for potentially-troublesome code sequences which might trigger the
8365 VFP11 denormal/antidependency erratum. See, e.g., the ARM1136 errata sheet
8366 (available from ARM) for details of the erratum. A short version is
8367 described in ld.texinfo. */
8368
8369bfd_boolean
8370bfd_elf32_arm_vfp11_erratum_scan (bfd *abfd, struct bfd_link_info *link_info)
8371{
8372 asection *sec;
8373 bfd_byte *contents = NULL;
8374 int state = 0;
8375 int regs[3], numregs = 0;
8376 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (link_info);
8377 int use_vector = (globals->vfp11_fix == BFD_ARM_VFP11_FIX_VECTOR);
906e58ca 8378
4dfe6ac6
NC		 8379 if (globals == NULL)
8380 return FALSE;
8381
c7b8f16e
JB		 8382 /* We use a simple FSM to match troublesome VFP11 instruction sequences.
8383 The states transition as follows:
906e58ca 8384
c7b8f16e 8385 0 -> 1 (vector) or 0 -> 2 (scalar)
99059e56
RM		 8386 A VFP FMAC-pipeline instruction has been seen. Fill
8387 regs[0]..regs[numregs-1] with its input operands. Remember this
8388 instruction in 'first_fmac'.
c7b8f16e
JB		 8389
8390 1 -> 2
99059e56
RM		 8391 Any instruction, except for a VFP instruction which overwrites
8392 regs[*].
906e58ca 8393
c7b8f16e
JB		 8394 1 -> 3 [ -> 0 ] or
8395 2 -> 3 [ -> 0 ]
99059e56
RM		 8396 A VFP instruction has been seen which overwrites any of regs[*].
8397 We must make a veneer! Reset state to 0 before examining next
8398 instruction.
906e58ca 8399
c7b8f16e 8400 2 -> 0
99059e56
RM		 8401 If we fail to match anything in state 2, reset to state 0 and reset
8402 the instruction pointer to the instruction after 'first_fmac'.
c7b8f16e
JB		 8403
8404 If the VFP11 vector mode is in use, there must be at least two unrelated
8405 instructions between anti-dependent VFP11 instructions to properly avoid
906e58ca 8406 triggering the erratum, hence the use of the extra state 1. */
c7b8f16e
JB		 8407
8408 /* If we are only performing a partial link do not bother
8409 to construct any glue. */
0e1862bb 8410 if (bfd_link_relocatable (link_info))
c7b8f16e
JB		 8411 return TRUE;
8412
0ffa91dd
NC		 8413 /* Skip if this bfd does not correspond to an ELF image. */
8414 if (! is_arm_elf (abfd))
8415 return TRUE;
906e58ca 8416
c7b8f16e
JB		 8417 /* We should have chosen a fix type by the time we get here. */
8418 BFD_ASSERT (globals->vfp11_fix != BFD_ARM_VFP11_FIX_DEFAULT);
8419
8420 if (globals->vfp11_fix == BFD_ARM_VFP11_FIX_NONE)
8421 return TRUE;
2e6030b9 8422
33a7ffc2
JM		 8423 /* Skip this BFD if it corresponds to an executable or dynamic object. */
8424 if ((abfd->flags & (EXEC_P | DYNAMIC)) != 0)
8425 return TRUE;
8426
c7b8f16e
JB		 8427 for (sec = abfd->sections; sec != NULL; sec = sec->next)
8428 {
8429 unsigned int i, span, first_fmac = 0, veneer_of_insn = 0;
8430 struct _arm_elf_section_data *sec_data;
8431
8432 /* If we don't have executable progbits, we're not interested in this
99059e56 8433 section. Also skip if section is to be excluded. */
c7b8f16e 8434 if (elf_section_type (sec) != SHT_PROGBITS
99059e56
RM		 8435 || (elf_section_flags (sec) & SHF_EXECINSTR) == 0
8436 || (sec->flags & SEC_EXCLUDE) != 0
dbaa2011 8437 || sec->sec_info_type == SEC_INFO_TYPE_JUST_SYMS
33a7ffc2 8438 || sec->output_section == bfd_abs_section_ptr
99059e56
RM		 8439 || strcmp (sec->name, VFP11_ERRATUM_VENEER_SECTION_NAME) == 0)
8440 continue;
c7b8f16e
JB		 8441
8442 sec_data = elf32_arm_section_data (sec);
906e58ca 8443
c7b8f16e 8444 if (sec_data->mapcount == 0)
99059e56 8445 continue;
906e58ca 8446
c7b8f16e
JB		 8447 if (elf_section_data (sec)->this_hdr.contents != NULL)
8448 contents = elf_section_data (sec)->this_hdr.contents;
8449 else if (! bfd_malloc_and_get_section (abfd, sec, &contents))
8450 goto error_return;
8451
8452 qsort (sec_data->map, sec_data->mapcount, sizeof (elf32_arm_section_map),
8453 elf32_arm_compare_mapping);
8454
8455 for (span = 0; span < sec_data->mapcount; span++)
99059e56
RM		 8456 {
8457 unsigned int span_start = sec_data->map[span].vma;
8458 unsigned int span_end = (span == sec_data->mapcount - 1)
c7b8f16e 8459 ? sec->size : sec_data->map[span + 1].vma;
99059e56
RM		 8460 char span_type = sec_data->map[span].type;
8461
8462 /* FIXME: Only ARM mode is supported at present. We may need to
8463 support Thumb-2 mode also at some point. */
8464 if (span_type != 'a')
8465 continue;
8466
8467 for (i = span_start; i < span_end;)
8468 {
8469 unsigned int next_i = i + 4;
8470 unsigned int insn = bfd_big_endian (abfd)
13c9c485
AM		 8471 ? (((unsigned) contents[i] << 24)
8472 | (contents[i + 1] << 16)
8473 | (contents[i + 2] << 8)
8474 | contents[i + 3])
8475 : (((unsigned) contents[i + 3] << 24)
8476 | (contents[i + 2] << 16)
8477 | (contents[i + 1] << 8)
8478 | contents[i]);
99059e56
RM		 8479 unsigned int writemask = 0;
8480 enum bfd_arm_vfp11_pipe vpipe;
8481
8482 switch (state)
8483 {
8484 case 0:
8485 vpipe = bfd_arm_vfp11_insn_decode (insn, &writemask, regs,
8486 &numregs);
8487 /* I'm assuming the VFP11 erratum can trigger with denorm
8488 operands on either the FMAC or the DS pipeline. This might
8489 lead to slightly overenthusiastic veneer insertion. */
8490 if (vpipe == VFP11_FMAC || vpipe == VFP11_DS)
8491 {
8492 state = use_vector ? 1 : 2;
8493 first_fmac = i;
8494 veneer_of_insn = insn;
8495 }
8496 break;
8497
8498 case 1:
8499 {
8500 int other_regs[3], other_numregs;
8501 vpipe = bfd_arm_vfp11_insn_decode (insn, &writemask,
c7b8f16e 8502 other_regs,
99059e56
RM		 8503 &other_numregs);
8504 if (vpipe != VFP11_BAD
8505 && bfd_arm_vfp11_antidependency (writemask, regs,
c7b8f16e 8506 numregs))
99059e56
RM		 8507 state = 3;
8508 else
8509 state = 2;
8510 }
8511 break;
8512
8513 case 2:
8514 {
8515 int other_regs[3], other_numregs;
8516 vpipe = bfd_arm_vfp11_insn_decode (insn, &writemask,
c7b8f16e 8517 other_regs,
99059e56
RM		 8518 &other_numregs);
8519 if (vpipe != VFP11_BAD
8520 && bfd_arm_vfp11_antidependency (writemask, regs,
c7b8f16e 8521 numregs))
99059e56
RM		 8522 state = 3;
8523 else
8524 {
8525 state = 0;
8526 next_i = first_fmac + 4;
8527 }
8528 }
8529 break;
8530
8531 case 3:
8532 abort (); /* Should be unreachable. */
8533 }
8534
8535 if (state == 3)
8536 {
8537 elf32_vfp11_erratum_list *newerr =(elf32_vfp11_erratum_list *)
8538 bfd_zmalloc (sizeof (elf32_vfp11_erratum_list));
8539
8540 elf32_arm_section_data (sec)->erratumcount += 1;
8541
8542 newerr->u.b.vfp_insn = veneer_of_insn;
8543
8544 switch (span_type)
8545 {
8546 case 'a':
8547 newerr->type = VFP11_ERRATUM_BRANCH_TO_ARM_VENEER;
8548 break;
8549
8550 default:
8551 abort ();
8552 }
8553
8554 record_vfp11_erratum_veneer (link_info, newerr, abfd, sec,
c7b8f16e
JB		 8555 first_fmac);
8556
99059e56 8557 newerr->vma = -1;
c7b8f16e 8558
99059e56
RM		 8559 newerr->next = sec_data->erratumlist;
8560 sec_data->erratumlist = newerr;
c7b8f16e 8561
99059e56
RM		 8562 state = 0;
8563 }
c7b8f16e 8564
99059e56
RM		 8565 i = next_i;
8566 }
8567 }
906e58ca 8568
c9594989 8569 if (elf_section_data (sec)->this_hdr.contents != contents)
99059e56 8570 free (contents);
c7b8f16e
JB		 8571 contents = NULL;
8572 }
8573
8574 return TRUE;
8575
dc1e8a47 8576 error_return:
c9594989 8577 if (elf_section_data (sec)->this_hdr.contents != contents)
c7b8f16e 8578 free (contents);
906e58ca 8579
c7b8f16e
JB		 8580 return FALSE;
8581}
8582
8583/* Find virtual-memory addresses for VFP11 erratum veneers and return locations
8584 after sections have been laid out, using specially-named symbols. */
8585
8586void
8587bfd_elf32_arm_vfp11_fix_veneer_locations (bfd *abfd,
8588 struct bfd_link_info *link_info)
8589{
8590 asection *sec;
8591 struct elf32_arm_link_hash_table *globals;
8592 char *tmp_name;
906e58ca 8593
0e1862bb 8594 if (bfd_link_relocatable (link_info))
c7b8f16e 8595 return;
2e6030b9
MS		 8596
8597 /* Skip if this bfd does not correspond to an ELF image. */
0ffa91dd 8598 if (! is_arm_elf (abfd))
2e6030b9
MS		 8599 return;
8600
c7b8f16e 8601 globals = elf32_arm_hash_table (link_info);
4dfe6ac6
NC		 8602 if (globals == NULL)
8603 return;
906e58ca 8604
21d799b5 8605 tmp_name = (char *) bfd_malloc ((bfd_size_type) strlen
99059e56 8606 (VFP11_ERRATUM_VENEER_ENTRY_NAME) + 10);
7a0fb7be 8607 BFD_ASSERT (tmp_name);
c7b8f16e
JB		 8608
8609 for (sec = abfd->sections; sec != NULL; sec = sec->next)
8610 {
8611 struct _arm_elf_section_data *sec_data = elf32_arm_section_data (sec);
8612 elf32_vfp11_erratum_list *errnode = sec_data->erratumlist;
906e58ca 8613
c7b8f16e 8614 for (; errnode != NULL; errnode = errnode->next)
99059e56
RM		 8615 {
8616 struct elf_link_hash_entry *myh;
8617 bfd_vma vma;
8618
8619 switch (errnode->type)
8620 {
8621 case VFP11_ERRATUM_BRANCH_TO_ARM_VENEER:
8622 case VFP11_ERRATUM_BRANCH_TO_THUMB_VENEER:
8623 /* Find veneer symbol. */
8624 sprintf (tmp_name, VFP11_ERRATUM_VENEER_ENTRY_NAME,
c7b8f16e
JB		 8625 errnode->u.b.veneer->u.v.id);
8626
99059e56
RM		 8627 myh = elf_link_hash_lookup
8628 (&(globals)->root, tmp_name, FALSE, FALSE, TRUE);
c7b8f16e 8629
a504d23a 8630 if (myh == NULL)
90b6238f
AM		 8631 _bfd_error_handler (_("%pB: unable to find %s veneer `%s'"),
8632 abfd, "VFP11", tmp_name);
a504d23a
LA		 8633
8634 vma = myh->root.u.def.section->output_section->vma
8635 + myh->root.u.def.section->output_offset
8636 + myh->root.u.def.value;
8637
8638 errnode->u.b.veneer->vma = vma;
8639 break;
8640
8641 case VFP11_ERRATUM_ARM_VENEER:
8642 case VFP11_ERRATUM_THUMB_VENEER:
8643 /* Find return location. */
8644 sprintf (tmp_name, VFP11_ERRATUM_VENEER_ENTRY_NAME "_r",
8645 errnode->u.v.id);
8646
8647 myh = elf_link_hash_lookup
8648 (&(globals)->root, tmp_name, FALSE, FALSE, TRUE);
8649
8650 if (myh == NULL)
90b6238f
AM		 8651 _bfd_error_handler (_("%pB: unable to find %s veneer `%s'"),
8652 abfd, "VFP11", tmp_name);
a504d23a
LA		 8653
8654 vma = myh->root.u.def.section->output_section->vma
8655 + myh->root.u.def.section->output_offset
8656 + myh->root.u.def.value;
8657
8658 errnode->u.v.branch->vma = vma;
8659 break;
8660
8661 default:
8662 abort ();
8663 }
8664 }
8665 }
8666
8667 free (tmp_name);
8668}
8669
8670/* Find virtual-memory addresses for STM32L4XX erratum veneers and
8671 return locations after sections have been laid out, using
8672 specially-named symbols. */
8673
8674void
8675bfd_elf32_arm_stm32l4xx_fix_veneer_locations (bfd *abfd,
8676 struct bfd_link_info *link_info)
8677{
8678 asection *sec;
8679 struct elf32_arm_link_hash_table *globals;
8680 char *tmp_name;
8681
8682 if (bfd_link_relocatable (link_info))
8683 return;
8684
8685 /* Skip if this bfd does not correspond to an ELF image. */
8686 if (! is_arm_elf (abfd))
8687 return;
8688
8689 globals = elf32_arm_hash_table (link_info);
8690 if (globals == NULL)
8691 return;
8692
8693 tmp_name = (char *) bfd_malloc ((bfd_size_type) strlen
8694 (STM32L4XX_ERRATUM_VENEER_ENTRY_NAME) + 10);
7a0fb7be 8695 BFD_ASSERT (tmp_name);
a504d23a
LA		 8696
8697 for (sec = abfd->sections; sec != NULL; sec = sec->next)
8698 {
8699 struct _arm_elf_section_data *sec_data = elf32_arm_section_data (sec);
8700 elf32_stm32l4xx_erratum_list *errnode = sec_data->stm32l4xx_erratumlist;
8701
8702 for (; errnode != NULL; errnode = errnode->next)
8703 {
8704 struct elf_link_hash_entry *myh;
8705 bfd_vma vma;
8706
8707 switch (errnode->type)
8708 {
8709 case STM32L4XX_ERRATUM_BRANCH_TO_VENEER:
8710 /* Find veneer symbol. */
8711 sprintf (tmp_name, STM32L4XX_ERRATUM_VENEER_ENTRY_NAME,
8712 errnode->u.b.veneer->u.v.id);
8713
8714 myh = elf_link_hash_lookup
8715 (&(globals)->root, tmp_name, FALSE, FALSE, TRUE);
8716
8717 if (myh == NULL)
90b6238f
AM		 8718 _bfd_error_handler (_("%pB: unable to find %s veneer `%s'"),
8719 abfd, "STM32L4XX", tmp_name);
a504d23a
LA		 8720
8721 vma = myh->root.u.def.section->output_section->vma
8722 + myh->root.u.def.section->output_offset
8723 + myh->root.u.def.value;
8724
8725 errnode->u.b.veneer->vma = vma;
8726 break;
8727
8728 case STM32L4XX_ERRATUM_VENEER:
8729 /* Find return location. */
8730 sprintf (tmp_name, STM32L4XX_ERRATUM_VENEER_ENTRY_NAME "_r",
8731 errnode->u.v.id);
8732
8733 myh = elf_link_hash_lookup
8734 (&(globals)->root, tmp_name, FALSE, FALSE, TRUE);
8735
8736 if (myh == NULL)
90b6238f
AM		 8737 _bfd_error_handler (_("%pB: unable to find %s veneer `%s'"),
8738 abfd, "STM32L4XX", tmp_name);
a504d23a
LA		 8739
8740 vma = myh->root.u.def.section->output_section->vma
8741 + myh->root.u.def.section->output_offset
8742 + myh->root.u.def.value;
8743
8744 errnode->u.v.branch->vma = vma;
8745 break;
8746
8747 default:
8748 abort ();
8749 }
8750 }
8751 }
8752
8753 free (tmp_name);
8754}
8755
8756static inline bfd_boolean
8757is_thumb2_ldmia (const insn32 insn)
8758{
8759 /* Encoding T2: LDM<c>.W <Rn>{!},<registers>
8760 1110 - 1000 - 10W1 - rrrr - PM (0) l - llll - llll - llll. */
8761 return (insn & 0xffd02000) == 0xe8900000;
8762}
8763
8764static inline bfd_boolean
8765is_thumb2_ldmdb (const insn32 insn)
8766{
8767 /* Encoding T1: LDMDB<c> <Rn>{!},<registers>
8768 1110 - 1001 - 00W1 - rrrr - PM (0) l - llll - llll - llll. */
8769 return (insn & 0xffd02000) == 0xe9100000;
8770}
8771
8772static inline bfd_boolean
8773is_thumb2_vldm (const insn32 insn)
8774{
8775 /* A6.5 Extension register load or store instruction
8776 A7.7.229
9239bbd3
CM		 8777 We look for SP 32-bit and DP 64-bit registers.
8778 Encoding T1 VLDM{mode}<c> <Rn>{!}, <list>
8779 <list> is consecutive 64-bit registers
8780 1110 - 110P - UDW1 - rrrr - vvvv - 1011 - iiii - iiii
a504d23a
LA		 8781 Encoding T2 VLDM{mode}<c> <Rn>{!}, <list>
8782 <list> is consecutive 32-bit registers
8783 1110 - 110P - UDW1 - rrrr - vvvv - 1010 - iiii - iiii
8784 if P==0 && U==1 && W==1 && Rn=1101 VPOP
8785 if PUW=010 || PUW=011 || PUW=101 VLDM. */
8786 return
9239bbd3
CM		 8787 (((insn & 0xfe100f00) == 0xec100b00) ||
8788 ((insn & 0xfe100f00) == 0xec100a00))
a504d23a
LA		 8789 && /* (IA without !). */
8790 (((((insn << 7) >> 28) & 0xd) == 0x4)
9239bbd3 8791 /* (IA with !), includes VPOP (when reg number is SP). */
a504d23a
LA		 8792 || ((((insn << 7) >> 28) & 0xd) == 0x5)
8793 /* (DB with !). */
8794 || ((((insn << 7) >> 28) & 0xd) == 0x9));
8795}
8796
8797/* STM STM32L4XX erratum : This function assumes that it receives an LDM or
8798 VLDM opcode and:
8799 - computes the number and the mode of memory accesses
8800 - decides if the replacement should be done:
8801 . replaces only if > 8-word accesses
8802 . or (testing purposes only) replaces all accesses. */
8803
8804static bfd_boolean
8805stm32l4xx_need_create_replacing_stub (const insn32 insn,
8806 bfd_arm_stm32l4xx_fix stm32l4xx_fix)
8807{
9239bbd3 8808 int nb_words = 0;
a504d23a
LA		 8809
8810 /* The field encoding the register list is the same for both LDMIA
8811 and LDMDB encodings. */
8812 if (is_thumb2_ldmia (insn) || is_thumb2_ldmdb (insn))
b25e998d 8813 nb_words = elf32_arm_popcount (insn & 0x0000ffff);
a504d23a 8814 else if (is_thumb2_vldm (insn))
9239bbd3 8815 nb_words = (insn & 0xff);
a504d23a
LA		 8816
8817 /* DEFAULT mode accounts for the real bug condition situation,
8818 ALL mode inserts stubs for each LDM/VLDM instruction (testing). */
8819 return
9239bbd3 8820 (stm32l4xx_fix == BFD_ARM_STM32L4XX_FIX_DEFAULT) ? nb_words > 8 :
a504d23a
LA		 8821 (stm32l4xx_fix == BFD_ARM_STM32L4XX_FIX_ALL) ? TRUE : FALSE;
8822}
8823
8824/* Look for potentially-troublesome code sequences which might trigger
8825 the STM STM32L4XX erratum. */
8826
8827bfd_boolean
8828bfd_elf32_arm_stm32l4xx_erratum_scan (bfd *abfd,
8829 struct bfd_link_info *link_info)
8830{
8831 asection *sec;
8832 bfd_byte *contents = NULL;
8833 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (link_info);
8834
8835 if (globals == NULL)
8836 return FALSE;
8837
8838 /* If we are only performing a partial link do not bother
8839 to construct any glue. */
8840 if (bfd_link_relocatable (link_info))
8841 return TRUE;
8842
8843 /* Skip if this bfd does not correspond to an ELF image. */
8844 if (! is_arm_elf (abfd))
8845 return TRUE;
8846
8847 if (globals->stm32l4xx_fix == BFD_ARM_STM32L4XX_FIX_NONE)
8848 return TRUE;
8849
8850 /* Skip this BFD if it corresponds to an executable or dynamic object. */
8851 if ((abfd->flags & (EXEC_P | DYNAMIC)) != 0)
8852 return TRUE;
8853
8854 for (sec = abfd->sections; sec != NULL; sec = sec->next)
8855 {
8856 unsigned int i, span;
8857 struct _arm_elf_section_data *sec_data;
8858
8859 /* If we don't have executable progbits, we're not interested in this
8860 section. Also skip if section is to be excluded. */
8861 if (elf_section_type (sec) != SHT_PROGBITS
8862 || (elf_section_flags (sec) & SHF_EXECINSTR) == 0
8863 || (sec->flags & SEC_EXCLUDE) != 0
8864 || sec->sec_info_type == SEC_INFO_TYPE_JUST_SYMS
8865 || sec->output_section == bfd_abs_section_ptr
8866 || strcmp (sec->name, STM32L4XX_ERRATUM_VENEER_SECTION_NAME) == 0)
8867 continue;
8868
8869 sec_data = elf32_arm_section_data (sec);
c7b8f16e 8870
a504d23a
LA		 8871 if (sec_data->mapcount == 0)
8872 continue;
c7b8f16e 8873
a504d23a
LA		 8874 if (elf_section_data (sec)->this_hdr.contents != NULL)
8875 contents = elf_section_data (sec)->this_hdr.contents;
8876 else if (! bfd_malloc_and_get_section (abfd, sec, &contents))
8877 goto error_return;
c7b8f16e 8878
a504d23a
LA		 8879 qsort (sec_data->map, sec_data->mapcount, sizeof (elf32_arm_section_map),
8880 elf32_arm_compare_mapping);
c7b8f16e 8881
a504d23a
LA		 8882 for (span = 0; span < sec_data->mapcount; span++)
8883 {
8884 unsigned int span_start = sec_data->map[span].vma;
8885 unsigned int span_end = (span == sec_data->mapcount - 1)
8886 ? sec->size : sec_data->map[span + 1].vma;
8887 char span_type = sec_data->map[span].type;
8888 int itblock_current_pos = 0;
c7b8f16e 8889
a504d23a
LA		 8890 /* Only Thumb2 mode need be supported with this CM4 specific
8891 code, we should not encounter any arm mode eg span_type
8892 != 'a'. */
8893 if (span_type != 't')
8894 continue;
c7b8f16e 8895
a504d23a
LA		 8896 for (i = span_start; i < span_end;)
8897 {
8898 unsigned int insn = bfd_get_16 (abfd, &contents[i]);
8899 bfd_boolean insn_32bit = FALSE;
8900 bfd_boolean is_ldm = FALSE;
8901 bfd_boolean is_vldm = FALSE;
8902 bfd_boolean is_not_last_in_it_block = FALSE;
8903
8904 /* The first 16-bits of all 32-bit thumb2 instructions start
8905 with opcode[15..13]=0b111 and the encoded op1 can be anything
8906 except opcode[12..11]!=0b00.
8907 See 32-bit Thumb instruction encoding. */
8908 if ((insn & 0xe000) == 0xe000 && (insn & 0x1800) != 0x0000)
8909 insn_32bit = TRUE;
c7b8f16e 8910
a504d23a
LA		 8911 /* Compute the predicate that tells if the instruction
8912 is concerned by the IT block
8913 - Creates an error if there is a ldm that is not
8914 last in the IT block thus cannot be replaced
8915 - Otherwise we can create a branch at the end of the
8916 IT block, it will be controlled naturally by IT
8917 with the proper pseudo-predicate
8918 - So the only interesting predicate is the one that
8919 tells that we are not on the last item of an IT
8920 block. */
8921 if (itblock_current_pos != 0)
8922 is_not_last_in_it_block = !!--itblock_current_pos;
906e58ca 8923
a504d23a
LA		 8924 if (insn_32bit)
8925 {
8926 /* Load the rest of the insn (in manual-friendly order). */
8927 insn = (insn << 16) | bfd_get_16 (abfd, &contents[i + 2]);
8928 is_ldm = is_thumb2_ldmia (insn) || is_thumb2_ldmdb (insn);
8929 is_vldm = is_thumb2_vldm (insn);
8930
8931 /* Veneers are created for (v)ldm depending on
8932 option flags and memory accesses conditions; but
8933 if the instruction is not the last instruction of
8934 an IT block, we cannot create a jump there, so we
8935 bail out. */
5025eb7c
AO		 8936 if ((is_ldm || is_vldm)
8937 && stm32l4xx_need_create_replacing_stub
a504d23a
LA		 8938 (insn, globals->stm32l4xx_fix))
8939 {
8940 if (is_not_last_in_it_block)
8941 {
4eca0228 8942 _bfd_error_handler
695344c0 8943 /* xgettext:c-format */
871b3ab2 8944 (_("%pB(%pA+%#x): error: multiple load detected"
90b6238f
AM		 8945 " in non-last IT block instruction:"
8946 " STM32L4XX veneer cannot be generated; "
8947 "use gcc option -mrestrict-it to generate"
8948 " only one instruction per IT block"),
d42c267e 8949 abfd, sec, i);
a504d23a
LA		 8950 }
8951 else
8952 {
8953 elf32_stm32l4xx_erratum_list *newerr =
8954 (elf32_stm32l4xx_erratum_list *)
8955 bfd_zmalloc
8956 (sizeof (elf32_stm32l4xx_erratum_list));
8957
8958 elf32_arm_section_data (sec)
8959 ->stm32l4xx_erratumcount += 1;
8960 newerr->u.b.insn = insn;
8961 /* We create only thumb branches. */
8962 newerr->type =
8963 STM32L4XX_ERRATUM_BRANCH_TO_VENEER;
8964 record_stm32l4xx_erratum_veneer
8965 (link_info, newerr, abfd, sec,
8966 i,
8967 is_ldm ?
8968 STM32L4XX_ERRATUM_LDM_VENEER_SIZE:
8969 STM32L4XX_ERRATUM_VLDM_VENEER_SIZE);
8970 newerr->vma = -1;
8971 newerr->next = sec_data->stm32l4xx_erratumlist;
8972 sec_data->stm32l4xx_erratumlist = newerr;
8973 }
8974 }
8975 }
8976 else
8977 {
8978 /* A7.7.37 IT p208
8979 IT blocks are only encoded in T1
8980 Encoding T1: IT{x{y{z}}} <firstcond>
8981 1 0 1 1 - 1 1 1 1 - firstcond - mask
8982 if mask = '0000' then see 'related encodings'
8983 We don't deal with UNPREDICTABLE, just ignore these.
8984 There can be no nested IT blocks so an IT block
8985 is naturally a new one for which it is worth
8986 computing its size. */
5025eb7c
AO		 8987 bfd_boolean is_newitblock = ((insn & 0xff00) == 0xbf00)
8988 && ((insn & 0x000f) != 0x0000);
a504d23a
LA		 8989 /* If we have a new IT block we compute its size. */
8990 if (is_newitblock)
8991 {
8992 /* Compute the number of instructions controlled
8993 by the IT block, it will be used to decide
8994 whether we are inside an IT block or not. */
8995 unsigned int mask = insn & 0x000f;
8996 itblock_current_pos = 4 - ctz (mask);
8997 }
8998 }
8999
9000 i += insn_32bit ? 4 : 2;
99059e56
RM		 9001 }
9002 }
a504d23a 9003
c9594989 9004 if (elf_section_data (sec)->this_hdr.contents != contents)
a504d23a
LA		 9005 free (contents);
9006 contents = NULL;
c7b8f16e 9007 }
906e58ca 9008
a504d23a
LA		 9009 return TRUE;
9010
dc1e8a47 9011 error_return:
c9594989 9012 if (elf_section_data (sec)->this_hdr.contents != contents)
a504d23a 9013 free (contents);
c7b8f16e 9014
a504d23a
LA		 9015 return FALSE;
9016}
c7b8f16e 9017
eb043451
PB		 9018/* Set target relocation values needed during linking. */
9019
9020void
68c39892 9021bfd_elf32_arm_set_target_params (struct bfd *output_bfd,
bf21ed78 9022 struct bfd_link_info *link_info,
68c39892 9023 struct elf32_arm_params *params)
eb043451
PB		 9024{
9025 struct elf32_arm_link_hash_table *globals;
9026
9027 globals = elf32_arm_hash_table (link_info);
4dfe6ac6
NC		 9028 if (globals == NULL)
9029 return;
eb043451 9030
68c39892 9031 globals->target1_is_rel = params->target1_is_rel;
29e9b073
CL		 9032 if (globals->fdpic_p)
9033 globals->target2_reloc = R_ARM_GOT32;
9034 else if (strcmp (params->target2_type, "rel") == 0)
eb043451 9035 globals->target2_reloc = R_ARM_REL32;
68c39892 9036 else if (strcmp (params->target2_type, "abs") == 0)
eeac373a 9037 globals->target2_reloc = R_ARM_ABS32;
68c39892 9038 else if (strcmp (params->target2_type, "got-rel") == 0)
eb043451
PB		 9039 globals->target2_reloc = R_ARM_GOT_PREL;
9040 else
9041 {
90b6238f 9042 _bfd_error_handler (_("invalid TARGET2 relocation type '%s'"),
68c39892 9043 params->target2_type);
eb043451 9044 }
68c39892
TP		 9045 globals->fix_v4bx = params->fix_v4bx;
9046 globals->use_blx |= params->use_blx;
9047 globals->vfp11_fix = params->vfp11_denorm_fix;
9048 globals->stm32l4xx_fix = params->stm32l4xx_fix;
e8b09b87
CL		 9049 if (globals->fdpic_p)
9050 globals->pic_veneer = 1;
9051 else
9052 globals->pic_veneer = params->pic_veneer;
68c39892
TP		 9053 globals->fix_cortex_a8 = params->fix_cortex_a8;
9054 globals->fix_arm1176 = params->fix_arm1176;
9055 globals->cmse_implib = params->cmse_implib;
9056 globals->in_implib_bfd = params->in_implib_bfd;
bf21ed78 9057
0ffa91dd 9058 BFD_ASSERT (is_arm_elf (output_bfd));
68c39892
TP		 9059 elf_arm_tdata (output_bfd)->no_enum_size_warning
9060 = params->no_enum_size_warning;
9061 elf_arm_tdata (output_bfd)->no_wchar_size_warning
9062 = params->no_wchar_size_warning;
eb043451 9063}
eb043451 9064
12a0a0fd 9065/* Replace the target offset of a Thumb bl or b.w instruction. */
252b5132 9066
12a0a0fd
PB		 9067static void
9068insert_thumb_branch (bfd *abfd, long int offset, bfd_byte *insn)
9069{
9070 bfd_vma upper;
9071 bfd_vma lower;
9072 int reloc_sign;
9073
9074 BFD_ASSERT ((offset & 1) == 0);
9075
9076 upper = bfd_get_16 (abfd, insn);
9077 lower = bfd_get_16 (abfd, insn + 2);
9078 reloc_sign = (offset < 0) ? 1 : 0;
9079 upper = (upper & ~(bfd_vma) 0x7ff)
9080 | ((offset >> 12) & 0x3ff)
9081 | (reloc_sign << 10);
906e58ca 9082 lower = (lower & ~(bfd_vma) 0x2fff)
12a0a0fd
PB		 9083 | (((!((offset >> 23) & 1)) ^ reloc_sign) << 13)
9084 | (((!((offset >> 22) & 1)) ^ reloc_sign) << 11)
9085 | ((offset >> 1) & 0x7ff);
9086 bfd_put_16 (abfd, upper, insn);
9087 bfd_put_16 (abfd, lower, insn + 2);
252b5132
RH		 9088}
9089
9b485d32
NC		 9090/* Thumb code calling an ARM function. */
9091
252b5132 9092static int
57e8b36a 9093elf32_thumb_to_arm_stub (struct bfd_link_info * info,
07d6d2b8
AM		 9094 const char * name,
9095 bfd * input_bfd,
9096 bfd * output_bfd,
9097 asection * input_section,
9098 bfd_byte * hit_data,
9099 asection * sym_sec,
9100 bfd_vma offset,
9101 bfd_signed_vma addend,
9102 bfd_vma val,
f2a9dd69 9103 char **error_message)
252b5132 9104{
bcbdc74c 9105 asection * s = 0;
dc810e39 9106 bfd_vma my_offset;
252b5132 9107 long int ret_offset;
bcbdc74c
NC		 9108 struct elf_link_hash_entry * myh;
9109 struct elf32_arm_link_hash_table * globals;
252b5132 9110
f2a9dd69 9111 myh = find_thumb_glue (info, name, error_message);
252b5132 9112 if (myh == NULL)
b34976b6 9113 return FALSE;
252b5132
RH		 9114
9115 globals = elf32_arm_hash_table (info);
252b5132
RH		 9116 BFD_ASSERT (globals != NULL);
9117 BFD_ASSERT (globals->bfd_of_glue_owner != NULL);
9118
9119 my_offset = myh->root.u.def.value;
9120
3d4d4302
AM		 9121 s = bfd_get_linker_section (globals->bfd_of_glue_owner,
9122 THUMB2ARM_GLUE_SECTION_NAME);
252b5132
RH		 9123
9124 BFD_ASSERT (s != NULL);
9125 BFD_ASSERT (s->contents != NULL);
9126 BFD_ASSERT (s->output_section != NULL);
9127
9128 if ((my_offset & 0x01) == 0x01)
9129 {
9130 if (sym_sec != NULL
9131 && sym_sec->owner != NULL
9132 && !INTERWORK_FLAG (sym_sec->owner))
9133 {
4eca0228 9134 _bfd_error_handler
90b6238f
AM		 9135 (_("%pB(%s): warning: interworking not enabled;"
9136 " first occurrence: %pB: %s call to %s"),
9137 sym_sec->owner, name, input_bfd, "Thumb", "ARM");
252b5132 9138
b34976b6 9139 return FALSE;
252b5132
RH		 9140 }
9141
9142 --my_offset;
9143 myh->root.u.def.value = my_offset;
9144
52ab56c2
PB		 9145 put_thumb_insn (globals, output_bfd, (bfd_vma) t2a1_bx_pc_insn,
9146 s->contents + my_offset);
252b5132 9147
52ab56c2
PB		 9148 put_thumb_insn (globals, output_bfd, (bfd_vma) t2a2_noop_insn,
9149 s->contents + my_offset + 2);
252b5132
RH		 9150
9151 ret_offset =
9b485d32
NC		 9152 /* Address of destination of the stub. */
9153 ((bfd_signed_vma) val)
252b5132 9154 - ((bfd_signed_vma)
57e8b36a
NC		 9155 /* Offset from the start of the current section
9156 to the start of the stubs. */
9b485d32
NC		 9157 (s->output_offset
9158 /* Offset of the start of this stub from the start of the stubs. */
9159 + my_offset
9160 /* Address of the start of the current section. */
9161 + s->output_section->vma)
9162 /* The branch instruction is 4 bytes into the stub. */
9163 + 4
9164 /* ARM branches work from the pc of the instruction + 8. */
9165 + 8);
252b5132 9166
52ab56c2
PB		 9167 put_arm_insn (globals, output_bfd,
9168 (bfd_vma) t2a3_b_insn | ((ret_offset >> 2) & 0x00FFFFFF),
9169 s->contents + my_offset + 4);
252b5132
RH		 9170 }
9171
9172 BFD_ASSERT (my_offset <= globals->thumb_glue_size);
9173
427bfd90
NC		 9174 /* Now go back and fix up the original BL insn to point to here. */
9175 ret_offset =
9176 /* Address of where the stub is located. */
9177 (s->output_section->vma + s->output_offset + my_offset)
9178 /* Address of where the BL is located. */
57e8b36a
NC		 9179 - (input_section->output_section->vma + input_section->output_offset
9180 + offset)
427bfd90
NC		 9181 /* Addend in the relocation. */
9182 - addend
9183 /* Biassing for PC-relative addressing. */
9184 - 8;
252b5132 9185
12a0a0fd 9186 insert_thumb_branch (input_bfd, ret_offset, hit_data - input_section->vma);
252b5132 9187
b34976b6 9188 return TRUE;
252b5132
RH		 9189}
9190
a4fd1a8e 9191/* Populate an Arm to Thumb stub. Returns the stub symbol. */
9b485d32 9192
a4fd1a8e
PB		 9193static struct elf_link_hash_entry *
9194elf32_arm_create_thumb_stub (struct bfd_link_info * info,
07d6d2b8
AM		 9195 const char * name,
9196 bfd * input_bfd,
9197 bfd * output_bfd,
9198 asection * sym_sec,
9199 bfd_vma val,
9200 asection * s,
9201 char ** error_message)
252b5132 9202{
dc810e39 9203 bfd_vma my_offset;
252b5132 9204 long int ret_offset;
bcbdc74c
NC		 9205 struct elf_link_hash_entry * myh;
9206 struct elf32_arm_link_hash_table * globals;
252b5132 9207
f2a9dd69 9208 myh = find_arm_glue (info, name, error_message);
252b5132 9209 if (myh == NULL)
a4fd1a8e 9210 return NULL;
252b5132
RH		 9211
9212 globals = elf32_arm_hash_table (info);
252b5132
RH		 9213 BFD_ASSERT (globals != NULL);
9214 BFD_ASSERT (globals->bfd_of_glue_owner != NULL);
9215
9216 my_offset = myh->root.u.def.value;
252b5132
RH		 9217
9218 if ((my_offset & 0x01) == 0x01)
9219 {
9220 if (sym_sec != NULL
9221 && sym_sec->owner != NULL
9222 && !INTERWORK_FLAG (sym_sec->owner))
9223 {
4eca0228 9224 _bfd_error_handler
90b6238f
AM		 9225 (_("%pB(%s): warning: interworking not enabled;"
9226 " first occurrence: %pB: %s call to %s"),
9227 sym_sec->owner, name, input_bfd, "ARM", "Thumb");
252b5132 9228 }
9b485d32 9229
252b5132
RH		 9230 --my_offset;
9231 myh->root.u.def.value = my_offset;
9232
0e1862bb
L		 9233 if (bfd_link_pic (info)
9234 || globals->root.is_relocatable_executable
27e55c4d 9235 || globals->pic_veneer)
8f6277f5
PB		 9236 {
9237 /* For relocatable objects we can't use absolute addresses,
9238 so construct the address from a relative offset. */
9239 /* TODO: If the offset is small it's probably worth
9240 constructing the address with adds. */
52ab56c2
PB		 9241 put_arm_insn (globals, output_bfd, (bfd_vma) a2t1p_ldr_insn,
9242 s->contents + my_offset);
9243 put_arm_insn (globals, output_bfd, (bfd_vma) a2t2p_add_pc_insn,
9244 s->contents + my_offset + 4);
9245 put_arm_insn (globals, output_bfd, (bfd_vma) a2t3p_bx_r12_insn,
9246 s->contents + my_offset + 8);
8f6277f5
PB		 9247 /* Adjust the offset by 4 for the position of the add,
9248 and 8 for the pipeline offset. */
9249 ret_offset = (val - (s->output_offset
9250 + s->output_section->vma
9251 + my_offset + 12))
9252 | 1;
9253 bfd_put_32 (output_bfd, ret_offset,
9254 s->contents + my_offset + 12);
9255 }
26079076
PB		 9256 else if (globals->use_blx)
9257 {
9258 put_arm_insn (globals, output_bfd, (bfd_vma) a2t1v5_ldr_insn,
9259 s->contents + my_offset);
9260
9261 /* It's a thumb address. Add the low order bit. */
9262 bfd_put_32 (output_bfd, val | a2t2v5_func_addr_insn,
9263 s->contents + my_offset + 4);
9264 }
8f6277f5
PB		 9265 else
9266 {
52ab56c2
PB		 9267 put_arm_insn (globals, output_bfd, (bfd_vma) a2t1_ldr_insn,
9268 s->contents + my_offset);
252b5132 9269
52ab56c2
PB		 9270 put_arm_insn (globals, output_bfd, (bfd_vma) a2t2_bx_r12_insn,
9271 s->contents + my_offset + 4);
252b5132 9272
8f6277f5
PB		 9273 /* It's a thumb address. Add the low order bit. */
9274 bfd_put_32 (output_bfd, val | a2t3_func_addr_insn,
9275 s->contents + my_offset + 8);
8029a119
NC		 9276
9277 my_offset += 12;
8f6277f5 9278 }
252b5132
RH		 9279 }
9280
9281 BFD_ASSERT (my_offset <= globals->arm_glue_size);
9282
a4fd1a8e
PB		 9283 return myh;
9284}
9285
9286/* Arm code calling a Thumb function. */
9287
9288static int
9289elf32_arm_to_thumb_stub (struct bfd_link_info * info,
07d6d2b8
AM		 9290 const char * name,
9291 bfd * input_bfd,
9292 bfd * output_bfd,
9293 asection * input_section,
9294 bfd_byte * hit_data,
9295 asection * sym_sec,
9296 bfd_vma offset,
9297 bfd_signed_vma addend,
9298 bfd_vma val,
f2a9dd69 9299 char **error_message)
a4fd1a8e
PB		 9300{
9301 unsigned long int tmp;
9302 bfd_vma my_offset;
9303 asection * s;
9304 long int ret_offset;
9305 struct elf_link_hash_entry * myh;
9306 struct elf32_arm_link_hash_table * globals;
9307
9308 globals = elf32_arm_hash_table (info);
a4fd1a8e
PB		 9309 BFD_ASSERT (globals != NULL);
9310 BFD_ASSERT (globals->bfd_of_glue_owner != NULL);
9311
3d4d4302
AM		 9312 s = bfd_get_linker_section (globals->bfd_of_glue_owner,
9313 ARM2THUMB_GLUE_SECTION_NAME);
a4fd1a8e
PB		 9314 BFD_ASSERT (s != NULL);
9315 BFD_ASSERT (s->contents != NULL);
9316 BFD_ASSERT (s->output_section != NULL);
9317
9318 myh = elf32_arm_create_thumb_stub (info, name, input_bfd, output_bfd,
f2a9dd69 9319 sym_sec, val, s, error_message);
a4fd1a8e
PB		 9320 if (!myh)
9321 return FALSE;
9322
9323 my_offset = myh->root.u.def.value;
252b5132
RH		 9324 tmp = bfd_get_32 (input_bfd, hit_data);
9325 tmp = tmp & 0xFF000000;
9326
9b485d32 9327 /* Somehow these are both 4 too far, so subtract 8. */
dc810e39
AM		 9328 ret_offset = (s->output_offset
9329 + my_offset
9330 + s->output_section->vma
9331 - (input_section->output_offset
9332 + input_section->output_section->vma
9333 + offset + addend)
9334 - 8);
9a5aca8c 9335
252b5132
RH		 9336 tmp = tmp | ((ret_offset >> 2) & 0x00FFFFFF);
9337
dc810e39 9338 bfd_put_32 (output_bfd, (bfd_vma) tmp, hit_data - input_section->vma);
252b5132 9339
b34976b6 9340 return TRUE;
252b5132
RH		 9341}
9342
a4fd1a8e
PB		 9343/* Populate Arm stub for an exported Thumb function. */
9344
9345static bfd_boolean
9346elf32_arm_to_thumb_export_stub (struct elf_link_hash_entry *h, void * inf)
9347{
9348 struct bfd_link_info * info = (struct bfd_link_info *) inf;
9349 asection * s;
9350 struct elf_link_hash_entry * myh;
9351 struct elf32_arm_link_hash_entry *eh;
9352 struct elf32_arm_link_hash_table * globals;
9353 asection *sec;
9354 bfd_vma val;
f2a9dd69 9355 char *error_message;
a4fd1a8e 9356
906e58ca 9357 eh = elf32_arm_hash_entry (h);
a4fd1a8e
PB		 9358 /* Allocate stubs for exported Thumb functions on v4t. */
9359 if (eh->export_glue == NULL)
9360 return TRUE;
9361
9362 globals = elf32_arm_hash_table (info);
a4fd1a8e
PB		 9363 BFD_ASSERT (globals != NULL);
9364 BFD_ASSERT (globals->bfd_of_glue_owner != NULL);
9365
3d4d4302
AM		 9366 s = bfd_get_linker_section (globals->bfd_of_glue_owner,
9367 ARM2THUMB_GLUE_SECTION_NAME);
a4fd1a8e
PB		 9368 BFD_ASSERT (s != NULL);
9369 BFD_ASSERT (s->contents != NULL);
9370 BFD_ASSERT (s->output_section != NULL);
9371
9372 sec = eh->export_glue->root.u.def.section;
0eaedd0e
PB		 9373
9374 BFD_ASSERT (sec->output_section != NULL);
9375
a4fd1a8e
PB		 9376 val = eh->export_glue->root.u.def.value + sec->output_offset
9377 + sec->output_section->vma;
8029a119 9378
a4fd1a8e
PB		 9379 myh = elf32_arm_create_thumb_stub (info, h->root.root.string,
9380 h->root.u.def.section->owner,
f2a9dd69
DJ		 9381 globals->obfd, sec, val, s,
9382 &error_message);
a4fd1a8e
PB		 9383 BFD_ASSERT (myh);
9384 return TRUE;
9385}
9386
845b51d6
PB		 9387/* Populate ARMv4 BX veneers. Returns the absolute adress of the veneer. */
9388
9389static bfd_vma
9390elf32_arm_bx_glue (struct bfd_link_info * info, int reg)
9391{
9392 bfd_byte *p;
9393 bfd_vma glue_addr;
9394 asection *s;
9395 struct elf32_arm_link_hash_table *globals;
9396
9397 globals = elf32_arm_hash_table (info);
845b51d6
PB		 9398 BFD_ASSERT (globals != NULL);
9399 BFD_ASSERT (globals->bfd_of_glue_owner != NULL);
9400
3d4d4302
AM		 9401 s = bfd_get_linker_section (globals->bfd_of_glue_owner,
9402 ARM_BX_GLUE_SECTION_NAME);
845b51d6
PB		 9403 BFD_ASSERT (s != NULL);
9404 BFD_ASSERT (s->contents != NULL);
9405 BFD_ASSERT (s->output_section != NULL);
9406
9407 BFD_ASSERT (globals->bx_glue_offset[reg] & 2);
9408
9409 glue_addr = globals->bx_glue_offset[reg] & ~(bfd_vma)3;
9410
9411 if ((globals->bx_glue_offset[reg] & 1) == 0)
9412 {
9413 p = s->contents + glue_addr;
9414 bfd_put_32 (globals->obfd, armbx1_tst_insn + (reg << 16), p);
9415 bfd_put_32 (globals->obfd, armbx2_moveq_insn + reg, p + 4);
9416 bfd_put_32 (globals->obfd, armbx3_bx_insn + reg, p + 8);
9417 globals->bx_glue_offset[reg] |= 1;
9418 }
9419
9420 return glue_addr + s->output_section->vma + s->output_offset;
9421}
9422
a4fd1a8e
PB		 9423/* Generate Arm stubs for exported Thumb symbols. */
9424static void
906e58ca 9425elf32_arm_begin_write_processing (bfd *abfd ATTRIBUTE_UNUSED,
a4fd1a8e
PB		 9426 struct bfd_link_info *link_info)
9427{
9428 struct elf32_arm_link_hash_table * globals;
9429
8029a119
NC		 9430 if (link_info == NULL)
9431 /* Ignore this if we are not called by the ELF backend linker. */
a4fd1a8e
PB		 9432 return;
9433
9434 globals = elf32_arm_hash_table (link_info);
4dfe6ac6
NC		 9435 if (globals == NULL)
9436 return;
9437
84c08195
PB		 9438 /* If blx is available then exported Thumb symbols are OK and there is
9439 nothing to do. */
a4fd1a8e
PB		 9440 if (globals->use_blx)
9441 return;
9442
9443 elf_link_hash_traverse (&globals->root, elf32_arm_to_thumb_export_stub,
9444 link_info);
9445}
9446
47beaa6a
RS		 9447/* Reserve space for COUNT dynamic relocations in relocation selection
9448 SRELOC. */
9449
9450static void
9451elf32_arm_allocate_dynrelocs (struct bfd_link_info *info, asection *sreloc,
9452 bfd_size_type count)
9453{
9454 struct elf32_arm_link_hash_table *htab;
9455
9456 htab = elf32_arm_hash_table (info);
9457 BFD_ASSERT (htab->root.dynamic_sections_created);
9458 if (sreloc == NULL)
9459 abort ();
9460 sreloc->size += RELOC_SIZE (htab) * count;
9461}
9462
34e77a92
RS		 9463/* Reserve space for COUNT R_ARM_IRELATIVE relocations. If the link is
9464 dynamic, the relocations should go in SRELOC, otherwise they should
9465 go in the special .rel.iplt section. */
9466
9467static void
9468elf32_arm_allocate_irelocs (struct bfd_link_info *info, asection *sreloc,
9469 bfd_size_type count)
9470{
9471 struct elf32_arm_link_hash_table *htab;
9472
9473 htab = elf32_arm_hash_table (info);
9474 if (!htab->root.dynamic_sections_created)
9475 htab->root.irelplt->size += RELOC_SIZE (htab) * count;
9476 else
9477 {
9478 BFD_ASSERT (sreloc != NULL);
9479 sreloc->size += RELOC_SIZE (htab) * count;
9480 }
9481}
9482
47beaa6a
RS		 9483/* Add relocation REL to the end of relocation section SRELOC. */
9484
9485static void
9486elf32_arm_add_dynreloc (bfd *output_bfd, struct bfd_link_info *info,
9487 asection *sreloc, Elf_Internal_Rela *rel)
9488{
9489 bfd_byte *loc;
9490 struct elf32_arm_link_hash_table *htab;
9491
9492 htab = elf32_arm_hash_table (info);
34e77a92
RS		 9493 if (!htab->root.dynamic_sections_created
9494 && ELF32_R_TYPE (rel->r_info) == R_ARM_IRELATIVE)
9495 sreloc = htab->root.irelplt;
47beaa6a
RS		 9496 if (sreloc == NULL)
9497 abort ();
9498 loc = sreloc->contents;
9499 loc += sreloc->reloc_count++ * RELOC_SIZE (htab);
9500 if (sreloc->reloc_count * RELOC_SIZE (htab) > sreloc->size)
9501 abort ();
9502 SWAP_RELOC_OUT (htab) (output_bfd, rel, loc);
9503}
9504
34e77a92
RS		 9505/* Allocate room for a PLT entry described by ROOT_PLT and ARM_PLT.
9506 IS_IPLT_ENTRY says whether the entry belongs to .iplt rather than
9507 to .plt. */
9508
9509static void
9510elf32_arm_allocate_plt_entry (struct bfd_link_info *info,
9511 bfd_boolean is_iplt_entry,
9512 union gotplt_union *root_plt,
9513 struct arm_plt_info *arm_plt)
9514{
9515 struct elf32_arm_link_hash_table *htab;
9516 asection *splt;
9517 asection *sgotplt;
9518
9519 htab = elf32_arm_hash_table (info);
9520
9521 if (is_iplt_entry)
9522 {
9523 splt = htab->root.iplt;
9524 sgotplt = htab->root.igotplt;
9525
99059e56
RM		 9526 /* NaCl uses a special first entry in .iplt too. */
9527 if (htab->nacl_p && splt->size == 0)
9528 splt->size += htab->plt_header_size;
9529
34e77a92
RS		 9530 /* Allocate room for an R_ARM_IRELATIVE relocation in .rel.iplt. */
9531 elf32_arm_allocate_irelocs (info, htab->root.irelplt, 1);
9532 }
9533 else
9534 {
9535 splt = htab->root.splt;
9536 sgotplt = htab->root.sgotplt;
9537
7801f98f
CL		 9538 if (htab->fdpic_p)
9539 {
9540 /* Allocate room for R_ARM_FUNCDESC_VALUE. */
9541 /* For lazy binding, relocations will be put into .rel.plt, in
9542 .rel.got otherwise. */
9543 /* FIXME: today we don't support lazy binding so put it in .rel.got */
9544 if (info->flags & DF_BIND_NOW)
9545 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
9546 else
9547 elf32_arm_allocate_dynrelocs (info, htab->root.srelplt, 1);
9548 }
9549 else
9550 {
9551 /* Allocate room for an R_JUMP_SLOT relocation in .rel.plt. */
9552 elf32_arm_allocate_dynrelocs (info, htab->root.srelplt, 1);
9553 }
34e77a92
RS		 9554
9555 /* If this is the first .plt entry, make room for the special
9556 first entry. */
9557 if (splt->size == 0)
9558 splt->size += htab->plt_header_size;
9f19ab6d
WN		 9559
9560 htab->next_tls_desc_index++;
34e77a92
RS		 9561 }
9562
9563 /* Allocate the PLT entry itself, including any leading Thumb stub. */
9564 if (elf32_arm_plt_needs_thumb_stub_p (info, arm_plt))
9565 splt->size += PLT_THUMB_STUB_SIZE;
9566 root_plt->offset = splt->size;
9567 splt->size += htab->plt_entry_size;
9568
9569 if (!htab->symbian_p)
9570 {
9571 /* We also need to make an entry in the .got.plt section, which
9572 will be placed in the .got section by the linker script. */
9f19ab6d
WN		 9573 if (is_iplt_entry)
9574 arm_plt->got_offset = sgotplt->size;
9575 else
9576 arm_plt->got_offset = sgotplt->size - 8 * htab->num_tls_desc;
7801f98f
CL		 9577 if (htab->fdpic_p)
9578 /* Function descriptor takes 64 bits in GOT. */
4b24dd1a 9579 sgotplt->size += 8;
7801f98f
CL		 9580 else
9581 sgotplt->size += 4;
34e77a92
RS		 9582 }
9583}
9584
b38cadfb
NC		 9585static bfd_vma
9586arm_movw_immediate (bfd_vma value)
9587{
9588 return (value & 0x00000fff) | ((value & 0x0000f000) << 4);
9589}
9590
9591static bfd_vma
9592arm_movt_immediate (bfd_vma value)
9593{
9594 return ((value & 0x0fff0000) >> 16) | ((value & 0xf0000000) >> 12);
9595}
9596
34e77a92
RS		 9597/* Fill in a PLT entry and its associated GOT slot. If DYNINDX == -1,
9598 the entry lives in .iplt and resolves to (*SYM_VALUE)().
9599 Otherwise, DYNINDX is the index of the symbol in the dynamic
9600 symbol table and SYM_VALUE is undefined.
9601
9602 ROOT_PLT points to the offset of the PLT entry from the start of its
9603 section (.iplt or .plt). ARM_PLT points to the symbol's ARM-specific
57460bcf 9604 bookkeeping information.
34e77a92 9605
57460bcf
NC		 9606 Returns FALSE if there was a problem. */
9607
9608static bfd_boolean
34e77a92
RS		 9609elf32_arm_populate_plt_entry (bfd *output_bfd, struct bfd_link_info *info,
9610 union gotplt_union *root_plt,
9611 struct arm_plt_info *arm_plt,
9612 int dynindx, bfd_vma sym_value)
9613{
9614 struct elf32_arm_link_hash_table *htab;
9615 asection *sgot;
9616 asection *splt;
9617 asection *srel;
9618 bfd_byte *loc;
9619 bfd_vma plt_index;
9620 Elf_Internal_Rela rel;
9621 bfd_vma plt_header_size;
9622 bfd_vma got_header_size;
9623
9624 htab = elf32_arm_hash_table (info);
9625
9626 /* Pick the appropriate sections and sizes. */
9627 if (dynindx == -1)
9628 {
9629 splt = htab->root.iplt;
9630 sgot = htab->root.igotplt;
9631 srel = htab->root.irelplt;
9632
9633 /* There are no reserved entries in .igot.plt, and no special
9634 first entry in .iplt. */
9635 got_header_size = 0;
9636 plt_header_size = 0;
9637 }
9638 else
9639 {
9640 splt = htab->root.splt;
9641 sgot = htab->root.sgotplt;
9642 srel = htab->root.srelplt;
9643
9644 got_header_size = get_elf_backend_data (output_bfd)->got_header_size;
9645 plt_header_size = htab->plt_header_size;
9646 }
9647 BFD_ASSERT (splt != NULL && srel != NULL);
9648
9649 /* Fill in the entry in the procedure linkage table. */
9650 if (htab->symbian_p)
9651 {
9652 BFD_ASSERT (dynindx >= 0);
9653 put_arm_insn (htab, output_bfd,
9654 elf32_arm_symbian_plt_entry[0],
9655 splt->contents + root_plt->offset);
9656 bfd_put_32 (output_bfd,
9657 elf32_arm_symbian_plt_entry[1],
9658 splt->contents + root_plt->offset + 4);
9659
9660 /* Fill in the entry in the .rel.plt section. */
9661 rel.r_offset = (splt->output_section->vma
9662 + splt->output_offset
9663 + root_plt->offset + 4);
9664 rel.r_info = ELF32_R_INFO (dynindx, R_ARM_GLOB_DAT);
9665
9666 /* Get the index in the procedure linkage table which
9667 corresponds to this symbol. This is the index of this symbol
9668 in all the symbols for which we are making plt entries. The
9669 first entry in the procedure linkage table is reserved. */
9670 plt_index = ((root_plt->offset - plt_header_size)
9671 / htab->plt_entry_size);
9672 }
9673 else
9674 {
9675 bfd_vma got_offset, got_address, plt_address;
9676 bfd_vma got_displacement, initial_got_entry;
9677 bfd_byte * ptr;
9678
9679 BFD_ASSERT (sgot != NULL);
9680
9681 /* Get the offset into the .(i)got.plt table of the entry that
9682 corresponds to this function. */
9683 got_offset = (arm_plt->got_offset & -2);
9684
9685 /* Get the index in the procedure linkage table which
9686 corresponds to this symbol. This is the index of this symbol
9687 in all the symbols for which we are making plt entries.
9688 After the reserved .got.plt entries, all symbols appear in
9689 the same order as in .plt. */
7801f98f 9690 if (htab->fdpic_p)
4b24dd1a
AM		 9691 /* Function descriptor takes 8 bytes. */
9692 plt_index = (got_offset - got_header_size) / 8;
7801f98f 9693 else
4b24dd1a 9694 plt_index = (got_offset - got_header_size) / 4;
34e77a92
RS		 9695
9696 /* Calculate the address of the GOT entry. */
9697 got_address = (sgot->output_section->vma
9698 + sgot->output_offset
9699 + got_offset);
9700
9701 /* ...and the address of the PLT entry. */
9702 plt_address = (splt->output_section->vma
9703 + splt->output_offset
9704 + root_plt->offset);
9705
9706 ptr = splt->contents + root_plt->offset;
0e1862bb 9707 if (htab->vxworks_p && bfd_link_pic (info))
34e77a92
RS		 9708 {
9709 unsigned int i;
9710 bfd_vma val;
9711
9712 for (i = 0; i != htab->plt_entry_size / 4; i++, ptr += 4)
9713 {
9714 val = elf32_arm_vxworks_shared_plt_entry[i];
9715 if (i == 2)
9716 val |= got_address - sgot->output_section->vma;
9717 if (i == 5)
9718 val |= plt_index * RELOC_SIZE (htab);
9719 if (i == 2 || i == 5)
9720 bfd_put_32 (output_bfd, val, ptr);
9721 else
9722 put_arm_insn (htab, output_bfd, val, ptr);
9723 }
9724 }
9725 else if (htab->vxworks_p)
9726 {
9727 unsigned int i;
9728 bfd_vma val;
9729
9730 for (i = 0; i != htab->plt_entry_size / 4; i++, ptr += 4)
9731 {
9732 val = elf32_arm_vxworks_exec_plt_entry[i];
9733 if (i == 2)
9734 val |= got_address;
9735 if (i == 4)
9736 val |= 0xffffff & -((root_plt->offset + i * 4 + 8) >> 2);
9737 if (i == 5)
9738 val |= plt_index * RELOC_SIZE (htab);
9739 if (i == 2 || i == 5)
9740 bfd_put_32 (output_bfd, val, ptr);
9741 else
9742 put_arm_insn (htab, output_bfd, val, ptr);
9743 }
9744
9745 loc = (htab->srelplt2->contents
9746 + (plt_index * 2 + 1) * RELOC_SIZE (htab));
9747
9748 /* Create the .rela.plt.unloaded R_ARM_ABS32 relocation
9749 referencing the GOT for this PLT entry. */
9750 rel.r_offset = plt_address + 8;
9751 rel.r_info = ELF32_R_INFO (htab->root.hgot->indx, R_ARM_ABS32);
9752 rel.r_addend = got_offset;
9753 SWAP_RELOC_OUT (htab) (output_bfd, &rel, loc);
9754 loc += RELOC_SIZE (htab);
9755
9756 /* Create the R_ARM_ABS32 relocation referencing the
9757 beginning of the PLT for this GOT entry. */
9758 rel.r_offset = got_address;
9759 rel.r_info = ELF32_R_INFO (htab->root.hplt->indx, R_ARM_ABS32);
9760 rel.r_addend = 0;
9761 SWAP_RELOC_OUT (htab) (output_bfd, &rel, loc);
9762 }
b38cadfb
NC		 9763 else if (htab->nacl_p)
9764 {
9765 /* Calculate the displacement between the PLT slot and the
9766 common tail that's part of the special initial PLT slot. */
6034aab8 9767 int32_t tail_displacement
b38cadfb
NC		 9768 = ((splt->output_section->vma + splt->output_offset
9769 + ARM_NACL_PLT_TAIL_OFFSET)
9770 - (plt_address + htab->plt_entry_size + 4));
9771 BFD_ASSERT ((tail_displacement & 3) == 0);
9772 tail_displacement >>= 2;
9773
9774 BFD_ASSERT ((tail_displacement & 0xff000000) == 0
9775 || (-tail_displacement & 0xff000000) == 0);
9776
9777 /* Calculate the displacement between the PLT slot and the entry
9778 in the GOT. The offset accounts for the value produced by
9779 adding to pc in the penultimate instruction of the PLT stub. */
6034aab8 9780 got_displacement = (got_address
99059e56 9781 - (plt_address + htab->plt_entry_size));
b38cadfb
NC		 9782
9783 /* NaCl does not support interworking at all. */
9784 BFD_ASSERT (!elf32_arm_plt_needs_thumb_stub_p (info, arm_plt));
9785
9786 put_arm_insn (htab, output_bfd,
9787 elf32_arm_nacl_plt_entry[0]
9788 | arm_movw_immediate (got_displacement),
9789 ptr + 0);
9790 put_arm_insn (htab, output_bfd,
9791 elf32_arm_nacl_plt_entry[1]
9792 | arm_movt_immediate (got_displacement),
9793 ptr + 4);
9794 put_arm_insn (htab, output_bfd,
9795 elf32_arm_nacl_plt_entry[2],
9796 ptr + 8);
9797 put_arm_insn (htab, output_bfd,
9798 elf32_arm_nacl_plt_entry[3]
9799 | (tail_displacement & 0x00ffffff),
9800 ptr + 12);
9801 }
7801f98f
CL		 9802 else if (htab->fdpic_p)
9803 {
59029f57
CL		 9804 const bfd_vma *plt_entry = using_thumb_only(htab)
9805 ? elf32_arm_fdpic_thumb_plt_entry
9806 : elf32_arm_fdpic_plt_entry;
9807
7801f98f
CL		 9808 /* Fill-up Thumb stub if needed. */
9809 if (elf32_arm_plt_needs_thumb_stub_p (info, arm_plt))
9810 {
9811 put_thumb_insn (htab, output_bfd,
9812 elf32_arm_plt_thumb_stub[0], ptr - 4);
9813 put_thumb_insn (htab, output_bfd,
9814 elf32_arm_plt_thumb_stub[1], ptr - 2);
9815 }
59029f57
CL		 9816 /* As we are using 32 bit instructions even for the Thumb
9817 version, we have to use 'put_arm_insn' instead of
9818 'put_thumb_insn'. */
9819 put_arm_insn(htab, output_bfd, plt_entry[0], ptr + 0);
9820 put_arm_insn(htab, output_bfd, plt_entry[1], ptr + 4);
9821 put_arm_insn(htab, output_bfd, plt_entry[2], ptr + 8);
9822 put_arm_insn(htab, output_bfd, plt_entry[3], ptr + 12);
7801f98f
CL		 9823 bfd_put_32 (output_bfd, got_offset, ptr + 16);
9824
9825 if (!(info->flags & DF_BIND_NOW))
9826 {
9827 /* funcdesc_value_reloc_offset. */
9828 bfd_put_32 (output_bfd,
9829 htab->root.srelplt->reloc_count * RELOC_SIZE (htab),
9830 ptr + 20);
59029f57
CL		 9831 put_arm_insn(htab, output_bfd, plt_entry[6], ptr + 24);
9832 put_arm_insn(htab, output_bfd, plt_entry[7], ptr + 28);
9833 put_arm_insn(htab, output_bfd, plt_entry[8], ptr + 32);
9834 put_arm_insn(htab, output_bfd, plt_entry[9], ptr + 36);
7801f98f
CL		 9835 }
9836 }
57460bcf
NC		 9837 else if (using_thumb_only (htab))
9838 {
eed94f8f 9839 /* PR ld/16017: Generate thumb only PLT entries. */
469a3493 9840 if (!using_thumb2 (htab))
eed94f8f
NC		 9841 {
9842 /* FIXME: We ought to be able to generate thumb-1 PLT
9843 instructions... */
90b6238f 9844 _bfd_error_handler (_("%pB: warning: thumb-1 mode PLT generation not currently supported"),
eed94f8f
NC		 9845 output_bfd);
9846 return FALSE;
9847 }
57460bcf 9848
eed94f8f
NC		 9849 /* Calculate the displacement between the PLT slot and the entry in
9850 the GOT. The 12-byte offset accounts for the value produced by
9851 adding to pc in the 3rd instruction of the PLT stub. */
9852 got_displacement = got_address - (plt_address + 12);
9853
9854 /* As we are using 32 bit instructions we have to use 'put_arm_insn'
9855 instead of 'put_thumb_insn'. */
9856 put_arm_insn (htab, output_bfd,
9857 elf32_thumb2_plt_entry[0]
9858 | ((got_displacement & 0x000000ff) << 16)
9859 | ((got_displacement & 0x00000700) << 20)
9860 | ((got_displacement & 0x00000800) >> 1)
9861 | ((got_displacement & 0x0000f000) >> 12),
9862 ptr + 0);
9863 put_arm_insn (htab, output_bfd,
9864 elf32_thumb2_plt_entry[1]
9865 | ((got_displacement & 0x00ff0000) )
9866 | ((got_displacement & 0x07000000) << 4)
9867 | ((got_displacement & 0x08000000) >> 17)
9868 | ((got_displacement & 0xf0000000) >> 28),
9869 ptr + 4);
9870 put_arm_insn (htab, output_bfd,
9871 elf32_thumb2_plt_entry[2],
9872 ptr + 8);
9873 put_arm_insn (htab, output_bfd,
9874 elf32_thumb2_plt_entry[3],
9875 ptr + 12);
57460bcf 9876 }
34e77a92
RS		 9877 else
9878 {
9879 /* Calculate the displacement between the PLT slot and the
9880 entry in the GOT. The eight-byte offset accounts for the
9881 value produced by adding to pc in the first instruction
9882 of the PLT stub. */
9883 got_displacement = got_address - (plt_address + 8);
9884
34e77a92
RS		 9885 if (elf32_arm_plt_needs_thumb_stub_p (info, arm_plt))
9886 {
9887 put_thumb_insn (htab, output_bfd,
9888 elf32_arm_plt_thumb_stub[0], ptr - 4);
9889 put_thumb_insn (htab, output_bfd,
9890 elf32_arm_plt_thumb_stub[1], ptr - 2);
9891 }
9892
1db37fe6
YG		 9893 if (!elf32_arm_use_long_plt_entry)
9894 {
9895 BFD_ASSERT ((got_displacement & 0xf0000000) == 0);
9896
9897 put_arm_insn (htab, output_bfd,
9898 elf32_arm_plt_entry_short[0]
9899 | ((got_displacement & 0x0ff00000) >> 20),
9900 ptr + 0);
9901 put_arm_insn (htab, output_bfd,
9902 elf32_arm_plt_entry_short[1]
9903 | ((got_displacement & 0x000ff000) >> 12),
9904 ptr+ 4);
9905 put_arm_insn (htab, output_bfd,
9906 elf32_arm_plt_entry_short[2]
9907 | (got_displacement & 0x00000fff),
9908 ptr + 8);
34e77a92 9909#ifdef FOUR_WORD_PLT
1db37fe6 9910 bfd_put_32 (output_bfd, elf32_arm_plt_entry_short[3], ptr + 12);
34e77a92 9911#endif
1db37fe6
YG		 9912 }
9913 else
9914 {
9915 put_arm_insn (htab, output_bfd,
9916 elf32_arm_plt_entry_long[0]
9917 | ((got_displacement & 0xf0000000) >> 28),
9918 ptr + 0);
9919 put_arm_insn (htab, output_bfd,
9920 elf32_arm_plt_entry_long[1]
9921 | ((got_displacement & 0x0ff00000) >> 20),
9922 ptr + 4);
9923 put_arm_insn (htab, output_bfd,
9924 elf32_arm_plt_entry_long[2]
9925 | ((got_displacement & 0x000ff000) >> 12),
9926 ptr+ 8);
9927 put_arm_insn (htab, output_bfd,
9928 elf32_arm_plt_entry_long[3]
9929 | (got_displacement & 0x00000fff),
9930 ptr + 12);
9931 }
34e77a92
RS		 9932 }
9933
9934 /* Fill in the entry in the .rel(a).(i)plt section. */
9935 rel.r_offset = got_address;
9936 rel.r_addend = 0;
9937 if (dynindx == -1)
9938 {
9939 /* .igot.plt entries use IRELATIVE relocations against SYM_VALUE.
9940 The dynamic linker or static executable then calls SYM_VALUE
9941 to determine the correct run-time value of the .igot.plt entry. */
9942 rel.r_info = ELF32_R_INFO (0, R_ARM_IRELATIVE);
9943 initial_got_entry = sym_value;
9944 }
9945 else
9946 {
7801f98f
CL		 9947 /* For FDPIC we will have to resolve a R_ARM_FUNCDESC_VALUE
9948 used by PLT entry. */
9949 if (htab->fdpic_p)
9950 {
9951 rel.r_info = ELF32_R_INFO (dynindx, R_ARM_FUNCDESC_VALUE);
9952 initial_got_entry = 0;
9953 }
9954 else
9955 {
9956 rel.r_info = ELF32_R_INFO (dynindx, R_ARM_JUMP_SLOT);
9957 initial_got_entry = (splt->output_section->vma
9958 + splt->output_offset);
a7618269
TC		 9959
9960 /* PR ld/16017
9961 When thumb only we need to set the LSB for any address that
9962 will be used with an interworking branch instruction. */
9963 if (using_thumb_only (htab))
9964 initial_got_entry |= 1;
7801f98f 9965 }
34e77a92
RS		 9966 }
9967
9968 /* Fill in the entry in the global offset table. */
9969 bfd_put_32 (output_bfd, initial_got_entry,
9970 sgot->contents + got_offset);
7801f98f
CL		 9971
9972 if (htab->fdpic_p && !(info->flags & DF_BIND_NOW))
9973 {
9974 /* Setup initial funcdesc value. */
9975 /* FIXME: we don't support lazy binding because there is a
9976 race condition between both words getting written and
9977 some other thread attempting to read them. The ARM
9978 architecture does not have an atomic 64 bit load/store
9979 instruction that could be used to prevent it; it is
9980 recommended that threaded FDPIC applications run with the
9981 LD_BIND_NOW environment variable set. */
9982 bfd_put_32(output_bfd, plt_address + 0x18,
9983 sgot->contents + got_offset);
9984 bfd_put_32(output_bfd, -1 /*TODO*/,
9985 sgot->contents + got_offset + 4);
9986 }
34e77a92
RS		 9987 }
9988
aba8c3de
WN		 9989 if (dynindx == -1)
9990 elf32_arm_add_dynreloc (output_bfd, info, srel, &rel);
9991 else
9992 {
7801f98f
CL		 9993 if (htab->fdpic_p)
9994 {
9995 /* For FDPIC we put PLT relocationss into .rel.got when not
9996 lazy binding otherwise we put them in .rel.plt. For now,
9997 we don't support lazy binding so put it in .rel.got. */
9998 if (info->flags & DF_BIND_NOW)
9999 elf32_arm_add_dynreloc(output_bfd, info, htab->root.srelgot, &rel);
10000 else
10001 elf32_arm_add_dynreloc(output_bfd, info, htab->root.srelplt, &rel);
10002 }
10003 else
10004 {
10005 loc = srel->contents + plt_index * RELOC_SIZE (htab);
10006 SWAP_RELOC_OUT (htab) (output_bfd, &rel, loc);
10007 }
aba8c3de 10008 }
57460bcf
NC		 10009
10010 return TRUE;
34e77a92
RS		 10011}
10012
eb043451
PB		 10013/* Some relocations map to different relocations depending on the
10014 target. Return the real relocation. */
8029a119 10015
eb043451
PB		 10016static int
10017arm_real_reloc_type (struct elf32_arm_link_hash_table * globals,
10018 int r_type)
10019{
10020 switch (r_type)
10021 {
10022 case R_ARM_TARGET1:
10023 if (globals->target1_is_rel)
10024 return R_ARM_REL32;
10025 else
10026 return R_ARM_ABS32;
10027
10028 case R_ARM_TARGET2:
10029 return globals->target2_reloc;
10030
10031 default:
10032 return r_type;
10033 }
10034}
eb043451 10035
ba93b8ac
DJ		 10036/* Return the base VMA address which should be subtracted from real addresses
10037 when resolving @dtpoff relocation.
10038 This is PT_TLS segment p_vaddr. */
10039
10040static bfd_vma
10041dtpoff_base (struct bfd_link_info *info)
10042{
10043 /* If tls_sec is NULL, we should have signalled an error already. */
10044 if (elf_hash_table (info)->tls_sec == NULL)
10045 return 0;
10046 return elf_hash_table (info)->tls_sec->vma;
10047}
10048
10049/* Return the relocation value for @tpoff relocation
10050 if STT_TLS virtual address is ADDRESS. */
10051
10052static bfd_vma
10053tpoff (struct bfd_link_info *info, bfd_vma address)
10054{
10055 struct elf_link_hash_table *htab = elf_hash_table (info);
10056 bfd_vma base;
10057
10058 /* If tls_sec is NULL, we should have signalled an error already. */
10059 if (htab->tls_sec == NULL)
10060 return 0;
10061 base = align_power ((bfd_vma) TCB_SIZE, htab->tls_sec->alignment_power);
10062 return address - htab->tls_sec->vma + base;
10063}
10064
00a97672
RS		 10065/* Perform an R_ARM_ABS12 relocation on the field pointed to by DATA.
10066 VALUE is the relocation value. */
10067
10068static bfd_reloc_status_type
10069elf32_arm_abs12_reloc (bfd *abfd, void *data, bfd_vma value)
10070{
10071 if (value > 0xfff)
10072 return bfd_reloc_overflow;
10073
10074 value |= bfd_get_32 (abfd, data) & 0xfffff000;
10075 bfd_put_32 (abfd, value, data);
10076 return bfd_reloc_ok;
10077}
10078
0855e32b
NS		 10079/* Handle TLS relaxations. Relaxing is possible for symbols that use
10080 R_ARM_GOTDESC, R_ARM_{,THM_}TLS_CALL or
10081 R_ARM_{,THM_}TLS_DESCSEQ relocations, during a static link.
10082
10083 Return bfd_reloc_ok if we're done, bfd_reloc_continue if the caller
10084 is to then call final_link_relocate. Return other values in the
62672b10
NS		 10085 case of error.
10086
10087 FIXME:When --emit-relocs is in effect, we'll emit relocs describing
10088 the pre-relaxed code. It would be nice if the relocs were updated
10089 to match the optimization. */
0855e32b 10090
b38cadfb 10091static bfd_reloc_status_type
0855e32b 10092elf32_arm_tls_relax (struct elf32_arm_link_hash_table *globals,
b38cadfb 10093 bfd *input_bfd, asection *input_sec, bfd_byte *contents,
0855e32b
NS		 10094 Elf_Internal_Rela *rel, unsigned long is_local)
10095{
10096 unsigned long insn;
b38cadfb 10097
0855e32b
NS		 10098 switch (ELF32_R_TYPE (rel->r_info))
10099 {
10100 default:
10101 return bfd_reloc_notsupported;
b38cadfb 10102
0855e32b
NS		 10103 case R_ARM_TLS_GOTDESC:
10104 if (is_local)
10105 insn = 0;
10106 else
10107 {
10108 insn = bfd_get_32 (input_bfd, contents + rel->r_offset);
10109 if (insn & 1)
10110 insn -= 5; /* THUMB */
10111 else
10112 insn -= 8; /* ARM */
10113 }
10114 bfd_put_32 (input_bfd, insn, contents + rel->r_offset);
10115 return bfd_reloc_continue;
10116
10117 case R_ARM_THM_TLS_DESCSEQ:
10118 /* Thumb insn. */
10119 insn = bfd_get_16 (input_bfd, contents + rel->r_offset);
10120 if ((insn & 0xff78) == 0x4478) /* add rx, pc */
10121 {
10122 if (is_local)
10123 /* nop */
10124 bfd_put_16 (input_bfd, 0x46c0, contents + rel->r_offset);
10125 }
10126 else if ((insn & 0xffc0) == 0x6840) /* ldr rx,[ry,#4] */
10127 {
10128 if (is_local)
10129 /* nop */
10130 bfd_put_16 (input_bfd, 0x46c0, contents + rel->r_offset);
10131 else
10132 /* ldr rx,[ry] */
10133 bfd_put_16 (input_bfd, insn & 0xf83f, contents + rel->r_offset);
10134 }
10135 else if ((insn & 0xff87) == 0x4780) /* blx rx */
10136 {
10137 if (is_local)
10138 /* nop */
10139 bfd_put_16 (input_bfd, 0x46c0, contents + rel->r_offset);
10140 else
10141 /* mov r0, rx */
10142 bfd_put_16 (input_bfd, 0x4600 | (insn & 0x78),
10143 contents + rel->r_offset);
10144 }
10145 else
10146 {
10147 if ((insn & 0xf000) == 0xf000 || (insn & 0xf800) == 0xe800)
10148 /* It's a 32 bit instruction, fetch the rest of it for
10149 error generation. */
10150 insn = (insn << 16)
10151 | bfd_get_16 (input_bfd, contents + rel->r_offset + 2);
4eca0228 10152 _bfd_error_handler
695344c0 10153 /* xgettext:c-format */
2dcf00ce 10154 (_("%pB(%pA+%#" PRIx64 "): "
90b6238f
AM		 10155 "unexpected %s instruction '%#lx' in TLS trampoline"),
10156 input_bfd, input_sec, (uint64_t) rel->r_offset,
10157 "Thumb", insn);
0855e32b
NS		 10158 return bfd_reloc_notsupported;
10159 }
10160 break;
b38cadfb 10161
0855e32b
NS		 10162 case R_ARM_TLS_DESCSEQ:
10163 /* arm insn. */
10164 insn = bfd_get_32 (input_bfd, contents + rel->r_offset);
10165 if ((insn & 0xffff0ff0) == 0xe08f0000) /* add rx,pc,ry */
10166 {
10167 if (is_local)
10168 /* mov rx, ry */
10169 bfd_put_32 (input_bfd, 0xe1a00000 | (insn & 0xffff),
10170 contents + rel->r_offset);
10171 }
10172 else if ((insn & 0xfff00fff) == 0xe5900004) /* ldr rx,[ry,#4]*/
10173 {
10174 if (is_local)
10175 /* nop */
10176 bfd_put_32 (input_bfd, 0xe1a00000, contents + rel->r_offset);
10177 else
10178 /* ldr rx,[ry] */
10179 bfd_put_32 (input_bfd, insn & 0xfffff000,
10180 contents + rel->r_offset);
10181 }
10182 else if ((insn & 0xfffffff0) == 0xe12fff30) /* blx rx */
10183 {
10184 if (is_local)
10185 /* nop */
10186 bfd_put_32 (input_bfd, 0xe1a00000, contents + rel->r_offset);
10187 else
10188 /* mov r0, rx */
10189 bfd_put_32 (input_bfd, 0xe1a00000 | (insn & 0xf),
10190 contents + rel->r_offset);
10191 }
10192 else
10193 {
4eca0228 10194 _bfd_error_handler
695344c0 10195 /* xgettext:c-format */
2dcf00ce 10196 (_("%pB(%pA+%#" PRIx64 "): "
90b6238f
AM		 10197 "unexpected %s instruction '%#lx' in TLS trampoline"),
10198 input_bfd, input_sec, (uint64_t) rel->r_offset,
10199 "ARM", insn);
0855e32b
NS		 10200 return bfd_reloc_notsupported;
10201 }
10202 break;
10203
10204 case R_ARM_TLS_CALL:
10205 /* GD->IE relaxation, turn the instruction into 'nop' or
10206 'ldr r0, [pc,r0]' */
10207 insn = is_local ? 0xe1a00000 : 0xe79f0000;
10208 bfd_put_32 (input_bfd, insn, contents + rel->r_offset);
10209 break;
b38cadfb 10210
0855e32b 10211 case R_ARM_THM_TLS_CALL:
6a631e86 10212 /* GD->IE relaxation. */
0855e32b
NS		 10213 if (!is_local)
10214 /* add r0,pc; ldr r0, [r0] */
10215 insn = 0x44786800;
60a019a0 10216 else if (using_thumb2 (globals))
0855e32b
NS		 10217 /* nop.w */
10218 insn = 0xf3af8000;
10219 else
10220 /* nop; nop */
10221 insn = 0xbf00bf00;
b38cadfb 10222
0855e32b
NS		 10223 bfd_put_16 (input_bfd, insn >> 16, contents + rel->r_offset);
10224 bfd_put_16 (input_bfd, insn & 0xffff, contents + rel->r_offset + 2);
10225 break;
10226 }
10227 return bfd_reloc_ok;
10228}
10229
4962c51a
MS		 10230/* For a given value of n, calculate the value of G_n as required to
10231 deal with group relocations. We return it in the form of an
10232 encoded constant-and-rotation, together with the final residual. If n is
10233 specified as less than zero, then final_residual is filled with the
10234 input value and no further action is performed. */
10235
10236static bfd_vma
10237calculate_group_reloc_mask (bfd_vma value, int n, bfd_vma *final_residual)
10238{
10239 int current_n;
10240 bfd_vma g_n;
10241 bfd_vma encoded_g_n = 0;
10242 bfd_vma residual = value; /* Also known as Y_n. */
10243
10244 for (current_n = 0; current_n <= n; current_n++)
10245 {
10246 int shift;
10247
10248 /* Calculate which part of the value to mask. */
10249 if (residual == 0)
99059e56 10250 shift = 0;
4962c51a 10251 else
99059e56
RM		 10252 {
10253 int msb;
10254
10255 /* Determine the most significant bit in the residual and
10256 align the resulting value to a 2-bit boundary. */
10257 for (msb = 30; msb >= 0; msb -= 2)
10258 if (residual & (3 << msb))
10259 break;
10260
10261 /* The desired shift is now (msb - 6), or zero, whichever
10262 is the greater. */
10263 shift = msb - 6;
10264 if (shift < 0)
10265 shift = 0;
10266 }
4962c51a
MS		 10267
10268 /* Calculate g_n in 32-bit as well as encoded constant+rotation form. */
10269 g_n = residual & (0xff << shift);
10270 encoded_g_n = (g_n >> shift)
99059e56 10271 | ((g_n <= 0xff ? 0 : (32 - shift) / 2) << 8);
4962c51a
MS		 10272
10273 /* Calculate the residual for the next time around. */
10274 residual &= ~g_n;
10275 }
10276
10277 *final_residual = residual;
10278
10279 return encoded_g_n;
10280}
10281
10282/* Given an ARM instruction, determine whether it is an ADD or a SUB.
10283 Returns 1 if it is an ADD, -1 if it is a SUB, and 0 otherwise. */
906e58ca 10284
4962c51a 10285static int
906e58ca 10286identify_add_or_sub (bfd_vma insn)
4962c51a
MS		 10287{
10288 int opcode = insn & 0x1e00000;
10289
10290 if (opcode == 1 << 23) /* ADD */
10291 return 1;
10292
10293 if (opcode == 1 << 22) /* SUB */
10294 return -1;
10295
10296 return 0;
10297}
10298
252b5132 10299/* Perform a relocation as part of a final link. */
9b485d32 10300
252b5132 10301static bfd_reloc_status_type
07d6d2b8
AM		 10302elf32_arm_final_link_relocate (reloc_howto_type * howto,
10303 bfd * input_bfd,
10304 bfd * output_bfd,
10305 asection * input_section,
10306 bfd_byte * contents,
10307 Elf_Internal_Rela * rel,
10308 bfd_vma value,
10309 struct bfd_link_info * info,
10310 asection * sym_sec,
10311 const char * sym_name,
10312 unsigned char st_type,
10313 enum arm_st_branch_type branch_type,
0945cdfd 10314 struct elf_link_hash_entry * h,
07d6d2b8
AM		 10315 bfd_boolean * unresolved_reloc_p,
10316 char ** error_message)
10317{
10318 unsigned long r_type = howto->type;
10319 unsigned long r_symndx;
10320 bfd_byte * hit_data = contents + rel->r_offset;
10321 bfd_vma * local_got_offsets;
10322 bfd_vma * local_tlsdesc_gotents;
10323 asection * sgot;
10324 asection * splt;
10325 asection * sreloc = NULL;
10326 asection * srelgot;
10327 bfd_vma addend;
10328 bfd_signed_vma signed_addend;
10329 unsigned char dynreloc_st_type;
10330 bfd_vma dynreloc_value;
ba96a88f 10331 struct elf32_arm_link_hash_table * globals;
34e77a92 10332 struct elf32_arm_link_hash_entry *eh;
07d6d2b8
AM		 10333 union gotplt_union *root_plt;
10334 struct arm_plt_info *arm_plt;
10335 bfd_vma plt_offset;
10336 bfd_vma gotplt_offset;
10337 bfd_boolean has_iplt_entry;
10338 bfd_boolean resolved_to_zero;
f21f3fe0 10339
9c504268 10340 globals = elf32_arm_hash_table (info);
4dfe6ac6
NC		 10341 if (globals == NULL)
10342 return bfd_reloc_notsupported;
9c504268 10343
0ffa91dd 10344 BFD_ASSERT (is_arm_elf (input_bfd));
47aeb64c 10345 BFD_ASSERT (howto != NULL);
0ffa91dd
NC		 10346
10347 /* Some relocation types map to different relocations depending on the
9c504268 10348 target. We pick the right one here. */
eb043451 10349 r_type = arm_real_reloc_type (globals, r_type);
0855e32b
NS		 10350
10351 /* It is possible to have linker relaxations on some TLS access
10352 models. Update our information here. */
10353 r_type = elf32_arm_tls_transition (info, r_type, h);
10354
eb043451
PB		 10355 if (r_type != howto->type)
10356 howto = elf32_arm_howto_from_type (r_type);
9c504268 10357
34e77a92 10358 eh = (struct elf32_arm_link_hash_entry *) h;
362d30a1 10359 sgot = globals->root.sgot;
252b5132 10360 local_got_offsets = elf_local_got_offsets (input_bfd);
0855e32b
NS		 10361 local_tlsdesc_gotents = elf32_arm_local_tlsdesc_gotent (input_bfd);
10362
34e77a92
RS		 10363 if (globals->root.dynamic_sections_created)
10364 srelgot = globals->root.srelgot;
10365 else
10366 srelgot = NULL;
10367
252b5132
RH		 10368 r_symndx = ELF32_R_SYM (rel->r_info);
10369
4e7fd91e 10370 if (globals->use_rel)
ba96a88f 10371 {
4e7fd91e
PB		 10372 addend = bfd_get_32 (input_bfd, hit_data) & howto->src_mask;
10373
10374 if (addend & ((howto->src_mask + 1) >> 1))
10375 {
10376 signed_addend = -1;
10377 signed_addend &= ~ howto->src_mask;
10378 signed_addend |= addend;
10379 }
10380 else
10381 signed_addend = addend;
ba96a88f
NC		 10382 }
10383 else
4e7fd91e 10384 addend = signed_addend = rel->r_addend;
f21f3fe0 10385
39f21624
NC		 10386 /* ST_BRANCH_TO_ARM is nonsense to thumb-only targets when we
10387 are resolving a function call relocation. */
10388 if (using_thumb_only (globals)
10389 && (r_type == R_ARM_THM_CALL
10390 || r_type == R_ARM_THM_JUMP24)
10391 && branch_type == ST_BRANCH_TO_ARM)
10392 branch_type = ST_BRANCH_TO_THUMB;
10393
34e77a92
RS		 10394 /* Record the symbol information that should be used in dynamic
10395 relocations. */
10396 dynreloc_st_type = st_type;
10397 dynreloc_value = value;
10398 if (branch_type == ST_BRANCH_TO_THUMB)
10399 dynreloc_value |= 1;
10400
10401 /* Find out whether the symbol has a PLT. Set ST_VALUE, BRANCH_TYPE and
10402 VALUE appropriately for relocations that we resolve at link time. */
10403 has_iplt_entry = FALSE;
4ba2ef8f
TP		 10404 if (elf32_arm_get_plt_info (input_bfd, globals, eh, r_symndx, &root_plt,
10405 &arm_plt)
34e77a92
RS		 10406 && root_plt->offset != (bfd_vma) -1)
10407 {
10408 plt_offset = root_plt->offset;
10409 gotplt_offset = arm_plt->got_offset;
10410
10411 if (h == NULL || eh->is_iplt)
10412 {
10413 has_iplt_entry = TRUE;
10414 splt = globals->root.iplt;
10415
10416 /* Populate .iplt entries here, because not all of them will
10417 be seen by finish_dynamic_symbol. The lower bit is set if
10418 we have already populated the entry. */
10419 if (plt_offset & 1)
10420 plt_offset--;
10421 else
10422 {
57460bcf
NC		 10423 if (elf32_arm_populate_plt_entry (output_bfd, info, root_plt, arm_plt,
10424 -1, dynreloc_value))
10425 root_plt->offset |= 1;
10426 else
10427 return bfd_reloc_notsupported;
34e77a92
RS		 10428 }
10429
10430 /* Static relocations always resolve to the .iplt entry. */
10431 st_type = STT_FUNC;
10432 value = (splt->output_section->vma
10433 + splt->output_offset
10434 + plt_offset);
10435 branch_type = ST_BRANCH_TO_ARM;
10436
10437 /* If there are non-call relocations that resolve to the .iplt
10438 entry, then all dynamic ones must too. */
10439 if (arm_plt->noncall_refcount != 0)
10440 {
10441 dynreloc_st_type = st_type;
10442 dynreloc_value = value;
10443 }
10444 }
10445 else
10446 /* We populate the .plt entry in finish_dynamic_symbol. */
10447 splt = globals->root.splt;
10448 }
10449 else
10450 {
10451 splt = NULL;
10452 plt_offset = (bfd_vma) -1;
10453 gotplt_offset = (bfd_vma) -1;
10454 }
10455
95b03e4a
L		 10456 resolved_to_zero = (h != NULL
10457 && UNDEFWEAK_NO_DYNAMIC_RELOC (info, h));
10458
252b5132
RH		 10459 switch (r_type)
10460 {
10461 case R_ARM_NONE:
28a094c2
DJ		 10462 /* We don't need to find a value for this symbol. It's just a
10463 marker. */
10464 *unresolved_reloc_p = FALSE;
252b5132
RH		 10465 return bfd_reloc_ok;
10466
00a97672
RS		 10467 case R_ARM_ABS12:
10468 if (!globals->vxworks_p)
10469 return elf32_arm_abs12_reloc (input_bfd, hit_data, value + addend);
1a0670f3 10470 /* Fall through. */
00a97672 10471
252b5132
RH		 10472 case R_ARM_PC24:
10473 case R_ARM_ABS32:
bb224fc3 10474 case R_ARM_ABS32_NOI:
252b5132 10475 case R_ARM_REL32:
bb224fc3 10476 case R_ARM_REL32_NOI:
5b5bb741
PB		 10477 case R_ARM_CALL:
10478 case R_ARM_JUMP24:
dfc5f959 10479 case R_ARM_XPC25:
eb043451 10480 case R_ARM_PREL31:
7359ea65 10481 case R_ARM_PLT32:
7359ea65
DJ		 10482 /* Handle relocations which should use the PLT entry. ABS32/REL32
10483 will use the symbol's value, which may point to a PLT entry, but we
10484 don't need to handle that here. If we created a PLT entry, all
5fa9e92f
CL		 10485 branches in this object should go to it, except if the PLT is too
10486 far away, in which case a long branch stub should be inserted. */
bb224fc3 10487 if ((r_type != R_ARM_ABS32 && r_type != R_ARM_REL32
99059e56 10488 && r_type != R_ARM_ABS32_NOI && r_type != R_ARM_REL32_NOI
155d87d7
CL		 10489 && r_type != R_ARM_CALL
10490 && r_type != R_ARM_JUMP24
10491 && r_type != R_ARM_PLT32)
34e77a92 10492 && plt_offset != (bfd_vma) -1)
7359ea65 10493 {
34e77a92
RS		 10494 /* If we've created a .plt section, and assigned a PLT entry
10495 to this function, it must either be a STT_GNU_IFUNC reference
10496 or not be known to bind locally. In other cases, we should
10497 have cleared the PLT entry by now. */
10498 BFD_ASSERT (has_iplt_entry || !SYMBOL_CALLS_LOCAL (info, h));
7359ea65
DJ		 10499
10500 value = (splt->output_section->vma
10501 + splt->output_offset
34e77a92 10502 + plt_offset);
0945cdfd 10503 *unresolved_reloc_p = FALSE;
7359ea65
DJ		 10504 return _bfd_final_link_relocate (howto, input_bfd, input_section,
10505 contents, rel->r_offset, value,
00a97672 10506 rel->r_addend);
7359ea65
DJ		 10507 }
10508
67687978
PB		 10509 /* When generating a shared object or relocatable executable, these
10510 relocations are copied into the output file to be resolved at
10511 run time. */
0e1862bb 10512 if ((bfd_link_pic (info)
e8b09b87
CL		 10513 || globals->root.is_relocatable_executable
10514 || globals->fdpic_p)
7359ea65 10515 && (input_section->flags & SEC_ALLOC)
4dfe6ac6 10516 && !(globals->vxworks_p
3348747a
NS		 10517 && strcmp (input_section->output_section->name,
10518 ".tls_vars") == 0)
bb224fc3 10519 && ((r_type != R_ARM_REL32 && r_type != R_ARM_REL32_NOI)
ee06dc07 10520 || !SYMBOL_CALLS_LOCAL (info, h))
ca6b5f82
AM		 10521 && !(input_bfd == globals->stub_bfd
10522 && strstr (input_section->name, STUB_SUFFIX))
7359ea65 10523 && (h == NULL
95b03e4a
L		 10524 || (ELF_ST_VISIBILITY (h->other) == STV_DEFAULT
10525 && !resolved_to_zero)
7359ea65
DJ		 10526 || h->root.type != bfd_link_hash_undefweak)
10527 && r_type != R_ARM_PC24
5b5bb741
PB		 10528 && r_type != R_ARM_CALL
10529 && r_type != R_ARM_JUMP24
ee06dc07 10530 && r_type != R_ARM_PREL31
7359ea65 10531 && r_type != R_ARM_PLT32)
252b5132 10532 {
947216bf 10533 Elf_Internal_Rela outrel;
b34976b6 10534 bfd_boolean skip, relocate;
e8b09b87 10535 int isrofixup = 0;
f21f3fe0 10536
52db4ec2
JW		 10537 if ((r_type == R_ARM_REL32 || r_type == R_ARM_REL32_NOI)
10538 && !h->def_regular)
10539 {
10540 char *v = _("shared object");
10541
0e1862bb 10542 if (bfd_link_executable (info))
52db4ec2
JW		 10543 v = _("PIE executable");
10544
4eca0228 10545 _bfd_error_handler
871b3ab2 10546 (_("%pB: relocation %s against external or undefined symbol `%s'"
52db4ec2
JW		 10547 " can not be used when making a %s; recompile with -fPIC"), input_bfd,
10548 elf32_arm_howto_table_1[r_type].name, h->root.root.string, v);
10549 return bfd_reloc_notsupported;
10550 }
10551
0945cdfd
DJ		 10552 *unresolved_reloc_p = FALSE;
10553
34e77a92 10554 if (sreloc == NULL && globals->root.dynamic_sections_created)
252b5132 10555 {
83bac4b0
NC		 10556 sreloc = _bfd_elf_get_dynamic_reloc_section (input_bfd, input_section,
10557 ! globals->use_rel);
f21f3fe0 10558
83bac4b0 10559 if (sreloc == NULL)
252b5132 10560 return bfd_reloc_notsupported;
252b5132 10561 }
f21f3fe0 10562
b34976b6
AM		 10563 skip = FALSE;
10564 relocate = FALSE;
f21f3fe0 10565
00a97672 10566 outrel.r_addend = addend;
c629eae0
JJ		 10567 outrel.r_offset =
10568 _bfd_elf_section_offset (output_bfd, info, input_section,
10569 rel->r_offset);
10570 if (outrel.r_offset == (bfd_vma) -1)
b34976b6 10571 skip = TRUE;
0bb2d96a 10572 else if (outrel.r_offset == (bfd_vma) -2)
b34976b6 10573 skip = TRUE, relocate = TRUE;
252b5132
RH		 10574 outrel.r_offset += (input_section->output_section->vma
10575 + input_section->output_offset);
f21f3fe0 10576
252b5132 10577 if (skip)
0bb2d96a 10578 memset (&outrel, 0, sizeof outrel);
5e681ec4
PB		 10579 else if (h != NULL
10580 && h->dynindx != -1
0e1862bb 10581 && (!bfd_link_pic (info)
1dcb9720
JW		 10582 || !(bfd_link_pie (info)
10583 || SYMBOLIC_BIND (info, h))
f5385ebf 10584 || !h->def_regular))
5e681ec4 10585 outrel.r_info = ELF32_R_INFO (h->dynindx, r_type);
252b5132
RH		 10586 else
10587 {
a16385dc
MM		 10588 int symbol;
10589
5e681ec4 10590 /* This symbol is local, or marked to become local. */
e8b09b87
CL		 10591 BFD_ASSERT (r_type == R_ARM_ABS32 || r_type == R_ARM_ABS32_NOI
10592 || (globals->fdpic_p && !bfd_link_pic(info)));
a16385dc 10593 if (globals->symbian_p)
6366ff1e 10594 {
74541ad4
AM		 10595 asection *osec;
10596
6366ff1e
MM		 10597 /* On Symbian OS, the data segment and text segement
10598 can be relocated independently. Therefore, we
10599 must indicate the segment to which this
10600 relocation is relative. The BPABI allows us to
10601 use any symbol in the right segment; we just use
10602 the section symbol as it is convenient. (We
10603 cannot use the symbol given by "h" directly as it
74541ad4
AM		 10604 will not appear in the dynamic symbol table.)
10605
10606 Note that the dynamic linker ignores the section
10607 symbol value, so we don't subtract osec->vma
10608 from the emitted reloc addend. */
10dbd1f3 10609 if (sym_sec)
74541ad4 10610 osec = sym_sec->output_section;
10dbd1f3 10611 else
74541ad4
AM		 10612 osec = input_section->output_section;
10613 symbol = elf_section_data (osec)->dynindx;
10614 if (symbol == 0)
10615 {
10616 struct elf_link_hash_table *htab = elf_hash_table (info);
10617
10618 if ((osec->flags & SEC_READONLY) == 0
10619 && htab->data_index_section != NULL)
10620 osec = htab->data_index_section;
10621 else
10622 osec = htab->text_index_section;
10623 symbol = elf_section_data (osec)->dynindx;
10624 }
6366ff1e
MM		 10625 BFD_ASSERT (symbol != 0);
10626 }
a16385dc
MM		 10627 else
10628 /* On SVR4-ish systems, the dynamic loader cannot
10629 relocate the text and data segments independently,
10630 so the symbol does not matter. */
10631 symbol = 0;
34e77a92
RS		 10632 if (dynreloc_st_type == STT_GNU_IFUNC)
10633 /* We have an STT_GNU_IFUNC symbol that doesn't resolve
10634 to the .iplt entry. Instead, every non-call reference
10635 must use an R_ARM_IRELATIVE relocation to obtain the
10636 correct run-time address. */
10637 outrel.r_info = ELF32_R_INFO (symbol, R_ARM_IRELATIVE);
e8b09b87
CL		 10638 else if (globals->fdpic_p && !bfd_link_pic(info))
10639 isrofixup = 1;
34e77a92
RS		 10640 else
10641 outrel.r_info = ELF32_R_INFO (symbol, R_ARM_RELATIVE);
00a97672
RS		 10642 if (globals->use_rel)
10643 relocate = TRUE;
10644 else
34e77a92 10645 outrel.r_addend += dynreloc_value;
252b5132 10646 }
f21f3fe0 10647
e8b09b87
CL		 10648 if (isrofixup)
10649 arm_elf_add_rofixup(output_bfd, globals->srofixup, outrel.r_offset);
10650 else
10651 elf32_arm_add_dynreloc (output_bfd, info, sreloc, &outrel);
9a5aca8c 10652
f21f3fe0 10653 /* If this reloc is against an external symbol, we do not want to
252b5132 10654 fiddle with the addend. Otherwise, we need to include the symbol
9b485d32 10655 value so that it becomes an addend for the dynamic reloc. */
252b5132
RH		 10656 if (! relocate)
10657 return bfd_reloc_ok;
9a5aca8c 10658
f21f3fe0 10659 return _bfd_final_link_relocate (howto, input_bfd, input_section,
34e77a92
RS		 10660 contents, rel->r_offset,
10661 dynreloc_value, (bfd_vma) 0);
252b5132
RH		 10662 }
10663 else switch (r_type)
10664 {
00a97672
RS		 10665 case R_ARM_ABS12:
10666 return elf32_arm_abs12_reloc (input_bfd, hit_data, value + addend);
10667
dfc5f959 10668 case R_ARM_XPC25: /* Arm BLX instruction. */
5b5bb741
PB		 10669 case R_ARM_CALL:
10670 case R_ARM_JUMP24:
8029a119 10671 case R_ARM_PC24: /* Arm B/BL instruction. */
7359ea65 10672 case R_ARM_PLT32:
906e58ca 10673 {
906e58ca
NC		 10674 struct elf32_arm_stub_hash_entry *stub_entry = NULL;
10675
dfc5f959 10676 if (r_type == R_ARM_XPC25)
252b5132 10677 {
dfc5f959
NC		 10678 /* Check for Arm calling Arm function. */
10679 /* FIXME: Should we translate the instruction into a BL
10680 instruction instead ? */
35fc36a8 10681 if (branch_type != ST_BRANCH_TO_THUMB)
4eca0228 10682 _bfd_error_handler
90b6238f
AM		 10683 (_("\%pB: warning: %s BLX instruction targets"
10684 " %s function '%s'"),
10685 input_bfd, "ARM",
10686 "ARM", h ? h->root.root.string : "(local)");
dfc5f959 10687 }
155d87d7 10688 else if (r_type == R_ARM_PC24)
dfc5f959
NC		 10689 {
10690 /* Check for Arm calling Thumb function. */
35fc36a8 10691 if (branch_type == ST_BRANCH_TO_THUMB)
dfc5f959 10692 {
f2a9dd69
DJ		 10693 if (elf32_arm_to_thumb_stub (info, sym_name, input_bfd,
10694 output_bfd, input_section,
10695 hit_data, sym_sec, rel->r_offset,
10696 signed_addend, value,
10697 error_message))
10698 return bfd_reloc_ok;
10699 else
10700 return bfd_reloc_dangerous;
dfc5f959 10701 }
252b5132 10702 }
ba96a88f 10703
906e58ca 10704 /* Check if a stub has to be inserted because the
8029a119 10705 destination is too far or we are changing mode. */
155d87d7
CL		 10706 if ( r_type == R_ARM_CALL
10707 || r_type == R_ARM_JUMP24
10708 || r_type == R_ARM_PLT32)
906e58ca 10709 {
fe33d2fa
CL		 10710 enum elf32_arm_stub_type stub_type = arm_stub_none;
10711 struct elf32_arm_link_hash_entry *hash;
10712
10713 hash = (struct elf32_arm_link_hash_entry *) h;
10714 stub_type = arm_type_of_stub (info, input_section, rel,
34e77a92
RS		 10715 st_type, &branch_type,
10716 hash, value, sym_sec,
fe33d2fa 10717 input_bfd, sym_name);
5fa9e92f 10718
fe33d2fa 10719 if (stub_type != arm_stub_none)
906e58ca
NC		 10720 {
10721 /* The target is out of reach, so redirect the
10722 branch to the local stub for this function. */
906e58ca
NC		 10723 stub_entry = elf32_arm_get_stub_entry (input_section,
10724 sym_sec, h,
fe33d2fa
CL		 10725 rel, globals,
10726 stub_type);
9cd3e4e5
NC		 10727 {
10728 if (stub_entry != NULL)
10729 value = (stub_entry->stub_offset
10730 + stub_entry->stub_sec->output_offset
10731 + stub_entry->stub_sec->output_section->vma);
10732
10733 if (plt_offset != (bfd_vma) -1)
10734 *unresolved_reloc_p = FALSE;
10735 }
906e58ca 10736 }
fe33d2fa
CL		 10737 else
10738 {
10739 /* If the call goes through a PLT entry, make sure to
10740 check distance to the right destination address. */
34e77a92 10741 if (plt_offset != (bfd_vma) -1)
fe33d2fa
CL		 10742 {
10743 value = (splt->output_section->vma
10744 + splt->output_offset
34e77a92 10745 + plt_offset);
fe33d2fa
CL		 10746 *unresolved_reloc_p = FALSE;
10747 /* The PLT entry is in ARM mode, regardless of the
10748 target function. */
35fc36a8 10749 branch_type = ST_BRANCH_TO_ARM;
fe33d2fa
CL		 10750 }
10751 }
906e58ca
NC		 10752 }
10753
dea514f5
PB		 10754 /* The ARM ELF ABI says that this reloc is computed as: S - P + A
10755 where:
10756 S is the address of the symbol in the relocation.
10757 P is address of the instruction being relocated.
10758 A is the addend (extracted from the instruction) in bytes.
10759
10760 S is held in 'value'.
10761 P is the base address of the section containing the
10762 instruction plus the offset of the reloc into that
10763 section, ie:
10764 (input_section->output_section->vma +
10765 input_section->output_offset +
10766 rel->r_offset).
10767 A is the addend, converted into bytes, ie:
10768 (signed_addend * 4)
10769
10770 Note: None of these operations have knowledge of the pipeline
10771 size of the processor, thus it is up to the assembler to
10772 encode this information into the addend. */
10773 value -= (input_section->output_section->vma
10774 + input_section->output_offset);
10775 value -= rel->r_offset;
4e7fd91e
PB		 10776 if (globals->use_rel)
10777 value += (signed_addend << howto->size);
10778 else
10779 /* RELA addends do not have to be adjusted by howto->size. */
10780 value += signed_addend;
23080146 10781
dcb5e6e6
NC		 10782 signed_addend = value;
10783 signed_addend >>= howto->rightshift;
9a5aca8c 10784
5ab79981 10785 /* A branch to an undefined weak symbol is turned into a jump to
ffcb4889 10786 the next instruction unless a PLT entry will be created.
77b4f08f 10787 Do the same for local undefined symbols (but not for STN_UNDEF).
cd1dac3d
DG		 10788 The jump to the next instruction is optimized as a NOP depending
10789 on the architecture. */
ffcb4889 10790 if (h ? (h->root.type == bfd_link_hash_undefweak
34e77a92 10791 && plt_offset == (bfd_vma) -1)
77b4f08f 10792 : r_symndx != STN_UNDEF && bfd_is_und_section (sym_sec))
5ab79981 10793 {
cd1dac3d
DG		 10794 value = (bfd_get_32 (input_bfd, hit_data) & 0xf0000000);
10795
10796 if (arch_has_arm_nop (globals))
10797 value |= 0x0320f000;
10798 else
10799 value |= 0x01a00000; /* Using pre-UAL nop: mov r0, r0. */
5ab79981
PB		 10800 }
10801 else
59f2c4e7 10802 {
9b485d32 10803 /* Perform a signed range check. */
dcb5e6e6 10804 if ( signed_addend > ((bfd_signed_vma) (howto->dst_mask >> 1))
59f2c4e7
NC		 10805 || signed_addend < - ((bfd_signed_vma) ((howto->dst_mask + 1) >> 1)))
10806 return bfd_reloc_overflow;
9a5aca8c 10807
5ab79981 10808 addend = (value & 2);
39b41c9c 10809
5ab79981
PB		 10810 value = (signed_addend & howto->dst_mask)
10811 | (bfd_get_32 (input_bfd, hit_data) & (~ howto->dst_mask));
39b41c9c 10812
5ab79981
PB		 10813 if (r_type == R_ARM_CALL)
10814 {
155d87d7 10815 /* Set the H bit in the BLX instruction. */
35fc36a8 10816 if (branch_type == ST_BRANCH_TO_THUMB)
155d87d7
CL		 10817 {
10818 if (addend)
10819 value |= (1 << 24);
10820 else
10821 value &= ~(bfd_vma)(1 << 24);
10822 }
10823
5ab79981 10824 /* Select the correct instruction (BL or BLX). */
906e58ca 10825 /* Only if we are not handling a BL to a stub. In this
8029a119 10826 case, mode switching is performed by the stub. */
35fc36a8 10827 if (branch_type == ST_BRANCH_TO_THUMB && !stub_entry)
5ab79981 10828 value |= (1 << 28);
63e1a0fc 10829 else if (stub_entry || branch_type != ST_BRANCH_UNKNOWN)
5ab79981
PB		 10830 {
10831 value &= ~(bfd_vma)(1 << 28);
10832 value |= (1 << 24);
10833 }
39b41c9c
PB		 10834 }
10835 }
906e58ca 10836 }
252b5132 10837 break;
f21f3fe0 10838
252b5132
RH		 10839 case R_ARM_ABS32:
10840 value += addend;
35fc36a8 10841 if (branch_type == ST_BRANCH_TO_THUMB)
252b5132
RH		 10842 value |= 1;
10843 break;
f21f3fe0 10844
bb224fc3
MS		 10845 case R_ARM_ABS32_NOI:
10846 value += addend;
10847 break;
10848
252b5132 10849 case R_ARM_REL32:
a8bc6c78 10850 value += addend;
35fc36a8 10851 if (branch_type == ST_BRANCH_TO_THUMB)
a8bc6c78 10852 value |= 1;
252b5132 10853 value -= (input_section->output_section->vma
62efb346 10854 + input_section->output_offset + rel->r_offset);
252b5132 10855 break;
eb043451 10856
bb224fc3
MS		 10857 case R_ARM_REL32_NOI:
10858 value += addend;
10859 value -= (input_section->output_section->vma
10860 + input_section->output_offset + rel->r_offset);
10861 break;
10862
eb043451
PB		 10863 case R_ARM_PREL31:
10864 value -= (input_section->output_section->vma
10865 + input_section->output_offset + rel->r_offset);
10866 value += signed_addend;
10867 if (! h || h->root.type != bfd_link_hash_undefweak)
10868 {
8029a119 10869 /* Check for overflow. */
eb043451
PB		 10870 if ((value ^ (value >> 1)) & (1 << 30))
10871 return bfd_reloc_overflow;
10872 }
10873 value &= 0x7fffffff;
10874 value |= (bfd_get_32 (input_bfd, hit_data) & 0x80000000);
35fc36a8 10875 if (branch_type == ST_BRANCH_TO_THUMB)
eb043451
PB		 10876 value |= 1;
10877 break;
252b5132 10878 }
f21f3fe0 10879
252b5132
RH		 10880 bfd_put_32 (input_bfd, value, hit_data);
10881 return bfd_reloc_ok;
10882
10883 case R_ARM_ABS8:
fd0fd00c
MJ		 10884 /* PR 16202: Refectch the addend using the correct size. */
10885 if (globals->use_rel)
10886 addend = bfd_get_8 (input_bfd, hit_data);
252b5132 10887 value += addend;
4e67d4ca
DG		 10888
10889 /* There is no way to tell whether the user intended to use a signed or
10890 unsigned addend. When checking for overflow we accept either,
10891 as specified by the AAELF. */
10892 if ((long) value > 0xff || (long) value < -0x80)
252b5132
RH		 10893 return bfd_reloc_overflow;
10894
10895 bfd_put_8 (input_bfd, value, hit_data);
10896 return bfd_reloc_ok;
10897
10898 case R_ARM_ABS16:
fd0fd00c
MJ		 10899 /* PR 16202: Refectch the addend using the correct size. */
10900 if (globals->use_rel)
10901 addend = bfd_get_16 (input_bfd, hit_data);
252b5132
RH		 10902 value += addend;
10903
4e67d4ca
DG		 10904 /* See comment for R_ARM_ABS8. */
10905 if ((long) value > 0xffff || (long) value < -0x8000)
252b5132
RH		 10906 return bfd_reloc_overflow;
10907
10908 bfd_put_16 (input_bfd, value, hit_data);
10909 return bfd_reloc_ok;
10910
252b5132 10911 case R_ARM_THM_ABS5:
9b485d32 10912 /* Support ldr and str instructions for the thumb. */
4e7fd91e
PB		 10913 if (globals->use_rel)
10914 {
10915 /* Need to refetch addend. */
10916 addend = bfd_get_16 (input_bfd, hit_data) & howto->src_mask;
10917 /* ??? Need to determine shift amount from operand size. */
10918 addend >>= howto->rightshift;
10919 }
252b5132
RH		 10920 value += addend;
10921
10922 /* ??? Isn't value unsigned? */
10923 if ((long) value > 0x1f || (long) value < -0x10)
10924 return bfd_reloc_overflow;
10925
10926 /* ??? Value needs to be properly shifted into place first. */
10927 value |= bfd_get_16 (input_bfd, hit_data) & 0xf83f;
10928 bfd_put_16 (input_bfd, value, hit_data);
10929 return bfd_reloc_ok;
10930
2cab6cc3
MS		 10931 case R_ARM_THM_ALU_PREL_11_0:
10932 /* Corresponds to: addw.w reg, pc, #offset (and similarly for subw). */
10933 {
10934 bfd_vma insn;
10935 bfd_signed_vma relocation;
10936
10937 insn = (bfd_get_16 (input_bfd, hit_data) << 16)
99059e56 10938 | bfd_get_16 (input_bfd, hit_data + 2);
2cab6cc3 10939
99059e56
RM		 10940 if (globals->use_rel)
10941 {
10942 signed_addend = (insn & 0xff) | ((insn & 0x7000) >> 4)
10943 | ((insn & (1 << 26)) >> 15);
10944 if (insn & 0xf00000)
10945 signed_addend = -signed_addend;
10946 }
2cab6cc3
MS		 10947
10948 relocation = value + signed_addend;
79f08007 10949 relocation -= Pa (input_section->output_section->vma
99059e56
RM		 10950 + input_section->output_offset
10951 + rel->r_offset);
2cab6cc3 10952
8c65b54f
CS		 10953 /* PR 21523: Use an absolute value. The user of this reloc will
10954 have already selected an ADD or SUB insn appropriately. */
453f8e1e 10955 value = llabs (relocation);
2cab6cc3 10956
99059e56
RM		 10957 if (value >= 0x1000)
10958 return bfd_reloc_overflow;
2cab6cc3 10959
e645cf40
AG		 10960 /* Destination is Thumb. Force bit 0 to 1 to reflect this. */
10961 if (branch_type == ST_BRANCH_TO_THUMB)
10962 value |= 1;
10963
2cab6cc3 10964 insn = (insn & 0xfb0f8f00) | (value & 0xff)
99059e56
RM		 10965 | ((value & 0x700) << 4)
10966 | ((value & 0x800) << 15);
10967 if (relocation < 0)
10968 insn |= 0xa00000;
2cab6cc3
MS		 10969
10970 bfd_put_16 (input_bfd, insn >> 16, hit_data);
10971 bfd_put_16 (input_bfd, insn & 0xffff, hit_data + 2);
10972
99059e56 10973 return bfd_reloc_ok;
2cab6cc3
MS		 10974 }
10975
e1ec24c6
NC		 10976 case R_ARM_THM_PC8:
10977 /* PR 10073: This reloc is not generated by the GNU toolchain,
10978 but it is supported for compatibility with third party libraries
10979 generated by other compilers, specifically the ARM/IAR. */
10980 {
10981 bfd_vma insn;
10982 bfd_signed_vma relocation;
10983
10984 insn = bfd_get_16 (input_bfd, hit_data);
10985
99059e56 10986 if (globals->use_rel)
79f08007 10987 addend = ((((insn & 0x00ff) << 2) + 4) & 0x3ff) -4;
e1ec24c6
NC		 10988
10989 relocation = value + addend;
79f08007 10990 relocation -= Pa (input_section->output_section->vma
99059e56
RM		 10991 + input_section->output_offset
10992 + rel->r_offset);
e1ec24c6 10993
b6518b38 10994 value = relocation;
e1ec24c6
NC		 10995
10996 /* We do not check for overflow of this reloc. Although strictly
10997 speaking this is incorrect, it appears to be necessary in order
10998 to work with IAR generated relocs. Since GCC and GAS do not
10999 generate R_ARM_THM_PC8 relocs, the lack of a check should not be
11000 a problem for them. */
11001 value &= 0x3fc;
11002
11003 insn = (insn & 0xff00) | (value >> 2);
11004
11005 bfd_put_16 (input_bfd, insn, hit_data);
11006
99059e56 11007 return bfd_reloc_ok;
e1ec24c6
NC		 11008 }
11009
2cab6cc3
MS		 11010 case R_ARM_THM_PC12:
11011 /* Corresponds to: ldr.w reg, [pc, #offset]. */
11012 {
11013 bfd_vma insn;
11014 bfd_signed_vma relocation;
11015
11016 insn = (bfd_get_16 (input_bfd, hit_data) << 16)
99059e56 11017 | bfd_get_16 (input_bfd, hit_data + 2);
2cab6cc3 11018
99059e56
RM		 11019 if (globals->use_rel)
11020 {
11021 signed_addend = insn & 0xfff;
11022 if (!(insn & (1 << 23)))
11023 signed_addend = -signed_addend;
11024 }
2cab6cc3
MS		 11025
11026 relocation = value + signed_addend;
79f08007 11027 relocation -= Pa (input_section->output_section->vma
99059e56
RM		 11028 + input_section->output_offset
11029 + rel->r_offset);
2cab6cc3 11030
b6518b38 11031 value = relocation;
2cab6cc3 11032
99059e56
RM		 11033 if (value >= 0x1000)
11034 return bfd_reloc_overflow;
2cab6cc3
MS		 11035
11036 insn = (insn & 0xff7ff000) | value;
99059e56
RM		 11037 if (relocation >= 0)
11038 insn |= (1 << 23);
2cab6cc3
MS		 11039
11040 bfd_put_16 (input_bfd, insn >> 16, hit_data);
11041 bfd_put_16 (input_bfd, insn & 0xffff, hit_data + 2);
11042
99059e56 11043 return bfd_reloc_ok;
2cab6cc3
MS		 11044 }
11045
dfc5f959 11046 case R_ARM_THM_XPC22:
c19d1205 11047 case R_ARM_THM_CALL:
bd97cb95 11048 case R_ARM_THM_JUMP24:
dfc5f959 11049 /* Thumb BL (branch long instruction). */
252b5132 11050 {
b34976b6 11051 bfd_vma relocation;
99059e56 11052 bfd_vma reloc_sign;
b34976b6
AM		 11053 bfd_boolean overflow = FALSE;
11054 bfd_vma upper_insn = bfd_get_16 (input_bfd, hit_data);
11055 bfd_vma lower_insn = bfd_get_16 (input_bfd, hit_data + 2);
e95de063
MS		 11056 bfd_signed_vma reloc_signed_max;
11057 bfd_signed_vma reloc_signed_min;
b34976b6 11058 bfd_vma check;
252b5132 11059 bfd_signed_vma signed_check;
e95de063 11060 int bitsize;
cd1dac3d 11061 const int thumb2 = using_thumb2 (globals);
5e866f5a 11062 const int thumb2_bl = using_thumb2_bl (globals);
252b5132 11063
5ab79981 11064 /* A branch to an undefined weak symbol is turned into a jump to
cd1dac3d
DG		 11065 the next instruction unless a PLT entry will be created.
11066 The jump to the next instruction is optimized as a NOP.W for
11067 Thumb-2 enabled architectures. */
19540007 11068 if (h && h->root.type == bfd_link_hash_undefweak
34e77a92 11069 && plt_offset == (bfd_vma) -1)
5ab79981 11070 {
60a019a0 11071 if (thumb2)
cd1dac3d
DG		 11072 {
11073 bfd_put_16 (input_bfd, 0xf3af, hit_data);
11074 bfd_put_16 (input_bfd, 0x8000, hit_data + 2);
11075 }
11076 else
11077 {
11078 bfd_put_16 (input_bfd, 0xe000, hit_data);
11079 bfd_put_16 (input_bfd, 0xbf00, hit_data + 2);
11080 }
5ab79981
PB		 11081 return bfd_reloc_ok;
11082 }
11083
e95de063 11084 /* Fetch the addend. We use the Thumb-2 encoding (backwards compatible
99059e56 11085 with Thumb-1) involving the J1 and J2 bits. */
4e7fd91e
PB		 11086 if (globals->use_rel)
11087 {
99059e56
RM		 11088 bfd_vma s = (upper_insn & (1 << 10)) >> 10;
11089 bfd_vma upper = upper_insn & 0x3ff;
11090 bfd_vma lower = lower_insn & 0x7ff;
e95de063
MS		 11091 bfd_vma j1 = (lower_insn & (1 << 13)) >> 13;
11092 bfd_vma j2 = (lower_insn & (1 << 11)) >> 11;
99059e56
RM		 11093 bfd_vma i1 = j1 ^ s ? 0 : 1;
11094 bfd_vma i2 = j2 ^ s ? 0 : 1;
e95de063 11095
99059e56
RM		 11096 addend = (i1 << 23) | (i2 << 22) | (upper << 12) | (lower << 1);
11097 /* Sign extend. */
11098 addend = (addend | ((s ? 0 : 1) << 24)) - (1 << 24);
e95de063 11099
4e7fd91e
PB		 11100 signed_addend = addend;
11101 }
cb1afa5c 11102
dfc5f959
NC		 11103 if (r_type == R_ARM_THM_XPC22)
11104 {
11105 /* Check for Thumb to Thumb call. */
11106 /* FIXME: Should we translate the instruction into a BL
11107 instruction instead ? */
35fc36a8 11108 if (branch_type == ST_BRANCH_TO_THUMB)
4eca0228 11109 _bfd_error_handler
90b6238f
AM		 11110 (_("%pB: warning: %s BLX instruction targets"
11111 " %s function '%s'"),
11112 input_bfd, "Thumb",
11113 "Thumb", h ? h->root.root.string : "(local)");
dfc5f959
NC		 11114 }
11115 else
252b5132 11116 {
dfc5f959
NC		 11117 /* If it is not a call to Thumb, assume call to Arm.
11118 If it is a call relative to a section name, then it is not a
b7693d02
DJ		 11119 function call at all, but rather a long jump. Calls through
11120 the PLT do not require stubs. */
34e77a92 11121 if (branch_type == ST_BRANCH_TO_ARM && plt_offset == (bfd_vma) -1)
dfc5f959 11122 {
bd97cb95 11123 if (globals->use_blx && r_type == R_ARM_THM_CALL)
39b41c9c
PB		 11124 {
11125 /* Convert BL to BLX. */
11126 lower_insn = (lower_insn & ~0x1000) | 0x0800;
11127 }
155d87d7
CL		 11128 else if (( r_type != R_ARM_THM_CALL)
11129 && (r_type != R_ARM_THM_JUMP24))
8029a119
NC		 11130 {
11131 if (elf32_thumb_to_arm_stub
11132 (info, sym_name, input_bfd, output_bfd, input_section,
11133 hit_data, sym_sec, rel->r_offset, signed_addend, value,
11134 error_message))
11135 return bfd_reloc_ok;
11136 else
11137 return bfd_reloc_dangerous;
11138 }
da5938a2 11139 }
35fc36a8
RS		 11140 else if (branch_type == ST_BRANCH_TO_THUMB
11141 && globals->use_blx
bd97cb95 11142 && r_type == R_ARM_THM_CALL)
39b41c9c
PB		 11143 {
11144 /* Make sure this is a BL. */
11145 lower_insn |= 0x1800;
11146 }
252b5132 11147 }
f21f3fe0 11148
fe33d2fa 11149 enum elf32_arm_stub_type stub_type = arm_stub_none;
155d87d7 11150 if (r_type == R_ARM_THM_CALL || r_type == R_ARM_THM_JUMP24)
906e58ca
NC		 11151 {
11152 /* Check if a stub has to be inserted because the destination
8029a119 11153 is too far. */
fe33d2fa
CL		 11154 struct elf32_arm_stub_hash_entry *stub_entry;
11155 struct elf32_arm_link_hash_entry *hash;
11156
11157 hash = (struct elf32_arm_link_hash_entry *) h;
11158
11159 stub_type = arm_type_of_stub (info, input_section, rel,
34e77a92
RS		 11160 st_type, &branch_type,
11161 hash, value, sym_sec,
fe33d2fa
CL		 11162 input_bfd, sym_name);
11163
11164 if (stub_type != arm_stub_none)
906e58ca
NC		 11165 {
11166 /* The target is out of reach or we are changing modes, so
11167 redirect the branch to the local stub for this
11168 function. */
11169 stub_entry = elf32_arm_get_stub_entry (input_section,
11170 sym_sec, h,
fe33d2fa
CL		 11171 rel, globals,
11172 stub_type);
906e58ca 11173 if (stub_entry != NULL)
9cd3e4e5
NC		 11174 {
11175 value = (stub_entry->stub_offset
11176 + stub_entry->stub_sec->output_offset
11177 + stub_entry->stub_sec->output_section->vma);
11178
11179 if (plt_offset != (bfd_vma) -1)
11180 *unresolved_reloc_p = FALSE;
11181 }
906e58ca 11182
f4ac8484 11183 /* If this call becomes a call to Arm, force BLX. */
155d87d7 11184 if (globals->use_blx && (r_type == R_ARM_THM_CALL))
f4ac8484
DJ		 11185 {
11186 if ((stub_entry
11187 && !arm_stub_is_thumb (stub_entry->stub_type))
35fc36a8 11188 || branch_type != ST_BRANCH_TO_THUMB)
f4ac8484
DJ		 11189 lower_insn = (lower_insn & ~0x1000) | 0x0800;
11190 }
906e58ca
NC		 11191 }
11192 }
11193
fe33d2fa 11194 /* Handle calls via the PLT. */
34e77a92 11195 if (stub_type == arm_stub_none && plt_offset != (bfd_vma) -1)
fe33d2fa
CL		 11196 {
11197 value = (splt->output_section->vma
11198 + splt->output_offset
34e77a92 11199 + plt_offset);
fe33d2fa 11200
eed94f8f
NC		 11201 if (globals->use_blx
11202 && r_type == R_ARM_THM_CALL
11203 && ! using_thumb_only (globals))
fe33d2fa
CL		 11204 {
11205 /* If the Thumb BLX instruction is available, convert
11206 the BL to a BLX instruction to call the ARM-mode
11207 PLT entry. */
11208 lower_insn = (lower_insn & ~0x1000) | 0x0800;
35fc36a8 11209 branch_type = ST_BRANCH_TO_ARM;
fe33d2fa
CL		 11210 }
11211 else
11212 {
eed94f8f
NC		 11213 if (! using_thumb_only (globals))
11214 /* Target the Thumb stub before the ARM PLT entry. */
11215 value -= PLT_THUMB_STUB_SIZE;
35fc36a8 11216 branch_type = ST_BRANCH_TO_THUMB;
fe33d2fa
CL		 11217 }
11218 *unresolved_reloc_p = FALSE;
11219 }
11220
ba96a88f 11221 relocation = value + signed_addend;
f21f3fe0 11222
252b5132 11223 relocation -= (input_section->output_section->vma
ba96a88f
NC		 11224 + input_section->output_offset
11225 + rel->r_offset);
9a5aca8c 11226
252b5132
RH		 11227 check = relocation >> howto->rightshift;
11228
11229 /* If this is a signed value, the rightshift just dropped
11230 leading 1 bits (assuming twos complement). */
11231 if ((bfd_signed_vma) relocation >= 0)
11232 signed_check = check;
11233 else
11234 signed_check = check | ~((bfd_vma) -1 >> howto->rightshift);
11235
e95de063
MS		 11236 /* Calculate the permissable maximum and minimum values for
11237 this relocation according to whether we're relocating for
11238 Thumb-2 or not. */
11239 bitsize = howto->bitsize;
5e866f5a 11240 if (!thumb2_bl)
e95de063 11241 bitsize -= 2;
f6ebfac0 11242 reloc_signed_max = (1 << (bitsize - 1)) - 1;
e95de063
MS		 11243 reloc_signed_min = ~reloc_signed_max;
11244
252b5132 11245 /* Assumes two's complement. */
ba96a88f 11246 if (signed_check > reloc_signed_max || signed_check < reloc_signed_min)
b34976b6 11247 overflow = TRUE;
252b5132 11248
bd97cb95 11249 if ((lower_insn & 0x5000) == 0x4000)
c62e1cc3
NC		 11250 /* For a BLX instruction, make sure that the relocation is rounded up
11251 to a word boundary. This follows the semantics of the instruction
11252 which specifies that bit 1 of the target address will come from bit
11253 1 of the base address. */
11254 relocation = (relocation + 2) & ~ 3;
cb1afa5c 11255
e95de063
MS		 11256 /* Put RELOCATION back into the insn. Assumes two's complement.
11257 We use the Thumb-2 encoding, which is safe even if dealing with
11258 a Thumb-1 instruction by virtue of our overflow check above. */
99059e56 11259 reloc_sign = (signed_check < 0) ? 1 : 0;
e95de063 11260 upper_insn = (upper_insn & ~(bfd_vma) 0x7ff)
99059e56
RM		 11261 | ((relocation >> 12) & 0x3ff)
11262 | (reloc_sign << 10);
906e58ca 11263 lower_insn = (lower_insn & ~(bfd_vma) 0x2fff)
99059e56
RM		 11264 | (((!((relocation >> 23) & 1)) ^ reloc_sign) << 13)
11265 | (((!((relocation >> 22) & 1)) ^ reloc_sign) << 11)
11266 | ((relocation >> 1) & 0x7ff);
c62e1cc3 11267
252b5132
RH		 11268 /* Put the relocated value back in the object file: */
11269 bfd_put_16 (input_bfd, upper_insn, hit_data);
11270 bfd_put_16 (input_bfd, lower_insn, hit_data + 2);
11271
11272 return (overflow ? bfd_reloc_overflow : bfd_reloc_ok);
11273 }
11274 break;
11275
c19d1205
ZW		 11276 case R_ARM_THM_JUMP19:
11277 /* Thumb32 conditional branch instruction. */
11278 {
11279 bfd_vma relocation;
11280 bfd_boolean overflow = FALSE;
11281 bfd_vma upper_insn = bfd_get_16 (input_bfd, hit_data);
11282 bfd_vma lower_insn = bfd_get_16 (input_bfd, hit_data + 2);
a00a1f35
MS		 11283 bfd_signed_vma reloc_signed_max = 0xffffe;
11284 bfd_signed_vma reloc_signed_min = -0x100000;
c19d1205 11285 bfd_signed_vma signed_check;
07d6d2b8 11286 enum elf32_arm_stub_type stub_type = arm_stub_none;
c5423981
TG		 11287 struct elf32_arm_stub_hash_entry *stub_entry;
11288 struct elf32_arm_link_hash_entry *hash;
c19d1205
ZW		 11289
11290 /* Need to refetch the addend, reconstruct the top three bits,
11291 and squish the two 11 bit pieces together. */
11292 if (globals->use_rel)
11293 {
11294 bfd_vma S = (upper_insn & 0x0400) >> 10;
a00a1f35 11295 bfd_vma upper = (upper_insn & 0x003f);
c19d1205
ZW		 11296 bfd_vma J1 = (lower_insn & 0x2000) >> 13;
11297 bfd_vma J2 = (lower_insn & 0x0800) >> 11;
11298 bfd_vma lower = (lower_insn & 0x07ff);
11299
a00a1f35
MS		 11300 upper |= J1 << 6;
11301 upper |= J2 << 7;
11302 upper |= (!S) << 8;
c19d1205
ZW		 11303 upper -= 0x0100; /* Sign extend. */
11304
11305 addend = (upper << 12) | (lower << 1);
11306 signed_addend = addend;
11307 }
11308
bd97cb95 11309 /* Handle calls via the PLT. */
34e77a92 11310 if (plt_offset != (bfd_vma) -1)
bd97cb95
DJ		 11311 {
11312 value = (splt->output_section->vma
11313 + splt->output_offset
34e77a92 11314 + plt_offset);
bd97cb95
DJ		 11315 /* Target the Thumb stub before the ARM PLT entry. */
11316 value -= PLT_THUMB_STUB_SIZE;
11317 *unresolved_reloc_p = FALSE;
11318 }
11319
c5423981
TG		 11320 hash = (struct elf32_arm_link_hash_entry *)h;
11321
11322 stub_type = arm_type_of_stub (info, input_section, rel,
07d6d2b8
AM		 11323 st_type, &branch_type,
11324 hash, value, sym_sec,
11325 input_bfd, sym_name);
c5423981
TG		 11326 if (stub_type != arm_stub_none)
11327 {
11328 stub_entry = elf32_arm_get_stub_entry (input_section,
07d6d2b8
AM		 11329 sym_sec, h,
11330 rel, globals,
11331 stub_type);
c5423981
TG		 11332 if (stub_entry != NULL)
11333 {
07d6d2b8
AM		 11334 value = (stub_entry->stub_offset
11335 + stub_entry->stub_sec->output_offset
11336 + stub_entry->stub_sec->output_section->vma);
c5423981
TG		 11337 }
11338 }
c19d1205 11339
99059e56 11340 relocation = value + signed_addend;
c19d1205
ZW		 11341 relocation -= (input_section->output_section->vma
11342 + input_section->output_offset
11343 + rel->r_offset);
a00a1f35 11344 signed_check = (bfd_signed_vma) relocation;
c19d1205 11345
c19d1205
ZW		 11346 if (signed_check > reloc_signed_max || signed_check < reloc_signed_min)
11347 overflow = TRUE;
11348
11349 /* Put RELOCATION back into the insn. */
11350 {
11351 bfd_vma S = (relocation & 0x00100000) >> 20;
11352 bfd_vma J2 = (relocation & 0x00080000) >> 19;
11353 bfd_vma J1 = (relocation & 0x00040000) >> 18;
11354 bfd_vma hi = (relocation & 0x0003f000) >> 12;
11355 bfd_vma lo = (relocation & 0x00000ffe) >> 1;
11356
a00a1f35 11357 upper_insn = (upper_insn & 0xfbc0) | (S << 10) | hi;
c19d1205
ZW		 11358 lower_insn = (lower_insn & 0xd000) | (J1 << 13) | (J2 << 11) | lo;
11359 }
11360
11361 /* Put the relocated value back in the object file: */
11362 bfd_put_16 (input_bfd, upper_insn, hit_data);
11363 bfd_put_16 (input_bfd, lower_insn, hit_data + 2);
11364
11365 return (overflow ? bfd_reloc_overflow : bfd_reloc_ok);
11366 }
11367
11368 case R_ARM_THM_JUMP11:
11369 case R_ARM_THM_JUMP8:
11370 case R_ARM_THM_JUMP6:
51c5503b
NC		 11371 /* Thumb B (branch) instruction). */
11372 {
6cf9e9fe 11373 bfd_signed_vma relocation;
51c5503b
NC		 11374 bfd_signed_vma reloc_signed_max = (1 << (howto->bitsize - 1)) - 1;
11375 bfd_signed_vma reloc_signed_min = ~ reloc_signed_max;
51c5503b
NC		 11376 bfd_signed_vma signed_check;
11377
c19d1205
ZW		 11378 /* CZB cannot jump backward. */
11379 if (r_type == R_ARM_THM_JUMP6)
11380 reloc_signed_min = 0;
11381
4e7fd91e 11382 if (globals->use_rel)
6cf9e9fe 11383 {
4e7fd91e
PB		 11384 /* Need to refetch addend. */
11385 addend = bfd_get_16 (input_bfd, hit_data) & howto->src_mask;
11386 if (addend & ((howto->src_mask + 1) >> 1))
11387 {
11388 signed_addend = -1;
11389 signed_addend &= ~ howto->src_mask;
11390 signed_addend |= addend;
11391 }
11392 else
11393 signed_addend = addend;
11394 /* The value in the insn has been right shifted. We need to
11395 undo this, so that we can perform the address calculation
11396 in terms of bytes. */
11397 signed_addend <<= howto->rightshift;
6cf9e9fe 11398 }
6cf9e9fe 11399 relocation = value + signed_addend;
51c5503b
NC		 11400
11401 relocation -= (input_section->output_section->vma
11402 + input_section->output_offset
11403 + rel->r_offset);
11404
6cf9e9fe
NC		 11405 relocation >>= howto->rightshift;
11406 signed_check = relocation;
c19d1205
ZW		 11407
11408 if (r_type == R_ARM_THM_JUMP6)
11409 relocation = ((relocation & 0x0020) << 4) | ((relocation & 0x001f) << 3);
11410 else
11411 relocation &= howto->dst_mask;
51c5503b 11412 relocation |= (bfd_get_16 (input_bfd, hit_data) & (~ howto->dst_mask));
cedb70c5 11413
51c5503b
NC		 11414 bfd_put_16 (input_bfd, relocation, hit_data);
11415
11416 /* Assumes two's complement. */
11417 if (signed_check > reloc_signed_max || signed_check < reloc_signed_min)
11418 return bfd_reloc_overflow;
11419
11420 return bfd_reloc_ok;
11421 }
cedb70c5 11422
8375c36b
PB		 11423 case R_ARM_ALU_PCREL7_0:
11424 case R_ARM_ALU_PCREL15_8:
11425 case R_ARM_ALU_PCREL23_15:
11426 {
11427 bfd_vma insn;
11428 bfd_vma relocation;
11429
11430 insn = bfd_get_32 (input_bfd, hit_data);
4e7fd91e
PB		 11431 if (globals->use_rel)
11432 {
11433 /* Extract the addend. */
11434 addend = (insn & 0xff) << ((insn & 0xf00) >> 7);
11435 signed_addend = addend;
11436 }
8375c36b
PB		 11437 relocation = value + signed_addend;
11438
11439 relocation -= (input_section->output_section->vma
11440 + input_section->output_offset
11441 + rel->r_offset);
11442 insn = (insn & ~0xfff)
11443 | ((howto->bitpos << 7) & 0xf00)
11444 | ((relocation >> howto->bitpos) & 0xff);
11445 bfd_put_32 (input_bfd, value, hit_data);
11446 }
11447 return bfd_reloc_ok;
11448
252b5132
RH		 11449 case R_ARM_GNU_VTINHERIT:
11450 case R_ARM_GNU_VTENTRY:
11451 return bfd_reloc_ok;
11452
c19d1205 11453 case R_ARM_GOTOFF32:
252b5132 11454 /* Relocation is relative to the start of the
99059e56 11455 global offset table. */
252b5132
RH		 11456
11457 BFD_ASSERT (sgot != NULL);
11458 if (sgot == NULL)
99059e56 11459 return bfd_reloc_notsupported;
9a5aca8c 11460
cedb70c5 11461 /* If we are addressing a Thumb function, we need to adjust the
ee29b9fb
RE		 11462 address by one, so that attempts to call the function pointer will
11463 correctly interpret it as Thumb code. */
35fc36a8 11464 if (branch_type == ST_BRANCH_TO_THUMB)
ee29b9fb
RE		 11465 value += 1;
11466
252b5132 11467 /* Note that sgot->output_offset is not involved in this
99059e56
RM		 11468 calculation. We always want the start of .got. If we
11469 define _GLOBAL_OFFSET_TABLE in a different way, as is
11470 permitted by the ABI, we might have to change this
11471 calculation. */
252b5132 11472 value -= sgot->output_section->vma;
f21f3fe0 11473 return _bfd_final_link_relocate (howto, input_bfd, input_section,
99e4ae17 11474 contents, rel->r_offset, value,
00a97672 11475 rel->r_addend);
252b5132
RH		 11476
11477 case R_ARM_GOTPC:
a7c10850 11478 /* Use global offset table as symbol value. */
252b5132 11479 BFD_ASSERT (sgot != NULL);
f21f3fe0 11480
252b5132 11481 if (sgot == NULL)
99059e56 11482 return bfd_reloc_notsupported;
252b5132 11483
0945cdfd 11484 *unresolved_reloc_p = FALSE;
252b5132 11485 value = sgot->output_section->vma;
f21f3fe0 11486 return _bfd_final_link_relocate (howto, input_bfd, input_section,
99e4ae17 11487 contents, rel->r_offset, value,
00a97672 11488 rel->r_addend);
f21f3fe0 11489
252b5132 11490 case R_ARM_GOT32:
eb043451 11491 case R_ARM_GOT_PREL:
252b5132 11492 /* Relocation is to the entry for this symbol in the
99059e56 11493 global offset table. */
252b5132
RH		 11494 if (sgot == NULL)
11495 return bfd_reloc_notsupported;
f21f3fe0 11496
34e77a92
RS		 11497 if (dynreloc_st_type == STT_GNU_IFUNC
11498 && plt_offset != (bfd_vma) -1
11499 && (h == NULL || SYMBOL_REFERENCES_LOCAL (info, h)))
11500 {
11501 /* We have a relocation against a locally-binding STT_GNU_IFUNC
11502 symbol, and the relocation resolves directly to the runtime
11503 target rather than to the .iplt entry. This means that any
11504 .got entry would be the same value as the .igot.plt entry,
11505 so there's no point creating both. */
11506 sgot = globals->root.igotplt;
11507 value = sgot->output_offset + gotplt_offset;
11508 }
11509 else if (h != NULL)
252b5132
RH		 11510 {
11511 bfd_vma off;
f21f3fe0 11512
252b5132
RH		 11513 off = h->got.offset;
11514 BFD_ASSERT (off != (bfd_vma) -1);
b436d854 11515 if ((off & 1) != 0)
252b5132 11516 {
b436d854
RS		 11517 /* We have already processsed one GOT relocation against
11518 this symbol. */
11519 off &= ~1;
11520 if (globals->root.dynamic_sections_created
11521 && !SYMBOL_REFERENCES_LOCAL (info, h))
11522 *unresolved_reloc_p = FALSE;
11523 }
11524 else
11525 {
11526 Elf_Internal_Rela outrel;
e8b09b87 11527 int isrofixup = 0;
b436d854 11528
e8b09b87
CL		 11529 if (((h->dynindx != -1) || globals->fdpic_p)
11530 && !SYMBOL_REFERENCES_LOCAL (info, h))
b436d854
RS		 11531 {
11532 /* If the symbol doesn't resolve locally in a static
11533 object, we have an undefined reference. If the
11534 symbol doesn't resolve locally in a dynamic object,
11535 it should be resolved by the dynamic linker. */
11536 if (globals->root.dynamic_sections_created)
11537 {
11538 outrel.r_info = ELF32_R_INFO (h->dynindx, R_ARM_GLOB_DAT);
11539 *unresolved_reloc_p = FALSE;
11540 }
11541 else
11542 outrel.r_info = 0;
11543 outrel.r_addend = 0;
11544 }
252b5132
RH		 11545 else
11546 {
34e77a92 11547 if (dynreloc_st_type == STT_GNU_IFUNC)
99059e56 11548 outrel.r_info = ELF32_R_INFO (0, R_ARM_IRELATIVE);
5025eb7c 11549 else if (bfd_link_pic (info)
7f026732 11550 && !UNDEFWEAK_NO_DYNAMIC_RELOC (info, h))
99059e56
RM		 11551 outrel.r_info = ELF32_R_INFO (0, R_ARM_RELATIVE);
11552 else
2376f038
EB		 11553 {
11554 outrel.r_info = 0;
11555 if (globals->fdpic_p)
11556 isrofixup = 1;
11557 }
34e77a92 11558 outrel.r_addend = dynreloc_value;
b436d854 11559 }
ee29b9fb 11560
b436d854
RS		 11561 /* The GOT entry is initialized to zero by default.
11562 See if we should install a different value. */
11563 if (outrel.r_addend != 0
2376f038 11564 && (globals->use_rel || outrel.r_info == 0))
b436d854
RS		 11565 {
11566 bfd_put_32 (output_bfd, outrel.r_addend,
11567 sgot->contents + off);
11568 outrel.r_addend = 0;
252b5132 11569 }
f21f3fe0 11570
2376f038
EB		 11571 if (isrofixup)
11572 arm_elf_add_rofixup (output_bfd,
11573 elf32_arm_hash_table(info)->srofixup,
11574 sgot->output_section->vma
11575 + sgot->output_offset + off);
11576
11577 else if (outrel.r_info != 0)
b436d854
RS		 11578 {
11579 outrel.r_offset = (sgot->output_section->vma
11580 + sgot->output_offset
11581 + off);
11582 elf32_arm_add_dynreloc (output_bfd, info, srelgot, &outrel);
11583 }
2376f038 11584
b436d854
RS		 11585 h->got.offset |= 1;
11586 }
252b5132
RH		 11587 value = sgot->output_offset + off;
11588 }
11589 else
11590 {
11591 bfd_vma off;
f21f3fe0 11592
5025eb7c
AO		 11593 BFD_ASSERT (local_got_offsets != NULL
11594 && local_got_offsets[r_symndx] != (bfd_vma) -1);
f21f3fe0 11595
252b5132 11596 off = local_got_offsets[r_symndx];
f21f3fe0 11597
252b5132
RH		 11598 /* The offset must always be a multiple of 4. We use the
11599 least significant bit to record whether we have already
9b485d32 11600 generated the necessary reloc. */
252b5132
RH		 11601 if ((off & 1) != 0)
11602 off &= ~1;
11603 else
11604 {
2376f038
EB		 11605 Elf_Internal_Rela outrel;
11606 int isrofixup = 0;
f21f3fe0 11607
2376f038
EB		 11608 if (dynreloc_st_type == STT_GNU_IFUNC)
11609 outrel.r_info = ELF32_R_INFO (0, R_ARM_IRELATIVE);
11610 else if (bfd_link_pic (info))
11611 outrel.r_info = ELF32_R_INFO (0, R_ARM_RELATIVE);
11612 else
252b5132 11613 {
2376f038
EB		 11614 outrel.r_info = 0;
11615 if (globals->fdpic_p)
11616 isrofixup = 1;
11617 }
11618
11619 /* The GOT entry is initialized to zero by default.
11620 See if we should install a different value. */
11621 if (globals->use_rel || outrel.r_info == 0)
11622 bfd_put_32 (output_bfd, dynreloc_value, sgot->contents + off);
11623
11624 if (isrofixup)
11625 arm_elf_add_rofixup (output_bfd,
11626 globals->srofixup,
11627 sgot->output_section->vma
11628 + sgot->output_offset + off);
f21f3fe0 11629
2376f038
EB		 11630 else if (outrel.r_info != 0)
11631 {
34e77a92 11632 outrel.r_addend = addend + dynreloc_value;
252b5132 11633 outrel.r_offset = (sgot->output_section->vma
f21f3fe0 11634 + sgot->output_offset
252b5132 11635 + off);
47beaa6a 11636 elf32_arm_add_dynreloc (output_bfd, info, srelgot, &outrel);
252b5132 11637 }
f21f3fe0 11638
252b5132
RH		 11639 local_got_offsets[r_symndx] |= 1;
11640 }
f21f3fe0 11641
252b5132
RH		 11642 value = sgot->output_offset + off;
11643 }
eb043451
PB		 11644 if (r_type != R_ARM_GOT32)
11645 value += sgot->output_section->vma;
9a5aca8c 11646
f21f3fe0 11647 return _bfd_final_link_relocate (howto, input_bfd, input_section,
99e4ae17 11648 contents, rel->r_offset, value,
00a97672 11649 rel->r_addend);
f21f3fe0 11650
ba93b8ac
DJ		 11651 case R_ARM_TLS_LDO32:
11652 value = value - dtpoff_base (info);
11653
11654 return _bfd_final_link_relocate (howto, input_bfd, input_section,
00a97672
RS		 11655 contents, rel->r_offset, value,
11656 rel->r_addend);
ba93b8ac
DJ		 11657
11658 case R_ARM_TLS_LDM32:
5c5a4843 11659 case R_ARM_TLS_LDM32_FDPIC:
ba93b8ac
DJ		 11660 {
11661 bfd_vma off;
11662
362d30a1 11663 if (sgot == NULL)
ba93b8ac
DJ		 11664 abort ();
11665
11666 off = globals->tls_ldm_got.offset;
11667
11668 if ((off & 1) != 0)
11669 off &= ~1;
11670 else
11671 {
11672 /* If we don't know the module number, create a relocation
11673 for it. */
9cb09e33 11674 if (bfd_link_dll (info))
ba93b8ac
DJ		 11675 {
11676 Elf_Internal_Rela outrel;
ba93b8ac 11677
362d30a1 11678 if (srelgot == NULL)
ba93b8ac
DJ		 11679 abort ();
11680
00a97672 11681 outrel.r_addend = 0;
362d30a1
RS		 11682 outrel.r_offset = (sgot->output_section->vma
11683 + sgot->output_offset + off);
ba93b8ac
DJ		 11684 outrel.r_info = ELF32_R_INFO (0, R_ARM_TLS_DTPMOD32);
11685
00a97672
RS		 11686 if (globals->use_rel)
11687 bfd_put_32 (output_bfd, outrel.r_addend,
362d30a1 11688 sgot->contents + off);
ba93b8ac 11689
47beaa6a 11690 elf32_arm_add_dynreloc (output_bfd, info, srelgot, &outrel);
ba93b8ac
DJ		 11691 }
11692 else
362d30a1 11693 bfd_put_32 (output_bfd, 1, sgot->contents + off);
ba93b8ac
DJ		 11694
11695 globals->tls_ldm_got.offset |= 1;
11696 }
11697
5c5a4843 11698 if (r_type == R_ARM_TLS_LDM32_FDPIC)
e8b09b87
CL		 11699 {
11700 bfd_put_32(output_bfd,
11701 globals->root.sgot->output_offset + off,
11702 contents + rel->r_offset);
11703
11704 return bfd_reloc_ok;
11705 }
11706 else
11707 {
11708 value = sgot->output_section->vma + sgot->output_offset + off
11709 - (input_section->output_section->vma
11710 + input_section->output_offset + rel->r_offset);
ba93b8ac 11711
e8b09b87
CL		 11712 return _bfd_final_link_relocate (howto, input_bfd, input_section,
11713 contents, rel->r_offset, value,
11714 rel->r_addend);
11715 }
ba93b8ac
DJ		 11716 }
11717
0855e32b
NS		 11718 case R_ARM_TLS_CALL:
11719 case R_ARM_THM_TLS_CALL:
ba93b8ac 11720 case R_ARM_TLS_GD32:
5c5a4843 11721 case R_ARM_TLS_GD32_FDPIC:
ba93b8ac 11722 case R_ARM_TLS_IE32:
5c5a4843 11723 case R_ARM_TLS_IE32_FDPIC:
0855e32b
NS		 11724 case R_ARM_TLS_GOTDESC:
11725 case R_ARM_TLS_DESCSEQ:
11726 case R_ARM_THM_TLS_DESCSEQ:
ba93b8ac 11727 {
0855e32b
NS		 11728 bfd_vma off, offplt;
11729 int indx = 0;
ba93b8ac
DJ		 11730 char tls_type;
11731
0855e32b 11732 BFD_ASSERT (sgot != NULL);
ba93b8ac 11733
ba93b8ac
DJ		 11734 if (h != NULL)
11735 {
11736 bfd_boolean dyn;
11737 dyn = globals->root.dynamic_sections_created;
0e1862bb
L		 11738 if (WILL_CALL_FINISH_DYNAMIC_SYMBOL (dyn,
11739 bfd_link_pic (info),
11740 h)
11741 && (!bfd_link_pic (info)
ba93b8ac
DJ		 11742 || !SYMBOL_REFERENCES_LOCAL (info, h)))
11743 {
11744 *unresolved_reloc_p = FALSE;
11745 indx = h->dynindx;
11746 }
11747 off = h->got.offset;
0855e32b 11748 offplt = elf32_arm_hash_entry (h)->tlsdesc_got;
ba93b8ac
DJ		 11749 tls_type = ((struct elf32_arm_link_hash_entry *) h)->tls_type;
11750 }
11751 else
11752 {
0855e32b 11753 BFD_ASSERT (local_got_offsets != NULL);
ba93b8ac 11754 off = local_got_offsets[r_symndx];
0855e32b 11755 offplt = local_tlsdesc_gotents[r_symndx];
ba93b8ac
DJ		 11756 tls_type = elf32_arm_local_got_tls_type (input_bfd)[r_symndx];
11757 }
11758
0855e32b 11759 /* Linker relaxations happens from one of the
b38cadfb 11760 R_ARM_{GOTDESC,CALL,DESCSEQ} relocations to IE or LE. */
0855e32b 11761 if (ELF32_R_TYPE(rel->r_info) != r_type)
b38cadfb 11762 tls_type = GOT_TLS_IE;
0855e32b
NS		 11763
11764 BFD_ASSERT (tls_type != GOT_UNKNOWN);
ba93b8ac
DJ		 11765
11766 if ((off & 1) != 0)
11767 off &= ~1;
11768 else
11769 {
11770 bfd_boolean need_relocs = FALSE;
11771 Elf_Internal_Rela outrel;
ba93b8ac
DJ		 11772 int cur_off = off;
11773
11774 /* The GOT entries have not been initialized yet. Do it
11775 now, and emit any relocations. If both an IE GOT and a
11776 GD GOT are necessary, we emit the GD first. */
11777
9cb09e33 11778 if ((bfd_link_dll (info) || indx != 0)
ba93b8ac 11779 && (h == NULL
95b03e4a
L		 11780 || (ELF_ST_VISIBILITY (h->other) == STV_DEFAULT
11781 && !resolved_to_zero)
ba93b8ac
DJ		 11782 || h->root.type != bfd_link_hash_undefweak))
11783 {
11784 need_relocs = TRUE;
0855e32b 11785 BFD_ASSERT (srelgot != NULL);
ba93b8ac
DJ		 11786 }
11787
0855e32b
NS		 11788 if (tls_type & GOT_TLS_GDESC)
11789 {
47beaa6a
RS		 11790 bfd_byte *loc;
11791
0855e32b
NS		 11792 /* We should have relaxed, unless this is an undefined
11793 weak symbol. */
11794 BFD_ASSERT ((h && (h->root.type == bfd_link_hash_undefweak))
9cb09e33 11795 || bfd_link_dll (info));
0855e32b 11796 BFD_ASSERT (globals->sgotplt_jump_table_size + offplt + 8
99059e56 11797 <= globals->root.sgotplt->size);
0855e32b
NS		 11798
11799 outrel.r_addend = 0;
11800 outrel.r_offset = (globals->root.sgotplt->output_section->vma
11801 + globals->root.sgotplt->output_offset
11802 + offplt
11803 + globals->sgotplt_jump_table_size);
b38cadfb 11804
0855e32b
NS		 11805 outrel.r_info = ELF32_R_INFO (indx, R_ARM_TLS_DESC);
11806 sreloc = globals->root.srelplt;
11807 loc = sreloc->contents;
11808 loc += globals->next_tls_desc_index++ * RELOC_SIZE (globals);
11809 BFD_ASSERT (loc + RELOC_SIZE (globals)
99059e56 11810 <= sreloc->contents + sreloc->size);
0855e32b
NS		 11811
11812 SWAP_RELOC_OUT (globals) (output_bfd, &outrel, loc);
11813
11814 /* For globals, the first word in the relocation gets
11815 the relocation index and the top bit set, or zero,
11816 if we're binding now. For locals, it gets the
11817 symbol's offset in the tls section. */
99059e56 11818 bfd_put_32 (output_bfd,
0855e32b
NS		 11819 !h ? value - elf_hash_table (info)->tls_sec->vma
11820 : info->flags & DF_BIND_NOW ? 0
11821 : 0x80000000 | ELF32_R_SYM (outrel.r_info),
b38cadfb
NC		 11822 globals->root.sgotplt->contents + offplt
11823 + globals->sgotplt_jump_table_size);
11824
0855e32b 11825 /* Second word in the relocation is always zero. */
99059e56 11826 bfd_put_32 (output_bfd, 0,
b38cadfb
NC		 11827 globals->root.sgotplt->contents + offplt
11828 + globals->sgotplt_jump_table_size + 4);
0855e32b 11829 }
ba93b8ac
DJ		 11830 if (tls_type & GOT_TLS_GD)
11831 {
11832 if (need_relocs)
11833 {
00a97672 11834 outrel.r_addend = 0;
362d30a1
RS		 11835 outrel.r_offset = (sgot->output_section->vma
11836 + sgot->output_offset
00a97672 11837 + cur_off);
ba93b8ac 11838 outrel.r_info = ELF32_R_INFO (indx, R_ARM_TLS_DTPMOD32);
ba93b8ac 11839
00a97672
RS		 11840 if (globals->use_rel)
11841 bfd_put_32 (output_bfd, outrel.r_addend,
362d30a1 11842 sgot->contents + cur_off);
00a97672 11843
47beaa6a 11844 elf32_arm_add_dynreloc (output_bfd, info, srelgot, &outrel);
ba93b8ac
DJ		 11845
11846 if (indx == 0)
11847 bfd_put_32 (output_bfd, value - dtpoff_base (info),
362d30a1 11848 sgot->contents + cur_off + 4);
ba93b8ac
DJ		 11849 else
11850 {
00a97672 11851 outrel.r_addend = 0;
ba93b8ac
DJ		 11852 outrel.r_info = ELF32_R_INFO (indx,
11853 R_ARM_TLS_DTPOFF32);
11854 outrel.r_offset += 4;
00a97672
RS		 11855
11856 if (globals->use_rel)
11857 bfd_put_32 (output_bfd, outrel.r_addend,
362d30a1 11858 sgot->contents + cur_off + 4);
00a97672 11859
47beaa6a
RS		 11860 elf32_arm_add_dynreloc (output_bfd, info,
11861 srelgot, &outrel);
ba93b8ac
DJ		 11862 }
11863 }
11864 else
11865 {
11866 /* If we are not emitting relocations for a
11867 general dynamic reference, then we must be in a
11868 static link or an executable link with the
11869 symbol binding locally. Mark it as belonging
11870 to module 1, the executable. */
11871 bfd_put_32 (output_bfd, 1,
362d30a1 11872 sgot->contents + cur_off);
ba93b8ac 11873 bfd_put_32 (output_bfd, value - dtpoff_base (info),
362d30a1 11874 sgot->contents + cur_off + 4);
ba93b8ac
DJ		 11875 }
11876
11877 cur_off += 8;
11878 }
11879
11880 if (tls_type & GOT_TLS_IE)
11881 {
11882 if (need_relocs)
11883 {
00a97672
RS		 11884 if (indx == 0)
11885 outrel.r_addend = value - dtpoff_base (info);
11886 else
11887 outrel.r_addend = 0;
362d30a1
RS		 11888 outrel.r_offset = (sgot->output_section->vma
11889 + sgot->output_offset
ba93b8ac
DJ		 11890 + cur_off);
11891 outrel.r_info = ELF32_R_INFO (indx, R_ARM_TLS_TPOFF32);
11892
00a97672
RS		 11893 if (globals->use_rel)
11894 bfd_put_32 (output_bfd, outrel.r_addend,
362d30a1 11895 sgot->contents + cur_off);
ba93b8ac 11896
47beaa6a 11897 elf32_arm_add_dynreloc (output_bfd, info, srelgot, &outrel);
ba93b8ac
DJ		 11898 }
11899 else
11900 bfd_put_32 (output_bfd, tpoff (info, value),
362d30a1 11901 sgot->contents + cur_off);
ba93b8ac
DJ		 11902 cur_off += 4;
11903 }
11904
11905 if (h != NULL)
11906 h->got.offset |= 1;
11907 else
11908 local_got_offsets[r_symndx] |= 1;
11909 }
11910
5c5a4843 11911 if ((tls_type & GOT_TLS_GD) && r_type != R_ARM_TLS_GD32 && r_type != R_ARM_TLS_GD32_FDPIC)
ba93b8ac 11912 off += 8;
0855e32b
NS		 11913 else if (tls_type & GOT_TLS_GDESC)
11914 off = offplt;
11915
11916 if (ELF32_R_TYPE(rel->r_info) == R_ARM_TLS_CALL
11917 || ELF32_R_TYPE(rel->r_info) == R_ARM_THM_TLS_CALL)
11918 {
11919 bfd_signed_vma offset;
12352d3f
PB		 11920 /* TLS stubs are arm mode. The original symbol is a
11921 data object, so branch_type is bogus. */
11922 branch_type = ST_BRANCH_TO_ARM;
0855e32b 11923 enum elf32_arm_stub_type stub_type
34e77a92
RS		 11924 = arm_type_of_stub (info, input_section, rel,
11925 st_type, &branch_type,
0855e32b
NS		 11926 (struct elf32_arm_link_hash_entry *)h,
11927 globals->tls_trampoline, globals->root.splt,
11928 input_bfd, sym_name);
11929
11930 if (stub_type != arm_stub_none)
11931 {
11932 struct elf32_arm_stub_hash_entry *stub_entry
11933 = elf32_arm_get_stub_entry
11934 (input_section, globals->root.splt, 0, rel,
11935 globals, stub_type);
11936 offset = (stub_entry->stub_offset
11937 + stub_entry->stub_sec->output_offset
11938 + stub_entry->stub_sec->output_section->vma);
11939 }
11940 else
11941 offset = (globals->root.splt->output_section->vma
11942 + globals->root.splt->output_offset
11943 + globals->tls_trampoline);
11944
11945 if (ELF32_R_TYPE(rel->r_info) == R_ARM_TLS_CALL)
11946 {
11947 unsigned long inst;
b38cadfb
NC		 11948
11949 offset -= (input_section->output_section->vma
11950 + input_section->output_offset
11951 + rel->r_offset + 8);
0855e32b
NS		 11952
11953 inst = offset >> 2;
11954 inst &= 0x00ffffff;
11955 value = inst | (globals->use_blx ? 0xfa000000 : 0xeb000000);
11956 }
11957 else
11958 {
11959 /* Thumb blx encodes the offset in a complicated
11960 fashion. */
11961 unsigned upper_insn, lower_insn;
11962 unsigned neg;
11963
b38cadfb
NC		 11964 offset -= (input_section->output_section->vma
11965 + input_section->output_offset
0855e32b 11966 + rel->r_offset + 4);
b38cadfb 11967
12352d3f
PB		 11968 if (stub_type != arm_stub_none
11969 && arm_stub_is_thumb (stub_type))
11970 {
11971 lower_insn = 0xd000;
11972 }
11973 else
11974 {
11975 lower_insn = 0xc000;
6a631e86 11976 /* Round up the offset to a word boundary. */
12352d3f
PB		 11977 offset = (offset + 2) & ~2;
11978 }
11979
0855e32b
NS		 11980 neg = offset < 0;
11981 upper_insn = (0xf000
11982 | ((offset >> 12) & 0x3ff)
11983 | (neg << 10));
12352d3f 11984 lower_insn |= (((!((offset >> 23) & 1)) ^ neg) << 13)
0855e32b 11985 | (((!((offset >> 22) & 1)) ^ neg) << 11)
12352d3f 11986 | ((offset >> 1) & 0x7ff);
0855e32b
NS		 11987 bfd_put_16 (input_bfd, upper_insn, hit_data);
11988 bfd_put_16 (input_bfd, lower_insn, hit_data + 2);
11989 return bfd_reloc_ok;
11990 }
11991 }
11992 /* These relocations needs special care, as besides the fact
11993 they point somewhere in .gotplt, the addend must be
11994 adjusted accordingly depending on the type of instruction
6a631e86 11995 we refer to. */
0855e32b
NS		 11996 else if ((r_type == R_ARM_TLS_GOTDESC) && (tls_type & GOT_TLS_GDESC))
11997 {
11998 unsigned long data, insn;
11999 unsigned thumb;
b38cadfb 12000
b627f562 12001 data = bfd_get_signed_32 (input_bfd, hit_data);
0855e32b 12002 thumb = data & 1;
b627f562 12003 data &= ~1ul;
b38cadfb 12004
0855e32b
NS		 12005 if (thumb)
12006 {
12007 insn = bfd_get_16 (input_bfd, contents + rel->r_offset - data);
12008 if ((insn & 0xf000) == 0xf000 || (insn & 0xf800) == 0xe800)
12009 insn = (insn << 16)
12010 | bfd_get_16 (input_bfd,
12011 contents + rel->r_offset - data + 2);
12012 if ((insn & 0xf800c000) == 0xf000c000)
12013 /* bl/blx */
12014 value = -6;
12015 else if ((insn & 0xffffff00) == 0x4400)
12016 /* add */
12017 value = -5;
12018 else
12019 {
4eca0228 12020 _bfd_error_handler
695344c0 12021 /* xgettext:c-format */
2dcf00ce 12022 (_("%pB(%pA+%#" PRIx64 "): "
90b6238f 12023 "unexpected %s instruction '%#lx' "
2dcf00ce
AM		 12024 "referenced by TLS_GOTDESC"),
12025 input_bfd, input_section, (uint64_t) rel->r_offset,
90b6238f 12026 "Thumb", insn);
0855e32b
NS		 12027 return bfd_reloc_notsupported;
12028 }
12029 }
12030 else
12031 {
12032 insn = bfd_get_32 (input_bfd, contents + rel->r_offset - data);
12033
12034 switch (insn >> 24)
12035 {
12036 case 0xeb: /* bl */
12037 case 0xfa: /* blx */
12038 value = -4;
12039 break;
12040
12041 case 0xe0: /* add */
12042 value = -8;
12043 break;
b38cadfb 12044
0855e32b 12045 default:
4eca0228 12046 _bfd_error_handler
695344c0 12047 /* xgettext:c-format */
2dcf00ce 12048 (_("%pB(%pA+%#" PRIx64 "): "
90b6238f 12049 "unexpected %s instruction '%#lx' "
2dcf00ce
AM		 12050 "referenced by TLS_GOTDESC"),
12051 input_bfd, input_section, (uint64_t) rel->r_offset,
90b6238f 12052 "ARM", insn);
0855e32b
NS		 12053 return bfd_reloc_notsupported;
12054 }
12055 }
b38cadfb 12056
0855e32b
NS		 12057 value += ((globals->root.sgotplt->output_section->vma
12058 + globals->root.sgotplt->output_offset + off)
12059 - (input_section->output_section->vma
12060 + input_section->output_offset
12061 + rel->r_offset)
12062 + globals->sgotplt_jump_table_size);
12063 }
12064 else
12065 value = ((globals->root.sgot->output_section->vma
12066 + globals->root.sgot->output_offset + off)
12067 - (input_section->output_section->vma
12068 + input_section->output_offset + rel->r_offset));
ba93b8ac 12069
5c5a4843
CL		 12070 if (globals->fdpic_p && (r_type == R_ARM_TLS_GD32_FDPIC ||
12071 r_type == R_ARM_TLS_IE32_FDPIC))
e8b09b87
CL		 12072 {
12073 /* For FDPIC relocations, resolve to the offset of the GOT
12074 entry from the start of GOT. */
12075 bfd_put_32(output_bfd,
12076 globals->root.sgot->output_offset + off,
12077 contents + rel->r_offset);
12078
12079 return bfd_reloc_ok;
12080 }
12081 else
12082 {
12083 return _bfd_final_link_relocate (howto, input_bfd, input_section,
12084 contents, rel->r_offset, value,
12085 rel->r_addend);
12086 }
ba93b8ac
DJ		 12087 }
12088
12089 case R_ARM_TLS_LE32:
3cbc1e5e 12090 if (bfd_link_dll (info))
ba93b8ac 12091 {
4eca0228 12092 _bfd_error_handler
695344c0 12093 /* xgettext:c-format */
2dcf00ce
AM		 12094 (_("%pB(%pA+%#" PRIx64 "): %s relocation not permitted "
12095 "in shared object"),
12096 input_bfd, input_section, (uint64_t) rel->r_offset, howto->name);
46691134 12097 return bfd_reloc_notsupported;
ba93b8ac
DJ		 12098 }
12099 else
12100 value = tpoff (info, value);
906e58ca 12101
ba93b8ac 12102 return _bfd_final_link_relocate (howto, input_bfd, input_section,
00a97672
RS		 12103 contents, rel->r_offset, value,
12104 rel->r_addend);
ba93b8ac 12105
319850b4
JB		 12106 case R_ARM_V4BX:
12107 if (globals->fix_v4bx)
845b51d6
PB		 12108 {
12109 bfd_vma insn = bfd_get_32 (input_bfd, hit_data);
319850b4 12110
845b51d6
PB		 12111 /* Ensure that we have a BX instruction. */
12112 BFD_ASSERT ((insn & 0x0ffffff0) == 0x012fff10);
319850b4 12113
845b51d6
PB		 12114 if (globals->fix_v4bx == 2 && (insn & 0xf) != 0xf)
12115 {
12116 /* Branch to veneer. */
12117 bfd_vma glue_addr;
12118 glue_addr = elf32_arm_bx_glue (info, insn & 0xf);
12119 glue_addr -= input_section->output_section->vma
12120 + input_section->output_offset
12121 + rel->r_offset + 8;
12122 insn = (insn & 0xf0000000) | 0x0a000000
12123 | ((glue_addr >> 2) & 0x00ffffff);
12124 }
12125 else
12126 {
12127 /* Preserve Rm (lowest four bits) and the condition code
12128 (highest four bits). Other bits encode MOV PC,Rm. */
12129 insn = (insn & 0xf000000f) | 0x01a0f000;
12130 }
319850b4 12131
845b51d6
PB		 12132 bfd_put_32 (input_bfd, insn, hit_data);
12133 }
319850b4
JB		 12134 return bfd_reloc_ok;
12135
b6895b4f
PB		 12136 case R_ARM_MOVW_ABS_NC:
12137 case R_ARM_MOVT_ABS:
12138 case R_ARM_MOVW_PREL_NC:
12139 case R_ARM_MOVT_PREL:
92f5d02b
MS		 12140 /* Until we properly support segment-base-relative addressing then
12141 we assume the segment base to be zero, as for the group relocations.
12142 Thus R_ARM_MOVW_BREL_NC has the same semantics as R_ARM_MOVW_ABS_NC
12143 and R_ARM_MOVT_BREL has the same semantics as R_ARM_MOVT_ABS. */
12144 case R_ARM_MOVW_BREL_NC:
12145 case R_ARM_MOVW_BREL:
12146 case R_ARM_MOVT_BREL:
b6895b4f
PB		 12147 {
12148 bfd_vma insn = bfd_get_32 (input_bfd, hit_data);
12149
12150 if (globals->use_rel)
12151 {
12152 addend = ((insn >> 4) & 0xf000) | (insn & 0xfff);
39623e12 12153 signed_addend = (addend ^ 0x8000) - 0x8000;
b6895b4f 12154 }
92f5d02b 12155
b6895b4f 12156 value += signed_addend;
b6895b4f
PB		 12157
12158 if (r_type == R_ARM_MOVW_PREL_NC || r_type == R_ARM_MOVT_PREL)
12159 value -= (input_section->output_section->vma
12160 + input_section->output_offset + rel->r_offset);
12161
92f5d02b 12162 if (r_type == R_ARM_MOVW_BREL && value >= 0x10000)
99059e56 12163 return bfd_reloc_overflow;
92f5d02b 12164
35fc36a8 12165 if (branch_type == ST_BRANCH_TO_THUMB)
92f5d02b
MS		 12166 value |= 1;
12167
12168 if (r_type == R_ARM_MOVT_ABS || r_type == R_ARM_MOVT_PREL
99059e56 12169 || r_type == R_ARM_MOVT_BREL)
b6895b4f
PB		 12170 value >>= 16;
12171
12172 insn &= 0xfff0f000;
12173 insn |= value & 0xfff;
12174 insn |= (value & 0xf000) << 4;
12175 bfd_put_32 (input_bfd, insn, hit_data);
12176 }
12177 return bfd_reloc_ok;
12178
12179 case R_ARM_THM_MOVW_ABS_NC:
12180 case R_ARM_THM_MOVT_ABS:
12181 case R_ARM_THM_MOVW_PREL_NC:
12182 case R_ARM_THM_MOVT_PREL:
92f5d02b
MS		 12183 /* Until we properly support segment-base-relative addressing then
12184 we assume the segment base to be zero, as for the above relocations.
12185 Thus R_ARM_THM_MOVW_BREL_NC has the same semantics as
12186 R_ARM_THM_MOVW_ABS_NC and R_ARM_THM_MOVT_BREL has the same semantics
12187 as R_ARM_THM_MOVT_ABS. */
12188 case R_ARM_THM_MOVW_BREL_NC:
12189 case R_ARM_THM_MOVW_BREL:
12190 case R_ARM_THM_MOVT_BREL:
b6895b4f
PB		 12191 {
12192 bfd_vma insn;
906e58ca 12193
b6895b4f
PB		 12194 insn = bfd_get_16 (input_bfd, hit_data) << 16;
12195 insn |= bfd_get_16 (input_bfd, hit_data + 2);
12196
12197 if (globals->use_rel)
12198 {
12199 addend = ((insn >> 4) & 0xf000)
12200 | ((insn >> 15) & 0x0800)
12201 | ((insn >> 4) & 0x0700)
07d6d2b8 12202 | (insn & 0x00ff);
39623e12 12203 signed_addend = (addend ^ 0x8000) - 0x8000;
b6895b4f 12204 }
92f5d02b 12205
b6895b4f 12206 value += signed_addend;
b6895b4f
PB		 12207
12208 if (r_type == R_ARM_THM_MOVW_PREL_NC || r_type == R_ARM_THM_MOVT_PREL)
12209 value -= (input_section->output_section->vma
12210 + input_section->output_offset + rel->r_offset);
12211
92f5d02b 12212 if (r_type == R_ARM_THM_MOVW_BREL && value >= 0x10000)
99059e56 12213 return bfd_reloc_overflow;
92f5d02b 12214
35fc36a8 12215 if (branch_type == ST_BRANCH_TO_THUMB)
92f5d02b
MS		 12216 value |= 1;
12217
12218 if (r_type == R_ARM_THM_MOVT_ABS || r_type == R_ARM_THM_MOVT_PREL
99059e56 12219 || r_type == R_ARM_THM_MOVT_BREL)
b6895b4f
PB		 12220 value >>= 16;
12221
12222 insn &= 0xfbf08f00;
12223 insn |= (value & 0xf000) << 4;
12224 insn |= (value & 0x0800) << 15;
12225 insn |= (value & 0x0700) << 4;
12226 insn |= (value & 0x00ff);
12227
12228 bfd_put_16 (input_bfd, insn >> 16, hit_data);
12229 bfd_put_16 (input_bfd, insn & 0xffff, hit_data + 2);
12230 }
12231 return bfd_reloc_ok;
12232
4962c51a
MS		 12233 case R_ARM_ALU_PC_G0_NC:
12234 case R_ARM_ALU_PC_G1_NC:
12235 case R_ARM_ALU_PC_G0:
12236 case R_ARM_ALU_PC_G1:
12237 case R_ARM_ALU_PC_G2:
12238 case R_ARM_ALU_SB_G0_NC:
12239 case R_ARM_ALU_SB_G1_NC:
12240 case R_ARM_ALU_SB_G0:
12241 case R_ARM_ALU_SB_G1:
12242 case R_ARM_ALU_SB_G2:
12243 {
12244 bfd_vma insn = bfd_get_32 (input_bfd, hit_data);
99059e56 12245 bfd_vma pc = input_section->output_section->vma
4962c51a 12246 + input_section->output_offset + rel->r_offset;
31a91d61 12247 /* sb is the origin of the *segment* containing the symbol. */
62c34db3 12248 bfd_vma sb = sym_sec ? sym_sec->output_section->vma : 0;
99059e56
RM		 12249 bfd_vma residual;
12250 bfd_vma g_n;
4962c51a 12251 bfd_signed_vma signed_value;
99059e56
RM		 12252 int group = 0;
12253
12254 /* Determine which group of bits to select. */
12255 switch (r_type)
12256 {
12257 case R_ARM_ALU_PC_G0_NC:
12258 case R_ARM_ALU_PC_G0:
12259 case R_ARM_ALU_SB_G0_NC:
12260 case R_ARM_ALU_SB_G0:
12261 group = 0;
12262 break;
12263
12264 case R_ARM_ALU_PC_G1_NC:
12265 case R_ARM_ALU_PC_G1:
12266 case R_ARM_ALU_SB_G1_NC:
12267 case R_ARM_ALU_SB_G1:
12268 group = 1;
12269 break;
12270
12271 case R_ARM_ALU_PC_G2:
12272 case R_ARM_ALU_SB_G2:
12273 group = 2;
12274 break;
12275
12276 default:
12277 abort ();
12278 }
12279
12280 /* If REL, extract the addend from the insn. If RELA, it will
12281 have already been fetched for us. */
4962c51a 12282 if (globals->use_rel)
99059e56
RM		 12283 {
12284 int negative;
12285 bfd_vma constant = insn & 0xff;
12286 bfd_vma rotation = (insn & 0xf00) >> 8;
12287
12288 if (rotation == 0)
12289 signed_addend = constant;
12290 else
12291 {
12292 /* Compensate for the fact that in the instruction, the
12293 rotation is stored in multiples of 2 bits. */
12294 rotation *= 2;
12295
12296 /* Rotate "constant" right by "rotation" bits. */
12297 signed_addend = (constant >> rotation) |
12298 (constant << (8 * sizeof (bfd_vma) - rotation));
12299 }
12300
12301 /* Determine if the instruction is an ADD or a SUB.
12302 (For REL, this determines the sign of the addend.) */
12303 negative = identify_add_or_sub (insn);
12304 if (negative == 0)
12305 {
4eca0228 12306 _bfd_error_handler
695344c0 12307 /* xgettext:c-format */
90b6238f 12308 (_("%pB(%pA+%#" PRIx64 "): only ADD or SUB instructions "
2dcf00ce
AM		 12309 "are allowed for ALU group relocations"),
12310 input_bfd, input_section, (uint64_t) rel->r_offset);
99059e56
RM		 12311 return bfd_reloc_overflow;
12312 }
12313
12314 signed_addend *= negative;
12315 }
4962c51a
MS		 12316
12317 /* Compute the value (X) to go in the place. */
99059e56
RM		 12318 if (r_type == R_ARM_ALU_PC_G0_NC
12319 || r_type == R_ARM_ALU_PC_G1_NC
12320 || r_type == R_ARM_ALU_PC_G0
12321 || r_type == R_ARM_ALU_PC_G1
12322 || r_type == R_ARM_ALU_PC_G2)
12323 /* PC relative. */
12324 signed_value = value - pc + signed_addend;
12325 else
12326 /* Section base relative. */
12327 signed_value = value - sb + signed_addend;
12328
12329 /* If the target symbol is a Thumb function, then set the
12330 Thumb bit in the address. */
35fc36a8 12331 if (branch_type == ST_BRANCH_TO_THUMB)
4962c51a
MS		 12332 signed_value |= 1;
12333
99059e56
RM		 12334 /* Calculate the value of the relevant G_n, in encoded
12335 constant-with-rotation format. */
b6518b38
NC		 12336 g_n = calculate_group_reloc_mask (signed_value < 0 ? - signed_value : signed_value,
12337 group, &residual);
99059e56
RM		 12338
12339 /* Check for overflow if required. */
12340 if ((r_type == R_ARM_ALU_PC_G0
12341 || r_type == R_ARM_ALU_PC_G1
12342 || r_type == R_ARM_ALU_PC_G2
12343 || r_type == R_ARM_ALU_SB_G0
12344 || r_type == R_ARM_ALU_SB_G1
12345 || r_type == R_ARM_ALU_SB_G2) && residual != 0)
12346 {
4eca0228 12347 _bfd_error_handler
695344c0 12348 /* xgettext:c-format */
90b6238f 12349 (_("%pB(%pA+%#" PRIx64 "): overflow whilst "
2dcf00ce
AM		 12350 "splitting %#" PRIx64 " for group relocation %s"),
12351 input_bfd, input_section, (uint64_t) rel->r_offset,
12352 (uint64_t) (signed_value < 0 ? -signed_value : signed_value),
12353 howto->name);
99059e56
RM		 12354 return bfd_reloc_overflow;
12355 }
12356
12357 /* Mask out the value and the ADD/SUB part of the opcode; take care
12358 not to destroy the S bit. */
12359 insn &= 0xff1ff000;
12360
12361 /* Set the opcode according to whether the value to go in the
12362 place is negative. */
12363 if (signed_value < 0)
12364 insn |= 1 << 22;
12365 else
12366 insn |= 1 << 23;
12367
12368 /* Encode the offset. */
12369 insn |= g_n;
4962c51a
MS		 12370
12371 bfd_put_32 (input_bfd, insn, hit_data);
12372 }
12373 return bfd_reloc_ok;
12374
12375 case R_ARM_LDR_PC_G0:
12376 case R_ARM_LDR_PC_G1:
12377 case R_ARM_LDR_PC_G2:
12378 case R_ARM_LDR_SB_G0:
12379 case R_ARM_LDR_SB_G1:
12380 case R_ARM_LDR_SB_G2:
12381 {
12382 bfd_vma insn = bfd_get_32 (input_bfd, hit_data);
99059e56 12383 bfd_vma pc = input_section->output_section->vma
4962c51a 12384 + input_section->output_offset + rel->r_offset;
31a91d61 12385 /* sb is the origin of the *segment* containing the symbol. */
62c34db3 12386 bfd_vma sb = sym_sec ? sym_sec->output_section->vma : 0;
99059e56 12387 bfd_vma residual;
4962c51a 12388 bfd_signed_vma signed_value;
99059e56
RM		 12389 int group = 0;
12390
12391 /* Determine which groups of bits to calculate. */
12392 switch (r_type)
12393 {
12394 case R_ARM_LDR_PC_G0:
12395 case R_ARM_LDR_SB_G0:
12396 group = 0;
12397 break;
12398
12399 case R_ARM_LDR_PC_G1:
12400 case R_ARM_LDR_SB_G1:
12401 group = 1;
12402 break;
12403
12404 case R_ARM_LDR_PC_G2:
12405 case R_ARM_LDR_SB_G2:
12406 group = 2;
12407 break;
12408
12409 default:
12410 abort ();
12411 }
12412
12413 /* If REL, extract the addend from the insn. If RELA, it will
12414 have already been fetched for us. */
4962c51a 12415 if (globals->use_rel)
99059e56
RM		 12416 {
12417 int negative = (insn & (1 << 23)) ? 1 : -1;
12418 signed_addend = negative * (insn & 0xfff);
12419 }
4962c51a
MS		 12420
12421 /* Compute the value (X) to go in the place. */
99059e56
RM		 12422 if (r_type == R_ARM_LDR_PC_G0
12423 || r_type == R_ARM_LDR_PC_G1
12424 || r_type == R_ARM_LDR_PC_G2)
12425 /* PC relative. */
12426 signed_value = value - pc + signed_addend;
12427 else
12428 /* Section base relative. */
12429 signed_value = value - sb + signed_addend;
12430
12431 /* Calculate the value of the relevant G_{n-1} to obtain
12432 the residual at that stage. */
b6518b38
NC		 12433 calculate_group_reloc_mask (signed_value < 0 ? - signed_value : signed_value,
12434 group - 1, &residual);
99059e56
RM		 12435
12436 /* Check for overflow. */
12437 if (residual >= 0x1000)
12438 {
4eca0228 12439 _bfd_error_handler
695344c0 12440 /* xgettext:c-format */
90b6238f 12441 (_("%pB(%pA+%#" PRIx64 "): overflow whilst "
2dcf00ce
AM		 12442 "splitting %#" PRIx64 " for group relocation %s"),
12443 input_bfd, input_section, (uint64_t) rel->r_offset,
12444 (uint64_t) (signed_value < 0 ? -signed_value : signed_value),
12445 howto->name);
99059e56
RM		 12446 return bfd_reloc_overflow;
12447 }
12448
12449 /* Mask out the value and U bit. */
12450 insn &= 0xff7ff000;
12451
12452 /* Set the U bit if the value to go in the place is non-negative. */
12453 if (signed_value >= 0)
12454 insn |= 1 << 23;
12455
12456 /* Encode the offset. */
12457 insn |= residual;
4962c51a
MS		 12458
12459 bfd_put_32 (input_bfd, insn, hit_data);
12460 }
12461 return bfd_reloc_ok;
12462
12463 case R_ARM_LDRS_PC_G0:
12464 case R_ARM_LDRS_PC_G1:
12465 case R_ARM_LDRS_PC_G2:
12466 case R_ARM_LDRS_SB_G0:
12467 case R_ARM_LDRS_SB_G1:
12468 case R_ARM_LDRS_SB_G2:
12469 {
12470 bfd_vma insn = bfd_get_32 (input_bfd, hit_data);
99059e56 12471 bfd_vma pc = input_section->output_section->vma
4962c51a 12472 + input_section->output_offset + rel->r_offset;
31a91d61 12473 /* sb is the origin of the *segment* containing the symbol. */
62c34db3 12474 bfd_vma sb = sym_sec ? sym_sec->output_section->vma : 0;
99059e56 12475 bfd_vma residual;
4962c51a 12476 bfd_signed_vma signed_value;
99059e56
RM		 12477 int group = 0;
12478
12479 /* Determine which groups of bits to calculate. */
12480 switch (r_type)
12481 {
12482 case R_ARM_LDRS_PC_G0:
12483 case R_ARM_LDRS_SB_G0:
12484 group = 0;
12485 break;
12486
12487 case R_ARM_LDRS_PC_G1:
12488 case R_ARM_LDRS_SB_G1:
12489 group = 1;
12490 break;
12491
12492 case R_ARM_LDRS_PC_G2:
12493 case R_ARM_LDRS_SB_G2:
12494 group = 2;
12495 break;
12496
12497 default:
12498 abort ();
12499 }
12500
12501 /* If REL, extract the addend from the insn. If RELA, it will
12502 have already been fetched for us. */
4962c51a 12503 if (globals->use_rel)
99059e56
RM		 12504 {
12505 int negative = (insn & (1 << 23)) ? 1 : -1;
12506 signed_addend = negative * (((insn & 0xf00) >> 4) + (insn & 0xf));
12507 }
4962c51a
MS		 12508
12509 /* Compute the value (X) to go in the place. */
99059e56
RM		 12510 if (r_type == R_ARM_LDRS_PC_G0
12511 || r_type == R_ARM_LDRS_PC_G1
12512 || r_type == R_ARM_LDRS_PC_G2)
12513 /* PC relative. */
12514 signed_value = value - pc + signed_addend;
12515 else
12516 /* Section base relative. */
12517 signed_value = value - sb + signed_addend;
12518
12519 /* Calculate the value of the relevant G_{n-1} to obtain
12520 the residual at that stage. */
b6518b38
NC		 12521 calculate_group_reloc_mask (signed_value < 0 ? - signed_value : signed_value,
12522 group - 1, &residual);
99059e56
RM		 12523
12524 /* Check for overflow. */
12525 if (residual >= 0x100)
12526 {
4eca0228 12527 _bfd_error_handler
695344c0 12528 /* xgettext:c-format */
90b6238f 12529 (_("%pB(%pA+%#" PRIx64 "): overflow whilst "
2dcf00ce
AM		 12530 "splitting %#" PRIx64 " for group relocation %s"),
12531 input_bfd, input_section, (uint64_t) rel->r_offset,
12532 (uint64_t) (signed_value < 0 ? -signed_value : signed_value),
12533 howto->name);
99059e56
RM		 12534 return bfd_reloc_overflow;
12535 }
12536
12537 /* Mask out the value and U bit. */
12538 insn &= 0xff7ff0f0;
12539
12540 /* Set the U bit if the value to go in the place is non-negative. */
12541 if (signed_value >= 0)
12542 insn |= 1 << 23;
12543
12544 /* Encode the offset. */
12545 insn |= ((residual & 0xf0) << 4) | (residual & 0xf);
4962c51a
MS		 12546
12547 bfd_put_32 (input_bfd, insn, hit_data);
12548 }
12549 return bfd_reloc_ok;
12550
12551 case R_ARM_LDC_PC_G0:
12552 case R_ARM_LDC_PC_G1:
12553 case R_ARM_LDC_PC_G2:
12554 case R_ARM_LDC_SB_G0:
12555 case R_ARM_LDC_SB_G1:
12556 case R_ARM_LDC_SB_G2:
12557 {
12558 bfd_vma insn = bfd_get_32 (input_bfd, hit_data);
99059e56 12559 bfd_vma pc = input_section->output_section->vma
4962c51a 12560 + input_section->output_offset + rel->r_offset;
31a91d61 12561 /* sb is the origin of the *segment* containing the symbol. */
62c34db3 12562 bfd_vma sb = sym_sec ? sym_sec->output_section->vma : 0;
99059e56 12563 bfd_vma residual;
4962c51a 12564 bfd_signed_vma signed_value;
99059e56
RM		 12565 int group = 0;
12566
12567 /* Determine which groups of bits to calculate. */
12568 switch (r_type)
12569 {
12570 case R_ARM_LDC_PC_G0:
12571 case R_ARM_LDC_SB_G0:
12572 group = 0;
12573 break;
12574
12575 case R_ARM_LDC_PC_G1:
12576 case R_ARM_LDC_SB_G1:
12577 group = 1;
12578 break;
12579
12580 case R_ARM_LDC_PC_G2:
12581 case R_ARM_LDC_SB_G2:
12582 group = 2;
12583 break;
12584
12585 default:
12586 abort ();
12587 }
12588
12589 /* If REL, extract the addend from the insn. If RELA, it will
12590 have already been fetched for us. */
4962c51a 12591 if (globals->use_rel)
99059e56
RM		 12592 {
12593 int negative = (insn & (1 << 23)) ? 1 : -1;
12594 signed_addend = negative * ((insn & 0xff) << 2);
12595 }
4962c51a
MS		 12596
12597 /* Compute the value (X) to go in the place. */
99059e56
RM		 12598 if (r_type == R_ARM_LDC_PC_G0
12599 || r_type == R_ARM_LDC_PC_G1
12600 || r_type == R_ARM_LDC_PC_G2)
12601 /* PC relative. */
12602 signed_value = value - pc + signed_addend;
12603 else
12604 /* Section base relative. */
12605 signed_value = value - sb + signed_addend;
12606
12607 /* Calculate the value of the relevant G_{n-1} to obtain
12608 the residual at that stage. */
b6518b38
NC		 12609 calculate_group_reloc_mask (signed_value < 0 ? - signed_value : signed_value,
12610 group - 1, &residual);
99059e56
RM		 12611
12612 /* Check for overflow. (The absolute value to go in the place must be
12613 divisible by four and, after having been divided by four, must
12614 fit in eight bits.) */
12615 if ((residual & 0x3) != 0 || residual >= 0x400)
12616 {
4eca0228 12617 _bfd_error_handler
695344c0 12618 /* xgettext:c-format */
90b6238f 12619 (_("%pB(%pA+%#" PRIx64 "): overflow whilst "
2dcf00ce
AM		 12620 "splitting %#" PRIx64 " for group relocation %s"),
12621 input_bfd, input_section, (uint64_t) rel->r_offset,
12622 (uint64_t) (signed_value < 0 ? -signed_value : signed_value),
12623 howto->name);
99059e56
RM		 12624 return bfd_reloc_overflow;
12625 }
12626
12627 /* Mask out the value and U bit. */
12628 insn &= 0xff7fff00;
12629
12630 /* Set the U bit if the value to go in the place is non-negative. */
12631 if (signed_value >= 0)
12632 insn |= 1 << 23;
12633
12634 /* Encode the offset. */
12635 insn |= residual >> 2;
4962c51a
MS		 12636
12637 bfd_put_32 (input_bfd, insn, hit_data);
12638 }
12639 return bfd_reloc_ok;
12640
72d98d16
MG		 12641 case R_ARM_THM_ALU_ABS_G0_NC:
12642 case R_ARM_THM_ALU_ABS_G1_NC:
12643 case R_ARM_THM_ALU_ABS_G2_NC:
12644 case R_ARM_THM_ALU_ABS_G3_NC:
12645 {
12646 const int shift_array[4] = {0, 8, 16, 24};
12647 bfd_vma insn = bfd_get_16 (input_bfd, hit_data);
12648 bfd_vma addr = value;
12649 int shift = shift_array[r_type - R_ARM_THM_ALU_ABS_G0_NC];
12650
12651 /* Compute address. */
12652 if (globals->use_rel)
12653 signed_addend = insn & 0xff;
12654 addr += signed_addend;
12655 if (branch_type == ST_BRANCH_TO_THUMB)
12656 addr |= 1;
12657 /* Clean imm8 insn. */
12658 insn &= 0xff00;
12659 /* And update with correct part of address. */
12660 insn |= (addr >> shift) & 0xff;
12661 /* Update insn. */
12662 bfd_put_16 (input_bfd, insn, hit_data);
12663 }
12664
12665 *unresolved_reloc_p = FALSE;
12666 return bfd_reloc_ok;
12667
e8b09b87
CL		 12668 case R_ARM_GOTOFFFUNCDESC:
12669 {
4b24dd1a 12670 if (h == NULL)
e8b09b87
CL		 12671 {
12672 struct fdpic_local *local_fdpic_cnts = elf32_arm_local_fdpic_cnts(input_bfd);
12673 int dynindx = elf_section_data (sym_sec->output_section)->dynindx;
12674 int offset = local_fdpic_cnts[r_symndx].funcdesc_offset & ~1;
12675 bfd_vma addr = dynreloc_value - sym_sec->output_section->vma;
12676 bfd_vma seg = -1;
12677
12678 if (bfd_link_pic(info) && dynindx == 0)
12679 abort();
12680
12681 /* Resolve relocation. */
12682 bfd_put_32(output_bfd, (offset + sgot->output_offset)
12683 , contents + rel->r_offset);
12684 /* Emit R_ARM_FUNCDESC_VALUE or two fixups on funcdesc if
12685 not done yet. */
12686 arm_elf_fill_funcdesc(output_bfd, info,
12687 &local_fdpic_cnts[r_symndx].funcdesc_offset,
12688 dynindx, offset, addr, dynreloc_value, seg);
12689 }
12690 else
12691 {
12692 int dynindx;
12693 int offset = eh->fdpic_cnts.funcdesc_offset & ~1;
12694 bfd_vma addr;
12695 bfd_vma seg = -1;
12696
12697 /* For static binaries, sym_sec can be null. */
12698 if (sym_sec)
12699 {
12700 dynindx = elf_section_data (sym_sec->output_section)->dynindx;
12701 addr = dynreloc_value - sym_sec->output_section->vma;
12702 }
12703 else
12704 {
12705 dynindx = 0;
12706 addr = 0;
12707 }
12708
12709 if (bfd_link_pic(info) && dynindx == 0)
12710 abort();
12711
12712 /* This case cannot occur since funcdesc is allocated by
12713 the dynamic loader so we cannot resolve the relocation. */
12714 if (h->dynindx != -1)
12715 abort();
12716
12717 /* Resolve relocation. */
12718 bfd_put_32(output_bfd, (offset + sgot->output_offset),
12719 contents + rel->r_offset);
12720 /* Emit R_ARM_FUNCDESC_VALUE on funcdesc if not done yet. */
12721 arm_elf_fill_funcdesc(output_bfd, info,
12722 &eh->fdpic_cnts.funcdesc_offset,
12723 dynindx, offset, addr, dynreloc_value, seg);
12724 }
12725 }
12726 *unresolved_reloc_p = FALSE;
12727 return bfd_reloc_ok;
12728
12729 case R_ARM_GOTFUNCDESC:
12730 {
4b24dd1a 12731 if (h != NULL)
e8b09b87
CL		 12732 {
12733 Elf_Internal_Rela outrel;
12734
12735 /* Resolve relocation. */
12736 bfd_put_32(output_bfd, ((eh->fdpic_cnts.gotfuncdesc_offset & ~1)
12737 + sgot->output_offset),
12738 contents + rel->r_offset);
12739 /* Add funcdesc and associated R_ARM_FUNCDESC_VALUE. */
12740 if(h->dynindx == -1)
12741 {
12742 int dynindx;
12743 int offset = eh->fdpic_cnts.funcdesc_offset & ~1;
12744 bfd_vma addr;
12745 bfd_vma seg = -1;
12746
12747 /* For static binaries sym_sec can be null. */
12748 if (sym_sec)
12749 {
12750 dynindx = elf_section_data (sym_sec->output_section)->dynindx;
12751 addr = dynreloc_value - sym_sec->output_section->vma;
12752 }
12753 else
12754 {
12755 dynindx = 0;
12756 addr = 0;
12757 }
12758
12759 /* Emit R_ARM_FUNCDESC_VALUE on funcdesc if not done yet. */
12760 arm_elf_fill_funcdesc(output_bfd, info,
12761 &eh->fdpic_cnts.funcdesc_offset,
12762 dynindx, offset, addr, dynreloc_value, seg);
12763 }
12764
12765 /* Add a dynamic relocation on GOT entry if not already done. */
12766 if ((eh->fdpic_cnts.gotfuncdesc_offset & 1) == 0)
12767 {
12768 if (h->dynindx == -1)
12769 {
12770 outrel.r_info = ELF32_R_INFO (0, R_ARM_RELATIVE);
12771 if (h->root.type == bfd_link_hash_undefweak)
12772 bfd_put_32(output_bfd, 0, sgot->contents
12773 + (eh->fdpic_cnts.gotfuncdesc_offset & ~1));
12774 else
12775 bfd_put_32(output_bfd, sgot->output_section->vma
12776 + sgot->output_offset
12777 + (eh->fdpic_cnts.funcdesc_offset & ~1),
12778 sgot->contents
12779 + (eh->fdpic_cnts.gotfuncdesc_offset & ~1));
12780 }
12781 else
12782 {
12783 outrel.r_info = ELF32_R_INFO (h->dynindx, R_ARM_FUNCDESC);
12784 }
12785 outrel.r_offset = sgot->output_section->vma
12786 + sgot->output_offset
12787 + (eh->fdpic_cnts.gotfuncdesc_offset & ~1);
12788 outrel.r_addend = 0;
12789 if (h->dynindx == -1 && !bfd_link_pic(info))
12790 if (h->root.type == bfd_link_hash_undefweak)
4b24dd1a 12791 arm_elf_add_rofixup(output_bfd, globals->srofixup, -1);
e8b09b87 12792 else
4b24dd1a
AM		 12793 arm_elf_add_rofixup(output_bfd, globals->srofixup,
12794 outrel.r_offset);
e8b09b87
CL		 12795 else
12796 elf32_arm_add_dynreloc (output_bfd, info, srelgot, &outrel);
12797 eh->fdpic_cnts.gotfuncdesc_offset |= 1;
12798 }
12799 }
12800 else
12801 {
12802 /* Such relocation on static function should not have been
12803 emitted by the compiler. */
12804 abort();
12805 }
12806 }
12807 *unresolved_reloc_p = FALSE;
12808 return bfd_reloc_ok;
12809
12810 case R_ARM_FUNCDESC:
12811 {
4b24dd1a 12812 if (h == NULL)
e8b09b87
CL		 12813 {
12814 struct fdpic_local *local_fdpic_cnts = elf32_arm_local_fdpic_cnts(input_bfd);
12815 Elf_Internal_Rela outrel;
12816 int dynindx = elf_section_data (sym_sec->output_section)->dynindx;
12817 int offset = local_fdpic_cnts[r_symndx].funcdesc_offset & ~1;
12818 bfd_vma addr = dynreloc_value - sym_sec->output_section->vma;
12819 bfd_vma seg = -1;
12820
12821 if (bfd_link_pic(info) && dynindx == 0)
12822 abort();
12823
12824 /* Replace static FUNCDESC relocation with a
12825 R_ARM_RELATIVE dynamic relocation or with a rofixup for
12826 executable. */
12827 outrel.r_info = ELF32_R_INFO (0, R_ARM_RELATIVE);
12828 outrel.r_offset = input_section->output_section->vma
12829 + input_section->output_offset + rel->r_offset;
12830 outrel.r_addend = 0;
12831 if (bfd_link_pic(info))
12832 elf32_arm_add_dynreloc (output_bfd, info, srelgot, &outrel);
12833 else
12834 arm_elf_add_rofixup(output_bfd, globals->srofixup, outrel.r_offset);
12835
12836 bfd_put_32 (input_bfd, sgot->output_section->vma
12837 + sgot->output_offset + offset, hit_data);
12838
12839 /* Emit R_ARM_FUNCDESC_VALUE on funcdesc if not done yet. */
12840 arm_elf_fill_funcdesc(output_bfd, info,
12841 &local_fdpic_cnts[r_symndx].funcdesc_offset,
12842 dynindx, offset, addr, dynreloc_value, seg);
12843 }
12844 else
12845 {
12846 if (h->dynindx == -1)
12847 {
12848 int dynindx;
12849 int offset = eh->fdpic_cnts.funcdesc_offset & ~1;
12850 bfd_vma addr;
12851 bfd_vma seg = -1;
12852 Elf_Internal_Rela outrel;
12853
12854 /* For static binaries sym_sec can be null. */
12855 if (sym_sec)
12856 {
12857 dynindx = elf_section_data (sym_sec->output_section)->dynindx;
12858 addr = dynreloc_value - sym_sec->output_section->vma;
12859 }
12860 else
12861 {
12862 dynindx = 0;
12863 addr = 0;
12864 }
12865
12866 if (bfd_link_pic(info) && dynindx == 0)
12867 abort();
12868
12869 /* Replace static FUNCDESC relocation with a
12870 R_ARM_RELATIVE dynamic relocation. */
12871 outrel.r_info = ELF32_R_INFO (0, R_ARM_RELATIVE);
12872 outrel.r_offset = input_section->output_section->vma
12873 + input_section->output_offset + rel->r_offset;
12874 outrel.r_addend = 0;
12875 if (bfd_link_pic(info))
12876 elf32_arm_add_dynreloc (output_bfd, info, srelgot, &outrel);
12877 else
12878 arm_elf_add_rofixup(output_bfd, globals->srofixup, outrel.r_offset);
12879
12880 bfd_put_32 (input_bfd, sgot->output_section->vma
12881 + sgot->output_offset + offset, hit_data);
12882
12883 /* Emit R_ARM_FUNCDESC_VALUE on funcdesc if not done yet. */
12884 arm_elf_fill_funcdesc(output_bfd, info,
12885 &eh->fdpic_cnts.funcdesc_offset,
12886 dynindx, offset, addr, dynreloc_value, seg);
12887 }
12888 else
12889 {
12890 Elf_Internal_Rela outrel;
12891
12892 /* Add a dynamic relocation. */
12893 outrel.r_info = ELF32_R_INFO (h->dynindx, R_ARM_FUNCDESC);
12894 outrel.r_offset = input_section->output_section->vma
12895 + input_section->output_offset + rel->r_offset;
12896 outrel.r_addend = 0;
12897 elf32_arm_add_dynreloc (output_bfd, info, srelgot, &outrel);
12898 }
12899 }
12900 }
12901 *unresolved_reloc_p = FALSE;
12902 return bfd_reloc_ok;
12903
e5d6e09e
AV		 12904 case R_ARM_THM_BF16:
12905 {
12906 bfd_vma relocation;
12907 bfd_vma upper_insn = bfd_get_16 (input_bfd, hit_data);
12908 bfd_vma lower_insn = bfd_get_16 (input_bfd, hit_data + 2);
12909
12910 if (globals->use_rel)
12911 {
12912 bfd_vma immA = (upper_insn & 0x001f);
12913 bfd_vma immB = (lower_insn & 0x07fe) >> 1;
12914 bfd_vma immC = (lower_insn & 0x0800) >> 11;
12915 addend = (immA << 12);
12916 addend |= (immB << 2);
12917 addend |= (immC << 1);
12918 addend |= 1;
12919 /* Sign extend. */
e6f65e75 12920 signed_addend = (addend & 0x10000) ? addend - (1 << 17) : addend;
e5d6e09e
AV		 12921 }
12922
e6f65e75 12923 relocation = value + signed_addend;
e5d6e09e
AV		 12924 relocation -= (input_section->output_section->vma
12925 + input_section->output_offset
12926 + rel->r_offset);
12927
12928 /* Put RELOCATION back into the insn. */
12929 {
12930 bfd_vma immA = (relocation & 0x0001f000) >> 12;
12931 bfd_vma immB = (relocation & 0x00000ffc) >> 2;
12932 bfd_vma immC = (relocation & 0x00000002) >> 1;
12933
12934 upper_insn = (upper_insn & 0xffe0) | immA;
12935 lower_insn = (lower_insn & 0xf001) | (immC << 11) | (immB << 1);
12936 }
12937
12938 /* Put the relocated value back in the object file: */
12939 bfd_put_16 (input_bfd, upper_insn, hit_data);
12940 bfd_put_16 (input_bfd, lower_insn, hit_data + 2);
12941
12942 return bfd_reloc_ok;
12943 }
12944
1889da70
AV		 12945 case R_ARM_THM_BF12:
12946 {
12947 bfd_vma relocation;
12948 bfd_vma upper_insn = bfd_get_16 (input_bfd, hit_data);
12949 bfd_vma lower_insn = bfd_get_16 (input_bfd, hit_data + 2);
12950
12951 if (globals->use_rel)
12952 {
12953 bfd_vma immA = (upper_insn & 0x0001);
12954 bfd_vma immB = (lower_insn & 0x07fe) >> 1;
12955 bfd_vma immC = (lower_insn & 0x0800) >> 11;
12956 addend = (immA << 12);
12957 addend |= (immB << 2);
12958 addend |= (immC << 1);
12959 addend |= 1;
12960 /* Sign extend. */
12961 addend = (addend & 0x1000) ? addend - (1 << 13) : addend;
e6f65e75 12962 signed_addend = addend;
1889da70
AV		 12963 }
12964
e6f65e75 12965 relocation = value + signed_addend;
1889da70
AV		 12966 relocation -= (input_section->output_section->vma
12967 + input_section->output_offset
12968 + rel->r_offset);
12969
12970 /* Put RELOCATION back into the insn. */
12971 {
12972 bfd_vma immA = (relocation & 0x00001000) >> 12;
12973 bfd_vma immB = (relocation & 0x00000ffc) >> 2;
12974 bfd_vma immC = (relocation & 0x00000002) >> 1;
12975
12976 upper_insn = (upper_insn & 0xfffe) | immA;
12977 lower_insn = (lower_insn & 0xf001) | (immC << 11) | (immB << 1);
12978 }
12979
12980 /* Put the relocated value back in the object file: */
12981 bfd_put_16 (input_bfd, upper_insn, hit_data);
12982 bfd_put_16 (input_bfd, lower_insn, hit_data + 2);
12983
12984 return bfd_reloc_ok;
12985 }
12986
1caf72a5
AV		 12987 case R_ARM_THM_BF18:
12988 {
12989 bfd_vma relocation;
12990 bfd_vma upper_insn = bfd_get_16 (input_bfd, hit_data);
12991 bfd_vma lower_insn = bfd_get_16 (input_bfd, hit_data + 2);
12992
12993 if (globals->use_rel)
12994 {
12995 bfd_vma immA = (upper_insn & 0x007f);
12996 bfd_vma immB = (lower_insn & 0x07fe) >> 1;
12997 bfd_vma immC = (lower_insn & 0x0800) >> 11;
12998 addend = (immA << 12);
12999 addend |= (immB << 2);
13000 addend |= (immC << 1);
13001 addend |= 1;
13002 /* Sign extend. */
13003 addend = (addend & 0x40000) ? addend - (1 << 19) : addend;
e6f65e75 13004 signed_addend = addend;
1caf72a5
AV		 13005 }
13006
e6f65e75 13007 relocation = value + signed_addend;
1caf72a5
AV		 13008 relocation -= (input_section->output_section->vma
13009 + input_section->output_offset
13010 + rel->r_offset);
13011
13012 /* Put RELOCATION back into the insn. */
13013 {
13014 bfd_vma immA = (relocation & 0x0007f000) >> 12;
13015 bfd_vma immB = (relocation & 0x00000ffc) >> 2;
13016 bfd_vma immC = (relocation & 0x00000002) >> 1;
13017
13018 upper_insn = (upper_insn & 0xff80) | immA;
13019 lower_insn = (lower_insn & 0xf001) | (immC << 11) | (immB << 1);
13020 }
13021
13022 /* Put the relocated value back in the object file: */
13023 bfd_put_16 (input_bfd, upper_insn, hit_data);
13024 bfd_put_16 (input_bfd, lower_insn, hit_data + 2);
13025
13026 return bfd_reloc_ok;
13027 }
13028
252b5132
RH		 13029 default:
13030 return bfd_reloc_notsupported;
13031 }
13032}
13033
98c1d4aa
NC		 13034/* Add INCREMENT to the reloc (of type HOWTO) at ADDRESS. */
13035static void
07d6d2b8
AM		 13036arm_add_to_rel (bfd * abfd,
13037 bfd_byte * address,
57e8b36a 13038 reloc_howto_type * howto,
07d6d2b8 13039 bfd_signed_vma increment)
98c1d4aa 13040{
98c1d4aa
NC		 13041 bfd_signed_vma addend;
13042
bd97cb95
DJ		 13043 if (howto->type == R_ARM_THM_CALL
13044 || howto->type == R_ARM_THM_JUMP24)
98c1d4aa 13045 {
9a5aca8c
AM		 13046 int upper_insn, lower_insn;
13047 int upper, lower;
98c1d4aa 13048
9a5aca8c
AM		 13049 upper_insn = bfd_get_16 (abfd, address);
13050 lower_insn = bfd_get_16 (abfd, address + 2);
13051 upper = upper_insn & 0x7ff;
13052 lower = lower_insn & 0x7ff;
13053
13054 addend = (upper << 12) | (lower << 1);
ddda4409 13055 addend += increment;
9a5aca8c 13056 addend >>= 1;
98c1d4aa 13057
9a5aca8c
AM		 13058 upper_insn = (upper_insn & 0xf800) | ((addend >> 11) & 0x7ff);
13059 lower_insn = (lower_insn & 0xf800) | (addend & 0x7ff);
13060
dc810e39
AM		 13061 bfd_put_16 (abfd, (bfd_vma) upper_insn, address);
13062 bfd_put_16 (abfd, (bfd_vma) lower_insn, address + 2);
9a5aca8c
AM		 13063 }
13064 else
13065 {
07d6d2b8 13066 bfd_vma contents;
9a5aca8c
AM		 13067
13068 contents = bfd_get_32 (abfd, address);
13069
13070 /* Get the (signed) value from the instruction. */
13071 addend = contents & howto->src_mask;
13072 if (addend & ((howto->src_mask + 1) >> 1))
13073 {
13074 bfd_signed_vma mask;
13075
13076 mask = -1;
13077 mask &= ~ howto->src_mask;
13078 addend |= mask;
13079 }
13080
13081 /* Add in the increment, (which is a byte value). */
13082 switch (howto->type)
13083 {
13084 default:
13085 addend += increment;
13086 break;
13087
13088 case R_ARM_PC24:
c6596c5e 13089 case R_ARM_PLT32:
5b5bb741
PB		 13090 case R_ARM_CALL:
13091 case R_ARM_JUMP24:
9a5aca8c 13092 addend <<= howto->size;
dc810e39 13093 addend += increment;
9a5aca8c
AM		 13094
13095 /* Should we check for overflow here ? */
13096
13097 /* Drop any undesired bits. */
13098 addend >>= howto->rightshift;
13099 break;
13100 }
13101
13102 contents = (contents & ~ howto->dst_mask) | (addend & howto->dst_mask);
13103
13104 bfd_put_32 (abfd, contents, address);
ddda4409 13105 }
98c1d4aa 13106}
252b5132 13107
ba93b8ac
DJ		 13108#define IS_ARM_TLS_RELOC(R_TYPE) \
13109 ((R_TYPE) == R_ARM_TLS_GD32 \
5c5a4843 13110 || (R_TYPE) == R_ARM_TLS_GD32_FDPIC \
ba93b8ac
DJ		 13111 || (R_TYPE) == R_ARM_TLS_LDO32 \
13112 || (R_TYPE) == R_ARM_TLS_LDM32 \
5c5a4843 13113 || (R_TYPE) == R_ARM_TLS_LDM32_FDPIC \
ba93b8ac
DJ		 13114 || (R_TYPE) == R_ARM_TLS_DTPOFF32 \
13115 || (R_TYPE) == R_ARM_TLS_DTPMOD32 \
13116 || (R_TYPE) == R_ARM_TLS_TPOFF32 \
13117 || (R_TYPE) == R_ARM_TLS_LE32 \
0855e32b 13118 || (R_TYPE) == R_ARM_TLS_IE32 \
5c5a4843 13119 || (R_TYPE) == R_ARM_TLS_IE32_FDPIC \
0855e32b
NS		 13120 || IS_ARM_TLS_GNU_RELOC (R_TYPE))
13121
13122/* Specific set of relocations for the gnu tls dialect. */
13123#define IS_ARM_TLS_GNU_RELOC(R_TYPE) \
13124 ((R_TYPE) == R_ARM_TLS_GOTDESC \
13125 || (R_TYPE) == R_ARM_TLS_CALL \
13126 || (R_TYPE) == R_ARM_THM_TLS_CALL \
13127 || (R_TYPE) == R_ARM_TLS_DESCSEQ \
13128 || (R_TYPE) == R_ARM_THM_TLS_DESCSEQ)
ba93b8ac 13129
252b5132 13130/* Relocate an ARM ELF section. */
906e58ca 13131
b34976b6 13132static bfd_boolean
07d6d2b8 13133elf32_arm_relocate_section (bfd * output_bfd,
57e8b36a 13134 struct bfd_link_info * info,
07d6d2b8
AM		 13135 bfd * input_bfd,
13136 asection * input_section,
13137 bfd_byte * contents,
13138 Elf_Internal_Rela * relocs,
13139 Elf_Internal_Sym * local_syms,
13140 asection ** local_sections)
252b5132 13141{
b34976b6
AM		 13142 Elf_Internal_Shdr *symtab_hdr;
13143 struct elf_link_hash_entry **sym_hashes;
13144 Elf_Internal_Rela *rel;
13145 Elf_Internal_Rela *relend;
13146 const char *name;
b32d3aa2 13147 struct elf32_arm_link_hash_table * globals;
252b5132 13148
4e7fd91e 13149 globals = elf32_arm_hash_table (info);
4dfe6ac6
NC		 13150 if (globals == NULL)
13151 return FALSE;
b491616a 13152
0ffa91dd 13153 symtab_hdr = & elf_symtab_hdr (input_bfd);
252b5132
RH		 13154 sym_hashes = elf_sym_hashes (input_bfd);
13155
13156 rel = relocs;
13157 relend = relocs + input_section->reloc_count;
13158 for (; rel < relend; rel++)
13159 {
07d6d2b8
AM		 13160 int r_type;
13161 reloc_howto_type * howto;
13162 unsigned long r_symndx;
13163 Elf_Internal_Sym * sym;
13164 asection * sec;
252b5132 13165 struct elf_link_hash_entry * h;
07d6d2b8
AM		 13166 bfd_vma relocation;
13167 bfd_reloc_status_type r;
13168 arelent bfd_reloc;
13169 char sym_type;
13170 bfd_boolean unresolved_reloc = FALSE;
f2a9dd69 13171 char *error_message = NULL;
f21f3fe0 13172
252b5132 13173 r_symndx = ELF32_R_SYM (rel->r_info);
ba96a88f 13174 r_type = ELF32_R_TYPE (rel->r_info);
b32d3aa2 13175 r_type = arm_real_reloc_type (globals, r_type);
252b5132 13176
ba96a88f 13177 if ( r_type == R_ARM_GNU_VTENTRY
99059e56
RM		 13178 || r_type == R_ARM_GNU_VTINHERIT)
13179 continue;
252b5132 13180
47aeb64c
NC		 13181 howto = bfd_reloc.howto = elf32_arm_howto_from_type (r_type);
13182
13183 if (howto == NULL)
13184 return _bfd_unrecognized_reloc (input_bfd, input_section, r_type);
252b5132 13185
252b5132
RH		 13186 h = NULL;
13187 sym = NULL;
13188 sec = NULL;
9b485d32 13189
252b5132
RH		 13190 if (r_symndx < symtab_hdr->sh_info)
13191 {
13192 sym = local_syms + r_symndx;
ba93b8ac 13193 sym_type = ELF32_ST_TYPE (sym->st_info);
252b5132 13194 sec = local_sections[r_symndx];
ffcb4889
NS		 13195
13196 /* An object file might have a reference to a local
13197 undefined symbol. This is a daft object file, but we
13198 should at least do something about it. V4BX & NONE
13199 relocations do not use the symbol and are explicitly
77b4f08f
TS		 13200 allowed to use the undefined symbol, so allow those.
13201 Likewise for relocations against STN_UNDEF. */
ffcb4889
NS		 13202 if (r_type != R_ARM_V4BX
13203 && r_type != R_ARM_NONE
77b4f08f 13204 && r_symndx != STN_UNDEF
ffcb4889
NS		 13205 && bfd_is_und_section (sec)
13206 && ELF_ST_BIND (sym->st_info) != STB_WEAK)
1a72702b
AM		 13207 (*info->callbacks->undefined_symbol)
13208 (info, bfd_elf_string_from_elf_section
13209 (input_bfd, symtab_hdr->sh_link, sym->st_name),
13210 input_bfd, input_section,
13211 rel->r_offset, TRUE);
b38cadfb 13212
4e7fd91e 13213 if (globals->use_rel)
f8df10f4 13214 {
4e7fd91e
PB		 13215 relocation = (sec->output_section->vma
13216 + sec->output_offset
13217 + sym->st_value);
0e1862bb 13218 if (!bfd_link_relocatable (info)
ab96bf03
AM		 13219 && (sec->flags & SEC_MERGE)
13220 && ELF_ST_TYPE (sym->st_info) == STT_SECTION)
f8df10f4 13221 {
4e7fd91e
PB		 13222 asection *msec;
13223 bfd_vma addend, value;
13224
39623e12 13225 switch (r_type)
4e7fd91e 13226 {
39623e12
PB		 13227 case R_ARM_MOVW_ABS_NC:
13228 case R_ARM_MOVT_ABS:
13229 value = bfd_get_32 (input_bfd, contents + rel->r_offset);
13230 addend = ((value & 0xf0000) >> 4) | (value & 0xfff);
13231 addend = (addend ^ 0x8000) - 0x8000;
13232 break;
f8df10f4 13233
39623e12
PB		 13234 case R_ARM_THM_MOVW_ABS_NC:
13235 case R_ARM_THM_MOVT_ABS:
13236 value = bfd_get_16 (input_bfd, contents + rel->r_offset)
13237 << 16;
13238 value |= bfd_get_16 (input_bfd,
13239 contents + rel->r_offset + 2);
13240 addend = ((value & 0xf7000) >> 4) | (value & 0xff)
13241 | ((value & 0x04000000) >> 15);
13242 addend = (addend ^ 0x8000) - 0x8000;
13243 break;
f8df10f4 13244
39623e12
PB		 13245 default:
13246 if (howto->rightshift
13247 || (howto->src_mask & (howto->src_mask + 1)))
13248 {
4eca0228 13249 _bfd_error_handler
695344c0 13250 /* xgettext:c-format */
2dcf00ce
AM		 13251 (_("%pB(%pA+%#" PRIx64 "): "
13252 "%s relocation against SEC_MERGE section"),
39623e12 13253 input_bfd, input_section,
2dcf00ce 13254 (uint64_t) rel->r_offset, howto->name);
39623e12
PB		 13255 return FALSE;
13256 }
13257
13258 value = bfd_get_32 (input_bfd, contents + rel->r_offset);
13259
13260 /* Get the (signed) value from the instruction. */
13261 addend = value & howto->src_mask;
13262 if (addend & ((howto->src_mask + 1) >> 1))
13263 {
13264 bfd_signed_vma mask;
13265
13266 mask = -1;
13267 mask &= ~ howto->src_mask;
13268 addend |= mask;
13269 }
13270 break;
4e7fd91e 13271 }
39623e12 13272
4e7fd91e
PB		 13273 msec = sec;
13274 addend =
13275 _bfd_elf_rel_local_sym (output_bfd, sym, &msec, addend)
13276 - relocation;
13277 addend += msec->output_section->vma + msec->output_offset;
39623e12 13278
cc643b88 13279 /* Cases here must match those in the preceding
39623e12
PB		 13280 switch statement. */
13281 switch (r_type)
13282 {
13283 case R_ARM_MOVW_ABS_NC:
13284 case R_ARM_MOVT_ABS:
13285 value = (value & 0xfff0f000) | ((addend & 0xf000) << 4)
13286 | (addend & 0xfff);
13287 bfd_put_32 (input_bfd, value, contents + rel->r_offset);
13288 break;
13289
13290 case R_ARM_THM_MOVW_ABS_NC:
13291 case R_ARM_THM_MOVT_ABS:
13292 value = (value & 0xfbf08f00) | ((addend & 0xf700) << 4)
13293 | (addend & 0xff) | ((addend & 0x0800) << 15);
13294 bfd_put_16 (input_bfd, value >> 16,
13295 contents + rel->r_offset);
13296 bfd_put_16 (input_bfd, value,
13297 contents + rel->r_offset + 2);
13298 break;
13299
13300 default:
13301 value = (value & ~ howto->dst_mask)
13302 | (addend & howto->dst_mask);
13303 bfd_put_32 (input_bfd, value, contents + rel->r_offset);
13304 break;
13305 }
f8df10f4 13306 }
f8df10f4 13307 }
4e7fd91e
PB		 13308 else
13309 relocation = _bfd_elf_rela_local_sym (output_bfd, sym, &sec, rel);
252b5132
RH		 13310 }
13311 else
13312 {
62d887d4 13313 bfd_boolean warned, ignored;
560e09e9 13314
b2a8e766
AM		 13315 RELOC_FOR_GLOBAL_SYMBOL (info, input_bfd, input_section, rel,
13316 r_symndx, symtab_hdr, sym_hashes,
13317 h, sec, relocation,
62d887d4 13318 unresolved_reloc, warned, ignored);
ba93b8ac
DJ		 13319
13320 sym_type = h->type;
252b5132
RH		 13321 }
13322
dbaa2011 13323 if (sec != NULL && discarded_section (sec))
e4067dbb 13324 RELOC_AGAINST_DISCARDED_SECTION (info, input_bfd, input_section,
545fd46b 13325 rel, 1, relend, howto, 0, contents);
ab96bf03 13326
0e1862bb 13327 if (bfd_link_relocatable (info))
ab96bf03
AM		 13328 {
13329 /* This is a relocatable link. We don't have to change
13330 anything, unless the reloc is against a section symbol,
13331 in which case we have to adjust according to where the
13332 section symbol winds up in the output section. */
13333 if (sym != NULL && ELF_ST_TYPE (sym->st_info) == STT_SECTION)
13334 {
13335 if (globals->use_rel)
13336 arm_add_to_rel (input_bfd, contents + rel->r_offset,
13337 howto, (bfd_signed_vma) sec->output_offset);
13338 else
13339 rel->r_addend += sec->output_offset;
13340 }
13341 continue;
13342 }
13343
252b5132
RH		 13344 if (h != NULL)
13345 name = h->root.root.string;
13346 else
13347 {
13348 name = (bfd_elf_string_from_elf_section
13349 (input_bfd, symtab_hdr->sh_link, sym->st_name));
13350 if (name == NULL || *name == '\0')
fd361982 13351 name = bfd_section_name (sec);
252b5132 13352 }
f21f3fe0 13353
cf35638d 13354 if (r_symndx != STN_UNDEF
ba93b8ac
DJ		 13355 && r_type != R_ARM_NONE
13356 && (h == NULL
13357 || h->root.type == bfd_link_hash_defined
13358 || h->root.type == bfd_link_hash_defweak)
13359 && IS_ARM_TLS_RELOC (r_type) != (sym_type == STT_TLS))
13360 {
4eca0228 13361 _bfd_error_handler
ba93b8ac 13362 ((sym_type == STT_TLS
695344c0 13363 /* xgettext:c-format */
2dcf00ce 13364 ? _("%pB(%pA+%#" PRIx64 "): %s used with TLS symbol %s")
695344c0 13365 /* xgettext:c-format */
2dcf00ce 13366 : _("%pB(%pA+%#" PRIx64 "): %s used with non-TLS symbol %s")),
ba93b8ac
DJ		 13367 input_bfd,
13368 input_section,
2dcf00ce 13369 (uint64_t) rel->r_offset,
ba93b8ac
DJ		 13370 howto->name,
13371 name);
13372 }
13373
0855e32b 13374 /* We call elf32_arm_final_link_relocate unless we're completely
99059e56
RM		 13375 done, i.e., the relaxation produced the final output we want,
13376 and we won't let anybody mess with it. Also, we have to do
13377 addend adjustments in case of a R_ARM_TLS_GOTDESC relocation
6a631e86 13378 both in relaxed and non-relaxed cases. */
39d911fc
TP		 13379 if ((elf32_arm_tls_transition (info, r_type, h) != (unsigned)r_type)
13380 || (IS_ARM_TLS_GNU_RELOC (r_type)
13381 && !((h ? elf32_arm_hash_entry (h)->tls_type :
13382 elf32_arm_local_got_tls_type (input_bfd)[r_symndx])
13383 & GOT_TLS_GDESC)))
13384 {
13385 r = elf32_arm_tls_relax (globals, input_bfd, input_section,
13386 contents, rel, h == NULL);
13387 /* This may have been marked unresolved because it came from
13388 a shared library. But we've just dealt with that. */
13389 unresolved_reloc = 0;
13390 }
13391 else
13392 r = bfd_reloc_continue;
b38cadfb 13393
39d911fc
TP		 13394 if (r == bfd_reloc_continue)
13395 {
13396 unsigned char branch_type =
13397 h ? ARM_GET_SYM_BRANCH_TYPE (h->target_internal)
13398 : ARM_GET_SYM_BRANCH_TYPE (sym->st_target_internal);
13399
13400 r = elf32_arm_final_link_relocate (howto, input_bfd, output_bfd,
13401 input_section, contents, rel,
13402 relocation, info, sec, name,
13403 sym_type, branch_type, h,
13404 &unresolved_reloc,
13405 &error_message);
13406 }
0945cdfd
DJ		 13407
13408 /* Dynamic relocs are not propagated for SEC_DEBUGGING sections
13409 because such sections are not SEC_ALLOC and thus ld.so will
13410 not process them. */
13411 if (unresolved_reloc
99059e56
RM		 13412 && !((input_section->flags & SEC_DEBUGGING) != 0
13413 && h->def_dynamic)
1d5316ab
AM		 13414 && _bfd_elf_section_offset (output_bfd, info, input_section,
13415 rel->r_offset) != (bfd_vma) -1)
0945cdfd 13416 {
4eca0228 13417 _bfd_error_handler
695344c0 13418 /* xgettext:c-format */
2dcf00ce
AM		 13419 (_("%pB(%pA+%#" PRIx64 "): "
13420 "unresolvable %s relocation against symbol `%s'"),
843fe662
L		 13421 input_bfd,
13422 input_section,
2dcf00ce 13423 (uint64_t) rel->r_offset,
843fe662
L		 13424 howto->name,
13425 h->root.root.string);
0945cdfd
DJ		 13426 return FALSE;
13427 }
252b5132
RH		 13428
13429 if (r != bfd_reloc_ok)
13430 {
252b5132
RH		 13431 switch (r)
13432 {
13433 case bfd_reloc_overflow:
cf919dfd
PB		 13434 /* If the overflowing reloc was to an undefined symbol,
13435 we have already printed one error message and there
13436 is no point complaining again. */
1a72702b
AM		 13437 if (!h || h->root.type != bfd_link_hash_undefined)
13438 (*info->callbacks->reloc_overflow)
13439 (info, (h ? &h->root : NULL), name, howto->name,
13440 (bfd_vma) 0, input_bfd, input_section, rel->r_offset);
252b5132
RH		 13441 break;
13442
13443 case bfd_reloc_undefined:
1a72702b
AM		 13444 (*info->callbacks->undefined_symbol)
13445 (info, name, input_bfd, input_section, rel->r_offset, TRUE);
252b5132
RH		 13446 break;
13447
13448 case bfd_reloc_outofrange:
f2a9dd69 13449 error_message = _("out of range");
252b5132
RH		 13450 goto common_error;
13451
13452 case bfd_reloc_notsupported:
f2a9dd69 13453 error_message = _("unsupported relocation");
252b5132
RH		 13454 goto common_error;
13455
13456 case bfd_reloc_dangerous:
f2a9dd69 13457 /* error_message should already be set. */
252b5132
RH		 13458 goto common_error;
13459
13460 default:
f2a9dd69 13461 error_message = _("unknown error");
8029a119 13462 /* Fall through. */
252b5132
RH		 13463
13464 common_error:
f2a9dd69 13465 BFD_ASSERT (error_message != NULL);
1a72702b
AM		 13466 (*info->callbacks->reloc_dangerous)
13467 (info, error_message, input_bfd, input_section, rel->r_offset);
252b5132
RH		 13468 break;
13469 }
13470 }
13471 }
13472
b34976b6 13473 return TRUE;
252b5132
RH		 13474}
13475
91d6fa6a 13476/* Add a new unwind edit to the list described by HEAD, TAIL. If TINDEX is zero,
2468f9c9 13477 adds the edit to the start of the list. (The list must be built in order of
91d6fa6a 13478 ascending TINDEX: the function's callers are primarily responsible for
2468f9c9
PB		 13479 maintaining that condition). */
13480
13481static void
13482add_unwind_table_edit (arm_unwind_table_edit **head,
13483 arm_unwind_table_edit **tail,
13484 arm_unwind_edit_type type,
13485 asection *linked_section,
91d6fa6a 13486 unsigned int tindex)
2468f9c9 13487{
21d799b5
NC		 13488 arm_unwind_table_edit *new_edit = (arm_unwind_table_edit *)
13489 xmalloc (sizeof (arm_unwind_table_edit));
b38cadfb 13490
2468f9c9
PB		 13491 new_edit->type = type;
13492 new_edit->linked_section = linked_section;
91d6fa6a 13493 new_edit->index = tindex;
b38cadfb 13494
91d6fa6a 13495 if (tindex > 0)
2468f9c9
PB		 13496 {
13497 new_edit->next = NULL;
13498
13499 if (*tail)
13500 (*tail)->next = new_edit;
13501
13502 (*tail) = new_edit;
13503
13504 if (!*head)
13505 (*head) = new_edit;
13506 }
13507 else
13508 {
13509 new_edit->next = *head;
13510
13511 if (!*tail)
13512 *tail = new_edit;
13513
13514 *head = new_edit;
13515 }
13516}
13517
13518static _arm_elf_section_data *get_arm_elf_section_data (asection *);
13519
13520/* Increase the size of EXIDX_SEC by ADJUST bytes. ADJUST mau be negative. */
13521static void
13522adjust_exidx_size(asection *exidx_sec, int adjust)
13523{
13524 asection *out_sec;
13525
13526 if (!exidx_sec->rawsize)
13527 exidx_sec->rawsize = exidx_sec->size;
13528
fd361982 13529 bfd_set_section_size (exidx_sec, exidx_sec->size + adjust);
2468f9c9
PB		 13530 out_sec = exidx_sec->output_section;
13531 /* Adjust size of output section. */
fd361982 13532 bfd_set_section_size (out_sec, out_sec->size +adjust);
2468f9c9
PB		 13533}
13534
13535/* Insert an EXIDX_CANTUNWIND marker at the end of a section. */
13536static void
13537insert_cantunwind_after(asection *text_sec, asection *exidx_sec)
13538{
13539 struct _arm_elf_section_data *exidx_arm_data;
13540
13541 exidx_arm_data = get_arm_elf_section_data (exidx_sec);
13542 add_unwind_table_edit (
13543 &exidx_arm_data->u.exidx.unwind_edit_list,
13544 &exidx_arm_data->u.exidx.unwind_edit_tail,
13545 INSERT_EXIDX_CANTUNWIND_AT_END, text_sec, UINT_MAX);
13546
491d01d3
YU		 13547 exidx_arm_data->additional_reloc_count++;
13548
2468f9c9
PB		 13549 adjust_exidx_size(exidx_sec, 8);
13550}
13551
13552/* Scan .ARM.exidx tables, and create a list describing edits which should be
13553 made to those tables, such that:
b38cadfb 13554
2468f9c9
PB		 13555 1. Regions without unwind data are marked with EXIDX_CANTUNWIND entries.
13556 2. Duplicate entries are merged together (EXIDX_CANTUNWIND, or unwind
99059e56 13557 codes which have been inlined into the index).
2468f9c9 13558
85fdf906
AH		 13559 If MERGE_EXIDX_ENTRIES is false, duplicate entries are not merged.
13560
2468f9c9 13561 The edits are applied when the tables are written
b38cadfb 13562 (in elf32_arm_write_section). */
2468f9c9
PB		 13563
13564bfd_boolean
13565elf32_arm_fix_exidx_coverage (asection **text_section_order,
13566 unsigned int num_text_sections,
85fdf906
AH		 13567 struct bfd_link_info *info,
13568 bfd_boolean merge_exidx_entries)
2468f9c9
PB		 13569{
13570 bfd *inp;
13571 unsigned int last_second_word = 0, i;
13572 asection *last_exidx_sec = NULL;
13573 asection *last_text_sec = NULL;
13574 int last_unwind_type = -1;
13575
13576 /* Walk over all EXIDX sections, and create backlinks from the corrsponding
13577 text sections. */
c72f2fb2 13578 for (inp = info->input_bfds; inp != NULL; inp = inp->link.next)
2468f9c9
PB		 13579 {
13580 asection *sec;
b38cadfb 13581
2468f9c9 13582 for (sec = inp->sections; sec != NULL; sec = sec->next)
99059e56 13583 {
2468f9c9
PB		 13584 struct bfd_elf_section_data *elf_sec = elf_section_data (sec);
13585 Elf_Internal_Shdr *hdr = &elf_sec->this_hdr;
b38cadfb 13586
dec9d5df 13587 if (!hdr || hdr->sh_type != SHT_ARM_EXIDX)
2468f9c9 13588 continue;
b38cadfb 13589
2468f9c9
PB		 13590 if (elf_sec->linked_to)
13591 {
13592 Elf_Internal_Shdr *linked_hdr
99059e56 13593 = &elf_section_data (elf_sec->linked_to)->this_hdr;
2468f9c9 13594 struct _arm_elf_section_data *linked_sec_arm_data
99059e56 13595 = get_arm_elf_section_data (linked_hdr->bfd_section);
2468f9c9
PB		 13596
13597 if (linked_sec_arm_data == NULL)
99059e56 13598 continue;
2468f9c9
PB		 13599
13600 /* Link this .ARM.exidx section back from the text section it
99059e56 13601 describes. */
2468f9c9
PB		 13602 linked_sec_arm_data->u.text.arm_exidx_sec = sec;
13603 }
13604 }
13605 }
13606
13607 /* Walk all text sections in order of increasing VMA. Eilminate duplicate
13608 index table entries (EXIDX_CANTUNWIND and inlined unwind opcodes),
91d6fa6a 13609 and add EXIDX_CANTUNWIND entries for sections with no unwind table data. */
2468f9c9
PB		 13610
13611 for (i = 0; i < num_text_sections; i++)
13612 {
13613 asection *sec = text_section_order[i];
13614 asection *exidx_sec;
13615 struct _arm_elf_section_data *arm_data = get_arm_elf_section_data (sec);
13616 struct _arm_elf_section_data *exidx_arm_data;
13617 bfd_byte *contents = NULL;
13618 int deleted_exidx_bytes = 0;
13619 bfd_vma j;
13620 arm_unwind_table_edit *unwind_edit_head = NULL;
13621 arm_unwind_table_edit *unwind_edit_tail = NULL;
13622 Elf_Internal_Shdr *hdr;
13623 bfd *ibfd;
13624
13625 if (arm_data == NULL)
99059e56 13626 continue;
2468f9c9
PB		 13627
13628 exidx_sec = arm_data->u.text.arm_exidx_sec;
13629 if (exidx_sec == NULL)
13630 {
13631 /* Section has no unwind data. */
13632 if (last_unwind_type == 0 || !last_exidx_sec)
13633 continue;
13634
13635 /* Ignore zero sized sections. */
13636 if (sec->size == 0)
13637 continue;
13638
13639 insert_cantunwind_after(last_text_sec, last_exidx_sec);
13640 last_unwind_type = 0;
13641 continue;
13642 }
13643
22a8f80e
PB		 13644 /* Skip /DISCARD/ sections. */
13645 if (bfd_is_abs_section (exidx_sec->output_section))
13646 continue;
13647
2468f9c9
PB		 13648 hdr = &elf_section_data (exidx_sec)->this_hdr;
13649 if (hdr->sh_type != SHT_ARM_EXIDX)
99059e56 13650 continue;
b38cadfb 13651
2468f9c9
PB		 13652 exidx_arm_data = get_arm_elf_section_data (exidx_sec);
13653 if (exidx_arm_data == NULL)
99059e56 13654 continue;
b38cadfb 13655
2468f9c9 13656 ibfd = exidx_sec->owner;
b38cadfb 13657
2468f9c9
PB		 13658 if (hdr->contents != NULL)
13659 contents = hdr->contents;
13660 else if (! bfd_malloc_and_get_section (ibfd, exidx_sec, &contents))
13661 /* An error? */
13662 continue;
13663
ac06903d
YU		 13664 if (last_unwind_type > 0)
13665 {
13666 unsigned int first_word = bfd_get_32 (ibfd, contents);
13667 /* Add cantunwind if first unwind item does not match section
13668 start. */
13669 if (first_word != sec->vma)
13670 {
13671 insert_cantunwind_after (last_text_sec, last_exidx_sec);
13672 last_unwind_type = 0;
13673 }
13674 }
13675
2468f9c9
PB		 13676 for (j = 0; j < hdr->sh_size; j += 8)
13677 {
13678 unsigned int second_word = bfd_get_32 (ibfd, contents + j + 4);
13679 int unwind_type;
13680 int elide = 0;
13681
13682 /* An EXIDX_CANTUNWIND entry. */
13683 if (second_word == 1)
13684 {
13685 if (last_unwind_type == 0)
13686 elide = 1;
13687 unwind_type = 0;
13688 }
13689 /* Inlined unwinding data. Merge if equal to previous. */
13690 else if ((second_word & 0x80000000) != 0)
13691 {
85fdf906
AH		 13692 if (merge_exidx_entries
13693 && last_second_word == second_word && last_unwind_type == 1)
2468f9c9
PB		 13694 elide = 1;
13695 unwind_type = 1;
13696 last_second_word = second_word;
13697 }
13698 /* Normal table entry. In theory we could merge these too,
13699 but duplicate entries are likely to be much less common. */
13700 else
13701 unwind_type = 2;
13702
491d01d3 13703 if (elide && !bfd_link_relocatable (info))
2468f9c9
PB		 13704 {
13705 add_unwind_table_edit (&unwind_edit_head, &unwind_edit_tail,
13706 DELETE_EXIDX_ENTRY, NULL, j / 8);
13707
13708 deleted_exidx_bytes += 8;
13709 }
13710
13711 last_unwind_type = unwind_type;
13712 }
13713
13714 /* Free contents if we allocated it ourselves. */
13715 if (contents != hdr->contents)
99059e56 13716 free (contents);
2468f9c9
PB		 13717
13718 /* Record edits to be applied later (in elf32_arm_write_section). */
13719 exidx_arm_data->u.exidx.unwind_edit_list = unwind_edit_head;
13720 exidx_arm_data->u.exidx.unwind_edit_tail = unwind_edit_tail;
b38cadfb 13721
2468f9c9
PB		 13722 if (deleted_exidx_bytes > 0)
13723 adjust_exidx_size(exidx_sec, -deleted_exidx_bytes);
13724
13725 last_exidx_sec = exidx_sec;
13726 last_text_sec = sec;
13727 }
13728
13729 /* Add terminating CANTUNWIND entry. */
491d01d3
YU		 13730 if (!bfd_link_relocatable (info) && last_exidx_sec
13731 && last_unwind_type != 0)
2468f9c9
PB		 13732 insert_cantunwind_after(last_text_sec, last_exidx_sec);
13733
13734 return TRUE;
13735}
13736
3e6b1042
DJ		 13737static bfd_boolean
13738elf32_arm_output_glue_section (struct bfd_link_info *info, bfd *obfd,
13739 bfd *ibfd, const char *name)
13740{
13741 asection *sec, *osec;
13742
3d4d4302 13743 sec = bfd_get_linker_section (ibfd, name);
3e6b1042
DJ		 13744 if (sec == NULL || (sec->flags & SEC_EXCLUDE) != 0)
13745 return TRUE;
13746
13747 osec = sec->output_section;
13748 if (elf32_arm_write_section (obfd, info, sec, sec->contents))
13749 return TRUE;
13750
13751 if (! bfd_set_section_contents (obfd, osec, sec->contents,
13752 sec->output_offset, sec->size))
13753 return FALSE;
13754
13755 return TRUE;
13756}
13757
13758static bfd_boolean
13759elf32_arm_final_link (bfd *abfd, struct bfd_link_info *info)
13760{
13761 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (info);
fe33d2fa 13762 asection *sec, *osec;
3e6b1042 13763
4dfe6ac6
NC		 13764 if (globals == NULL)
13765 return FALSE;
13766
3e6b1042
DJ		 13767 /* Invoke the regular ELF backend linker to do all the work. */
13768 if (!bfd_elf_final_link (abfd, info))
13769 return FALSE;
13770
fe33d2fa
CL		 13771 /* Process stub sections (eg BE8 encoding, ...). */
13772 struct elf32_arm_link_hash_table *htab = elf32_arm_hash_table (info);
7292b3ac 13773 unsigned int i;
cdb21a0a
NS		 13774 for (i=0; i<htab->top_id; i++)
13775 {
13776 sec = htab->stub_group[i].stub_sec;
13777 /* Only process it once, in its link_sec slot. */
13778 if (sec && i == htab->stub_group[i].link_sec->id)
13779 {
13780 osec = sec->output_section;
13781 elf32_arm_write_section (abfd, info, sec, sec->contents);
13782 if (! bfd_set_section_contents (abfd, osec, sec->contents,
13783 sec->output_offset, sec->size))
13784 return FALSE;
13785 }
fe33d2fa 13786 }
fe33d2fa 13787
3e6b1042
DJ		 13788 /* Write out any glue sections now that we have created all the
13789 stubs. */
13790 if (globals->bfd_of_glue_owner != NULL)
13791 {
13792 if (! elf32_arm_output_glue_section (info, abfd,
13793 globals->bfd_of_glue_owner,
13794 ARM2THUMB_GLUE_SECTION_NAME))
13795 return FALSE;
13796
13797 if (! elf32_arm_output_glue_section (info, abfd,
13798 globals->bfd_of_glue_owner,
13799 THUMB2ARM_GLUE_SECTION_NAME))
13800 return FALSE;
13801
13802 if (! elf32_arm_output_glue_section (info, abfd,
13803 globals->bfd_of_glue_owner,
13804 VFP11_ERRATUM_VENEER_SECTION_NAME))
13805 return FALSE;
13806
a504d23a
LA		 13807 if (! elf32_arm_output_glue_section (info, abfd,
13808 globals->bfd_of_glue_owner,
13809 STM32L4XX_ERRATUM_VENEER_SECTION_NAME))
13810 return FALSE;
13811
3e6b1042
DJ		 13812 if (! elf32_arm_output_glue_section (info, abfd,
13813 globals->bfd_of_glue_owner,
13814 ARM_BX_GLUE_SECTION_NAME))
13815 return FALSE;
13816 }
13817
13818 return TRUE;
13819}
13820
5968a7b8
NC		 13821/* Return a best guess for the machine number based on the attributes. */
13822
13823static unsigned int
13824bfd_arm_get_mach_from_attributes (bfd * abfd)
13825{
13826 int arch = bfd_elf_get_obj_attr_int (abfd, OBJ_ATTR_PROC, Tag_CPU_arch);
13827
13828 switch (arch)
13829 {
c0c468d5 13830 case TAG_CPU_ARCH_PRE_V4: return bfd_mach_arm_3M;
5968a7b8
NC		 13831 case TAG_CPU_ARCH_V4: return bfd_mach_arm_4;
13832 case TAG_CPU_ARCH_V4T: return bfd_mach_arm_4T;
13833 case TAG_CPU_ARCH_V5T: return bfd_mach_arm_5T;
13834
13835 case TAG_CPU_ARCH_V5TE:
13836 {
13837 char * name;
13838
13839 BFD_ASSERT (Tag_CPU_name < NUM_KNOWN_OBJ_ATTRIBUTES);
13840 name = elf_known_obj_attributes (abfd) [OBJ_ATTR_PROC][Tag_CPU_name].s;
13841
13842 if (name)
13843 {
13844 if (strcmp (name, "IWMMXT2") == 0)
13845 return bfd_mach_arm_iWMMXt2;
13846
13847 if (strcmp (name, "IWMMXT") == 0)
6034aab8 13848 return bfd_mach_arm_iWMMXt;
088ca6c1
NC		 13849
13850 if (strcmp (name, "XSCALE") == 0)
13851 {
13852 int wmmx;
13853
13854 BFD_ASSERT (Tag_WMMX_arch < NUM_KNOWN_OBJ_ATTRIBUTES);
13855 wmmx = elf_known_obj_attributes (abfd) [OBJ_ATTR_PROC][Tag_WMMX_arch].i;
13856 switch (wmmx)
13857 {
13858 case 1: return bfd_mach_arm_iWMMXt;
13859 case 2: return bfd_mach_arm_iWMMXt2;
13860 default: return bfd_mach_arm_XScale;
13861 }
13862 }
5968a7b8
NC		 13863 }
13864
13865 return bfd_mach_arm_5TE;
13866 }
13867
c0c468d5
TP		 13868 case TAG_CPU_ARCH_V5TEJ:
13869 return bfd_mach_arm_5TEJ;
13870 case TAG_CPU_ARCH_V6:
13871 return bfd_mach_arm_6;
13872 case TAG_CPU_ARCH_V6KZ:
13873 return bfd_mach_arm_6KZ;
13874 case TAG_CPU_ARCH_V6T2:
13875 return bfd_mach_arm_6T2;
13876 case TAG_CPU_ARCH_V6K:
13877 return bfd_mach_arm_6K;
13878 case TAG_CPU_ARCH_V7:
13879 return bfd_mach_arm_7;
13880 case TAG_CPU_ARCH_V6_M:
13881 return bfd_mach_arm_6M;
13882 case TAG_CPU_ARCH_V6S_M:
13883 return bfd_mach_arm_6SM;
13884 case TAG_CPU_ARCH_V7E_M:
13885 return bfd_mach_arm_7EM;
13886 case TAG_CPU_ARCH_V8:
13887 return bfd_mach_arm_8;
13888 case TAG_CPU_ARCH_V8R:
13889 return bfd_mach_arm_8R;
13890 case TAG_CPU_ARCH_V8M_BASE:
13891 return bfd_mach_arm_8M_BASE;
13892 case TAG_CPU_ARCH_V8M_MAIN:
13893 return bfd_mach_arm_8M_MAIN;
031254f2
AV		 13894 case TAG_CPU_ARCH_V8_1M_MAIN:
13895 return bfd_mach_arm_8_1M_MAIN;
c0c468d5 13896
5968a7b8 13897 default:
c0c468d5
TP		 13898 /* Force entry to be added for any new known Tag_CPU_arch value. */
13899 BFD_ASSERT (arch > MAX_TAG_CPU_ARCH);
13900
13901 /* Unknown Tag_CPU_arch value. */
5968a7b8
NC		 13902 return bfd_mach_arm_unknown;
13903 }
13904}
13905
c178919b
NC		 13906/* Set the right machine number. */
13907
13908static bfd_boolean
57e8b36a 13909elf32_arm_object_p (bfd *abfd)
c178919b 13910{
5a6c6817 13911 unsigned int mach;
57e8b36a 13912
5a6c6817 13913 mach = bfd_arm_get_mach_from_notes (abfd, ARM_NOTE_SECTION);
c178919b 13914
5968a7b8
NC		 13915 if (mach == bfd_mach_arm_unknown)
13916 {
13917 if (elf_elfheader (abfd)->e_flags & EF_ARM_MAVERICK_FLOAT)
13918 mach = bfd_mach_arm_ep9312;
13919 else
13920 mach = bfd_arm_get_mach_from_attributes (abfd);
13921 }
c178919b 13922
5968a7b8 13923 bfd_default_set_arch_mach (abfd, bfd_arch_arm, mach);
c178919b
NC		 13924 return TRUE;
13925}
13926
fc830a83 13927/* Function to keep ARM specific flags in the ELF header. */
3c9458e9 13928
b34976b6 13929static bfd_boolean
57e8b36a 13930elf32_arm_set_private_flags (bfd *abfd, flagword flags)
252b5132
RH		 13931{
13932 if (elf_flags_init (abfd)
13933 && elf_elfheader (abfd)->e_flags != flags)
13934 {
fc830a83
NC		 13935 if (EF_ARM_EABI_VERSION (flags) == EF_ARM_EABI_UNKNOWN)
13936 {
fd2ec330 13937 if (flags & EF_ARM_INTERWORK)
4eca0228 13938 _bfd_error_handler
90b6238f 13939 (_("warning: not setting interworking flag of %pB since it has already been specified as non-interworking"),
d003868e 13940 abfd);
fc830a83 13941 else
d003868e 13942 _bfd_error_handler
90b6238f 13943 (_("warning: clearing the interworking flag of %pB due to outside request"),
d003868e 13944 abfd);
fc830a83 13945 }
252b5132
RH		 13946 }
13947 else
13948 {
13949 elf_elfheader (abfd)->e_flags = flags;
b34976b6 13950 elf_flags_init (abfd) = TRUE;
252b5132
RH		 13951 }
13952
b34976b6 13953 return TRUE;
252b5132
RH		 13954}
13955
fc830a83 13956/* Copy backend specific data from one object module to another. */
9b485d32 13957
b34976b6 13958static bfd_boolean
57e8b36a 13959elf32_arm_copy_private_bfd_data (bfd *ibfd, bfd *obfd)
252b5132
RH		 13960{
13961 flagword in_flags;
13962 flagword out_flags;
13963
0ffa91dd 13964 if (! is_arm_elf (ibfd) || ! is_arm_elf (obfd))
b34976b6 13965 return TRUE;
252b5132 13966
fc830a83 13967 in_flags = elf_elfheader (ibfd)->e_flags;
252b5132
RH		 13968 out_flags = elf_elfheader (obfd)->e_flags;
13969
fc830a83
NC		 13970 if (elf_flags_init (obfd)
13971 && EF_ARM_EABI_VERSION (out_flags) == EF_ARM_EABI_UNKNOWN
13972 && in_flags != out_flags)
252b5132 13973 {
252b5132 13974 /* Cannot mix APCS26 and APCS32 code. */
fd2ec330 13975 if ((in_flags & EF_ARM_APCS_26) != (out_flags & EF_ARM_APCS_26))
b34976b6 13976 return FALSE;
252b5132
RH		 13977
13978 /* Cannot mix float APCS and non-float APCS code. */
fd2ec330 13979 if ((in_flags & EF_ARM_APCS_FLOAT) != (out_flags & EF_ARM_APCS_FLOAT))
b34976b6 13980 return FALSE;
252b5132
RH		 13981
13982 /* If the src and dest have different interworking flags
99059e56 13983 then turn off the interworking bit. */
fd2ec330 13984 if ((in_flags & EF_ARM_INTERWORK) != (out_flags & EF_ARM_INTERWORK))
252b5132 13985 {
fd2ec330 13986 if (out_flags & EF_ARM_INTERWORK)
d003868e 13987 _bfd_error_handler
90b6238f 13988 (_("warning: clearing the interworking flag of %pB because non-interworking code in %pB has been linked with it"),
d003868e 13989 obfd, ibfd);
252b5132 13990
fd2ec330 13991 in_flags &= ~EF_ARM_INTERWORK;
252b5132 13992 }
1006ba19
PB		 13993
13994 /* Likewise for PIC, though don't warn for this case. */
fd2ec330
PB		 13995 if ((in_flags & EF_ARM_PIC) != (out_flags & EF_ARM_PIC))
13996 in_flags &= ~EF_ARM_PIC;
252b5132
RH		 13997 }
13998
13999 elf_elfheader (obfd)->e_flags = in_flags;
b34976b6 14000 elf_flags_init (obfd) = TRUE;
252b5132 14001
e2349352 14002 return _bfd_elf_copy_private_bfd_data (ibfd, obfd);
ee065d83
PB		 14003}
14004
14005/* Values for Tag_ABI_PCS_R9_use. */
14006enum
14007{
14008 AEABI_R9_V6,
14009 AEABI_R9_SB,
14010 AEABI_R9_TLS,
14011 AEABI_R9_unused
14012};
14013
14014/* Values for Tag_ABI_PCS_RW_data. */
14015enum
14016{
14017 AEABI_PCS_RW_data_absolute,
14018 AEABI_PCS_RW_data_PCrel,
14019 AEABI_PCS_RW_data_SBrel,
14020 AEABI_PCS_RW_data_unused
14021};
14022
14023/* Values for Tag_ABI_enum_size. */
14024enum
14025{
14026 AEABI_enum_unused,
14027 AEABI_enum_short,
14028 AEABI_enum_wide,
14029 AEABI_enum_forced_wide
14030};
14031
104d59d1
JM		 14032/* Determine whether an object attribute tag takes an integer, a
14033 string or both. */
906e58ca 14034
104d59d1
JM		 14035static int
14036elf32_arm_obj_attrs_arg_type (int tag)
14037{
14038 if (tag == Tag_compatibility)
3483fe2e 14039 return ATTR_TYPE_FLAG_INT_VAL | ATTR_TYPE_FLAG_STR_VAL;
2d0bb761 14040 else if (tag == Tag_nodefaults)
3483fe2e
AS		 14041 return ATTR_TYPE_FLAG_INT_VAL | ATTR_TYPE_FLAG_NO_DEFAULT;
14042 else if (tag == Tag_CPU_raw_name || tag == Tag_CPU_name)
14043 return ATTR_TYPE_FLAG_STR_VAL;
104d59d1 14044 else if (tag < 32)
3483fe2e 14045 return ATTR_TYPE_FLAG_INT_VAL;
104d59d1 14046 else
3483fe2e 14047 return (tag & 1) != 0 ? ATTR_TYPE_FLAG_STR_VAL : ATTR_TYPE_FLAG_INT_VAL;
104d59d1
JM		 14048}
14049
5aa6ff7c
AS		 14050/* The ABI defines that Tag_conformance should be emitted first, and that
14051 Tag_nodefaults should be second (if either is defined). This sets those
14052 two positions, and bumps up the position of all the remaining tags to
14053 compensate. */
14054static int
14055elf32_arm_obj_attrs_order (int num)
14056{
3de4a297 14057 if (num == LEAST_KNOWN_OBJ_ATTRIBUTE)
5aa6ff7c 14058 return Tag_conformance;
3de4a297 14059 if (num == LEAST_KNOWN_OBJ_ATTRIBUTE + 1)
5aa6ff7c
AS		 14060 return Tag_nodefaults;
14061 if ((num - 2) < Tag_nodefaults)
14062 return num - 2;
14063 if ((num - 1) < Tag_conformance)
14064 return num - 1;
14065 return num;
14066}
14067
e8b36cd1
JM		 14068/* Attribute numbers >=64 (mod 128) can be safely ignored. */
14069static bfd_boolean
14070elf32_arm_obj_attrs_handle_unknown (bfd *abfd, int tag)
14071{
14072 if ((tag & 127) < 64)
14073 {
14074 _bfd_error_handler
90b6238f 14075 (_("%pB: unknown mandatory EABI object attribute %d"),
e8b36cd1
JM		 14076 abfd, tag);
14077 bfd_set_error (bfd_error_bad_value);
14078 return FALSE;
14079 }
14080 else
14081 {
14082 _bfd_error_handler
90b6238f 14083 (_("warning: %pB: unknown EABI object attribute %d"),
e8b36cd1
JM		 14084 abfd, tag);
14085 return TRUE;
14086 }
14087}
14088
91e22acd
AS		 14089/* Read the architecture from the Tag_also_compatible_with attribute, if any.
14090 Returns -1 if no architecture could be read. */
14091
14092static int
14093get_secondary_compatible_arch (bfd *abfd)
14094{
14095 obj_attribute *attr =
14096 &elf_known_obj_attributes_proc (abfd)[Tag_also_compatible_with];
14097
14098 /* Note: the tag and its argument below are uleb128 values, though
14099 currently-defined values fit in one byte for each. */
14100 if (attr->s
14101 && attr->s[0] == Tag_CPU_arch
14102 && (attr->s[1] & 128) != 128
14103 && attr->s[2] == 0)
14104 return attr->s[1];
14105
14106 /* This tag is "safely ignorable", so don't complain if it looks funny. */
14107 return -1;
14108}
14109
14110/* Set, or unset, the architecture of the Tag_also_compatible_with attribute.
14111 The tag is removed if ARCH is -1. */
14112
8e79c3df 14113static void
91e22acd 14114set_secondary_compatible_arch (bfd *abfd, int arch)
8e79c3df 14115{
91e22acd
AS		 14116 obj_attribute *attr =
14117 &elf_known_obj_attributes_proc (abfd)[Tag_also_compatible_with];
8e79c3df 14118
91e22acd
AS		 14119 if (arch == -1)
14120 {
14121 attr->s = NULL;
14122 return;
8e79c3df 14123 }
91e22acd
AS		 14124
14125 /* Note: the tag and its argument below are uleb128 values, though
14126 currently-defined values fit in one byte for each. */
14127 if (!attr->s)
21d799b5 14128 attr->s = (char *) bfd_alloc (abfd, 3);
91e22acd
AS		 14129 attr->s[0] = Tag_CPU_arch;
14130 attr->s[1] = arch;
14131 attr->s[2] = '\0';
8e79c3df
CM		 14132}
14133
91e22acd
AS		 14134/* Combine two values for Tag_CPU_arch, taking secondary compatibility tags
14135 into account. */
14136
14137static int
14138tag_cpu_arch_combine (bfd *ibfd, int oldtag, int *secondary_compat_out,
14139 int newtag, int secondary_compat)
8e79c3df 14140{
91e22acd
AS		 14141#define T(X) TAG_CPU_ARCH_##X
14142 int tagl, tagh, result;
14143 const int v6t2[] =
14144 {
14145 T(V6T2), /* PRE_V4. */
14146 T(V6T2), /* V4. */
14147 T(V6T2), /* V4T. */
14148 T(V6T2), /* V5T. */
14149 T(V6T2), /* V5TE. */
14150 T(V6T2), /* V5TEJ. */
14151 T(V6T2), /* V6. */
14152 T(V7), /* V6KZ. */
14153 T(V6T2) /* V6T2. */
14154 };
14155 const int v6k[] =
14156 {
14157 T(V6K), /* PRE_V4. */
14158 T(V6K), /* V4. */
14159 T(V6K), /* V4T. */
14160 T(V6K), /* V5T. */
14161 T(V6K), /* V5TE. */
14162 T(V6K), /* V5TEJ. */
14163 T(V6K), /* V6. */
14164 T(V6KZ), /* V6KZ. */
14165 T(V7), /* V6T2. */
14166 T(V6K) /* V6K. */
14167 };
14168 const int v7[] =
14169 {
14170 T(V7), /* PRE_V4. */
14171 T(V7), /* V4. */
14172 T(V7), /* V4T. */
14173 T(V7), /* V5T. */
14174 T(V7), /* V5TE. */
14175 T(V7), /* V5TEJ. */
14176 T(V7), /* V6. */
14177 T(V7), /* V6KZ. */
14178 T(V7), /* V6T2. */
14179 T(V7), /* V6K. */
14180 T(V7) /* V7. */
14181 };
14182 const int v6_m[] =
14183 {
07d6d2b8
AM		 14184 -1, /* PRE_V4. */
14185 -1, /* V4. */
91e22acd
AS		 14186 T(V6K), /* V4T. */
14187 T(V6K), /* V5T. */
14188 T(V6K), /* V5TE. */
14189 T(V6K), /* V5TEJ. */
14190 T(V6K), /* V6. */
14191 T(V6KZ), /* V6KZ. */
14192 T(V7), /* V6T2. */
14193 T(V6K), /* V6K. */
14194 T(V7), /* V7. */
14195 T(V6_M) /* V6_M. */
14196 };
14197 const int v6s_m[] =
14198 {
07d6d2b8
AM		 14199 -1, /* PRE_V4. */
14200 -1, /* V4. */
91e22acd
AS		 14201 T(V6K), /* V4T. */
14202 T(V6K), /* V5T. */
14203 T(V6K), /* V5TE. */
14204 T(V6K), /* V5TEJ. */
14205 T(V6K), /* V6. */
14206 T(V6KZ), /* V6KZ. */
14207 T(V7), /* V6T2. */
14208 T(V6K), /* V6K. */
14209 T(V7), /* V7. */
14210 T(V6S_M), /* V6_M. */
14211 T(V6S_M) /* V6S_M. */
14212 };
9e3c6df6
PB		 14213 const int v7e_m[] =
14214 {
07d6d2b8
AM		 14215 -1, /* PRE_V4. */
14216 -1, /* V4. */
9e3c6df6
PB		 14217 T(V7E_M), /* V4T. */
14218 T(V7E_M), /* V5T. */
14219 T(V7E_M), /* V5TE. */
14220 T(V7E_M), /* V5TEJ. */
14221 T(V7E_M), /* V6. */
14222 T(V7E_M), /* V6KZ. */
14223 T(V7E_M), /* V6T2. */
14224 T(V7E_M), /* V6K. */
14225 T(V7E_M), /* V7. */
14226 T(V7E_M), /* V6_M. */
14227 T(V7E_M), /* V6S_M. */
14228 T(V7E_M) /* V7E_M. */
14229 };
bca38921
MGD		 14230 const int v8[] =
14231 {
14232 T(V8), /* PRE_V4. */
14233 T(V8), /* V4. */
14234 T(V8), /* V4T. */
14235 T(V8), /* V5T. */
14236 T(V8), /* V5TE. */
14237 T(V8), /* V5TEJ. */
14238 T(V8), /* V6. */
14239 T(V8), /* V6KZ. */
14240 T(V8), /* V6T2. */
14241 T(V8), /* V6K. */
14242 T(V8), /* V7. */
14243 T(V8), /* V6_M. */
14244 T(V8), /* V6S_M. */
14245 T(V8), /* V7E_M. */
14246 T(V8) /* V8. */
14247 };
bff0500d
TP		 14248 const int v8r[] =
14249 {
14250 T(V8R), /* PRE_V4. */
14251 T(V8R), /* V4. */
14252 T(V8R), /* V4T. */
14253 T(V8R), /* V5T. */
14254 T(V8R), /* V5TE. */
14255 T(V8R), /* V5TEJ. */
14256 T(V8R), /* V6. */
14257 T(V8R), /* V6KZ. */
14258 T(V8R), /* V6T2. */
14259 T(V8R), /* V6K. */
14260 T(V8R), /* V7. */
14261 T(V8R), /* V6_M. */
14262 T(V8R), /* V6S_M. */
14263 T(V8R), /* V7E_M. */
14264 T(V8), /* V8. */
14265 T(V8R), /* V8R. */
14266 };
2fd158eb
TP		 14267 const int v8m_baseline[] =
14268 {
14269 -1, /* PRE_V4. */
14270 -1, /* V4. */
14271 -1, /* V4T. */
14272 -1, /* V5T. */
14273 -1, /* V5TE. */
14274 -1, /* V5TEJ. */
14275 -1, /* V6. */
14276 -1, /* V6KZ. */
14277 -1, /* V6T2. */
14278 -1, /* V6K. */
14279 -1, /* V7. */
14280 T(V8M_BASE), /* V6_M. */
14281 T(V8M_BASE), /* V6S_M. */
14282 -1, /* V7E_M. */
14283 -1, /* V8. */
bff0500d 14284 -1, /* V8R. */
2fd158eb
TP		 14285 T(V8M_BASE) /* V8-M BASELINE. */
14286 };
14287 const int v8m_mainline[] =
14288 {
14289 -1, /* PRE_V4. */
14290 -1, /* V4. */
14291 -1, /* V4T. */
14292 -1, /* V5T. */
14293 -1, /* V5TE. */
14294 -1, /* V5TEJ. */
14295 -1, /* V6. */
14296 -1, /* V6KZ. */
14297 -1, /* V6T2. */
14298 -1, /* V6K. */
14299 T(V8M_MAIN), /* V7. */
14300 T(V8M_MAIN), /* V6_M. */
14301 T(V8M_MAIN), /* V6S_M. */
14302 T(V8M_MAIN), /* V7E_M. */
14303 -1, /* V8. */
bff0500d 14304 -1, /* V8R. */
2fd158eb
TP		 14305 T(V8M_MAIN), /* V8-M BASELINE. */
14306 T(V8M_MAIN) /* V8-M MAINLINE. */
14307 };
031254f2
AV		 14308 const int v8_1m_mainline[] =
14309 {
14310 -1, /* PRE_V4. */
14311 -1, /* V4. */
14312 -1, /* V4T. */
14313 -1, /* V5T. */
14314 -1, /* V5TE. */
14315 -1, /* V5TEJ. */
14316 -1, /* V6. */
14317 -1, /* V6KZ. */
14318 -1, /* V6T2. */
14319 -1, /* V6K. */
14320 T(V8_1M_MAIN), /* V7. */
14321 T(V8_1M_MAIN), /* V6_M. */
14322 T(V8_1M_MAIN), /* V6S_M. */
14323 T(V8_1M_MAIN), /* V7E_M. */
14324 -1, /* V8. */
14325 -1, /* V8R. */
14326 T(V8_1M_MAIN), /* V8-M BASELINE. */
14327 T(V8_1M_MAIN), /* V8-M MAINLINE. */
14328 -1, /* Unused (18). */
14329 -1, /* Unused (19). */
14330 -1, /* Unused (20). */
14331 T(V8_1M_MAIN) /* V8.1-M MAINLINE. */
14332 };
91e22acd
AS		 14333 const int v4t_plus_v6_m[] =
14334 {
14335 -1, /* PRE_V4. */
14336 -1, /* V4. */
14337 T(V4T), /* V4T. */
14338 T(V5T), /* V5T. */
14339 T(V5TE), /* V5TE. */
14340 T(V5TEJ), /* V5TEJ. */
14341 T(V6), /* V6. */
14342 T(V6KZ), /* V6KZ. */
14343 T(V6T2), /* V6T2. */
14344 T(V6K), /* V6K. */
14345 T(V7), /* V7. */
14346 T(V6_M), /* V6_M. */
14347 T(V6S_M), /* V6S_M. */
9e3c6df6 14348 T(V7E_M), /* V7E_M. */
bca38921 14349 T(V8), /* V8. */
bff0500d 14350 -1, /* V8R. */
2fd158eb
TP		 14351 T(V8M_BASE), /* V8-M BASELINE. */
14352 T(V8M_MAIN), /* V8-M MAINLINE. */
031254f2
AV		 14353 -1, /* Unused (18). */
14354 -1, /* Unused (19). */
14355 -1, /* Unused (20). */
14356 T(V8_1M_MAIN), /* V8.1-M MAINLINE. */
91e22acd
AS		 14357 T(V4T_PLUS_V6_M) /* V4T plus V6_M. */
14358 };
14359 const int *comb[] =
14360 {
14361 v6t2,
14362 v6k,
14363 v7,
14364 v6_m,
14365 v6s_m,
9e3c6df6 14366 v7e_m,
bca38921 14367 v8,
bff0500d 14368 v8r,
2fd158eb
TP		 14369 v8m_baseline,
14370 v8m_mainline,
031254f2
AV		 14371 NULL,
14372 NULL,
14373 NULL,
14374 v8_1m_mainline,
91e22acd
AS		 14375 /* Pseudo-architecture. */
14376 v4t_plus_v6_m
14377 };
14378
14379 /* Check we've not got a higher architecture than we know about. */
14380
9e3c6df6 14381 if (oldtag > MAX_TAG_CPU_ARCH || newtag > MAX_TAG_CPU_ARCH)
91e22acd 14382 {
90b6238f 14383 _bfd_error_handler (_("error: %pB: unknown CPU architecture"), ibfd);
91e22acd
AS		 14384 return -1;
14385 }
14386
14387 /* Override old tag if we have a Tag_also_compatible_with on the output. */
14388
14389 if ((oldtag == T(V6_M) && *secondary_compat_out == T(V4T))
14390 || (oldtag == T(V4T) && *secondary_compat_out == T(V6_M)))
14391 oldtag = T(V4T_PLUS_V6_M);
14392
14393 /* And override the new tag if we have a Tag_also_compatible_with on the
14394 input. */
14395
14396 if ((newtag == T(V6_M) && secondary_compat == T(V4T))
14397 || (newtag == T(V4T) && secondary_compat == T(V6_M)))
14398 newtag = T(V4T_PLUS_V6_M);
14399
14400 tagl = (oldtag < newtag) ? oldtag : newtag;
14401 result = tagh = (oldtag > newtag) ? oldtag : newtag;
14402
14403 /* Architectures before V6KZ add features monotonically. */
14404 if (tagh <= TAG_CPU_ARCH_V6KZ)
14405 return result;
14406
4ed7ed8d 14407 result = comb[tagh - T(V6T2)] ? comb[tagh - T(V6T2)][tagl] : -1;
91e22acd
AS		 14408
14409 /* Use Tag_CPU_arch == V4T and Tag_also_compatible_with (Tag_CPU_arch V6_M)
14410 as the canonical version. */
14411 if (result == T(V4T_PLUS_V6_M))
14412 {
14413 result = T(V4T);
14414 *secondary_compat_out = T(V6_M);
14415 }
14416 else
14417 *secondary_compat_out = -1;
14418
14419 if (result == -1)
14420 {
90b6238f 14421 _bfd_error_handler (_("error: %pB: conflicting CPU architectures %d/%d"),
91e22acd
AS		 14422 ibfd, oldtag, newtag);
14423 return -1;
14424 }
14425
14426 return result;
14427#undef T
8e79c3df
CM		 14428}
14429
ac56ee8f
MGD		 14430/* Query attributes object to see if integer divide instructions may be
14431 present in an object. */
14432static bfd_boolean
14433elf32_arm_attributes_accept_div (const obj_attribute *attr)
14434{
14435 int arch = attr[Tag_CPU_arch].i;
14436 int profile = attr[Tag_CPU_arch_profile].i;
14437
14438 switch (attr[Tag_DIV_use].i)
14439 {
14440 case 0:
14441 /* Integer divide allowed if instruction contained in archetecture. */
14442 if (arch == TAG_CPU_ARCH_V7 && (profile == 'R' || profile == 'M'))
14443 return TRUE;
14444 else if (arch >= TAG_CPU_ARCH_V7E_M)
14445 return TRUE;
14446 else
14447 return FALSE;
14448
14449 case 1:
14450 /* Integer divide explicitly prohibited. */
14451 return FALSE;
14452
14453 default:
14454 /* Unrecognised case - treat as allowing divide everywhere. */
14455 case 2:
14456 /* Integer divide allowed in ARM state. */
14457 return TRUE;
14458 }
14459}
14460
14461/* Query attributes object to see if integer divide instructions are
14462 forbidden to be in the object. This is not the inverse of
14463 elf32_arm_attributes_accept_div. */
14464static bfd_boolean
14465elf32_arm_attributes_forbid_div (const obj_attribute *attr)
14466{
14467 return attr[Tag_DIV_use].i == 1;
14468}
14469
ee065d83
PB		 14470/* Merge EABI object attributes from IBFD into OBFD. Raise an error if there
14471 are conflicting attributes. */
906e58ca 14472
ee065d83 14473static bfd_boolean
50e03d47 14474elf32_arm_merge_eabi_attributes (bfd *ibfd, struct bfd_link_info *info)
ee065d83 14475{
50e03d47 14476 bfd *obfd = info->output_bfd;
104d59d1
JM		 14477 obj_attribute *in_attr;
14478 obj_attribute *out_attr;
ee065d83
PB		 14479 /* Some tags have 0 = don't care, 1 = strong requirement,
14480 2 = weak requirement. */
91e22acd 14481 static const int order_021[3] = {0, 2, 1};
ee065d83 14482 int i;
91e22acd 14483 bfd_boolean result = TRUE;
9274e9de 14484 const char *sec_name = get_elf_backend_data (ibfd)->obj_attrs_section;
ee065d83 14485
3e6b1042
DJ		 14486 /* Skip the linker stubs file. This preserves previous behavior
14487 of accepting unknown attributes in the first input file - but
14488 is that a bug? */
14489 if (ibfd->flags & BFD_LINKER_CREATED)
14490 return TRUE;
14491
9274e9de
TG		 14492 /* Skip any input that hasn't attribute section.
14493 This enables to link object files without attribute section with
14494 any others. */
14495 if (bfd_get_section_by_name (ibfd, sec_name) == NULL)
14496 return TRUE;
14497
104d59d1 14498 if (!elf_known_obj_attributes_proc (obfd)[0].i)
ee065d83
PB		 14499 {
14500 /* This is the first object. Copy the attributes. */
104d59d1 14501 _bfd_elf_copy_obj_attributes (ibfd, obfd);
004ae526 14502
cd21e546
MGD		 14503 out_attr = elf_known_obj_attributes_proc (obfd);
14504
004ae526
PB		 14505 /* Use the Tag_null value to indicate the attributes have been
14506 initialized. */
cd21e546 14507 out_attr[0].i = 1;
004ae526 14508
cd21e546
MGD		 14509 /* We do not output objects with Tag_MPextension_use_legacy - we move
14510 the attribute's value to Tag_MPextension_use. */
14511 if (out_attr[Tag_MPextension_use_legacy].i != 0)
14512 {
14513 if (out_attr[Tag_MPextension_use].i != 0
14514 && out_attr[Tag_MPextension_use_legacy].i
99059e56 14515 != out_attr[Tag_MPextension_use].i)
cd21e546
MGD		 14516 {
14517 _bfd_error_handler
871b3ab2 14518 (_("Error: %pB has both the current and legacy "
cd21e546
MGD		 14519 "Tag_MPextension_use attributes"), ibfd);
14520 result = FALSE;
14521 }
14522
14523 out_attr[Tag_MPextension_use] =
14524 out_attr[Tag_MPextension_use_legacy];
14525 out_attr[Tag_MPextension_use_legacy].type = 0;
14526 out_attr[Tag_MPextension_use_legacy].i = 0;
14527 }
14528
14529 return result;
ee065d83
PB		 14530 }
14531
104d59d1
JM		 14532 in_attr = elf_known_obj_attributes_proc (ibfd);
14533 out_attr = elf_known_obj_attributes_proc (obfd);
ee065d83
PB		 14534 /* This needs to happen before Tag_ABI_FP_number_model is merged. */
14535 if (in_attr[Tag_ABI_VFP_args].i != out_attr[Tag_ABI_VFP_args].i)
14536 {
5c294fee
TG		 14537 /* Ignore mismatches if the object doesn't use floating point or is
14538 floating point ABI independent. */
14539 if (out_attr[Tag_ABI_FP_number_model].i == AEABI_FP_number_model_none
14540 || (in_attr[Tag_ABI_FP_number_model].i != AEABI_FP_number_model_none
14541 && out_attr[Tag_ABI_VFP_args].i == AEABI_VFP_args_compatible))
ee065d83 14542 out_attr[Tag_ABI_VFP_args].i = in_attr[Tag_ABI_VFP_args].i;
5c294fee
TG		 14543 else if (in_attr[Tag_ABI_FP_number_model].i != AEABI_FP_number_model_none
14544 && in_attr[Tag_ABI_VFP_args].i != AEABI_VFP_args_compatible)
ee065d83
PB		 14545 {
14546 _bfd_error_handler
871b3ab2 14547 (_("error: %pB uses VFP register arguments, %pB does not"),
deddc40b
NS		 14548 in_attr[Tag_ABI_VFP_args].i ? ibfd : obfd,
14549 in_attr[Tag_ABI_VFP_args].i ? obfd : ibfd);
91e22acd 14550 result = FALSE;
ee065d83
PB		 14551 }
14552 }
14553
3de4a297 14554 for (i = LEAST_KNOWN_OBJ_ATTRIBUTE; i < NUM_KNOWN_OBJ_ATTRIBUTES; i++)
ee065d83
PB		 14555 {
14556 /* Merge this attribute with existing attributes. */
14557 switch (i)
14558 {
14559 case Tag_CPU_raw_name:
14560 case Tag_CPU_name:
6a631e86 14561 /* These are merged after Tag_CPU_arch. */
ee065d83
PB		 14562 break;
14563
14564 case Tag_ABI_optimization_goals:
14565 case Tag_ABI_FP_optimization_goals:
14566 /* Use the first value seen. */
14567 break;
14568
14569 case Tag_CPU_arch:
91e22acd
AS		 14570 {
14571 int secondary_compat = -1, secondary_compat_out = -1;
14572 unsigned int saved_out_attr = out_attr[i].i;
70e99720
TG		 14573 int arch_attr;
14574 static const char *name_table[] =
14575 {
91e22acd
AS		 14576 /* These aren't real CPU names, but we can't guess
14577 that from the architecture version alone. */
14578 "Pre v4",
14579 "ARM v4",
14580 "ARM v4T",
14581 "ARM v5T",
14582 "ARM v5TE",
14583 "ARM v5TEJ",
14584 "ARM v6",
14585 "ARM v6KZ",
14586 "ARM v6T2",
14587 "ARM v6K",
14588 "ARM v7",
14589 "ARM v6-M",
bca38921 14590 "ARM v6S-M",
2fd158eb
TP		 14591 "ARM v8",
14592 "",
14593 "ARM v8-M.baseline",
14594 "ARM v8-M.mainline",
91e22acd
AS		 14595 };
14596
14597 /* Merge Tag_CPU_arch and Tag_also_compatible_with. */
14598 secondary_compat = get_secondary_compatible_arch (ibfd);
14599 secondary_compat_out = get_secondary_compatible_arch (obfd);
70e99720
TG		 14600 arch_attr = tag_cpu_arch_combine (ibfd, out_attr[i].i,
14601 &secondary_compat_out,
14602 in_attr[i].i,
14603 secondary_compat);
14604
14605 /* Return with error if failed to merge. */
14606 if (arch_attr == -1)
14607 return FALSE;
14608
14609 out_attr[i].i = arch_attr;
14610
91e22acd
AS		 14611 set_secondary_compatible_arch (obfd, secondary_compat_out);
14612
14613 /* Merge Tag_CPU_name and Tag_CPU_raw_name. */
14614 if (out_attr[i].i == saved_out_attr)
14615 ; /* Leave the names alone. */
14616 else if (out_attr[i].i == in_attr[i].i)
14617 {
14618 /* The output architecture has been changed to match the
14619 input architecture. Use the input names. */
14620 out_attr[Tag_CPU_name].s = in_attr[Tag_CPU_name].s
14621 ? _bfd_elf_attr_strdup (obfd, in_attr[Tag_CPU_name].s)
14622 : NULL;
14623 out_attr[Tag_CPU_raw_name].s = in_attr[Tag_CPU_raw_name].s
14624 ? _bfd_elf_attr_strdup (obfd, in_attr[Tag_CPU_raw_name].s)
14625 : NULL;
14626 }
14627 else
14628 {
14629 out_attr[Tag_CPU_name].s = NULL;
14630 out_attr[Tag_CPU_raw_name].s = NULL;
14631 }
14632
14633 /* If we still don't have a value for Tag_CPU_name,
14634 make one up now. Tag_CPU_raw_name remains blank. */
14635 if (out_attr[Tag_CPU_name].s == NULL
14636 && out_attr[i].i < ARRAY_SIZE (name_table))
14637 out_attr[Tag_CPU_name].s =
14638 _bfd_elf_attr_strdup (obfd, name_table[out_attr[i].i]);
14639 }
14640 break;
14641
ee065d83
PB		 14642 case Tag_ARM_ISA_use:
14643 case Tag_THUMB_ISA_use:
ee065d83 14644 case Tag_WMMX_arch:
91e22acd
AS		 14645 case Tag_Advanced_SIMD_arch:
14646 /* ??? Do Advanced_SIMD (NEON) and WMMX conflict? */
ee065d83 14647 case Tag_ABI_FP_rounding:
ee065d83
PB		 14648 case Tag_ABI_FP_exceptions:
14649 case Tag_ABI_FP_user_exceptions:
14650 case Tag_ABI_FP_number_model:
75375b3e 14651 case Tag_FP_HP_extension:
91e22acd
AS		 14652 case Tag_CPU_unaligned_access:
14653 case Tag_T2EE_use:
91e22acd 14654 case Tag_MPextension_use:
a7ad558c 14655 case Tag_MVE_arch:
ee065d83
PB		 14656 /* Use the largest value specified. */
14657 if (in_attr[i].i > out_attr[i].i)
14658 out_attr[i].i = in_attr[i].i;
14659 break;
14660
75375b3e 14661 case Tag_ABI_align_preserved:
91e22acd
AS		 14662 case Tag_ABI_PCS_RO_data:
14663 /* Use the smallest value specified. */
14664 if (in_attr[i].i < out_attr[i].i)
14665 out_attr[i].i = in_attr[i].i;
14666 break;
14667
75375b3e 14668 case Tag_ABI_align_needed:
91e22acd 14669 if ((in_attr[i].i > 0 || out_attr[i].i > 0)
75375b3e
MGD		 14670 && (in_attr[Tag_ABI_align_preserved].i == 0
14671 || out_attr[Tag_ABI_align_preserved].i == 0))
ee065d83 14672 {
91e22acd
AS		 14673 /* This error message should be enabled once all non-conformant
14674 binaries in the toolchain have had the attributes set
14675 properly.
ee065d83 14676 _bfd_error_handler
871b3ab2 14677 (_("error: %pB: 8-byte data alignment conflicts with %pB"),
91e22acd
AS		 14678 obfd, ibfd);
14679 result = FALSE; */
ee065d83 14680 }
91e22acd
AS		 14681 /* Fall through. */
14682 case Tag_ABI_FP_denormal:
14683 case Tag_ABI_PCS_GOT_use:
14684 /* Use the "greatest" from the sequence 0, 2, 1, or the largest
14685 value if greater than 2 (for future-proofing). */
14686 if ((in_attr[i].i > 2 && in_attr[i].i > out_attr[i].i)
14687 || (in_attr[i].i <= 2 && out_attr[i].i <= 2
14688 && order_021[in_attr[i].i] > order_021[out_attr[i].i]))
ee065d83
PB		 14689 out_attr[i].i = in_attr[i].i;
14690 break;
91e22acd 14691
75375b3e
MGD		 14692 case Tag_Virtualization_use:
14693 /* The virtualization tag effectively stores two bits of
14694 information: the intended use of TrustZone (in bit 0), and the
14695 intended use of Virtualization (in bit 1). */
14696 if (out_attr[i].i == 0)
14697 out_attr[i].i = in_attr[i].i;
14698 else if (in_attr[i].i != 0
14699 && in_attr[i].i != out_attr[i].i)
14700 {
14701 if (in_attr[i].i <= 3 && out_attr[i].i <= 3)
14702 out_attr[i].i = 3;
14703 else
14704 {
14705 _bfd_error_handler
871b3ab2
AM		 14706 (_("error: %pB: unable to merge virtualization attributes "
14707 "with %pB"),
75375b3e
MGD		 14708 obfd, ibfd);
14709 result = FALSE;
14710 }
14711 }
14712 break;
91e22acd
AS		 14713
14714 case Tag_CPU_arch_profile:
14715 if (out_attr[i].i != in_attr[i].i)
14716 {
14717 /* 0 will merge with anything.
14718 'A' and 'S' merge to 'A'.
14719 'R' and 'S' merge to 'R'.
99059e56 14720 'M' and 'A|R|S' is an error. */
91e22acd
AS		 14721 if (out_attr[i].i == 0
14722 || (out_attr[i].i == 'S'
14723 && (in_attr[i].i == 'A' || in_attr[i].i == 'R')))
14724 out_attr[i].i = in_attr[i].i;
14725 else if (in_attr[i].i == 0
14726 || (in_attr[i].i == 'S'
14727 && (out_attr[i].i == 'A' || out_attr[i].i == 'R')))
6a631e86 14728 ; /* Do nothing. */
91e22acd
AS		 14729 else
14730 {
14731 _bfd_error_handler
90b6238f 14732 (_("error: %pB: conflicting architecture profiles %c/%c"),
91e22acd
AS		 14733 ibfd,
14734 in_attr[i].i ? in_attr[i].i : '0',
14735 out_attr[i].i ? out_attr[i].i : '0');
14736 result = FALSE;
14737 }
14738 }
14739 break;
15afaa63
TP		 14740
14741 case Tag_DSP_extension:
14742 /* No need to change output value if any of:
14743 - pre (<=) ARMv5T input architecture (do not have DSP)
14744 - M input profile not ARMv7E-M and do not have DSP. */
14745 if (in_attr[Tag_CPU_arch].i <= 3
14746 || (in_attr[Tag_CPU_arch_profile].i == 'M'
14747 && in_attr[Tag_CPU_arch].i != 13
14748 && in_attr[i].i == 0))
14749 ; /* Do nothing. */
14750 /* Output value should be 0 if DSP part of architecture, ie.
14751 - post (>=) ARMv5te architecture output
14752 - A, R or S profile output or ARMv7E-M output architecture. */
14753 else if (out_attr[Tag_CPU_arch].i >= 4
14754 && (out_attr[Tag_CPU_arch_profile].i == 'A'
14755 || out_attr[Tag_CPU_arch_profile].i == 'R'
14756 || out_attr[Tag_CPU_arch_profile].i == 'S'
14757 || out_attr[Tag_CPU_arch].i == 13))
14758 out_attr[i].i = 0;
14759 /* Otherwise, DSP instructions are added and not part of output
14760 architecture. */
14761 else
14762 out_attr[i].i = 1;
14763 break;
14764
75375b3e 14765 case Tag_FP_arch:
62f3b8c8 14766 {
4547cb56
NC		 14767 /* Tag_ABI_HardFP_use is handled along with Tag_FP_arch since
14768 the meaning of Tag_ABI_HardFP_use depends on Tag_FP_arch
14769 when it's 0. It might mean absence of FP hardware if
99654aaf 14770 Tag_FP_arch is zero. */
4547cb56 14771
a715796b 14772#define VFP_VERSION_COUNT 9
62f3b8c8
PB		 14773 static const struct
14774 {
14775 int ver;
14776 int regs;
bca38921 14777 } vfp_versions[VFP_VERSION_COUNT] =
62f3b8c8
PB		 14778 {
14779 {0, 0},
14780 {1, 16},
14781 {2, 16},
14782 {3, 32},
14783 {3, 16},
14784 {4, 32},
bca38921 14785 {4, 16},
a715796b
TG		 14786 {8, 32},
14787 {8, 16}
62f3b8c8
PB		 14788 };
14789 int ver;
14790 int regs;
14791 int newval;
14792
4547cb56
NC		 14793 /* If the output has no requirement about FP hardware,
14794 follow the requirement of the input. */
14795 if (out_attr[i].i == 0)
14796 {
4ec192e6
RE		 14797 /* This assert is still reasonable, we shouldn't
14798 produce the suspicious build attribute
14799 combination (See below for in_attr). */
4547cb56
NC		 14800 BFD_ASSERT (out_attr[Tag_ABI_HardFP_use].i == 0);
14801 out_attr[i].i = in_attr[i].i;
14802 out_attr[Tag_ABI_HardFP_use].i
14803 = in_attr[Tag_ABI_HardFP_use].i;
14804 break;
14805 }
14806 /* If the input has no requirement about FP hardware, do
14807 nothing. */
14808 else if (in_attr[i].i == 0)
14809 {
4ec192e6
RE		 14810 /* We used to assert that Tag_ABI_HardFP_use was
14811 zero here, but we should never assert when
14812 consuming an object file that has suspicious
14813 build attributes. The single precision variant
14814 of 'no FP architecture' is still 'no FP
14815 architecture', so we just ignore the tag in this
14816 case. */
4547cb56
NC		 14817 break;
14818 }
14819
14820 /* Both the input and the output have nonzero Tag_FP_arch.
99654aaf 14821 So Tag_ABI_HardFP_use is implied by Tag_FP_arch when it's zero. */
4547cb56
NC		 14822
14823 /* If both the input and the output have zero Tag_ABI_HardFP_use,
14824 do nothing. */
14825 if (in_attr[Tag_ABI_HardFP_use].i == 0
14826 && out_attr[Tag_ABI_HardFP_use].i == 0)
14827 ;
14828 /* If the input and the output have different Tag_ABI_HardFP_use,
99654aaf 14829 the combination of them is 0 (implied by Tag_FP_arch). */
4547cb56
NC		 14830 else if (in_attr[Tag_ABI_HardFP_use].i
14831 != out_attr[Tag_ABI_HardFP_use].i)
99654aaf 14832 out_attr[Tag_ABI_HardFP_use].i = 0;
4547cb56
NC		 14833
14834 /* Now we can handle Tag_FP_arch. */
14835
bca38921
MGD		 14836 /* Values of VFP_VERSION_COUNT or more aren't defined, so just
14837 pick the biggest. */
14838 if (in_attr[i].i >= VFP_VERSION_COUNT
14839 && in_attr[i].i > out_attr[i].i)
62f3b8c8
PB		 14840 {
14841 out_attr[i] = in_attr[i];
14842 break;
14843 }
14844 /* The output uses the superset of input features
14845 (ISA version) and registers. */
14846 ver = vfp_versions[in_attr[i].i].ver;
14847 if (ver < vfp_versions[out_attr[i].i].ver)
14848 ver = vfp_versions[out_attr[i].i].ver;
14849 regs = vfp_versions[in_attr[i].i].regs;
14850 if (regs < vfp_versions[out_attr[i].i].regs)
14851 regs = vfp_versions[out_attr[i].i].regs;
14852 /* This assumes all possible supersets are also a valid
99059e56 14853 options. */
bca38921 14854 for (newval = VFP_VERSION_COUNT - 1; newval > 0; newval--)
62f3b8c8
PB		 14855 {
14856 if (regs == vfp_versions[newval].regs
14857 && ver == vfp_versions[newval].ver)
14858 break;
14859 }
14860 out_attr[i].i = newval;
14861 }
b1cc4aeb 14862 break;
ee065d83
PB		 14863 case Tag_PCS_config:
14864 if (out_attr[i].i == 0)
14865 out_attr[i].i = in_attr[i].i;
b6009aca 14866 else if (in_attr[i].i != 0 && out_attr[i].i != in_attr[i].i)
ee065d83
PB		 14867 {
14868 /* It's sometimes ok to mix different configs, so this is only
99059e56 14869 a warning. */
ee065d83 14870 _bfd_error_handler
90b6238f 14871 (_("warning: %pB: conflicting platform configuration"), ibfd);
ee065d83
PB		 14872 }
14873 break;
14874 case Tag_ABI_PCS_R9_use:
004ae526
PB		 14875 if (in_attr[i].i != out_attr[i].i
14876 && out_attr[i].i != AEABI_R9_unused
ee065d83
PB		 14877 && in_attr[i].i != AEABI_R9_unused)
14878 {
14879 _bfd_error_handler
90b6238f 14880 (_("error: %pB: conflicting use of R9"), ibfd);
91e22acd 14881 result = FALSE;
ee065d83
PB		 14882 }
14883 if (out_attr[i].i == AEABI_R9_unused)
14884 out_attr[i].i = in_attr[i].i;
14885 break;
14886 case Tag_ABI_PCS_RW_data:
14887 if (in_attr[i].i == AEABI_PCS_RW_data_SBrel
14888 && out_attr[Tag_ABI_PCS_R9_use].i != AEABI_R9_SB
14889 && out_attr[Tag_ABI_PCS_R9_use].i != AEABI_R9_unused)
14890 {
14891 _bfd_error_handler
871b3ab2 14892 (_("error: %pB: SB relative addressing conflicts with use of R9"),
ee065d83 14893 ibfd);
91e22acd 14894 result = FALSE;
ee065d83
PB		 14895 }
14896 /* Use the smallest value specified. */
14897 if (in_attr[i].i < out_attr[i].i)
14898 out_attr[i].i = in_attr[i].i;
14899 break;
ee065d83 14900 case Tag_ABI_PCS_wchar_t:
a9dc9481
JM		 14901 if (out_attr[i].i && in_attr[i].i && out_attr[i].i != in_attr[i].i
14902 && !elf_arm_tdata (obfd)->no_wchar_size_warning)
ee065d83
PB		 14903 {
14904 _bfd_error_handler
871b3ab2 14905 (_("warning: %pB uses %u-byte wchar_t yet the output is to use %u-byte wchar_t; use of wchar_t values across objects may fail"),
a9dc9481 14906 ibfd, in_attr[i].i, out_attr[i].i);
ee065d83 14907 }
a9dc9481 14908 else if (in_attr[i].i && !out_attr[i].i)
ee065d83
PB		 14909 out_attr[i].i = in_attr[i].i;
14910 break;
ee065d83
PB		 14911 case Tag_ABI_enum_size:
14912 if (in_attr[i].i != AEABI_enum_unused)
14913 {
14914 if (out_attr[i].i == AEABI_enum_unused
14915 || out_attr[i].i == AEABI_enum_forced_wide)
14916 {
14917 /* The existing object is compatible with anything.
14918 Use whatever requirements the new object has. */
14919 out_attr[i].i = in_attr[i].i;
14920 }
14921 else if (in_attr[i].i != AEABI_enum_forced_wide
bf21ed78 14922 && out_attr[i].i != in_attr[i].i
0ffa91dd 14923 && !elf_arm_tdata (obfd)->no_enum_size_warning)
ee065d83 14924 {
91e22acd 14925 static const char *aeabi_enum_names[] =
bf21ed78 14926 { "", "variable-size", "32-bit", "" };
91e22acd
AS		 14927 const char *in_name =
14928 in_attr[i].i < ARRAY_SIZE(aeabi_enum_names)
14929 ? aeabi_enum_names[in_attr[i].i]
14930 : "<unknown>";
14931 const char *out_name =
14932 out_attr[i].i < ARRAY_SIZE(aeabi_enum_names)
14933 ? aeabi_enum_names[out_attr[i].i]
14934 : "<unknown>";
ee065d83 14935 _bfd_error_handler
871b3ab2 14936 (_("warning: %pB uses %s enums yet the output is to use %s enums; use of enum values across objects may fail"),
91e22acd 14937 ibfd, in_name, out_name);
ee065d83
PB		 14938 }
14939 }
14940 break;
14941 case Tag_ABI_VFP_args:
14942 /* Aready done. */
14943 break;
14944 case Tag_ABI_WMMX_args:
14945 if (in_attr[i].i != out_attr[i].i)
14946 {
14947 _bfd_error_handler
871b3ab2 14948 (_("error: %pB uses iWMMXt register arguments, %pB does not"),
ee065d83 14949 ibfd, obfd);
91e22acd 14950 result = FALSE;
ee065d83
PB		 14951 }
14952 break;
7b86a9fa
AS		 14953 case Tag_compatibility:
14954 /* Merged in target-independent code. */
14955 break;
91e22acd 14956 case Tag_ABI_HardFP_use:
4547cb56 14957 /* This is handled along with Tag_FP_arch. */
91e22acd
AS		 14958 break;
14959 case Tag_ABI_FP_16bit_format:
14960 if (in_attr[i].i != 0 && out_attr[i].i != 0)
14961 {
14962 if (in_attr[i].i != out_attr[i].i)
14963 {
14964 _bfd_error_handler
871b3ab2 14965 (_("error: fp16 format mismatch between %pB and %pB"),
91e22acd
AS		 14966 ibfd, obfd);
14967 result = FALSE;
14968 }
14969 }
14970 if (in_attr[i].i != 0)
14971 out_attr[i].i = in_attr[i].i;
14972 break;
7b86a9fa 14973
cd21e546 14974 case Tag_DIV_use:
ac56ee8f
MGD		 14975 /* A value of zero on input means that the divide instruction may
14976 be used if available in the base architecture as specified via
14977 Tag_CPU_arch and Tag_CPU_arch_profile. A value of 1 means that
14978 the user did not want divide instructions. A value of 2
14979 explicitly means that divide instructions were allowed in ARM
14980 and Thumb state. */
14981 if (in_attr[i].i == out_attr[i].i)
14982 /* Do nothing. */ ;
14983 else if (elf32_arm_attributes_forbid_div (in_attr)
14984 && !elf32_arm_attributes_accept_div (out_attr))
14985 out_attr[i].i = 1;
14986 else if (elf32_arm_attributes_forbid_div (out_attr)
14987 && elf32_arm_attributes_accept_div (in_attr))
14988 out_attr[i].i = in_attr[i].i;
14989 else if (in_attr[i].i == 2)
14990 out_attr[i].i = in_attr[i].i;
cd21e546
MGD		 14991 break;
14992
14993 case Tag_MPextension_use_legacy:
14994 /* We don't output objects with Tag_MPextension_use_legacy - we
14995 move the value to Tag_MPextension_use. */
14996 if (in_attr[i].i != 0 && in_attr[Tag_MPextension_use].i != 0)
14997 {
14998 if (in_attr[Tag_MPextension_use].i != in_attr[i].i)
14999 {
15000 _bfd_error_handler
871b3ab2 15001 (_("%pB has both the current and legacy "
b38cadfb 15002 "Tag_MPextension_use attributes"),
cd21e546
MGD		 15003 ibfd);
15004 result = FALSE;
15005 }
15006 }
15007
15008 if (in_attr[i].i > out_attr[Tag_MPextension_use].i)
15009 out_attr[Tag_MPextension_use] = in_attr[i];
15010
15011 break;
15012
91e22acd 15013 case Tag_nodefaults:
2d0bb761
AS		 15014 /* This tag is set if it exists, but the value is unused (and is
15015 typically zero). We don't actually need to do anything here -
15016 the merge happens automatically when the type flags are merged
15017 below. */
91e22acd
AS		 15018 break;
15019 case Tag_also_compatible_with:
15020 /* Already done in Tag_CPU_arch. */
15021 break;
15022 case Tag_conformance:
15023 /* Keep the attribute if it matches. Throw it away otherwise.
15024 No attribute means no claim to conform. */
15025 if (!in_attr[i].s || !out_attr[i].s
15026 || strcmp (in_attr[i].s, out_attr[i].s) != 0)
15027 out_attr[i].s = NULL;
15028 break;
3cfad14c 15029
91e22acd 15030 default:
e8b36cd1
JM		 15031 result
15032 = result && _bfd_elf_merge_unknown_attribute_low (ibfd, obfd, i);
91e22acd
AS		 15033 }
15034
15035 /* If out_attr was copied from in_attr then it won't have a type yet. */
15036 if (in_attr[i].type && !out_attr[i].type)
15037 out_attr[i].type = in_attr[i].type;
ee065d83
PB		 15038 }
15039
104d59d1 15040 /* Merge Tag_compatibility attributes and any common GNU ones. */
50e03d47 15041 if (!_bfd_elf_merge_object_attributes (ibfd, info))
5488d830 15042 return FALSE;
ee065d83 15043
104d59d1 15044 /* Check for any attributes not known on ARM. */
e8b36cd1 15045 result &= _bfd_elf_merge_unknown_attribute_list (ibfd, obfd);
91e22acd 15046
91e22acd 15047 return result;
252b5132
RH		 15048}
15049
3a4a14e9
PB		 15050
15051/* Return TRUE if the two EABI versions are incompatible. */
15052
15053static bfd_boolean
15054elf32_arm_versions_compatible (unsigned iver, unsigned over)
15055{
15056 /* v4 and v5 are the same spec before and after it was released,
15057 so allow mixing them. */
15058 if ((iver == EF_ARM_EABI_VER4 && over == EF_ARM_EABI_VER5)
15059 || (iver == EF_ARM_EABI_VER5 && over == EF_ARM_EABI_VER4))
15060 return TRUE;
15061
15062 return (iver == over);
15063}
15064
252b5132
RH		 15065/* Merge backend specific data from an object file to the output
15066 object file when linking. */
9b485d32 15067
b34976b6 15068static bfd_boolean
50e03d47 15069elf32_arm_merge_private_bfd_data (bfd *, struct bfd_link_info *);
252b5132 15070
9b485d32
NC		 15071/* Display the flags field. */
15072
b34976b6 15073static bfd_boolean
57e8b36a 15074elf32_arm_print_private_bfd_data (bfd *abfd, void * ptr)
252b5132 15075{
fc830a83
NC		 15076 FILE * file = (FILE *) ptr;
15077 unsigned long flags;
252b5132
RH		 15078
15079 BFD_ASSERT (abfd != NULL && ptr != NULL);
15080
15081 /* Print normal ELF private data. */
15082 _bfd_elf_print_private_bfd_data (abfd, ptr);
15083
fc830a83 15084 flags = elf_elfheader (abfd)->e_flags;
9b485d32
NC		 15085 /* Ignore init flag - it may not be set, despite the flags field
15086 containing valid data. */
252b5132 15087
9b485d32 15088 fprintf (file, _("private flags = %lx:"), elf_elfheader (abfd)->e_flags);
252b5132 15089
fc830a83
NC		 15090 switch (EF_ARM_EABI_VERSION (flags))
15091 {
15092 case EF_ARM_EABI_UNKNOWN:
4cc11e76 15093 /* The following flag bits are GNU extensions and not part of the
fc830a83
NC		 15094 official ARM ELF extended ABI. Hence they are only decoded if
15095 the EABI version is not set. */
fd2ec330 15096 if (flags & EF_ARM_INTERWORK)
9b485d32 15097 fprintf (file, _(" [interworking enabled]"));
9a5aca8c 15098
fd2ec330 15099 if (flags & EF_ARM_APCS_26)
6c571f00 15100 fprintf (file, " [APCS-26]");
fc830a83 15101 else
6c571f00 15102 fprintf (file, " [APCS-32]");
9a5aca8c 15103
96a846ea
RE		 15104 if (flags & EF_ARM_VFP_FLOAT)
15105 fprintf (file, _(" [VFP float format]"));
fde78edd
NC		 15106 else if (flags & EF_ARM_MAVERICK_FLOAT)
15107 fprintf (file, _(" [Maverick float format]"));
96a846ea
RE		 15108 else
15109 fprintf (file, _(" [FPA float format]"));
15110
fd2ec330 15111 if (flags & EF_ARM_APCS_FLOAT)
9b485d32 15112 fprintf (file, _(" [floats passed in float registers]"));
9a5aca8c 15113
fd2ec330 15114 if (flags & EF_ARM_PIC)
9b485d32 15115 fprintf (file, _(" [position independent]"));
fc830a83 15116
fd2ec330 15117 if (flags & EF_ARM_NEW_ABI)
9b485d32 15118 fprintf (file, _(" [new ABI]"));
9a5aca8c 15119
fd2ec330 15120 if (flags & EF_ARM_OLD_ABI)
9b485d32 15121 fprintf (file, _(" [old ABI]"));
9a5aca8c 15122
fd2ec330 15123 if (flags & EF_ARM_SOFT_FLOAT)
9b485d32 15124 fprintf (file, _(" [software FP]"));
9a5aca8c 15125
96a846ea
RE		 15126 flags &= ~(EF_ARM_INTERWORK | EF_ARM_APCS_26 | EF_ARM_APCS_FLOAT
15127 | EF_ARM_PIC | EF_ARM_NEW_ABI | EF_ARM_OLD_ABI
fde78edd
NC		 15128 | EF_ARM_SOFT_FLOAT | EF_ARM_VFP_FLOAT
15129 | EF_ARM_MAVERICK_FLOAT);
fc830a83 15130 break;
9a5aca8c 15131
fc830a83 15132 case EF_ARM_EABI_VER1:
9b485d32 15133 fprintf (file, _(" [Version1 EABI]"));
9a5aca8c 15134
fc830a83 15135 if (flags & EF_ARM_SYMSARESORTED)
9b485d32 15136 fprintf (file, _(" [sorted symbol table]"));
fc830a83 15137 else
9b485d32 15138 fprintf (file, _(" [unsorted symbol table]"));
9a5aca8c 15139
fc830a83
NC		 15140 flags &= ~ EF_ARM_SYMSARESORTED;
15141 break;
9a5aca8c 15142
fd2ec330
PB		 15143 case EF_ARM_EABI_VER2:
15144 fprintf (file, _(" [Version2 EABI]"));
15145
15146 if (flags & EF_ARM_SYMSARESORTED)
15147 fprintf (file, _(" [sorted symbol table]"));
15148 else
15149 fprintf (file, _(" [unsorted symbol table]"));
15150
15151 if (flags & EF_ARM_DYNSYMSUSESEGIDX)
15152 fprintf (file, _(" [dynamic symbols use segment index]"));
15153
15154 if (flags & EF_ARM_MAPSYMSFIRST)
15155 fprintf (file, _(" [mapping symbols precede others]"));
15156
99e4ae17 15157 flags &= ~(EF_ARM_SYMSARESORTED | EF_ARM_DYNSYMSUSESEGIDX
fd2ec330
PB		 15158 | EF_ARM_MAPSYMSFIRST);
15159 break;
15160
d507cf36
PB		 15161 case EF_ARM_EABI_VER3:
15162 fprintf (file, _(" [Version3 EABI]"));
8cb51566
PB		 15163 break;
15164
15165 case EF_ARM_EABI_VER4:
15166 fprintf (file, _(" [Version4 EABI]"));
3a4a14e9 15167 goto eabi;
d507cf36 15168
3a4a14e9
PB		 15169 case EF_ARM_EABI_VER5:
15170 fprintf (file, _(" [Version5 EABI]"));
3bfcb652
NC		 15171
15172 if (flags & EF_ARM_ABI_FLOAT_SOFT)
15173 fprintf (file, _(" [soft-float ABI]"));
15174
15175 if (flags & EF_ARM_ABI_FLOAT_HARD)
15176 fprintf (file, _(" [hard-float ABI]"));
15177
15178 flags &= ~(EF_ARM_ABI_FLOAT_SOFT | EF_ARM_ABI_FLOAT_HARD);
15179
3a4a14e9 15180 eabi:
d507cf36
PB		 15181 if (flags & EF_ARM_BE8)
15182 fprintf (file, _(" [BE8]"));
15183
15184 if (flags & EF_ARM_LE8)
15185 fprintf (file, _(" [LE8]"));
15186
15187 flags &= ~(EF_ARM_LE8 | EF_ARM_BE8);
15188 break;
15189
fc830a83 15190 default:
9b485d32 15191 fprintf (file, _(" <EABI version unrecognised>"));
fc830a83
NC		 15192 break;
15193 }
252b5132 15194
fc830a83 15195 flags &= ~ EF_ARM_EABIMASK;
252b5132 15196
fc830a83 15197 if (flags & EF_ARM_RELEXEC)
9b485d32 15198 fprintf (file, _(" [relocatable executable]"));
252b5132 15199
18a20338
CL		 15200 if (flags & EF_ARM_PIC)
15201 fprintf (file, _(" [position independent]"));
15202
15203 if (elf_elfheader (abfd)->e_ident[EI_OSABI] == ELFOSABI_ARM_FDPIC)
15204 fprintf (file, _(" [FDPIC ABI supplement]"));
15205
15206 flags &= ~ (EF_ARM_RELEXEC | EF_ARM_PIC);
fc830a83
NC		 15207
15208 if (flags)
9b485d32 15209 fprintf (file, _("<Unrecognised flag bits set>"));
9a5aca8c 15210
252b5132
RH		 15211 fputc ('\n', file);
15212
b34976b6 15213 return TRUE;
252b5132
RH		 15214}
15215
15216static int
57e8b36a 15217elf32_arm_get_symbol_type (Elf_Internal_Sym * elf_sym, int type)
252b5132 15218{
2f0ca46a
NC		 15219 switch (ELF_ST_TYPE (elf_sym->st_info))
15220 {
15221 case STT_ARM_TFUNC:
15222 return ELF_ST_TYPE (elf_sym->st_info);
ce855c42 15223
2f0ca46a
NC		 15224 case STT_ARM_16BIT:
15225 /* If the symbol is not an object, return the STT_ARM_16BIT flag.
15226 This allows us to distinguish between data used by Thumb instructions
15227 and non-data (which is probably code) inside Thumb regions of an
15228 executable. */
1a0eb693 15229 if (type != STT_OBJECT && type != STT_TLS)
2f0ca46a
NC		 15230 return ELF_ST_TYPE (elf_sym->st_info);
15231 break;
9a5aca8c 15232
ce855c42
NC		 15233 default:
15234 break;
2f0ca46a
NC		 15235 }
15236
15237 return type;
252b5132 15238}
f21f3fe0 15239
252b5132 15240static asection *
07adf181
AM		 15241elf32_arm_gc_mark_hook (asection *sec,
15242 struct bfd_link_info *info,
15243 Elf_Internal_Rela *rel,
15244 struct elf_link_hash_entry *h,
15245 Elf_Internal_Sym *sym)
252b5132
RH		 15246{
15247 if (h != NULL)
07adf181 15248 switch (ELF32_R_TYPE (rel->r_info))
252b5132
RH		 15249 {
15250 case R_ARM_GNU_VTINHERIT:
15251 case R_ARM_GNU_VTENTRY:
07adf181
AM		 15252 return NULL;
15253 }
9ad5cbcf 15254
07adf181 15255 return _bfd_elf_gc_mark_hook (sec, info, rel, h, sym);
252b5132
RH		 15256}
15257
780a67af
NC		 15258/* Look through the relocs for a section during the first phase. */
15259
b34976b6 15260static bfd_boolean
57e8b36a
NC		 15261elf32_arm_check_relocs (bfd *abfd, struct bfd_link_info *info,
15262 asection *sec, const Elf_Internal_Rela *relocs)
252b5132 15263{
b34976b6
AM		 15264 Elf_Internal_Shdr *symtab_hdr;
15265 struct elf_link_hash_entry **sym_hashes;
b34976b6
AM		 15266 const Elf_Internal_Rela *rel;
15267 const Elf_Internal_Rela *rel_end;
15268 bfd *dynobj;
5e681ec4 15269 asection *sreloc;
5e681ec4 15270 struct elf32_arm_link_hash_table *htab;
f6e32f6d
RS		 15271 bfd_boolean call_reloc_p;
15272 bfd_boolean may_become_dynamic_p;
15273 bfd_boolean may_need_local_target_p;
ce98a316 15274 unsigned long nsyms;
9a5aca8c 15275
0e1862bb 15276 if (bfd_link_relocatable (info))
b34976b6 15277 return TRUE;
9a5aca8c 15278
0ffa91dd
NC		 15279 BFD_ASSERT (is_arm_elf (abfd));
15280
5e681ec4 15281 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 15282 if (htab == NULL)
15283 return FALSE;
15284
5e681ec4 15285 sreloc = NULL;
9a5aca8c 15286
67687978
PB		 15287 /* Create dynamic sections for relocatable executables so that we can
15288 copy relocations. */
15289 if (htab->root.is_relocatable_executable
15290 && ! htab->root.dynamic_sections_created)
15291 {
15292 if (! _bfd_elf_link_create_dynamic_sections (abfd, info))
15293 return FALSE;
15294 }
15295
cbc704f3
RS		 15296 if (htab->root.dynobj == NULL)
15297 htab->root.dynobj = abfd;
34e77a92
RS		 15298 if (!create_ifunc_sections (info))
15299 return FALSE;
cbc704f3
RS		 15300
15301 dynobj = htab->root.dynobj;
15302
0ffa91dd 15303 symtab_hdr = & elf_symtab_hdr (abfd);
252b5132 15304 sym_hashes = elf_sym_hashes (abfd);
ce98a316 15305 nsyms = NUM_SHDR_ENTRIES (symtab_hdr);
b38cadfb 15306
252b5132
RH		 15307 rel_end = relocs + sec->reloc_count;
15308 for (rel = relocs; rel < rel_end; rel++)
15309 {
34e77a92 15310 Elf_Internal_Sym *isym;
252b5132 15311 struct elf_link_hash_entry *h;
b7693d02 15312 struct elf32_arm_link_hash_entry *eh;
d42c267e 15313 unsigned int r_symndx;
eb043451 15314 int r_type;
9a5aca8c 15315
252b5132 15316 r_symndx = ELF32_R_SYM (rel->r_info);
eb043451 15317 r_type = ELF32_R_TYPE (rel->r_info);
eb043451 15318 r_type = arm_real_reloc_type (htab, r_type);
ba93b8ac 15319
ce98a316
NC		 15320 if (r_symndx >= nsyms
15321 /* PR 9934: It is possible to have relocations that do not
15322 refer to symbols, thus it is also possible to have an
15323 object file containing relocations but no symbol table. */
cf35638d 15324 && (r_symndx > STN_UNDEF || nsyms > 0))
ba93b8ac 15325 {
871b3ab2 15326 _bfd_error_handler (_("%pB: bad symbol index: %d"), abfd,
4eca0228 15327 r_symndx);
ba93b8ac
DJ		 15328 return FALSE;
15329 }
15330
34e77a92
RS		 15331 h = NULL;
15332 isym = NULL;
15333 if (nsyms > 0)
973a3492 15334 {
34e77a92
RS		 15335 if (r_symndx < symtab_hdr->sh_info)
15336 {
15337 /* A local symbol. */
15338 isym = bfd_sym_from_r_symndx (&htab->sym_cache,
15339 abfd, r_symndx);
15340 if (isym == NULL)
15341 return FALSE;
15342 }
15343 else
15344 {
15345 h = sym_hashes[r_symndx - symtab_hdr->sh_info];
15346 while (h->root.type == bfd_link_hash_indirect
15347 || h->root.type == bfd_link_hash_warning)
15348 h = (struct elf_link_hash_entry *) h->root.u.i.link;
15349 }
973a3492 15350 }
9a5aca8c 15351
b7693d02
DJ		 15352 eh = (struct elf32_arm_link_hash_entry *) h;
15353
f6e32f6d
RS		 15354 call_reloc_p = FALSE;
15355 may_become_dynamic_p = FALSE;
15356 may_need_local_target_p = FALSE;
15357
0855e32b
NS		 15358 /* Could be done earlier, if h were already available. */
15359 r_type = elf32_arm_tls_transition (info, r_type, h);
eb043451 15360 switch (r_type)
99059e56 15361 {
e8b09b87
CL		 15362 case R_ARM_GOTOFFFUNCDESC:
15363 {
15364 if (h == NULL)
15365 {
15366 if (!elf32_arm_allocate_local_sym_info (abfd))
15367 return FALSE;
15368 elf32_arm_local_fdpic_cnts(abfd)[r_symndx].gotofffuncdesc_cnt += 1;
15369 elf32_arm_local_fdpic_cnts(abfd)[r_symndx].funcdesc_offset = -1;
15370 }
15371 else
15372 {
15373 eh->fdpic_cnts.gotofffuncdesc_cnt++;
15374 }
15375 }
15376 break;
15377
15378 case R_ARM_GOTFUNCDESC:
15379 {
15380 if (h == NULL)
15381 {
15382 /* Such a relocation is not supposed to be generated
15383 by gcc on a static function. */
15384 /* Anyway if needed it could be handled. */
15385 abort();
15386 }
15387 else
15388 {
15389 eh->fdpic_cnts.gotfuncdesc_cnt++;
15390 }
15391 }
15392 break;
15393
15394 case R_ARM_FUNCDESC:
15395 {
15396 if (h == NULL)
15397 {
15398 if (!elf32_arm_allocate_local_sym_info (abfd))
15399 return FALSE;
15400 elf32_arm_local_fdpic_cnts(abfd)[r_symndx].funcdesc_cnt += 1;
15401 elf32_arm_local_fdpic_cnts(abfd)[r_symndx].funcdesc_offset = -1;
15402 }
15403 else
15404 {
15405 eh->fdpic_cnts.funcdesc_cnt++;
15406 }
15407 }
15408 break;
15409
5e681ec4 15410 case R_ARM_GOT32:
eb043451 15411 case R_ARM_GOT_PREL:
ba93b8ac 15412 case R_ARM_TLS_GD32:
5c5a4843 15413 case R_ARM_TLS_GD32_FDPIC:
ba93b8ac 15414 case R_ARM_TLS_IE32:
5c5a4843 15415 case R_ARM_TLS_IE32_FDPIC:
0855e32b
NS		 15416 case R_ARM_TLS_GOTDESC:
15417 case R_ARM_TLS_DESCSEQ:
15418 case R_ARM_THM_TLS_DESCSEQ:
15419 case R_ARM_TLS_CALL:
15420 case R_ARM_THM_TLS_CALL:
5e681ec4 15421 /* This symbol requires a global offset table entry. */
ba93b8ac
DJ		 15422 {
15423 int tls_type, old_tls_type;
5e681ec4 15424
ba93b8ac
DJ		 15425 switch (r_type)
15426 {
15427 case R_ARM_TLS_GD32: tls_type = GOT_TLS_GD; break;
5c5a4843 15428 case R_ARM_TLS_GD32_FDPIC: tls_type = GOT_TLS_GD; break;
b38cadfb 15429
ba93b8ac 15430 case R_ARM_TLS_IE32: tls_type = GOT_TLS_IE; break;
5c5a4843 15431 case R_ARM_TLS_IE32_FDPIC: tls_type = GOT_TLS_IE; break;
b38cadfb 15432
0855e32b
NS		 15433 case R_ARM_TLS_GOTDESC:
15434 case R_ARM_TLS_CALL: case R_ARM_THM_TLS_CALL:
15435 case R_ARM_TLS_DESCSEQ: case R_ARM_THM_TLS_DESCSEQ:
15436 tls_type = GOT_TLS_GDESC; break;
b38cadfb 15437
ba93b8ac
DJ		 15438 default: tls_type = GOT_NORMAL; break;
15439 }
252b5132 15440
0e1862bb 15441 if (!bfd_link_executable (info) && (tls_type & GOT_TLS_IE))
eea6dad2
KM		 15442 info->flags |= DF_STATIC_TLS;
15443
ba93b8ac
DJ		 15444 if (h != NULL)
15445 {
15446 h->got.refcount++;
15447 old_tls_type = elf32_arm_hash_entry (h)->tls_type;
15448 }
15449 else
15450 {
ba93b8ac 15451 /* This is a global offset table entry for a local symbol. */
34e77a92
RS		 15452 if (!elf32_arm_allocate_local_sym_info (abfd))
15453 return FALSE;
15454 elf_local_got_refcounts (abfd)[r_symndx] += 1;
ba93b8ac
DJ		 15455 old_tls_type = elf32_arm_local_got_tls_type (abfd) [r_symndx];
15456 }
15457
0855e32b 15458 /* If a variable is accessed with both tls methods, two
99059e56 15459 slots may be created. */
0855e32b
NS		 15460 if (GOT_TLS_GD_ANY_P (old_tls_type)
15461 && GOT_TLS_GD_ANY_P (tls_type))
15462 tls_type |= old_tls_type;
15463
15464 /* We will already have issued an error message if there
15465 is a TLS/non-TLS mismatch, based on the symbol
15466 type. So just combine any TLS types needed. */
ba93b8ac
DJ		 15467 if (old_tls_type != GOT_UNKNOWN && old_tls_type != GOT_NORMAL
15468 && tls_type != GOT_NORMAL)
15469 tls_type |= old_tls_type;
15470
0855e32b 15471 /* If the symbol is accessed in both IE and GDESC
99059e56
RM		 15472 method, we're able to relax. Turn off the GDESC flag,
15473 without messing up with any other kind of tls types
6a631e86 15474 that may be involved. */
0855e32b
NS		 15475 if ((tls_type & GOT_TLS_IE) && (tls_type & GOT_TLS_GDESC))
15476 tls_type &= ~GOT_TLS_GDESC;
15477
ba93b8ac
DJ		 15478 if (old_tls_type != tls_type)
15479 {
15480 if (h != NULL)
15481 elf32_arm_hash_entry (h)->tls_type = tls_type;
15482 else
15483 elf32_arm_local_got_tls_type (abfd) [r_symndx] = tls_type;
15484 }
15485 }
8029a119 15486 /* Fall through. */
ba93b8ac
DJ		 15487
15488 case R_ARM_TLS_LDM32:
5c5a4843
CL		 15489 case R_ARM_TLS_LDM32_FDPIC:
15490 if (r_type == R_ARM_TLS_LDM32 || r_type == R_ARM_TLS_LDM32_FDPIC)
ba93b8ac 15491 htab->tls_ldm_got.refcount++;
8029a119 15492 /* Fall through. */
252b5132 15493
c19d1205 15494 case R_ARM_GOTOFF32:
5e681ec4 15495 case R_ARM_GOTPC:
cbc704f3
RS		 15496 if (htab->root.sgot == NULL
15497 && !create_got_section (htab->root.dynobj, info))
15498 return FALSE;
252b5132
RH		 15499 break;
15500
252b5132 15501 case R_ARM_PC24:
7359ea65 15502 case R_ARM_PLT32:
5b5bb741
PB		 15503 case R_ARM_CALL:
15504 case R_ARM_JUMP24:
eb043451 15505 case R_ARM_PREL31:
c19d1205 15506 case R_ARM_THM_CALL:
bd97cb95
DJ		 15507 case R_ARM_THM_JUMP24:
15508 case R_ARM_THM_JUMP19:
f6e32f6d
RS		 15509 call_reloc_p = TRUE;
15510 may_need_local_target_p = TRUE;
15511 break;
15512
15513 case R_ARM_ABS12:
15514 /* VxWorks uses dynamic R_ARM_ABS12 relocations for
15515 ldr __GOTT_INDEX__ offsets. */
15516 if (!htab->vxworks_p)
15517 {
15518 may_need_local_target_p = TRUE;
15519 break;
15520 }
aebf9be7 15521 else goto jump_over;
9eaff861 15522
f6e32f6d 15523 /* Fall through. */
39623e12 15524
96c23d59
JM		 15525 case R_ARM_MOVW_ABS_NC:
15526 case R_ARM_MOVT_ABS:
15527 case R_ARM_THM_MOVW_ABS_NC:
15528 case R_ARM_THM_MOVT_ABS:
0e1862bb 15529 if (bfd_link_pic (info))
96c23d59 15530 {
4eca0228 15531 _bfd_error_handler
871b3ab2 15532 (_("%pB: relocation %s against `%s' can not be used when making a shared object; recompile with -fPIC"),
96c23d59
JM		 15533 abfd, elf32_arm_howto_table_1[r_type].name,
15534 (h) ? h->root.root.string : "a local symbol");
15535 bfd_set_error (bfd_error_bad_value);
15536 return FALSE;
15537 }
15538
15539 /* Fall through. */
39623e12
PB		 15540 case R_ARM_ABS32:
15541 case R_ARM_ABS32_NOI:
aebf9be7 15542 jump_over:
0e1862bb 15543 if (h != NULL && bfd_link_executable (info))
97323ad1
WN		 15544 {
15545 h->pointer_equality_needed = 1;
15546 }
15547 /* Fall through. */
39623e12
PB		 15548 case R_ARM_REL32:
15549 case R_ARM_REL32_NOI:
b6895b4f
PB		 15550 case R_ARM_MOVW_PREL_NC:
15551 case R_ARM_MOVT_PREL:
b6895b4f
PB		 15552 case R_ARM_THM_MOVW_PREL_NC:
15553 case R_ARM_THM_MOVT_PREL:
39623e12 15554
b7693d02 15555 /* Should the interworking branches be listed here? */
e8b09b87
CL		 15556 if ((bfd_link_pic (info) || htab->root.is_relocatable_executable
15557 || htab->fdpic_p)
34e77a92
RS		 15558 && (sec->flags & SEC_ALLOC) != 0)
15559 {
15560 if (h == NULL
469a3493 15561 && elf32_arm_howto_from_type (r_type)->pc_relative)
34e77a92
RS		 15562 {
15563 /* In shared libraries and relocatable executables,
15564 we treat local relative references as calls;
15565 see the related SYMBOL_CALLS_LOCAL code in
15566 allocate_dynrelocs. */
15567 call_reloc_p = TRUE;
15568 may_need_local_target_p = TRUE;
15569 }
15570 else
15571 /* We are creating a shared library or relocatable
15572 executable, and this is a reloc against a global symbol,
15573 or a non-PC-relative reloc against a local symbol.
15574 We may need to copy the reloc into the output. */
15575 may_become_dynamic_p = TRUE;
15576 }
f6e32f6d
RS		 15577 else
15578 may_need_local_target_p = TRUE;
252b5132
RH		 15579 break;
15580
99059e56
RM		 15581 /* This relocation describes the C++ object vtable hierarchy.
15582 Reconstruct it for later use during GC. */
15583 case R_ARM_GNU_VTINHERIT:
15584 if (!bfd_elf_gc_record_vtinherit (abfd, sec, h, rel->r_offset))
15585 return FALSE;
15586 break;
15587
15588 /* This relocation describes which C++ vtable entries are actually
15589 used. Record for later use during GC. */
15590 case R_ARM_GNU_VTENTRY:
a0ea3a14 15591 if (!bfd_elf_gc_record_vtentry (abfd, sec, h, rel->r_offset))
99059e56
RM		 15592 return FALSE;
15593 break;
15594 }
f6e32f6d
RS		 15595
15596 if (h != NULL)
15597 {
15598 if (call_reloc_p)
15599 /* We may need a .plt entry if the function this reloc
15600 refers to is in a different object, regardless of the
15601 symbol's type. We can't tell for sure yet, because
15602 something later might force the symbol local. */
15603 h->needs_plt = 1;
15604 else if (may_need_local_target_p)
15605 /* If this reloc is in a read-only section, we might
15606 need a copy reloc. We can't check reliably at this
15607 stage whether the section is read-only, as input
15608 sections have not yet been mapped to output sections.
15609 Tentatively set the flag for now, and correct in
15610 adjust_dynamic_symbol. */
15611 h->non_got_ref = 1;
15612 }
15613
34e77a92
RS		 15614 if (may_need_local_target_p
15615 && (h != NULL || ELF32_ST_TYPE (isym->st_info) == STT_GNU_IFUNC))
f6e32f6d 15616 {
34e77a92
RS		 15617 union gotplt_union *root_plt;
15618 struct arm_plt_info *arm_plt;
15619 struct arm_local_iplt_info *local_iplt;
15620
15621 if (h != NULL)
15622 {
15623 root_plt = &h->plt;
15624 arm_plt = &eh->plt;
15625 }
15626 else
15627 {
15628 local_iplt = elf32_arm_create_local_iplt (abfd, r_symndx);
15629 if (local_iplt == NULL)
15630 return FALSE;
15631 root_plt = &local_iplt->root;
15632 arm_plt = &local_iplt->arm;
15633 }
15634
f6e32f6d
RS		 15635 /* If the symbol is a function that doesn't bind locally,
15636 this relocation will need a PLT entry. */
a8c887dd
NC		 15637 if (root_plt->refcount != -1)
15638 root_plt->refcount += 1;
34e77a92
RS		 15639
15640 if (!call_reloc_p)
15641 arm_plt->noncall_refcount++;
f6e32f6d
RS		 15642
15643 /* It's too early to use htab->use_blx here, so we have to
15644 record possible blx references separately from
15645 relocs that definitely need a thumb stub. */
15646
15647 if (r_type == R_ARM_THM_CALL)
34e77a92 15648 arm_plt->maybe_thumb_refcount += 1;
f6e32f6d
RS		 15649
15650 if (r_type == R_ARM_THM_JUMP24
15651 || r_type == R_ARM_THM_JUMP19)
34e77a92 15652 arm_plt->thumb_refcount += 1;
f6e32f6d
RS		 15653 }
15654
15655 if (may_become_dynamic_p)
15656 {
15657 struct elf_dyn_relocs *p, **head;
15658
15659 /* Create a reloc section in dynobj. */
15660 if (sreloc == NULL)
15661 {
15662 sreloc = _bfd_elf_make_dynamic_reloc_section
15663 (sec, dynobj, 2, abfd, ! htab->use_rel);
15664
15665 if (sreloc == NULL)
15666 return FALSE;
15667
15668 /* BPABI objects never have dynamic relocations mapped. */
15669 if (htab->symbian_p)
15670 {
15671 flagword flags;
15672
fd361982 15673 flags = bfd_section_flags (sreloc);
f6e32f6d 15674 flags &= ~(SEC_LOAD | SEC_ALLOC);
fd361982 15675 bfd_set_section_flags (sreloc, flags);
f6e32f6d
RS		 15676 }
15677 }
15678
15679 /* If this is a global symbol, count the number of
15680 relocations we need for this symbol. */
15681 if (h != NULL)
190eb1dd 15682 head = &h->dyn_relocs;
f6e32f6d
RS		 15683 else
15684 {
34e77a92
RS		 15685 head = elf32_arm_get_local_dynreloc_list (abfd, r_symndx, isym);
15686 if (head == NULL)
f6e32f6d 15687 return FALSE;
f6e32f6d
RS		 15688 }
15689
15690 p = *head;
15691 if (p == NULL || p->sec != sec)
15692 {
986f0783 15693 size_t amt = sizeof *p;
f6e32f6d
RS		 15694
15695 p = (struct elf_dyn_relocs *) bfd_alloc (htab->root.dynobj, amt);
15696 if (p == NULL)
15697 return FALSE;
15698 p->next = *head;
15699 *head = p;
15700 p->sec = sec;
15701 p->count = 0;
15702 p->pc_count = 0;
15703 }
15704
469a3493 15705 if (elf32_arm_howto_from_type (r_type)->pc_relative)
f6e32f6d
RS		 15706 p->pc_count += 1;
15707 p->count += 1;
e8b09b87
CL		 15708 if (h == NULL && htab->fdpic_p && !bfd_link_pic(info)
15709 && r_type != R_ARM_ABS32 && r_type != R_ARM_ABS32_NOI) {
15710 /* Here we only support R_ARM_ABS32 and R_ARM_ABS32_NOI
15711 that will become rofixup. */
15712 /* This is due to the fact that we suppose all will become rofixup. */
15713 fprintf(stderr, "FDPIC does not yet support %d relocation to become dynamic for executable\n", r_type);
15714 _bfd_error_handler
15715 (_("FDPIC does not yet support %s relocation"
15716 " to become dynamic for executable"),
15717 elf32_arm_howto_table_1[r_type].name);
15718 abort();
15719 }
f6e32f6d 15720 }
252b5132 15721 }
f21f3fe0 15722
b34976b6 15723 return TRUE;
252b5132
RH		 15724}
15725
9eaff861
AO		 15726static void
15727elf32_arm_update_relocs (asection *o,
15728 struct bfd_elf_section_reloc_data *reldata)
15729{
15730 void (*swap_in) (bfd *, const bfd_byte *, Elf_Internal_Rela *);
15731 void (*swap_out) (bfd *, const Elf_Internal_Rela *, bfd_byte *);
15732 const struct elf_backend_data *bed;
15733 _arm_elf_section_data *eado;
15734 struct bfd_link_order *p;
15735 bfd_byte *erela_head, *erela;
15736 Elf_Internal_Rela *irela_head, *irela;
15737 Elf_Internal_Shdr *rel_hdr;
15738 bfd *abfd;
15739 unsigned int count;
15740
15741 eado = get_arm_elf_section_data (o);
15742
15743 if (!eado || eado->elf.this_hdr.sh_type != SHT_ARM_EXIDX)
15744 return;
15745
15746 abfd = o->owner;
15747 bed = get_elf_backend_data (abfd);
15748 rel_hdr = reldata->hdr;
15749
15750 if (rel_hdr->sh_entsize == bed->s->sizeof_rel)
15751 {
15752 swap_in = bed->s->swap_reloc_in;
15753 swap_out = bed->s->swap_reloc_out;
15754 }
15755 else if (rel_hdr->sh_entsize == bed->s->sizeof_rela)
15756 {
15757 swap_in = bed->s->swap_reloca_in;
15758 swap_out = bed->s->swap_reloca_out;
15759 }
15760 else
15761 abort ();
15762
15763 erela_head = rel_hdr->contents;
15764 irela_head = (Elf_Internal_Rela *) bfd_zmalloc
15765 ((NUM_SHDR_ENTRIES (rel_hdr) + 1) * sizeof (*irela_head));
15766
15767 erela = erela_head;
15768 irela = irela_head;
15769 count = 0;
15770
15771 for (p = o->map_head.link_order; p; p = p->next)
15772 {
15773 if (p->type == bfd_section_reloc_link_order
15774 || p->type == bfd_symbol_reloc_link_order)
15775 {
15776 (*swap_in) (abfd, erela, irela);
15777 erela += rel_hdr->sh_entsize;
15778 irela++;
15779 count++;
15780 }
15781 else if (p->type == bfd_indirect_link_order)
15782 {
15783 struct bfd_elf_section_reloc_data *input_reldata;
15784 arm_unwind_table_edit *edit_list, *edit_tail;
15785 _arm_elf_section_data *eadi;
15786 bfd_size_type j;
15787 bfd_vma offset;
15788 asection *i;
15789
15790 i = p->u.indirect.section;
15791
15792 eadi = get_arm_elf_section_data (i);
15793 edit_list = eadi->u.exidx.unwind_edit_list;
15794 edit_tail = eadi->u.exidx.unwind_edit_tail;
539300fb 15795 offset = i->output_offset;
9eaff861
AO		 15796
15797 if (eadi->elf.rel.hdr &&
15798 eadi->elf.rel.hdr->sh_entsize == rel_hdr->sh_entsize)
15799 input_reldata = &eadi->elf.rel;
15800 else if (eadi->elf.rela.hdr &&
15801 eadi->elf.rela.hdr->sh_entsize == rel_hdr->sh_entsize)
15802 input_reldata = &eadi->elf.rela;
15803 else
15804 abort ();
15805
15806 if (edit_list)
15807 {
15808 for (j = 0; j < NUM_SHDR_ENTRIES (input_reldata->hdr); j++)
15809 {
15810 arm_unwind_table_edit *edit_node, *edit_next;
15811 bfd_vma bias;
c48182bf 15812 bfd_vma reloc_index;
9eaff861
AO		 15813
15814 (*swap_in) (abfd, erela, irela);
c48182bf 15815 reloc_index = (irela->r_offset - offset) / 8;
9eaff861
AO		 15816
15817 bias = 0;
15818 edit_node = edit_list;
15819 for (edit_next = edit_list;
c48182bf 15820 edit_next && edit_next->index <= reloc_index;
9eaff861
AO		 15821 edit_next = edit_node->next)
15822 {
15823 bias++;
15824 edit_node = edit_next;
15825 }
15826
15827 if (edit_node->type != DELETE_EXIDX_ENTRY
c48182bf 15828 || edit_node->index != reloc_index)
9eaff861
AO		 15829 {
15830 irela->r_offset -= bias * 8;
15831 irela++;
15832 count++;
15833 }
15834
15835 erela += rel_hdr->sh_entsize;
15836 }
15837
15838 if (edit_tail->type == INSERT_EXIDX_CANTUNWIND_AT_END)
15839 {
15840 /* New relocation entity. */
15841 asection *text_sec = edit_tail->linked_section;
15842 asection *text_out = text_sec->output_section;
15843 bfd_vma exidx_offset = offset + i->size - 8;
15844
15845 irela->r_addend = 0;
15846 irela->r_offset = exidx_offset;
15847 irela->r_info = ELF32_R_INFO
15848 (text_out->target_index, R_ARM_PREL31);
15849 irela++;
15850 count++;
15851 }
15852 }
15853 else
15854 {
15855 for (j = 0; j < NUM_SHDR_ENTRIES (input_reldata->hdr); j++)
15856 {
15857 (*swap_in) (abfd, erela, irela);
15858 erela += rel_hdr->sh_entsize;
15859 irela++;
15860 }
15861
15862 count += NUM_SHDR_ENTRIES (input_reldata->hdr);
15863 }
15864 }
15865 }
15866
15867 reldata->count = count;
15868 rel_hdr->sh_size = count * rel_hdr->sh_entsize;
15869
15870 erela = erela_head;
15871 irela = irela_head;
15872 while (count > 0)
15873 {
15874 (*swap_out) (abfd, irela, erela);
15875 erela += rel_hdr->sh_entsize;
15876 irela++;
15877 count--;
15878 }
15879
15880 free (irela_head);
15881
15882 /* Hashes are no longer valid. */
15883 free (reldata->hashes);
15884 reldata->hashes = NULL;
15885}
15886
6a5bb875 15887/* Unwinding tables are not referenced directly. This pass marks them as
4ba2ef8f
TP		 15888 required if the corresponding code section is marked. Similarly, ARMv8-M
15889 secure entry functions can only be referenced by SG veneers which are
15890 created after the GC process. They need to be marked in case they reside in
15891 their own section (as would be the case if code was compiled with
15892 -ffunction-sections). */
6a5bb875
PB		 15893
15894static bfd_boolean
906e58ca
NC		 15895elf32_arm_gc_mark_extra_sections (struct bfd_link_info *info,
15896 elf_gc_mark_hook_fn gc_mark_hook)
6a5bb875
PB		 15897{
15898 bfd *sub;
15899 Elf_Internal_Shdr **elf_shdrp;
4ba2ef8f
TP		 15900 asection *cmse_sec;
15901 obj_attribute *out_attr;
15902 Elf_Internal_Shdr *symtab_hdr;
15903 unsigned i, sym_count, ext_start;
15904 const struct elf_backend_data *bed;
15905 struct elf_link_hash_entry **sym_hashes;
15906 struct elf32_arm_link_hash_entry *cmse_hash;
15907 bfd_boolean again, is_v8m, first_bfd_browse = TRUE;
bb32413f
SP		 15908 bfd_boolean debug_sec_need_to_be_marked = FALSE;
15909 asection *isec;
6a5bb875 15910
7f6ab9f8
AM		 15911 _bfd_elf_gc_mark_extra_sections (info, gc_mark_hook);
15912
4ba2ef8f
TP		 15913 out_attr = elf_known_obj_attributes_proc (info->output_bfd);
15914 is_v8m = out_attr[Tag_CPU_arch].i >= TAG_CPU_ARCH_V8M_BASE
15915 && out_attr[Tag_CPU_arch_profile].i == 'M';
15916
6a5bb875
PB		 15917 /* Marking EH data may cause additional code sections to be marked,
15918 requiring multiple passes. */
15919 again = TRUE;
15920 while (again)
15921 {
15922 again = FALSE;
c72f2fb2 15923 for (sub = info->input_bfds; sub != NULL; sub = sub->link.next)
6a5bb875
PB		 15924 {
15925 asection *o;
15926
0ffa91dd 15927 if (! is_arm_elf (sub))
6a5bb875
PB		 15928 continue;
15929
15930 elf_shdrp = elf_elfsections (sub);
15931 for (o = sub->sections; o != NULL; o = o->next)
15932 {
15933 Elf_Internal_Shdr *hdr;
0ffa91dd 15934
6a5bb875 15935 hdr = &elf_section_data (o)->this_hdr;
4fbb74a6
AM		 15936 if (hdr->sh_type == SHT_ARM_EXIDX
15937 && hdr->sh_link
15938 && hdr->sh_link < elf_numsections (sub)
6a5bb875
PB		 15939 && !o->gc_mark
15940 && elf_shdrp[hdr->sh_link]->bfd_section->gc_mark)
15941 {
15942 again = TRUE;
15943 if (!_bfd_elf_gc_mark (info, o, gc_mark_hook))
15944 return FALSE;
15945 }
15946 }
4ba2ef8f
TP		 15947
15948 /* Mark section holding ARMv8-M secure entry functions. We mark all
15949 of them so no need for a second browsing. */
15950 if (is_v8m && first_bfd_browse)
15951 {
15952 sym_hashes = elf_sym_hashes (sub);
15953 bed = get_elf_backend_data (sub);
15954 symtab_hdr = &elf_tdata (sub)->symtab_hdr;
15955 sym_count = symtab_hdr->sh_size / bed->s->sizeof_sym;
15956 ext_start = symtab_hdr->sh_info;
15957
15958 /* Scan symbols. */
15959 for (i = ext_start; i < sym_count; i++)
15960 {
15961 cmse_hash = elf32_arm_hash_entry (sym_hashes[i - ext_start]);
15962
15963 /* Assume it is a special symbol. If not, cmse_scan will
15964 warn about it and user can do something about it. */
baf46cd7
AM		 15965 if (CONST_STRNEQ (cmse_hash->root.root.root.string,
15966 CMSE_PREFIX))
4ba2ef8f
TP		 15967 {
15968 cmse_sec = cmse_hash->root.root.u.def.section;
5025eb7c
AO		 15969 if (!cmse_sec->gc_mark
15970 && !_bfd_elf_gc_mark (info, cmse_sec, gc_mark_hook))
4ba2ef8f 15971 return FALSE;
bb32413f
SP		 15972 /* The debug sections related to these secure entry
15973 functions are marked on enabling below flag. */
15974 debug_sec_need_to_be_marked = TRUE;
4ba2ef8f
TP		 15975 }
15976 }
bb32413f
SP		 15977
15978 if (debug_sec_need_to_be_marked)
15979 {
15980 /* Looping over all the sections of the object file containing
15981 Armv8-M secure entry functions and marking all the debug
15982 sections. */
15983 for (isec = sub->sections; isec != NULL; isec = isec->next)
15984 {
15985 /* If not a debug sections, skip it. */
15986 if (!isec->gc_mark && (isec->flags & SEC_DEBUGGING))
15987 isec->gc_mark = 1 ;
15988 }
15989 debug_sec_need_to_be_marked = FALSE;
15990 }
4ba2ef8f 15991 }
6a5bb875 15992 }
4ba2ef8f 15993 first_bfd_browse = FALSE;
6a5bb875
PB		 15994 }
15995
15996 return TRUE;
15997}
15998
3c9458e9
NC		 15999/* Treat mapping symbols as special target symbols. */
16000
16001static bfd_boolean
16002elf32_arm_is_target_special_symbol (bfd * abfd ATTRIBUTE_UNUSED, asymbol * sym)
16003{
b0796911
PB		 16004 return bfd_is_arm_special_symbol_name (sym->name,
16005 BFD_ARM_SPECIAL_SYM_TYPE_ANY);
3c9458e9
NC		 16006}
16007
e7679060
AM		 16008/* If the ELF symbol SYM might be a function in SEC, return the
16009 function size and set *CODE_OFF to the function's entry point,
16010 otherwise return zero. */
252b5132 16011
e7679060
AM		 16012static bfd_size_type
16013elf32_arm_maybe_function_sym (const asymbol *sym, asection *sec,
16014 bfd_vma *code_off)
16015{
16016 bfd_size_type size;
252b5132 16017
e7679060
AM		 16018 if ((sym->flags & (BSF_SECTION_SYM | BSF_FILE | BSF_OBJECT
16019 | BSF_THREAD_LOCAL | BSF_RELC | BSF_SRELC)) != 0
16020 || sym->section != sec)
16021 return 0;
252b5132 16022
e7679060
AM		 16023 if (!(sym->flags & BSF_SYNTHETIC))
16024 switch (ELF_ST_TYPE (((elf_symbol_type *) sym)->internal_elf_sym.st_info))
16025 {
252b5132
RH		 16026 case STT_FUNC:
16027 case STT_ARM_TFUNC:
9d2da7ca 16028 case STT_NOTYPE:
252b5132 16029 break;
e7679060
AM		 16030 default:
16031 return 0;
16032 }
0367ecfb 16033
e7679060
AM		 16034 if ((sym->flags & BSF_LOCAL)
16035 && bfd_is_arm_special_symbol_name (sym->name,
16036 BFD_ARM_SPECIAL_SYM_TYPE_ANY))
16037 return 0;
0367ecfb 16038
e7679060
AM		 16039 *code_off = sym->value;
16040 size = 0;
16041 if (!(sym->flags & BSF_SYNTHETIC))
16042 size = ((elf_symbol_type *) sym)->internal_elf_sym.st_size;
16043 if (size == 0)
16044 size = 1;
16045 return size;
252b5132
RH		 16046}
16047
4ab527b0 16048static bfd_boolean
07d6d2b8 16049elf32_arm_find_inliner_info (bfd * abfd,
4ab527b0
FF		 16050 const char ** filename_ptr,
16051 const char ** functionname_ptr,
16052 unsigned int * line_ptr)
16053{
16054 bfd_boolean found;
16055 found = _bfd_dwarf2_find_inliner_info (abfd, filename_ptr,
16056 functionname_ptr, line_ptr,
16057 & elf_tdata (abfd)->dwarf2_find_line_info);
16058 return found;
16059}
16060
252b5132
RH		 16061/* Adjust a symbol defined by a dynamic object and referenced by a
16062 regular object. The current definition is in some section of the
16063 dynamic object, but we're not including those sections. We have to
16064 change the definition to something the rest of the link can
16065 understand. */
16066
b34976b6 16067static bfd_boolean
57e8b36a
NC		 16068elf32_arm_adjust_dynamic_symbol (struct bfd_link_info * info,
16069 struct elf_link_hash_entry * h)
252b5132
RH		 16070{
16071 bfd * dynobj;
5474d94f 16072 asection *s, *srel;
b7693d02 16073 struct elf32_arm_link_hash_entry * eh;
67687978 16074 struct elf32_arm_link_hash_table *globals;
252b5132 16075
67687978 16076 globals = elf32_arm_hash_table (info);
4dfe6ac6
NC		 16077 if (globals == NULL)
16078 return FALSE;
16079
252b5132
RH		 16080 dynobj = elf_hash_table (info)->dynobj;
16081
16082 /* Make sure we know what is going on here. */
16083 BFD_ASSERT (dynobj != NULL
f5385ebf 16084 && (h->needs_plt
34e77a92 16085 || h->type == STT_GNU_IFUNC
60d67dc8 16086 || h->is_weakalias
f5385ebf
AM		 16087 || (h->def_dynamic
16088 && h->ref_regular
16089 && !h->def_regular)));
252b5132 16090
b7693d02
DJ		 16091 eh = (struct elf32_arm_link_hash_entry *) h;
16092
252b5132
RH		 16093 /* If this is a function, put it in the procedure linkage table. We
16094 will fill in the contents of the procedure linkage table later,
16095 when we know the address of the .got section. */
34e77a92 16096 if (h->type == STT_FUNC || h->type == STT_GNU_IFUNC || h->needs_plt)
252b5132 16097 {
34e77a92
RS		 16098 /* Calls to STT_GNU_IFUNC symbols always use a PLT, even if the
16099 symbol binds locally. */
5e681ec4 16100 if (h->plt.refcount <= 0
34e77a92
RS		 16101 || (h->type != STT_GNU_IFUNC
16102 && (SYMBOL_CALLS_LOCAL (info, h)
16103 || (ELF_ST_VISIBILITY (h->other) != STV_DEFAULT
16104 && h->root.type == bfd_link_hash_undefweak))))
252b5132
RH		 16105 {
16106 /* This case can occur if we saw a PLT32 reloc in an input
5e681ec4
PB		 16107 file, but the symbol was never referred to by a dynamic
16108 object, or if all references were garbage collected. In
16109 such a case, we don't actually need to build a procedure
16110 linkage table, and we can just do a PC24 reloc instead. */
16111 h->plt.offset = (bfd_vma) -1;
34e77a92
RS		 16112 eh->plt.thumb_refcount = 0;
16113 eh->plt.maybe_thumb_refcount = 0;
16114 eh->plt.noncall_refcount = 0;
f5385ebf 16115 h->needs_plt = 0;
252b5132
RH		 16116 }
16117
b34976b6 16118 return TRUE;
252b5132 16119 }
5e681ec4 16120 else
b7693d02
DJ		 16121 {
16122 /* It's possible that we incorrectly decided a .plt reloc was
16123 needed for an R_ARM_PC24 or similar reloc to a non-function sym
16124 in check_relocs. We can't decide accurately between function
16125 and non-function syms in check-relocs; Objects loaded later in
16126 the link may change h->type. So fix it now. */
16127 h->plt.offset = (bfd_vma) -1;
34e77a92
RS		 16128 eh->plt.thumb_refcount = 0;
16129 eh->plt.maybe_thumb_refcount = 0;
16130 eh->plt.noncall_refcount = 0;
b7693d02 16131 }
252b5132
RH		 16132
16133 /* If this is a weak symbol, and there is a real definition, the
16134 processor independent code will have arranged for us to see the
16135 real definition first, and we can just use the same value. */
60d67dc8 16136 if (h->is_weakalias)
252b5132 16137 {
60d67dc8
AM		 16138 struct elf_link_hash_entry *def = weakdef (h);
16139 BFD_ASSERT (def->root.type == bfd_link_hash_defined);
16140 h->root.u.def.section = def->root.u.def.section;
16141 h->root.u.def.value = def->root.u.def.value;
b34976b6 16142 return TRUE;
252b5132
RH		 16143 }
16144
ba93b8ac
DJ		 16145 /* If there are no non-GOT references, we do not need a copy
16146 relocation. */
16147 if (!h->non_got_ref)
16148 return TRUE;
16149
252b5132
RH		 16150 /* This is a reference to a symbol defined by a dynamic object which
16151 is not a function. */
16152
16153 /* If we are creating a shared library, we must presume that the
16154 only references to the symbol are via the global offset table.
16155 For such cases we need not do anything here; the relocations will
67687978
PB		 16156 be handled correctly by relocate_section. Relocatable executables
16157 can reference data in shared objects directly, so we don't need to
16158 do anything here. */
0e1862bb 16159 if (bfd_link_pic (info) || globals->root.is_relocatable_executable)
b34976b6 16160 return TRUE;
252b5132
RH		 16161
16162 /* We must allocate the symbol in our .dynbss section, which will
16163 become part of the .bss section of the executable. There will be
16164 an entry for this symbol in the .dynsym section. The dynamic
16165 object will contain position independent code, so all references
16166 from the dynamic object to this symbol will go through the global
16167 offset table. The dynamic linker will use the .dynsym entry to
16168 determine the address it must put in the global offset table, so
16169 both the dynamic object and the regular object will refer to the
16170 same memory location for the variable. */
5522f910
NC		 16171 /* If allowed, we must generate a R_ARM_COPY reloc to tell the dynamic
16172 linker to copy the initial value out of the dynamic object and into
16173 the runtime process image. We need to remember the offset into the
00a97672 16174 .rel(a).bss section we are going to use. */
5474d94f
AM		 16175 if ((h->root.u.def.section->flags & SEC_READONLY) != 0)
16176 {
16177 s = globals->root.sdynrelro;
16178 srel = globals->root.sreldynrelro;
16179 }
16180 else
16181 {
16182 s = globals->root.sdynbss;
16183 srel = globals->root.srelbss;
16184 }
5522f910
NC		 16185 if (info->nocopyreloc == 0
16186 && (h->root.u.def.section->flags & SEC_ALLOC) != 0
5522f910 16187 && h->size != 0)
252b5132 16188 {
47beaa6a 16189 elf32_arm_allocate_dynrelocs (info, srel, 1);
f5385ebf 16190 h->needs_copy = 1;
252b5132
RH		 16191 }
16192
6cabe1ea 16193 return _bfd_elf_adjust_dynamic_copy (info, h, s);
252b5132
RH		 16194}
16195
5e681ec4
PB		 16196/* Allocate space in .plt, .got and associated reloc sections for
16197 dynamic relocs. */
16198
16199static bfd_boolean
47beaa6a 16200allocate_dynrelocs_for_symbol (struct elf_link_hash_entry *h, void * inf)
5e681ec4
PB		 16201{
16202 struct bfd_link_info *info;
16203 struct elf32_arm_link_hash_table *htab;
16204 struct elf32_arm_link_hash_entry *eh;
0bdcacaf 16205 struct elf_dyn_relocs *p;
5e681ec4
PB		 16206
16207 if (h->root.type == bfd_link_hash_indirect)
16208 return TRUE;
16209
e6a6bb22
AM		 16210 eh = (struct elf32_arm_link_hash_entry *) h;
16211
5e681ec4
PB		 16212 info = (struct bfd_link_info *) inf;
16213 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 16214 if (htab == NULL)
16215 return FALSE;
5e681ec4 16216
34e77a92 16217 if ((htab->root.dynamic_sections_created || h->type == STT_GNU_IFUNC)
5e681ec4
PB		 16218 && h->plt.refcount > 0)
16219 {
16220 /* Make sure this symbol is output as a dynamic symbol.
16221 Undefined weak syms won't yet be marked as dynamic. */
6c699715
RL		 16222 if (h->dynindx == -1 && !h->forced_local
16223 && h->root.type == bfd_link_hash_undefweak)
5e681ec4 16224 {
c152c796 16225 if (! bfd_elf_link_record_dynamic_symbol (info, h))
5e681ec4
PB		 16226 return FALSE;
16227 }
16228
34e77a92
RS		 16229 /* If the call in the PLT entry binds locally, the associated
16230 GOT entry should use an R_ARM_IRELATIVE relocation instead of
16231 the usual R_ARM_JUMP_SLOT. Put it in the .iplt section rather
16232 than the .plt section. */
16233 if (h->type == STT_GNU_IFUNC && SYMBOL_CALLS_LOCAL (info, h))
16234 {
16235 eh->is_iplt = 1;
16236 if (eh->plt.noncall_refcount == 0
16237 && SYMBOL_REFERENCES_LOCAL (info, h))
16238 /* All non-call references can be resolved directly.
16239 This means that they can (and in some cases, must)
16240 resolve directly to the run-time target, rather than
16241 to the PLT. That in turns means that any .got entry
16242 would be equal to the .igot.plt entry, so there's
16243 no point having both. */
16244 h->got.refcount = 0;
16245 }
16246
0e1862bb 16247 if (bfd_link_pic (info)
34e77a92 16248 || eh->is_iplt
7359ea65 16249 || WILL_CALL_FINISH_DYNAMIC_SYMBOL (1, 0, h))
5e681ec4 16250 {
34e77a92 16251 elf32_arm_allocate_plt_entry (info, eh->is_iplt, &h->plt, &eh->plt);
b7693d02 16252
5e681ec4
PB		 16253 /* If this symbol is not defined in a regular file, and we are
16254 not generating a shared library, then set the symbol to this
16255 location in the .plt. This is required to make function
16256 pointers compare as equal between the normal executable and
16257 the shared library. */
0e1862bb 16258 if (! bfd_link_pic (info)
f5385ebf 16259 && !h->def_regular)
5e681ec4 16260 {
34e77a92 16261 h->root.u.def.section = htab->root.splt;
5e681ec4 16262 h->root.u.def.value = h->plt.offset;
5e681ec4 16263
67d74e43
DJ		 16264 /* Make sure the function is not marked as Thumb, in case
16265 it is the target of an ABS32 relocation, which will
16266 point to the PLT entry. */
39d911fc 16267 ARM_SET_SYM_BRANCH_TYPE (h->target_internal, ST_BRANCH_TO_ARM);
67d74e43 16268 }
022f8312 16269
00a97672
RS		 16270 /* VxWorks executables have a second set of relocations for
16271 each PLT entry. They go in a separate relocation section,
16272 which is processed by the kernel loader. */
0e1862bb 16273 if (htab->vxworks_p && !bfd_link_pic (info))
00a97672
RS		 16274 {
16275 /* There is a relocation for the initial PLT entry:
16276 an R_ARM_32 relocation for _GLOBAL_OFFSET_TABLE_. */
16277 if (h->plt.offset == htab->plt_header_size)
47beaa6a 16278 elf32_arm_allocate_dynrelocs (info, htab->srelplt2, 1);
00a97672
RS		 16279
16280 /* There are two extra relocations for each subsequent
16281 PLT entry: an R_ARM_32 relocation for the GOT entry,
16282 and an R_ARM_32 relocation for the PLT entry. */
47beaa6a 16283 elf32_arm_allocate_dynrelocs (info, htab->srelplt2, 2);
00a97672 16284 }
5e681ec4
PB		 16285 }
16286 else
16287 {
16288 h->plt.offset = (bfd_vma) -1;
f5385ebf 16289 h->needs_plt = 0;
5e681ec4
PB		 16290 }
16291 }
16292 else
16293 {
16294 h->plt.offset = (bfd_vma) -1;
f5385ebf 16295 h->needs_plt = 0;
5e681ec4
PB		 16296 }
16297
0855e32b
NS		 16298 eh = (struct elf32_arm_link_hash_entry *) h;
16299 eh->tlsdesc_got = (bfd_vma) -1;
16300
5e681ec4
PB		 16301 if (h->got.refcount > 0)
16302 {
16303 asection *s;
16304 bfd_boolean dyn;
ba93b8ac
DJ		 16305 int tls_type = elf32_arm_hash_entry (h)->tls_type;
16306 int indx;
5e681ec4
PB		 16307
16308 /* Make sure this symbol is output as a dynamic symbol.
16309 Undefined weak syms won't yet be marked as dynamic. */
e8b09b87 16310 if (htab->root.dynamic_sections_created && h->dynindx == -1 && !h->forced_local
6c699715 16311 && h->root.type == bfd_link_hash_undefweak)
5e681ec4 16312 {
c152c796 16313 if (! bfd_elf_link_record_dynamic_symbol (info, h))
5e681ec4
PB		 16314 return FALSE;
16315 }
16316
e5a52504
MM		 16317 if (!htab->symbian_p)
16318 {
362d30a1 16319 s = htab->root.sgot;
e5a52504 16320 h->got.offset = s->size;
ba93b8ac
DJ		 16321
16322 if (tls_type == GOT_UNKNOWN)
16323 abort ();
16324
16325 if (tls_type == GOT_NORMAL)
16326 /* Non-TLS symbols need one GOT slot. */
16327 s->size += 4;
16328 else
16329 {
99059e56
RM		 16330 if (tls_type & GOT_TLS_GDESC)
16331 {
0855e32b 16332 /* R_ARM_TLS_DESC needs 2 GOT slots. */
99059e56 16333 eh->tlsdesc_got
0855e32b
NS		 16334 = (htab->root.sgotplt->size
16335 - elf32_arm_compute_jump_table_size (htab));
99059e56
RM		 16336 htab->root.sgotplt->size += 8;
16337 h->got.offset = (bfd_vma) -2;
34e77a92 16338 /* plt.got_offset needs to know there's a TLS_DESC
0855e32b 16339 reloc in the middle of .got.plt. */
99059e56
RM		 16340 htab->num_tls_desc++;
16341 }
0855e32b 16342
ba93b8ac 16343 if (tls_type & GOT_TLS_GD)
0855e32b 16344 {
5c5a4843
CL		 16345 /* R_ARM_TLS_GD32 and R_ARM_TLS_GD32_FDPIC need two
16346 consecutive GOT slots. If the symbol is both GD
16347 and GDESC, got.offset may have been
16348 overwritten. */
0855e32b
NS		 16349 h->got.offset = s->size;
16350 s->size += 8;
16351 }
16352
ba93b8ac 16353 if (tls_type & GOT_TLS_IE)
5c5a4843
CL		 16354 /* R_ARM_TLS_IE32/R_ARM_TLS_IE32_FDPIC need one GOT
16355 slot. */
ba93b8ac
DJ		 16356 s->size += 4;
16357 }
16358
e5a52504 16359 dyn = htab->root.dynamic_sections_created;
ba93b8ac
DJ		 16360
16361 indx = 0;
0e1862bb
L		 16362 if (WILL_CALL_FINISH_DYNAMIC_SYMBOL (dyn,
16363 bfd_link_pic (info),
16364 h)
16365 && (!bfd_link_pic (info)
ba93b8ac
DJ		 16366 || !SYMBOL_REFERENCES_LOCAL (info, h)))
16367 indx = h->dynindx;
16368
16369 if (tls_type != GOT_NORMAL
9cb09e33 16370 && (bfd_link_dll (info) || indx != 0)
ba93b8ac
DJ		 16371 && (ELF_ST_VISIBILITY (h->other) == STV_DEFAULT
16372 || h->root.type != bfd_link_hash_undefweak))
16373 {
16374 if (tls_type & GOT_TLS_IE)
47beaa6a 16375 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
ba93b8ac
DJ		 16376
16377 if (tls_type & GOT_TLS_GD)
47beaa6a 16378 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
ba93b8ac 16379
b38cadfb 16380 if (tls_type & GOT_TLS_GDESC)
0855e32b 16381 {
47beaa6a 16382 elf32_arm_allocate_dynrelocs (info, htab->root.srelplt, 1);
0855e32b
NS		 16383 /* GDESC needs a trampoline to jump to. */
16384 htab->tls_trampoline = -1;
16385 }
16386
16387 /* Only GD needs it. GDESC just emits one relocation per
16388 2 entries. */
b38cadfb 16389 if ((tls_type & GOT_TLS_GD) && indx != 0)
47beaa6a 16390 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
ba93b8ac 16391 }
e8b09b87
CL		 16392 else if (((indx != -1) || htab->fdpic_p)
16393 && !SYMBOL_REFERENCES_LOCAL (info, h))
b436d854
RS		 16394 {
16395 if (htab->root.dynamic_sections_created)
16396 /* Reserve room for the GOT entry's R_ARM_GLOB_DAT relocation. */
16397 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
16398 }
34e77a92
RS		 16399 else if (h->type == STT_GNU_IFUNC
16400 && eh->plt.noncall_refcount == 0)
16401 /* No non-call references resolve the STT_GNU_IFUNC's PLT entry;
16402 they all resolve dynamically instead. Reserve room for the
16403 GOT entry's R_ARM_IRELATIVE relocation. */
16404 elf32_arm_allocate_irelocs (info, htab->root.srelgot, 1);
0e1862bb 16405 else if (bfd_link_pic (info)
7f026732 16406 && !UNDEFWEAK_NO_DYNAMIC_RELOC (info, h))
b436d854 16407 /* Reserve room for the GOT entry's R_ARM_RELATIVE relocation. */
47beaa6a 16408 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
e8b09b87
CL		 16409 else if (htab->fdpic_p && tls_type == GOT_NORMAL)
16410 /* Reserve room for rofixup for FDPIC executable. */
16411 /* TLS relocs do not need space since they are completely
16412 resolved. */
16413 htab->srofixup->size += 4;
e5a52504 16414 }
5e681ec4
PB		 16415 }
16416 else
16417 h->got.offset = (bfd_vma) -1;
16418
e8b09b87
CL		 16419 /* FDPIC support. */
16420 if (eh->fdpic_cnts.gotofffuncdesc_cnt > 0)
16421 {
16422 /* Symbol musn't be exported. */
16423 if (h->dynindx != -1)
16424 abort();
16425
16426 /* We only allocate one function descriptor with its associated relocation. */
16427 if (eh->fdpic_cnts.funcdesc_offset == -1)
16428 {
16429 asection *s = htab->root.sgot;
16430
16431 eh->fdpic_cnts.funcdesc_offset = s->size;
16432 s->size += 8;
16433 /* We will add an R_ARM_FUNCDESC_VALUE relocation or two rofixups. */
16434 if (bfd_link_pic(info))
16435 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
16436 else
16437 htab->srofixup->size += 8;
16438 }
16439 }
16440
16441 if (eh->fdpic_cnts.gotfuncdesc_cnt > 0)
16442 {
16443 asection *s = htab->root.sgot;
16444
16445 if (htab->root.dynamic_sections_created && h->dynindx == -1
16446 && !h->forced_local)
16447 if (! bfd_elf_link_record_dynamic_symbol (info, h))
16448 return FALSE;
16449
16450 if (h->dynindx == -1)
16451 {
16452 /* We only allocate one function descriptor with its associated relocation. q */
16453 if (eh->fdpic_cnts.funcdesc_offset == -1)
16454 {
16455
16456 eh->fdpic_cnts.funcdesc_offset = s->size;
16457 s->size += 8;
16458 /* We will add an R_ARM_FUNCDESC_VALUE relocation or two rofixups. */
16459 if (bfd_link_pic(info))
16460 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
16461 else
16462 htab->srofixup->size += 8;
16463 }
16464 }
16465
16466 /* Add one entry into the GOT and a R_ARM_FUNCDESC or
16467 R_ARM_RELATIVE/rofixup relocation on it. */
16468 eh->fdpic_cnts.gotfuncdesc_offset = s->size;
16469 s->size += 4;
16470 if (h->dynindx == -1 && !bfd_link_pic(info))
4b24dd1a 16471 htab->srofixup->size += 4;
e8b09b87 16472 else
4b24dd1a 16473 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
e8b09b87
CL		 16474 }
16475
16476 if (eh->fdpic_cnts.funcdesc_cnt > 0)
16477 {
16478 if (htab->root.dynamic_sections_created && h->dynindx == -1
16479 && !h->forced_local)
16480 if (! bfd_elf_link_record_dynamic_symbol (info, h))
16481 return FALSE;
16482
16483 if (h->dynindx == -1)
16484 {
16485 /* We only allocate one function descriptor with its associated relocation. */
16486 if (eh->fdpic_cnts.funcdesc_offset == -1)
16487 {
16488 asection *s = htab->root.sgot;
16489
16490 eh->fdpic_cnts.funcdesc_offset = s->size;
16491 s->size += 8;
16492 /* We will add an R_ARM_FUNCDESC_VALUE relocation or two rofixups. */
16493 if (bfd_link_pic(info))
16494 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
16495 else
16496 htab->srofixup->size += 8;
16497 }
16498 }
16499 if (h->dynindx == -1 && !bfd_link_pic(info))
16500 {
16501 /* For FDPIC executable we replace R_ARM_RELATIVE with a rofixup. */
16502 htab->srofixup->size += 4 * eh->fdpic_cnts.funcdesc_cnt;
16503 }
16504 else
16505 {
16506 /* Will need one dynamic reloc per reference. will be either
16507 R_ARM_FUNCDESC or R_ARM_RELATIVE for hidden symbols. */
16508 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot,
16509 eh->fdpic_cnts.funcdesc_cnt);
16510 }
16511 }
16512
a4fd1a8e
PB		 16513 /* Allocate stubs for exported Thumb functions on v4t. */
16514 if (!htab->use_blx && h->dynindx != -1
0eaedd0e 16515 && h->def_regular
39d911fc 16516 && ARM_GET_SYM_BRANCH_TYPE (h->target_internal) == ST_BRANCH_TO_THUMB
a4fd1a8e
PB		 16517 && ELF_ST_VISIBILITY (h->other) == STV_DEFAULT)
16518 {
16519 struct elf_link_hash_entry * th;
16520 struct bfd_link_hash_entry * bh;
16521 struct elf_link_hash_entry * myh;
16522 char name[1024];
16523 asection *s;
16524 bh = NULL;
16525 /* Create a new symbol to regist the real location of the function. */
16526 s = h->root.u.def.section;
906e58ca 16527 sprintf (name, "__real_%s", h->root.root.string);
a4fd1a8e
PB		 16528 _bfd_generic_link_add_one_symbol (info, s->owner,
16529 name, BSF_GLOBAL, s,
16530 h->root.u.def.value,
16531 NULL, TRUE, FALSE, &bh);
16532
16533 myh = (struct elf_link_hash_entry *) bh;
35fc36a8 16534 myh->type = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
a4fd1a8e 16535 myh->forced_local = 1;
39d911fc 16536 ARM_SET_SYM_BRANCH_TYPE (myh->target_internal, ST_BRANCH_TO_THUMB);
a4fd1a8e
PB		 16537 eh->export_glue = myh;
16538 th = record_arm_to_thumb_glue (info, h);
16539 /* Point the symbol at the stub. */
16540 h->type = ELF_ST_INFO (ELF_ST_BIND (h->type), STT_FUNC);
39d911fc 16541 ARM_SET_SYM_BRANCH_TYPE (h->target_internal, ST_BRANCH_TO_ARM);
a4fd1a8e
PB		 16542 h->root.u.def.section = th->root.u.def.section;
16543 h->root.u.def.value = th->root.u.def.value & ~1;
16544 }
16545
190eb1dd 16546 if (h->dyn_relocs == NULL)
5e681ec4
PB		 16547 return TRUE;
16548
16549 /* In the shared -Bsymbolic case, discard space allocated for
16550 dynamic pc-relative relocs against symbols which turn out to be
16551 defined in regular objects. For the normal shared case, discard
16552 space for pc-relative relocs that have become local due to symbol
16553 visibility changes. */
16554
e8b09b87 16555 if (bfd_link_pic (info) || htab->root.is_relocatable_executable || htab->fdpic_p)
5e681ec4 16556 {
469a3493
RM		 16557 /* Relocs that use pc_count are PC-relative forms, which will appear
16558 on something like ".long foo - ." or "movw REG, foo - .". We want
16559 calls to protected symbols to resolve directly to the function
16560 rather than going via the plt. If people want function pointer
16561 comparisons to work as expected then they should avoid writing
16562 assembly like ".long foo - .". */
ba93b8ac
DJ		 16563 if (SYMBOL_CALLS_LOCAL (info, h))
16564 {
0bdcacaf 16565 struct elf_dyn_relocs **pp;
ba93b8ac 16566
190eb1dd 16567 for (pp = &h->dyn_relocs; (p = *pp) != NULL; )
ba93b8ac
DJ		 16568 {
16569 p->count -= p->pc_count;
16570 p->pc_count = 0;
16571 if (p->count == 0)
16572 *pp = p->next;
16573 else
16574 pp = &p->next;
16575 }
16576 }
16577
4dfe6ac6 16578 if (htab->vxworks_p)
3348747a 16579 {
0bdcacaf 16580 struct elf_dyn_relocs **pp;
3348747a 16581
190eb1dd 16582 for (pp = &h->dyn_relocs; (p = *pp) != NULL; )
3348747a 16583 {
0bdcacaf 16584 if (strcmp (p->sec->output_section->name, ".tls_vars") == 0)
3348747a
NS		 16585 *pp = p->next;
16586 else
16587 pp = &p->next;
16588 }
16589 }
16590
ba93b8ac 16591 /* Also discard relocs on undefined weak syms with non-default
99059e56 16592 visibility. */
190eb1dd 16593 if (h->dyn_relocs != NULL
5e681ec4 16594 && h->root.type == bfd_link_hash_undefweak)
22d606e9 16595 {
95b03e4a
L		 16596 if (ELF_ST_VISIBILITY (h->other) != STV_DEFAULT
16597 || UNDEFWEAK_NO_DYNAMIC_RELOC (info, h))
190eb1dd 16598 h->dyn_relocs = NULL;
22d606e9
AM		 16599
16600 /* Make sure undefined weak symbols are output as a dynamic
16601 symbol in PIEs. */
e8b09b87 16602 else if (htab->root.dynamic_sections_created && h->dynindx == -1
22d606e9
AM		 16603 && !h->forced_local)
16604 {
16605 if (! bfd_elf_link_record_dynamic_symbol (info, h))
16606 return FALSE;
16607 }
16608 }
16609
67687978
PB		 16610 else if (htab->root.is_relocatable_executable && h->dynindx == -1
16611 && h->root.type == bfd_link_hash_new)
16612 {
16613 /* Output absolute symbols so that we can create relocations
16614 against them. For normal symbols we output a relocation
16615 against the section that contains them. */
16616 if (! bfd_elf_link_record_dynamic_symbol (info, h))
16617 return FALSE;
16618 }
16619
5e681ec4
PB		 16620 }
16621 else
16622 {
16623 /* For the non-shared case, discard space for relocs against
16624 symbols which turn out to need copy relocs or are not
16625 dynamic. */
16626
f5385ebf
AM		 16627 if (!h->non_got_ref
16628 && ((h->def_dynamic
16629 && !h->def_regular)
5e681ec4
PB		 16630 || (htab->root.dynamic_sections_created
16631 && (h->root.type == bfd_link_hash_undefweak
16632 || h->root.type == bfd_link_hash_undefined))))
16633 {
16634 /* Make sure this symbol is output as a dynamic symbol.
16635 Undefined weak syms won't yet be marked as dynamic. */
6c699715
RL		 16636 if (h->dynindx == -1 && !h->forced_local
16637 && h->root.type == bfd_link_hash_undefweak)
5e681ec4 16638 {
c152c796 16639 if (! bfd_elf_link_record_dynamic_symbol (info, h))
5e681ec4
PB		 16640 return FALSE;
16641 }
16642
16643 /* If that succeeded, we know we'll be keeping all the
16644 relocs. */
16645 if (h->dynindx != -1)
16646 goto keep;
16647 }
16648
190eb1dd 16649 h->dyn_relocs = NULL;
5e681ec4
PB		 16650
16651 keep: ;
16652 }
16653
16654 /* Finally, allocate space. */
190eb1dd 16655 for (p = h->dyn_relocs; p != NULL; p = p->next)
5e681ec4 16656 {
0bdcacaf 16657 asection *sreloc = elf_section_data (p->sec)->sreloc;
e8b09b87 16658
34e77a92
RS		 16659 if (h->type == STT_GNU_IFUNC
16660 && eh->plt.noncall_refcount == 0
16661 && SYMBOL_REFERENCES_LOCAL (info, h))
16662 elf32_arm_allocate_irelocs (info, sreloc, p->count);
e8b09b87
CL		 16663 else if (h->dynindx != -1 && (!bfd_link_pic(info) || !info->symbolic || !h->def_regular))
16664 elf32_arm_allocate_dynrelocs (info, sreloc, p->count);
16665 else if (htab->fdpic_p && !bfd_link_pic(info))
16666 htab->srofixup->size += 4 * p->count;
34e77a92
RS		 16667 else
16668 elf32_arm_allocate_dynrelocs (info, sreloc, p->count);
5e681ec4
PB		 16669 }
16670
16671 return TRUE;
16672}
16673
d504ffc8
DJ		 16674void
16675bfd_elf32_arm_set_byteswap_code (struct bfd_link_info *info,
16676 int byteswap_code)
16677{
16678 struct elf32_arm_link_hash_table *globals;
16679
16680 globals = elf32_arm_hash_table (info);
4dfe6ac6
NC		 16681 if (globals == NULL)
16682 return;
16683
d504ffc8
DJ		 16684 globals->byteswap_code = byteswap_code;
16685}
16686
252b5132
RH		 16687/* Set the sizes of the dynamic sections. */
16688
b34976b6 16689static bfd_boolean
57e8b36a
NC		 16690elf32_arm_size_dynamic_sections (bfd * output_bfd ATTRIBUTE_UNUSED,
16691 struct bfd_link_info * info)
252b5132
RH		 16692{
16693 bfd * dynobj;
16694 asection * s;
b34976b6
AM		 16695 bfd_boolean plt;
16696 bfd_boolean relocs;
5e681ec4
PB		 16697 bfd *ibfd;
16698 struct elf32_arm_link_hash_table *htab;
252b5132 16699
5e681ec4 16700 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 16701 if (htab == NULL)
16702 return FALSE;
16703
252b5132
RH		 16704 dynobj = elf_hash_table (info)->dynobj;
16705 BFD_ASSERT (dynobj != NULL);
39b41c9c 16706 check_use_blx (htab);
252b5132
RH		 16707
16708 if (elf_hash_table (info)->dynamic_sections_created)
16709 {
16710 /* Set the contents of the .interp section to the interpreter. */
9b8b325a 16711 if (bfd_link_executable (info) && !info->nointerp)
252b5132 16712 {
3d4d4302 16713 s = bfd_get_linker_section (dynobj, ".interp");
252b5132 16714 BFD_ASSERT (s != NULL);
eea6121a 16715 s->size = sizeof ELF_DYNAMIC_INTERPRETER;
252b5132
RH		 16716 s->contents = (unsigned char *) ELF_DYNAMIC_INTERPRETER;
16717 }
16718 }
5e681ec4
PB		 16719
16720 /* Set up .got offsets for local syms, and space for local dynamic
16721 relocs. */
c72f2fb2 16722 for (ibfd = info->input_bfds; ibfd != NULL; ibfd = ibfd->link.next)
252b5132 16723 {
5e681ec4
PB		 16724 bfd_signed_vma *local_got;
16725 bfd_signed_vma *end_local_got;
34e77a92 16726 struct arm_local_iplt_info **local_iplt_ptr, *local_iplt;
5e681ec4 16727 char *local_tls_type;
0855e32b 16728 bfd_vma *local_tlsdesc_gotent;
5e681ec4
PB		 16729 bfd_size_type locsymcount;
16730 Elf_Internal_Shdr *symtab_hdr;
16731 asection *srel;
4dfe6ac6 16732 bfd_boolean is_vxworks = htab->vxworks_p;
34e77a92 16733 unsigned int symndx;
e8b09b87 16734 struct fdpic_local *local_fdpic_cnts;
5e681ec4 16735
0ffa91dd 16736 if (! is_arm_elf (ibfd))
5e681ec4
PB		 16737 continue;
16738
16739 for (s = ibfd->sections; s != NULL; s = s->next)
16740 {
0bdcacaf 16741 struct elf_dyn_relocs *p;
5e681ec4 16742
0bdcacaf 16743 for (p = (struct elf_dyn_relocs *)
99059e56 16744 elf_section_data (s)->local_dynrel; p != NULL; p = p->next)
5e681ec4 16745 {
0bdcacaf
RS		 16746 if (!bfd_is_abs_section (p->sec)
16747 && bfd_is_abs_section (p->sec->output_section))
5e681ec4
PB		 16748 {
16749 /* Input section has been discarded, either because
16750 it is a copy of a linkonce section or due to
16751 linker script /DISCARD/, so we'll be discarding
16752 the relocs too. */
16753 }
3348747a 16754 else if (is_vxworks
0bdcacaf 16755 && strcmp (p->sec->output_section->name,
3348747a
NS		 16756 ".tls_vars") == 0)
16757 {
16758 /* Relocations in vxworks .tls_vars sections are
16759 handled specially by the loader. */
16760 }
5e681ec4
PB		 16761 else if (p->count != 0)
16762 {
0bdcacaf 16763 srel = elf_section_data (p->sec)->sreloc;
e8b09b87
CL		 16764 if (htab->fdpic_p && !bfd_link_pic(info))
16765 htab->srofixup->size += 4 * p->count;
16766 else
16767 elf32_arm_allocate_dynrelocs (info, srel, p->count);
0bdcacaf 16768 if ((p->sec->output_section->flags & SEC_READONLY) != 0)
5e681ec4
PB		 16769 info->flags |= DF_TEXTREL;
16770 }
16771 }
16772 }
16773
16774 local_got = elf_local_got_refcounts (ibfd);
16775 if (!local_got)
16776 continue;
16777
0ffa91dd 16778 symtab_hdr = & elf_symtab_hdr (ibfd);
5e681ec4
PB		 16779 locsymcount = symtab_hdr->sh_info;
16780 end_local_got = local_got + locsymcount;
34e77a92 16781 local_iplt_ptr = elf32_arm_local_iplt (ibfd);
ba93b8ac 16782 local_tls_type = elf32_arm_local_got_tls_type (ibfd);
0855e32b 16783 local_tlsdesc_gotent = elf32_arm_local_tlsdesc_gotent (ibfd);
e8b09b87 16784 local_fdpic_cnts = elf32_arm_local_fdpic_cnts (ibfd);
34e77a92 16785 symndx = 0;
362d30a1
RS		 16786 s = htab->root.sgot;
16787 srel = htab->root.srelgot;
0855e32b 16788 for (; local_got < end_local_got;
34e77a92 16789 ++local_got, ++local_iplt_ptr, ++local_tls_type,
e8b09b87 16790 ++local_tlsdesc_gotent, ++symndx, ++local_fdpic_cnts)
5e681ec4 16791 {
0855e32b 16792 *local_tlsdesc_gotent = (bfd_vma) -1;
34e77a92 16793 local_iplt = *local_iplt_ptr;
e8b09b87
CL		 16794
16795 /* FDPIC support. */
16796 if (local_fdpic_cnts->gotofffuncdesc_cnt > 0)
16797 {
16798 if (local_fdpic_cnts->funcdesc_offset == -1)
16799 {
16800 local_fdpic_cnts->funcdesc_offset = s->size;
16801 s->size += 8;
16802
16803 /* We will add an R_ARM_FUNCDESC_VALUE relocation or two rofixups. */
16804 if (bfd_link_pic(info))
16805 elf32_arm_allocate_dynrelocs (info, srel, 1);
16806 else
16807 htab->srofixup->size += 8;
16808 }
16809 }
16810
16811 if (local_fdpic_cnts->funcdesc_cnt > 0)
16812 {
16813 if (local_fdpic_cnts->funcdesc_offset == -1)
16814 {
16815 local_fdpic_cnts->funcdesc_offset = s->size;
16816 s->size += 8;
16817
16818 /* We will add an R_ARM_FUNCDESC_VALUE relocation or two rofixups. */
16819 if (bfd_link_pic(info))
16820 elf32_arm_allocate_dynrelocs (info, srel, 1);
16821 else
16822 htab->srofixup->size += 8;
16823 }
16824
16825 /* We will add n R_ARM_RELATIVE relocations or n rofixups. */
16826 if (bfd_link_pic(info))
16827 elf32_arm_allocate_dynrelocs (info, srel, local_fdpic_cnts->funcdesc_cnt);
16828 else
16829 htab->srofixup->size += 4 * local_fdpic_cnts->funcdesc_cnt;
16830 }
16831
34e77a92
RS		 16832 if (local_iplt != NULL)
16833 {
16834 struct elf_dyn_relocs *p;
16835
16836 if (local_iplt->root.refcount > 0)
16837 {
16838 elf32_arm_allocate_plt_entry (info, TRUE,
16839 &local_iplt->root,
16840 &local_iplt->arm);
16841 if (local_iplt->arm.noncall_refcount == 0)
16842 /* All references to the PLT are calls, so all
16843 non-call references can resolve directly to the
16844 run-time target. This means that the .got entry
16845 would be the same as the .igot.plt entry, so there's
16846 no point creating both. */
16847 *local_got = 0;
16848 }
16849 else
16850 {
16851 BFD_ASSERT (local_iplt->arm.noncall_refcount == 0);
16852 local_iplt->root.offset = (bfd_vma) -1;
16853 }
16854
16855 for (p = local_iplt->dyn_relocs; p != NULL; p = p->next)
16856 {
16857 asection *psrel;
16858
16859 psrel = elf_section_data (p->sec)->sreloc;
16860 if (local_iplt->arm.noncall_refcount == 0)
16861 elf32_arm_allocate_irelocs (info, psrel, p->count);
16862 else
16863 elf32_arm_allocate_dynrelocs (info, psrel, p->count);
16864 }
16865 }
5e681ec4
PB		 16866 if (*local_got > 0)
16867 {
34e77a92
RS		 16868 Elf_Internal_Sym *isym;
16869
eea6121a 16870 *local_got = s->size;
ba93b8ac
DJ		 16871 if (*local_tls_type & GOT_TLS_GD)
16872 /* TLS_GD relocs need an 8-byte structure in the GOT. */
16873 s->size += 8;
0855e32b
NS		 16874 if (*local_tls_type & GOT_TLS_GDESC)
16875 {
16876 *local_tlsdesc_gotent = htab->root.sgotplt->size
16877 - elf32_arm_compute_jump_table_size (htab);
16878 htab->root.sgotplt->size += 8;
16879 *local_got = (bfd_vma) -2;
34e77a92 16880 /* plt.got_offset needs to know there's a TLS_DESC
0855e32b 16881 reloc in the middle of .got.plt. */
99059e56 16882 htab->num_tls_desc++;
0855e32b 16883 }
ba93b8ac
DJ		 16884 if (*local_tls_type & GOT_TLS_IE)
16885 s->size += 4;
ba93b8ac 16886
0855e32b
NS		 16887 if (*local_tls_type & GOT_NORMAL)
16888 {
16889 /* If the symbol is both GD and GDESC, *local_got
16890 may have been overwritten. */
16891 *local_got = s->size;
16892 s->size += 4;
16893 }
16894
34e77a92
RS		 16895 isym = bfd_sym_from_r_symndx (&htab->sym_cache, ibfd, symndx);
16896 if (isym == NULL)
16897 return FALSE;
16898
16899 /* If all references to an STT_GNU_IFUNC PLT are calls,
16900 then all non-call references, including this GOT entry,
16901 resolve directly to the run-time target. */
16902 if (ELF32_ST_TYPE (isym->st_info) == STT_GNU_IFUNC
16903 && (local_iplt == NULL
16904 || local_iplt->arm.noncall_refcount == 0))
16905 elf32_arm_allocate_irelocs (info, srel, 1);
e8b09b87 16906 else if (bfd_link_pic (info) || output_bfd->flags & DYNAMIC || htab->fdpic_p)
0855e32b 16907 {
e8b09b87 16908 if ((bfd_link_pic (info) && !(*local_tls_type & GOT_TLS_GDESC)))
3064e1ff 16909 elf32_arm_allocate_dynrelocs (info, srel, 1);
e8b09b87
CL		 16910 else if (htab->fdpic_p && *local_tls_type & GOT_NORMAL)
16911 htab->srofixup->size += 4;
99059e56 16912
e8b09b87
CL		 16913 if ((bfd_link_pic (info) || htab->fdpic_p)
16914 && *local_tls_type & GOT_TLS_GDESC)
3064e1ff
JB		 16915 {
16916 elf32_arm_allocate_dynrelocs (info,
16917 htab->root.srelplt, 1);
16918 htab->tls_trampoline = -1;
16919 }
0855e32b 16920 }
5e681ec4
PB		 16921 }
16922 else
16923 *local_got = (bfd_vma) -1;
16924 }
252b5132
RH		 16925 }
16926
ba93b8ac
DJ		 16927 if (htab->tls_ldm_got.refcount > 0)
16928 {
16929 /* Allocate two GOT entries and one dynamic relocation (if necessary)
5c5a4843 16930 for R_ARM_TLS_LDM32/R_ARM_TLS_LDM32_FDPIC relocations. */
362d30a1
RS		 16931 htab->tls_ldm_got.offset = htab->root.sgot->size;
16932 htab->root.sgot->size += 8;
0e1862bb 16933 if (bfd_link_pic (info))
47beaa6a 16934 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
ba93b8ac
DJ		 16935 }
16936 else
16937 htab->tls_ldm_got.offset = -1;
16938
e8b09b87
CL		 16939 /* At the very end of the .rofixup section is a pointer to the GOT,
16940 reserve space for it. */
16941 if (htab->fdpic_p && htab->srofixup != NULL)
16942 htab->srofixup->size += 4;
16943
5e681ec4
PB		 16944 /* Allocate global sym .plt and .got entries, and space for global
16945 sym dynamic relocs. */
47beaa6a 16946 elf_link_hash_traverse (& htab->root, allocate_dynrelocs_for_symbol, info);
252b5132 16947
d504ffc8 16948 /* Here we rummage through the found bfds to collect glue information. */
c72f2fb2 16949 for (ibfd = info->input_bfds; ibfd != NULL; ibfd = ibfd->link.next)
c7b8f16e 16950 {
0ffa91dd 16951 if (! is_arm_elf (ibfd))
e44a2c9c
AM		 16952 continue;
16953
c7b8f16e
JB		 16954 /* Initialise mapping tables for code/data. */
16955 bfd_elf32_arm_init_maps (ibfd);
906e58ca 16956
c7b8f16e 16957 if (!bfd_elf32_arm_process_before_allocation (ibfd, info)
a504d23a
LA		 16958 || !bfd_elf32_arm_vfp11_erratum_scan (ibfd, info)
16959 || !bfd_elf32_arm_stm32l4xx_erratum_scan (ibfd, info))
90b6238f 16960 _bfd_error_handler (_("errors encountered processing file %pB"), ibfd);
c7b8f16e 16961 }
d504ffc8 16962
3e6b1042
DJ		 16963 /* Allocate space for the glue sections now that we've sized them. */
16964 bfd_elf32_arm_allocate_interworking_sections (info);
16965
0855e32b
NS		 16966 /* For every jump slot reserved in the sgotplt, reloc_count is
16967 incremented. However, when we reserve space for TLS descriptors,
16968 it's not incremented, so in order to compute the space reserved
16969 for them, it suffices to multiply the reloc count by the jump
16970 slot size. */
16971 if (htab->root.srelplt)
16972 htab->sgotplt_jump_table_size = elf32_arm_compute_jump_table_size(htab);
16973
16974 if (htab->tls_trampoline)
16975 {
16976 if (htab->root.splt->size == 0)
16977 htab->root.splt->size += htab->plt_header_size;
b38cadfb 16978
0855e32b
NS		 16979 htab->tls_trampoline = htab->root.splt->size;
16980 htab->root.splt->size += htab->plt_entry_size;
b38cadfb 16981
0855e32b 16982 /* If we're not using lazy TLS relocations, don't generate the
99059e56 16983 PLT and GOT entries they require. */
0855e32b
NS		 16984 if (!(info->flags & DF_BIND_NOW))
16985 {
16986 htab->dt_tlsdesc_got = htab->root.sgot->size;
16987 htab->root.sgot->size += 4;
16988
16989 htab->dt_tlsdesc_plt = htab->root.splt->size;
16990 htab->root.splt->size += 4 * ARRAY_SIZE (dl_tlsdesc_lazy_trampoline);
16991 }
16992 }
16993
252b5132
RH		 16994 /* The check_relocs and adjust_dynamic_symbol entry points have
16995 determined the sizes of the various dynamic sections. Allocate
16996 memory for them. */
b34976b6
AM		 16997 plt = FALSE;
16998 relocs = FALSE;
252b5132
RH		 16999 for (s = dynobj->sections; s != NULL; s = s->next)
17000 {
17001 const char * name;
252b5132
RH		 17002
17003 if ((s->flags & SEC_LINKER_CREATED) == 0)
17004 continue;
17005
17006 /* It's OK to base decisions on the section name, because none
17007 of the dynobj section names depend upon the input files. */
fd361982 17008 name = bfd_section_name (s);
252b5132 17009
34e77a92 17010 if (s == htab->root.splt)
252b5132 17011 {
c456f082
AM		 17012 /* Remember whether there is a PLT. */
17013 plt = s->size != 0;
252b5132 17014 }
0112cd26 17015 else if (CONST_STRNEQ (name, ".rel"))
252b5132 17016 {
c456f082 17017 if (s->size != 0)
252b5132 17018 {
252b5132 17019 /* Remember whether there are any reloc sections other
00a97672 17020 than .rel(a).plt and .rela.plt.unloaded. */
362d30a1 17021 if (s != htab->root.srelplt && s != htab->srelplt2)
b34976b6 17022 relocs = TRUE;
252b5132
RH		 17023
17024 /* We use the reloc_count field as a counter if we need
17025 to copy relocs into the output file. */
17026 s->reloc_count = 0;
17027 }
17028 }
34e77a92
RS		 17029 else if (s != htab->root.sgot
17030 && s != htab->root.sgotplt
17031 && s != htab->root.iplt
17032 && s != htab->root.igotplt
5474d94f 17033 && s != htab->root.sdynbss
e8b09b87
CL		 17034 && s != htab->root.sdynrelro
17035 && s != htab->srofixup)
252b5132
RH		 17036 {
17037 /* It's not one of our sections, so don't allocate space. */
17038 continue;
17039 }
17040
c456f082 17041 if (s->size == 0)
252b5132 17042 {
c456f082 17043 /* If we don't need this section, strip it from the
00a97672
RS		 17044 output file. This is mostly to handle .rel(a).bss and
17045 .rel(a).plt. We must create both sections in
c456f082
AM		 17046 create_dynamic_sections, because they must be created
17047 before the linker maps input sections to output
17048 sections. The linker does that before
17049 adjust_dynamic_symbol is called, and it is that
17050 function which decides whether anything needs to go
17051 into these sections. */
8423293d 17052 s->flags |= SEC_EXCLUDE;
252b5132
RH		 17053 continue;
17054 }
17055
c456f082
AM		 17056 if ((s->flags & SEC_HAS_CONTENTS) == 0)
17057 continue;
17058
252b5132 17059 /* Allocate memory for the section contents. */
21d799b5 17060 s->contents = (unsigned char *) bfd_zalloc (dynobj, s->size);
c456f082 17061 if (s->contents == NULL)
b34976b6 17062 return FALSE;
252b5132
RH		 17063 }
17064
17065 if (elf_hash_table (info)->dynamic_sections_created)
17066 {
17067 /* Add some entries to the .dynamic section. We fill in the
17068 values later, in elf32_arm_finish_dynamic_sections, but we
17069 must add the entries now so that we get the correct size for
17070 the .dynamic section. The DT_DEBUG entry is filled in by the
17071 dynamic linker and used by the debugger. */
dc810e39 17072#define add_dynamic_entry(TAG, VAL) \
5a580b3a 17073 _bfd_elf_add_dynamic_entry (info, TAG, VAL)
dc810e39 17074
0e1862bb 17075 if (bfd_link_executable (info))
252b5132 17076 {
dc810e39 17077 if (!add_dynamic_entry (DT_DEBUG, 0))
b34976b6 17078 return FALSE;
252b5132
RH		 17079 }
17080
17081 if (plt)
17082 {
dc810e39
AM		 17083 if ( !add_dynamic_entry (DT_PLTGOT, 0)
17084 || !add_dynamic_entry (DT_PLTRELSZ, 0)
00a97672
RS		 17085 || !add_dynamic_entry (DT_PLTREL,
17086 htab->use_rel ? DT_REL : DT_RELA)
dc810e39 17087 || !add_dynamic_entry (DT_JMPREL, 0))
b34976b6 17088 return FALSE;
0855e32b 17089
5025eb7c
AO		 17090 if (htab->dt_tlsdesc_plt
17091 && (!add_dynamic_entry (DT_TLSDESC_PLT,0)
17092 || !add_dynamic_entry (DT_TLSDESC_GOT,0)))
b38cadfb 17093 return FALSE;
252b5132
RH		 17094 }
17095
17096 if (relocs)
17097 {
00a97672
RS		 17098 if (htab->use_rel)
17099 {
17100 if (!add_dynamic_entry (DT_REL, 0)
17101 || !add_dynamic_entry (DT_RELSZ, 0)
17102 || !add_dynamic_entry (DT_RELENT, RELOC_SIZE (htab)))
17103 return FALSE;
17104 }
17105 else
17106 {
17107 if (!add_dynamic_entry (DT_RELA, 0)
17108 || !add_dynamic_entry (DT_RELASZ, 0)
17109 || !add_dynamic_entry (DT_RELAENT, RELOC_SIZE (htab)))
17110 return FALSE;
17111 }
252b5132
RH		 17112 }
17113
08d1f311
DJ		 17114 /* If any dynamic relocs apply to a read-only section,
17115 then we need a DT_TEXTREL entry. */
17116 if ((info->flags & DF_TEXTREL) == 0)
d49e5065
L		 17117 elf_link_hash_traverse (&htab->root,
17118 _bfd_elf_maybe_set_textrel, info);
08d1f311 17119
99e4ae17 17120 if ((info->flags & DF_TEXTREL) != 0)
252b5132 17121 {
dc810e39 17122 if (!add_dynamic_entry (DT_TEXTREL, 0))
b34976b6 17123 return FALSE;
252b5132 17124 }
7a2b07ff
NS		 17125 if (htab->vxworks_p
17126 && !elf_vxworks_add_dynamic_entries (output_bfd, info))
17127 return FALSE;
252b5132 17128 }
8532796c 17129#undef add_dynamic_entry
252b5132 17130
b34976b6 17131 return TRUE;
252b5132
RH		 17132}
17133
0855e32b
NS		 17134/* Size sections even though they're not dynamic. We use it to setup
17135 _TLS_MODULE_BASE_, if needed. */
17136
17137static bfd_boolean
17138elf32_arm_always_size_sections (bfd *output_bfd,
99059e56 17139 struct bfd_link_info *info)
0855e32b
NS		 17140{
17141 asection *tls_sec;
cb10292c
CL		 17142 struct elf32_arm_link_hash_table *htab;
17143
17144 htab = elf32_arm_hash_table (info);
0855e32b 17145
0e1862bb 17146 if (bfd_link_relocatable (info))
0855e32b
NS		 17147 return TRUE;
17148
17149 tls_sec = elf_hash_table (info)->tls_sec;
17150
17151 if (tls_sec)
17152 {
17153 struct elf_link_hash_entry *tlsbase;
17154
17155 tlsbase = elf_link_hash_lookup
17156 (elf_hash_table (info), "_TLS_MODULE_BASE_", TRUE, TRUE, FALSE);
17157
17158 if (tlsbase)
99059e56
RM		 17159 {
17160 struct bfd_link_hash_entry *bh = NULL;
0855e32b 17161 const struct elf_backend_data *bed
99059e56 17162 = get_elf_backend_data (output_bfd);
0855e32b 17163
99059e56 17164 if (!(_bfd_generic_link_add_one_symbol
0855e32b
NS		 17165 (info, output_bfd, "_TLS_MODULE_BASE_", BSF_LOCAL,
17166 tls_sec, 0, NULL, FALSE,
17167 bed->collect, &bh)))
17168 return FALSE;
b38cadfb 17169
99059e56
RM		 17170 tlsbase->type = STT_TLS;
17171 tlsbase = (struct elf_link_hash_entry *)bh;
17172 tlsbase->def_regular = 1;
17173 tlsbase->other = STV_HIDDEN;
17174 (*bed->elf_backend_hide_symbol) (info, tlsbase, TRUE);
0855e32b
NS		 17175 }
17176 }
cb10292c
CL		 17177
17178 if (htab->fdpic_p && !bfd_link_relocatable (info)
17179 && !bfd_elf_stack_segment_size (output_bfd, info,
17180 "__stacksize", DEFAULT_STACK_SIZE))
17181 return FALSE;
17182
0855e32b
NS		 17183 return TRUE;
17184}
17185
252b5132
RH		 17186/* Finish up dynamic symbol handling. We set the contents of various
17187 dynamic sections here. */
17188
b34976b6 17189static bfd_boolean
906e58ca
NC		 17190elf32_arm_finish_dynamic_symbol (bfd * output_bfd,
17191 struct bfd_link_info * info,
17192 struct elf_link_hash_entry * h,
17193 Elf_Internal_Sym * sym)
252b5132 17194{
e5a52504 17195 struct elf32_arm_link_hash_table *htab;
b7693d02 17196 struct elf32_arm_link_hash_entry *eh;
252b5132 17197
e5a52504 17198 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 17199 if (htab == NULL)
17200 return FALSE;
17201
b7693d02 17202 eh = (struct elf32_arm_link_hash_entry *) h;
252b5132
RH		 17203
17204 if (h->plt.offset != (bfd_vma) -1)
17205 {
34e77a92 17206 if (!eh->is_iplt)
e5a52504 17207 {
34e77a92 17208 BFD_ASSERT (h->dynindx != -1);
57460bcf
NC		 17209 if (! elf32_arm_populate_plt_entry (output_bfd, info, &h->plt, &eh->plt,
17210 h->dynindx, 0))
17211 return FALSE;
e5a52504 17212 }
57e8b36a 17213
f5385ebf 17214 if (!h->def_regular)
252b5132
RH		 17215 {
17216 /* Mark the symbol as undefined, rather than as defined in
3a635617 17217 the .plt section. */
252b5132 17218 sym->st_shndx = SHN_UNDEF;
3a635617 17219 /* If the symbol is weak we need to clear the value.
d982ba73
PB		 17220 Otherwise, the PLT entry would provide a definition for
17221 the symbol even if the symbol wasn't defined anywhere,
3a635617
WN		 17222 and so the symbol would never be NULL. Leave the value if
17223 there were any relocations where pointer equality matters
17224 (this is a clue for the dynamic linker, to make function
17225 pointer comparisons work between an application and shared
17226 library). */
97323ad1 17227 if (!h->ref_regular_nonweak || !h->pointer_equality_needed)
d982ba73 17228 sym->st_value = 0;
252b5132 17229 }
34e77a92
RS		 17230 else if (eh->is_iplt && eh->plt.noncall_refcount != 0)
17231 {
17232 /* At least one non-call relocation references this .iplt entry,
17233 so the .iplt entry is the function's canonical address. */
17234 sym->st_info = ELF_ST_INFO (ELF_ST_BIND (sym->st_info), STT_FUNC);
39d911fc 17235 ARM_SET_SYM_BRANCH_TYPE (sym->st_target_internal, ST_BRANCH_TO_ARM);
34e77a92
RS		 17236 sym->st_shndx = (_bfd_elf_section_from_bfd_section
17237 (output_bfd, htab->root.iplt->output_section));
17238 sym->st_value = (h->plt.offset
17239 + htab->root.iplt->output_section->vma
17240 + htab->root.iplt->output_offset);
17241 }
252b5132
RH		 17242 }
17243
f5385ebf 17244 if (h->needs_copy)
252b5132
RH		 17245 {
17246 asection * s;
947216bf 17247 Elf_Internal_Rela rel;
252b5132
RH		 17248
17249 /* This symbol needs a copy reloc. Set it up. */
252b5132
RH		 17250 BFD_ASSERT (h->dynindx != -1
17251 && (h->root.type == bfd_link_hash_defined
17252 || h->root.type == bfd_link_hash_defweak));
17253
00a97672 17254 rel.r_addend = 0;
252b5132
RH		 17255 rel.r_offset = (h->root.u.def.value
17256 + h->root.u.def.section->output_section->vma
17257 + h->root.u.def.section->output_offset);
17258 rel.r_info = ELF32_R_INFO (h->dynindx, R_ARM_COPY);
afbf7e8e 17259 if (h->root.u.def.section == htab->root.sdynrelro)
5474d94f
AM		 17260 s = htab->root.sreldynrelro;
17261 else
17262 s = htab->root.srelbss;
47beaa6a 17263 elf32_arm_add_dynreloc (output_bfd, info, s, &rel);
252b5132
RH		 17264 }
17265
00a97672 17266 /* Mark _DYNAMIC and _GLOBAL_OFFSET_TABLE_ as absolute. On VxWorks,
fac7bd64
CL		 17267 and for FDPIC, the _GLOBAL_OFFSET_TABLE_ symbol is not absolute:
17268 it is relative to the ".got" section. */
9637f6ef 17269 if (h == htab->root.hdynamic
fac7bd64 17270 || (!htab->fdpic_p && !htab->vxworks_p && h == htab->root.hgot))
252b5132
RH		 17271 sym->st_shndx = SHN_ABS;
17272
b34976b6 17273 return TRUE;
252b5132
RH		 17274}
17275
0855e32b
NS		 17276static void
17277arm_put_trampoline (struct elf32_arm_link_hash_table *htab, bfd *output_bfd,
17278 void *contents,
17279 const unsigned long *template, unsigned count)
17280{
17281 unsigned ix;
b38cadfb 17282
0855e32b
NS		 17283 for (ix = 0; ix != count; ix++)
17284 {
17285 unsigned long insn = template[ix];
17286
17287 /* Emit mov pc,rx if bx is not permitted. */
17288 if (htab->fix_v4bx == 1 && (insn & 0x0ffffff0) == 0x012fff10)
17289 insn = (insn & 0xf000000f) | 0x01a0f000;
17290 put_arm_insn (htab, output_bfd, insn, (char *)contents + ix*4);
17291 }
17292}
17293
99059e56
RM		 17294/* Install the special first PLT entry for elf32-arm-nacl. Unlike
17295 other variants, NaCl needs this entry in a static executable's
17296 .iplt too. When we're handling that case, GOT_DISPLACEMENT is
17297 zero. For .iplt really only the last bundle is useful, and .iplt
17298 could have a shorter first entry, with each individual PLT entry's
17299 relative branch calculated differently so it targets the last
17300 bundle instead of the instruction before it (labelled .Lplt_tail
17301 above). But it's simpler to keep the size and layout of PLT0
17302 consistent with the dynamic case, at the cost of some dead code at
17303 the start of .iplt and the one dead store to the stack at the start
17304 of .Lplt_tail. */
17305static void
17306arm_nacl_put_plt0 (struct elf32_arm_link_hash_table *htab, bfd *output_bfd,
17307 asection *plt, bfd_vma got_displacement)
17308{
17309 unsigned int i;
17310
17311 put_arm_insn (htab, output_bfd,
17312 elf32_arm_nacl_plt0_entry[0]
17313 | arm_movw_immediate (got_displacement),
17314 plt->contents + 0);
17315 put_arm_insn (htab, output_bfd,
17316 elf32_arm_nacl_plt0_entry[1]
17317 | arm_movt_immediate (got_displacement),
17318 plt->contents + 4);
17319
17320 for (i = 2; i < ARRAY_SIZE (elf32_arm_nacl_plt0_entry); ++i)
17321 put_arm_insn (htab, output_bfd,
17322 elf32_arm_nacl_plt0_entry[i],
17323 plt->contents + (i * 4));
17324}
17325
252b5132
RH		 17326/* Finish up the dynamic sections. */
17327
b34976b6 17328static bfd_boolean
57e8b36a 17329elf32_arm_finish_dynamic_sections (bfd * output_bfd, struct bfd_link_info * info)
252b5132
RH		 17330{
17331 bfd * dynobj;
17332 asection * sgot;
17333 asection * sdyn;
4dfe6ac6
NC		 17334 struct elf32_arm_link_hash_table *htab;
17335
17336 htab = elf32_arm_hash_table (info);
17337 if (htab == NULL)
17338 return FALSE;
252b5132
RH		 17339
17340 dynobj = elf_hash_table (info)->dynobj;
17341
362d30a1 17342 sgot = htab->root.sgotplt;
894891db
NC		 17343 /* A broken linker script might have discarded the dynamic sections.
17344 Catch this here so that we do not seg-fault later on. */
17345 if (sgot != NULL && bfd_is_abs_section (sgot->output_section))
17346 return FALSE;
3d4d4302 17347 sdyn = bfd_get_linker_section (dynobj, ".dynamic");
252b5132
RH		 17348
17349 if (elf_hash_table (info)->dynamic_sections_created)
17350 {
17351 asection *splt;
17352 Elf32_External_Dyn *dyncon, *dynconend;
17353
362d30a1 17354 splt = htab->root.splt;
24a1ba0f 17355 BFD_ASSERT (splt != NULL && sdyn != NULL);
cbc704f3 17356 BFD_ASSERT (htab->symbian_p || sgot != NULL);
252b5132
RH		 17357
17358 dyncon = (Elf32_External_Dyn *) sdyn->contents;
eea6121a 17359 dynconend = (Elf32_External_Dyn *) (sdyn->contents + sdyn->size);
9b485d32 17360
252b5132
RH		 17361 for (; dyncon < dynconend; dyncon++)
17362 {
17363 Elf_Internal_Dyn dyn;
17364 const char * name;
17365 asection * s;
17366
17367 bfd_elf32_swap_dyn_in (dynobj, dyncon, &dyn);
17368
17369 switch (dyn.d_tag)
17370 {
229fcec5
MM		 17371 unsigned int type;
17372
252b5132 17373 default:
7a2b07ff
NS		 17374 if (htab->vxworks_p
17375 && elf_vxworks_finish_dynamic_entry (output_bfd, &dyn))
17376 bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
252b5132
RH		 17377 break;
17378
229fcec5
MM		 17379 case DT_HASH:
17380 name = ".hash";
17381 goto get_vma_if_bpabi;
17382 case DT_STRTAB:
17383 name = ".dynstr";
17384 goto get_vma_if_bpabi;
17385 case DT_SYMTAB:
17386 name = ".dynsym";
17387 goto get_vma_if_bpabi;
c0042f5d
MM		 17388 case DT_VERSYM:
17389 name = ".gnu.version";
17390 goto get_vma_if_bpabi;
17391 case DT_VERDEF:
17392 name = ".gnu.version_d";
17393 goto get_vma_if_bpabi;
17394 case DT_VERNEED:
17395 name = ".gnu.version_r";
17396 goto get_vma_if_bpabi;
17397
252b5132 17398 case DT_PLTGOT:
4ade44b7 17399 name = htab->symbian_p ? ".got" : ".got.plt";
252b5132
RH		 17400 goto get_vma;
17401 case DT_JMPREL:
00a97672 17402 name = RELOC_SECTION (htab, ".plt");
252b5132 17403 get_vma:
4ade44b7 17404 s = bfd_get_linker_section (dynobj, name);
05456594
NC		 17405 if (s == NULL)
17406 {
4eca0228 17407 _bfd_error_handler
4ade44b7 17408 (_("could not find section %s"), name);
05456594
NC		 17409 bfd_set_error (bfd_error_invalid_operation);
17410 return FALSE;
17411 }
229fcec5 17412 if (!htab->symbian_p)
4ade44b7 17413 dyn.d_un.d_ptr = s->output_section->vma + s->output_offset;
229fcec5
MM		 17414 else
17415 /* In the BPABI, tags in the PT_DYNAMIC section point
17416 at the file offset, not the memory address, for the
17417 convenience of the post linker. */
4ade44b7 17418 dyn.d_un.d_ptr = s->output_section->filepos + s->output_offset;
252b5132
RH		 17419 bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
17420 break;
17421
229fcec5
MM		 17422 get_vma_if_bpabi:
17423 if (htab->symbian_p)
17424 goto get_vma;
17425 break;
17426
252b5132 17427 case DT_PLTRELSZ:
362d30a1 17428 s = htab->root.srelplt;
252b5132 17429 BFD_ASSERT (s != NULL);
eea6121a 17430 dyn.d_un.d_val = s->size;
252b5132
RH		 17431 bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
17432 break;
906e58ca 17433
252b5132 17434 case DT_RELSZ:
00a97672 17435 case DT_RELASZ:
229fcec5
MM		 17436 case DT_REL:
17437 case DT_RELA:
229fcec5
MM		 17438 /* In the BPABI, the DT_REL tag must point at the file
17439 offset, not the VMA, of the first relocation
17440 section. So, we use code similar to that in
17441 elflink.c, but do not check for SHF_ALLOC on the
64f52338
AM		 17442 relocation section, since relocation sections are
17443 never allocated under the BPABI. PLT relocs are also
17444 included. */
229fcec5
MM		 17445 if (htab->symbian_p)
17446 {
17447 unsigned int i;
17448 type = ((dyn.d_tag == DT_REL || dyn.d_tag == DT_RELSZ)
17449 ? SHT_REL : SHT_RELA);
17450 dyn.d_un.d_val = 0;
17451 for (i = 1; i < elf_numsections (output_bfd); i++)
17452 {
906e58ca 17453 Elf_Internal_Shdr *hdr
229fcec5
MM		 17454 = elf_elfsections (output_bfd)[i];
17455 if (hdr->sh_type == type)
17456 {
906e58ca 17457 if (dyn.d_tag == DT_RELSZ
229fcec5
MM		 17458 || dyn.d_tag == DT_RELASZ)
17459 dyn.d_un.d_val += hdr->sh_size;
de52dba4
AM		 17460 else if ((ufile_ptr) hdr->sh_offset
17461 <= dyn.d_un.d_val - 1)
229fcec5
MM		 17462 dyn.d_un.d_val = hdr->sh_offset;
17463 }
17464 }
17465 bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
17466 }
252b5132 17467 break;
88f7bcd5 17468
0855e32b 17469 case DT_TLSDESC_PLT:
99059e56 17470 s = htab->root.splt;
0855e32b
NS		 17471 dyn.d_un.d_ptr = (s->output_section->vma + s->output_offset
17472 + htab->dt_tlsdesc_plt);
17473 bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
17474 break;
17475
17476 case DT_TLSDESC_GOT:
99059e56 17477 s = htab->root.sgot;
0855e32b 17478 dyn.d_un.d_ptr = (s->output_section->vma + s->output_offset
99059e56 17479 + htab->dt_tlsdesc_got);
0855e32b
NS		 17480 bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
17481 break;
17482
88f7bcd5
NC		 17483 /* Set the bottom bit of DT_INIT/FINI if the
17484 corresponding function is Thumb. */
17485 case DT_INIT:
17486 name = info->init_function;
17487 goto get_sym;
17488 case DT_FINI:
17489 name = info->fini_function;
17490 get_sym:
17491 /* If it wasn't set by elf_bfd_final_link
4cc11e76 17492 then there is nothing to adjust. */
88f7bcd5
NC		 17493 if (dyn.d_un.d_val != 0)
17494 {
17495 struct elf_link_hash_entry * eh;
17496
17497 eh = elf_link_hash_lookup (elf_hash_table (info), name,
b34976b6 17498 FALSE, FALSE, TRUE);
39d911fc
TP		 17499 if (eh != NULL
17500 && ARM_GET_SYM_BRANCH_TYPE (eh->target_internal)
17501 == ST_BRANCH_TO_THUMB)
88f7bcd5
NC		 17502 {
17503 dyn.d_un.d_val |= 1;
b34976b6 17504 bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
88f7bcd5
NC		 17505 }
17506 }
17507 break;
252b5132
RH		 17508 }
17509 }
17510
24a1ba0f 17511 /* Fill in the first entry in the procedure linkage table. */
4dfe6ac6 17512 if (splt->size > 0 && htab->plt_header_size)
f7a74f8c 17513 {
00a97672
RS		 17514 const bfd_vma *plt0_entry;
17515 bfd_vma got_address, plt_address, got_displacement;
17516
17517 /* Calculate the addresses of the GOT and PLT. */
17518 got_address = sgot->output_section->vma + sgot->output_offset;
17519 plt_address = splt->output_section->vma + splt->output_offset;
17520
17521 if (htab->vxworks_p)
17522 {
17523 /* The VxWorks GOT is relocated by the dynamic linker.
17524 Therefore, we must emit relocations rather than simply
17525 computing the values now. */
17526 Elf_Internal_Rela rel;
17527
17528 plt0_entry = elf32_arm_vxworks_exec_plt0_entry;
52ab56c2
PB		 17529 put_arm_insn (htab, output_bfd, plt0_entry[0],
17530 splt->contents + 0);
17531 put_arm_insn (htab, output_bfd, plt0_entry[1],
17532 splt->contents + 4);
17533 put_arm_insn (htab, output_bfd, plt0_entry[2],
17534 splt->contents + 8);
00a97672
RS		 17535 bfd_put_32 (output_bfd, got_address, splt->contents + 12);
17536
8029a119 17537 /* Generate a relocation for _GLOBAL_OFFSET_TABLE_. */
00a97672
RS		 17538 rel.r_offset = plt_address + 12;
17539 rel.r_info = ELF32_R_INFO (htab->root.hgot->indx, R_ARM_ABS32);
17540 rel.r_addend = 0;
17541 SWAP_RELOC_OUT (htab) (output_bfd, &rel,
17542 htab->srelplt2->contents);
17543 }
b38cadfb 17544 else if (htab->nacl_p)
99059e56
RM		 17545 arm_nacl_put_plt0 (htab, output_bfd, splt,
17546 got_address + 8 - (plt_address + 16));
eed94f8f
NC		 17547 else if (using_thumb_only (htab))
17548 {
17549 got_displacement = got_address - (plt_address + 12);
17550
17551 plt0_entry = elf32_thumb2_plt0_entry;
17552 put_arm_insn (htab, output_bfd, plt0_entry[0],
17553 splt->contents + 0);
17554 put_arm_insn (htab, output_bfd, plt0_entry[1],
17555 splt->contents + 4);
17556 put_arm_insn (htab, output_bfd, plt0_entry[2],
17557 splt->contents + 8);
17558
17559 bfd_put_32 (output_bfd, got_displacement, splt->contents + 12);
17560 }
00a97672
RS		 17561 else
17562 {
17563 got_displacement = got_address - (plt_address + 16);
17564
17565 plt0_entry = elf32_arm_plt0_entry;
52ab56c2
PB		 17566 put_arm_insn (htab, output_bfd, plt0_entry[0],
17567 splt->contents + 0);
17568 put_arm_insn (htab, output_bfd, plt0_entry[1],
17569 splt->contents + 4);
17570 put_arm_insn (htab, output_bfd, plt0_entry[2],
17571 splt->contents + 8);
17572 put_arm_insn (htab, output_bfd, plt0_entry[3],
17573 splt->contents + 12);
5e681ec4 17574
5e681ec4 17575#ifdef FOUR_WORD_PLT
00a97672
RS		 17576 /* The displacement value goes in the otherwise-unused
17577 last word of the second entry. */
17578 bfd_put_32 (output_bfd, got_displacement, splt->contents + 28);
5e681ec4 17579#else
00a97672 17580 bfd_put_32 (output_bfd, got_displacement, splt->contents + 16);
5e681ec4 17581#endif
00a97672 17582 }
f7a74f8c 17583 }
252b5132
RH		 17584
17585 /* UnixWare sets the entsize of .plt to 4, although that doesn't
17586 really seem like the right value. */
74541ad4
AM		 17587 if (splt->output_section->owner == output_bfd)
17588 elf_section_data (splt->output_section)->this_hdr.sh_entsize = 4;
00a97672 17589
0855e32b
NS		 17590 if (htab->dt_tlsdesc_plt)
17591 {
17592 bfd_vma got_address
17593 = sgot->output_section->vma + sgot->output_offset;
17594 bfd_vma gotplt_address = (htab->root.sgot->output_section->vma
17595 + htab->root.sgot->output_offset);
17596 bfd_vma plt_address
17597 = splt->output_section->vma + splt->output_offset;
17598
b38cadfb 17599 arm_put_trampoline (htab, output_bfd,
0855e32b
NS		 17600 splt->contents + htab->dt_tlsdesc_plt,
17601 dl_tlsdesc_lazy_trampoline, 6);
17602
17603 bfd_put_32 (output_bfd,
17604 gotplt_address + htab->dt_tlsdesc_got
17605 - (plt_address + htab->dt_tlsdesc_plt)
17606 - dl_tlsdesc_lazy_trampoline[6],
17607 splt->contents + htab->dt_tlsdesc_plt + 24);
17608 bfd_put_32 (output_bfd,
17609 got_address - (plt_address + htab->dt_tlsdesc_plt)
17610 - dl_tlsdesc_lazy_trampoline[7],
17611 splt->contents + htab->dt_tlsdesc_plt + 24 + 4);
17612 }
17613
17614 if (htab->tls_trampoline)
17615 {
b38cadfb 17616 arm_put_trampoline (htab, output_bfd,
0855e32b
NS		 17617 splt->contents + htab->tls_trampoline,
17618 tls_trampoline, 3);
17619#ifdef FOUR_WORD_PLT
17620 bfd_put_32 (output_bfd, 0x00000000,
17621 splt->contents + htab->tls_trampoline + 12);
b38cadfb 17622#endif
0855e32b
NS		 17623 }
17624
0e1862bb
L		 17625 if (htab->vxworks_p
17626 && !bfd_link_pic (info)
17627 && htab->root.splt->size > 0)
00a97672
RS		 17628 {
17629 /* Correct the .rel(a).plt.unloaded relocations. They will have
17630 incorrect symbol indexes. */
17631 int num_plts;
eed62c48 17632 unsigned char *p;
00a97672 17633
362d30a1 17634 num_plts = ((htab->root.splt->size - htab->plt_header_size)
00a97672
RS		 17635 / htab->plt_entry_size);
17636 p = htab->srelplt2->contents + RELOC_SIZE (htab);
17637
17638 for (; num_plts; num_plts--)
17639 {
17640 Elf_Internal_Rela rel;
17641
17642 SWAP_RELOC_IN (htab) (output_bfd, p, &rel);
17643 rel.r_info = ELF32_R_INFO (htab->root.hgot->indx, R_ARM_ABS32);
17644 SWAP_RELOC_OUT (htab) (output_bfd, &rel, p);
17645 p += RELOC_SIZE (htab);
17646
17647 SWAP_RELOC_IN (htab) (output_bfd, p, &rel);
17648 rel.r_info = ELF32_R_INFO (htab->root.hplt->indx, R_ARM_ABS32);
17649 SWAP_RELOC_OUT (htab) (output_bfd, &rel, p);
17650 p += RELOC_SIZE (htab);
17651 }
17652 }
252b5132
RH		 17653 }
17654
99059e56
RM		 17655 if (htab->nacl_p && htab->root.iplt != NULL && htab->root.iplt->size > 0)
17656 /* NaCl uses a special first entry in .iplt too. */
17657 arm_nacl_put_plt0 (htab, output_bfd, htab->root.iplt, 0);
17658
252b5132 17659 /* Fill in the first three entries in the global offset table. */
229fcec5 17660 if (sgot)
252b5132 17661 {
229fcec5
MM		 17662 if (sgot->size > 0)
17663 {
17664 if (sdyn == NULL)
17665 bfd_put_32 (output_bfd, (bfd_vma) 0, sgot->contents);
17666 else
17667 bfd_put_32 (output_bfd,
17668 sdyn->output_section->vma + sdyn->output_offset,
17669 sgot->contents);
17670 bfd_put_32 (output_bfd, (bfd_vma) 0, sgot->contents + 4);
17671 bfd_put_32 (output_bfd, (bfd_vma) 0, sgot->contents + 8);
17672 }
252b5132 17673
229fcec5
MM		 17674 elf_section_data (sgot->output_section)->this_hdr.sh_entsize = 4;
17675 }
252b5132 17676
e8b09b87
CL		 17677 /* At the very end of the .rofixup section is a pointer to the GOT. */
17678 if (htab->fdpic_p && htab->srofixup != NULL)
17679 {
17680 struct elf_link_hash_entry *hgot = htab->root.hgot;
17681
17682 bfd_vma got_value = hgot->root.u.def.value
17683 + hgot->root.u.def.section->output_section->vma
17684 + hgot->root.u.def.section->output_offset;
17685
17686 arm_elf_add_rofixup(output_bfd, htab->srofixup, got_value);
17687
17688 /* Make sure we allocated and generated the same number of fixups. */
17689 BFD_ASSERT (htab->srofixup->reloc_count * 4 == htab->srofixup->size);
17690 }
17691
b34976b6 17692 return TRUE;
252b5132
RH		 17693}
17694
ed7e9d0b
AM		 17695static bfd_boolean
17696elf32_arm_init_file_header (bfd *abfd, struct bfd_link_info *link_info)
ba96a88f 17697{
9b485d32 17698 Elf_Internal_Ehdr * i_ehdrp; /* ELF file header, internal form. */
e489d0ae 17699 struct elf32_arm_link_hash_table *globals;
ac4c9b04 17700 struct elf_segment_map *m;
ba96a88f 17701
ed7e9d0b
AM		 17702 if (!_bfd_elf_init_file_header (abfd, link_info))
17703 return FALSE;
17704
ba96a88f
NC		 17705 i_ehdrp = elf_elfheader (abfd);
17706
94a3258f
PB		 17707 if (EF_ARM_EABI_VERSION (i_ehdrp->e_flags) == EF_ARM_EABI_UNKNOWN)
17708 i_ehdrp->e_ident[EI_OSABI] = ELFOSABI_ARM;
ba96a88f 17709 i_ehdrp->e_ident[EI_ABIVERSION] = ARM_ELF_ABI_VERSION;
e489d0ae 17710
93204d3a
PB		 17711 if (link_info)
17712 {
17713 globals = elf32_arm_hash_table (link_info);
4dfe6ac6 17714 if (globals != NULL && globals->byteswap_code)
93204d3a 17715 i_ehdrp->e_flags |= EF_ARM_BE8;
18a20338
CL		 17716
17717 if (globals->fdpic_p)
17718 i_ehdrp->e_ident[EI_OSABI] |= ELFOSABI_ARM_FDPIC;
93204d3a 17719 }
3bfcb652
NC		 17720
17721 if (EF_ARM_EABI_VERSION (i_ehdrp->e_flags) == EF_ARM_EABI_VER5
17722 && ((i_ehdrp->e_type == ET_DYN) || (i_ehdrp->e_type == ET_EXEC)))
17723 {
17724 int abi = bfd_elf_get_obj_attr_int (abfd, OBJ_ATTR_PROC, Tag_ABI_VFP_args);
5c294fee 17725 if (abi == AEABI_VFP_args_vfp)
3bfcb652
NC		 17726 i_ehdrp->e_flags |= EF_ARM_ABI_FLOAT_HARD;
17727 else
17728 i_ehdrp->e_flags |= EF_ARM_ABI_FLOAT_SOFT;
17729 }
ac4c9b04
MG		 17730
17731 /* Scan segment to set p_flags attribute if it contains only sections with
f0728ee3 17732 SHF_ARM_PURECODE flag. */
ac4c9b04
MG		 17733 for (m = elf_seg_map (abfd); m != NULL; m = m->next)
17734 {
17735 unsigned int j;
17736
17737 if (m->count == 0)
17738 continue;
17739 for (j = 0; j < m->count; j++)
17740 {
f0728ee3 17741 if (!(elf_section_flags (m->sections[j]) & SHF_ARM_PURECODE))
ac4c9b04
MG		 17742 break;
17743 }
17744 if (j == m->count)
17745 {
17746 m->p_flags = PF_X;
17747 m->p_flags_valid = 1;
17748 }
17749 }
ed7e9d0b 17750 return TRUE;
ba96a88f
NC		 17751}
17752
99e4ae17 17753static enum elf_reloc_type_class
7e612e98
AM		 17754elf32_arm_reloc_type_class (const struct bfd_link_info *info ATTRIBUTE_UNUSED,
17755 const asection *rel_sec ATTRIBUTE_UNUSED,
17756 const Elf_Internal_Rela *rela)
99e4ae17 17757{
f51e552e 17758 switch ((int) ELF32_R_TYPE (rela->r_info))
99e4ae17
AJ		 17759 {
17760 case R_ARM_RELATIVE:
17761 return reloc_class_relative;
17762 case R_ARM_JUMP_SLOT:
17763 return reloc_class_plt;
17764 case R_ARM_COPY:
17765 return reloc_class_copy;
109575d7
JW		 17766 case R_ARM_IRELATIVE:
17767 return reloc_class_ifunc;
99e4ae17
AJ		 17768 default:
17769 return reloc_class_normal;
17770 }
17771}
17772
e489d0ae 17773static void
cc364be6 17774arm_final_write_processing (bfd *abfd)
e16bb312 17775{
5a6c6817 17776 bfd_arm_update_notes (abfd, ARM_NOTE_SECTION);
e16bb312
NC		 17777}
17778
cc364be6
AM		 17779static bfd_boolean
17780elf32_arm_final_write_processing (bfd *abfd)
06f44071 17781{
cc364be6
AM		 17782 arm_final_write_processing (abfd);
17783 return _bfd_elf_final_write_processing (abfd);
06f44071
AM		 17784}
17785
40a18ebd
NC		 17786/* Return TRUE if this is an unwinding table entry. */
17787
17788static bfd_boolean
17789is_arm_elf_unwind_section_name (bfd * abfd ATTRIBUTE_UNUSED, const char * name)
17790{
0112cd26
NC		 17791 return (CONST_STRNEQ (name, ELF_STRING_ARM_unwind)
17792 || CONST_STRNEQ (name, ELF_STRING_ARM_unwind_once));
40a18ebd
NC		 17793}
17794
17795
17796/* Set the type and flags for an ARM section. We do this by
17797 the section name, which is a hack, but ought to work. */
17798
17799static bfd_boolean
17800elf32_arm_fake_sections (bfd * abfd, Elf_Internal_Shdr * hdr, asection * sec)
17801{
17802 const char * name;
17803
fd361982 17804 name = bfd_section_name (sec);
40a18ebd
NC		 17805
17806 if (is_arm_elf_unwind_section_name (abfd, name))
17807 {
17808 hdr->sh_type = SHT_ARM_EXIDX;
17809 hdr->sh_flags |= SHF_LINK_ORDER;
17810 }
ac4c9b04 17811
f0728ee3
AV		 17812 if (sec->flags & SEC_ELF_PURECODE)
17813 hdr->sh_flags |= SHF_ARM_PURECODE;
ac4c9b04 17814
40a18ebd
NC		 17815 return TRUE;
17816}
17817
6dc132d9
L		 17818/* Handle an ARM specific section when reading an object file. This is
17819 called when bfd_section_from_shdr finds a section with an unknown
17820 type. */
40a18ebd
NC		 17821
17822static bfd_boolean
17823elf32_arm_section_from_shdr (bfd *abfd,
17824 Elf_Internal_Shdr * hdr,
6dc132d9
L		 17825 const char *name,
17826 int shindex)
40a18ebd
NC		 17827{
17828 /* There ought to be a place to keep ELF backend specific flags, but
17829 at the moment there isn't one. We just keep track of the
17830 sections by their name, instead. Fortunately, the ABI gives
17831 names for all the ARM specific sections, so we will probably get
17832 away with this. */
17833 switch (hdr->sh_type)
17834 {
17835 case SHT_ARM_EXIDX:
0951f019
RE		 17836 case SHT_ARM_PREEMPTMAP:
17837 case SHT_ARM_ATTRIBUTES:
40a18ebd
NC		 17838 break;
17839
17840 default:
17841 return FALSE;
17842 }
17843
6dc132d9 17844 if (! _bfd_elf_make_section_from_shdr (abfd, hdr, name, shindex))
40a18ebd
NC		 17845 return FALSE;
17846
17847 return TRUE;
17848}
e489d0ae 17849
44444f50
NC		 17850static _arm_elf_section_data *
17851get_arm_elf_section_data (asection * sec)
17852{
47b2e99c
JZ		 17853 if (sec && sec->owner && is_arm_elf (sec->owner))
17854 return elf32_arm_section_data (sec);
44444f50
NC		 17855 else
17856 return NULL;
8e3de13a
NC		 17857}
17858
4e617b1e
PB		 17859typedef struct
17860{
57402f1e 17861 void *flaginfo;
4e617b1e 17862 struct bfd_link_info *info;
91a5743d
PB		 17863 asection *sec;
17864 int sec_shndx;
6e0b88f1
AM		 17865 int (*func) (void *, const char *, Elf_Internal_Sym *,
17866 asection *, struct elf_link_hash_entry *);
4e617b1e
PB		 17867} output_arch_syminfo;
17868
17869enum map_symbol_type
17870{
17871 ARM_MAP_ARM,
17872 ARM_MAP_THUMB,
17873 ARM_MAP_DATA
17874};
17875
17876
7413f23f 17877/* Output a single mapping symbol. */
4e617b1e
PB		 17878
17879static bfd_boolean
7413f23f
DJ		 17880elf32_arm_output_map_sym (output_arch_syminfo *osi,
17881 enum map_symbol_type type,
17882 bfd_vma offset)
4e617b1e
PB		 17883{
17884 static const char *names[3] = {"$a", "$t", "$d"};
4e617b1e
PB		 17885 Elf_Internal_Sym sym;
17886
91a5743d
PB		 17887 sym.st_value = osi->sec->output_section->vma
17888 + osi->sec->output_offset
17889 + offset;
4e617b1e
PB		 17890 sym.st_size = 0;
17891 sym.st_other = 0;
17892 sym.st_info = ELF_ST_INFO (STB_LOCAL, STT_NOTYPE);
91a5743d 17893 sym.st_shndx = osi->sec_shndx;
35fc36a8 17894 sym.st_target_internal = 0;
fe33d2fa 17895 elf32_arm_section_map_add (osi->sec, names[type][1], offset);
57402f1e 17896 return osi->func (osi->flaginfo, names[type], &sym, osi->sec, NULL) == 1;
4e617b1e
PB		 17897}
17898
34e77a92
RS		 17899/* Output mapping symbols for the PLT entry described by ROOT_PLT and ARM_PLT.
17900 IS_IPLT_ENTRY_P says whether the PLT is in .iplt rather than .plt. */
4e617b1e
PB		 17901
17902static bfd_boolean
34e77a92
RS		 17903elf32_arm_output_plt_map_1 (output_arch_syminfo *osi,
17904 bfd_boolean is_iplt_entry_p,
17905 union gotplt_union *root_plt,
17906 struct arm_plt_info *arm_plt)
4e617b1e 17907{
4e617b1e 17908 struct elf32_arm_link_hash_table *htab;
34e77a92 17909 bfd_vma addr, plt_header_size;
4e617b1e 17910
34e77a92 17911 if (root_plt->offset == (bfd_vma) -1)
4e617b1e
PB		 17912 return TRUE;
17913
4dfe6ac6
NC		 17914 htab = elf32_arm_hash_table (osi->info);
17915 if (htab == NULL)
17916 return FALSE;
17917
34e77a92
RS		 17918 if (is_iplt_entry_p)
17919 {
17920 osi->sec = htab->root.iplt;
17921 plt_header_size = 0;
17922 }
17923 else
17924 {
17925 osi->sec = htab->root.splt;
17926 plt_header_size = htab->plt_header_size;
17927 }
17928 osi->sec_shndx = (_bfd_elf_section_from_bfd_section
17929 (osi->info->output_bfd, osi->sec->output_section));
17930
17931 addr = root_plt->offset & -2;
4e617b1e
PB		 17932 if (htab->symbian_p)
17933 {
7413f23f 17934 if (!elf32_arm_output_map_sym (osi, ARM_MAP_ARM, addr))
4e617b1e 17935 return FALSE;
7413f23f 17936 if (!elf32_arm_output_map_sym (osi, ARM_MAP_DATA, addr + 4))
4e617b1e
PB		 17937 return FALSE;
17938 }
17939 else if (htab->vxworks_p)
17940 {
7413f23f 17941 if (!elf32_arm_output_map_sym (osi, ARM_MAP_ARM, addr))
4e617b1e 17942 return FALSE;
7413f23f 17943 if (!elf32_arm_output_map_sym (osi, ARM_MAP_DATA, addr + 8))
4e617b1e 17944 return FALSE;
7413f23f 17945 if (!elf32_arm_output_map_sym (osi, ARM_MAP_ARM, addr + 12))
4e617b1e 17946 return FALSE;
7413f23f 17947 if (!elf32_arm_output_map_sym (osi, ARM_MAP_DATA, addr + 20))
4e617b1e
PB		 17948 return FALSE;
17949 }
b38cadfb
NC		 17950 else if (htab->nacl_p)
17951 {
17952 if (!elf32_arm_output_map_sym (osi, ARM_MAP_ARM, addr))
17953 return FALSE;
17954 }
7801f98f
CL		 17955 else if (htab->fdpic_p)
17956 {
59029f57
CL		 17957 enum map_symbol_type type = using_thumb_only(htab)
17958 ? ARM_MAP_THUMB
17959 : ARM_MAP_ARM;
17960
7801f98f 17961 if (elf32_arm_plt_needs_thumb_stub_p (osi->info, arm_plt))
4b24dd1a
AM		 17962 if (!elf32_arm_output_map_sym (osi, ARM_MAP_THUMB, addr - 4))
17963 return FALSE;
59029f57 17964 if (!elf32_arm_output_map_sym (osi, type, addr))
4b24dd1a 17965 return FALSE;
7801f98f 17966 if (!elf32_arm_output_map_sym (osi, ARM_MAP_DATA, addr + 16))
4b24dd1a 17967 return FALSE;
7801f98f 17968 if (htab->plt_entry_size == 4 * ARRAY_SIZE(elf32_arm_fdpic_plt_entry))
4b24dd1a
AM		 17969 if (!elf32_arm_output_map_sym (osi, type, addr + 24))
17970 return FALSE;
7801f98f 17971 }
eed94f8f
NC		 17972 else if (using_thumb_only (htab))
17973 {
17974 if (!elf32_arm_output_map_sym (osi, ARM_MAP_THUMB, addr))
17975 return FALSE;
6a631e86 17976 }
4e617b1e
PB		 17977 else
17978 {
34e77a92 17979 bfd_boolean thumb_stub_p;
bd97cb95 17980
34e77a92
RS		 17981 thumb_stub_p = elf32_arm_plt_needs_thumb_stub_p (osi->info, arm_plt);
17982 if (thumb_stub_p)
4e617b1e 17983 {
7413f23f 17984 if (!elf32_arm_output_map_sym (osi, ARM_MAP_THUMB, addr - 4))
4e617b1e
PB		 17985 return FALSE;
17986 }
17987#ifdef FOUR_WORD_PLT
7413f23f 17988 if (!elf32_arm_output_map_sym (osi, ARM_MAP_ARM, addr))
4e617b1e 17989 return FALSE;
7413f23f 17990 if (!elf32_arm_output_map_sym (osi, ARM_MAP_DATA, addr + 12))
4e617b1e
PB		 17991 return FALSE;
17992#else
906e58ca 17993 /* A three-word PLT with no Thumb thunk contains only Arm code,
4e617b1e
PB		 17994 so only need to output a mapping symbol for the first PLT entry and
17995 entries with thumb thunks. */
34e77a92 17996 if (thumb_stub_p || addr == plt_header_size)
4e617b1e 17997 {
7413f23f 17998 if (!elf32_arm_output_map_sym (osi, ARM_MAP_ARM, addr))
4e617b1e
PB		 17999 return FALSE;
18000 }
18001#endif
18002 }
18003
18004 return TRUE;
18005}
18006
34e77a92
RS		 18007/* Output mapping symbols for PLT entries associated with H. */
18008
18009static bfd_boolean
18010elf32_arm_output_plt_map (struct elf_link_hash_entry *h, void *inf)
18011{
18012 output_arch_syminfo *osi = (output_arch_syminfo *) inf;
18013 struct elf32_arm_link_hash_entry *eh;
18014
18015 if (h->root.type == bfd_link_hash_indirect)
18016 return TRUE;
18017
18018 if (h->root.type == bfd_link_hash_warning)
18019 /* When warning symbols are created, they **replace** the "real"
18020 entry in the hash table, thus we never get to see the real
18021 symbol in a hash traversal. So look at it now. */
18022 h = (struct elf_link_hash_entry *) h->root.u.i.link;
18023
18024 eh = (struct elf32_arm_link_hash_entry *) h;
18025 return elf32_arm_output_plt_map_1 (osi, SYMBOL_CALLS_LOCAL (osi->info, h),
18026 &h->plt, &eh->plt);
18027}
18028
4f4faa4d
TP		 18029/* Bind a veneered symbol to its veneer identified by its hash entry
18030 STUB_ENTRY. The veneered location thus loose its symbol. */
18031
18032static void
18033arm_stub_claim_sym (struct elf32_arm_stub_hash_entry *stub_entry)
18034{
18035 struct elf32_arm_link_hash_entry *hash = stub_entry->h;
18036
18037 BFD_ASSERT (hash);
18038 hash->root.root.u.def.section = stub_entry->stub_sec;
18039 hash->root.root.u.def.value = stub_entry->stub_offset;
18040 hash->root.size = stub_entry->stub_size;
18041}
18042
7413f23f
DJ		 18043/* Output a single local symbol for a generated stub. */
18044
18045static bfd_boolean
18046elf32_arm_output_stub_sym (output_arch_syminfo *osi, const char *name,
18047 bfd_vma offset, bfd_vma size)
18048{
7413f23f
DJ		 18049 Elf_Internal_Sym sym;
18050
7413f23f
DJ		 18051 sym.st_value = osi->sec->output_section->vma
18052 + osi->sec->output_offset
18053 + offset;
18054 sym.st_size = size;
18055 sym.st_other = 0;
18056 sym.st_info = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
18057 sym.st_shndx = osi->sec_shndx;
35fc36a8 18058 sym.st_target_internal = 0;
57402f1e 18059 return osi->func (osi->flaginfo, name, &sym, osi->sec, NULL) == 1;
7413f23f 18060}
4e617b1e 18061
da5938a2 18062static bfd_boolean
8029a119
NC		 18063arm_map_one_stub (struct bfd_hash_entry * gen_entry,
18064 void * in_arg)
da5938a2
NC		 18065{
18066 struct elf32_arm_stub_hash_entry *stub_entry;
da5938a2
NC		 18067 asection *stub_sec;
18068 bfd_vma addr;
7413f23f 18069 char *stub_name;
9a008db3 18070 output_arch_syminfo *osi;
d3ce72d0 18071 const insn_sequence *template_sequence;
461a49ca
DJ		 18072 enum stub_insn_type prev_type;
18073 int size;
18074 int i;
18075 enum map_symbol_type sym_type;
da5938a2
NC		 18076
18077 /* Massage our args to the form they really have. */
18078 stub_entry = (struct elf32_arm_stub_hash_entry *) gen_entry;
9a008db3 18079 osi = (output_arch_syminfo *) in_arg;
da5938a2 18080
da5938a2
NC		 18081 stub_sec = stub_entry->stub_sec;
18082
18083 /* Ensure this stub is attached to the current section being
7413f23f 18084 processed. */
da5938a2
NC		 18085 if (stub_sec != osi->sec)
18086 return TRUE;
18087
7413f23f 18088 addr = (bfd_vma) stub_entry->stub_offset;
d3ce72d0 18089 template_sequence = stub_entry->stub_template;
4f4faa4d
TP		 18090
18091 if (arm_stub_sym_claimed (stub_entry->stub_type))
18092 arm_stub_claim_sym (stub_entry);
18093 else
7413f23f 18094 {
4f4faa4d
TP		 18095 stub_name = stub_entry->output_name;
18096 switch (template_sequence[0].type)
18097 {
18098 case ARM_TYPE:
18099 if (!elf32_arm_output_stub_sym (osi, stub_name, addr,
18100 stub_entry->stub_size))
18101 return FALSE;
18102 break;
18103 case THUMB16_TYPE:
18104 case THUMB32_TYPE:
18105 if (!elf32_arm_output_stub_sym (osi, stub_name, addr | 1,
18106 stub_entry->stub_size))
18107 return FALSE;
18108 break;
18109 default:
18110 BFD_FAIL ();
18111 return 0;
18112 }
7413f23f 18113 }
da5938a2 18114
461a49ca
DJ		 18115 prev_type = DATA_TYPE;
18116 size = 0;
18117 for (i = 0; i < stub_entry->stub_template_size; i++)
18118 {
d3ce72d0 18119 switch (template_sequence[i].type)
461a49ca
DJ		 18120 {
18121 case ARM_TYPE:
18122 sym_type = ARM_MAP_ARM;
18123 break;
18124
18125 case THUMB16_TYPE:
48229727 18126 case THUMB32_TYPE:
461a49ca
DJ		 18127 sym_type = ARM_MAP_THUMB;
18128 break;
18129
18130 case DATA_TYPE:
18131 sym_type = ARM_MAP_DATA;
18132 break;
18133
18134 default:
18135 BFD_FAIL ();
4e31c731 18136 return FALSE;
461a49ca
DJ		 18137 }
18138
d3ce72d0 18139 if (template_sequence[i].type != prev_type)
461a49ca 18140 {
d3ce72d0 18141 prev_type = template_sequence[i].type;
461a49ca
DJ		 18142 if (!elf32_arm_output_map_sym (osi, sym_type, addr + size))
18143 return FALSE;
18144 }
18145
d3ce72d0 18146 switch (template_sequence[i].type)
461a49ca
DJ		 18147 {
18148 case ARM_TYPE:
48229727 18149 case THUMB32_TYPE:
461a49ca
DJ		 18150 size += 4;
18151 break;
18152
18153 case THUMB16_TYPE:
18154 size += 2;
18155 break;
18156
18157 case DATA_TYPE:
18158 size += 4;
18159 break;
18160
18161 default:
18162 BFD_FAIL ();
4e31c731 18163 return FALSE;
461a49ca
DJ		 18164 }
18165 }
18166
da5938a2
NC		 18167 return TRUE;
18168}
18169
33811162
DG		 18170/* Output mapping symbols for linker generated sections,
18171 and for those data-only sections that do not have a
18172 $d. */
4e617b1e
PB		 18173
18174static bfd_boolean
18175elf32_arm_output_arch_local_syms (bfd *output_bfd,
906e58ca 18176 struct bfd_link_info *info,
57402f1e 18177 void *flaginfo,
6e0b88f1
AM		 18178 int (*func) (void *, const char *,
18179 Elf_Internal_Sym *,
18180 asection *,
18181 struct elf_link_hash_entry *))
4e617b1e
PB		 18182{
18183 output_arch_syminfo osi;
18184 struct elf32_arm_link_hash_table *htab;
91a5743d
PB		 18185 bfd_vma offset;
18186 bfd_size_type size;
33811162 18187 bfd *input_bfd;
4e617b1e
PB		 18188
18189 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 18190 if (htab == NULL)
18191 return FALSE;
18192
906e58ca 18193 check_use_blx (htab);
91a5743d 18194
57402f1e 18195 osi.flaginfo = flaginfo;
4e617b1e
PB		 18196 osi.info = info;
18197 osi.func = func;
906e58ca 18198
33811162
DG		 18199 /* Add a $d mapping symbol to data-only sections that
18200 don't have any mapping symbol. This may result in (harmless) redundant
18201 mapping symbols. */
18202 for (input_bfd = info->input_bfds;
18203 input_bfd != NULL;
c72f2fb2 18204 input_bfd = input_bfd->link.next)
33811162
DG		 18205 {
18206 if ((input_bfd->flags & (BFD_LINKER_CREATED | HAS_SYMS)) == HAS_SYMS)
18207 for (osi.sec = input_bfd->sections;
18208 osi.sec != NULL;
18209 osi.sec = osi.sec->next)
18210 {
18211 if (osi.sec->output_section != NULL
f7dd8c79
DJ		 18212 && ((osi.sec->output_section->flags & (SEC_ALLOC | SEC_CODE))
18213 != 0)
33811162
DG		 18214 && (osi.sec->flags & (SEC_HAS_CONTENTS | SEC_LINKER_CREATED))
18215 == SEC_HAS_CONTENTS
18216 && get_arm_elf_section_data (osi.sec) != NULL
501abfe0 18217 && get_arm_elf_section_data (osi.sec)->mapcount == 0
7d500b83
CL		 18218 && osi.sec->size > 0
18219 && (osi.sec->flags & SEC_EXCLUDE) == 0)
33811162
DG		 18220 {
18221 osi.sec_shndx = _bfd_elf_section_from_bfd_section
18222 (output_bfd, osi.sec->output_section);
18223 if (osi.sec_shndx != (int)SHN_BAD)
18224 elf32_arm_output_map_sym (&osi, ARM_MAP_DATA, 0);
18225 }
18226 }
18227 }
18228
91a5743d
PB		 18229 /* ARM->Thumb glue. */
18230 if (htab->arm_glue_size > 0)
18231 {
3d4d4302
AM		 18232 osi.sec = bfd_get_linker_section (htab->bfd_of_glue_owner,
18233 ARM2THUMB_GLUE_SECTION_NAME);
91a5743d
PB		 18234
18235 osi.sec_shndx = _bfd_elf_section_from_bfd_section
18236 (output_bfd, osi.sec->output_section);
0e1862bb 18237 if (bfd_link_pic (info) || htab->root.is_relocatable_executable
91a5743d
PB		 18238 || htab->pic_veneer)
18239 size = ARM2THUMB_PIC_GLUE_SIZE;
18240 else if (htab->use_blx)
18241 size = ARM2THUMB_V5_STATIC_GLUE_SIZE;
18242 else
18243 size = ARM2THUMB_STATIC_GLUE_SIZE;
4e617b1e 18244
91a5743d
PB		 18245 for (offset = 0; offset < htab->arm_glue_size; offset += size)
18246 {
7413f23f
DJ		 18247 elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, offset);
18248 elf32_arm_output_map_sym (&osi, ARM_MAP_DATA, offset + size - 4);
91a5743d
PB		 18249 }
18250 }
18251
18252 /* Thumb->ARM glue. */
18253 if (htab->thumb_glue_size > 0)
18254 {
3d4d4302
AM		 18255 osi.sec = bfd_get_linker_section (htab->bfd_of_glue_owner,
18256 THUMB2ARM_GLUE_SECTION_NAME);
91a5743d
PB		 18257
18258 osi.sec_shndx = _bfd_elf_section_from_bfd_section
18259 (output_bfd, osi.sec->output_section);
18260 size = THUMB2ARM_GLUE_SIZE;
18261
18262 for (offset = 0; offset < htab->thumb_glue_size; offset += size)
18263 {
7413f23f
DJ		 18264 elf32_arm_output_map_sym (&osi, ARM_MAP_THUMB, offset);
18265 elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, offset + 4);
91a5743d
PB		 18266 }
18267 }
18268
845b51d6
PB		 18269 /* ARMv4 BX veneers. */
18270 if (htab->bx_glue_size > 0)
18271 {
3d4d4302
AM		 18272 osi.sec = bfd_get_linker_section (htab->bfd_of_glue_owner,
18273 ARM_BX_GLUE_SECTION_NAME);
845b51d6
PB		 18274
18275 osi.sec_shndx = _bfd_elf_section_from_bfd_section
18276 (output_bfd, osi.sec->output_section);
18277
7413f23f 18278 elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, 0);
845b51d6
PB		 18279 }
18280
8029a119
NC		 18281 /* Long calls stubs. */
18282 if (htab->stub_bfd && htab->stub_bfd->sections)
18283 {
da5938a2 18284 asection* stub_sec;
8029a119 18285
da5938a2
NC		 18286 for (stub_sec = htab->stub_bfd->sections;
18287 stub_sec != NULL;
8029a119
NC		 18288 stub_sec = stub_sec->next)
18289 {
18290 /* Ignore non-stub sections. */
18291 if (!strstr (stub_sec->name, STUB_SUFFIX))
18292 continue;
da5938a2 18293
8029a119 18294 osi.sec = stub_sec;
da5938a2 18295
8029a119
NC		 18296 osi.sec_shndx = _bfd_elf_section_from_bfd_section
18297 (output_bfd, osi.sec->output_section);
da5938a2 18298
8029a119
NC		 18299 bfd_hash_traverse (&htab->stub_hash_table, arm_map_one_stub, &osi);
18300 }
18301 }
da5938a2 18302
91a5743d 18303 /* Finally, output mapping symbols for the PLT. */
34e77a92 18304 if (htab->root.splt && htab->root.splt->size > 0)
4e617b1e 18305 {
34e77a92
RS		 18306 osi.sec = htab->root.splt;
18307 osi.sec_shndx = (_bfd_elf_section_from_bfd_section
18308 (output_bfd, osi.sec->output_section));
18309
18310 /* Output mapping symbols for the plt header. SymbianOS does not have a
18311 plt header. */
18312 if (htab->vxworks_p)
18313 {
18314 /* VxWorks shared libraries have no PLT header. */
0e1862bb 18315 if (!bfd_link_pic (info))
34e77a92
RS		 18316 {
18317 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, 0))
18318 return FALSE;
18319 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_DATA, 12))
18320 return FALSE;
18321 }
18322 }
b38cadfb
NC		 18323 else if (htab->nacl_p)
18324 {
18325 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, 0))
18326 return FALSE;
18327 }
59029f57 18328 else if (using_thumb_only (htab) && !htab->fdpic_p)
eed94f8f
NC		 18329 {
18330 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_THUMB, 0))
18331 return FALSE;
18332 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_DATA, 12))
18333 return FALSE;
18334 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_THUMB, 16))
18335 return FALSE;
18336 }
e8b09b87 18337 else if (!htab->symbian_p && !htab->fdpic_p)
4e617b1e 18338 {
7413f23f 18339 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, 0))
4e617b1e 18340 return FALSE;
34e77a92
RS		 18341#ifndef FOUR_WORD_PLT
18342 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_DATA, 16))
4e617b1e 18343 return FALSE;
34e77a92 18344#endif
4e617b1e
PB		 18345 }
18346 }
99059e56
RM		 18347 if (htab->nacl_p && htab->root.iplt && htab->root.iplt->size > 0)
18348 {
18349 /* NaCl uses a special first entry in .iplt too. */
18350 osi.sec = htab->root.iplt;
18351 osi.sec_shndx = (_bfd_elf_section_from_bfd_section
18352 (output_bfd, osi.sec->output_section));
18353 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, 0))
18354 return FALSE;
18355 }
34e77a92
RS		 18356 if ((htab->root.splt && htab->root.splt->size > 0)
18357 || (htab->root.iplt && htab->root.iplt->size > 0))
4e617b1e 18358 {
34e77a92
RS		 18359 elf_link_hash_traverse (&htab->root, elf32_arm_output_plt_map, &osi);
18360 for (input_bfd = info->input_bfds;
18361 input_bfd != NULL;
c72f2fb2 18362 input_bfd = input_bfd->link.next)
34e77a92
RS		 18363 {
18364 struct arm_local_iplt_info **local_iplt;
18365 unsigned int i, num_syms;
4e617b1e 18366
34e77a92
RS		 18367 local_iplt = elf32_arm_local_iplt (input_bfd);
18368 if (local_iplt != NULL)
18369 {
18370 num_syms = elf_symtab_hdr (input_bfd).sh_info;
18371 for (i = 0; i < num_syms; i++)
18372 if (local_iplt[i] != NULL
18373 && !elf32_arm_output_plt_map_1 (&osi, TRUE,
18374 &local_iplt[i]->root,
18375 &local_iplt[i]->arm))
18376 return FALSE;
18377 }
18378 }
18379 }
0855e32b
NS		 18380 if (htab->dt_tlsdesc_plt != 0)
18381 {
18382 /* Mapping symbols for the lazy tls trampoline. */
18383 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, htab->dt_tlsdesc_plt))
18384 return FALSE;
b38cadfb 18385
0855e32b
NS		 18386 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_DATA,
18387 htab->dt_tlsdesc_plt + 24))
18388 return FALSE;
18389 }
18390 if (htab->tls_trampoline != 0)
18391 {
18392 /* Mapping symbols for the tls trampoline. */
18393 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, htab->tls_trampoline))
18394 return FALSE;
18395#ifdef FOUR_WORD_PLT
18396 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_DATA,
18397 htab->tls_trampoline + 12))
18398 return FALSE;
b38cadfb 18399#endif
0855e32b 18400 }
b38cadfb 18401
4e617b1e
PB		 18402 return TRUE;
18403}
18404
54ddd295
TP		 18405/* Filter normal symbols of CMSE entry functions of ABFD to include in
18406 the import library. All SYMCOUNT symbols of ABFD can be examined
18407 from their pointers in SYMS. Pointers of symbols to keep should be
18408 stored continuously at the beginning of that array.
18409
18410 Returns the number of symbols to keep. */
18411
18412static unsigned int
18413elf32_arm_filter_cmse_symbols (bfd *abfd ATTRIBUTE_UNUSED,
18414 struct bfd_link_info *info,
18415 asymbol **syms, long symcount)
18416{
18417 size_t maxnamelen;
18418 char *cmse_name;
18419 long src_count, dst_count = 0;
18420 struct elf32_arm_link_hash_table *htab;
18421
18422 htab = elf32_arm_hash_table (info);
18423 if (!htab->stub_bfd || !htab->stub_bfd->sections)
18424 symcount = 0;
18425
18426 maxnamelen = 128;
18427 cmse_name = (char *) bfd_malloc (maxnamelen);
7a0fb7be
NC		 18428 BFD_ASSERT (cmse_name);
18429
54ddd295
TP		 18430 for (src_count = 0; src_count < symcount; src_count++)
18431 {
18432 struct elf32_arm_link_hash_entry *cmse_hash;
18433 asymbol *sym;
18434 flagword flags;
18435 char *name;
18436 size_t namelen;
18437
18438 sym = syms[src_count];
18439 flags = sym->flags;
18440 name = (char *) bfd_asymbol_name (sym);
18441
18442 if ((flags & BSF_FUNCTION) != BSF_FUNCTION)
18443 continue;
18444 if (!(flags & (BSF_GLOBAL | BSF_WEAK)))
18445 continue;
18446
18447 namelen = strlen (name) + sizeof (CMSE_PREFIX) + 1;
18448 if (namelen > maxnamelen)
18449 {
18450 cmse_name = (char *)
18451 bfd_realloc (cmse_name, namelen);
18452 maxnamelen = namelen;
18453 }
18454 snprintf (cmse_name, maxnamelen, "%s%s", CMSE_PREFIX, name);
18455 cmse_hash = (struct elf32_arm_link_hash_entry *)
18456 elf_link_hash_lookup (&(htab)->root, cmse_name, FALSE, FALSE, TRUE);
18457
18458 if (!cmse_hash
18459 || (cmse_hash->root.root.type != bfd_link_hash_defined
18460 && cmse_hash->root.root.type != bfd_link_hash_defweak)
18461 || cmse_hash->root.type != STT_FUNC)
18462 continue;
18463
54ddd295
TP		 18464 syms[dst_count++] = sym;
18465 }
18466 free (cmse_name);
18467
18468 syms[dst_count] = NULL;
18469
18470 return dst_count;
18471}
18472
18473/* Filter symbols of ABFD to include in the import library. All
18474 SYMCOUNT symbols of ABFD can be examined from their pointers in
18475 SYMS. Pointers of symbols to keep should be stored continuously at
18476 the beginning of that array.
18477
18478 Returns the number of symbols to keep. */
18479
18480static unsigned int
18481elf32_arm_filter_implib_symbols (bfd *abfd ATTRIBUTE_UNUSED,
18482 struct bfd_link_info *info,
18483 asymbol **syms, long symcount)
18484{
18485 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (info);
18486
046734ff
TP		 18487 /* Requirement 8 of "ARM v8-M Security Extensions: Requirements on
18488 Development Tools" (ARM-ECM-0359818) mandates Secure Gateway import
18489 library to be a relocatable object file. */
18490 BFD_ASSERT (!(bfd_get_file_flags (info->out_implib_bfd) & EXEC_P));
54ddd295
TP		 18491 if (globals->cmse_implib)
18492 return elf32_arm_filter_cmse_symbols (abfd, info, syms, symcount);
18493 else
18494 return _bfd_elf_filter_global_symbols (abfd, info, syms, symcount);
18495}
18496
e489d0ae
PB		 18497/* Allocate target specific section data. */
18498
18499static bfd_boolean
18500elf32_arm_new_section_hook (bfd *abfd, asection *sec)
18501{
f592407e
AM		 18502 if (!sec->used_by_bfd)
18503 {
18504 _arm_elf_section_data *sdata;
986f0783 18505 size_t amt = sizeof (*sdata);
e489d0ae 18506
21d799b5 18507 sdata = (_arm_elf_section_data *) bfd_zalloc (abfd, amt);
f592407e
AM		 18508 if (sdata == NULL)
18509 return FALSE;
18510 sec->used_by_bfd = sdata;
18511 }
e489d0ae
PB		 18512
18513 return _bfd_elf_new_section_hook (abfd, sec);
18514}
18515
18516
18517/* Used to order a list of mapping symbols by address. */
18518
18519static int
18520elf32_arm_compare_mapping (const void * a, const void * b)
18521{
7f6a71ff
JM		 18522 const elf32_arm_section_map *amap = (const elf32_arm_section_map *) a;
18523 const elf32_arm_section_map *bmap = (const elf32_arm_section_map *) b;
18524
18525 if (amap->vma > bmap->vma)
18526 return 1;
18527 else if (amap->vma < bmap->vma)
18528 return -1;
18529 else if (amap->type > bmap->type)
18530 /* Ensure results do not depend on the host qsort for objects with
18531 multiple mapping symbols at the same address by sorting on type
18532 after vma. */
18533 return 1;
18534 else if (amap->type < bmap->type)
18535 return -1;
18536 else
18537 return 0;
e489d0ae
PB		 18538}
18539
2468f9c9
PB		 18540/* Add OFFSET to lower 31 bits of ADDR, leaving other bits unmodified. */
18541
18542static unsigned long
18543offset_prel31 (unsigned long addr, bfd_vma offset)
18544{
18545 return (addr & ~0x7ffffffful) | ((addr + offset) & 0x7ffffffful);
18546}
18547
18548/* Copy an .ARM.exidx table entry, adding OFFSET to (applied) PREL31
18549 relocations. */
18550
18551static void
18552copy_exidx_entry (bfd *output_bfd, bfd_byte *to, bfd_byte *from, bfd_vma offset)
18553{
18554 unsigned long first_word = bfd_get_32 (output_bfd, from);
18555 unsigned long second_word = bfd_get_32 (output_bfd, from + 4);
b38cadfb 18556
2468f9c9
PB		 18557 /* High bit of first word is supposed to be zero. */
18558 if ((first_word & 0x80000000ul) == 0)
18559 first_word = offset_prel31 (first_word, offset);
b38cadfb 18560
2468f9c9
PB		 18561 /* If the high bit of the first word is clear, and the bit pattern is not 0x1
18562 (EXIDX_CANTUNWIND), this is an offset to an .ARM.extab entry. */
18563 if ((second_word != 0x1) && ((second_word & 0x80000000ul) == 0))
18564 second_word = offset_prel31 (second_word, offset);
b38cadfb 18565
2468f9c9
PB		 18566 bfd_put_32 (output_bfd, first_word, to);
18567 bfd_put_32 (output_bfd, second_word, to + 4);
18568}
e489d0ae 18569
48229727
JB		 18570/* Data for make_branch_to_a8_stub(). */
18571
b38cadfb
NC		 18572struct a8_branch_to_stub_data
18573{
48229727
JB		 18574 asection *writing_section;
18575 bfd_byte *contents;
18576};
18577
18578
18579/* Helper to insert branches to Cortex-A8 erratum stubs in the right
18580 places for a particular section. */
18581
18582static bfd_boolean
18583make_branch_to_a8_stub (struct bfd_hash_entry *gen_entry,
99059e56 18584 void *in_arg)
48229727
JB		 18585{
18586 struct elf32_arm_stub_hash_entry *stub_entry;
18587 struct a8_branch_to_stub_data *data;
18588 bfd_byte *contents;
18589 unsigned long branch_insn;
18590 bfd_vma veneered_insn_loc, veneer_entry_loc;
18591 bfd_signed_vma branch_offset;
18592 bfd *abfd;
8d9d9490 18593 unsigned int loc;
48229727
JB		 18594
18595 stub_entry = (struct elf32_arm_stub_hash_entry *) gen_entry;
18596 data = (struct a8_branch_to_stub_data *) in_arg;
18597
18598 if (stub_entry->target_section != data->writing_section
4563a860 18599 || stub_entry->stub_type < arm_stub_a8_veneer_lwm)
48229727
JB		 18600 return TRUE;
18601
18602 contents = data->contents;
18603
8d9d9490
TP		 18604 /* We use target_section as Cortex-A8 erratum workaround stubs are only
18605 generated when both source and target are in the same section. */
48229727
JB		 18606 veneered_insn_loc = stub_entry->target_section->output_section->vma
18607 + stub_entry->target_section->output_offset
8d9d9490 18608 + stub_entry->source_value;
48229727
JB		 18609
18610 veneer_entry_loc = stub_entry->stub_sec->output_section->vma
18611 + stub_entry->stub_sec->output_offset
18612 + stub_entry->stub_offset;
18613
18614 if (stub_entry->stub_type == arm_stub_a8_veneer_blx)
18615 veneered_insn_loc &= ~3u;
18616
18617 branch_offset = veneer_entry_loc - veneered_insn_loc - 4;
18618
18619 abfd = stub_entry->target_section->owner;
8d9d9490 18620 loc = stub_entry->source_value;
48229727
JB		 18621
18622 /* We attempt to avoid this condition by setting stubs_always_after_branch
18623 in elf32_arm_size_stubs if we've enabled the Cortex-A8 erratum workaround.
18624 This check is just to be on the safe side... */
18625 if ((veneered_insn_loc & ~0xfff) == (veneer_entry_loc & ~0xfff))
18626 {
871b3ab2 18627 _bfd_error_handler (_("%pB: error: Cortex-A8 erratum stub is "
4eca0228 18628 "allocated in unsafe location"), abfd);
48229727
JB		 18629 return FALSE;
18630 }
18631
18632 switch (stub_entry->stub_type)
18633 {
18634 case arm_stub_a8_veneer_b:
18635 case arm_stub_a8_veneer_b_cond:
18636 branch_insn = 0xf0009000;
18637 goto jump24;
18638
18639 case arm_stub_a8_veneer_blx:
18640 branch_insn = 0xf000e800;
18641 goto jump24;
18642
18643 case arm_stub_a8_veneer_bl:
18644 {
18645 unsigned int i1, j1, i2, j2, s;
18646
18647 branch_insn = 0xf000d000;
18648
18649 jump24:
18650 if (branch_offset < -16777216 || branch_offset > 16777214)
18651 {
18652 /* There's not much we can do apart from complain if this
18653 happens. */
871b3ab2 18654 _bfd_error_handler (_("%pB: error: Cortex-A8 erratum stub out "
4eca0228 18655 "of range (input file too large)"), abfd);
48229727
JB		 18656 return FALSE;
18657 }
18658
18659 /* i1 = not(j1 eor s), so:
18660 not i1 = j1 eor s
18661 j1 = (not i1) eor s. */
18662
18663 branch_insn |= (branch_offset >> 1) & 0x7ff;
18664 branch_insn |= ((branch_offset >> 12) & 0x3ff) << 16;
18665 i2 = (branch_offset >> 22) & 1;
18666 i1 = (branch_offset >> 23) & 1;
18667 s = (branch_offset >> 24) & 1;
18668 j1 = (!i1) ^ s;
18669 j2 = (!i2) ^ s;
18670 branch_insn |= j2 << 11;
18671 branch_insn |= j1 << 13;
18672 branch_insn |= s << 26;
18673 }
18674 break;
18675
18676 default:
18677 BFD_FAIL ();
18678 return FALSE;
18679 }
18680
8d9d9490
TP		 18681 bfd_put_16 (abfd, (branch_insn >> 16) & 0xffff, &contents[loc]);
18682 bfd_put_16 (abfd, branch_insn & 0xffff, &contents[loc + 2]);
48229727
JB		 18683
18684 return TRUE;
18685}
18686
a504d23a
LA		 18687/* Beginning of stm32l4xx work-around. */
18688
18689/* Functions encoding instructions necessary for the emission of the
18690 fix-stm32l4xx-629360.
18691 Encoding is extracted from the
18692 ARM (C) Architecture Reference Manual
18693 ARMv7-A and ARMv7-R edition
18694 ARM DDI 0406C.b (ID072512). */
18695
18696static inline bfd_vma
82188b29 18697create_instruction_branch_absolute (int branch_offset)
a504d23a
LA		 18698{
18699 /* A8.8.18 B (A8-334)
18700 B target_address (Encoding T4). */
18701 /* 1111 - 0Sii - iiii - iiii - 10J1 - Jiii - iiii - iiii. */
18702 /* jump offset is: S:I1:I2:imm10:imm11:0. */
18703 /* with : I1 = NOT (J1 EOR S) I2 = NOT (J2 EOR S). */
18704
a504d23a
LA		 18705 int s = ((branch_offset & 0x1000000) >> 24);
18706 int j1 = s ^ !((branch_offset & 0x800000) >> 23);
18707 int j2 = s ^ !((branch_offset & 0x400000) >> 22);
18708
18709 if (branch_offset < -(1 << 24) || branch_offset >= (1 << 24))
18710 BFD_ASSERT (0 && "Error: branch out of range. Cannot create branch.");
18711
18712 bfd_vma patched_inst = 0xf0009000
18713 | s << 26 /* S. */
18714 | (((unsigned long) (branch_offset) >> 12) & 0x3ff) << 16 /* imm10. */
18715 | j1 << 13 /* J1. */
18716 | j2 << 11 /* J2. */
18717 | (((unsigned long) (branch_offset) >> 1) & 0x7ff); /* imm11. */
18718
18719 return patched_inst;
18720}
18721
18722static inline bfd_vma
18723create_instruction_ldmia (int base_reg, int wback, int reg_mask)
18724{
18725 /* A8.8.57 LDM/LDMIA/LDMFD (A8-396)
18726 LDMIA Rn!, {Ra, Rb, Rc, ...} (Encoding T2). */
18727 bfd_vma patched_inst = 0xe8900000
18728 | (/*W=*/wback << 21)
18729 | (base_reg << 16)
18730 | (reg_mask & 0x0000ffff);
18731
18732 return patched_inst;
18733}
18734
18735static inline bfd_vma
18736create_instruction_ldmdb (int base_reg, int wback, int reg_mask)
18737{
18738 /* A8.8.60 LDMDB/LDMEA (A8-402)
18739 LDMDB Rn!, {Ra, Rb, Rc, ...} (Encoding T1). */
18740 bfd_vma patched_inst = 0xe9100000
18741 | (/*W=*/wback << 21)
18742 | (base_reg << 16)
18743 | (reg_mask & 0x0000ffff);
18744
18745 return patched_inst;
18746}
18747
18748static inline bfd_vma
18749create_instruction_mov (int target_reg, int source_reg)
18750{
18751 /* A8.8.103 MOV (register) (A8-486)
18752 MOV Rd, Rm (Encoding T1). */
18753 bfd_vma patched_inst = 0x4600
18754 | (target_reg & 0x7)
18755 | ((target_reg & 0x8) >> 3) << 7
18756 | (source_reg << 3);
18757
18758 return patched_inst;
18759}
18760
18761static inline bfd_vma
18762create_instruction_sub (int target_reg, int source_reg, int value)
18763{
18764 /* A8.8.221 SUB (immediate) (A8-708)
18765 SUB Rd, Rn, #value (Encoding T3). */
18766 bfd_vma patched_inst = 0xf1a00000
18767 | (target_reg << 8)
18768 | (source_reg << 16)
18769 | (/*S=*/0 << 20)
18770 | ((value & 0x800) >> 11) << 26
18771 | ((value & 0x700) >> 8) << 12
18772 | (value & 0x0ff);
18773
18774 return patched_inst;
18775}
18776
18777static inline bfd_vma
9239bbd3 18778create_instruction_vldmia (int base_reg, int is_dp, int wback, int num_words,
a504d23a
LA		 18779 int first_reg)
18780{
18781 /* A8.8.332 VLDM (A8-922)
9239bbd3
CM		 18782 VLMD{MODE} Rn{!}, {list} (Encoding T1 or T2). */
18783 bfd_vma patched_inst = (is_dp ? 0xec900b00 : 0xec900a00)
a504d23a
LA		 18784 | (/*W=*/wback << 21)
18785 | (base_reg << 16)
9239bbd3
CM		 18786 | (num_words & 0x000000ff)
18787 | (((unsigned)first_reg >> 1) & 0x0000000f) << 12
a504d23a
LA		 18788 | (first_reg & 0x00000001) << 22;
18789
18790 return patched_inst;
18791}
18792
18793static inline bfd_vma
9239bbd3
CM		 18794create_instruction_vldmdb (int base_reg, int is_dp, int num_words,
18795 int first_reg)
a504d23a
LA		 18796{
18797 /* A8.8.332 VLDM (A8-922)
9239bbd3
CM		 18798 VLMD{MODE} Rn!, {} (Encoding T1 or T2). */
18799 bfd_vma patched_inst = (is_dp ? 0xed300b00 : 0xed300a00)
a504d23a 18800 | (base_reg << 16)
9239bbd3
CM		 18801 | (num_words & 0x000000ff)
18802 | (((unsigned)first_reg >>1 ) & 0x0000000f) << 12
a504d23a
LA		 18803 | (first_reg & 0x00000001) << 22;
18804
18805 return patched_inst;
18806}
18807
18808static inline bfd_vma
18809create_instruction_udf_w (int value)
18810{
18811 /* A8.8.247 UDF (A8-758)
18812 Undefined (Encoding T2). */
18813 bfd_vma patched_inst = 0xf7f0a000
18814 | (value & 0x00000fff)
18815 | (value & 0x000f0000) << 16;
18816
18817 return patched_inst;
18818}
18819
18820static inline bfd_vma
18821create_instruction_udf (int value)
18822{
18823 /* A8.8.247 UDF (A8-758)
18824 Undefined (Encoding T1). */
18825 bfd_vma patched_inst = 0xde00
18826 | (value & 0xff);
18827
18828 return patched_inst;
18829}
18830
18831/* Functions writing an instruction in memory, returning the next
18832 memory position to write to. */
18833
18834static inline bfd_byte *
18835push_thumb2_insn32 (struct elf32_arm_link_hash_table * htab,
18836 bfd * output_bfd, bfd_byte *pt, insn32 insn)
18837{
18838 put_thumb2_insn (htab, output_bfd, insn, pt);
18839 return pt + 4;
18840}
18841
18842static inline bfd_byte *
18843push_thumb2_insn16 (struct elf32_arm_link_hash_table * htab,
18844 bfd * output_bfd, bfd_byte *pt, insn32 insn)
18845{
18846 put_thumb_insn (htab, output_bfd, insn, pt);
18847 return pt + 2;
18848}
18849
18850/* Function filling up a region in memory with T1 and T2 UDFs taking
18851 care of alignment. */
18852
18853static bfd_byte *
18854stm32l4xx_fill_stub_udf (struct elf32_arm_link_hash_table * htab,
07d6d2b8
AM		 18855 bfd * output_bfd,
18856 const bfd_byte * const base_stub_contents,
18857 bfd_byte * const from_stub_contents,
18858 const bfd_byte * const end_stub_contents)
a504d23a
LA		 18859{
18860 bfd_byte *current_stub_contents = from_stub_contents;
18861
18862 /* Fill the remaining of the stub with deterministic contents : UDF
18863 instructions.
18864 Check if realignment is needed on modulo 4 frontier using T1, to
18865 further use T2. */
18866 if ((current_stub_contents < end_stub_contents)
18867 && !((current_stub_contents - base_stub_contents) % 2)
18868 && ((current_stub_contents - base_stub_contents) % 4))
18869 current_stub_contents =
18870 push_thumb2_insn16 (htab, output_bfd, current_stub_contents,
18871 create_instruction_udf (0));
18872
18873 for (; current_stub_contents < end_stub_contents;)
18874 current_stub_contents =
18875 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18876 create_instruction_udf_w (0));
18877
18878 return current_stub_contents;
18879}
18880
18881/* Functions writing the stream of instructions equivalent to the
18882 derived sequence for ldmia, ldmdb, vldm respectively. */
18883
18884static void
18885stm32l4xx_create_replacing_stub_ldmia (struct elf32_arm_link_hash_table * htab,
18886 bfd * output_bfd,
18887 const insn32 initial_insn,
18888 const bfd_byte *const initial_insn_addr,
18889 bfd_byte *const base_stub_contents)
18890{
18891 int wback = (initial_insn & 0x00200000) >> 21;
18892 int ri, rn = (initial_insn & 0x000F0000) >> 16;
18893 int insn_all_registers = initial_insn & 0x0000ffff;
18894 int insn_low_registers, insn_high_registers;
18895 int usable_register_mask;
b25e998d 18896 int nb_registers = elf32_arm_popcount (insn_all_registers);
a504d23a
LA		 18897 int restore_pc = (insn_all_registers & (1 << 15)) ? 1 : 0;
18898 int restore_rn = (insn_all_registers & (1 << rn)) ? 1 : 0;
18899 bfd_byte *current_stub_contents = base_stub_contents;
18900
18901 BFD_ASSERT (is_thumb2_ldmia (initial_insn));
18902
18903 /* In BFD_ARM_STM32L4XX_FIX_ALL mode we may have to deal with
18904 smaller than 8 registers load sequences that do not cause the
18905 hardware issue. */
18906 if (nb_registers <= 8)
18907 {
18908 /* UNTOUCHED : LDMIA Rn{!}, {R-all-register-list}. */
18909 current_stub_contents =
18910 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18911 initial_insn);
18912
18913 /* B initial_insn_addr+4. */
18914 if (!restore_pc)
18915 current_stub_contents =
18916 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18917 create_instruction_branch_absolute
82188b29 18918 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 18919
18920 /* Fill the remaining of the stub with deterministic contents. */
18921 current_stub_contents =
18922 stm32l4xx_fill_stub_udf (htab, output_bfd,
18923 base_stub_contents, current_stub_contents,
18924 base_stub_contents +
18925 STM32L4XX_ERRATUM_LDM_VENEER_SIZE);
18926
18927 return;
18928 }
18929
18930 /* - reg_list[13] == 0. */
18931 BFD_ASSERT ((insn_all_registers & (1 << 13))==0);
18932
18933 /* - reg_list[14] & reg_list[15] != 1. */
18934 BFD_ASSERT ((insn_all_registers & 0xC000) != 0xC000);
18935
18936 /* - if (wback==1) reg_list[rn] == 0. */
18937 BFD_ASSERT (!wback || !restore_rn);
18938
18939 /* - nb_registers > 8. */
b25e998d 18940 BFD_ASSERT (elf32_arm_popcount (insn_all_registers) > 8);
a504d23a
LA		 18941
18942 /* At this point, LDMxx initial insn loads between 9 and 14 registers. */
18943
18944 /* In the following algorithm, we split this wide LDM using 2 LDM insns:
18945 - One with the 7 lowest registers (register mask 0x007F)
18946 This LDM will finally contain between 2 and 7 registers
18947 - One with the 7 highest registers (register mask 0xDF80)
18948 This ldm will finally contain between 2 and 7 registers. */
18949 insn_low_registers = insn_all_registers & 0x007F;
18950 insn_high_registers = insn_all_registers & 0xDF80;
18951
18952 /* A spare register may be needed during this veneer to temporarily
18953 handle the base register. This register will be restored with the
18954 last LDM operation.
18955 The usable register may be any general purpose register (that
18956 excludes PC, SP, LR : register mask is 0x1FFF). */
18957 usable_register_mask = 0x1FFF;
18958
18959 /* Generate the stub function. */
18960 if (wback)
18961 {
18962 /* LDMIA Rn!, {R-low-register-list} : (Encoding T2). */
18963 current_stub_contents =
18964 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18965 create_instruction_ldmia
18966 (rn, /*wback=*/1, insn_low_registers));
18967
18968 /* LDMIA Rn!, {R-high-register-list} : (Encoding T2). */
18969 current_stub_contents =
18970 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18971 create_instruction_ldmia
18972 (rn, /*wback=*/1, insn_high_registers));
18973 if (!restore_pc)
18974 {
18975 /* B initial_insn_addr+4. */
18976 current_stub_contents =
18977 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18978 create_instruction_branch_absolute
82188b29 18979 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 18980 }
18981 }
18982 else /* if (!wback). */
18983 {
18984 ri = rn;
18985
18986 /* If Rn is not part of the high-register-list, move it there. */
18987 if (!(insn_high_registers & (1 << rn)))
18988 {
18989 /* Choose a Ri in the high-register-list that will be restored. */
18990 ri = ctz (insn_high_registers & usable_register_mask & ~(1 << rn));
18991
18992 /* MOV Ri, Rn. */
18993 current_stub_contents =
18994 push_thumb2_insn16 (htab, output_bfd, current_stub_contents,
18995 create_instruction_mov (ri, rn));
18996 }
18997
18998 /* LDMIA Ri!, {R-low-register-list} : (Encoding T2). */
18999 current_stub_contents =
19000 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19001 create_instruction_ldmia
19002 (ri, /*wback=*/1, insn_low_registers));
19003
19004 /* LDMIA Ri, {R-high-register-list} : (Encoding T2). */
19005 current_stub_contents =
19006 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19007 create_instruction_ldmia
19008 (ri, /*wback=*/0, insn_high_registers));
19009
19010 if (!restore_pc)
19011 {
19012 /* B initial_insn_addr+4. */
19013 current_stub_contents =
19014 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19015 create_instruction_branch_absolute
82188b29 19016 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 19017 }
19018 }
19019
19020 /* Fill the remaining of the stub with deterministic contents. */
19021 current_stub_contents =
19022 stm32l4xx_fill_stub_udf (htab, output_bfd,
19023 base_stub_contents, current_stub_contents,
19024 base_stub_contents +
19025 STM32L4XX_ERRATUM_LDM_VENEER_SIZE);
19026}
19027
19028static void
19029stm32l4xx_create_replacing_stub_ldmdb (struct elf32_arm_link_hash_table * htab,
19030 bfd * output_bfd,
19031 const insn32 initial_insn,
19032 const bfd_byte *const initial_insn_addr,
19033 bfd_byte *const base_stub_contents)
19034{
19035 int wback = (initial_insn & 0x00200000) >> 21;
19036 int ri, rn = (initial_insn & 0x000f0000) >> 16;
19037 int insn_all_registers = initial_insn & 0x0000ffff;
19038 int insn_low_registers, insn_high_registers;
19039 int usable_register_mask;
19040 int restore_pc = (insn_all_registers & (1 << 15)) ? 1 : 0;
19041 int restore_rn = (insn_all_registers & (1 << rn)) ? 1 : 0;
b25e998d 19042 int nb_registers = elf32_arm_popcount (insn_all_registers);
a504d23a
LA		 19043 bfd_byte *current_stub_contents = base_stub_contents;
19044
19045 BFD_ASSERT (is_thumb2_ldmdb (initial_insn));
19046
19047 /* In BFD_ARM_STM32L4XX_FIX_ALL mode we may have to deal with
19048 smaller than 8 registers load sequences that do not cause the
19049 hardware issue. */
19050 if (nb_registers <= 8)
19051 {
19052 /* UNTOUCHED : LDMIA Rn{!}, {R-all-register-list}. */
19053 current_stub_contents =
19054 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19055 initial_insn);
19056
19057 /* B initial_insn_addr+4. */
19058 current_stub_contents =
19059 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19060 create_instruction_branch_absolute
82188b29 19061 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 19062
19063 /* Fill the remaining of the stub with deterministic contents. */
19064 current_stub_contents =
19065 stm32l4xx_fill_stub_udf (htab, output_bfd,
19066 base_stub_contents, current_stub_contents,
19067 base_stub_contents +
19068 STM32L4XX_ERRATUM_LDM_VENEER_SIZE);
19069
19070 return;
19071 }
19072
19073 /* - reg_list[13] == 0. */
19074 BFD_ASSERT ((insn_all_registers & (1 << 13)) == 0);
19075
19076 /* - reg_list[14] & reg_list[15] != 1. */
19077 BFD_ASSERT ((insn_all_registers & 0xC000) != 0xC000);
19078
19079 /* - if (wback==1) reg_list[rn] == 0. */
19080 BFD_ASSERT (!wback || !restore_rn);
19081
19082 /* - nb_registers > 8. */
b25e998d 19083 BFD_ASSERT (elf32_arm_popcount (insn_all_registers) > 8);
a504d23a
LA		 19084
19085 /* At this point, LDMxx initial insn loads between 9 and 14 registers. */
19086
19087 /* In the following algorithm, we split this wide LDM using 2 LDM insn:
19088 - One with the 7 lowest registers (register mask 0x007F)
19089 This LDM will finally contain between 2 and 7 registers
19090 - One with the 7 highest registers (register mask 0xDF80)
19091 This ldm will finally contain between 2 and 7 registers. */
19092 insn_low_registers = insn_all_registers & 0x007F;
19093 insn_high_registers = insn_all_registers & 0xDF80;
19094
19095 /* A spare register may be needed during this veneer to temporarily
19096 handle the base register. This register will be restored with
19097 the last LDM operation.
19098 The usable register may be any general purpose register (that excludes
19099 PC, SP, LR : register mask is 0x1FFF). */
19100 usable_register_mask = 0x1FFF;
19101
19102 /* Generate the stub function. */
19103 if (!wback && !restore_pc && !restore_rn)
19104 {
19105 /* Choose a Ri in the low-register-list that will be restored. */
19106 ri = ctz (insn_low_registers & usable_register_mask & ~(1 << rn));
19107
19108 /* MOV Ri, Rn. */
19109 current_stub_contents =
19110 push_thumb2_insn16 (htab, output_bfd, current_stub_contents,
19111 create_instruction_mov (ri, rn));
19112
19113 /* LDMDB Ri!, {R-high-register-list}. */
19114 current_stub_contents =
19115 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19116 create_instruction_ldmdb
19117 (ri, /*wback=*/1, insn_high_registers));
19118
19119 /* LDMDB Ri, {R-low-register-list}. */
19120 current_stub_contents =
19121 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19122 create_instruction_ldmdb
19123 (ri, /*wback=*/0, insn_low_registers));
19124
19125 /* B initial_insn_addr+4. */
19126 current_stub_contents =
19127 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19128 create_instruction_branch_absolute
82188b29 19129 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 19130 }
19131 else if (wback && !restore_pc && !restore_rn)
19132 {
19133 /* LDMDB Rn!, {R-high-register-list}. */
19134 current_stub_contents =
19135 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19136 create_instruction_ldmdb
19137 (rn, /*wback=*/1, insn_high_registers));
19138
19139 /* LDMDB Rn!, {R-low-register-list}. */
19140 current_stub_contents =
19141 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19142 create_instruction_ldmdb
19143 (rn, /*wback=*/1, insn_low_registers));
19144
19145 /* B initial_insn_addr+4. */
19146 current_stub_contents =
19147 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19148 create_instruction_branch_absolute
82188b29 19149 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 19150 }
19151 else if (!wback && restore_pc && !restore_rn)
19152 {
19153 /* Choose a Ri in the high-register-list that will be restored. */
19154 ri = ctz (insn_high_registers & usable_register_mask & ~(1 << rn));
19155
19156 /* SUB Ri, Rn, #(4*nb_registers). */
19157 current_stub_contents =
19158 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19159 create_instruction_sub (ri, rn, (4 * nb_registers)));
19160
19161 /* LDMIA Ri!, {R-low-register-list}. */
19162 current_stub_contents =
19163 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19164 create_instruction_ldmia
19165 (ri, /*wback=*/1, insn_low_registers));
19166
19167 /* LDMIA Ri, {R-high-register-list}. */
19168 current_stub_contents =
19169 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19170 create_instruction_ldmia
19171 (ri, /*wback=*/0, insn_high_registers));
19172 }
19173 else if (wback && restore_pc && !restore_rn)
19174 {
19175 /* Choose a Ri in the high-register-list that will be restored. */
19176 ri = ctz (insn_high_registers & usable_register_mask & ~(1 << rn));
19177
19178 /* SUB Rn, Rn, #(4*nb_registers) */
19179 current_stub_contents =
19180 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19181 create_instruction_sub (rn, rn, (4 * nb_registers)));
19182
19183 /* MOV Ri, Rn. */
19184 current_stub_contents =
19185 push_thumb2_insn16 (htab, output_bfd, current_stub_contents,
19186 create_instruction_mov (ri, rn));
19187
19188 /* LDMIA Ri!, {R-low-register-list}. */
19189 current_stub_contents =
19190 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19191 create_instruction_ldmia
19192 (ri, /*wback=*/1, insn_low_registers));
19193
19194 /* LDMIA Ri, {R-high-register-list}. */
19195 current_stub_contents =
19196 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19197 create_instruction_ldmia
19198 (ri, /*wback=*/0, insn_high_registers));
19199 }
19200 else if (!wback && !restore_pc && restore_rn)
19201 {
19202 ri = rn;
19203 if (!(insn_low_registers & (1 << rn)))
19204 {
19205 /* Choose a Ri in the low-register-list that will be restored. */
19206 ri = ctz (insn_low_registers & usable_register_mask & ~(1 << rn));
19207
19208 /* MOV Ri, Rn. */
19209 current_stub_contents =
19210 push_thumb2_insn16 (htab, output_bfd, current_stub_contents,
19211 create_instruction_mov (ri, rn));
19212 }
19213
19214 /* LDMDB Ri!, {R-high-register-list}. */
19215 current_stub_contents =
19216 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19217 create_instruction_ldmdb
19218 (ri, /*wback=*/1, insn_high_registers));
19219
19220 /* LDMDB Ri, {R-low-register-list}. */
19221 current_stub_contents =
19222 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19223 create_instruction_ldmdb
19224 (ri, /*wback=*/0, insn_low_registers));
19225
19226 /* B initial_insn_addr+4. */
19227 current_stub_contents =
19228 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19229 create_instruction_branch_absolute
82188b29 19230 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 19231 }
19232 else if (!wback && restore_pc && restore_rn)
19233 {
19234 ri = rn;
19235 if (!(insn_high_registers & (1 << rn)))
19236 {
19237 /* Choose a Ri in the high-register-list that will be restored. */
19238 ri = ctz (insn_high_registers & usable_register_mask & ~(1 << rn));
19239 }
19240
19241 /* SUB Ri, Rn, #(4*nb_registers). */
19242 current_stub_contents =
19243 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19244 create_instruction_sub (ri, rn, (4 * nb_registers)));
19245
19246 /* LDMIA Ri!, {R-low-register-list}. */
19247 current_stub_contents =
19248 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19249 create_instruction_ldmia
19250 (ri, /*wback=*/1, insn_low_registers));
19251
19252 /* LDMIA Ri, {R-high-register-list}. */
19253 current_stub_contents =
19254 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19255 create_instruction_ldmia
19256 (ri, /*wback=*/0, insn_high_registers));
19257 }
19258 else if (wback && restore_rn)
19259 {
19260 /* The assembler should not have accepted to encode this. */
19261 BFD_ASSERT (0 && "Cannot patch an instruction that has an "
19262 "undefined behavior.\n");
19263 }
19264
19265 /* Fill the remaining of the stub with deterministic contents. */
19266 current_stub_contents =
19267 stm32l4xx_fill_stub_udf (htab, output_bfd,
19268 base_stub_contents, current_stub_contents,
19269 base_stub_contents +
19270 STM32L4XX_ERRATUM_LDM_VENEER_SIZE);
19271
19272}
19273
19274static void
19275stm32l4xx_create_replacing_stub_vldm (struct elf32_arm_link_hash_table * htab,
19276 bfd * output_bfd,
19277 const insn32 initial_insn,
19278 const bfd_byte *const initial_insn_addr,
19279 bfd_byte *const base_stub_contents)
19280{
13c9c485 19281 int num_words = initial_insn & 0xff;
a504d23a
LA		 19282 bfd_byte *current_stub_contents = base_stub_contents;
19283
19284 BFD_ASSERT (is_thumb2_vldm (initial_insn));
19285
19286 /* In BFD_ARM_STM32L4XX_FIX_ALL mode we may have to deal with
9239bbd3 19287 smaller than 8 words load sequences that do not cause the
a504d23a 19288 hardware issue. */
9239bbd3 19289 if (num_words <= 8)
a504d23a
LA		 19290 {
19291 /* Untouched instruction. */
19292 current_stub_contents =
19293 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19294 initial_insn);
19295
19296 /* B initial_insn_addr+4. */
19297 current_stub_contents =
19298 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19299 create_instruction_branch_absolute
82188b29 19300 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 19301 }
19302 else
19303 {
9eaff861 19304 bfd_boolean is_dp = /* DP encoding. */
9239bbd3 19305 (initial_insn & 0xfe100f00) == 0xec100b00;
a504d23a
LA		 19306 bfd_boolean is_ia_nobang = /* (IA without !). */
19307 (((initial_insn << 7) >> 28) & 0xd) == 0x4;
19308 bfd_boolean is_ia_bang = /* (IA with !) - includes VPOP. */
19309 (((initial_insn << 7) >> 28) & 0xd) == 0x5;
19310 bfd_boolean is_db_bang = /* (DB with !). */
19311 (((initial_insn << 7) >> 28) & 0xd) == 0x9;
9239bbd3 19312 int base_reg = ((unsigned int) initial_insn << 12) >> 28;
a504d23a 19313 /* d = UInt (Vd:D);. */
9239bbd3 19314 int first_reg = ((((unsigned int) initial_insn << 16) >> 28) << 1)
a504d23a
LA		 19315 | (((unsigned int)initial_insn << 9) >> 31);
19316
9239bbd3
CM		 19317 /* Compute the number of 8-words chunks needed to split. */
19318 int chunks = (num_words % 8) ? (num_words / 8 + 1) : (num_words / 8);
a504d23a
LA		 19319 int chunk;
19320
19321 /* The test coverage has been done assuming the following
19322 hypothesis that exactly one of the previous is_ predicates is
19323 true. */
9239bbd3
CM		 19324 BFD_ASSERT ( (is_ia_nobang ^ is_ia_bang ^ is_db_bang)
19325 && !(is_ia_nobang & is_ia_bang & is_db_bang));
a504d23a 19326
9239bbd3 19327 /* We treat the cutting of the words in one pass for all
a504d23a
LA		 19328 cases, then we emit the adjustments:
19329
19330 vldm rx, {...}
19331 -> vldm rx!, {8_words_or_less} for each needed 8_word
19332 -> sub rx, rx, #size (list)
19333
19334 vldm rx!, {...}
19335 -> vldm rx!, {8_words_or_less} for each needed 8_word
19336 This also handles vpop instruction (when rx is sp)
19337
19338 vldmd rx!, {...}
19339 -> vldmb rx!, {8_words_or_less} for each needed 8_word. */
9239bbd3 19340 for (chunk = 0; chunk < chunks; ++chunk)
a504d23a 19341 {
9239bbd3
CM		 19342 bfd_vma new_insn = 0;
19343
a504d23a
LA		 19344 if (is_ia_nobang || is_ia_bang)
19345 {
9239bbd3
CM		 19346 new_insn = create_instruction_vldmia
19347 (base_reg,
19348 is_dp,
19349 /*wback= . */1,
19350 chunks - (chunk + 1) ?
19351 8 : num_words - chunk * 8,
19352 first_reg + chunk * 8);
a504d23a
LA		 19353 }
19354 else if (is_db_bang)
19355 {
9239bbd3
CM		 19356 new_insn = create_instruction_vldmdb
19357 (base_reg,
19358 is_dp,
19359 chunks - (chunk + 1) ?
19360 8 : num_words - chunk * 8,
19361 first_reg + chunk * 8);
a504d23a 19362 }
9239bbd3
CM		 19363
19364 if (new_insn)
19365 current_stub_contents =
19366 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19367 new_insn);
a504d23a
LA		 19368 }
19369
19370 /* Only this case requires the base register compensation
19371 subtract. */
19372 if (is_ia_nobang)
19373 {
19374 current_stub_contents =
19375 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19376 create_instruction_sub
9239bbd3 19377 (base_reg, base_reg, 4*num_words));
a504d23a
LA		 19378 }
19379
19380 /* B initial_insn_addr+4. */
19381 current_stub_contents =
19382 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19383 create_instruction_branch_absolute
82188b29 19384 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 19385 }
19386
19387 /* Fill the remaining of the stub with deterministic contents. */
19388 current_stub_contents =
19389 stm32l4xx_fill_stub_udf (htab, output_bfd,
19390 base_stub_contents, current_stub_contents,
19391 base_stub_contents +
19392 STM32L4XX_ERRATUM_VLDM_VENEER_SIZE);
19393}
19394
19395static void
19396stm32l4xx_create_replacing_stub (struct elf32_arm_link_hash_table * htab,
19397 bfd * output_bfd,
19398 const insn32 wrong_insn,
19399 const bfd_byte *const wrong_insn_addr,
19400 bfd_byte *const stub_contents)
19401{
19402 if (is_thumb2_ldmia (wrong_insn))
19403 stm32l4xx_create_replacing_stub_ldmia (htab, output_bfd,
19404 wrong_insn, wrong_insn_addr,
19405 stub_contents);
19406 else if (is_thumb2_ldmdb (wrong_insn))
19407 stm32l4xx_create_replacing_stub_ldmdb (htab, output_bfd,
19408 wrong_insn, wrong_insn_addr,
19409 stub_contents);
19410 else if (is_thumb2_vldm (wrong_insn))
19411 stm32l4xx_create_replacing_stub_vldm (htab, output_bfd,
19412 wrong_insn, wrong_insn_addr,
19413 stub_contents);
19414}
19415
19416/* End of stm32l4xx work-around. */
19417
19418
e489d0ae
PB		 19419/* Do code byteswapping. Return FALSE afterwards so that the section is
19420 written out as normal. */
19421
19422static bfd_boolean
c7b8f16e 19423elf32_arm_write_section (bfd *output_bfd,
8029a119
NC		 19424 struct bfd_link_info *link_info,
19425 asection *sec,
e489d0ae
PB		 19426 bfd_byte *contents)
19427{
48229727 19428 unsigned int mapcount, errcount;
8e3de13a 19429 _arm_elf_section_data *arm_data;
c7b8f16e 19430 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (link_info);
e489d0ae 19431 elf32_arm_section_map *map;
c7b8f16e 19432 elf32_vfp11_erratum_list *errnode;
a504d23a 19433 elf32_stm32l4xx_erratum_list *stm32l4xx_errnode;
e489d0ae
PB		 19434 bfd_vma ptr;
19435 bfd_vma end;
c7b8f16e 19436 bfd_vma offset = sec->output_section->vma + sec->output_offset;
e489d0ae 19437 bfd_byte tmp;
48229727 19438 unsigned int i;
57e8b36a 19439
4dfe6ac6
NC		 19440 if (globals == NULL)
19441 return FALSE;
19442
8e3de13a
NC		 19443 /* If this section has not been allocated an _arm_elf_section_data
19444 structure then we cannot record anything. */
19445 arm_data = get_arm_elf_section_data (sec);
19446 if (arm_data == NULL)
19447 return FALSE;
19448
19449 mapcount = arm_data->mapcount;
19450 map = arm_data->map;
c7b8f16e
JB		 19451 errcount = arm_data->erratumcount;
19452
19453 if (errcount != 0)
19454 {
19455 unsigned int endianflip = bfd_big_endian (output_bfd) ? 3 : 0;
19456
19457 for (errnode = arm_data->erratumlist; errnode != 0;
99059e56
RM		 19458 errnode = errnode->next)
19459 {
19460 bfd_vma target = errnode->vma - offset;
19461
19462 switch (errnode->type)
19463 {
19464 case VFP11_ERRATUM_BRANCH_TO_ARM_VENEER:
19465 {
19466 bfd_vma branch_to_veneer;
19467 /* Original condition code of instruction, plus bit mask for
19468 ARM B instruction. */
19469 unsigned int insn = (errnode->u.b.vfp_insn & 0xf0000000)
19470 | 0x0a000000;
c7b8f16e
JB		 19471
19472 /* The instruction is before the label. */
91d6fa6a 19473 target -= 4;
c7b8f16e
JB		 19474
19475 /* Above offset included in -4 below. */
19476 branch_to_veneer = errnode->u.b.veneer->vma
99059e56 19477 - errnode->vma - 4;
c7b8f16e
JB		 19478
19479 if ((signed) branch_to_veneer < -(1 << 25)
19480 || (signed) branch_to_veneer >= (1 << 25))
871b3ab2 19481 _bfd_error_handler (_("%pB: error: VFP11 veneer out of "
4eca0228 19482 "range"), output_bfd);
c7b8f16e 19483
99059e56
RM		 19484 insn |= (branch_to_veneer >> 2) & 0xffffff;
19485 contents[endianflip ^ target] = insn & 0xff;
19486 contents[endianflip ^ (target + 1)] = (insn >> 8) & 0xff;
19487 contents[endianflip ^ (target + 2)] = (insn >> 16) & 0xff;
19488 contents[endianflip ^ (target + 3)] = (insn >> 24) & 0xff;
19489 }
19490 break;
c7b8f16e
JB		 19491
19492 case VFP11_ERRATUM_ARM_VENEER:
99059e56
RM		 19493 {
19494 bfd_vma branch_from_veneer;
19495 unsigned int insn;
c7b8f16e 19496
99059e56
RM		 19497 /* Take size of veneer into account. */
19498 branch_from_veneer = errnode->u.v.branch->vma
19499 - errnode->vma - 12;
c7b8f16e
JB		 19500
19501 if ((signed) branch_from_veneer < -(1 << 25)
19502 || (signed) branch_from_veneer >= (1 << 25))
871b3ab2 19503 _bfd_error_handler (_("%pB: error: VFP11 veneer out of "
4eca0228 19504 "range"), output_bfd);
c7b8f16e 19505
99059e56
RM		 19506 /* Original instruction. */
19507 insn = errnode->u.v.branch->u.b.vfp_insn;
19508 contents[endianflip ^ target] = insn & 0xff;
19509 contents[endianflip ^ (target + 1)] = (insn >> 8) & 0xff;
19510 contents[endianflip ^ (target + 2)] = (insn >> 16) & 0xff;
19511 contents[endianflip ^ (target + 3)] = (insn >> 24) & 0xff;
19512
19513 /* Branch back to insn after original insn. */
19514 insn = 0xea000000 | ((branch_from_veneer >> 2) & 0xffffff);
19515 contents[endianflip ^ (target + 4)] = insn & 0xff;
19516 contents[endianflip ^ (target + 5)] = (insn >> 8) & 0xff;
19517 contents[endianflip ^ (target + 6)] = (insn >> 16) & 0xff;
19518 contents[endianflip ^ (target + 7)] = (insn >> 24) & 0xff;
19519 }
19520 break;
c7b8f16e 19521
99059e56
RM		 19522 default:
19523 abort ();
19524 }
19525 }
c7b8f16e 19526 }
e489d0ae 19527
a504d23a
LA		 19528 if (arm_data->stm32l4xx_erratumcount != 0)
19529 {
19530 for (stm32l4xx_errnode = arm_data->stm32l4xx_erratumlist;
19531 stm32l4xx_errnode != 0;
19532 stm32l4xx_errnode = stm32l4xx_errnode->next)
19533 {
19534 bfd_vma target = stm32l4xx_errnode->vma - offset;
19535
19536 switch (stm32l4xx_errnode->type)
19537 {
19538 case STM32L4XX_ERRATUM_BRANCH_TO_VENEER:
19539 {
19540 unsigned int insn;
19541 bfd_vma branch_to_veneer =
19542 stm32l4xx_errnode->u.b.veneer->vma - stm32l4xx_errnode->vma;
19543
19544 if ((signed) branch_to_veneer < -(1 << 24)
19545 || (signed) branch_to_veneer >= (1 << 24))
19546 {
19547 bfd_vma out_of_range =
19548 ((signed) branch_to_veneer < -(1 << 24)) ?
19549 - branch_to_veneer - (1 << 24) :
19550 ((signed) branch_to_veneer >= (1 << 24)) ?
19551 branch_to_veneer - (1 << 24) : 0;
19552
4eca0228 19553 _bfd_error_handler
2dcf00ce 19554 (_("%pB(%#" PRIx64 "): error: "
90b6238f
AM		 19555 "cannot create STM32L4XX veneer; "
19556 "jump out of range by %" PRId64 " bytes; "
19557 "cannot encode branch instruction"),
a504d23a 19558 output_bfd,
2dcf00ce
AM		 19559 (uint64_t) (stm32l4xx_errnode->vma - 4),
19560 (int64_t) out_of_range);
a504d23a
LA		 19561 continue;
19562 }
19563
19564 insn = create_instruction_branch_absolute
82188b29 19565 (stm32l4xx_errnode->u.b.veneer->vma - stm32l4xx_errnode->vma);
a504d23a 19566
a2699ef2
AM		 19567 /* The instruction is before the label. */
19568 target -= 4;
19569
a504d23a
LA		 19570 put_thumb2_insn (globals, output_bfd,
19571 (bfd_vma) insn, contents + target);
19572 }
19573 break;
19574
19575 case STM32L4XX_ERRATUM_VENEER:
19576 {
82188b29
NC		 19577 bfd_byte * veneer;
19578 bfd_byte * veneer_r;
a504d23a
LA		 19579 unsigned int insn;
19580
82188b29
NC		 19581 veneer = contents + target;
19582 veneer_r = veneer
19583 + stm32l4xx_errnode->u.b.veneer->vma
19584 - stm32l4xx_errnode->vma - 4;
a504d23a
LA		 19585
19586 if ((signed) (veneer_r - veneer -
19587 STM32L4XX_ERRATUM_VLDM_VENEER_SIZE >
19588 STM32L4XX_ERRATUM_LDM_VENEER_SIZE ?
19589 STM32L4XX_ERRATUM_VLDM_VENEER_SIZE :
19590 STM32L4XX_ERRATUM_LDM_VENEER_SIZE) < -(1 << 24)
19591 || (signed) (veneer_r - veneer) >= (1 << 24))
19592 {
90b6238f
AM		 19593 _bfd_error_handler (_("%pB: error: cannot create STM32L4XX "
19594 "veneer"), output_bfd);
a504d23a
LA		 19595 continue;
19596 }
19597
19598 /* Original instruction. */
19599 insn = stm32l4xx_errnode->u.v.branch->u.b.insn;
19600
19601 stm32l4xx_create_replacing_stub
19602 (globals, output_bfd, insn, (void*)veneer_r, (void*)veneer);
19603 }
19604 break;
19605
19606 default:
19607 abort ();
19608 }
19609 }
19610 }
19611
2468f9c9
PB		 19612 if (arm_data->elf.this_hdr.sh_type == SHT_ARM_EXIDX)
19613 {
19614 arm_unwind_table_edit *edit_node
99059e56 19615 = arm_data->u.exidx.unwind_edit_list;
2468f9c9 19616 /* Now, sec->size is the size of the section we will write. The original
99059e56 19617 size (before we merged duplicate entries and inserted EXIDX_CANTUNWIND
2468f9c9
PB		 19618 markers) was sec->rawsize. (This isn't the case if we perform no
19619 edits, then rawsize will be zero and we should use size). */
21d799b5 19620 bfd_byte *edited_contents = (bfd_byte *) bfd_malloc (sec->size);
2468f9c9
PB		 19621 unsigned int input_size = sec->rawsize ? sec->rawsize : sec->size;
19622 unsigned int in_index, out_index;
19623 bfd_vma add_to_offsets = 0;
19624
7a0fb7be
NC		 19625 if (edited_contents == NULL)
19626 return FALSE;
2468f9c9 19627 for (in_index = 0, out_index = 0; in_index * 8 < input_size || edit_node;)
99059e56 19628 {
2468f9c9
PB		 19629 if (edit_node)
19630 {
19631 unsigned int edit_index = edit_node->index;
b38cadfb 19632
2468f9c9 19633 if (in_index < edit_index && in_index * 8 < input_size)
99059e56 19634 {
2468f9c9
PB		 19635 copy_exidx_entry (output_bfd, edited_contents + out_index * 8,
19636 contents + in_index * 8, add_to_offsets);
19637 out_index++;
19638 in_index++;
19639 }
19640 else if (in_index == edit_index
19641 || (in_index * 8 >= input_size
19642 && edit_index == UINT_MAX))
99059e56 19643 {
2468f9c9
PB		 19644 switch (edit_node->type)
19645 {
19646 case DELETE_EXIDX_ENTRY:
19647 in_index++;
19648 add_to_offsets += 8;
19649 break;
b38cadfb 19650
2468f9c9
PB		 19651 case INSERT_EXIDX_CANTUNWIND_AT_END:
19652 {
99059e56 19653 asection *text_sec = edit_node->linked_section;
2468f9c9
PB		 19654 bfd_vma text_offset = text_sec->output_section->vma
19655 + text_sec->output_offset
19656 + text_sec->size;
19657 bfd_vma exidx_offset = offset + out_index * 8;
99059e56 19658 unsigned long prel31_offset;
2468f9c9
PB		 19659
19660 /* Note: this is meant to be equivalent to an
19661 R_ARM_PREL31 relocation. These synthetic
19662 EXIDX_CANTUNWIND markers are not relocated by the
19663 usual BFD method. */
19664 prel31_offset = (text_offset - exidx_offset)
19665 & 0x7ffffffful;
491d01d3
YU		 19666 if (bfd_link_relocatable (link_info))
19667 {
19668 /* Here relocation for new EXIDX_CANTUNWIND is
19669 created, so there is no need to
19670 adjust offset by hand. */
19671 prel31_offset = text_sec->output_offset
19672 + text_sec->size;
491d01d3 19673 }
2468f9c9
PB		 19674
19675 /* First address we can't unwind. */
19676 bfd_put_32 (output_bfd, prel31_offset,
19677 &edited_contents[out_index * 8]);
19678
19679 /* Code for EXIDX_CANTUNWIND. */
19680 bfd_put_32 (output_bfd, 0x1,
19681 &edited_contents[out_index * 8 + 4]);
19682
19683 out_index++;
19684 add_to_offsets -= 8;
19685 }
19686 break;
19687 }
b38cadfb 19688
2468f9c9
PB		 19689 edit_node = edit_node->next;
19690 }
19691 }
19692 else
19693 {
19694 /* No more edits, copy remaining entries verbatim. */
19695 copy_exidx_entry (output_bfd, edited_contents + out_index * 8,
19696 contents + in_index * 8, add_to_offsets);
19697 out_index++;
19698 in_index++;
19699 }
19700 }
19701
19702 if (!(sec->flags & SEC_EXCLUDE) && !(sec->flags & SEC_NEVER_LOAD))
19703 bfd_set_section_contents (output_bfd, sec->output_section,
19704 edited_contents,
19705 (file_ptr) sec->output_offset, sec->size);
19706
19707 return TRUE;
19708 }
19709
48229727
JB		 19710 /* Fix code to point to Cortex-A8 erratum stubs. */
19711 if (globals->fix_cortex_a8)
19712 {
19713 struct a8_branch_to_stub_data data;
19714
19715 data.writing_section = sec;
19716 data.contents = contents;
19717
a504d23a
LA		 19718 bfd_hash_traverse (& globals->stub_hash_table, make_branch_to_a8_stub,
19719 & data);
48229727
JB		 19720 }
19721
e489d0ae
PB		 19722 if (mapcount == 0)
19723 return FALSE;
19724
c7b8f16e 19725 if (globals->byteswap_code)
e489d0ae 19726 {
c7b8f16e 19727 qsort (map, mapcount, sizeof (* map), elf32_arm_compare_mapping);
57e8b36a 19728
c7b8f16e
JB		 19729 ptr = map[0].vma;
19730 for (i = 0; i < mapcount; i++)
99059e56
RM		 19731 {
19732 if (i == mapcount - 1)
c7b8f16e 19733 end = sec->size;
99059e56
RM		 19734 else
19735 end = map[i + 1].vma;
e489d0ae 19736
99059e56 19737 switch (map[i].type)
e489d0ae 19738 {
c7b8f16e
JB		 19739 case 'a':
19740 /* Byte swap code words. */
19741 while (ptr + 3 < end)
99059e56
RM		 19742 {
19743 tmp = contents[ptr];
19744 contents[ptr] = contents[ptr + 3];
19745 contents[ptr + 3] = tmp;
19746 tmp = contents[ptr + 1];
19747 contents[ptr + 1] = contents[ptr + 2];
19748 contents[ptr + 2] = tmp;
19749 ptr += 4;
19750 }
c7b8f16e 19751 break;
e489d0ae 19752
c7b8f16e
JB		 19753 case 't':
19754 /* Byte swap code halfwords. */
19755 while (ptr + 1 < end)
99059e56
RM		 19756 {
19757 tmp = contents[ptr];
19758 contents[ptr] = contents[ptr + 1];
19759 contents[ptr + 1] = tmp;
19760 ptr += 2;
19761 }
c7b8f16e
JB		 19762 break;
19763
19764 case 'd':
19765 /* Leave data alone. */
19766 break;
19767 }
99059e56
RM		 19768 ptr = end;
19769 }
e489d0ae 19770 }
8e3de13a 19771
93204d3a 19772 free (map);
47b2e99c 19773 arm_data->mapcount = -1;
c7b8f16e 19774 arm_data->mapsize = 0;
8e3de13a 19775 arm_data->map = NULL;
8e3de13a 19776
e489d0ae
PB		 19777 return FALSE;
19778}
19779
0beaef2b
PB		 19780/* Mangle thumb function symbols as we read them in. */
19781
8384fb8f 19782static bfd_boolean
0beaef2b
PB		 19783elf32_arm_swap_symbol_in (bfd * abfd,
19784 const void *psrc,
19785 const void *pshn,
19786 Elf_Internal_Sym *dst)
19787{
8384fb8f
AM		 19788 if (!bfd_elf32_swap_symbol_in (abfd, psrc, pshn, dst))
19789 return FALSE;
39d911fc 19790 dst->st_target_internal = 0;
0beaef2b
PB		 19791
19792 /* New EABI objects mark thumb function symbols by setting the low bit of
35fc36a8 19793 the address. */
63e1a0fc
PB		 19794 if (ELF_ST_TYPE (dst->st_info) == STT_FUNC
19795 || ELF_ST_TYPE (dst->st_info) == STT_GNU_IFUNC)
0beaef2b 19796 {
63e1a0fc
PB		 19797 if (dst->st_value & 1)
19798 {
19799 dst->st_value &= ~(bfd_vma) 1;
39d911fc
TP		 19800 ARM_SET_SYM_BRANCH_TYPE (dst->st_target_internal,
19801 ST_BRANCH_TO_THUMB);
63e1a0fc
PB		 19802 }
19803 else
39d911fc 19804 ARM_SET_SYM_BRANCH_TYPE (dst->st_target_internal, ST_BRANCH_TO_ARM);
35fc36a8
RS		 19805 }
19806 else if (ELF_ST_TYPE (dst->st_info) == STT_ARM_TFUNC)
19807 {
19808 dst->st_info = ELF_ST_INFO (ELF_ST_BIND (dst->st_info), STT_FUNC);
39d911fc 19809 ARM_SET_SYM_BRANCH_TYPE (dst->st_target_internal, ST_BRANCH_TO_THUMB);
0beaef2b 19810 }
35fc36a8 19811 else if (ELF_ST_TYPE (dst->st_info) == STT_SECTION)
39d911fc 19812 ARM_SET_SYM_BRANCH_TYPE (dst->st_target_internal, ST_BRANCH_LONG);
35fc36a8 19813 else
39d911fc 19814 ARM_SET_SYM_BRANCH_TYPE (dst->st_target_internal, ST_BRANCH_UNKNOWN);
35fc36a8 19815
8384fb8f 19816 return TRUE;
0beaef2b
PB		 19817}
19818
19819
19820/* Mangle thumb function symbols as we write them out. */
19821
19822static void
19823elf32_arm_swap_symbol_out (bfd *abfd,
19824 const Elf_Internal_Sym *src,
19825 void *cdst,
19826 void *shndx)
19827{
19828 Elf_Internal_Sym newsym;
19829
19830 /* We convert STT_ARM_TFUNC symbols into STT_FUNC with the low bit
19831 of the address set, as per the new EABI. We do this unconditionally
19832 because objcopy does not set the elf header flags until after
19833 it writes out the symbol table. */
39d911fc 19834 if (ARM_GET_SYM_BRANCH_TYPE (src->st_target_internal) == ST_BRANCH_TO_THUMB)
0beaef2b
PB		 19835 {
19836 newsym = *src;
34e77a92
RS		 19837 if (ELF_ST_TYPE (src->st_info) != STT_GNU_IFUNC)
19838 newsym.st_info = ELF_ST_INFO (ELF_ST_BIND (src->st_info), STT_FUNC);
0fa3dcad 19839 if (newsym.st_shndx != SHN_UNDEF)
99059e56
RM		 19840 {
19841 /* Do this only for defined symbols. At link type, the static
19842 linker will simulate the work of dynamic linker of resolving
19843 symbols and will carry over the thumbness of found symbols to
19844 the output symbol table. It's not clear how it happens, but
19845 the thumbness of undefined symbols can well be different at
19846 runtime, and writing '1' for them will be confusing for users
19847 and possibly for dynamic linker itself.
19848 */
19849 newsym.st_value |= 1;
19850 }
906e58ca 19851
0beaef2b
PB		 19852 src = &newsym;
19853 }
19854 bfd_elf32_swap_symbol_out (abfd, src, cdst, shndx);
19855}
19856
b294bdf8
MM		 19857/* Add the PT_ARM_EXIDX program header. */
19858
19859static bfd_boolean
906e58ca 19860elf32_arm_modify_segment_map (bfd *abfd,
b294bdf8
MM		 19861 struct bfd_link_info *info ATTRIBUTE_UNUSED)
19862{
19863 struct elf_segment_map *m;
19864 asection *sec;
19865
19866 sec = bfd_get_section_by_name (abfd, ".ARM.exidx");
19867 if (sec != NULL && (sec->flags & SEC_LOAD) != 0)
19868 {
19869 /* If there is already a PT_ARM_EXIDX header, then we do not
19870 want to add another one. This situation arises when running
19871 "strip"; the input binary already has the header. */
12bd6957 19872 m = elf_seg_map (abfd);
b294bdf8
MM		 19873 while (m && m->p_type != PT_ARM_EXIDX)
19874 m = m->next;
19875 if (!m)
19876 {
21d799b5 19877 m = (struct elf_segment_map *)
99059e56 19878 bfd_zalloc (abfd, sizeof (struct elf_segment_map));
b294bdf8
MM		 19879 if (m == NULL)
19880 return FALSE;
19881 m->p_type = PT_ARM_EXIDX;
19882 m->count = 1;
19883 m->sections[0] = sec;
19884
12bd6957
AM		 19885 m->next = elf_seg_map (abfd);
19886 elf_seg_map (abfd) = m;
b294bdf8
MM		 19887 }
19888 }
19889
19890 return TRUE;
19891}
19892
19893/* We may add a PT_ARM_EXIDX program header. */
19894
19895static int
a6b96beb
AM		 19896elf32_arm_additional_program_headers (bfd *abfd,
19897 struct bfd_link_info *info ATTRIBUTE_UNUSED)
b294bdf8
MM		 19898{
19899 asection *sec;
19900
19901 sec = bfd_get_section_by_name (abfd, ".ARM.exidx");
19902 if (sec != NULL && (sec->flags & SEC_LOAD) != 0)
19903 return 1;
19904 else
19905 return 0;
19906}
19907
34e77a92
RS		 19908/* Hook called by the linker routine which adds symbols from an object
19909 file. */
19910
19911static bfd_boolean
19912elf32_arm_add_symbol_hook (bfd *abfd, struct bfd_link_info *info,
19913 Elf_Internal_Sym *sym, const char **namep,
19914 flagword *flagsp, asection **secp, bfd_vma *valp)
19915{
c792917c
NC		 19916 if (elf32_arm_hash_table (info) == NULL)
19917 return FALSE;
19918
34e77a92
RS		 19919 if (elf32_arm_hash_table (info)->vxworks_p
19920 && !elf_vxworks_add_symbol_hook (abfd, info, sym, namep,
19921 flagsp, secp, valp))
19922 return FALSE;
19923
19924 return TRUE;
19925}
19926
0beaef2b 19927/* We use this to override swap_symbol_in and swap_symbol_out. */
906e58ca
NC		 19928const struct elf_size_info elf32_arm_size_info =
19929{
0beaef2b
PB		 19930 sizeof (Elf32_External_Ehdr),
19931 sizeof (Elf32_External_Phdr),
19932 sizeof (Elf32_External_Shdr),
19933 sizeof (Elf32_External_Rel),
19934 sizeof (Elf32_External_Rela),
19935 sizeof (Elf32_External_Sym),
19936 sizeof (Elf32_External_Dyn),
19937 sizeof (Elf_External_Note),
19938 4,
19939 1,
19940 32, 2,
19941 ELFCLASS32, EV_CURRENT,
19942 bfd_elf32_write_out_phdrs,
19943 bfd_elf32_write_shdrs_and_ehdr,
1489a3a0 19944 bfd_elf32_checksum_contents,
0beaef2b
PB		 19945 bfd_elf32_write_relocs,
19946 elf32_arm_swap_symbol_in,
19947 elf32_arm_swap_symbol_out,
19948 bfd_elf32_slurp_reloc_table,
19949 bfd_elf32_slurp_symbol_table,
19950 bfd_elf32_swap_dyn_in,
19951 bfd_elf32_swap_dyn_out,
19952 bfd_elf32_swap_reloc_in,
19953 bfd_elf32_swap_reloc_out,
19954 bfd_elf32_swap_reloca_in,
19955 bfd_elf32_swap_reloca_out
19956};
19957
685e70ae
VK		 19958static bfd_vma
19959read_code32 (const bfd *abfd, const bfd_byte *addr)
19960{
19961 /* V7 BE8 code is always little endian. */
19962 if ((elf_elfheader (abfd)->e_flags & EF_ARM_BE8) != 0)
19963 return bfd_getl32 (addr);
19964
19965 return bfd_get_32 (abfd, addr);
19966}
19967
19968static bfd_vma
19969read_code16 (const bfd *abfd, const bfd_byte *addr)
19970{
19971 /* V7 BE8 code is always little endian. */
19972 if ((elf_elfheader (abfd)->e_flags & EF_ARM_BE8) != 0)
19973 return bfd_getl16 (addr);
19974
19975 return bfd_get_16 (abfd, addr);
19976}
19977
6a631e86
YG		 19978/* Return size of plt0 entry starting at ADDR
19979 or (bfd_vma) -1 if size can not be determined. */
19980
19981static bfd_vma
19982elf32_arm_plt0_size (const bfd *abfd, const bfd_byte *addr)
19983{
19984 bfd_vma first_word;
19985 bfd_vma plt0_size;
19986
685e70ae 19987 first_word = read_code32 (abfd, addr);
6a631e86
YG		 19988
19989 if (first_word == elf32_arm_plt0_entry[0])
19990 plt0_size = 4 * ARRAY_SIZE (elf32_arm_plt0_entry);
19991 else if (first_word == elf32_thumb2_plt0_entry[0])
19992 plt0_size = 4 * ARRAY_SIZE (elf32_thumb2_plt0_entry);
19993 else
19994 /* We don't yet handle this PLT format. */
19995 return (bfd_vma) -1;
19996
19997 return plt0_size;
19998}
19999
20000/* Return size of plt entry starting at offset OFFSET
20001 of plt section located at address START
20002 or (bfd_vma) -1 if size can not be determined. */
20003
20004static bfd_vma
20005elf32_arm_plt_size (const bfd *abfd, const bfd_byte *start, bfd_vma offset)
20006{
20007 bfd_vma first_insn;
20008 bfd_vma plt_size = 0;
20009 const bfd_byte *addr = start + offset;
20010
20011 /* PLT entry size if fixed on Thumb-only platforms. */
685e70ae 20012 if (read_code32 (abfd, start) == elf32_thumb2_plt0_entry[0])
6a631e86
YG		 20013 return 4 * ARRAY_SIZE (elf32_thumb2_plt_entry);
20014
20015 /* Respect Thumb stub if necessary. */
685e70ae 20016 if (read_code16 (abfd, addr) == elf32_arm_plt_thumb_stub[0])
6a631e86
YG		 20017 {
20018 plt_size += 2 * ARRAY_SIZE(elf32_arm_plt_thumb_stub);
20019 }
20020
20021 /* Strip immediate from first add. */
685e70ae 20022 first_insn = read_code32 (abfd, addr + plt_size) & 0xffffff00;
6a631e86
YG		 20023
20024#ifdef FOUR_WORD_PLT
20025 if (first_insn == elf32_arm_plt_entry[0])
20026 plt_size += 4 * ARRAY_SIZE (elf32_arm_plt_entry);
20027#else
20028 if (first_insn == elf32_arm_plt_entry_long[0])
20029 plt_size += 4 * ARRAY_SIZE (elf32_arm_plt_entry_long);
20030 else if (first_insn == elf32_arm_plt_entry_short[0])
20031 plt_size += 4 * ARRAY_SIZE (elf32_arm_plt_entry_short);
20032#endif
20033 else
20034 /* We don't yet handle this PLT format. */
20035 return (bfd_vma) -1;
20036
20037 return plt_size;
20038}
20039
20040/* Implementation is shamelessly borrowed from _bfd_elf_get_synthetic_symtab. */
20041
20042static long
20043elf32_arm_get_synthetic_symtab (bfd *abfd,
20044 long symcount ATTRIBUTE_UNUSED,
20045 asymbol **syms ATTRIBUTE_UNUSED,
20046 long dynsymcount,
20047 asymbol **dynsyms,
20048 asymbol **ret)
20049{
20050 asection *relplt;
20051 asymbol *s;
20052 arelent *p;
20053 long count, i, n;
20054 size_t size;
20055 Elf_Internal_Shdr *hdr;
20056 char *names;
20057 asection *plt;
20058 bfd_vma offset;
20059 bfd_byte *data;
20060
20061 *ret = NULL;
20062
20063 if ((abfd->flags & (DYNAMIC | EXEC_P)) == 0)
20064 return 0;
20065
20066 if (dynsymcount <= 0)
20067 return 0;
20068
20069 relplt = bfd_get_section_by_name (abfd, ".rel.plt");
20070 if (relplt == NULL)
20071 return 0;
20072
20073 hdr = &elf_section_data (relplt)->this_hdr;
20074 if (hdr->sh_link != elf_dynsymtab (abfd)
20075 || (hdr->sh_type != SHT_REL && hdr->sh_type != SHT_RELA))
20076 return 0;
20077
20078 plt = bfd_get_section_by_name (abfd, ".plt");
20079 if (plt == NULL)
20080 return 0;
20081
20082 if (!elf32_arm_size_info.slurp_reloc_table (abfd, relplt, dynsyms, TRUE))
20083 return -1;
20084
20085 data = plt->contents;
20086 if (data == NULL)
20087 {
20088 if (!bfd_get_full_section_contents(abfd, (asection *) plt, &data) || data == NULL)
20089 return -1;
20090 bfd_cache_section_contents((asection *) plt, data);
20091 }
20092
20093 count = relplt->size / hdr->sh_entsize;
20094 size = count * sizeof (asymbol);
20095 p = relplt->relocation;
20096 for (i = 0; i < count; i++, p += elf32_arm_size_info.int_rels_per_ext_rel)
20097 {
20098 size += strlen ((*p->sym_ptr_ptr)->name) + sizeof ("@plt");
20099 if (p->addend != 0)
20100 size += sizeof ("+0x") - 1 + 8;
20101 }
20102
20103 s = *ret = (asymbol *) bfd_malloc (size);
20104 if (s == NULL)
20105 return -1;
20106
20107 offset = elf32_arm_plt0_size (abfd, data);
20108 if (offset == (bfd_vma) -1)
20109 return -1;
20110
20111 names = (char *) (s + count);
20112 p = relplt->relocation;
20113 n = 0;
20114 for (i = 0; i < count; i++, p += elf32_arm_size_info.int_rels_per_ext_rel)
20115 {
20116 size_t len;
20117
20118 bfd_vma plt_size = elf32_arm_plt_size (abfd, data, offset);
20119 if (plt_size == (bfd_vma) -1)
20120 break;
20121
20122 *s = **p->sym_ptr_ptr;
20123 /* Undefined syms won't have BSF_LOCAL or BSF_GLOBAL set. Since
20124 we are defining a symbol, ensure one of them is set. */
20125 if ((s->flags & BSF_LOCAL) == 0)
20126 s->flags |= BSF_GLOBAL;
20127 s->flags |= BSF_SYNTHETIC;
20128 s->section = plt;
20129 s->value = offset;
20130 s->name = names;
20131 s->udata.p = NULL;
20132 len = strlen ((*p->sym_ptr_ptr)->name);
20133 memcpy (names, (*p->sym_ptr_ptr)->name, len);
20134 names += len;
20135 if (p->addend != 0)
20136 {
20137 char buf[30], *a;
20138
20139 memcpy (names, "+0x", sizeof ("+0x") - 1);
20140 names += sizeof ("+0x") - 1;
20141 bfd_sprintf_vma (abfd, buf, p->addend);
20142 for (a = buf; *a == '0'; ++a)
20143 ;
20144 len = strlen (a);
20145 memcpy (names, a, len);
20146 names += len;
20147 }
20148 memcpy (names, "@plt", sizeof ("@plt"));
20149 names += sizeof ("@plt");
20150 ++s, ++n;
20151 offset += plt_size;
20152 }
20153
20154 return n;
20155}
20156
ac4c9b04 20157static bfd_boolean
8c803a2d 20158elf32_arm_section_flags (const Elf_Internal_Shdr *hdr)
ac4c9b04 20159{
f0728ee3 20160 if (hdr->sh_flags & SHF_ARM_PURECODE)
8c803a2d 20161 hdr->bfd_section->flags |= SEC_ELF_PURECODE;
ac4c9b04
MG		 20162 return TRUE;
20163}
20164
20165static flagword
20166elf32_arm_lookup_section_flags (char *flag_name)
20167{
f0728ee3
AV		 20168 if (!strcmp (flag_name, "SHF_ARM_PURECODE"))
20169 return SHF_ARM_PURECODE;
ac4c9b04
MG		 20170
20171 return SEC_NO_FLAGS;
20172}
20173
491d01d3
YU		 20174static unsigned int
20175elf32_arm_count_additional_relocs (asection *sec)
20176{
20177 struct _arm_elf_section_data *arm_data;
20178 arm_data = get_arm_elf_section_data (sec);
5025eb7c 20179
6342be70 20180 return arm_data == NULL ? 0 : arm_data->additional_reloc_count;
491d01d3
YU		 20181}
20182
5522f910 20183/* Called to set the sh_flags, sh_link and sh_info fields of OSECTION which
9eaff861 20184 has a type >= SHT_LOOS. Returns TRUE if these fields were initialised
5522f910
NC		 20185 FALSE otherwise. ISECTION is the best guess matching section from the
20186 input bfd IBFD, but it might be NULL. */
20187
20188static bfd_boolean
20189elf32_arm_copy_special_section_fields (const bfd *ibfd ATTRIBUTE_UNUSED,
20190 bfd *obfd ATTRIBUTE_UNUSED,
20191 const Elf_Internal_Shdr *isection ATTRIBUTE_UNUSED,
20192 Elf_Internal_Shdr *osection)
20193{
20194 switch (osection->sh_type)
20195 {
20196 case SHT_ARM_EXIDX:
20197 {
20198 Elf_Internal_Shdr **oheaders = elf_elfsections (obfd);
20199 Elf_Internal_Shdr **iheaders = elf_elfsections (ibfd);
20200 unsigned i = 0;
20201
20202 osection->sh_flags = SHF_ALLOC | SHF_LINK_ORDER;
20203 osection->sh_info = 0;
20204
20205 /* The sh_link field must be set to the text section associated with
20206 this index section. Unfortunately the ARM EHABI does not specify
20207 exactly how to determine this association. Our caller does try
20208 to match up OSECTION with its corresponding input section however
20209 so that is a good first guess. */
20210 if (isection != NULL
20211 && osection->bfd_section != NULL
20212 && isection->bfd_section != NULL
20213 && isection->bfd_section->output_section != NULL
20214 && isection->bfd_section->output_section == osection->bfd_section
20215 && iheaders != NULL
20216 && isection->sh_link > 0
20217 && isection->sh_link < elf_numsections (ibfd)
20218 && iheaders[isection->sh_link]->bfd_section != NULL
20219 && iheaders[isection->sh_link]->bfd_section->output_section != NULL
20220 )
20221 {
20222 for (i = elf_numsections (obfd); i-- > 0;)
20223 if (oheaders[i]->bfd_section
20224 == iheaders[isection->sh_link]->bfd_section->output_section)
20225 break;
20226 }
9eaff861 20227
5522f910
NC		 20228 if (i == 0)
20229 {
20230 /* Failing that we have to find a matching section ourselves. If
20231 we had the output section name available we could compare that
20232 with input section names. Unfortunately we don't. So instead
20233 we use a simple heuristic and look for the nearest executable
20234 section before this one. */
20235 for (i = elf_numsections (obfd); i-- > 0;)
20236 if (oheaders[i] == osection)
20237 break;
20238 if (i == 0)
20239 break;
20240
20241 while (i-- > 0)
20242 if (oheaders[i]->sh_type == SHT_PROGBITS
20243 && (oheaders[i]->sh_flags & (SHF_ALLOC | SHF_EXECINSTR))
20244 == (SHF_ALLOC | SHF_EXECINSTR))
20245 break;
20246 }
20247
20248 if (i)
20249 {
20250 osection->sh_link = i;
20251 /* If the text section was part of a group
20252 then the index section should be too. */
20253 if (oheaders[i]->sh_flags & SHF_GROUP)
20254 osection->sh_flags |= SHF_GROUP;
20255 return TRUE;
20256 }
20257 }
20258 break;
20259
20260 case SHT_ARM_PREEMPTMAP:
20261 osection->sh_flags = SHF_ALLOC;
20262 break;
20263
20264 case SHT_ARM_ATTRIBUTES:
20265 case SHT_ARM_DEBUGOVERLAY:
20266 case SHT_ARM_OVERLAYSECTION:
20267 default:
20268 break;
20269 }
20270
20271 return FALSE;
20272}
20273
d691934d
NC		 20274/* Returns TRUE if NAME is an ARM mapping symbol.
20275 Traditionally the symbols $a, $d and $t have been used.
20276 The ARM ELF standard also defines $x (for A64 code). It also allows a
20277 period initiated suffix to be added to the symbol: "$[adtx]\.[:sym_char]+".
20278 Other tools might also produce $b (Thumb BL), $f, $p, $m and $v, but we do
20279 not support them here. $t.x indicates the start of ThumbEE instructions. */
20280
20281static bfd_boolean
20282is_arm_mapping_symbol (const char * name)
20283{
20284 return name != NULL /* Paranoia. */
20285 && name[0] == '$' /* Note: if objcopy --prefix-symbols has been used then
20286 the mapping symbols could have acquired a prefix.
20287 We do not support this here, since such symbols no
20288 longer conform to the ARM ELF ABI. */
20289 && (name[1] == 'a' || name[1] == 'd' || name[1] == 't' || name[1] == 'x')
20290 && (name[2] == 0 || name[2] == '.');
20291 /* FIXME: Strictly speaking the symbol is only a valid mapping symbol if
20292 any characters that follow the period are legal characters for the body
20293 of a symbol's name. For now we just assume that this is the case. */
20294}
20295
fca2a38f
NC		 20296/* Make sure that mapping symbols in object files are not removed via the
20297 "strip --strip-unneeded" tool. These symbols are needed in order to
20298 correctly generate interworking veneers, and for byte swapping code
20299 regions. Once an object file has been linked, it is safe to remove the
20300 symbols as they will no longer be needed. */
20301
20302static void
20303elf32_arm_backend_symbol_processing (bfd *abfd, asymbol *sym)
20304{
20305 if (((abfd->flags & (EXEC_P | DYNAMIC)) == 0)
fca2a38f 20306 && sym->section != bfd_abs_section_ptr
d691934d 20307 && is_arm_mapping_symbol (sym->name))
fca2a38f
NC		 20308 sym->flags |= BSF_KEEP;
20309}
20310
5522f910
NC		 20311#undef elf_backend_copy_special_section_fields
20312#define elf_backend_copy_special_section_fields elf32_arm_copy_special_section_fields
20313
252b5132 20314#define ELF_ARCH bfd_arch_arm
ae95ffa6 20315#define ELF_TARGET_ID ARM_ELF_DATA
252b5132 20316#define ELF_MACHINE_CODE EM_ARM
d0facd1b
NC		 20317#ifdef __QNXTARGET__
20318#define ELF_MAXPAGESIZE 0x1000
20319#else
7572ca89 20320#define ELF_MAXPAGESIZE 0x10000
d0facd1b 20321#endif
b1342370 20322#define ELF_MINPAGESIZE 0x1000
24718e3b 20323#define ELF_COMMONPAGESIZE 0x1000
252b5132 20324
07d6d2b8 20325#define bfd_elf32_mkobject elf32_arm_mkobject
ba93b8ac 20326
99e4ae17
AJ		 20327#define bfd_elf32_bfd_copy_private_bfd_data elf32_arm_copy_private_bfd_data
20328#define bfd_elf32_bfd_merge_private_bfd_data elf32_arm_merge_private_bfd_data
252b5132
RH		 20329#define bfd_elf32_bfd_set_private_flags elf32_arm_set_private_flags
20330#define bfd_elf32_bfd_print_private_bfd_data elf32_arm_print_private_bfd_data
07d6d2b8 20331#define bfd_elf32_bfd_link_hash_table_create elf32_arm_link_hash_table_create
dc810e39 20332#define bfd_elf32_bfd_reloc_type_lookup elf32_arm_reloc_type_lookup
b38cadfb 20333#define bfd_elf32_bfd_reloc_name_lookup elf32_arm_reloc_name_lookup
07d6d2b8 20334#define bfd_elf32_find_inliner_info elf32_arm_find_inliner_info
e489d0ae 20335#define bfd_elf32_new_section_hook elf32_arm_new_section_hook
3c9458e9 20336#define bfd_elf32_bfd_is_target_special_symbol elf32_arm_is_target_special_symbol
3e6b1042 20337#define bfd_elf32_bfd_final_link elf32_arm_final_link
07d6d2b8 20338#define bfd_elf32_get_synthetic_symtab elf32_arm_get_synthetic_symtab
252b5132 20339
07d6d2b8 20340#define elf_backend_get_symbol_type elf32_arm_get_symbol_type
e7679060 20341#define elf_backend_maybe_function_sym elf32_arm_maybe_function_sym
07d6d2b8 20342#define elf_backend_gc_mark_hook elf32_arm_gc_mark_hook
6a5bb875 20343#define elf_backend_gc_mark_extra_sections elf32_arm_gc_mark_extra_sections
07d6d2b8 20344#define elf_backend_check_relocs elf32_arm_check_relocs
9eaff861 20345#define elf_backend_update_relocs elf32_arm_update_relocs
dc810e39 20346#define elf_backend_relocate_section elf32_arm_relocate_section
e489d0ae 20347#define elf_backend_write_section elf32_arm_write_section
252b5132 20348#define elf_backend_adjust_dynamic_symbol elf32_arm_adjust_dynamic_symbol
07d6d2b8 20349#define elf_backend_create_dynamic_sections elf32_arm_create_dynamic_sections
252b5132
RH		 20350#define elf_backend_finish_dynamic_symbol elf32_arm_finish_dynamic_symbol
20351#define elf_backend_finish_dynamic_sections elf32_arm_finish_dynamic_sections
20352#define elf_backend_size_dynamic_sections elf32_arm_size_dynamic_sections
0855e32b 20353#define elf_backend_always_size_sections elf32_arm_always_size_sections
74541ad4 20354#define elf_backend_init_index_section _bfd_elf_init_2_index_sections
ed7e9d0b 20355#define elf_backend_init_file_header elf32_arm_init_file_header
99e4ae17 20356#define elf_backend_reloc_type_class elf32_arm_reloc_type_class
c178919b 20357#define elf_backend_object_p elf32_arm_object_p
07d6d2b8
AM		 20358#define elf_backend_fake_sections elf32_arm_fake_sections
20359#define elf_backend_section_from_shdr elf32_arm_section_from_shdr
20360#define elf_backend_final_write_processing elf32_arm_final_write_processing
20361#define elf_backend_copy_indirect_symbol elf32_arm_copy_indirect_symbol
0beaef2b 20362#define elf_backend_size_info elf32_arm_size_info
b294bdf8 20363#define elf_backend_modify_segment_map elf32_arm_modify_segment_map
07d6d2b8
AM		 20364#define elf_backend_additional_program_headers elf32_arm_additional_program_headers
20365#define elf_backend_output_arch_local_syms elf32_arm_output_arch_local_syms
54ddd295 20366#define elf_backend_filter_implib_symbols elf32_arm_filter_implib_symbols
07d6d2b8 20367#define elf_backend_begin_write_processing elf32_arm_begin_write_processing
34e77a92 20368#define elf_backend_add_symbol_hook elf32_arm_add_symbol_hook
491d01d3 20369#define elf_backend_count_additional_relocs elf32_arm_count_additional_relocs
fca2a38f 20370#define elf_backend_symbol_processing elf32_arm_backend_symbol_processing
906e58ca
NC		 20371
20372#define elf_backend_can_refcount 1
20373#define elf_backend_can_gc_sections 1
20374#define elf_backend_plt_readonly 1
20375#define elf_backend_want_got_plt 1
20376#define elf_backend_want_plt_sym 0
5474d94f 20377#define elf_backend_want_dynrelro 1
906e58ca
NC		 20378#define elf_backend_may_use_rel_p 1
20379#define elf_backend_may_use_rela_p 0
4e7fd91e 20380#define elf_backend_default_use_rela_p 0
64f52338 20381#define elf_backend_dtrel_excludes_plt 1
252b5132 20382
04f7c78d 20383#define elf_backend_got_header_size 12
b68a20d6 20384#define elf_backend_extern_protected_data 1
04f7c78d 20385
07d6d2b8 20386#undef elf_backend_obj_attrs_vendor
906e58ca 20387#define elf_backend_obj_attrs_vendor "aeabi"
07d6d2b8 20388#undef elf_backend_obj_attrs_section
906e58ca 20389#define elf_backend_obj_attrs_section ".ARM.attributes"
07d6d2b8 20390#undef elf_backend_obj_attrs_arg_type
906e58ca 20391#define elf_backend_obj_attrs_arg_type elf32_arm_obj_attrs_arg_type
07d6d2b8 20392#undef elf_backend_obj_attrs_section_type
104d59d1 20393#define elf_backend_obj_attrs_section_type SHT_ARM_ATTRIBUTES
b38cadfb 20394#define elf_backend_obj_attrs_order elf32_arm_obj_attrs_order
07d6d2b8 20395#define elf_backend_obj_attrs_handle_unknown elf32_arm_obj_attrs_handle_unknown
104d59d1 20396
07d6d2b8 20397#undef elf_backend_section_flags
ac4c9b04 20398#define elf_backend_section_flags elf32_arm_section_flags
07d6d2b8
AM		 20399#undef elf_backend_lookup_section_flags_hook
20400#define elf_backend_lookup_section_flags_hook elf32_arm_lookup_section_flags
ac4c9b04 20401
a2f63b2e
MR		 20402#define elf_backend_linux_prpsinfo32_ugid16 TRUE
20403
252b5132 20404#include "elf32-target.h"
7f266840 20405
b38cadfb
NC		 20406/* Native Client targets. */
20407
20408#undef TARGET_LITTLE_SYM
6d00b590 20409#define TARGET_LITTLE_SYM arm_elf32_nacl_le_vec
b38cadfb
NC		 20410#undef TARGET_LITTLE_NAME
20411#define TARGET_LITTLE_NAME "elf32-littlearm-nacl"
20412#undef TARGET_BIG_SYM
6d00b590 20413#define TARGET_BIG_SYM arm_elf32_nacl_be_vec
b38cadfb
NC		 20414#undef TARGET_BIG_NAME
20415#define TARGET_BIG_NAME "elf32-bigarm-nacl"
20416
20417/* Like elf32_arm_link_hash_table_create -- but overrides
20418 appropriately for NaCl. */
20419
20420static struct bfd_link_hash_table *
20421elf32_arm_nacl_link_hash_table_create (bfd *abfd)
20422{
20423 struct bfd_link_hash_table *ret;
20424
20425 ret = elf32_arm_link_hash_table_create (abfd);
20426 if (ret)
20427 {
20428 struct elf32_arm_link_hash_table *htab
20429 = (struct elf32_arm_link_hash_table *) ret;
20430
20431 htab->nacl_p = 1;
20432
20433 htab->plt_header_size = 4 * ARRAY_SIZE (elf32_arm_nacl_plt0_entry);
20434 htab->plt_entry_size = 4 * ARRAY_SIZE (elf32_arm_nacl_plt_entry);
20435 }
20436 return ret;
20437}
20438
20439/* Since NaCl doesn't use the ARM-specific unwind format, we don't
20440 really need to use elf32_arm_modify_segment_map. But we do it
20441 anyway just to reduce gratuitous differences with the stock ARM backend. */
20442
20443static bfd_boolean
20444elf32_arm_nacl_modify_segment_map (bfd *abfd, struct bfd_link_info *info)
20445{
20446 return (elf32_arm_modify_segment_map (abfd, info)
20447 && nacl_modify_segment_map (abfd, info));
20448}
20449
cc364be6
AM		 20450static bfd_boolean
20451elf32_arm_nacl_final_write_processing (bfd *abfd)
887badb3 20452{
cc364be6
AM		 20453 arm_final_write_processing (abfd);
20454 return nacl_final_write_processing (abfd);
887badb3
RM		 20455}
20456
6a631e86
YG		 20457static bfd_vma
20458elf32_arm_nacl_plt_sym_val (bfd_vma i, const asection *plt,
20459 const arelent *rel ATTRIBUTE_UNUSED)
20460{
20461 return plt->vma
20462 + 4 * (ARRAY_SIZE (elf32_arm_nacl_plt0_entry) +
20463 i * ARRAY_SIZE (elf32_arm_nacl_plt_entry));
20464}
887badb3 20465
b38cadfb 20466#undef elf32_bed
6a631e86 20467#define elf32_bed elf32_arm_nacl_bed
b38cadfb
NC		 20468#undef bfd_elf32_bfd_link_hash_table_create
20469#define bfd_elf32_bfd_link_hash_table_create \
20470 elf32_arm_nacl_link_hash_table_create
20471#undef elf_backend_plt_alignment
6a631e86 20472#define elf_backend_plt_alignment 4
b38cadfb
NC		 20473#undef elf_backend_modify_segment_map
20474#define elf_backend_modify_segment_map elf32_arm_nacl_modify_segment_map
6d6c25c8
AM		 20475#undef elf_backend_modify_headers
20476#define elf_backend_modify_headers nacl_modify_headers
887badb3
RM		 20477#undef elf_backend_final_write_processing
20478#define elf_backend_final_write_processing elf32_arm_nacl_final_write_processing
6a631e86
YG		 20479#undef bfd_elf32_get_synthetic_symtab
20480#undef elf_backend_plt_sym_val
20481#define elf_backend_plt_sym_val elf32_arm_nacl_plt_sym_val
5522f910 20482#undef elf_backend_copy_special_section_fields
b38cadfb 20483
887badb3
RM		 20484#undef ELF_MINPAGESIZE
20485#undef ELF_COMMONPAGESIZE
20486
b38cadfb
NC		 20487
20488#include "elf32-target.h"
20489
20490/* Reset to defaults. */
20491#undef elf_backend_plt_alignment
20492#undef elf_backend_modify_segment_map
20493#define elf_backend_modify_segment_map elf32_arm_modify_segment_map
6d6c25c8 20494#undef elf_backend_modify_headers
887badb3
RM		 20495#undef elf_backend_final_write_processing
20496#define elf_backend_final_write_processing elf32_arm_final_write_processing
20497#undef ELF_MINPAGESIZE
20498#define ELF_MINPAGESIZE 0x1000
20499#undef ELF_COMMONPAGESIZE
20500#define ELF_COMMONPAGESIZE 0x1000
20501
b38cadfb 20502
617a5ada
CL		 20503/* FDPIC Targets. */
20504
20505#undef TARGET_LITTLE_SYM
20506#define TARGET_LITTLE_SYM arm_elf32_fdpic_le_vec
20507#undef TARGET_LITTLE_NAME
20508#define TARGET_LITTLE_NAME "elf32-littlearm-fdpic"
20509#undef TARGET_BIG_SYM
20510#define TARGET_BIG_SYM arm_elf32_fdpic_be_vec
20511#undef TARGET_BIG_NAME
20512#define TARGET_BIG_NAME "elf32-bigarm-fdpic"
20513#undef elf_match_priority
20514#define elf_match_priority 128
18a20338
CL		 20515#undef ELF_OSABI
20516#define ELF_OSABI ELFOSABI_ARM_FDPIC
617a5ada
CL		 20517
20518/* Like elf32_arm_link_hash_table_create -- but overrides
20519 appropriately for FDPIC. */
20520
20521static struct bfd_link_hash_table *
20522elf32_arm_fdpic_link_hash_table_create (bfd *abfd)
20523{
20524 struct bfd_link_hash_table *ret;
20525
20526 ret = elf32_arm_link_hash_table_create (abfd);
20527 if (ret)
20528 {
20529 struct elf32_arm_link_hash_table *htab = (struct elf32_arm_link_hash_table *) ret;
20530
20531 htab->fdpic_p = 1;
20532 }
20533 return ret;
20534}
20535
e8b09b87
CL		 20536/* We need dynamic symbols for every section, since segments can
20537 relocate independently. */
20538static bfd_boolean
20539elf32_arm_fdpic_omit_section_dynsym (bfd *output_bfd ATTRIBUTE_UNUSED,
20540 struct bfd_link_info *info
20541 ATTRIBUTE_UNUSED,
20542 asection *p ATTRIBUTE_UNUSED)
20543{
20544 switch (elf_section_data (p)->this_hdr.sh_type)
20545 {
20546 case SHT_PROGBITS:
20547 case SHT_NOBITS:
20548 /* If sh_type is yet undecided, assume it could be
20549 SHT_PROGBITS/SHT_NOBITS. */
20550 case SHT_NULL:
20551 return FALSE;
20552
20553 /* There shouldn't be section relative relocations
20554 against any other section. */
20555 default:
20556 return TRUE;
20557 }
20558}
20559
617a5ada
CL		 20560#undef elf32_bed
20561#define elf32_bed elf32_arm_fdpic_bed
20562
20563#undef bfd_elf32_bfd_link_hash_table_create
4b24dd1a 20564#define bfd_elf32_bfd_link_hash_table_create elf32_arm_fdpic_link_hash_table_create
617a5ada 20565
e8b09b87
CL		 20566#undef elf_backend_omit_section_dynsym
20567#define elf_backend_omit_section_dynsym elf32_arm_fdpic_omit_section_dynsym
20568
617a5ada 20569#include "elf32-target.h"
e8b09b87 20570
617a5ada 20571#undef elf_match_priority
18a20338 20572#undef ELF_OSABI
e8b09b87 20573#undef elf_backend_omit_section_dynsym
617a5ada 20574
906e58ca 20575/* VxWorks Targets. */
4e7fd91e 20576
07d6d2b8
AM		 20577#undef TARGET_LITTLE_SYM
20578#define TARGET_LITTLE_SYM arm_elf32_vxworks_le_vec
20579#undef TARGET_LITTLE_NAME
20580#define TARGET_LITTLE_NAME "elf32-littlearm-vxworks"
20581#undef TARGET_BIG_SYM
20582#define TARGET_BIG_SYM arm_elf32_vxworks_be_vec
20583#undef TARGET_BIG_NAME
20584#define TARGET_BIG_NAME "elf32-bigarm-vxworks"
4e7fd91e
PB		 20585
20586/* Like elf32_arm_link_hash_table_create -- but overrides
20587 appropriately for VxWorks. */
906e58ca 20588
4e7fd91e
PB		 20589static struct bfd_link_hash_table *
20590elf32_arm_vxworks_link_hash_table_create (bfd *abfd)
20591{
20592 struct bfd_link_hash_table *ret;
20593
20594 ret = elf32_arm_link_hash_table_create (abfd);
20595 if (ret)
20596 {
20597 struct elf32_arm_link_hash_table *htab
00a97672 20598 = (struct elf32_arm_link_hash_table *) ret;
4e7fd91e 20599 htab->use_rel = 0;
00a97672 20600 htab->vxworks_p = 1;
4e7fd91e
PB		 20601 }
20602 return ret;
906e58ca 20603}
4e7fd91e 20604
cc364be6
AM		 20605static bfd_boolean
20606elf32_arm_vxworks_final_write_processing (bfd *abfd)
00a97672 20607{
cc364be6
AM		 20608 arm_final_write_processing (abfd);
20609 return elf_vxworks_final_write_processing (abfd);
00a97672
RS		 20610}
20611
906e58ca 20612#undef elf32_bed
4e7fd91e
PB		 20613#define elf32_bed elf32_arm_vxworks_bed
20614
906e58ca
NC		 20615#undef bfd_elf32_bfd_link_hash_table_create
20616#define bfd_elf32_bfd_link_hash_table_create elf32_arm_vxworks_link_hash_table_create
906e58ca
NC		 20617#undef elf_backend_final_write_processing
20618#define elf_backend_final_write_processing elf32_arm_vxworks_final_write_processing
20619#undef elf_backend_emit_relocs
9eaff861 20620#define elf_backend_emit_relocs elf_vxworks_emit_relocs
4e7fd91e 20621
906e58ca 20622#undef elf_backend_may_use_rel_p
00a97672 20623#define elf_backend_may_use_rel_p 0
906e58ca 20624#undef elf_backend_may_use_rela_p
00a97672 20625#define elf_backend_may_use_rela_p 1
906e58ca 20626#undef elf_backend_default_use_rela_p
00a97672 20627#define elf_backend_default_use_rela_p 1
906e58ca 20628#undef elf_backend_want_plt_sym
00a97672 20629#define elf_backend_want_plt_sym 1
906e58ca 20630#undef ELF_MAXPAGESIZE
00a97672 20631#define ELF_MAXPAGESIZE 0x1000
4e7fd91e
PB		 20632
20633#include "elf32-target.h"
20634
20635
21d799b5
NC		 20636/* Merge backend specific data from an object file to the output
20637 object file when linking. */
20638
20639static bfd_boolean
50e03d47 20640elf32_arm_merge_private_bfd_data (bfd *ibfd, struct bfd_link_info *info)
21d799b5 20641{
50e03d47 20642 bfd *obfd = info->output_bfd;
21d799b5
NC		 20643 flagword out_flags;
20644 flagword in_flags;
20645 bfd_boolean flags_compatible = TRUE;
20646 asection *sec;
20647
cc643b88 20648 /* Check if we have the same endianness. */
50e03d47 20649 if (! _bfd_generic_verify_endian_match (ibfd, info))
21d799b5
NC		 20650 return FALSE;
20651
20652 if (! is_arm_elf (ibfd) || ! is_arm_elf (obfd))
20653 return TRUE;
20654
50e03d47 20655 if (!elf32_arm_merge_eabi_attributes (ibfd, info))
21d799b5
NC		 20656 return FALSE;
20657
20658 /* The input BFD must have had its flags initialised. */
20659 /* The following seems bogus to me -- The flags are initialized in
20660 the assembler but I don't think an elf_flags_init field is
20661 written into the object. */
20662 /* BFD_ASSERT (elf_flags_init (ibfd)); */
20663
20664 in_flags = elf_elfheader (ibfd)->e_flags;
20665 out_flags = elf_elfheader (obfd)->e_flags;
20666
20667 /* In theory there is no reason why we couldn't handle this. However
20668 in practice it isn't even close to working and there is no real
20669 reason to want it. */
20670 if (EF_ARM_EABI_VERSION (in_flags) >= EF_ARM_EABI_VER4
20671 && !(ibfd->flags & DYNAMIC)
20672 && (in_flags & EF_ARM_BE8))
20673 {
871b3ab2 20674 _bfd_error_handler (_("error: %pB is already in final BE8 format"),
21d799b5
NC		 20675 ibfd);
20676 return FALSE;
20677 }
20678
20679 if (!elf_flags_init (obfd))
20680 {
20681 /* If the input is the default architecture and had the default
20682 flags then do not bother setting the flags for the output
20683 architecture, instead allow future merges to do this. If no
20684 future merges ever set these flags then they will retain their
99059e56
RM		 20685 uninitialised values, which surprise surprise, correspond
20686 to the default values. */
21d799b5
NC		 20687 if (bfd_get_arch_info (ibfd)->the_default
20688 && elf_elfheader (ibfd)->e_flags == 0)
20689 return TRUE;
20690
20691 elf_flags_init (obfd) = TRUE;
20692 elf_elfheader (obfd)->e_flags = in_flags;
20693
20694 if (bfd_get_arch (obfd) == bfd_get_arch (ibfd)
20695 && bfd_get_arch_info (obfd)->the_default)
20696 return bfd_set_arch_mach (obfd, bfd_get_arch (ibfd), bfd_get_mach (ibfd));
20697
20698 return TRUE;
20699 }
20700
20701 /* Determine what should happen if the input ARM architecture
20702 does not match the output ARM architecture. */
20703 if (! bfd_arm_merge_machines (ibfd, obfd))
20704 return FALSE;
20705
20706 /* Identical flags must be compatible. */
20707 if (in_flags == out_flags)
20708 return TRUE;
20709
20710 /* Check to see if the input BFD actually contains any sections. If
20711 not, its flags may not have been initialised either, but it
20712 cannot actually cause any incompatiblity. Do not short-circuit
20713 dynamic objects; their section list may be emptied by
20714 elf_link_add_object_symbols.
20715
20716 Also check to see if there are no code sections in the input.
20717 In this case there is no need to check for code specific flags.
20718 XXX - do we need to worry about floating-point format compatability
20719 in data sections ? */
20720 if (!(ibfd->flags & DYNAMIC))
20721 {
20722 bfd_boolean null_input_bfd = TRUE;
20723 bfd_boolean only_data_sections = TRUE;
20724
20725 for (sec = ibfd->sections; sec != NULL; sec = sec->next)
20726 {
20727 /* Ignore synthetic glue sections. */
20728 if (strcmp (sec->name, ".glue_7")
20729 && strcmp (sec->name, ".glue_7t"))
20730 {
fd361982 20731 if ((bfd_section_flags (sec)
21d799b5
NC		 20732 & (SEC_LOAD | SEC_CODE | SEC_HAS_CONTENTS))
20733 == (SEC_LOAD | SEC_CODE | SEC_HAS_CONTENTS))
99059e56 20734 only_data_sections = FALSE;
21d799b5
NC		 20735
20736 null_input_bfd = FALSE;
20737 break;
20738 }
20739 }
20740
20741 if (null_input_bfd || only_data_sections)
20742 return TRUE;
20743 }
20744
20745 /* Complain about various flag mismatches. */
20746 if (!elf32_arm_versions_compatible (EF_ARM_EABI_VERSION (in_flags),
20747 EF_ARM_EABI_VERSION (out_flags)))
20748 {
20749 _bfd_error_handler
90b6238f 20750 (_("error: source object %pB has EABI version %d, but target %pB has EABI version %d"),
c08bb8dd
AM		 20751 ibfd, (in_flags & EF_ARM_EABIMASK) >> 24,
20752 obfd, (out_flags & EF_ARM_EABIMASK) >> 24);
21d799b5
NC		 20753 return FALSE;
20754 }
20755
20756 /* Not sure what needs to be checked for EABI versions >= 1. */
20757 /* VxWorks libraries do not use these flags. */
20758 if (get_elf_backend_data (obfd) != &elf32_arm_vxworks_bed
20759 && get_elf_backend_data (ibfd) != &elf32_arm_vxworks_bed
20760 && EF_ARM_EABI_VERSION (in_flags) == EF_ARM_EABI_UNKNOWN)
20761 {
20762 if ((in_flags & EF_ARM_APCS_26) != (out_flags & EF_ARM_APCS_26))
20763 {
20764 _bfd_error_handler
871b3ab2 20765 (_("error: %pB is compiled for APCS-%d, whereas target %pB uses APCS-%d"),
c08bb8dd
AM		 20766 ibfd, in_flags & EF_ARM_APCS_26 ? 26 : 32,
20767 obfd, out_flags & EF_ARM_APCS_26 ? 26 : 32);
21d799b5
NC		 20768 flags_compatible = FALSE;
20769 }
20770
20771 if ((in_flags & EF_ARM_APCS_FLOAT) != (out_flags & EF_ARM_APCS_FLOAT))
20772 {
20773 if (in_flags & EF_ARM_APCS_FLOAT)
20774 _bfd_error_handler
871b3ab2 20775 (_("error: %pB passes floats in float registers, whereas %pB passes them in integer registers"),
21d799b5
NC		 20776 ibfd, obfd);
20777 else
20778 _bfd_error_handler
871b3ab2 20779 (_("error: %pB passes floats in integer registers, whereas %pB passes them in float registers"),
21d799b5
NC		 20780 ibfd, obfd);
20781
20782 flags_compatible = FALSE;
20783 }
20784
20785 if ((in_flags & EF_ARM_VFP_FLOAT) != (out_flags & EF_ARM_VFP_FLOAT))
20786 {
20787 if (in_flags & EF_ARM_VFP_FLOAT)
20788 _bfd_error_handler
90b6238f
AM		 20789 (_("error: %pB uses %s instructions, whereas %pB does not"),
20790 ibfd, "VFP", obfd);
21d799b5
NC		 20791 else
20792 _bfd_error_handler
90b6238f
AM		 20793 (_("error: %pB uses %s instructions, whereas %pB does not"),
20794 ibfd, "FPA", obfd);
21d799b5
NC		 20795
20796 flags_compatible = FALSE;
20797 }
20798
20799 if ((in_flags & EF_ARM_MAVERICK_FLOAT) != (out_flags & EF_ARM_MAVERICK_FLOAT))
20800 {
20801 if (in_flags & EF_ARM_MAVERICK_FLOAT)
20802 _bfd_error_handler
90b6238f
AM		 20803 (_("error: %pB uses %s instructions, whereas %pB does not"),
20804 ibfd, "Maverick", obfd);
21d799b5
NC		 20805 else
20806 _bfd_error_handler
90b6238f
AM		 20807 (_("error: %pB does not use %s instructions, whereas %pB does"),
20808 ibfd, "Maverick", obfd);
21d799b5
NC		 20809
20810 flags_compatible = FALSE;
20811 }
20812
20813#ifdef EF_ARM_SOFT_FLOAT
20814 if ((in_flags & EF_ARM_SOFT_FLOAT) != (out_flags & EF_ARM_SOFT_FLOAT))
20815 {
20816 /* We can allow interworking between code that is VFP format
20817 layout, and uses either soft float or integer regs for
20818 passing floating point arguments and results. We already
20819 know that the APCS_FLOAT flags match; similarly for VFP
20820 flags. */
20821 if ((in_flags & EF_ARM_APCS_FLOAT) != 0
20822 || (in_flags & EF_ARM_VFP_FLOAT) == 0)
20823 {
20824 if (in_flags & EF_ARM_SOFT_FLOAT)
20825 _bfd_error_handler
871b3ab2 20826 (_("error: %pB uses software FP, whereas %pB uses hardware FP"),
21d799b5
NC		 20827 ibfd, obfd);
20828 else
20829 _bfd_error_handler
871b3ab2 20830 (_("error: %pB uses hardware FP, whereas %pB uses software FP"),
21d799b5
NC		 20831 ibfd, obfd);
20832
20833 flags_compatible = FALSE;
20834 }
20835 }
20836#endif
20837
20838 /* Interworking mismatch is only a warning. */
20839 if ((in_flags & EF_ARM_INTERWORK) != (out_flags & EF_ARM_INTERWORK))
20840 {
20841 if (in_flags & EF_ARM_INTERWORK)
20842 {
20843 _bfd_error_handler
90b6238f 20844 (_("warning: %pB supports interworking, whereas %pB does not"),
21d799b5
NC		 20845 ibfd, obfd);
20846 }
20847 else
20848 {
20849 _bfd_error_handler
90b6238f 20850 (_("warning: %pB does not support interworking, whereas %pB does"),
21d799b5
NC		 20851 ibfd, obfd);
20852 }
20853 }
20854 }
20855
20856 return flags_compatible;
20857}
20858
20859
906e58ca 20860/* Symbian OS Targets. */
7f266840 20861
07d6d2b8
AM		 20862#undef TARGET_LITTLE_SYM
20863#define TARGET_LITTLE_SYM arm_elf32_symbian_le_vec
20864#undef TARGET_LITTLE_NAME
20865#define TARGET_LITTLE_NAME "elf32-littlearm-symbian"
20866#undef TARGET_BIG_SYM
20867#define TARGET_BIG_SYM arm_elf32_symbian_be_vec
20868#undef TARGET_BIG_NAME
20869#define TARGET_BIG_NAME "elf32-bigarm-symbian"
7f266840
DJ		 20870
20871/* Like elf32_arm_link_hash_table_create -- but overrides
20872 appropriately for Symbian OS. */
906e58ca 20873
7f266840
DJ		 20874static struct bfd_link_hash_table *
20875elf32_arm_symbian_link_hash_table_create (bfd *abfd)
20876{
20877 struct bfd_link_hash_table *ret;
20878
20879 ret = elf32_arm_link_hash_table_create (abfd);
20880 if (ret)
20881 {
20882 struct elf32_arm_link_hash_table *htab
20883 = (struct elf32_arm_link_hash_table *)ret;
20884 /* There is no PLT header for Symbian OS. */
20885 htab->plt_header_size = 0;
95720a86
DJ		 20886 /* The PLT entries are each one instruction and one word. */
20887 htab->plt_entry_size = 4 * ARRAY_SIZE (elf32_arm_symbian_plt_entry);
7f266840 20888 htab->symbian_p = 1;
33bfe774
JB		 20889 /* Symbian uses armv5t or above, so use_blx is always true. */
20890 htab->use_blx = 1;
67687978 20891 htab->root.is_relocatable_executable = 1;
7f266840
DJ		 20892 }
20893 return ret;
906e58ca 20894}
7f266840 20895
b35d266b 20896static const struct bfd_elf_special_section
551b43fd 20897elf32_arm_symbian_special_sections[] =
7f266840 20898{
5cd3778d
MM		 20899 /* In a BPABI executable, the dynamic linking sections do not go in
20900 the loadable read-only segment. The post-linker may wish to
20901 refer to these sections, but they are not part of the final
20902 program image. */
07d6d2b8
AM		 20903 { STRING_COMMA_LEN (".dynamic"), 0, SHT_DYNAMIC, 0 },
20904 { STRING_COMMA_LEN (".dynstr"), 0, SHT_STRTAB, 0 },
20905 { STRING_COMMA_LEN (".dynsym"), 0, SHT_DYNSYM, 0 },
20906 { STRING_COMMA_LEN (".got"), 0, SHT_PROGBITS, 0 },
20907 { STRING_COMMA_LEN (".hash"), 0, SHT_HASH, 0 },
5cd3778d
MM		 20908 /* These sections do not need to be writable as the SymbianOS
20909 postlinker will arrange things so that no dynamic relocation is
20910 required. */
07d6d2b8
AM		 20911 { STRING_COMMA_LEN (".init_array"), 0, SHT_INIT_ARRAY, SHF_ALLOC },
20912 { STRING_COMMA_LEN (".fini_array"), 0, SHT_FINI_ARRAY, SHF_ALLOC },
0112cd26 20913 { STRING_COMMA_LEN (".preinit_array"), 0, SHT_PREINIT_ARRAY, SHF_ALLOC },
07d6d2b8 20914 { NULL, 0, 0, 0, 0 }
7f266840
DJ		 20915};
20916
c3c76620 20917static void
906e58ca 20918elf32_arm_symbian_begin_write_processing (bfd *abfd,
a4fd1a8e 20919 struct bfd_link_info *link_info)
c3c76620
MM		 20920{
20921 /* BPABI objects are never loaded directly by an OS kernel; they are
20922 processed by a postlinker first, into an OS-specific format. If
20923 the D_PAGED bit is set on the file, BFD will align segments on
20924 page boundaries, so that an OS can directly map the file. With
20925 BPABI objects, that just results in wasted space. In addition,
20926 because we clear the D_PAGED bit, map_sections_to_segments will
20927 recognize that the program headers should not be mapped into any
20928 loadable segment. */
20929 abfd->flags &= ~D_PAGED;
906e58ca 20930 elf32_arm_begin_write_processing (abfd, link_info);
c3c76620 20931}
7f266840
DJ		 20932
20933static bfd_boolean
906e58ca 20934elf32_arm_symbian_modify_segment_map (bfd *abfd,
b294bdf8 20935 struct bfd_link_info *info)
7f266840
DJ		 20936{
20937 struct elf_segment_map *m;
20938 asection *dynsec;
20939
7f266840
DJ		 20940 /* BPABI shared libraries and executables should have a PT_DYNAMIC
20941 segment. However, because the .dynamic section is not marked
20942 with SEC_LOAD, the generic ELF code will not create such a
20943 segment. */
20944 dynsec = bfd_get_section_by_name (abfd, ".dynamic");
20945 if (dynsec)
20946 {
12bd6957 20947 for (m = elf_seg_map (abfd); m != NULL; m = m->next)
8ded5a0f
AM		 20948 if (m->p_type == PT_DYNAMIC)
20949 break;
20950
20951 if (m == NULL)
20952 {
20953 m = _bfd_elf_make_dynamic_segment (abfd, dynsec);
12bd6957
AM		 20954 m->next = elf_seg_map (abfd);
20955 elf_seg_map (abfd) = m;
8ded5a0f 20956 }
7f266840
DJ		 20957 }
20958
b294bdf8
MM		 20959 /* Also call the generic arm routine. */
20960 return elf32_arm_modify_segment_map (abfd, info);
7f266840
DJ		 20961}
20962
95720a86
DJ		 20963/* Return address for Ith PLT stub in section PLT, for relocation REL
20964 or (bfd_vma) -1 if it should not be included. */
20965
20966static bfd_vma
20967elf32_arm_symbian_plt_sym_val (bfd_vma i, const asection *plt,
20968 const arelent *rel ATTRIBUTE_UNUSED)
20969{
20970 return plt->vma + 4 * ARRAY_SIZE (elf32_arm_symbian_plt_entry) * i;
20971}
20972
8029a119 20973#undef elf32_bed
7f266840
DJ		 20974#define elf32_bed elf32_arm_symbian_bed
20975
20976/* The dynamic sections are not allocated on SymbianOS; the postlinker
20977 will process them and then discard them. */
906e58ca 20978#undef ELF_DYNAMIC_SEC_FLAGS
7f266840
DJ		 20979#define ELF_DYNAMIC_SEC_FLAGS \
20980 (SEC_HAS_CONTENTS | SEC_IN_MEMORY | SEC_LINKER_CREATED)
20981
9eaff861 20982#undef elf_backend_emit_relocs
c3c76620 20983
906e58ca
NC		 20984#undef bfd_elf32_bfd_link_hash_table_create
20985#define bfd_elf32_bfd_link_hash_table_create elf32_arm_symbian_link_hash_table_create
20986#undef elf_backend_special_sections
07d6d2b8 20987#define elf_backend_special_sections elf32_arm_symbian_special_sections
906e58ca
NC		 20988#undef elf_backend_begin_write_processing
20989#define elf_backend_begin_write_processing elf32_arm_symbian_begin_write_processing
20990#undef elf_backend_final_write_processing
20991#define elf_backend_final_write_processing elf32_arm_final_write_processing
20992
20993#undef elf_backend_modify_segment_map
7f266840
DJ		 20994#define elf_backend_modify_segment_map elf32_arm_symbian_modify_segment_map
20995
20996/* There is no .got section for BPABI objects, and hence no header. */
906e58ca 20997#undef elf_backend_got_header_size
7f266840
DJ		 20998#define elf_backend_got_header_size 0
20999
21000/* Similarly, there is no .got.plt section. */
906e58ca 21001#undef elf_backend_want_got_plt
7f266840
DJ		 21002#define elf_backend_want_got_plt 0
21003
906e58ca 21004#undef elf_backend_plt_sym_val
95720a86
DJ		 21005#define elf_backend_plt_sym_val elf32_arm_symbian_plt_sym_val
21006
906e58ca 21007#undef elf_backend_may_use_rel_p
00a97672 21008#define elf_backend_may_use_rel_p 1
906e58ca 21009#undef elf_backend_may_use_rela_p
00a97672 21010#define elf_backend_may_use_rela_p 0
906e58ca 21011#undef elf_backend_default_use_rela_p
00a97672 21012#define elf_backend_default_use_rela_p 0
906e58ca 21013#undef elf_backend_want_plt_sym
00a97672 21014#define elf_backend_want_plt_sym 0
64f52338
AM		 21015#undef elf_backend_dtrel_excludes_plt
21016#define elf_backend_dtrel_excludes_plt 0
906e58ca 21017#undef ELF_MAXPAGESIZE
00a97672 21018#define ELF_MAXPAGESIZE 0x8000
4e7fd91e 21019
7f266840 21020#include "elf32-target.h"
GDB Binutils - Deliverables
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