Switch the inferior before outputting its id in "info inferiors"

[deliverable/binutils-gdb.git] / cpu / or1k.cpu

; OpenRISC 1000 architecture.  -*- Scheme -*-
; Copyright 2000-2019 Free Software Foundation, Inc.
; Contributed for OR32 by Johan Rydberg, jrydberg@opencores.org
; Modified by Julius Baxter, juliusbaxter@gmail.com
; Modified by Peter Gavin, pgavin@gmail.com
; Modified by Andrey Bacherov, avbacherov@opencores.org
;
; This program is free software; you can redistribute it and/or modify
; it under the terms of the GNU General Public License as published by
; the Free Software Foundation; either version 3 of the License, or
; (at your option) any later version.
;
; This program is distributed in the hope that it will be useful,
; but WITHOUT ANY WARRANTY; without even the implied warranty of
; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
; GNU General Public License for more details.
;
; You should have received a copy of the GNU General Public License
; along with this program; if not, see <http://www.gnu.org/licenses/>

(include "simplify.inc")

; The OpenRISC family is a set of RISC microprocessor architectures with an
; emphasis on scalability and is targetted at embedded use.
; The CPU RTL development is a collaborative open source effort.
; http://opencores.org/or1k
; http://openrisc.net

(define-arch
  (name or1k)
  (comment "OpenRISC 1000")
  (default-alignment aligned)
  (insn-lsb0? #t)
  (machs or32 or32nd or64 or64nd)
  (isas openrisc)
)

; Instruction set parameters.
(define-isa
  ; Name of the ISA.
  (name openrisc)
  ; Base insturction length.  The insns are always 32 bits wide.
  (base-insn-bitsize 32)
  )

(define-pmacro OR32-MACHS       or32,or32nd)
(define-pmacro OR64-MACHS       or64,or64nd)
(define-pmacro ORBIS-MACHS      or32,or32nd,or64,or64nd)
(define-pmacro ORFPX32-MACHS    or32,or32nd,or64,or64nd)
(define-pmacro ORFPX64-MACHS    or64,or64nd)
(define-pmacro ORFPX64A32-MACHS or32,or32nd) ; float64 for 32-bit machs

(define-attr
  (for model)
  (type boolean)
  (name NO-DELAY-SLOT)
  (comment "does not have delay slots")
  )

(if (keep-mach? (or32 or32nd))
    (begin
      (define-cpu
        (name or1k32bf)
        (comment "OpenRISC 1000 32-bit CPU family")
        (insn-endian big)
        (data-endian big)
        (word-bitsize 32)
        (file-transform "")
        )

      (define-mach
        (name or32)
        (comment "Generic OpenRISC 1000 32-bit CPU")
        (cpu or1k32bf)
        (bfd-name "or1k")
        )

      (define-mach
        (name or32nd)
        (comment "Generic OpenRISC 1000 32-bit CPU with no branch delay slot")
        (cpu or1k32bf)
        (bfd-name "or1knd")
        )

      ; OpenRISC 1200 - 32-bit or1k CPU implementation
      (define-model
        (name or1200) (comment "OpenRISC 1200 model")
        (attrs)
        (mach or32)
        (unit u-exec "Execution Unit" () 1 1 () () () ())
        )

      ; OpenRISC 1200 - 32-bit or1k CPU implementation
      (define-model
        (name or1200nd) (comment "OpenRISC 1200 model with no branch delay slot")
        (attrs NO-DELAY-SLOT)
        (mach or32nd)
        (unit u-exec "Execution Unit" () 1 1 () () () ())
        )
      )
    )

(if (keep-mach? (or64 or64nd))
    (begin
      (define-cpu
        (name or1k64bf)
        (comment "OpenRISC 1000 64-bit CPU family")
        (insn-endian big)
        (data-endian big)
        (word-bitsize 64)
        (file-transform "64")
        )

      (define-mach
        (name or64)
        (comment "Generic OpenRISC 1000 64-bit CPU")
        (cpu or1k64bf)
        (bfd-name "or1k64")
        )

      (define-mach
        (name or64nd)
        (comment "Generic OpenRISC 1000 ND 64-bit CPU with no branch delay slot")
        (cpu or1k64bf)
        (bfd-name "or1k64nd")
        )
      )
    )

(include "or1kcommon.cpu")
(include "or1korbis.cpu")
(include "or1korfpx.cpu")