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[ARC] Improve parsing instruction operands.
[deliverable/binutils-gdb.git] / gas / config / tc-arc.c
CommitLineData
252b5132 1/* tc-arc.c -- Assembler for the ARC
b3adc24a 2 Copyright (C) 1994-2020 Free Software Foundation, Inc.
886a2506
NC		 3
4 Contributor: Claudiu Zissulescu <claziss@synopsys.com>
252b5132
RH		 5
6 This file is part of GAS, the GNU Assembler.
7
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
ec2655a6 10 the Free Software Foundation; either version 3, or (at your option)
252b5132
RH		 11 any later version.
12
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19203624 19 along with GAS; see the file COPYING. If not, write to the Free
4b4da160
NC		 20 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
21 02110-1301, USA. */
252b5132 22
252b5132 23#include "as.h"
886a2506 24#include "subsegs.h"
886a2506 25#include "dwarf2dbg.h"
726c18e1 26#include "dw2gencfi.h"
3882b010 27#include "safe-ctype.h"
886a2506 28
252b5132 29#include "opcode/arc.h"
53a346d8 30#include "opcode/arc-attrs.h"
252b5132 31#include "elf/arc.h"
b99747ae 32#include "../opcodes/arc-ext.h"
252b5132 33
886a2506 34/* Defines section. */
0d2bcfaf 35
886a2506
NC		 36#define MAX_INSN_FIXUPS 2
37#define MAX_CONSTR_STR 20
4670103e 38#define FRAG_MAX_GROWTH 8
0d2bcfaf 39
886a2506
NC		 40#ifdef DEBUG
41# define pr_debug(fmt, args...) fprintf (stderr, fmt, ##args)
42#else
43# define pr_debug(fmt, args...)
44#endif
45
46#define MAJOR_OPCODE(x) (((x) & 0xF8000000) >> 27)
47#define SUB_OPCODE(x) (((x) & 0x003F0000) >> 16)
db18dbab
GM		 48#define LP_INSN(x) ((MAJOR_OPCODE (x) == 0x4) \
49 && (SUB_OPCODE (x) == 0x28))
886a2506 50
9004b6bd
AB		 51#ifndef TARGET_WITH_CPU
52#define TARGET_WITH_CPU "arc700"
53#endif /* TARGET_WITH_CPU */
54
53a346d8
CZ		 55#define ARC_GET_FLAG(s) (*symbol_get_tc (s))
56#define ARC_SET_FLAG(s,v) (*symbol_get_tc (s) |= (v))
57#define streq(a, b) (strcmp (a, b) == 0)
58
4670103e
CZ		 59/* Enum used to enumerate the relaxable ins operands. */
60enum rlx_operand_type
61{
62 EMPTY = 0,
63 REGISTER,
64 REGISTER_S, /* Register for short instruction(s). */
65 REGISTER_NO_GP, /* Is a register but not gp register specifically. */
66 REGISTER_DUP, /* Duplication of previous operand of type register. */
67 IMMEDIATE,
68 BRACKET
69};
70
71enum arc_rlx_types
72{
73 ARC_RLX_NONE = 0,
74 ARC_RLX_BL_S,
75 ARC_RLX_BL,
76 ARC_RLX_B_S,
77 ARC_RLX_B,
78 ARC_RLX_ADD_U3,
79 ARC_RLX_ADD_U6,
80 ARC_RLX_ADD_LIMM,
81 ARC_RLX_LD_U7,
82 ARC_RLX_LD_S9,
83 ARC_RLX_LD_LIMM,
84 ARC_RLX_MOV_U8,
85 ARC_RLX_MOV_S12,
86 ARC_RLX_MOV_LIMM,
87 ARC_RLX_SUB_U3,
88 ARC_RLX_SUB_U6,
89 ARC_RLX_SUB_LIMM,
90 ARC_RLX_MPY_U6,
91 ARC_RLX_MPY_LIMM,
92 ARC_RLX_MOV_RU6,
93 ARC_RLX_MOV_RLIMM,
94 ARC_RLX_ADD_RRU6,
95 ARC_RLX_ADD_RRLIMM,
96};
97
886a2506
NC		 98/* Macros section. */
99
100#define regno(x) ((x) & 0x3F)
101#define is_ir_num(x) (((x) & ~0x3F) == 0)
8ddf6b2a
CZ		 102#define is_code_density_p(sc) (((sc) == CD1 || (sc) == CD2))
103#define is_spfp_p(op) (((sc) == SPX))
104#define is_dpfp_p(op) (((sc) == DPX))
105#define is_fpuda_p(op) (((sc) == DPA))
cf9bdae9 106#define is_br_jmp_insn_p(op) (((op)->insn_class == BRANCH \
107 || (op)->insn_class == JUMP \
108 || (op)->insn_class == BRCC \
109 || (op)->insn_class == BBIT0 \
110 || (op)->insn_class == BBIT1 \
111 || (op)->insn_class == BI \
112 || (op)->insn_class == EI \
113 || (op)->insn_class == ENTER \
114 || (op)->insn_class == JLI \
115 || (op)->insn_class == LOOP \
116 || (op)->insn_class == LEAVE \
117 ))
c810e0b8 118#define is_kernel_insn_p(op) (((op)->insn_class == KERNEL))
bdd582db 119#define is_nps400_p(op) (((sc) == NPS400))
0d2bcfaf 120
886a2506
NC		 121/* Generic assembler global variables which must be defined by all
122 targets. */
0d2bcfaf 123
886a2506 124/* Characters which always start a comment. */
252b5132
RH		 125const char comment_chars[] = "#;";
126
886a2506 127/* Characters which start a comment at the beginning of a line. */
252b5132
RH		 128const char line_comment_chars[] = "#";
129
886a2506
NC		 130/* Characters which may be used to separate multiple commands on a
131 single line. */
132const char line_separator_chars[] = "`";
252b5132 133
886a2506
NC		 134/* Characters which are used to indicate an exponent in a floating
135 point number. */
252b5132
RH		 136const char EXP_CHARS[] = "eE";
137
bcee8eb8
AM		 138/* Chars that mean this number is a floating point constant
139 As in 0f12.456 or 0d1.2345e12. */
252b5132
RH		 140const char FLT_CHARS[] = "rRsSfFdD";
141
142/* Byte order. */
143extern int target_big_endian;
144const char *arc_target_format = DEFAULT_TARGET_FORMAT;
145static int byte_order = DEFAULT_BYTE_ORDER;
146
b99747ae
CZ		 147/* Arc extension section. */
148static segT arcext_section;
149
4670103e
CZ		 150/* By default relaxation is disabled. */
151static int relaxation_state = 0;
152
886a2506 153extern int arc_get_mach (char *);
0d2bcfaf 154
4670103e 155/* Forward declarations. */
886a2506
NC		 156static void arc_lcomm (int);
157static void arc_option (int);
158static void arc_extra_reloc (int);
b99747ae 159static void arc_extinsn (int);
f36e33da 160static void arc_extcorereg (int);
53a346d8 161static void arc_attribute (int);
4670103e 162
886a2506 163const pseudo_typeS md_pseudo_table[] =
6f4b1afc
CM		 164{
165 /* Make sure that .word is 32 bits. */
166 { "word", cons, 4 },
886a2506 167
6f4b1afc
CM		 168 { "align", s_align_bytes, 0 }, /* Defaulting is invalid (0). */
169 { "lcomm", arc_lcomm, 0 },
170 { "lcommon", arc_lcomm, 0 },
171 { "cpu", arc_option, 0 },
252b5132 172
53a346d8 173 { "arc_attribute", arc_attribute, 0 },
f36e33da
CZ		 174 { "extinstruction", arc_extinsn, 0 },
175 { "extcoreregister", arc_extcorereg, EXT_CORE_REGISTER },
176 { "extauxregister", arc_extcorereg, EXT_AUX_REGISTER },
177 { "extcondcode", arc_extcorereg, EXT_COND_CODE },
b99747ae 178
6f4b1afc
CM		 179 { "tls_gd_ld", arc_extra_reloc, BFD_RELOC_ARC_TLS_GD_LD },
180 { "tls_gd_call", arc_extra_reloc, BFD_RELOC_ARC_TLS_GD_CALL },
886a2506 181
6f4b1afc
CM		 182 { NULL, NULL, 0 }
183};
252b5132 184
252b5132 185const char *md_shortopts = "";
ea1562b3
NC		 186
187enum options
6f4b1afc
CM		 188{
189 OPTION_EB = OPTION_MD_BASE,
190 OPTION_EL,
191
192 OPTION_ARC600,
193 OPTION_ARC601,
194 OPTION_ARC700,
195 OPTION_ARCEM,
196 OPTION_ARCHS,
197
198 OPTION_MCPU,
199 OPTION_CD,
4670103e 200 OPTION_RELAX,
bdd582db 201 OPTION_NPS400,
6f4b1afc 202
ce440d63
GM		 203 OPTION_SPFP,
204 OPTION_DPFP,
205 OPTION_FPUDA,
206
6f4b1afc
CM		 207 /* The following options are deprecated and provided here only for
208 compatibility reasons. */
209 OPTION_USER_MODE,
210 OPTION_LD_EXT_MASK,
211 OPTION_SWAP,
212 OPTION_NORM,
213 OPTION_BARREL_SHIFT,
214 OPTION_MIN_MAX,
215 OPTION_NO_MPY,
216 OPTION_EA,
217 OPTION_MUL64,
218 OPTION_SIMD,
6f4b1afc
CM		 219 OPTION_XMAC_D16,
220 OPTION_XMAC_24,
221 OPTION_DSP_PACKA,
222 OPTION_CRC,
223 OPTION_DVBF,
224 OPTION_TELEPHONY,
225 OPTION_XYMEMORY,
226 OPTION_LOCK,
227 OPTION_SWAPE,
ce440d63 228 OPTION_RTSC
6f4b1afc 229};
ea1562b3
NC		 230
231struct option md_longopts[] =
6f4b1afc
CM		 232{
233 { "EB", no_argument, NULL, OPTION_EB },
234 { "EL", no_argument, NULL, OPTION_EL },
235 { "mcpu", required_argument, NULL, OPTION_MCPU },
236 { "mA6", no_argument, NULL, OPTION_ARC600 },
24b368f8
CZ		 237 { "mARC600", no_argument, NULL, OPTION_ARC600 },
238 { "mARC601", no_argument, NULL, OPTION_ARC601 },
239 { "mARC700", no_argument, NULL, OPTION_ARC700 },
6f4b1afc
CM		 240 { "mA7", no_argument, NULL, OPTION_ARC700 },
241 { "mEM", no_argument, NULL, OPTION_ARCEM },
242 { "mHS", no_argument, NULL, OPTION_ARCHS },
243 { "mcode-density", no_argument, NULL, OPTION_CD },
4670103e 244 { "mrelax", no_argument, NULL, OPTION_RELAX },
bdd582db 245 { "mnps400", no_argument, NULL, OPTION_NPS400 },
6f4b1afc 246
ce440d63
GM		 247 /* Floating point options */
248 { "mspfp", no_argument, NULL, OPTION_SPFP},
249 { "mspfp-compact", no_argument, NULL, OPTION_SPFP},
250 { "mspfp_compact", no_argument, NULL, OPTION_SPFP},
251 { "mspfp-fast", no_argument, NULL, OPTION_SPFP},
252 { "mspfp_fast", no_argument, NULL, OPTION_SPFP},
253 { "mdpfp", no_argument, NULL, OPTION_DPFP},
254 { "mdpfp-compact", no_argument, NULL, OPTION_DPFP},
255 { "mdpfp_compact", no_argument, NULL, OPTION_DPFP},
256 { "mdpfp-fast", no_argument, NULL, OPTION_DPFP},
257 { "mdpfp_fast", no_argument, NULL, OPTION_DPFP},
258 { "mfpuda", no_argument, NULL, OPTION_FPUDA},
259
6f4b1afc
CM		 260 /* The following options are deprecated and provided here only for
261 compatibility reasons. */
262 { "mav2em", no_argument, NULL, OPTION_ARCEM },
263 { "mav2hs", no_argument, NULL, OPTION_ARCHS },
264 { "muser-mode-only", no_argument, NULL, OPTION_USER_MODE },
265 { "mld-extension-reg-mask", required_argument, NULL, OPTION_LD_EXT_MASK },
266 { "mswap", no_argument, NULL, OPTION_SWAP },
267 { "mnorm", no_argument, NULL, OPTION_NORM },
268 { "mbarrel-shifter", no_argument, NULL, OPTION_BARREL_SHIFT },
269 { "mbarrel_shifter", no_argument, NULL, OPTION_BARREL_SHIFT },
270 { "mmin-max", no_argument, NULL, OPTION_MIN_MAX },
271 { "mmin_max", no_argument, NULL, OPTION_MIN_MAX },
272 { "mno-mpy", no_argument, NULL, OPTION_NO_MPY },
273 { "mea", no_argument, NULL, OPTION_EA },
274 { "mEA", no_argument, NULL, OPTION_EA },
275 { "mmul64", no_argument, NULL, OPTION_MUL64 },
276 { "msimd", no_argument, NULL, OPTION_SIMD},
6f4b1afc
CM		 277 { "mmac-d16", no_argument, NULL, OPTION_XMAC_D16},
278 { "mmac_d16", no_argument, NULL, OPTION_XMAC_D16},
279 { "mmac-24", no_argument, NULL, OPTION_XMAC_24},
280 { "mmac_24", no_argument, NULL, OPTION_XMAC_24},
281 { "mdsp-packa", no_argument, NULL, OPTION_DSP_PACKA},
282 { "mdsp_packa", no_argument, NULL, OPTION_DSP_PACKA},
283 { "mcrc", no_argument, NULL, OPTION_CRC},
284 { "mdvbf", no_argument, NULL, OPTION_DVBF},
285 { "mtelephony", no_argument, NULL, OPTION_TELEPHONY},
286 { "mxy", no_argument, NULL, OPTION_XYMEMORY},
287 { "mlock", no_argument, NULL, OPTION_LOCK},
288 { "mswape", no_argument, NULL, OPTION_SWAPE},
289 { "mrtsc", no_argument, NULL, OPTION_RTSC},
6f4b1afc
CM		 290
291 { NULL, no_argument, NULL, 0 }
292};
252b5132 293
886a2506 294size_t md_longopts_size = sizeof (md_longopts);
0d2bcfaf 295
886a2506 296/* Local data and data types. */
252b5132 297
886a2506
NC		 298/* Used since new relocation types are introduced in this
299 file (DUMMY_RELOC_LITUSE_*). */
300typedef int extended_bfd_reloc_code_real_type;
252b5132 301
886a2506 302struct arc_fixup
252b5132 303{
886a2506 304 expressionS exp;
252b5132 305
886a2506 306 extended_bfd_reloc_code_real_type reloc;
252b5132 307
886a2506
NC		 308 /* index into arc_operands. */
309 unsigned int opindex;
252b5132 310
886a2506
NC		 311 /* PC-relative, used by internals fixups. */
312 unsigned char pcrel;
252b5132 313
886a2506
NC		 314 /* TRUE if this fixup is for LIMM operand. */
315 bfd_boolean islong;
316};
252b5132 317
886a2506
NC		 318struct arc_insn
319{
bdfe53e3 320 unsigned long long int insn;
886a2506
NC		 321 int nfixups;
322 struct arc_fixup fixups[MAX_INSN_FIXUPS];
323 long limm;
91fdca6f 324 unsigned int len; /* Length of instruction in bytes. */
886a2506
NC		 325 bfd_boolean has_limm; /* Boolean value: TRUE if limm field is
326 valid. */
4670103e
CZ		 327 bfd_boolean relax; /* Boolean value: TRUE if needs
328 relaxation. */
886a2506 329};
ea1562b3 330
886a2506
NC		 331/* Structure to hold any last two instructions. */
332static struct arc_last_insn
252b5132 333{
886a2506
NC		 334 /* Saved instruction opcode. */
335 const struct arc_opcode *opcode;
252b5132 336
886a2506
NC		 337 /* Boolean value: TRUE if current insn is short. */
338 bfd_boolean has_limm;
252b5132 339
886a2506
NC		 340 /* Boolean value: TRUE if current insn has delay slot. */
341 bfd_boolean has_delay_slot;
342} arc_last_insns[2];
252b5132 343
b99747ae
CZ		 344/* Extension instruction suffix classes. */
345typedef struct
346{
347 const char *name;
348 int len;
c810e0b8 349 int attr_class;
b99747ae
CZ		 350} attributes_t;
351
352static const attributes_t suffixclass[] =
353{
354 { "SUFFIX_FLAG", 11, ARC_SUFFIX_FLAG },
355 { "SUFFIX_COND", 11, ARC_SUFFIX_COND },
356 { "SUFFIX_NONE", 11, ARC_SUFFIX_NONE }
357};
358
359/* Extension instruction syntax classes. */
360static const attributes_t syntaxclass[] =
361{
362 { "SYNTAX_3OP", 10, ARC_SYNTAX_3OP },
945e0f82
CZ		 363 { "SYNTAX_2OP", 10, ARC_SYNTAX_2OP },
364 { "SYNTAX_1OP", 10, ARC_SYNTAX_1OP },
365 { "SYNTAX_NOP", 10, ARC_SYNTAX_NOP }
b99747ae
CZ		 366};
367
368/* Extension instruction syntax classes modifiers. */
369static const attributes_t syntaxclassmod[] =
370{
371 { "OP1_IMM_IMPLIED" , 15, ARC_OP1_IMM_IMPLIED },
372 { "OP1_MUST_BE_IMM" , 15, ARC_OP1_MUST_BE_IMM }
373};
374
f36e33da
CZ		 375/* Extension register type. */
376typedef struct
377{
378 char *name;
379 int number;
380 int imode;
381} extRegister_t;
382
383/* A structure to hold the additional conditional codes. */
384static struct
385{
386 struct arc_flag_operand *arc_ext_condcode;
387 int size;
388} ext_condcode = { NULL, 0 };
389
da5be039
AB		 390/* Structure to hold an entry in ARC_OPCODE_HASH. */
391struct arc_opcode_hash_entry
392{
393 /* The number of pointers in the OPCODE list. */
394 size_t count;
395
396 /* Points to a list of opcode pointers. */
397 const struct arc_opcode **opcode;
398};
399
1328504b
AB		 400/* Structure used for iterating through an arc_opcode_hash_entry. */
401struct arc_opcode_hash_entry_iterator
402{
403 /* Index into the OPCODE element of the arc_opcode_hash_entry. */
404 size_t index;
405
406 /* The specific ARC_OPCODE from the ARC_OPCODES table that was last
407 returned by this iterator. */
408 const struct arc_opcode *opcode;
409};
410
4670103e
CZ		 411/* Forward declaration. */
412static void assemble_insn
413 (const struct arc_opcode *, const expressionS *, int,
414 const struct arc_flags *, int, struct arc_insn *);
415
bb65a718
AB		 416/* The selection of the machine type can come from different sources. This
417 enum is used to track how the selection was made in order to perform
418 error checks. */
419enum mach_selection_type
420 {
421 MACH_SELECTION_NONE,
422 MACH_SELECTION_FROM_DEFAULT,
423 MACH_SELECTION_FROM_CPU_DIRECTIVE,
424 MACH_SELECTION_FROM_COMMAND_LINE
425 };
426
427/* How the current machine type was selected. */
428static enum mach_selection_type mach_selection_mode = MACH_SELECTION_NONE;
0d2bcfaf 429
886a2506
NC		 430/* The hash table of instruction opcodes. */
431static struct hash_control *arc_opcode_hash;
0d2bcfaf 432
886a2506
NC		 433/* The hash table of register symbols. */
434static struct hash_control *arc_reg_hash;
252b5132 435
f36e33da
CZ		 436/* The hash table of aux register symbols. */
437static struct hash_control *arc_aux_hash;
438
db18dbab
GM		 439/* The hash table of address types. */
440static struct hash_control *arc_addrtype_hash;
441
a9752fdf
CZ		 442#define ARC_CPU_TYPE_A6xx(NAME,EXTRA) \
443 { #NAME, ARC_OPCODE_ARC600, bfd_mach_arc_arc600, \
444 E_ARC_MACH_ARC600, EXTRA}
445#define ARC_CPU_TYPE_A7xx(NAME,EXTRA) \
446 { #NAME, ARC_OPCODE_ARC700, bfd_mach_arc_arc700, \
447 E_ARC_MACH_ARC700, EXTRA}
448#define ARC_CPU_TYPE_AV2EM(NAME,EXTRA) \
449 { #NAME, ARC_OPCODE_ARCv2EM, bfd_mach_arc_arcv2, \
450 EF_ARC_CPU_ARCV2EM, EXTRA}
451#define ARC_CPU_TYPE_AV2HS(NAME,EXTRA) \
452 { #NAME, ARC_OPCODE_ARCv2HS, bfd_mach_arc_arcv2, \
453 EF_ARC_CPU_ARCV2HS, EXTRA}
940171d0
AK		 454#define ARC_CPU_TYPE_NONE \
455 { 0, 0, 0, 0, 0 }
a9752fdf 456
886a2506
NC		 457/* A table of CPU names and opcode sets. */
458static const struct cpu_type
459{
460 const char *name;
461 unsigned flags;
462 int mach;
463 unsigned eflags;
464 unsigned features;
252b5132 465}
886a2506 466 cpu_types[] =
252b5132 467{
940171d0 468 #include "elf/arc-cpu.def"
886a2506 469};
252b5132 470
bb65a718 471/* Information about the cpu/variant we're assembling for. */
53a346d8 472static struct cpu_type selected_cpu = { 0, 0, 0, E_ARC_OSABI_CURRENT, 0 };
bb050a69 473
63741043 474/* TRUE if current assembly code uses RF16 only registers. */
475static bfd_boolean rf16_only = TRUE;
476
53a346d8
CZ		 477/* MPY option. */
478static unsigned mpy_option = 0;
479
480/* Use PIC. */
481static unsigned pic_option = 0;
482
483/* Use small data. */
484static unsigned sda_option = 0;
485
486/* Use TLS. */
487static unsigned tls_option = 0;
bb65a718 488
a9752fdf
CZ		 489/* Command line given features. */
490static unsigned cl_features = 0;
491
886a2506
NC		 492/* Used by the arc_reloc_op table. Order is important. */
493#define O_gotoff O_md1 /* @gotoff relocation. */
494#define O_gotpc O_md2 /* @gotpc relocation. */
495#define O_plt O_md3 /* @plt relocation. */
496#define O_sda O_md4 /* @sda relocation. */
497#define O_pcl O_md5 /* @pcl relocation. */
498#define O_tlsgd O_md6 /* @tlsgd relocation. */
499#define O_tlsie O_md7 /* @tlsie relocation. */
500#define O_tpoff9 O_md8 /* @tpoff9 relocation. */
501#define O_tpoff O_md9 /* @tpoff relocation. */
502#define O_dtpoff9 O_md10 /* @dtpoff9 relocation. */
503#define O_dtpoff O_md11 /* @dtpoff relocation. */
504#define O_last O_dtpoff
505
506/* Used to define a bracket as operand in tokens. */
507#define O_bracket O_md32
508
db18dbab
GM		 509/* Used to define a colon as an operand in tokens. */
510#define O_colon O_md31
511
512/* Used to define address types in nps400. */
513#define O_addrtype O_md30
514
886a2506
NC		 515/* Dummy relocation, to be sorted out. */
516#define DUMMY_RELOC_ARC_ENTRY (BFD_RELOC_UNUSED + 1)
517
518#define USER_RELOC_P(R) ((R) >= O_gotoff && (R) <= O_last)
519
520/* A table to map the spelling of a relocation operand into an appropriate
521 bfd_reloc_code_real_type type. The table is assumed to be ordered such
522 that op-O_literal indexes into it. */
523#define ARC_RELOC_TABLE(op) \
524 (&arc_reloc_op[ ((!USER_RELOC_P (op)) \
525 ? (abort (), 0) \
526 : (int) (op) - (int) O_gotoff) ])
527
528#define DEF(NAME, RELOC, REQ) \
529 { #NAME, sizeof (#NAME)-1, O_##NAME, RELOC, REQ}
530
531static const struct arc_reloc_op_tag
532{
533 /* String to lookup. */
534 const char *name;
535 /* Size of the string. */
536 size_t length;
537 /* Which operator to use. */
538 operatorT op;
539 extended_bfd_reloc_code_real_type reloc;
540 /* Allows complex relocation expression like identifier@reloc +
541 const. */
542 unsigned int complex_expr : 1;
543}
544 arc_reloc_op[] =
6f4b1afc
CM		 545{
546 DEF (gotoff, BFD_RELOC_ARC_GOTOFF, 1),
547 DEF (gotpc, BFD_RELOC_ARC_GOTPC32, 0),
548 DEF (plt, BFD_RELOC_ARC_PLT32, 0),
549 DEF (sda, DUMMY_RELOC_ARC_ENTRY, 1),
550 DEF (pcl, BFD_RELOC_ARC_PC32, 1),
551 DEF (tlsgd, BFD_RELOC_ARC_TLS_GD_GOT, 0),
552 DEF (tlsie, BFD_RELOC_ARC_TLS_IE_GOT, 0),
553 DEF (tpoff9, BFD_RELOC_ARC_TLS_LE_S9, 0),
b125bd17 554 DEF (tpoff, BFD_RELOC_ARC_TLS_LE_32, 1),
6f4b1afc 555 DEF (dtpoff9, BFD_RELOC_ARC_TLS_DTPOFF_S9, 0),
05bbf016 556 DEF (dtpoff, BFD_RELOC_ARC_TLS_DTPOFF, 1),
6f4b1afc 557};
252b5132 558
886a2506
NC		 559static const int arc_num_reloc_op
560= sizeof (arc_reloc_op) / sizeof (*arc_reloc_op);
561
4670103e
CZ		 562/* Structure for relaxable instruction that have to be swapped with a
563 smaller alternative instruction. */
564struct arc_relaxable_ins
565{
566 /* Mnemonic that should be checked. */
567 const char *mnemonic_r;
568
569 /* Operands that should be checked.
570 Indexes of operands from operand array. */
571 enum rlx_operand_type operands[6];
572
573 /* Flags that should be checked. */
574 unsigned flag_classes[5];
575
576 /* Mnemonic (smaller) alternative to be used later for relaxation. */
577 const char *mnemonic_alt;
578
579 /* Index of operand that generic relaxation has to check. */
580 unsigned opcheckidx;
581
582 /* Base subtype index used. */
583 enum arc_rlx_types subtype;
584};
585
586#define RELAX_TABLE_ENTRY(BITS, ISSIGNED, SIZE, NEXT) \
587 { (ISSIGNED) ? ((1 << ((BITS) - 1)) - 1) : ((1 << (BITS)) - 1), \
588 (ISSIGNED) ? -(1 << ((BITS) - 1)) : 0, \
589 (SIZE), \
590 (NEXT) } \
591
592#define RELAX_TABLE_ENTRY_MAX(ISSIGNED, SIZE, NEXT) \
593 { (ISSIGNED) ? 0x7FFFFFFF : 0xFFFFFFFF, \
594 (ISSIGNED) ? -(0x7FFFFFFF) : 0, \
595 (SIZE), \
596 (NEXT) } \
597
598
599/* ARC relaxation table. */
600const relax_typeS md_relax_table[] =
601{
602 /* Fake entry. */
603 {0, 0, 0, 0},
604
605 /* BL_S s13 ->
606 BL s25. */
db18dbab
GM		 607 RELAX_TABLE_ENTRY (13, 1, 2, ARC_RLX_BL),
608 RELAX_TABLE_ENTRY (25, 1, 4, ARC_RLX_NONE),
4670103e
CZ		 609
610 /* B_S s10 ->
611 B s25. */
db18dbab
GM		 612 RELAX_TABLE_ENTRY (10, 1, 2, ARC_RLX_B),
613 RELAX_TABLE_ENTRY (25, 1, 4, ARC_RLX_NONE),
4670103e
CZ		 614
615 /* ADD_S c,b, u3 ->
616 ADD<.f> a,b,u6 ->
617 ADD<.f> a,b,limm. */
db18dbab
GM		 618 RELAX_TABLE_ENTRY (3, 0, 2, ARC_RLX_ADD_U6),
619 RELAX_TABLE_ENTRY (6, 0, 4, ARC_RLX_ADD_LIMM),
620 RELAX_TABLE_ENTRY_MAX (0, 8, ARC_RLX_NONE),
4670103e
CZ		 621
622 /* LD_S a, [b, u7] ->
623 LD<zz><.x><.aa><.di> a, [b, s9] ->
624 LD<zz><.x><.aa><.di> a, [b, limm] */
db18dbab
GM		 625 RELAX_TABLE_ENTRY (7, 0, 2, ARC_RLX_LD_S9),
626 RELAX_TABLE_ENTRY (9, 1, 4, ARC_RLX_LD_LIMM),
627 RELAX_TABLE_ENTRY_MAX (1, 8, ARC_RLX_NONE),
4670103e
CZ		 628
629 /* MOV_S b, u8 ->
630 MOV<.f> b, s12 ->
631 MOV<.f> b, limm. */
db18dbab
GM		 632 RELAX_TABLE_ENTRY (8, 0, 2, ARC_RLX_MOV_S12),
633 RELAX_TABLE_ENTRY (8, 0, 4, ARC_RLX_MOV_LIMM),
634 RELAX_TABLE_ENTRY_MAX (0, 8, ARC_RLX_NONE),
4670103e
CZ		 635
636 /* SUB_S c, b, u3 ->
637 SUB<.f> a, b, u6 ->
638 SUB<.f> a, b, limm. */
db18dbab
GM		 639 RELAX_TABLE_ENTRY (3, 0, 2, ARC_RLX_SUB_U6),
640 RELAX_TABLE_ENTRY (6, 0, 4, ARC_RLX_SUB_LIMM),
641 RELAX_TABLE_ENTRY_MAX (0, 8, ARC_RLX_NONE),
4670103e
CZ		 642
643 /* MPY<.f> a, b, u6 ->
644 MPY<.f> a, b, limm. */
db18dbab
GM		 645 RELAX_TABLE_ENTRY (6, 0, 4, ARC_RLX_MPY_LIMM),
646 RELAX_TABLE_ENTRY_MAX (0, 8, ARC_RLX_NONE),
4670103e
CZ		 647
648 /* MOV<.f><.cc> b, u6 ->
649 MOV<.f><.cc> b, limm. */
db18dbab
GM		 650 RELAX_TABLE_ENTRY (6, 0, 4, ARC_RLX_MOV_RLIMM),
651 RELAX_TABLE_ENTRY_MAX (0, 8, ARC_RLX_NONE),
4670103e
CZ		 652
653 /* ADD<.f><.cc> b, b, u6 ->
654 ADD<.f><.cc> b, b, limm. */
db18dbab
GM		 655 RELAX_TABLE_ENTRY (6, 0, 4, ARC_RLX_ADD_RRLIMM),
656 RELAX_TABLE_ENTRY_MAX (0, 8, ARC_RLX_NONE),
4670103e
CZ		 657};
658
659/* Order of this table's entries matters! */
660const struct arc_relaxable_ins arc_relaxable_insns[] =
661{
662 { "bl", { IMMEDIATE }, { 0 }, "bl_s", 0, ARC_RLX_BL_S },
663 { "b", { IMMEDIATE }, { 0 }, "b_s", 0, ARC_RLX_B_S },
664 { "add", { REGISTER, REGISTER_DUP, IMMEDIATE }, { 5, 1, 0 }, "add",
665 2, ARC_RLX_ADD_RRU6},
666 { "add", { REGISTER_S, REGISTER_S, IMMEDIATE }, { 0 }, "add_s", 2,
667 ARC_RLX_ADD_U3 },
668 { "add", { REGISTER, REGISTER, IMMEDIATE }, { 5, 0 }, "add", 2,
669 ARC_RLX_ADD_U6 },
670 { "ld", { REGISTER_S, BRACKET, REGISTER_S, IMMEDIATE, BRACKET },
671 { 0 }, "ld_s", 3, ARC_RLX_LD_U7 },
672 { "ld", { REGISTER, BRACKET, REGISTER_NO_GP, IMMEDIATE, BRACKET },
673 { 11, 4, 14, 17, 0 }, "ld", 3, ARC_RLX_LD_S9 },
674 { "mov", { REGISTER_S, IMMEDIATE }, { 0 }, "mov_s", 1, ARC_RLX_MOV_U8 },
675 { "mov", { REGISTER, IMMEDIATE }, { 5, 0 }, "mov", 1, ARC_RLX_MOV_S12 },
676 { "mov", { REGISTER, IMMEDIATE }, { 5, 1, 0 },"mov", 1, ARC_RLX_MOV_RU6 },
677 { "sub", { REGISTER_S, REGISTER_S, IMMEDIATE }, { 0 }, "sub_s", 2,
678 ARC_RLX_SUB_U3 },
679 { "sub", { REGISTER, REGISTER, IMMEDIATE }, { 5, 0 }, "sub", 2,
680 ARC_RLX_SUB_U6 },
681 { "mpy", { REGISTER, REGISTER, IMMEDIATE }, { 5, 0 }, "mpy", 2,
682 ARC_RLX_MPY_U6 },
683};
684
685const unsigned arc_num_relaxable_ins = ARRAY_SIZE (arc_relaxable_insns);
686
886a2506
NC		 687/* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
688symbolS * GOT_symbol = 0;
689
690/* Set to TRUE when we assemble instructions. */
691static bfd_boolean assembling_insn = FALSE;
692
53a346d8
CZ		 693/* List with attributes set explicitly. */
694static bfd_boolean attributes_set_explicitly[NUM_KNOWN_OBJ_ATTRIBUTES];
695
886a2506
NC		 696/* Functions implementation. */
697
b9b47ab7
AB		 698/* Return a pointer to ARC_OPCODE_HASH_ENTRY that identifies all
699 ARC_OPCODE entries in ARC_OPCODE_HASH that match NAME, or NULL if there
700 are no matching entries in ARC_OPCODE_HASH. */
da5be039 701
b9b47ab7 702static const struct arc_opcode_hash_entry *
da5be039
AB		 703arc_find_opcode (const char *name)
704{
705 const struct arc_opcode_hash_entry *entry;
da5be039
AB		 706
707 entry = hash_find (arc_opcode_hash, name);
b9b47ab7 708 return entry;
da5be039
AB		 709}
710
1328504b
AB		 711/* Initialise the iterator ITER. */
712
713static void
714arc_opcode_hash_entry_iterator_init (struct arc_opcode_hash_entry_iterator *iter)
715{
716 iter->index = 0;
717 iter->opcode = NULL;
718}
719
720/* Return the next ARC_OPCODE from ENTRY, using ITER to hold state between
721 calls to this function. Return NULL when all ARC_OPCODE entries have
722 been returned. */
723
724static const struct arc_opcode *
725arc_opcode_hash_entry_iterator_next (const struct arc_opcode_hash_entry *entry,
726 struct arc_opcode_hash_entry_iterator *iter)
727{
728 if (iter->opcode == NULL && iter->index == 0)
729 {
730 gas_assert (entry->count > 0);
731 iter->opcode = entry->opcode[iter->index];
732 }
733 else if (iter->opcode != NULL)
734 {
735 const char *old_name = iter->opcode->name;
736
737 iter->opcode++;
fe779266
AB		 738 if (iter->opcode->name == NULL
739 || strcmp (old_name, iter->opcode->name) != 0)
1328504b
AB		 740 {
741 iter->index++;
742 if (iter->index == entry->count)
743 iter->opcode = NULL;
744 else
745 iter->opcode = entry->opcode[iter->index];
746 }
747 }
748
749 return iter->opcode;
750}
751
b99747ae
CZ		 752/* Insert an opcode into opcode hash structure. */
753
754static void
755arc_insert_opcode (const struct arc_opcode *opcode)
756{
757 const char *name, *retval;
758 struct arc_opcode_hash_entry *entry;
759 name = opcode->name;
760
761 entry = hash_find (arc_opcode_hash, name);
762 if (entry == NULL)
763 {
add39d23 764 entry = XNEW (struct arc_opcode_hash_entry);
b99747ae
CZ		 765 entry->count = 0;
766 entry->opcode = NULL;
767
768 retval = hash_insert (arc_opcode_hash, name, (void *) entry);
769 if (retval)
770 as_fatal (_("internal error: can't hash opcode '%s': %s"),
771 name, retval);
772 }
773
add39d23
TS		 774 entry->opcode = XRESIZEVEC (const struct arc_opcode *, entry->opcode,
775 entry->count + 1);
b99747ae
CZ		 776
777 if (entry->opcode == NULL)
778 as_fatal (_("Virtual memory exhausted"));
779
780 entry->opcode[entry->count] = opcode;
781 entry->count++;
782}
783
784
bdfe53e3
AB		 785/* Like md_number_to_chars but for middle-endian values. The 4-byte limm
786 value, is encoded as 'middle-endian' for a little-endian target. This
787 function is used for regular 4, 6, and 8 byte instructions as well. */
886a2506
NC		 788
789static void
bdfe53e3 790md_number_to_chars_midend (char *buf, unsigned long long val, int n)
886a2506 791{
bdfe53e3 792 switch (n)
886a2506 793 {
bdfe53e3
AB		 794 case 2:
795 md_number_to_chars (buf, val, n);
796 break;
797 case 6:
53b6d6f5 798 md_number_to_chars (buf, (val & 0xffff00000000ull) >> 32, 2);
bdfe53e3
AB		 799 md_number_to_chars_midend (buf + 2, (val & 0xffffffff), 4);
800 break;
801 case 4:
886a2506
NC		 802 md_number_to_chars (buf, (val & 0xffff0000) >> 16, 2);
803 md_number_to_chars (buf + 2, (val & 0xffff), 2);
bdfe53e3
AB		 804 break;
805 case 8:
53b6d6f5 806 md_number_to_chars_midend (buf, (val & 0xffffffff00000000ull) >> 32, 4);
bdfe53e3
AB		 807 md_number_to_chars_midend (buf + 4, (val & 0xffffffff), 4);
808 break;
809 default:
810 abort ();
886a2506 811 }
252b5132
RH		 812}
813
bb050a69
CZ		 814/* Check if a feature is allowed for a specific CPU. */
815
816static void
817arc_check_feature (void)
818{
819 unsigned i;
820
821 if (!selected_cpu.features
822 || !selected_cpu.name)
823 return;
53a346d8
CZ		 824
825 for (i = 0; i < ARRAY_SIZE (feature_list); i++)
826 if ((selected_cpu.features & feature_list[i].feature)
827 && !(selected_cpu.flags & feature_list[i].cpus))
828 as_bad (_("invalid %s option for %s cpu"), feature_list[i].name,
829 selected_cpu.name);
830
831 for (i = 0; i < ARRAY_SIZE (conflict_list); i++)
832 if ((selected_cpu.features & conflict_list[i]) == conflict_list[i])
833 as_bad(_("conflicting ISA extension attributes."));
bb050a69
CZ		 834}
835
24740d83 836/* Select an appropriate entry from CPU_TYPES based on ARG and initialise
bb65a718
AB		 837 the relevant static global variables. Parameter SEL describes where
838 this selection originated from. */
24740d83
AB		 839
840static void
bb65a718 841arc_select_cpu (const char *arg, enum mach_selection_type sel)
24740d83 842{
24740d83
AB		 843 int i;
844
bb65a718
AB		 845 /* We should only set a default if we've not made a selection from some
846 other source. */
847 gas_assert (sel != MACH_SELECTION_FROM_DEFAULT
848 || mach_selection_mode == MACH_SELECTION_NONE);
849
bb050a69
CZ		 850 if ((mach_selection_mode == MACH_SELECTION_FROM_CPU_DIRECTIVE)
851 && (sel == MACH_SELECTION_FROM_CPU_DIRECTIVE))
852 as_bad (_("Multiple .cpu directives found"));
853
bb65a718 854 /* Look for a matching entry in CPU_TYPES array. */
24740d83
AB		 855 for (i = 0; cpu_types[i].name; ++i)
856 {
857 if (!strcasecmp (cpu_types[i].name, arg))
858 {
bb65a718
AB		 859 /* If a previous selection was made on the command line, then we
860 allow later selections on the command line to override earlier
861 ones. However, a selection from a '.cpu NAME' directive must
862 match the command line selection, or we give a warning. */
863 if (mach_selection_mode == MACH_SELECTION_FROM_COMMAND_LINE)
864 {
865 gas_assert (sel == MACH_SELECTION_FROM_COMMAND_LINE
866 || sel == MACH_SELECTION_FROM_CPU_DIRECTIVE);
867 if (sel == MACH_SELECTION_FROM_CPU_DIRECTIVE
868 && selected_cpu.mach != cpu_types[i].mach)
869 {
870 as_warn (_("Command-line value overrides \".cpu\" directive"));
bb65a718 871 }
bb050a69 872 return;
bb65a718
AB		 873 }
874
bb050a69
CZ		 875 /* Initialise static global data about selected machine type. */
876 selected_cpu.flags = cpu_types[i].flags;
877 selected_cpu.name = cpu_types[i].name;
a9752fdf 878 selected_cpu.features = cpu_types[i].features | cl_features;
bb050a69 879 selected_cpu.mach = cpu_types[i].mach;
53a346d8
CZ		 880 selected_cpu.eflags = ((selected_cpu.eflags & ~EF_ARC_MACH_MSK)
881 | cpu_types[i].eflags);
24740d83
AB		 882 break;
883 }
884 }
885
886 if (!cpu_types[i].name)
887 as_fatal (_("unknown architecture: %s\n"), arg);
bb050a69
CZ		 888
889 /* Check if set features are compatible with the chosen CPU. */
890 arc_check_feature ();
53a346d8 891
bb65a718 892 mach_selection_mode = sel;
24740d83
AB		 893}
894
886a2506
NC		 895/* Here ends all the ARCompact extension instruction assembling
896 stuff. */
252b5132 897
886a2506
NC		 898static void
899arc_extra_reloc (int r_type)
ea1562b3 900{
886a2506
NC		 901 char *sym_name, c;
902 symbolS *sym, *lab = NULL;
903
904 if (*input_line_pointer == '@')
905 input_line_pointer++;
906 c = get_symbol_name (&sym_name);
907 sym = symbol_find_or_make (sym_name);
908 restore_line_pointer (c);
909 if (c == ',' && r_type == BFD_RELOC_ARC_TLS_GD_LD)
910 {
911 ++input_line_pointer;
912 char *lab_name;
913 c = get_symbol_name (&lab_name);
914 lab = symbol_find_or_make (lab_name);
915 restore_line_pointer (c);
916 }
841fdfcd
CZ		 917
918 /* These relocations exist as a mechanism for the compiler to tell the
919 linker how to patch the code if the tls model is optimised. However,
920 the relocation itself does not require any space within the assembler
921 fragment, and so we pass a size of 0.
922
923 The lines that generate these relocations look like this:
924
925 .tls_gd_ld @.tdata`bl __tls_get_addr@plt
926
927 The '.tls_gd_ld @.tdata' is processed first and generates the
928 additional relocation, while the 'bl __tls_get_addr@plt' is processed
929 second and generates the additional branch.
930
931 It is possible that the additional relocation generated by the
932 '.tls_gd_ld @.tdata' will be attached at the very end of one fragment,
933 while the 'bl __tls_get_addr@plt' will be generated as the first thing
934 in the next fragment. This will be fine; both relocations will still
935 appear to be at the same address in the generated object file.
936 However, this only works as the additional relocation is generated
937 with size of 0 bytes. */
886a2506
NC		 938 fixS *fixP
939 = fix_new (frag_now, /* Which frag? */
940 frag_now_fix (), /* Where in that frag? */
841fdfcd 941 0, /* size: 1, 2, or 4 usually. */
886a2506
NC		 942 sym, /* X_add_symbol. */
943 0, /* X_add_number. */
944 FALSE, /* TRUE if PC-relative relocation. */
945 r_type /* Relocation type. */);
946 fixP->fx_subsy = lab;
947}
252b5132 948
886a2506
NC		 949static symbolS *
950arc_lcomm_internal (int ignore ATTRIBUTE_UNUSED,
951 symbolS *symbolP, addressT size)
952{
953 addressT align = 0;
954 SKIP_WHITESPACE ();
252b5132 955
886a2506
NC		 956 if (*input_line_pointer == ',')
957 {
958 align = parse_align (1);
252b5132 959
886a2506
NC		 960 if (align == (addressT) -1)
961 return NULL;
962 }
963 else
964 {
965 if (size >= 8)
966 align = 3;
967 else if (size >= 4)
968 align = 2;
969 else if (size >= 2)
970 align = 1;
971 else
972 align = 0;
973 }
252b5132 974
886a2506
NC		 975 bss_alloc (symbolP, size, align);
976 S_CLEAR_EXTERNAL (symbolP);
ea1562b3 977
886a2506
NC		 978 return symbolP;
979}
ea1562b3 980
886a2506
NC		 981static void
982arc_lcomm (int ignore)
983{
984 symbolS *symbolP = s_comm_internal (ignore, arc_lcomm_internal);
ea1562b3 985
886a2506
NC		 986 if (symbolP)
987 symbol_get_bfdsym (symbolP)->flags |= BSF_OBJECT;
988}
ea1562b3 989
886a2506 990/* Select the cpu we're assembling for. */
ea1562b3 991
886a2506
NC		 992static void
993arc_option (int ignore ATTRIBUTE_UNUSED)
252b5132 994{
886a2506
NC		 995 char c;
996 char *cpu;
bb65a718 997 const char *cpu_name;
252b5132 998
886a2506 999 c = get_symbol_name (&cpu);
252b5132 1000
a9752fdf 1001 cpu_name = cpu;
bb65a718
AB		 1002 if ((!strcmp ("ARC600", cpu))
1003 || (!strcmp ("ARC601", cpu))
1004 || (!strcmp ("A6", cpu)))
1005 cpu_name = "arc600";
1006 else if ((!strcmp ("ARC700", cpu))
1007 || (!strcmp ("A7", cpu)))
1008 cpu_name = "arc700";
1009 else if (!strcmp ("EM", cpu))
1010 cpu_name = "arcem";
1011 else if (!strcmp ("HS", cpu))
1012 cpu_name = "archs";
1013 else if (!strcmp ("NPS400", cpu))
1014 cpu_name = "nps400";
886a2506 1015
a9752fdf 1016 arc_select_cpu (cpu_name, MACH_SELECTION_FROM_CPU_DIRECTIVE);
24b368f8 1017
24b368f8 1018 restore_line_pointer (c);
886a2506 1019 demand_empty_rest_of_line ();
ea1562b3 1020}
252b5132 1021
886a2506
NC		 1022/* Smartly print an expression. */
1023
ea1562b3 1024static void
886a2506 1025debug_exp (expressionS *t)
ea1562b3 1026{
886a2506
NC		 1027 const char *name ATTRIBUTE_UNUSED;
1028 const char *namemd ATTRIBUTE_UNUSED;
252b5132 1029
886a2506 1030 pr_debug ("debug_exp: ");
252b5132 1031
886a2506 1032 switch (t->X_op)
252b5132 1033 {
886a2506
NC		 1034 default: name = "unknown"; break;
1035 case O_illegal: name = "O_illegal"; break;
1036 case O_absent: name = "O_absent"; break;
1037 case O_constant: name = "O_constant"; break;
1038 case O_symbol: name = "O_symbol"; break;
1039 case O_symbol_rva: name = "O_symbol_rva"; break;
1040 case O_register: name = "O_register"; break;
1041 case O_big: name = "O_big"; break;
1042 case O_uminus: name = "O_uminus"; break;
1043 case O_bit_not: name = "O_bit_not"; break;
1044 case O_logical_not: name = "O_logical_not"; break;
1045 case O_multiply: name = "O_multiply"; break;
1046 case O_divide: name = "O_divide"; break;
1047 case O_modulus: name = "O_modulus"; break;
1048 case O_left_shift: name = "O_left_shift"; break;
1049 case O_right_shift: name = "O_right_shift"; break;
1050 case O_bit_inclusive_or: name = "O_bit_inclusive_or"; break;
1051 case O_bit_or_not: name = "O_bit_or_not"; break;
1052 case O_bit_exclusive_or: name = "O_bit_exclusive_or"; break;
1053 case O_bit_and: name = "O_bit_and"; break;
1054 case O_add: name = "O_add"; break;
1055 case O_subtract: name = "O_subtract"; break;
1056 case O_eq: name = "O_eq"; break;
1057 case O_ne: name = "O_ne"; break;
1058 case O_lt: name = "O_lt"; break;
1059 case O_le: name = "O_le"; break;
1060 case O_ge: name = "O_ge"; break;
1061 case O_gt: name = "O_gt"; break;
1062 case O_logical_and: name = "O_logical_and"; break;
1063 case O_logical_or: name = "O_logical_or"; break;
1064 case O_index: name = "O_index"; break;
1065 case O_bracket: name = "O_bracket"; break;
db18dbab
GM		 1066 case O_colon: name = "O_colon"; break;
1067 case O_addrtype: name = "O_addrtype"; break;
ea1562b3 1068 }
252b5132 1069
886a2506 1070 switch (t->X_md)
ea1562b3 1071 {
886a2506
NC		 1072 default: namemd = "unknown"; break;
1073 case O_gotoff: namemd = "O_gotoff"; break;
1074 case O_gotpc: namemd = "O_gotpc"; break;
1075 case O_plt: namemd = "O_plt"; break;
1076 case O_sda: namemd = "O_sda"; break;
1077 case O_pcl: namemd = "O_pcl"; break;
1078 case O_tlsgd: namemd = "O_tlsgd"; break;
1079 case O_tlsie: namemd = "O_tlsie"; break;
1080 case O_tpoff9: namemd = "O_tpoff9"; break;
1081 case O_tpoff: namemd = "O_tpoff"; break;
1082 case O_dtpoff9: namemd = "O_dtpoff9"; break;
1083 case O_dtpoff: namemd = "O_dtpoff"; break;
ea1562b3 1084 }
252b5132 1085
886a2506
NC		 1086 pr_debug ("%s (%s, %s, %d, %s)", name,
1087 (t->X_add_symbol) ? S_GET_NAME (t->X_add_symbol) : "--",
1088 (t->X_op_symbol) ? S_GET_NAME (t->X_op_symbol) : "--",
1089 (int) t->X_add_number,
1090 (t->X_md) ? namemd : "--");
1091 pr_debug ("\n");
1092 fflush (stderr);
1093}
252b5132 1094
2a1ebfb2
CZ		 1095/* Helper for parsing an argument, used for sorting out the relocation
1096 type. */
1097
1098static void
1099parse_reloc_symbol (expressionS *resultP)
1100{
1101 char *reloc_name, c, *sym_name;
1102 size_t len;
1103 int i;
1104 const struct arc_reloc_op_tag *r;
1105 expressionS right;
1106 symbolS *base;
1107
1108 /* A relocation operand has the following form
1109 @identifier@relocation_type. The identifier is already in
1110 tok! */
1111 if (resultP->X_op != O_symbol)
1112 {
1113 as_bad (_("No valid label relocation operand"));
1114 resultP->X_op = O_illegal;
1115 return;
1116 }
1117
1118 /* Parse @relocation_type. */
1119 input_line_pointer++;
1120 c = get_symbol_name (&reloc_name);
1121 len = input_line_pointer - reloc_name;
1122 if (len == 0)
1123 {
1124 as_bad (_("No relocation operand"));
1125 resultP->X_op = O_illegal;
1126 return;
1127 }
1128
1129 /* Go through known relocation and try to find a match. */
1130 r = &arc_reloc_op[0];
1131 for (i = arc_num_reloc_op - 1; i >= 0; i--, r++)
1132 if (len == r->length
1133 && memcmp (reloc_name, r->name, len) == 0)
1134 break;
1135 if (i < 0)
1136 {
1137 as_bad (_("Unknown relocation operand: @%s"), reloc_name);
1138 resultP->X_op = O_illegal;
1139 return;
1140 }
1141
1142 *input_line_pointer = c;
1143 SKIP_WHITESPACE_AFTER_NAME ();
1144 /* Extra check for TLS: base. */
1145 if (*input_line_pointer == '@')
1146 {
1147 if (resultP->X_op_symbol != NULL
1148 || resultP->X_op != O_symbol)
1149 {
1150 as_bad (_("Unable to parse TLS base: %s"),
1151 input_line_pointer);
1152 resultP->X_op = O_illegal;
1153 return;
1154 }
1155 input_line_pointer++;
1156 c = get_symbol_name (&sym_name);
1157 base = symbol_find_or_make (sym_name);
1158 resultP->X_op = O_subtract;
1159 resultP->X_op_symbol = base;
1160 restore_line_pointer (c);
1161 right.X_add_number = 0;
1162 }
1163
1164 if ((*input_line_pointer != '+')
1165 && (*input_line_pointer != '-'))
1166 right.X_add_number = 0;
1167 else
1168 {
1169 /* Parse the constant of a complex relocation expression
1170 like @identifier@reloc +/- const. */
1171 if (! r->complex_expr)
1172 {
1173 as_bad (_("@%s is not a complex relocation."), r->name);
1174 resultP->X_op = O_illegal;
1175 return;
1176 }
1177 expression (&right);
1178 if (right.X_op != O_constant)
1179 {
1180 as_bad (_("Bad expression: @%s + %s."),
1181 r->name, input_line_pointer);
1182 resultP->X_op = O_illegal;
1183 return;
1184 }
1185 }
1186
1187 resultP->X_md = r->op;
1188 resultP->X_add_number = right.X_add_number;
1189}
1190
886a2506
NC		 1191/* Parse the arguments to an opcode. */
1192
1193static int
1194tokenize_arguments (char *str,
1195 expressionS *tok,
1196 int ntok)
1197{
1198 char *old_input_line_pointer;
1199 bfd_boolean saw_comma = FALSE;
1200 bfd_boolean saw_arg = FALSE;
1201 int brk_lvl = 0;
1202 int num_args = 0;
886a2506
NC		 1203
1204 memset (tok, 0, sizeof (*tok) * ntok);
1205
1206 /* Save and restore input_line_pointer around this function. */
1207 old_input_line_pointer = input_line_pointer;
1208 input_line_pointer = str;
ea1562b3 1209
886a2506 1210 while (*input_line_pointer)
ea1562b3
NC		 1211 {
1212 SKIP_WHITESPACE ();
886a2506 1213 switch (*input_line_pointer)
252b5132 1214 {
886a2506
NC		 1215 case '\0':
1216 goto fini;
1217
1218 case ',':
1219 input_line_pointer++;
1220 if (saw_comma || !saw_arg)
1221 goto err;
1222 saw_comma = TRUE;
1223 break;
252b5132 1224
886a2506
NC		 1225 case '}':
1226 case ']':
1227 ++input_line_pointer;
1228 --brk_lvl;
3b889a78 1229 if (!saw_arg || num_args == ntok)
886a2506
NC		 1230 goto err;
1231 tok->X_op = O_bracket;
1232 ++tok;
1233 ++num_args;
1234 break;
ea1562b3 1235
886a2506
NC		 1236 case '{':
1237 case '[':
1238 input_line_pointer++;
3b889a78 1239 if (brk_lvl || num_args == ntok)
886a2506
NC		 1240 goto err;
1241 ++brk_lvl;
1242 tok->X_op = O_bracket;
1243 ++tok;
1244 ++num_args;
1245 break;
1246
db18dbab
GM		 1247 case ':':
1248 input_line_pointer++;
1249 if (!saw_arg || num_args == ntok)
1250 goto err;
1251 tok->X_op = O_colon;
1252 saw_arg = FALSE;
1253 ++tok;
1254 ++num_args;
1255 break;
1256
886a2506
NC		 1257 case '@':
1258 /* We have labels, function names and relocations, all
1259 starting with @ symbol. Sort them out. */
3b889a78 1260 if ((saw_arg && !saw_comma) || num_args == ntok)
886a2506
NC		 1261 goto err;
1262
1263 /* Parse @label. */
2a1ebfb2 1264 input_line_pointer++;
886a2506
NC		 1265 tok->X_op = O_symbol;
1266 tok->X_md = O_absent;
1267 expression (tok);
886a2506 1268
886a2506 1269 if (*input_line_pointer == '@')
2a1ebfb2 1270 parse_reloc_symbol (tok);
1e07b820 1271
886a2506 1272 debug_exp (tok);
ea1562b3 1273
2a1ebfb2
CZ		 1274 if (tok->X_op == O_illegal
1275 || tok->X_op == O_absent
1276 || num_args == ntok)
1277 goto err;
1278
886a2506
NC		 1279 saw_comma = FALSE;
1280 saw_arg = TRUE;
1281 tok++;
1282 num_args++;
1283 break;
252b5132 1284
886a2506
NC		 1285 case '%':
1286 /* Can be a register. */
1287 ++input_line_pointer;
1288 /* Fall through. */
1289 default:
252b5132 1290
3b889a78 1291 if ((saw_arg && !saw_comma) || num_args == ntok)
886a2506 1292 goto err;
252b5132 1293
886a2506 1294 tok->X_op = O_absent;
6f4b1afc 1295 tok->X_md = O_absent;
886a2506 1296 expression (tok);
252b5132 1297
6f4b1afc
CM		 1298 /* Legacy: There are cases when we have
1299 identifier@relocation_type, if it is the case parse the
1300 relocation type as well. */
1301 if (*input_line_pointer == '@')
2a1ebfb2 1302 parse_reloc_symbol (tok);
6f4b1afc 1303
886a2506 1304 debug_exp (tok);
252b5132 1305
3b889a78
AB		 1306 if (tok->X_op == O_illegal
1307 || tok->X_op == O_absent
1308 || num_args == ntok)
886a2506 1309 goto err;
252b5132 1310
886a2506
NC		 1311 saw_comma = FALSE;
1312 saw_arg = TRUE;
1313 tok++;
1314 num_args++;
1315 break;
1316 }
ea1562b3 1317 }
252b5132 1318
886a2506
NC		 1319 fini:
1320 if (saw_comma || brk_lvl)
1321 goto err;
1322 input_line_pointer = old_input_line_pointer;
252b5132 1323
886a2506 1324 return num_args;
252b5132 1325
886a2506
NC		 1326 err:
1327 if (brk_lvl)
1328 as_bad (_("Brackets in operand field incorrect"));
1329 else if (saw_comma)
1330 as_bad (_("extra comma"));
1331 else if (!saw_arg)
1332 as_bad (_("missing argument"));
1333 else
1334 as_bad (_("missing comma or colon"));
1335 input_line_pointer = old_input_line_pointer;
1336 return -1;
252b5132 1337}
ea1562b3 1338
886a2506
NC		 1339/* Parse the flags to a structure. */
1340
1341static int
1342tokenize_flags (const char *str,
1343 struct arc_flags flags[],
1344 int nflg)
252b5132 1345{
886a2506
NC		 1346 char *old_input_line_pointer;
1347 bfd_boolean saw_flg = FALSE;
1348 bfd_boolean saw_dot = FALSE;
1349 int num_flags = 0;
1350 size_t flgnamelen;
252b5132 1351
886a2506 1352 memset (flags, 0, sizeof (*flags) * nflg);
0d2bcfaf 1353
886a2506
NC		 1354 /* Save and restore input_line_pointer around this function. */
1355 old_input_line_pointer = input_line_pointer;
1356 input_line_pointer = (char *) str;
0d2bcfaf 1357
886a2506
NC		 1358 while (*input_line_pointer)
1359 {
1360 switch (*input_line_pointer)
1361 {
1362 case ' ':
1363 case '\0':
1364 goto fini;
1365
1366 case '.':
1367 input_line_pointer++;
1368 if (saw_dot)
1369 goto err;
1370 saw_dot = TRUE;
1371 saw_flg = FALSE;
1372 break;
ea1562b3 1373
886a2506
NC		 1374 default:
1375 if (saw_flg && !saw_dot)
1376 goto err;
0d2bcfaf 1377
886a2506
NC		 1378 if (num_flags >= nflg)
1379 goto err;
0d2bcfaf 1380
692166c2
AB		 1381 flgnamelen = strspn (input_line_pointer,
1382 "abcdefghijklmnopqrstuvwxyz0123456789");
83cda17b 1383 if (flgnamelen > MAX_FLAG_NAME_LENGTH)
886a2506 1384 goto err;
0d2bcfaf 1385
886a2506 1386 memcpy (flags->name, input_line_pointer, flgnamelen);
0d2bcfaf 1387
886a2506
NC		 1388 input_line_pointer += flgnamelen;
1389 flags++;
1390 saw_dot = FALSE;
1391 saw_flg = TRUE;
1392 num_flags++;
1393 break;
1e07b820 1394 }
0d2bcfaf
NC		 1395 }
1396
886a2506
NC		 1397 fini:
1398 input_line_pointer = old_input_line_pointer;
1399 return num_flags;
0d2bcfaf 1400
886a2506
NC		 1401 err:
1402 if (saw_dot)
1403 as_bad (_("extra dot"));
1404 else if (!saw_flg)
1405 as_bad (_("unrecognized flag"));
1406 else
1407 as_bad (_("failed to parse flags"));
1408 input_line_pointer = old_input_line_pointer;
1409 return -1;
1410}
0d2bcfaf 1411
4670103e 1412/* Apply the fixups in order. */
0d2bcfaf 1413
4670103e
CZ		 1414static void
1415apply_fixups (struct arc_insn *insn, fragS *fragP, int fix)
886a2506 1416{
4670103e 1417 int i;
0d2bcfaf 1418
4670103e 1419 for (i = 0; i < insn->nfixups; i++)
252b5132 1420 {
4670103e
CZ		 1421 struct arc_fixup *fixup = &insn->fixups[i];
1422 int size, pcrel, offset = 0;
0d2bcfaf 1423
4670103e
CZ		 1424 /* FIXME! the reloc size is wrong in the BFD file.
1425 When it is fixed please delete me. */
91fdca6f 1426 size = ((insn->len == 2) && !fixup->islong) ? 2 : 4;
0d2bcfaf 1427
4670103e 1428 if (fixup->islong)
91fdca6f 1429 offset = insn->len;
252b5132 1430
4670103e
CZ		 1431 /* Some fixups are only used internally, thus no howto. */
1432 if ((int) fixup->reloc == 0)
1433 as_fatal (_("Unhandled reloc type"));
886a2506 1434
4670103e
CZ		 1435 if ((int) fixup->reloc < 0)
1436 {
1437 /* FIXME! the reloc size is wrong in the BFD file.
1438 When it is fixed please enable me.
91fdca6f 1439 size = ((insn->len == 2 && !fixup->islong) ? 2 : 4; */
4670103e
CZ		 1440 pcrel = fixup->pcrel;
1441 }
1442 else
1443 {
1444 reloc_howto_type *reloc_howto =
1445 bfd_reloc_type_lookup (stdoutput,
1446 (bfd_reloc_code_real_type) fixup->reloc);
1447 gas_assert (reloc_howto);
0d2bcfaf 1448
4670103e
CZ		 1449 /* FIXME! the reloc size is wrong in the BFD file.
1450 When it is fixed please enable me.
1451 size = bfd_get_reloc_size (reloc_howto); */
1452 pcrel = reloc_howto->pc_relative;
1453 }
0d2bcfaf 1454
4670103e
CZ		 1455 pr_debug ("%s:%d: apply_fixups: new %s fixup (PCrel:%s) of size %d @ \
1456offset %d + %d\n",
1457 fragP->fr_file, fragP->fr_line,
1458 (fixup->reloc < 0) ? "Internal" :
1459 bfd_get_reloc_code_name (fixup->reloc),
1460 pcrel ? "Y" : "N",
1461 size, fix, offset);
1462 fix_new_exp (fragP, fix + offset,
1463 size, &fixup->exp, pcrel, fixup->reloc);
0d2bcfaf 1464
4670103e
CZ		 1465 /* Check for ZOLs, and update symbol info if any. */
1466 if (LP_INSN (insn->insn))
886a2506 1467 {
4670103e
CZ		 1468 gas_assert (fixup->exp.X_add_symbol);
1469 ARC_SET_FLAG (fixup->exp.X_add_symbol, ARC_FLAG_ZOL);
886a2506
NC		 1470 }
1471 }
252b5132
RH		 1472}
1473
4670103e 1474/* Actually output an instruction with its fixup. */
886a2506 1475
4670103e
CZ		 1476static void
1477emit_insn0 (struct arc_insn *insn, char *where, bfd_boolean relax)
252b5132 1478{
4670103e 1479 char *f = where;
91fdca6f 1480 size_t total_len;
252b5132 1481
bdfe53e3
AB		 1482 pr_debug ("Emit insn : 0x%llx\n", insn->insn);
1483 pr_debug ("\tLength : 0x%d\n", insn->len);
4670103e 1484 pr_debug ("\tLong imm: 0x%lx\n", insn->limm);
0d2bcfaf 1485
4670103e 1486 /* Write out the instruction. */
91fdca6f
GM		 1487 total_len = insn->len + (insn->has_limm ? 4 : 0);
1488 if (!relax)
1489 f = frag_more (total_len);
1490
1491 md_number_to_chars_midend(f, insn->insn, insn->len);
1492
1493 if (insn->has_limm)
1494 md_number_to_chars_midend (f + insn->len, insn->limm, 4);
1495 dwarf2_emit_insn (total_len);
252b5132 1496
4670103e
CZ		 1497 if (!relax)
1498 apply_fixups (insn, frag_now, (f - frag_now->fr_literal));
1499}
252b5132 1500
4670103e
CZ		 1501static void
1502emit_insn1 (struct arc_insn *insn)
1503{
1504 /* How frag_var's args are currently configured:
1505 - rs_machine_dependent, to dictate it's a relaxation frag.
1506 - FRAG_MAX_GROWTH, maximum size of instruction
1507 - 0, variable size that might grow...unused by generic relaxation.
1508 - frag_now->fr_subtype, fr_subtype starting value, set previously.
1509 - s, opand expression.
1510 - 0, offset but it's unused.
1511 - 0, opcode but it's unused. */
1512 symbolS *s = make_expr_symbol (&insn->fixups[0].exp);
1513 frag_now->tc_frag_data.pcrel = insn->fixups[0].pcrel;
1514
1515 if (frag_room () < FRAG_MAX_GROWTH)
1516 {
1517 /* Handle differently when frag literal memory is exhausted.
1518 This is used because when there's not enough memory left in
1519 the current frag, a new frag is created and the information
1520 we put into frag_now->tc_frag_data is disregarded. */
252b5132 1521
4670103e
CZ		 1522 struct arc_relax_type relax_info_copy;
1523 relax_substateT subtype = frag_now->fr_subtype;
252b5132 1524
4670103e
CZ		 1525 memcpy (&relax_info_copy, &frag_now->tc_frag_data,
1526 sizeof (struct arc_relax_type));
0d2bcfaf 1527
4670103e
CZ		 1528 frag_wane (frag_now);
1529 frag_grow (FRAG_MAX_GROWTH);
0d2bcfaf 1530
4670103e
CZ		 1531 memcpy (&frag_now->tc_frag_data, &relax_info_copy,
1532 sizeof (struct arc_relax_type));
252b5132 1533
4670103e
CZ		 1534 frag_var (rs_machine_dependent, FRAG_MAX_GROWTH, 0,
1535 subtype, s, 0, 0);
1536 }
1537 else
1538 frag_var (rs_machine_dependent, FRAG_MAX_GROWTH, 0,
1539 frag_now->fr_subtype, s, 0, 0);
1540}
252b5132 1541
4670103e
CZ		 1542static void
1543emit_insn (struct arc_insn *insn)
252b5132 1544{
4670103e
CZ		 1545 if (insn->relax)
1546 emit_insn1 (insn);
252b5132 1547 else
4670103e 1548 emit_insn0 (insn, NULL, FALSE);
252b5132
RH		 1549}
1550
4670103e 1551/* Check whether a symbol involves a register. */
252b5132 1552
4670103e
CZ		 1553static bfd_boolean
1554contains_register (symbolS *sym)
252b5132 1555{
4670103e
CZ		 1556 if (sym)
1557 {
1558 expressionS *ex = symbol_get_value_expression (sym);
252b5132 1559
4670103e
CZ		 1560 return ((O_register == ex->X_op)
1561 && !contains_register (ex->X_add_symbol)
1562 && !contains_register (ex->X_op_symbol));
1563 }
1564
1565 return FALSE;
252b5132
RH		 1566}
1567
4670103e 1568/* Returns the register number within a symbol. */
252b5132 1569
4670103e
CZ		 1570static int
1571get_register (symbolS *sym)
252b5132 1572{
4670103e
CZ		 1573 if (!contains_register (sym))
1574 return -1;
0d2bcfaf 1575
4670103e
CZ		 1576 expressionS *ex = symbol_get_value_expression (sym);
1577 return regno (ex->X_add_number);
1578}
252b5132 1579
4670103e
CZ		 1580/* Return true if a RELOC is generic. A generic reloc is PC-rel of a
1581 simple ME relocation (e.g. RELOC_ARC_32_ME, BFD_RELOC_ARC_PC32. */
f17c130b 1582
4670103e
CZ		 1583static bfd_boolean
1584generic_reloc_p (extended_bfd_reloc_code_real_type reloc)
1585{
1586 if (!reloc)
1587 return FALSE;
886a2506 1588
4670103e
CZ		 1589 switch (reloc)
1590 {
1591 case BFD_RELOC_ARC_SDA_LDST:
1592 case BFD_RELOC_ARC_SDA_LDST1:
1593 case BFD_RELOC_ARC_SDA_LDST2:
1594 case BFD_RELOC_ARC_SDA16_LD:
1595 case BFD_RELOC_ARC_SDA16_LD1:
1596 case BFD_RELOC_ARC_SDA16_LD2:
1597 case BFD_RELOC_ARC_SDA16_ST2:
1598 case BFD_RELOC_ARC_SDA32_ME:
1599 return FALSE;
1600 default:
1601 return TRUE;
f17c130b 1602 }
252b5132
RH		 1603}
1604
4670103e 1605/* Allocates a tok entry. */
252b5132 1606
4670103e
CZ		 1607static int
1608allocate_tok (expressionS *tok, int ntok, int cidx)
252b5132 1609{
4670103e
CZ		 1610 if (ntok > MAX_INSN_ARGS - 2)
1611 return 0; /* No space left. */
252b5132 1612
4670103e 1613 if (cidx > ntok)
33eaf5de 1614 return 0; /* Incorrect args. */
252b5132 1615
4670103e 1616 memcpy (&tok[ntok+1], &tok[ntok], sizeof (*tok));
252b5132 1617
4670103e
CZ		 1618 if (cidx == ntok)
1619 return 1; /* Success. */
1620 return allocate_tok (tok, ntok - 1, cidx);
1621}
886a2506 1622
8ddf6b2a
CZ		 1623/* Check if an particular ARC feature is enabled. */
1624
1625static bfd_boolean
1626check_cpu_feature (insn_subclass_t sc)
1627{
53a346d8 1628 if (is_code_density_p (sc) && !(selected_cpu.features & CD))
8ddf6b2a
CZ		 1629 return FALSE;
1630
53a346d8 1631 if (is_spfp_p (sc) && !(selected_cpu.features & SPX))
8ddf6b2a
CZ		 1632 return FALSE;
1633
53a346d8 1634 if (is_dpfp_p (sc) && !(selected_cpu.features & DPX))
8ddf6b2a
CZ		 1635 return FALSE;
1636
53a346d8 1637 if (is_fpuda_p (sc) && !(selected_cpu.features & DPA))
bdd582db
GM		 1638 return FALSE;
1639
53a346d8 1640 if (is_nps400_p (sc) && !(selected_cpu.features & NPS400))
8ddf6b2a
CZ		 1641 return FALSE;
1642
1643 return TRUE;
1644}
1645
4eb6f892
AB		 1646/* Parse the flags described by FIRST_PFLAG and NFLGS against the flag
1647 operands in OPCODE. Stores the matching OPCODES into the FIRST_PFLAG
1648 array and returns TRUE if the flag operands all match, otherwise,
1649 returns FALSE, in which case the FIRST_PFLAG array may have been
1650 modified. */
1651
1652static bfd_boolean
1653parse_opcode_flags (const struct arc_opcode *opcode,
1654 int nflgs,
1655 struct arc_flags *first_pflag)
1656{
1657 int lnflg, i;
1658 const unsigned char *flgidx;
1659
1660 lnflg = nflgs;
1661 for (i = 0; i < nflgs; i++)
1662 first_pflag[i].flgp = NULL;
1663
1664 /* Check the flags. Iterate over the valid flag classes. */
1665 for (flgidx = opcode->flags; *flgidx; ++flgidx)
1666 {
1667 /* Get a valid flag class. */
1668 const struct arc_flag_class *cl_flags = &arc_flag_classes[*flgidx];
1669 const unsigned *flgopridx;
1670 int cl_matches = 0;
1671 struct arc_flags *pflag = NULL;
1672
6ec7c1ae
CZ		 1673 /* Check if opcode has implicit flag classes. */
1674 if (cl_flags->flag_class & F_CLASS_IMPLICIT)
1675 continue;
1676
4eb6f892
AB		 1677 /* Check for extension conditional codes. */
1678 if (ext_condcode.arc_ext_condcode
1679 && cl_flags->flag_class & F_CLASS_EXTEND)
1680 {
1681 struct arc_flag_operand *pf = ext_condcode.arc_ext_condcode;
1682 while (pf->name)
1683 {
1684 pflag = first_pflag;
1685 for (i = 0; i < nflgs; i++, pflag++)
1686 {
1687 if (!strcmp (pf->name, pflag->name))
1688 {
1689 if (pflag->flgp != NULL)
1690 return FALSE;
1691 /* Found it. */
1692 cl_matches++;
1693 pflag->flgp = pf;
1694 lnflg--;
1695 break;
1696 }
1697 }
1698 pf++;
1699 }
1700 }
1701
1702 for (flgopridx = cl_flags->flags; *flgopridx; ++flgopridx)
1703 {
1704 const struct arc_flag_operand *flg_operand;
1705
1706 pflag = first_pflag;
1707 flg_operand = &arc_flag_operands[*flgopridx];
1708 for (i = 0; i < nflgs; i++, pflag++)
1709 {
1710 /* Match against the parsed flags. */
1711 if (!strcmp (flg_operand->name, pflag->name))
1712 {
1713 if (pflag->flgp != NULL)
1714 return FALSE;
1715 cl_matches++;
1716 pflag->flgp = flg_operand;
1717 lnflg--;
1718 break; /* goto next flag class and parsed flag. */
1719 }
1720 }
1721 }
1722
1723 if ((cl_flags->flag_class & F_CLASS_REQUIRED) && cl_matches == 0)
1724 return FALSE;
1725 if ((cl_flags->flag_class & F_CLASS_OPTIONAL) && cl_matches > 1)
1726 return FALSE;
1727 }
1728
1729 /* Did I check all the parsed flags? */
1730 return lnflg ? FALSE : TRUE;
1731}
1732
1733
4670103e
CZ		 1734/* Search forward through all variants of an opcode looking for a
1735 syntax match. */
886a2506 1736
4670103e 1737static const struct arc_opcode *
b9b47ab7 1738find_opcode_match (const struct arc_opcode_hash_entry *entry,
4670103e
CZ		 1739 expressionS *tok,
1740 int *pntok,
1741 struct arc_flags *first_pflag,
1742 int nflgs,
abe7c33b
CZ		 1743 int *pcpumatch,
1744 const char **errmsg)
4670103e 1745{
1328504b
AB		 1746 const struct arc_opcode *opcode;
1747 struct arc_opcode_hash_entry_iterator iter;
4670103e
CZ		 1748 int ntok = *pntok;
1749 int got_cpu_match = 0;
1750 expressionS bktok[MAX_INSN_ARGS];
1751 int bkntok;
1752 expressionS emptyE;
886a2506 1753
1328504b 1754 arc_opcode_hash_entry_iterator_init (&iter);
4670103e
CZ		 1755 memset (&emptyE, 0, sizeof (emptyE));
1756 memcpy (bktok, tok, MAX_INSN_ARGS * sizeof (*tok));
1757 bkntok = ntok;
a161fe53 1758
1328504b
AB		 1759 for (opcode = arc_opcode_hash_entry_iterator_next (entry, &iter);
1760 opcode != NULL;
1761 opcode = arc_opcode_hash_entry_iterator_next (entry, &iter))
252b5132 1762 {
4670103e 1763 const unsigned char *opidx;
4eb6f892 1764 int tokidx = 0;
4670103e 1765 const expressionS *t = &emptyE;
252b5132 1766
bdfe53e3 1767 pr_debug ("%s:%d: find_opcode_match: trying opcode 0x%08llX ",
4670103e 1768 frag_now->fr_file, frag_now->fr_line, opcode->opcode);
886a2506 1769
4670103e
CZ		 1770 /* Don't match opcodes that don't exist on this
1771 architecture. */
bb65a718 1772 if (!(opcode->cpu & selected_cpu.flags))
4670103e 1773 goto match_failed;
886a2506 1774
8ddf6b2a 1775 if (!check_cpu_feature (opcode->subclass))
4670103e 1776 goto match_failed;
886a2506 1777
4670103e
CZ		 1778 got_cpu_match = 1;
1779 pr_debug ("cpu ");
886a2506 1780
4670103e
CZ		 1781 /* Check the operands. */
1782 for (opidx = opcode->operands; *opidx; ++opidx)
252b5132 1783 {
4670103e 1784 const struct arc_operand *operand = &arc_operands[*opidx];
252b5132 1785
4670103e 1786 /* Only take input from real operands. */
db18dbab 1787 if (ARC_OPERAND_IS_FAKE (operand))
4670103e 1788 continue;
252b5132 1789
4670103e
CZ		 1790 /* When we expect input, make sure we have it. */
1791 if (tokidx >= ntok)
1792 goto match_failed;
6f4b1afc 1793
4670103e
CZ		 1794 /* Match operand type with expression type. */
1795 switch (operand->flags & ARC_OPERAND_TYPECHECK_MASK)
1796 {
db18dbab 1797 case ARC_OPERAND_ADDRTYPE:
b437d035 1798 {
abe7c33b 1799 *errmsg = NULL;
b437d035
AB		 1800
1801 /* Check to be an address type. */
1802 if (tok[tokidx].X_op != O_addrtype)
1803 goto match_failed;
1804
1805 /* All address type operands need to have an insert
1806 method in order to check that we have the correct
1807 address type. */
1808 gas_assert (operand->insert != NULL);
1809 (*operand->insert) (0, tok[tokidx].X_add_number,
abe7c33b
CZ		 1810 errmsg);
1811 if (*errmsg != NULL)
b437d035
AB		 1812 goto match_failed;
1813 }
db18dbab
GM		 1814 break;
1815
4670103e
CZ		 1816 case ARC_OPERAND_IR:
1817 /* Check to be a register. */
1818 if ((tok[tokidx].X_op != O_register
1819 || !is_ir_num (tok[tokidx].X_add_number))
1820 && !(operand->flags & ARC_OPERAND_IGNORE))
1821 goto match_failed;
1822
1823 /* If expect duplicate, make sure it is duplicate. */
1824 if (operand->flags & ARC_OPERAND_DUPLICATE)
1825 {
1826 /* Check for duplicate. */
1827 if (t->X_op != O_register
1828 || !is_ir_num (t->X_add_number)
1829 || (regno (t->X_add_number) !=
1830 regno (tok[tokidx].X_add_number)))
1831 goto match_failed;
1832 }
1833
1834 /* Special handling? */
1835 if (operand->insert)
1836 {
abe7c33b 1837 *errmsg = NULL;
4670103e
CZ		 1838 (*operand->insert)(0,
1839 regno (tok[tokidx].X_add_number),
abe7c33b
CZ		 1840 errmsg);
1841 if (*errmsg)
4670103e
CZ		 1842 {
1843 if (operand->flags & ARC_OPERAND_IGNORE)
1844 {
1845 /* Missing argument, create one. */
1846 if (!allocate_tok (tok, ntok - 1, tokidx))
1847 goto match_failed;
1848
1849 tok[tokidx].X_op = O_absent;
1850 ++ntok;
1851 }
1852 else
1853 goto match_failed;
1854 }
1855 }
1856
1857 t = &tok[tokidx];
1858 break;
1859
1860 case ARC_OPERAND_BRAKET:
1861 /* Check if bracket is also in opcode table as
1862 operand. */
1863 if (tok[tokidx].X_op != O_bracket)
1864 goto match_failed;
1865 break;
1866
db18dbab
GM		 1867 case ARC_OPERAND_COLON:
1868 /* Check if colon is also in opcode table as operand. */
1869 if (tok[tokidx].X_op != O_colon)
1870 goto match_failed;
1871 break;
1872
4670103e
CZ		 1873 case ARC_OPERAND_LIMM:
1874 case ARC_OPERAND_SIGNED:
1875 case ARC_OPERAND_UNSIGNED:
1876 switch (tok[tokidx].X_op)
1877 {
1878 case O_illegal:
1879 case O_absent:
1880 case O_register:
1881 goto match_failed;
1882
1883 case O_bracket:
1884 /* Got an (too) early bracket, check if it is an
1885 ignored operand. N.B. This procedure works only
1886 when bracket is the last operand! */
1887 if (!(operand->flags & ARC_OPERAND_IGNORE))
1888 goto match_failed;
1889 /* Insert the missing operand. */
1890 if (!allocate_tok (tok, ntok - 1, tokidx))
1891 goto match_failed;
1892
1893 tok[tokidx].X_op = O_absent;
1894 ++ntok;
1895 break;
1896
22b92fc4
AB		 1897 case O_symbol:
1898 {
1899 const char *p;
b6523c37 1900 char *tmpp, *pp;
22b92fc4 1901 const struct arc_aux_reg *auxr;
22b92fc4 1902
c810e0b8 1903 if (opcode->insn_class != AUXREG)
22b92fc4
AB		 1904 goto de_fault;
1905 p = S_GET_NAME (tok[tokidx].X_add_symbol);
f36e33da 1906
b6523c37 1907 /* For compatibility reasons, an aux register can
1908 be spelled with upper or lower case
1909 letters. */
1910 tmpp = strdup (p);
1911 for (pp = tmpp; *pp; ++pp) *pp = TOLOWER (*pp);
1912
1913 auxr = hash_find (arc_aux_hash, tmpp);
f36e33da
CZ		 1914 if (auxr)
1915 {
1916 /* We modify the token array here, safe in the
1917 knowledge, that if this was the wrong
1918 choice then the original contents will be
1919 restored from BKTOK. */
1920 tok[tokidx].X_op = O_constant;
1921 tok[tokidx].X_add_number = auxr->address;
1922 ARC_SET_FLAG (tok[tokidx].X_add_symbol, ARC_FLAG_AUX);
1923 }
b6523c37 1924 free (tmpp);
22b92fc4
AB		 1925
1926 if (tok[tokidx].X_op != O_constant)
1927 goto de_fault;
1928 }
1a0670f3 1929 /* Fall through. */
4670103e
CZ		 1930 case O_constant:
1931 /* Check the range. */
1932 if (operand->bits != 32
1933 && !(operand->flags & ARC_OPERAND_NCHK))
1934 {
1935 offsetT min, max, val;
1936 val = tok[tokidx].X_add_number;
1937
1938 if (operand->flags & ARC_OPERAND_SIGNED)
1939 {
1940 max = (1 << (operand->bits - 1)) - 1;
1941 min = -(1 << (operand->bits - 1));
1942 }
1943 else
1944 {
1945 max = (1 << operand->bits) - 1;
1946 min = 0;
1947 }
1948
1949 if (val < min || val > max)
1950 goto match_failed;
1951
33eaf5de 1952 /* Check alignments. */
4670103e
CZ		 1953 if ((operand->flags & ARC_OPERAND_ALIGNED32)
1954 && (val & 0x03))
1955 goto match_failed;
1956
1957 if ((operand->flags & ARC_OPERAND_ALIGNED16)
1958 && (val & 0x01))
1959 goto match_failed;
1960 }
1961 else if (operand->flags & ARC_OPERAND_NCHK)
1962 {
1963 if (operand->insert)
1964 {
abe7c33b 1965 *errmsg = NULL;
4670103e
CZ		 1966 (*operand->insert)(0,
1967 tok[tokidx].X_add_number,
abe7c33b
CZ		 1968 errmsg);
1969 if (*errmsg)
4670103e
CZ		 1970 goto match_failed;
1971 }
4eb6f892 1972 else if (!(operand->flags & ARC_OPERAND_IGNORE))
4670103e
CZ		 1973 goto match_failed;
1974 }
1975 break;
1976
1977 case O_subtract:
1978 /* Check if it is register range. */
1979 if ((tok[tokidx].X_add_number == 0)
1980 && contains_register (tok[tokidx].X_add_symbol)
1981 && contains_register (tok[tokidx].X_op_symbol))
1982 {
1983 int regs;
1984
1985 regs = get_register (tok[tokidx].X_add_symbol);
1986 regs <<= 16;
1987 regs |= get_register (tok[tokidx].X_op_symbol);
1988 if (operand->insert)
1989 {
abe7c33b 1990 *errmsg = NULL;
4670103e
CZ		 1991 (*operand->insert)(0,
1992 regs,
abe7c33b
CZ		 1993 errmsg);
1994 if (*errmsg)
4670103e
CZ		 1995 goto match_failed;
1996 }
1997 else
1998 goto match_failed;
1999 break;
2000 }
1a0670f3 2001 /* Fall through. */
4670103e 2002 default:
22b92fc4 2003 de_fault:
4670103e
CZ		 2004 if (operand->default_reloc == 0)
2005 goto match_failed; /* The operand needs relocation. */
2006
2007 /* Relocs requiring long immediate. FIXME! make it
2008 generic and move it to a function. */
2009 switch (tok[tokidx].X_md)
2010 {
2011 case O_gotoff:
2012 case O_gotpc:
2013 case O_pcl:
2014 case O_tpoff:
2015 case O_dtpoff:
2016 case O_tlsgd:
2017 case O_tlsie:
2018 if (!(operand->flags & ARC_OPERAND_LIMM))
2019 goto match_failed;
1a0670f3 2020 /* Fall through. */
4670103e
CZ		 2021 case O_absent:
2022 if (!generic_reloc_p (operand->default_reloc))
2023 goto match_failed;
2b804145 2024 break;
4670103e
CZ		 2025 default:
2026 break;
2027 }
2028 break;
2029 }
2030 /* If expect duplicate, make sure it is duplicate. */
2031 if (operand->flags & ARC_OPERAND_DUPLICATE)
2032 {
2033 if (t->X_op == O_illegal
2034 || t->X_op == O_absent
2035 || t->X_op == O_register
2036 || (t->X_add_number != tok[tokidx].X_add_number))
2037 goto match_failed;
2038 }
2039 t = &tok[tokidx];
2040 break;
2041
2042 default:
2043 /* Everything else should have been fake. */
2044 abort ();
2045 }
2046
2047 ++tokidx;
2048 }
2049 pr_debug ("opr ");
2050
1ae8ab47 2051 /* Setup ready for flag parsing. */
4eb6f892 2052 if (!parse_opcode_flags (opcode, nflgs, first_pflag))
4670103e
CZ		 2053 goto match_failed;
2054
2055 pr_debug ("flg");
2056 /* Possible match -- did we use all of our input? */
2057 if (tokidx == ntok)
2058 {
2059 *pntok = ntok;
2060 pr_debug ("\n");
2061 return opcode;
2062 }
2063
2064 match_failed:;
2065 pr_debug ("\n");
2066 /* Restore the original parameters. */
2067 memcpy (tok, bktok, MAX_INSN_ARGS * sizeof (*tok));
2068 ntok = bkntok;
2069 }
4670103e
CZ		 2070
2071 if (*pcpumatch)
2072 *pcpumatch = got_cpu_match;
2073
2074 return NULL;
2075}
2076
2077/* Swap operand tokens. */
2078
2079static void
2080swap_operand (expressionS *operand_array,
2081 unsigned source,
2082 unsigned destination)
2083{
2084 expressionS cpy_operand;
2085 expressionS *src_operand;
2086 expressionS *dst_operand;
2087 size_t size;
2088
2089 if (source == destination)
2090 return;
2091
2092 src_operand = &operand_array[source];
2093 dst_operand = &operand_array[destination];
2094 size = sizeof (expressionS);
2095
2096 /* Make copy of operand to swap with and swap. */
2097 memcpy (&cpy_operand, dst_operand, size);
2098 memcpy (dst_operand, src_operand, size);
2099 memcpy (src_operand, &cpy_operand, size);
2100}
2101
2102/* Check if *op matches *tok type.
2103 Returns FALSE if they don't match, TRUE if they match. */
2104
2105static bfd_boolean
2106pseudo_operand_match (const expressionS *tok,
2107 const struct arc_operand_operation *op)
2108{
2109 offsetT min, max, val;
2110 bfd_boolean ret;
2111 const struct arc_operand *operand_real = &arc_operands[op->operand_idx];
2112
2113 ret = FALSE;
2114 switch (tok->X_op)
2115 {
2116 case O_constant:
2117 if (operand_real->bits == 32 && (operand_real->flags & ARC_OPERAND_LIMM))
2118 ret = 1;
2119 else if (!(operand_real->flags & ARC_OPERAND_IR))
2120 {
2121 val = tok->X_add_number + op->count;
2122 if (operand_real->flags & ARC_OPERAND_SIGNED)
2123 {
2124 max = (1 << (operand_real->bits - 1)) - 1;
2125 min = -(1 << (operand_real->bits - 1));
2126 }
2127 else
2128 {
2129 max = (1 << operand_real->bits) - 1;
2130 min = 0;
2131 }
2132 if (min <= val && val <= max)
2133 ret = TRUE;
2134 }
6f4b1afc
CM		 2135 break;
2136
4670103e
CZ		 2137 case O_symbol:
2138 /* Handle all symbols as long immediates or signed 9. */
db18dbab
GM		 2139 if (operand_real->flags & ARC_OPERAND_LIMM
2140 || ((operand_real->flags & ARC_OPERAND_SIGNED)
2141 && operand_real->bits == 9))
4670103e 2142 ret = TRUE;
6f4b1afc
CM		 2143 break;
2144
4670103e
CZ		 2145 case O_register:
2146 if (operand_real->flags & ARC_OPERAND_IR)
2147 ret = TRUE;
2148 break;
2149
2150 case O_bracket:
2151 if (operand_real->flags & ARC_OPERAND_BRAKET)
2152 ret = TRUE;
6f4b1afc
CM		 2153 break;
2154
2155 default:
4670103e 2156 /* Unknown. */
6f4b1afc
CM		 2157 break;
2158 }
4670103e
CZ		 2159 return ret;
2160}
6f4b1afc 2161
4670103e
CZ		 2162/* Find pseudo instruction in array. */
2163
2164static const struct arc_pseudo_insn *
2165find_pseudo_insn (const char *opname,
2166 int ntok,
2167 const expressionS *tok)
2168{
2169 const struct arc_pseudo_insn *pseudo_insn = NULL;
2170 const struct arc_operand_operation *op;
2171 unsigned int i;
2172 int j;
2173
2174 for (i = 0; i < arc_num_pseudo_insn; ++i)
6f4b1afc 2175 {
4670103e
CZ		 2176 pseudo_insn = &arc_pseudo_insns[i];
2177 if (strcmp (pseudo_insn->mnemonic_p, opname) == 0)
2178 {
2179 op = pseudo_insn->operand;
2180 for (j = 0; j < ntok; ++j)
2181 if (!pseudo_operand_match (&tok[j], &op[j]))
2182 break;
2183
2184 /* Found the right instruction. */
2185 if (j == ntok)
2186 return pseudo_insn;
2187 }
6f4b1afc 2188 }
4670103e
CZ		 2189 return NULL;
2190}
252b5132 2191
4670103e 2192/* Assumes the expressionS *tok is of sufficient size. */
252b5132 2193
b9b47ab7 2194static const struct arc_opcode_hash_entry *
4670103e
CZ		 2195find_special_case_pseudo (const char *opname,
2196 int *ntok,
2197 expressionS *tok,
2198 int *nflgs,
2199 struct arc_flags *pflags)
2200{
2201 const struct arc_pseudo_insn *pseudo_insn = NULL;
2202 const struct arc_operand_operation *operand_pseudo;
2203 const struct arc_operand *operand_real;
2204 unsigned i;
2205 char construct_operand[MAX_CONSTR_STR];
886a2506 2206
4670103e
CZ		 2207 /* Find whether opname is in pseudo instruction array. */
2208 pseudo_insn = find_pseudo_insn (opname, *ntok, tok);
2209
2210 if (pseudo_insn == NULL)
2211 return NULL;
2212
2213 /* Handle flag, Limited to one flag at the moment. */
2214 if (pseudo_insn->flag_r != NULL)
2215 *nflgs += tokenize_flags (pseudo_insn->flag_r, &pflags[*nflgs],
2216 MAX_INSN_FLGS - *nflgs);
2217
2218 /* Handle operand operations. */
2219 for (i = 0; i < pseudo_insn->operand_cnt; ++i)
252b5132 2220 {
4670103e
CZ		 2221 operand_pseudo = &pseudo_insn->operand[i];
2222 operand_real = &arc_operands[operand_pseudo->operand_idx];
886a2506 2223
db18dbab
GM		 2224 if (operand_real->flags & ARC_OPERAND_BRAKET
2225 && !operand_pseudo->needs_insert)
4670103e 2226 continue;
b125bd17 2227
4670103e
CZ		 2228 /* Has to be inserted (i.e. this token does not exist yet). */
2229 if (operand_pseudo->needs_insert)
2230 {
2231 if (operand_real->flags & ARC_OPERAND_BRAKET)
2232 {
2233 tok[i].X_op = O_bracket;
2234 ++(*ntok);
2235 continue;
2236 }
b125bd17 2237
4670103e
CZ		 2238 /* Check if operand is a register or constant and handle it
2239 by type. */
2240 if (operand_real->flags & ARC_OPERAND_IR)
2241 snprintf (construct_operand, MAX_CONSTR_STR, "r%d",
2242 operand_pseudo->count);
2243 else
2244 snprintf (construct_operand, MAX_CONSTR_STR, "%d",
2245 operand_pseudo->count);
886a2506 2246
4670103e
CZ		 2247 tokenize_arguments (construct_operand, &tok[i], 1);
2248 ++(*ntok);
2249 }
2250
2251 else if (operand_pseudo->count)
2252 {
2253 /* Operand number has to be adjusted accordingly (by operand
2254 type). */
2255 switch (tok[i].X_op)
2256 {
2257 case O_constant:
2258 tok[i].X_add_number += operand_pseudo->count;
2259 break;
2260
2261 case O_symbol:
2262 break;
2263
2264 default:
2265 /* Ignored. */
2266 break;
2267 }
2268 }
2269 }
2270
2271 /* Swap operands if necessary. Only supports one swap at the
2272 moment. */
2273 for (i = 0; i < pseudo_insn->operand_cnt; ++i)
2274 {
2275 operand_pseudo = &pseudo_insn->operand[i];
2276
2277 if (operand_pseudo->swap_operand_idx == i)
2278 continue;
2279
2280 swap_operand (tok, i, operand_pseudo->swap_operand_idx);
2281
2282 /* Prevent a swap back later by breaking out. */
2283 break;
2284 }
2285
da5be039 2286 return arc_find_opcode (pseudo_insn->mnemonic_r);
4670103e
CZ		 2287}
2288
b9b47ab7 2289static const struct arc_opcode_hash_entry *
4670103e
CZ		 2290find_special_case_flag (const char *opname,
2291 int *nflgs,
2292 struct arc_flags *pflags)
2293{
2294 unsigned int i;
2295 const char *flagnm;
2296 unsigned flag_idx, flag_arr_idx;
2297 size_t flaglen, oplen;
2298 const struct arc_flag_special *arc_flag_special_opcode;
b9b47ab7 2299 const struct arc_opcode_hash_entry *entry;
4670103e
CZ		 2300
2301 /* Search for special case instruction. */
2302 for (i = 0; i < arc_num_flag_special; i++)
2303 {
2304 arc_flag_special_opcode = &arc_flag_special_cases[i];
2305 oplen = strlen (arc_flag_special_opcode->name);
2306
2307 if (strncmp (opname, arc_flag_special_opcode->name, oplen) != 0)
2308 continue;
2309
2310 /* Found a potential special case instruction, now test for
2311 flags. */
2312 for (flag_arr_idx = 0;; ++flag_arr_idx)
2313 {
2314 flag_idx = arc_flag_special_opcode->flags[flag_arr_idx];
2315 if (flag_idx == 0)
2316 break; /* End of array, nothing found. */
886a2506 2317
4670103e
CZ		 2318 flagnm = arc_flag_operands[flag_idx].name;
2319 flaglen = strlen (flagnm);
2320 if (strcmp (opname + oplen, flagnm) == 0)
2321 {
b9b47ab7 2322 entry = arc_find_opcode (arc_flag_special_opcode->name);
886a2506 2323
4670103e
CZ		 2324 if (*nflgs + 1 > MAX_INSN_FLGS)
2325 break;
2326 memcpy (pflags[*nflgs].name, flagnm, flaglen);
2327 pflags[*nflgs].name[flaglen] = '\0';
2328 (*nflgs)++;
b9b47ab7 2329 return entry;
4670103e
CZ		 2330 }
2331 }
2332 }
2333 return NULL;
2334}
886a2506 2335
4670103e 2336/* Used to find special case opcode. */
886a2506 2337
b9b47ab7 2338static const struct arc_opcode_hash_entry *
4670103e
CZ		 2339find_special_case (const char *opname,
2340 int *nflgs,
2341 struct arc_flags *pflags,
2342 expressionS *tok,
2343 int *ntok)
2344{
b9b47ab7 2345 const struct arc_opcode_hash_entry *entry;
886a2506 2346
b9b47ab7 2347 entry = find_special_case_pseudo (opname, ntok, tok, nflgs, pflags);
886a2506 2348
b9b47ab7
AB		 2349 if (entry == NULL)
2350 entry = find_special_case_flag (opname, nflgs, pflags);
886a2506 2351
b9b47ab7 2352 return entry;
4670103e 2353}
886a2506 2354
53a346d8
CZ		 2355/* Autodetect cpu attribute list. */
2356
2357static void
2358autodetect_attributes (const struct arc_opcode *opcode,
2359 const expressionS *tok,
2360 int ntok)
2361{
2362 unsigned i;
2363 struct mpy_type
2364 {
2365 unsigned feature;
2366 unsigned encoding;
2367 } mpy_list[] = {{ MPY1E, 1 }, { MPY6E, 6 }, { MPY7E, 7 }, { MPY8E, 8 },
2368 { MPY9E, 9 }};
2369
2370 for (i = 0; i < ARRAY_SIZE (feature_list); i++)
2371 if (opcode->subclass == feature_list[i].feature)
2372 selected_cpu.features |= feature_list[i].feature;
2373
2374 for (i = 0; i < ARRAY_SIZE (mpy_list); i++)
2375 if (opcode->subclass == mpy_list[i].feature)
2376 mpy_option = mpy_list[i].encoding;
2377
2378 for (i = 0; i < (unsigned) ntok; i++)
2379 {
2380 switch (tok[i].X_md)
2381 {
2382 case O_gotoff:
2383 case O_gotpc:
2384 case O_plt:
2385 pic_option = 2;
2386 break;
2387 case O_sda:
2388 sda_option = 2;
2389 break;
2390 case O_tlsgd:
2391 case O_tlsie:
2392 case O_tpoff9:
2393 case O_tpoff:
2394 case O_dtpoff9:
2395 case O_dtpoff:
2396 tls_option = 1;
2397 break;
2398 default:
2399 break;
2400 }
63741043 2401
2402 switch (tok[i].X_op)
2403 {
2404 case O_register:
2405 if ((tok[i].X_add_number >= 4 && tok[i].X_add_number <= 9)
2406 || (tok[i].X_add_number >= 16 && tok[i].X_add_number <= 25))
2407 rf16_only = FALSE;
2408 break;
2409 default:
2410 break;
2411 }
53a346d8
CZ		 2412 }
2413}
2414
2415/* Given an opcode name, pre-tockenized set of argumenst and the
4670103e 2416 opcode flags, take it all the way through emission. */
886a2506 2417
4670103e
CZ		 2418static void
2419assemble_tokens (const char *opname,
2420 expressionS *tok,
2421 int ntok,
2422 struct arc_flags *pflags,
2423 int nflgs)
2424{
2425 bfd_boolean found_something = FALSE;
b9b47ab7 2426 const struct arc_opcode_hash_entry *entry;
4670103e 2427 int cpumatch = 1;
abe7c33b 2428 const char *errmsg = NULL;
886a2506 2429
4670103e 2430 /* Search opcodes. */
b9b47ab7 2431 entry = arc_find_opcode (opname);
886a2506 2432
4670103e 2433 /* Couldn't find opcode conventional way, try special cases. */
b9b47ab7
AB		 2434 if (entry == NULL)
2435 entry = find_special_case (opname, &nflgs, pflags, tok, &ntok);
886a2506 2436
b9b47ab7 2437 if (entry != NULL)
4670103e 2438 {
b9b47ab7
AB		 2439 const struct arc_opcode *opcode;
2440
1328504b
AB		 2441 pr_debug ("%s:%d: assemble_tokens: %s\n",
2442 frag_now->fr_file, frag_now->fr_line, opname);
4670103e 2443 found_something = TRUE;
b9b47ab7 2444 opcode = find_opcode_match (entry, tok, &ntok, pflags,
abe7c33b 2445 nflgs, &cpumatch, &errmsg);
b9b47ab7 2446 if (opcode != NULL)
4670103e
CZ		 2447 {
2448 struct arc_insn insn;
b9b47ab7 2449
53a346d8 2450 autodetect_attributes (opcode, tok, ntok);
4670103e
CZ		 2451 assemble_insn (opcode, tok, ntok, pflags, nflgs, &insn);
2452 emit_insn (&insn);
2453 return;
2454 }
2455 }
886a2506 2456
4670103e
CZ		 2457 if (found_something)
2458 {
2459 if (cpumatch)
abe7c33b
CZ		 2460 if (errmsg)
2461 as_bad (_("%s for instruction '%s'"), errmsg, opname);
2462 else
2463 as_bad (_("inappropriate arguments for opcode '%s'"), opname);
4670103e
CZ		 2464 else
2465 as_bad (_("opcode '%s' not supported for target %s"), opname,
bb65a718 2466 selected_cpu.name);
4670103e
CZ		 2467 }
2468 else
2469 as_bad (_("unknown opcode '%s'"), opname);
886a2506
NC		 2470}
2471
4670103e 2472/* The public interface to the instruction assembler. */
886a2506 2473
4670103e
CZ		 2474void
2475md_assemble (char *str)
886a2506 2476{
4670103e
CZ		 2477 char *opname;
2478 expressionS tok[MAX_INSN_ARGS];
2479 int ntok, nflg;
2480 size_t opnamelen;
2481 struct arc_flags flags[MAX_INSN_FLGS];
886a2506 2482
4670103e
CZ		 2483 /* Split off the opcode. */
2484 opnamelen = strspn (str, "abcdefghijklmnopqrstuvwxyz_0123468");
29a2809e 2485 opname = xmemdup0 (str, opnamelen);
886a2506 2486
33eaf5de 2487 /* Signalize we are assembling the instructions. */
4670103e 2488 assembling_insn = TRUE;
886a2506 2489
4670103e
CZ		 2490 /* Tokenize the flags. */
2491 if ((nflg = tokenize_flags (str + opnamelen, flags, MAX_INSN_FLGS)) == -1)
2492 {
2493 as_bad (_("syntax error"));
2494 return;
2495 }
886a2506 2496
4670103e
CZ		 2497 /* Scan up to the end of the mnemonic which must end in space or end
2498 of string. */
2499 str += opnamelen;
2500 for (; *str != '\0'; str++)
2501 if (*str == ' ')
2502 break;
886a2506 2503
4670103e
CZ		 2504 /* Tokenize the rest of the line. */
2505 if ((ntok = tokenize_arguments (str, tok, MAX_INSN_ARGS)) < 0)
886a2506 2506 {
4670103e
CZ		 2507 as_bad (_("syntax error"));
2508 return;
252b5132
RH		 2509 }
2510
4670103e
CZ		 2511 /* Finish it off. */
2512 assemble_tokens (opname, tok, ntok, flags, nflg);
2513 assembling_insn = FALSE;
2514}
2515
2516/* Callback to insert a register into the hash table. */
2517
2518static void
f86f5863 2519declare_register (const char *name, int number)
4670103e
CZ		 2520{
2521 const char *err;
2522 symbolS *regS = symbol_create (name, reg_section,
2523 number, &zero_address_frag);
2524
2525 err = hash_insert (arc_reg_hash, S_GET_NAME (regS), (void *) regS);
2526 if (err)
e6ba1cba 2527 as_fatal (_("Inserting \"%s\" into register table failed: %s"),
4670103e
CZ		 2528 name, err);
2529}
252b5132 2530
4670103e 2531/* Construct symbols for each of the general registers. */
252b5132 2532
4670103e
CZ		 2533static void
2534declare_register_set (void)
2535{
2536 int i;
2537 for (i = 0; i < 64; ++i)
886a2506 2538 {
4670103e
CZ		 2539 char name[7];
2540
2541 sprintf (name, "r%d", i);
2542 declare_register (name, i);
2543 if ((i & 0x01) == 0)
886a2506 2544 {
4670103e
CZ		 2545 sprintf (name, "r%dr%d", i, i+1);
2546 declare_register (name, i);
886a2506
NC		 2547 }
2548 }
252b5132 2549}
ea1562b3 2550
db18dbab
GM		 2551/* Construct a symbol for an address type. */
2552
2553static void
2554declare_addrtype (const char *name, int number)
2555{
2556 const char *err;
2557 symbolS *addrtypeS = symbol_create (name, undefined_section,
2558 number, &zero_address_frag);
2559
2560 err = hash_insert (arc_addrtype_hash, S_GET_NAME (addrtypeS),
2561 (void *) addrtypeS);
2562 if (err)
2563 as_fatal (_("Inserting \"%s\" into address type table failed: %s"),
2564 name, err);
2565}
2566
4670103e
CZ		 2567/* Port-specific assembler initialization. This function is called
2568 once, at assembler startup time. */
ea1562b3
NC		 2569
2570void
4670103e 2571md_begin (void)
ea1562b3 2572{
b99747ae 2573 const struct arc_opcode *opcode = arc_opcodes;
886a2506 2574
bb65a718
AB		 2575 if (mach_selection_mode == MACH_SELECTION_NONE)
2576 arc_select_cpu (TARGET_WITH_CPU, MACH_SELECTION_FROM_DEFAULT);
24740d83 2577
4670103e
CZ		 2578 /* The endianness can be chosen "at the factory". */
2579 target_big_endian = byte_order == BIG_ENDIAN;
886a2506 2580
bb65a718 2581 if (!bfd_set_arch_mach (stdoutput, bfd_arch_arc, selected_cpu.mach))
4670103e
CZ		 2582 as_warn (_("could not set architecture and machine"));
2583
2584 /* Set elf header flags. */
bb65a718 2585 bfd_set_private_flags (stdoutput, selected_cpu.eflags);
4670103e
CZ		 2586
2587 /* Set up a hash table for the instructions. */
2588 arc_opcode_hash = hash_new ();
2589 if (arc_opcode_hash == NULL)
2590 as_fatal (_("Virtual memory exhausted"));
2591
2592 /* Initialize the hash table with the insns. */
b99747ae 2593 do
ea1562b3 2594 {
b99747ae 2595 const char *name = opcode->name;
da5be039 2596
b99747ae 2597 arc_insert_opcode (opcode);
4670103e 2598
b99747ae
CZ		 2599 while (++opcode && opcode->name
2600 && (opcode->name == name
2601 || !strcmp (opcode->name, name)))
4670103e 2602 continue;
b99747ae 2603 }while (opcode->name);
4670103e
CZ		 2604
2605 /* Register declaration. */
2606 arc_reg_hash = hash_new ();
2607 if (arc_reg_hash == NULL)
2608 as_fatal (_("Virtual memory exhausted"));
2609
2610 declare_register_set ();
2611 declare_register ("gp", 26);
2612 declare_register ("fp", 27);
2613 declare_register ("sp", 28);
2614 declare_register ("ilink", 29);
2615 declare_register ("ilink1", 29);
2616 declare_register ("ilink2", 30);
2617 declare_register ("blink", 31);
2618
87789e08
CZ		 2619 /* XY memory registers. */
2620 declare_register ("x0_u0", 32);
2621 declare_register ("x0_u1", 33);
2622 declare_register ("x1_u0", 34);
2623 declare_register ("x1_u1", 35);
2624 declare_register ("x2_u0", 36);
2625 declare_register ("x2_u1", 37);
2626 declare_register ("x3_u0", 38);
2627 declare_register ("x3_u1", 39);
2628 declare_register ("y0_u0", 40);
2629 declare_register ("y0_u1", 41);
2630 declare_register ("y1_u0", 42);
2631 declare_register ("y1_u1", 43);
2632 declare_register ("y2_u0", 44);
2633 declare_register ("y2_u1", 45);
2634 declare_register ("y3_u0", 46);
2635 declare_register ("y3_u1", 47);
2636 declare_register ("x0_nu", 48);
2637 declare_register ("x1_nu", 49);
2638 declare_register ("x2_nu", 50);
2639 declare_register ("x3_nu", 51);
2640 declare_register ("y0_nu", 52);
2641 declare_register ("y1_nu", 53);
2642 declare_register ("y2_nu", 54);
2643 declare_register ("y3_nu", 55);
2644
4670103e
CZ		 2645 declare_register ("mlo", 57);
2646 declare_register ("mmid", 58);
2647 declare_register ("mhi", 59);
2648
2649 declare_register ("acc1", 56);
2650 declare_register ("acc2", 57);
2651
2652 declare_register ("lp_count", 60);
2653 declare_register ("pcl", 63);
2654
2655 /* Initialize the last instructions. */
2656 memset (&arc_last_insns[0], 0, sizeof (arc_last_insns));
f36e33da
CZ		 2657
2658 /* Aux register declaration. */
2659 arc_aux_hash = hash_new ();
2660 if (arc_aux_hash == NULL)
2661 as_fatal (_("Virtual memory exhausted"));
2662
2663 const struct arc_aux_reg *auxr = &arc_aux_regs[0];
2664 unsigned int i;
2665 for (i = 0; i < arc_num_aux_regs; i++, auxr++)
2666 {
2667 const char *retval;
2668
bb65a718 2669 if (!(auxr->cpu & selected_cpu.flags))
f36e33da
CZ		 2670 continue;
2671
2672 if ((auxr->subclass != NONE)
2673 && !check_cpu_feature (auxr->subclass))
2674 continue;
2675
2676 retval = hash_insert (arc_aux_hash, auxr->name, (void *) auxr);
2677 if (retval)
2678 as_fatal (_("internal error: can't hash aux register '%s': %s"),
2679 auxr->name, retval);
2680 }
db18dbab
GM		 2681
2682 /* Address type declaration. */
2683 arc_addrtype_hash = hash_new ();
2684 if (arc_addrtype_hash == NULL)
2685 as_fatal (_("Virtual memory exhausted"));
2686
2687 declare_addrtype ("bd", ARC_NPS400_ADDRTYPE_BD);
2688 declare_addrtype ("jid", ARC_NPS400_ADDRTYPE_JID);
2689 declare_addrtype ("lbd", ARC_NPS400_ADDRTYPE_LBD);
2690 declare_addrtype ("mbd", ARC_NPS400_ADDRTYPE_MBD);
2691 declare_addrtype ("sd", ARC_NPS400_ADDRTYPE_SD);
2692 declare_addrtype ("sm", ARC_NPS400_ADDRTYPE_SM);
2693 declare_addrtype ("xa", ARC_NPS400_ADDRTYPE_XA);
2694 declare_addrtype ("xd", ARC_NPS400_ADDRTYPE_XD);
2695 declare_addrtype ("cd", ARC_NPS400_ADDRTYPE_CD);
2696 declare_addrtype ("cbd", ARC_NPS400_ADDRTYPE_CBD);
2697 declare_addrtype ("cjid", ARC_NPS400_ADDRTYPE_CJID);
2698 declare_addrtype ("clbd", ARC_NPS400_ADDRTYPE_CLBD);
2699 declare_addrtype ("cm", ARC_NPS400_ADDRTYPE_CM);
2700 declare_addrtype ("csd", ARC_NPS400_ADDRTYPE_CSD);
2701 declare_addrtype ("cxa", ARC_NPS400_ADDRTYPE_CXA);
2702 declare_addrtype ("cxd", ARC_NPS400_ADDRTYPE_CXD);
886a2506 2703}
ea1562b3 2704
4670103e
CZ		 2705/* Write a value out to the object file, using the appropriate
2706 endianness. */
ea1562b3 2707
4670103e
CZ		 2708void
2709md_number_to_chars (char *buf,
2710 valueT val,
2711 int n)
886a2506 2712{
4670103e
CZ		 2713 if (target_big_endian)
2714 number_to_chars_bigendian (buf, val, n);
2715 else
2716 number_to_chars_littleendian (buf, val, n);
886a2506 2717}
ea1562b3 2718
4670103e 2719/* Round up a section size to the appropriate boundary. */
ea1562b3 2720
4670103e
CZ		 2721valueT
2722md_section_align (segT segment,
2723 valueT size)
886a2506 2724{
fd361982 2725 int align = bfd_section_alignment (segment);
4670103e
CZ		 2726
2727 return ((size + (1 << align) - 1) & (-((valueT) 1 << align)));
886a2506 2728}
ea1562b3 2729
4670103e
CZ		 2730/* The location from which a PC relative jump should be calculated,
2731 given a PC relative reloc. */
ea1562b3 2732
4670103e
CZ		 2733long
2734md_pcrel_from_section (fixS *fixP,
2735 segT sec)
886a2506 2736{
4670103e 2737 offsetT base = fixP->fx_where + fixP->fx_frag->fr_address;
ea1562b3 2738
4670103e 2739 pr_debug ("pcrel_from_section, fx_offset = %d\n", (int) fixP->fx_offset);
ea1562b3 2740
4670103e
CZ		 2741 if (fixP->fx_addsy != (symbolS *) NULL
2742 && (!S_IS_DEFINED (fixP->fx_addsy)
2743 || S_GET_SEGMENT (fixP->fx_addsy) != sec))
2744 {
2745 pr_debug ("Unknown pcrel symbol: %s\n", S_GET_NAME (fixP->fx_addsy));
ea1562b3 2746
4670103e
CZ		 2747 /* The symbol is undefined (or is defined but not in this section).
2748 Let the linker figure it out. */
2749 return 0;
2750 }
2751
2752 if ((int) fixP->fx_r_type < 0)
886a2506 2753 {
4670103e
CZ		 2754 /* These are the "internal" relocations. Align them to
2755 32 bit boundary (PCL), for the moment. */
2756 base &= ~3;
886a2506 2757 }
4670103e
CZ		 2758 else
2759 {
2760 switch (fixP->fx_r_type)
2761 {
2762 case BFD_RELOC_ARC_PC32:
2763 /* The hardware calculates relative to the start of the
2764 insn, but this relocation is relative to location of the
2765 LIMM, compensate. The base always needs to be
2b0f3761 2766 subtracted by 4 as we do not support this type of PCrel
4670103e
CZ		 2767 relocation for short instructions. */
2768 base -= 4;
2769 /* Fall through. */
2770 case BFD_RELOC_ARC_PLT32:
2771 case BFD_RELOC_ARC_S25H_PCREL_PLT:
2772 case BFD_RELOC_ARC_S21H_PCREL_PLT:
2773 case BFD_RELOC_ARC_S25W_PCREL_PLT:
2774 case BFD_RELOC_ARC_S21W_PCREL_PLT:
2775
2776 case BFD_RELOC_ARC_S21H_PCREL:
2777 case BFD_RELOC_ARC_S25H_PCREL:
2778 case BFD_RELOC_ARC_S13_PCREL:
2779 case BFD_RELOC_ARC_S21W_PCREL:
2780 case BFD_RELOC_ARC_S25W_PCREL:
2781 base &= ~3;
2782 break;
2783 default:
2784 as_bad_where (fixP->fx_file, fixP->fx_line,
2785 _("unhandled reloc %s in md_pcrel_from_section"),
2786 bfd_get_reloc_code_name (fixP->fx_r_type));
2787 break;
2788 }
2789 }
2790
9e32d9ae
AB		 2791 pr_debug ("pcrel from %"BFD_VMA_FMT"x + %lx = %"BFD_VMA_FMT"x, "
2792 "symbol: %s (%"BFD_VMA_FMT"x)\n",
4670103e
CZ		 2793 fixP->fx_frag->fr_address, fixP->fx_where, base,
2794 fixP->fx_addsy ? S_GET_NAME (fixP->fx_addsy) : "(null)",
2795 fixP->fx_addsy ? S_GET_VALUE (fixP->fx_addsy) : 0);
2796
2797 return base;
886a2506 2798}
ea1562b3 2799
33eaf5de 2800/* Given a BFD relocation find the corresponding operand. */
ea1562b3 2801
4670103e
CZ		 2802static const struct arc_operand *
2803find_operand_for_reloc (extended_bfd_reloc_code_real_type reloc)
2804{
2805 unsigned i;
ea1562b3 2806
4670103e
CZ		 2807 for (i = 0; i < arc_num_operands; i++)
2808 if (arc_operands[i].default_reloc == reloc)
2809 return &arc_operands[i];
2810 return NULL;
2811}
ea1562b3 2812
4670103e 2813/* Insert an operand value into an instruction. */
ea1562b3 2814
bdfe53e3
AB		 2815static unsigned long long
2816insert_operand (unsigned long long insn,
4670103e 2817 const struct arc_operand *operand,
bdfe53e3 2818 long long val,
3b4dbbbf 2819 const char *file,
4670103e 2820 unsigned line)
886a2506 2821{
4670103e 2822 offsetT min = 0, max = 0;
ea1562b3 2823
4670103e
CZ		 2824 if (operand->bits != 32
2825 && !(operand->flags & ARC_OPERAND_NCHK)
2826 && !(operand->flags & ARC_OPERAND_FAKE))
886a2506 2827 {
4670103e
CZ		 2828 if (operand->flags & ARC_OPERAND_SIGNED)
2829 {
2830 max = (1 << (operand->bits - 1)) - 1;
2831 min = -(1 << (operand->bits - 1));
2832 }
2833 else
2834 {
2835 max = (1 << operand->bits) - 1;
2836 min = 0;
2837 }
886a2506 2838
4670103e
CZ		 2839 if (val < min || val > max)
2840 as_bad_value_out_of_range (_("operand"),
2841 val, min, max, file, line);
2842 }
ea1562b3 2843
cc07cda6 2844 pr_debug ("insert field: %ld <= %lld <= %ld in 0x%08llx\n",
4670103e 2845 min, val, max, insn);
ea1562b3 2846
4670103e
CZ		 2847 if ((operand->flags & ARC_OPERAND_ALIGNED32)
2848 && (val & 0x03))
2849 as_bad_where (file, line,
2850 _("Unaligned operand. Needs to be 32bit aligned"));
ea1562b3 2851
4670103e
CZ		 2852 if ((operand->flags & ARC_OPERAND_ALIGNED16)
2853 && (val & 0x01))
2854 as_bad_where (file, line,
2855 _("Unaligned operand. Needs to be 16bit aligned"));
ea1562b3 2856
4670103e
CZ		 2857 if (operand->insert)
2858 {
2859 const char *errmsg = NULL;
ea1562b3 2860
4670103e
CZ		 2861 insn = (*operand->insert) (insn, val, &errmsg);
2862 if (errmsg)
2863 as_warn_where (file, line, "%s", errmsg);
2864 }
2865 else
2866 {
2867 if (operand->flags & ARC_OPERAND_TRUNCATE)
2868 {
2869 if (operand->flags & ARC_OPERAND_ALIGNED32)
2870 val >>= 2;
2871 if (operand->flags & ARC_OPERAND_ALIGNED16)
2872 val >>= 1;
886a2506 2873 }
4670103e
CZ		 2874 insn |= ((val & ((1 << operand->bits) - 1)) << operand->shift);
2875 }
2876 return insn;
2877}
ea1562b3 2878
4670103e
CZ		 2879/* Apply a fixup to the object code. At this point all symbol values
2880 should be fully resolved, and we attempt to completely resolve the
2881 reloc. If we can not do that, we determine the correct reloc code
2882 and put it back in the fixup. To indicate that a fixup has been
2883 eliminated, set fixP->fx_done. */
ea1562b3 2884
4670103e
CZ		 2885void
2886md_apply_fix (fixS *fixP,
2887 valueT *valP,
2888 segT seg)
2889{
2890 char * const fixpos = fixP->fx_frag->fr_literal + fixP->fx_where;
2891 valueT value = *valP;
2892 unsigned insn = 0;
2893 symbolS *fx_addsy, *fx_subsy;
2894 offsetT fx_offset;
2895 segT add_symbol_segment = absolute_section;
2896 segT sub_symbol_segment = absolute_section;
2897 const struct arc_operand *operand = NULL;
2898 extended_bfd_reloc_code_real_type reloc;
886a2506 2899
4670103e
CZ		 2900 pr_debug ("%s:%u: apply_fix: r_type=%d (%s) value=0x%lX offset=0x%lX\n",
2901 fixP->fx_file, fixP->fx_line, fixP->fx_r_type,
2902 ((int) fixP->fx_r_type < 0) ? "Internal":
2903 bfd_get_reloc_code_name (fixP->fx_r_type), value,
2904 fixP->fx_offset);
886a2506 2905
4670103e
CZ		 2906 fx_addsy = fixP->fx_addsy;
2907 fx_subsy = fixP->fx_subsy;
2908 fx_offset = 0;
886a2506 2909
4670103e
CZ		 2910 if (fx_addsy)
2911 {
2912 add_symbol_segment = S_GET_SEGMENT (fx_addsy);
886a2506
NC		 2913 }
2914
4670103e
CZ		 2915 if (fx_subsy
2916 && fixP->fx_r_type != BFD_RELOC_ARC_TLS_DTPOFF
2917 && fixP->fx_r_type != BFD_RELOC_ARC_TLS_DTPOFF_S9
2918 && fixP->fx_r_type != BFD_RELOC_ARC_TLS_GD_LD)
2919 {
2920 resolve_symbol_value (fx_subsy);
2921 sub_symbol_segment = S_GET_SEGMENT (fx_subsy);
886a2506 2922
4670103e
CZ		 2923 if (sub_symbol_segment == absolute_section)
2924 {
2925 /* The symbol is really a constant. */
2926 fx_offset -= S_GET_VALUE (fx_subsy);
2927 fx_subsy = NULL;
2928 }
2929 else
2930 {
2931 as_bad_where (fixP->fx_file, fixP->fx_line,
2932 _("can't resolve `%s' {%s section} - `%s' {%s section}"),
2933 fx_addsy ? S_GET_NAME (fx_addsy) : "0",
2934 segment_name (add_symbol_segment),
2935 S_GET_NAME (fx_subsy),
2936 segment_name (sub_symbol_segment));
2937 return;
2938 }
2939 }
886a2506 2940
4670103e
CZ		 2941 if (fx_addsy
2942 && !S_IS_WEAK (fx_addsy))
2943 {
2944 if (add_symbol_segment == seg
2945 && fixP->fx_pcrel)
2946 {
2947 value += S_GET_VALUE (fx_addsy);
2948 value -= md_pcrel_from_section (fixP, seg);
2949 fx_addsy = NULL;
2950 fixP->fx_pcrel = FALSE;
2951 }
2952 else if (add_symbol_segment == absolute_section)
2953 {
2954 value = fixP->fx_offset;
2955 fx_offset += S_GET_VALUE (fixP->fx_addsy);
2956 fx_addsy = NULL;
2957 fixP->fx_pcrel = FALSE;
2958 }
2959 }
886a2506 2960
4670103e
CZ		 2961 if (!fx_addsy)
2962 fixP->fx_done = TRUE;
886a2506 2963
4670103e 2964 if (fixP->fx_pcrel)
886a2506 2965 {
4670103e
CZ		 2966 if (fx_addsy
2967 && ((S_IS_DEFINED (fx_addsy)
2968 && S_GET_SEGMENT (fx_addsy) != seg)
2969 || S_IS_WEAK (fx_addsy)))
2970 value += md_pcrel_from_section (fixP, seg);
886a2506 2971
4670103e
CZ		 2972 switch (fixP->fx_r_type)
2973 {
2974 case BFD_RELOC_ARC_32_ME:
2975 /* This is a pc-relative value in a LIMM. Adjust it to the
2976 address of the instruction not to the address of the
33eaf5de 2977 LIMM. Note: it is not any longer valid this affirmation as
4670103e
CZ		 2978 the linker consider ARC_PC32 a fixup to entire 64 bit
2979 insn. */
2980 fixP->fx_offset += fixP->fx_frag->fr_address;
2981 /* Fall through. */
2982 case BFD_RELOC_32:
2983 fixP->fx_r_type = BFD_RELOC_ARC_PC32;
2984 /* Fall through. */
2985 case BFD_RELOC_ARC_PC32:
2986 /* fixP->fx_offset += fixP->fx_where - fixP->fx_dot_value; */
886a2506
NC		 2987 break;
2988 default:
4670103e 2989 if ((int) fixP->fx_r_type < 0)
6e3f3473 2990 as_bad_where (fixP->fx_file, fixP->fx_line,
2991 _("PC relative relocation not allowed for (internal)"
2992 " type %d"),
2993 fixP->fx_r_type);
886a2506 2994 break;
ea1562b3
NC		 2995 }
2996 }
2997
4670103e
CZ		 2998 pr_debug ("%s:%u: apply_fix: r_type=%d (%s) value=0x%lX offset=0x%lX\n",
2999 fixP->fx_file, fixP->fx_line, fixP->fx_r_type,
3000 ((int) fixP->fx_r_type < 0) ? "Internal":
3001 bfd_get_reloc_code_name (fixP->fx_r_type), value,
3002 fixP->fx_offset);
886a2506 3003
886a2506 3004
4670103e
CZ		 3005 /* Now check for TLS relocations. */
3006 reloc = fixP->fx_r_type;
3007 switch (reloc)
886a2506 3008 {
4670103e
CZ		 3009 case BFD_RELOC_ARC_TLS_DTPOFF:
3010 case BFD_RELOC_ARC_TLS_LE_32:
3011 if (fixP->fx_done)
3012 break;
3013 /* Fall through. */
3014 case BFD_RELOC_ARC_TLS_GD_GOT:
3015 case BFD_RELOC_ARC_TLS_IE_GOT:
3016 S_SET_THREAD_LOCAL (fixP->fx_addsy);
3017 break;
886a2506 3018
4670103e
CZ		 3019 case BFD_RELOC_ARC_TLS_GD_LD:
3020 gas_assert (!fixP->fx_offset);
3021 if (fixP->fx_subsy)
3022 fixP->fx_offset
3023 = (S_GET_VALUE (fixP->fx_subsy)
3024 - fixP->fx_frag->fr_address- fixP->fx_where);
3025 fixP->fx_subsy = NULL;
3026 /* Fall through. */
3027 case BFD_RELOC_ARC_TLS_GD_CALL:
3028 /* These two relocs are there just to allow ld to change the tls
3029 model for this symbol, by patching the code. The offset -
3030 and scale, if any - will be installed by the linker. */
3031 S_SET_THREAD_LOCAL (fixP->fx_addsy);
3032 break;
886a2506 3033
4670103e
CZ		 3034 case BFD_RELOC_ARC_TLS_LE_S9:
3035 case BFD_RELOC_ARC_TLS_DTPOFF_S9:
3036 as_bad (_("TLS_*_S9 relocs are not supported yet"));
3037 break;
3038
3039 default:
3040 break;
886a2506
NC		 3041 }
3042
4670103e 3043 if (!fixP->fx_done)
886a2506 3044 {
4670103e 3045 return;
886a2506 3046 }
886a2506 3047
33eaf5de 3048 /* Adjust the value if we have a constant. */
4670103e 3049 value += fx_offset;
886a2506 3050
4670103e
CZ		 3051 /* For hosts with longs bigger than 32-bits make sure that the top
3052 bits of a 32-bit negative value read in by the parser are set,
3053 so that the correct comparisons are made. */
3054 if (value & 0x80000000)
69c9e028 3055 value |= (-1UL << 31);
886a2506 3056
4670103e
CZ		 3057 reloc = fixP->fx_r_type;
3058 switch (reloc)
3059 {
3060 case BFD_RELOC_8:
3061 case BFD_RELOC_16:
3062 case BFD_RELOC_24:
3063 case BFD_RELOC_32:
3064 case BFD_RELOC_64:
3065 case BFD_RELOC_ARC_32_PCREL:
3066 md_number_to_chars (fixpos, value, fixP->fx_size);
3067 return;
886a2506 3068
4670103e
CZ		 3069 case BFD_RELOC_ARC_GOTPC32:
3070 /* I cannot fix an GOTPC relocation because I need to relax it
3071 from ld rx,[pcl,@sym@gotpc] to add rx,pcl,@sym@gotpc. */
3072 as_bad (_("Unsupported operation on reloc"));
3073 return;
886a2506 3074
4670103e
CZ		 3075 case BFD_RELOC_ARC_TLS_DTPOFF:
3076 case BFD_RELOC_ARC_TLS_LE_32:
3077 gas_assert (!fixP->fx_addsy);
3078 gas_assert (!fixP->fx_subsy);
1a0670f3 3079 /* Fall through. */
886a2506 3080
4670103e
CZ		 3081 case BFD_RELOC_ARC_GOTOFF:
3082 case BFD_RELOC_ARC_32_ME:
3083 case BFD_RELOC_ARC_PC32:
3084 md_number_to_chars_midend (fixpos, value, fixP->fx_size);
3085 return;
886a2506 3086
4670103e
CZ		 3087 case BFD_RELOC_ARC_PLT32:
3088 md_number_to_chars_midend (fixpos, value, fixP->fx_size);
3089 return;
886a2506 3090
4670103e
CZ		 3091 case BFD_RELOC_ARC_S25H_PCREL_PLT:
3092 reloc = BFD_RELOC_ARC_S25W_PCREL;
3093 goto solve_plt;
886a2506 3094
4670103e
CZ		 3095 case BFD_RELOC_ARC_S21H_PCREL_PLT:
3096 reloc = BFD_RELOC_ARC_S21H_PCREL;
3097 goto solve_plt;
886a2506 3098
4670103e
CZ		 3099 case BFD_RELOC_ARC_S25W_PCREL_PLT:
3100 reloc = BFD_RELOC_ARC_S25W_PCREL;
3101 goto solve_plt;
886a2506 3102
4670103e
CZ		 3103 case BFD_RELOC_ARC_S21W_PCREL_PLT:
3104 reloc = BFD_RELOC_ARC_S21W_PCREL;
1a0670f3 3105 /* Fall through. */
886a2506 3106
4670103e
CZ		 3107 case BFD_RELOC_ARC_S25W_PCREL:
3108 case BFD_RELOC_ARC_S21W_PCREL:
3109 case BFD_RELOC_ARC_S21H_PCREL:
3110 case BFD_RELOC_ARC_S25H_PCREL:
3111 case BFD_RELOC_ARC_S13_PCREL:
3112 solve_plt:
3113 operand = find_operand_for_reloc (reloc);
3114 gas_assert (operand);
886a2506
NC		 3115 break;
3116
3117 default:
4670103e
CZ		 3118 {
3119 if ((int) fixP->fx_r_type >= 0)
3120 as_fatal (_("unhandled relocation type %s"),
3121 bfd_get_reloc_code_name (fixP->fx_r_type));
886a2506 3122
4670103e
CZ		 3123 /* The rest of these fixups needs to be completely resolved as
3124 constants. */
3125 if (fixP->fx_addsy != 0
3126 && S_GET_SEGMENT (fixP->fx_addsy) != absolute_section)
3127 as_bad_where (fixP->fx_file, fixP->fx_line,
3128 _("non-absolute expression in constant field"));
886a2506 3129
4670103e
CZ		 3130 gas_assert (-(int) fixP->fx_r_type < (int) arc_num_operands);
3131 operand = &arc_operands[-(int) fixP->fx_r_type];
3132 break;
3133 }
3134 }
886a2506 3135
4670103e 3136 if (target_big_endian)
886a2506 3137 {
4670103e 3138 switch (fixP->fx_size)
886a2506 3139 {
4670103e
CZ		 3140 case 4:
3141 insn = bfd_getb32 (fixpos);
3142 break;
3143 case 2:
3144 insn = bfd_getb16 (fixpos);
3145 break;
3146 default:
3147 as_bad_where (fixP->fx_file, fixP->fx_line,
3148 _("unknown fixup size"));
3149 }
3150 }
3151 else
3152 {
3153 insn = 0;
3154 switch (fixP->fx_size)
3155 {
3156 case 4:
3157 insn = bfd_getl16 (fixpos) << 16 | bfd_getl16 (fixpos + 2);
3158 break;
3159 case 2:
3160 insn = bfd_getl16 (fixpos);
3161 break;
3162 default:
3163 as_bad_where (fixP->fx_file, fixP->fx_line,
3164 _("unknown fixup size"));
886a2506
NC		 3165 }
3166 }
886a2506 3167
4670103e
CZ		 3168 insn = insert_operand (insn, operand, (offsetT) value,
3169 fixP->fx_file, fixP->fx_line);
886a2506 3170
4670103e
CZ		 3171 md_number_to_chars_midend (fixpos, insn, fixP->fx_size);
3172}
886a2506 3173
4670103e 3174/* Prepare machine-dependent frags for relaxation.
886a2506 3175
4670103e
CZ		 3176 Called just before relaxation starts. Any symbol that is now undefined
3177 will not become defined.
886a2506 3178
4670103e 3179 Return the correct fr_subtype in the frag.
886a2506 3180
4670103e
CZ		 3181 Return the initial "guess for fr_var" to caller. The guess for fr_var
3182 is *actually* the growth beyond fr_fix. Whatever we do to grow fr_fix
3183 or fr_var contributes to our returned value.
886a2506 3184
4670103e
CZ		 3185 Although it may not be explicit in the frag, pretend
3186 fr_var starts with a value. */
886a2506 3187
4670103e
CZ		 3188int
3189md_estimate_size_before_relax (fragS *fragP,
3190 segT segment)
3191{
3192 int growth;
3193
3194 /* If the symbol is not located within the same section AND it's not
3195 an absolute section, use the maximum. OR if the symbol is a
3196 constant AND the insn is by nature not pc-rel, use the maximum.
3197 OR if the symbol is being equated against another symbol, use the
3198 maximum. OR if the symbol is weak use the maximum. */
3199 if ((S_GET_SEGMENT (fragP->fr_symbol) != segment
3200 && S_GET_SEGMENT (fragP->fr_symbol) != absolute_section)
3201 || (symbol_constant_p (fragP->fr_symbol)
3202 && !fragP->tc_frag_data.pcrel)
3203 || symbol_equated_p (fragP->fr_symbol)
3204 || S_IS_WEAK (fragP->fr_symbol))
3205 {
3206 while (md_relax_table[fragP->fr_subtype].rlx_more != ARC_RLX_NONE)
3207 ++fragP->fr_subtype;
3208 }
886a2506 3209
4670103e
CZ		 3210 growth = md_relax_table[fragP->fr_subtype].rlx_length;
3211 fragP->fr_var = growth;
886a2506 3212
4670103e
CZ		 3213 pr_debug ("%s:%d: md_estimate_size_before_relax: %d\n",
3214 fragP->fr_file, fragP->fr_line, growth);
886a2506 3215
4670103e
CZ		 3216 return growth;
3217}
886a2506 3218
4670103e
CZ		 3219/* Translate internal representation of relocation info to BFD target
3220 format. */
886a2506 3221
4670103e
CZ		 3222arelent *
3223tc_gen_reloc (asection *section ATTRIBUTE_UNUSED,
3224 fixS *fixP)
3225{
3226 arelent *reloc;
3227 bfd_reloc_code_real_type code;
886a2506 3228
add39d23
TS		 3229 reloc = XNEW (arelent);
3230 reloc->sym_ptr_ptr = XNEW (asymbol *);
4670103e
CZ		 3231 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixP->fx_addsy);
3232 reloc->address = fixP->fx_frag->fr_address + fixP->fx_where;
886a2506 3233
4670103e
CZ		 3234 /* Make sure none of our internal relocations make it this far.
3235 They'd better have been fully resolved by this point. */
3236 gas_assert ((int) fixP->fx_r_type > 0);
886a2506 3237
4670103e 3238 code = fixP->fx_r_type;
886a2506 3239
4670103e
CZ		 3240 /* if we have something like add gp, pcl,
3241 _GLOBAL_OFFSET_TABLE_@gotpc. */
3242 if (code == BFD_RELOC_ARC_GOTPC32
3243 && GOT_symbol
3244 && fixP->fx_addsy == GOT_symbol)
3245 code = BFD_RELOC_ARC_GOTPC;
886a2506 3246
4670103e
CZ		 3247 reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
3248 if (reloc->howto == NULL)
886a2506 3249 {
4670103e
CZ		 3250 as_bad_where (fixP->fx_file, fixP->fx_line,
3251 _("cannot represent `%s' relocation in object file"),
3252 bfd_get_reloc_code_name (code));
3253 return NULL;
3254 }
886a2506 3255
4670103e
CZ		 3256 if (!fixP->fx_pcrel != !reloc->howto->pc_relative)
3257 as_fatal (_("internal error? cannot generate `%s' relocation"),
3258 bfd_get_reloc_code_name (code));
886a2506 3259
4670103e 3260 gas_assert (!fixP->fx_pcrel == !reloc->howto->pc_relative);
886a2506 3261
05bbf016 3262 reloc->addend = fixP->fx_offset;
4670103e
CZ		 3263
3264 return reloc;
886a2506
NC		 3265}
3266
4670103e
CZ		 3267/* Perform post-processing of machine-dependent frags after relaxation.
3268 Called after relaxation is finished.
3269 In: Address of frag.
3270 fr_type == rs_machine_dependent.
3271 fr_subtype is what the address relaxed to.
886a2506 3272
4670103e
CZ		 3273 Out: Any fixS:s and constants are set up. */
3274
3275void
3276md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED,
3277 segT segment ATTRIBUTE_UNUSED,
3278 fragS *fragP)
886a2506 3279{
4670103e
CZ		 3280 const relax_typeS *table_entry;
3281 char *dest;
3282 const struct arc_opcode *opcode;
3283 struct arc_insn insn;
3284 int size, fix;
3285 struct arc_relax_type *relax_arg = &fragP->tc_frag_data;
886a2506 3286
871a6bd2 3287 fix = fragP->fr_fix;
4670103e
CZ		 3288 dest = fragP->fr_literal + fix;
3289 table_entry = TC_GENERIC_RELAX_TABLE + fragP->fr_subtype;
886a2506 3290
9e32d9ae
AB		 3291 pr_debug ("%s:%d: md_convert_frag, subtype: %d, fix: %d, "
3292 "var: %"BFD_VMA_FMT"d\n",
4670103e
CZ		 3293 fragP->fr_file, fragP->fr_line,
3294 fragP->fr_subtype, fix, fragP->fr_var);
886a2506 3295
4670103e
CZ		 3296 if (fragP->fr_subtype <= 0
3297 && fragP->fr_subtype >= arc_num_relax_opcodes)
3298 as_fatal (_("no relaxation found for this instruction."));
886a2506 3299
4670103e 3300 opcode = &arc_relax_opcodes[fragP->fr_subtype];
886a2506 3301
4670103e
CZ		 3302 assemble_insn (opcode, relax_arg->tok, relax_arg->ntok, relax_arg->pflags,
3303 relax_arg->nflg, &insn);
886a2506 3304
4670103e 3305 apply_fixups (&insn, fragP, fix);
886a2506 3306
91fdca6f 3307 size = insn.len + (insn.has_limm ? 4 : 0);
4670103e
CZ		 3308 gas_assert (table_entry->rlx_length == size);
3309 emit_insn0 (&insn, dest, TRUE);
886a2506 3310
4670103e
CZ		 3311 fragP->fr_fix += table_entry->rlx_length;
3312 fragP->fr_var = 0;
886a2506
NC		 3313}
3314
4670103e
CZ		 3315/* We have no need to default values of symbols. We could catch
3316 register names here, but that is handled by inserting them all in
3317 the symbol table to begin with. */
886a2506 3318
4670103e
CZ		 3319symbolS *
3320md_undefined_symbol (char *name)
886a2506 3321{
4670103e
CZ		 3322 /* The arc abi demands that a GOT[0] should be referencible as
3323 [pc+_DYNAMIC@gotpc]. Hence we convert a _DYNAMIC@gotpc to a
3324 GOTPC reference to _GLOBAL_OFFSET_TABLE_. */
3325 if (((*name == '_')
3326 && (*(name+1) == 'G')
7ef0acc1 3327 && (strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0)))
886a2506 3328 {
4670103e
CZ		 3329 if (!GOT_symbol)
3330 {
3331 if (symbol_find (name))
3332 as_bad ("GOT already in symbol table");
3333
3334 GOT_symbol = symbol_new (GLOBAL_OFFSET_TABLE_NAME, undefined_section,
3335 (valueT) 0, &zero_address_frag);
3336 };
3337 return GOT_symbol;
886a2506 3338 }
4670103e 3339 return NULL;
886a2506
NC		 3340}
3341
4670103e
CZ		 3342/* Turn a string in input_line_pointer into a floating point constant
3343 of type type, and store the appropriate bytes in *litP. The number
3344 of LITTLENUMS emitted is stored in *sizeP. An error message is
3345 returned, or NULL on OK. */
886a2506 3346
6d4af3c2 3347const char *
4670103e 3348md_atof (int type, char *litP, int *sizeP)
886a2506 3349{
4670103e
CZ		 3350 return ieee_md_atof (type, litP, sizeP, target_big_endian);
3351}
886a2506 3352
4670103e
CZ		 3353/* Called for any expression that can not be recognized. When the
3354 function is called, `input_line_pointer' will point to the start of
2a1ebfb2
CZ		 3355 the expression. We use it when we have complex operations like
3356 @label1 - @label2. */
886a2506 3357
4670103e 3358void
2a1ebfb2 3359md_operand (expressionS *expressionP)
4670103e
CZ		 3360{
3361 char *p = input_line_pointer;
3362 if (*p == '@')
886a2506 3363 {
4670103e
CZ		 3364 input_line_pointer++;
3365 expressionP->X_op = O_symbol;
2a1ebfb2 3366 expressionP->X_md = O_absent;
4670103e
CZ		 3367 expression (expressionP);
3368 }
3369}
886a2506 3370
4670103e
CZ		 3371/* This function is called from the function 'expression', it attempts
3372 to parse special names (in our case register names). It fills in
3373 the expression with the identified register. It returns TRUE if
3374 it is a register and FALSE otherwise. */
886a2506 3375
4670103e
CZ		 3376bfd_boolean
3377arc_parse_name (const char *name,
3378 struct expressionS *e)
3379{
3380 struct symbol *sym;
886a2506 3381
4670103e
CZ		 3382 if (!assembling_insn)
3383 return FALSE;
886a2506 3384
2a1ebfb2
CZ		 3385 if (e->X_op == O_symbol
3386 && e->X_md == O_absent)
4670103e 3387 return FALSE;
886a2506 3388
4670103e
CZ		 3389 sym = hash_find (arc_reg_hash, name);
3390 if (sym)
3391 {
3392 e->X_op = O_register;
3393 e->X_add_number = S_GET_VALUE (sym);
3394 return TRUE;
3395 }
db18dbab
GM		 3396
3397 sym = hash_find (arc_addrtype_hash, name);
3398 if (sym)
3399 {
3400 e->X_op = O_addrtype;
3401 e->X_add_number = S_GET_VALUE (sym);
3402 return TRUE;
3403 }
3404
4670103e
CZ		 3405 return FALSE;
3406}
886a2506 3407
4670103e
CZ		 3408/* md_parse_option
3409 Invocation line includes a switch not recognized by the base assembler.
3410 See if it's a processor-specific option.
886a2506 3411
4670103e 3412 New options (supported) are:
886a2506 3413
4670103e
CZ		 3414 -mcpu=<cpu name> Assemble for selected processor
3415 -EB/-mbig-endian Big-endian
3416 -EL/-mlittle-endian Little-endian
3417 -mrelax Enable relaxation
886a2506 3418
4670103e 3419 The following CPU names are recognized:
ce440d63 3420 arc600, arc700, arcem, archs, nps400. */
886a2506 3421
4670103e 3422int
17b9d67d 3423md_parse_option (int c, const char *arg ATTRIBUTE_UNUSED)
4670103e 3424{
4670103e
CZ		 3425 switch (c)
3426 {
3427 case OPTION_ARC600:
3428 case OPTION_ARC601:
3429 return md_parse_option (OPTION_MCPU, "arc600");
886a2506 3430
4670103e
CZ		 3431 case OPTION_ARC700:
3432 return md_parse_option (OPTION_MCPU, "arc700");
886a2506 3433
4670103e
CZ		 3434 case OPTION_ARCEM:
3435 return md_parse_option (OPTION_MCPU, "arcem");
886a2506 3436
4670103e
CZ		 3437 case OPTION_ARCHS:
3438 return md_parse_option (OPTION_MCPU, "archs");
886a2506 3439
4670103e
CZ		 3440 case OPTION_MCPU:
3441 {
bb65a718 3442 arc_select_cpu (arg, MACH_SELECTION_FROM_COMMAND_LINE);
4670103e
CZ		 3443 break;
3444 }
886a2506 3445
4670103e
CZ		 3446 case OPTION_EB:
3447 arc_target_format = "elf32-bigarc";
3448 byte_order = BIG_ENDIAN;
3449 break;
886a2506 3450
4670103e
CZ		 3451 case OPTION_EL:
3452 arc_target_format = "elf32-littlearc";
3453 byte_order = LITTLE_ENDIAN;
3454 break;
886a2506 3455
4670103e 3456 case OPTION_CD:
53a346d8
CZ		 3457 selected_cpu.features |= CD;
3458 cl_features |= CD;
bb050a69 3459 arc_check_feature ();
4670103e 3460 break;
886a2506 3461
4670103e
CZ		 3462 case OPTION_RELAX:
3463 relaxation_state = 1;
3464 break;
886a2506 3465
bdd582db 3466 case OPTION_NPS400:
53a346d8
CZ		 3467 selected_cpu.features |= NPS400;
3468 cl_features |= NPS400;
bb050a69 3469 arc_check_feature ();
ce440d63 3470 break;
bdd582db 3471
ce440d63 3472 case OPTION_SPFP:
53a346d8
CZ		 3473 selected_cpu.features |= SPX;
3474 cl_features |= SPX;
bb050a69 3475 arc_check_feature ();
ce440d63
GM		 3476 break;
3477
3478 case OPTION_DPFP:
53a346d8
CZ		 3479 selected_cpu.features |= DPX;
3480 cl_features |= DPX;
bb050a69 3481 arc_check_feature ();
ce440d63
GM		 3482 break;
3483
3484 case OPTION_FPUDA:
53a346d8
CZ		 3485 selected_cpu.features |= DPA;
3486 cl_features |= DPA;
bb050a69 3487 arc_check_feature ();
ce440d63
GM		 3488 break;
3489
3490 /* Dummy options are accepted but have no effect. */
4670103e
CZ		 3491 case OPTION_USER_MODE:
3492 case OPTION_LD_EXT_MASK:
3493 case OPTION_SWAP:
3494 case OPTION_NORM:
3495 case OPTION_BARREL_SHIFT:
3496 case OPTION_MIN_MAX:
3497 case OPTION_NO_MPY:
3498 case OPTION_EA:
3499 case OPTION_MUL64:
3500 case OPTION_SIMD:
4670103e
CZ		 3501 case OPTION_XMAC_D16:
3502 case OPTION_XMAC_24:
3503 case OPTION_DSP_PACKA:
3504 case OPTION_CRC:
3505 case OPTION_DVBF:
3506 case OPTION_TELEPHONY:
3507 case OPTION_XYMEMORY:
3508 case OPTION_LOCK:
3509 case OPTION_SWAPE:
3510 case OPTION_RTSC:
8ddf6b2a
CZ		 3511 break;
3512
4670103e
CZ		 3513 default:
3514 return 0;
3515 }
886a2506 3516
4670103e
CZ		 3517 return 1;
3518}
886a2506 3519
a9752fdf
CZ		 3520/* Display the list of cpu names for use in the help text. */
3521
3522static void
3523arc_show_cpu_list (FILE *stream)
3524{
3525 int i, offset;
731f7c4e 3526 static const char *space_buf = " ";
a9752fdf 3527
731f7c4e
MR		 3528 fprintf (stream, "%s", space_buf);
3529 offset = strlen (space_buf);
a9752fdf
CZ		 3530 for (i = 0; cpu_types[i].name != NULL; ++i)
3531 {
3532 bfd_boolean last = (cpu_types[i + 1].name == NULL);
3533
3534 /* If displaying the new cpu name string, and the ', ' (for all
3535 but the last one) will take us past a target width of 80
3536 characters, then it's time for a new line. */
3537 if (offset + strlen (cpu_types[i].name) + (last ? 0 : 2) > 80)
3538 {
731f7c4e
MR		 3539 fprintf (stream, "\n%s", space_buf);
3540 offset = strlen (space_buf);
a9752fdf
CZ		 3541 }
3542
3543 fprintf (stream, "%s%s", cpu_types[i].name, (last ? "\n" : ", "));
3544 offset += strlen (cpu_types [i].name) + (last ? 0 : 2);
3545 }
3546}
3547
4670103e
CZ		 3548void
3549md_show_usage (FILE *stream)
3550{
3551 fprintf (stream, _("ARC-specific assembler options:\n"));
886a2506 3552
a9752fdf
CZ		 3553 fprintf (stream, " -mcpu=<cpu name>\t (default: %s), assemble for"
3554 " CPU <cpu name>, one of:\n", TARGET_WITH_CPU);
3555 arc_show_cpu_list (stream);
3556 fprintf (stream, "\n");
bdd582db
GM		 3557 fprintf (stream, " -mA6/-mARC600/-mARC601 same as -mcpu=arc600\n");
3558 fprintf (stream, " -mA7/-mARC700\t\t same as -mcpu=arc700\n");
3559 fprintf (stream, " -mEM\t\t\t same as -mcpu=arcem\n");
3560 fprintf (stream, " -mHS\t\t\t same as -mcpu=archs\n");
3561
3562 fprintf (stream, " -mnps400\t\t enable NPS-400 extended instructions\n");
a9752fdf
CZ		 3563 fprintf (stream, " -mspfp\t\t enable single-precision floating point"
3564 " instructions\n");
3565 fprintf (stream, " -mdpfp\t\t enable double-precision floating point"
3566 " instructions\n");
bdd582db
GM		 3567 fprintf (stream, " -mfpuda\t\t enable double-precision assist floating "
3568 "point\n\t\t\t instructions for ARC EM\n");
3569
4670103e
CZ		 3570 fprintf (stream,
3571 " -mcode-density\t enable code density option for ARC EM\n");
3572
3573 fprintf (stream, _("\
3574 -EB assemble code for a big-endian cpu\n"));
3575 fprintf (stream, _("\
3576 -EL assemble code for a little-endian cpu\n"));
3577 fprintf (stream, _("\
bdd582db
GM		 3578 -mrelax enable relaxation\n"));
3579
3580 fprintf (stream, _("The following ARC-specific assembler options are "
3581 "deprecated and are accepted\nfor compatibility only:\n"));
3582
3583 fprintf (stream, _(" -mEA\n"
3584 " -mbarrel-shifter\n"
3585 " -mbarrel_shifter\n"
3586 " -mcrc\n"
3587 " -mdsp-packa\n"
3588 " -mdsp_packa\n"
3589 " -mdvbf\n"
3590 " -mld-extension-reg-mask\n"
3591 " -mlock\n"
3592 " -mmac-24\n"
3593 " -mmac-d16\n"
3594 " -mmac_24\n"
3595 " -mmac_d16\n"
3596 " -mmin-max\n"
3597 " -mmin_max\n"
3598 " -mmul64\n"
3599 " -mno-mpy\n"
3600 " -mnorm\n"
3601 " -mrtsc\n"
3602 " -msimd\n"
3603 " -mswap\n"
3604 " -mswape\n"
3605 " -mtelephony\n"
3606 " -muser-mode-only\n"
3607 " -mxy\n"));
886a2506
NC		 3608}
3609
3610/* Find the proper relocation for the given opcode. */
3611
3612static extended_bfd_reloc_code_real_type
3613find_reloc (const char *name,
3614 const char *opcodename,
3615 const struct arc_flags *pflags,
3616 int nflg,
3617 extended_bfd_reloc_code_real_type reloc)
3618{
3619 unsigned int i;
3620 int j;
24b368f8 3621 bfd_boolean found_flag, tmp;
886a2506
NC		 3622 extended_bfd_reloc_code_real_type ret = BFD_RELOC_UNUSED;
3623
3624 for (i = 0; i < arc_num_equiv_tab; i++)
3625 {
3626 const struct arc_reloc_equiv_tab *r = &arc_reloc_equiv[i];
3627
3628 /* Find the entry. */
3629 if (strcmp (name, r->name))
3630 continue;
3631 if (r->mnemonic && (strcmp (r->mnemonic, opcodename)))
3632 continue;
24b368f8 3633 if (r->flags[0])
886a2506
NC		 3634 {
3635 if (!nflg)
3636 continue;
3637 found_flag = FALSE;
24b368f8
CZ		 3638 unsigned * psflg = (unsigned *)r->flags;
3639 do
3640 {
3641 tmp = FALSE;
3642 for (j = 0; j < nflg; j++)
3643 if (!strcmp (pflags[j].name,
3644 arc_flag_operands[*psflg].name))
3645 {
3646 tmp = TRUE;
3647 break;
3648 }
3649 if (!tmp)
3650 {
3651 found_flag = FALSE;
3652 break;
3653 }
3654 else
3655 {
3656 found_flag = TRUE;
3657 }
3658 ++ psflg;
3659 } while (*psflg);
3660
886a2506
NC		 3661 if (!found_flag)
3662 continue;
3663 }
3664
3665 if (reloc != r->oldreloc)
3666 continue;
3667 /* Found it. */
3668 ret = r->newreloc;
3669 break;
3670 }
3671
3672 if (ret == BFD_RELOC_UNUSED)
3673 as_bad (_("Unable to find %s relocation for instruction %s"),
3674 name, opcodename);
3675 return ret;
3676}
3677
4670103e
CZ		 3678/* All the symbol types that are allowed to be used for
3679 relaxation. */
3680
3681static bfd_boolean
3682may_relax_expr (expressionS tok)
3683{
3684 /* Check if we have unrelaxable relocs. */
3685 switch (tok.X_md)
3686 {
3687 default:
3688 break;
3689 case O_plt:
3690 return FALSE;
3691 }
3692
3693 switch (tok.X_op)
3694 {
3695 case O_symbol:
3696 case O_multiply:
3697 case O_divide:
3698 case O_modulus:
3699 case O_add:
3700 case O_subtract:
3701 break;
3702
3703 default:
3704 return FALSE;
3705 }
3706 return TRUE;
3707}
3708
3709/* Checks if flags are in line with relaxable insn. */
3710
3711static bfd_boolean
3712relaxable_flag (const struct arc_relaxable_ins *ins,
3713 const struct arc_flags *pflags,
3714 int nflgs)
3715{
3716 unsigned flag_class,
3717 flag,
3718 flag_class_idx = 0,
3719 flag_idx = 0;
3720
3721 const struct arc_flag_operand *flag_opand;
3722 int i, counttrue = 0;
3723
3724 /* Iterate through flags classes. */
3725 while ((flag_class = ins->flag_classes[flag_class_idx]) != 0)
3726 {
3727 /* Iterate through flags in flag class. */
3728 while ((flag = arc_flag_classes[flag_class].flags[flag_idx])
3729 != 0)
3730 {
3731 flag_opand = &arc_flag_operands[flag];
3732 /* Iterate through flags in ins to compare. */
3733 for (i = 0; i < nflgs; ++i)
3734 {
3735 if (strcmp (flag_opand->name, pflags[i].name) == 0)
3736 ++counttrue;
3737 }
3738
3739 ++flag_idx;
3740 }
3741
3742 ++flag_class_idx;
3743 flag_idx = 0;
3744 }
3745
3746 /* If counttrue == nflgs, then all flags have been found. */
3747 return (counttrue == nflgs ? TRUE : FALSE);
3748}
3749
3750/* Checks if operands are in line with relaxable insn. */
3751
3752static bfd_boolean
3753relaxable_operand (const struct arc_relaxable_ins *ins,
3754 const expressionS *tok,
3755 int ntok)
3756{
3757 const enum rlx_operand_type *operand = &ins->operands[0];
3758 int i = 0;
3759
3760 while (*operand != EMPTY)
3761 {
3762 const expressionS *epr = &tok[i];
3763
3764 if (i != 0 && i >= ntok)
3765 return FALSE;
3766
3767 switch (*operand)
3768 {
3769 case IMMEDIATE:
3770 if (!(epr->X_op == O_multiply
3771 || epr->X_op == O_divide
3772 || epr->X_op == O_modulus
3773 || epr->X_op == O_add
3774 || epr->X_op == O_subtract
3775 || epr->X_op == O_symbol))
3776 return FALSE;
3777 break;
3778
3779 case REGISTER_DUP:
3780 if ((i <= 0)
3781 || (epr->X_add_number != tok[i - 1].X_add_number))
3782 return FALSE;
3783 /* Fall through. */
3784 case REGISTER:
3785 if (epr->X_op != O_register)
3786 return FALSE;
3787 break;
3788
3789 case REGISTER_S:
3790 if (epr->X_op != O_register)
3791 return FALSE;
3792
3793 switch (epr->X_add_number)
3794 {
3795 case 0: case 1: case 2: case 3:
3796 case 12: case 13: case 14: case 15:
3797 break;
3798 default:
3799 return FALSE;
3800 }
3801 break;
3802
3803 case REGISTER_NO_GP:
3804 if ((epr->X_op != O_register)
3805 || (epr->X_add_number == 26)) /* 26 is the gp register. */
3806 return FALSE;
3807 break;
3808
3809 case BRACKET:
3810 if (epr->X_op != O_bracket)
3811 return FALSE;
3812 break;
3813
3814 default:
3815 /* Don't understand, bail out. */
3816 return FALSE;
3817 break;
3818 }
3819
3820 ++i;
3821 operand = &ins->operands[i];
3822 }
3823
3824 return (i == ntok ? TRUE : FALSE);
3825}
3826
3827/* Return TRUE if this OPDCODE is a candidate for relaxation. */
3828
3829static bfd_boolean
3830relax_insn_p (const struct arc_opcode *opcode,
3831 const expressionS *tok,
3832 int ntok,
3833 const struct arc_flags *pflags,
3834 int nflg)
3835{
3836 unsigned i;
3837 bfd_boolean rv = FALSE;
3838
3839 /* Check the relaxation table. */
3840 for (i = 0; i < arc_num_relaxable_ins && relaxation_state; ++i)
3841 {
3842 const struct arc_relaxable_ins *arc_rlx_ins = &arc_relaxable_insns[i];
3843
3844 if ((strcmp (opcode->name, arc_rlx_ins->mnemonic_r) == 0)
3845 && may_relax_expr (tok[arc_rlx_ins->opcheckidx])
3846 && relaxable_operand (arc_rlx_ins, tok, ntok)
3847 && relaxable_flag (arc_rlx_ins, pflags, nflg))
3848 {
3849 rv = TRUE;
3850 frag_now->fr_subtype = arc_relaxable_insns[i].subtype;
3851 memcpy (&frag_now->tc_frag_data.tok, tok,
3852 sizeof (expressionS) * ntok);
3853 memcpy (&frag_now->tc_frag_data.pflags, pflags,
3854 sizeof (struct arc_flags) * nflg);
3855 frag_now->tc_frag_data.nflg = nflg;
3856 frag_now->tc_frag_data.ntok = ntok;
3857 break;
3858 }
3859 }
3860
3861 return rv;
3862}
3863
886a2506
NC		 3864/* Turn an opcode description and a set of arguments into
3865 an instruction and a fixup. */
3866
3867static void
3868assemble_insn (const struct arc_opcode *opcode,
3869 const expressionS *tok,
3870 int ntok,
3871 const struct arc_flags *pflags,
3872 int nflg,
3873 struct arc_insn *insn)
3874{
3875 const expressionS *reloc_exp = NULL;
bdfe53e3 3876 unsigned long long image;
886a2506
NC		 3877 const unsigned char *argidx;
3878 int i;
3879 int tokidx = 0;
3880 unsigned char pcrel = 0;
3881 bfd_boolean needGOTSymbol;
3882 bfd_boolean has_delay_slot = FALSE;
3883 extended_bfd_reloc_code_real_type reloc = BFD_RELOC_UNUSED;
3884
3885 memset (insn, 0, sizeof (*insn));
3886 image = opcode->opcode;
3887
bdfe53e3 3888 pr_debug ("%s:%d: assemble_insn: %s using opcode %llx\n",
886a2506
NC		 3889 frag_now->fr_file, frag_now->fr_line, opcode->name,
3890 opcode->opcode);
3891
3892 /* Handle operands. */
3893 for (argidx = opcode->operands; *argidx; ++argidx)
3894 {
3895 const struct arc_operand *operand = &arc_operands[*argidx];
3896 const expressionS *t = (const expressionS *) 0;
3897
db18dbab 3898 if (ARC_OPERAND_IS_FAKE (operand))
886a2506
NC		 3899 continue;
3900
3901 if (operand->flags & ARC_OPERAND_DUPLICATE)
3902 {
3903 /* Duplicate operand, already inserted. */
3904 tokidx ++;
3905 continue;
3906 }
3907
3908 if (tokidx >= ntok)
3909 {
3910 abort ();
3911 }
3912 else
3913 t = &tok[tokidx++];
3914
3915 /* Regardless if we have a reloc or not mark the instruction
3916 limm if it is the case. */
3917 if (operand->flags & ARC_OPERAND_LIMM)
3918 insn->has_limm = TRUE;
3919
3920 switch (t->X_op)
3921 {
3922 case O_register:
3923 image = insert_operand (image, operand, regno (t->X_add_number),
3924 NULL, 0);
3925 break;
3926
3927 case O_constant:
3928 image = insert_operand (image, operand, t->X_add_number, NULL, 0);
3929 reloc_exp = t;
3930 if (operand->flags & ARC_OPERAND_LIMM)
3931 insn->limm = t->X_add_number;
3932 break;
3933
3934 case O_bracket:
db18dbab
GM		 3935 case O_colon:
3936 case O_addrtype:
3937 /* Ignore brackets, colons, and address types. */
886a2506
NC		 3938 break;
3939
3940 case O_absent:
3941 gas_assert (operand->flags & ARC_OPERAND_IGNORE);
3942 break;
3943
3944 case O_subtract:
3945 /* Maybe register range. */
3946 if ((t->X_add_number == 0)
3947 && contains_register (t->X_add_symbol)
3948 && contains_register (t->X_op_symbol))
3949 {
3950 int regs;
3951
3952 regs = get_register (t->X_add_symbol);
3953 regs <<= 16;
3954 regs |= get_register (t->X_op_symbol);
3955 image = insert_operand (image, operand, regs, NULL, 0);
3956 break;
3957 }
1a0670f3 3958 /* Fall through. */
886a2506
NC		 3959
3960 default:
3961 /* This operand needs a relocation. */
3962 needGOTSymbol = FALSE;
3963
3964 switch (t->X_md)
3965 {
3966 case O_plt:
c810e0b8 3967 if (opcode->insn_class == JUMP)
6e3f3473 3968 as_bad (_("Unable to use @plt relocation for insn %s"),
3969 opcode->name);
886a2506
NC		 3970 needGOTSymbol = TRUE;
3971 reloc = find_reloc ("plt", opcode->name,
3972 pflags, nflg,
3973 operand->default_reloc);
3974 break;
3975
3976 case O_gotoff:
3977 case O_gotpc:
3978 needGOTSymbol = TRUE;
3979 reloc = ARC_RELOC_TABLE (t->X_md)->reloc;
3980 break;
3981 case O_pcl:
cc07cda6
CZ		 3982 if (operand->flags & ARC_OPERAND_LIMM)
3983 {
3984 reloc = ARC_RELOC_TABLE (t->X_md)->reloc;
3985 if (arc_opcode_len (opcode) == 2
3986 || opcode->insn_class == JUMP)
6e3f3473 3987 as_bad (_("Unable to use @pcl relocation for insn %s"),
3988 opcode->name);
cc07cda6
CZ		 3989 }
3990 else
3991 {
3992 /* This is a relaxed operand which initially was
3993 limm, choose whatever we have defined in the
3994 opcode as reloc. */
3995 reloc = operand->default_reloc;
3996 }
886a2506
NC		 3997 break;
3998 case O_sda:
3999 reloc = find_reloc ("sda", opcode->name,
4000 pflags, nflg,
4001 operand->default_reloc);
4002 break;
4003 case O_tlsgd:
4004 case O_tlsie:
4005 needGOTSymbol = TRUE;
4006 /* Fall-through. */
4007
4008 case O_tpoff:
4009 case O_dtpoff:
4010 reloc = ARC_RELOC_TABLE (t->X_md)->reloc;
4011 break;
4012
4013 case O_tpoff9: /*FIXME! Check for the conditionality of
4014 the insn. */
4015 case O_dtpoff9: /*FIXME! Check for the conditionality of
4016 the insn. */
4017 as_bad (_("TLS_*_S9 relocs are not supported yet"));
4018 break;
4019
4020 default:
4021 /* Just consider the default relocation. */
4022 reloc = operand->default_reloc;
4023 break;
4024 }
4025
4026 if (needGOTSymbol && (GOT_symbol == NULL))
4027 GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME);
4028
4029 reloc_exp = t;
4030
4031#if 0
4032 if (reloc > 0)
4033 {
4034 /* sanity checks. */
4035 reloc_howto_type *reloc_howto
4036 = bfd_reloc_type_lookup (stdoutput,
4037 (bfd_reloc_code_real_type) reloc);
4038 unsigned reloc_bitsize = reloc_howto->bitsize;
4039 if (reloc_howto->rightshift)
4040 reloc_bitsize -= reloc_howto->rightshift;
4041 if (reloc_bitsize != operand->bits)
4042 {
4043 as_bad (_("invalid relocation %s for field"),
4044 bfd_get_reloc_code_name (reloc));
4045 return;
4046 }
4047 }
4048#endif
4049 if (insn->nfixups >= MAX_INSN_FIXUPS)
4050 as_fatal (_("too many fixups"));
4051
4052 struct arc_fixup *fixup;
4053 fixup = &insn->fixups[insn->nfixups++];
4054 fixup->exp = *t;
4055 fixup->reloc = reloc;
cc07cda6
CZ		 4056 if ((int) reloc < 0)
4057 pcrel = (operand->flags & ARC_OPERAND_PCREL) ? 1 : 0;
4058 else
4059 {
4060 reloc_howto_type *reloc_howto =
4061 bfd_reloc_type_lookup (stdoutput,
4062 (bfd_reloc_code_real_type) fixup->reloc);
4063 pcrel = reloc_howto->pc_relative;
4064 }
886a2506
NC		 4065 fixup->pcrel = pcrel;
4066 fixup->islong = (operand->flags & ARC_OPERAND_LIMM) ?
4067 TRUE : FALSE;
4068 break;
4069 }
4070 }
4071
4072 /* Handle flags. */
4073 for (i = 0; i < nflg; i++)
4074 {
f36e33da 4075 const struct arc_flag_operand *flg_operand = pflags[i].flgp;
886a2506
NC		 4076
4077 /* Check if the instruction has a delay slot. */
4078 if (!strcmp (flg_operand->name, "d"))
4079 has_delay_slot = TRUE;
4080
2c52e2e8
RZ		 4081 /* There is an exceptional case when we cannot insert a flag just as
4082 it is. On ARCv2 the '.t' and '.nt' flags must be handled in
4083 relation with the relative address. Unfortunately, some of the
4084 ARC700 extensions (NPS400) also have a '.nt' flag that should be
4085 handled in the normal way.
4086
4087 Flag operands don't have an architecture field, so we can't
4088 directly validate that FLAG_OPERAND is valid for the current
4089 architecture, what we do instead is just validate that we're
4090 assembling for an ARCv2 architecture. */
4091 if ((selected_cpu.flags & ARC_OPCODE_ARCV2)
4092 && (!strcmp (flg_operand->name, "t")
4093 || !strcmp (flg_operand->name, "nt")))
886a2506
NC		 4094 {
4095 unsigned bitYoperand = 0;
4096 /* FIXME! move selection bbit/brcc in arc-opc.c. */
4097 if (!strcmp (flg_operand->name, "t"))
4098 if (!strcmp (opcode->name, "bbit0")
4099 || !strcmp (opcode->name, "bbit1"))
4100 bitYoperand = arc_NToperand;
4101 else
4102 bitYoperand = arc_Toperand;
4103 else
4104 if (!strcmp (opcode->name, "bbit0")
4105 || !strcmp (opcode->name, "bbit1"))
4106 bitYoperand = arc_Toperand;
4107 else
4108 bitYoperand = arc_NToperand;
4109
4110 gas_assert (reloc_exp != NULL);
4111 if (reloc_exp->X_op == O_constant)
4112 {
4113 /* Check if we have a constant and solved it
4114 immediately. */
4115 offsetT val = reloc_exp->X_add_number;
4116 image |= insert_operand (image, &arc_operands[bitYoperand],
4117 val, NULL, 0);
4118 }
4119 else
4120 {
4121 struct arc_fixup *fixup;
4122
4123 if (insn->nfixups >= MAX_INSN_FIXUPS)
4124 as_fatal (_("too many fixups"));
4125
4126 fixup = &insn->fixups[insn->nfixups++];
4127 fixup->exp = *reloc_exp;
4128 fixup->reloc = -bitYoperand;
4129 fixup->pcrel = pcrel;
4130 fixup->islong = FALSE;
4131 }
4132 }
4133 else
4134 image |= (flg_operand->code & ((1 << flg_operand->bits) - 1))
4135 << flg_operand->shift;
4136 }
4137
4670103e
CZ		 4138 insn->relax = relax_insn_p (opcode, tok, ntok, pflags, nflg);
4139
91fdca6f 4140 /* Instruction length. */
06fe285f 4141 insn->len = arc_opcode_len (opcode);
886a2506
NC		 4142
4143 insn->insn = image;
4144
4145 /* Update last insn status. */
4146 arc_last_insns[1] = arc_last_insns[0];
4147 arc_last_insns[0].opcode = opcode;
4148 arc_last_insns[0].has_limm = insn->has_limm;
4149 arc_last_insns[0].has_delay_slot = has_delay_slot;
4150
4151 /* Check if the current instruction is legally used. */
4152 if (arc_last_insns[1].has_delay_slot
4153 && is_br_jmp_insn_p (arc_last_insns[0].opcode))
6e3f3473 4154 as_bad (_("Insn %s has a jump/branch instruction %s in its delay slot."),
4155 arc_last_insns[1].opcode->name,
4156 arc_last_insns[0].opcode->name);
cf9bdae9 4157 if (arc_last_insns[1].has_delay_slot
4158 && arc_last_insns[0].has_limm)
4159 as_bad (_("Insn %s has an instruction %s with limm in its delay slot."),
4160 arc_last_insns[1].opcode->name,
4161 arc_last_insns[0].opcode->name);
886a2506
NC		 4162}
4163
886a2506
NC		 4164void
4165arc_handle_align (fragS* fragP)
4166{
4167 if ((fragP)->fr_type == rs_align_code)
4168 {
4169 char *dest = (fragP)->fr_literal + (fragP)->fr_fix;
4170 valueT count = ((fragP)->fr_next->fr_address
4171 - (fragP)->fr_address - (fragP)->fr_fix);
4172
4173 (fragP)->fr_var = 2;
4174
4175 if (count & 1)/* Padding in the gap till the next 2-byte
4176 boundary with 0s. */
4177 {
4178 (fragP)->fr_fix++;
4179 *dest++ = 0;
4180 }
4181 /* Writing nop_s. */
4182 md_number_to_chars (dest, NOP_OPCODE_S, 2);
4183 }
4184}
4185
4186/* Here we decide which fixups can be adjusted to make them relative
4187 to the beginning of the section instead of the symbol. Basically
4188 we need to make sure that the dynamic relocations are done
4189 correctly, so in some cases we force the original symbol to be
4190 used. */
4191
4192int
4193tc_arc_fix_adjustable (fixS *fixP)
4194{
4195
4196 /* Prevent all adjustments to global symbols. */
4197 if (S_IS_EXTERNAL (fixP->fx_addsy))
4198 return 0;
4199 if (S_IS_WEAK (fixP->fx_addsy))
4200 return 0;
4201
4202 /* Adjust_reloc_syms doesn't know about the GOT. */
4203 switch (fixP->fx_r_type)
4204 {
4205 case BFD_RELOC_ARC_GOTPC32:
4206 case BFD_RELOC_ARC_PLT32:
4207 case BFD_RELOC_ARC_S25H_PCREL_PLT:
4208 case BFD_RELOC_ARC_S21H_PCREL_PLT:
4209 case BFD_RELOC_ARC_S25W_PCREL_PLT:
4210 case BFD_RELOC_ARC_S21W_PCREL_PLT:
4211 return 0;
4212
4213 default:
4214 break;
4215 }
4216
841fdfcd 4217 return 1;
886a2506
NC		 4218}
4219
4220/* Compute the reloc type of an expression EXP. */
4221
4222static void
4223arc_check_reloc (expressionS *exp,
4224 bfd_reloc_code_real_type *r_type_p)
4225{
4226 if (*r_type_p == BFD_RELOC_32
4227 && exp->X_op == O_subtract
4228 && exp->X_op_symbol != NULL
8d1015a8 4229 && S_GET_SEGMENT (exp->X_op_symbol) == now_seg)
6f4b1afc 4230 *r_type_p = BFD_RELOC_ARC_32_PCREL;
886a2506
NC		 4231}
4232
4233
4234/* Add expression EXP of SIZE bytes to offset OFF of fragment FRAG. */
4235
4236void
4237arc_cons_fix_new (fragS *frag,
4238 int off,
4239 int size,
4240 expressionS *exp,
4241 bfd_reloc_code_real_type r_type)
4242{
4243 r_type = BFD_RELOC_UNUSED;
4244
4245 switch (size)
4246 {
4247 case 1:
4248 r_type = BFD_RELOC_8;
4249 break;
4250
4251 case 2:
4252 r_type = BFD_RELOC_16;
4253 break;
4254
4255 case 3:
4256 r_type = BFD_RELOC_24;
4257 break;
4258
4259 case 4:
4260 r_type = BFD_RELOC_32;
4261 arc_check_reloc (exp, &r_type);
4262 break;
4263
4264 case 8:
4265 r_type = BFD_RELOC_64;
4266 break;
4267
4268 default:
4269 as_bad (_("unsupported BFD relocation size %u"), size);
4270 r_type = BFD_RELOC_UNUSED;
4271 }
4272
4273 fix_new_exp (frag, off, size, exp, 0, r_type);
4274}
4275
4276/* The actual routine that checks the ZOL conditions. */
4277
4278static void
4279check_zol (symbolS *s)
4280{
bb65a718 4281 switch (selected_cpu.mach)
886a2506
NC		 4282 {
4283 case bfd_mach_arc_arcv2:
bb65a718 4284 if (selected_cpu.flags & ARC_OPCODE_ARCv2EM)
886a2506
NC		 4285 return;
4286
4287 if (is_br_jmp_insn_p (arc_last_insns[0].opcode)
4288 || arc_last_insns[1].has_delay_slot)
4289 as_bad (_("Jump/Branch instruction detected at the end of the ZOL label @%s"),
4290 S_GET_NAME (s));
4291
4292 break;
4293 case bfd_mach_arc_arc600:
4294
4295 if (is_kernel_insn_p (arc_last_insns[0].opcode))
4296 as_bad (_("Kernel instruction detected at the end of the ZOL label @%s"),
4297 S_GET_NAME (s));
4298
4299 if (arc_last_insns[0].has_limm
4300 && is_br_jmp_insn_p (arc_last_insns[0].opcode))
4301 as_bad (_("A jump instruction with long immediate detected at the \
4302end of the ZOL label @%s"), S_GET_NAME (s));
4303
4304 /* Fall through. */
4305 case bfd_mach_arc_arc700:
4306 if (arc_last_insns[0].has_delay_slot)
4307 as_bad (_("An illegal use of delay slot detected at the end of the ZOL label @%s"),
4308 S_GET_NAME (s));
4309
4310 break;
4311 default:
4312 break;
4313 }
4314}
4315
4316/* If ZOL end check the last two instruction for illegals. */
4317void
4318arc_frob_label (symbolS * sym)
4319{
4320 if (ARC_GET_FLAG (sym) & ARC_FLAG_ZOL)
4321 check_zol (sym);
4322
4323 dwarf2_emit_label (sym);
ea1562b3 4324}
4670103e
CZ		 4325
4326/* Used because generic relaxation assumes a pc-rel value whilst we
4327 also relax instructions that use an absolute value resolved out of
4328 relative values (if that makes any sense). An example: 'add r1,
4329 r2, @.L2 - .' The symbols . and @.L2 are relative to the section
4330 but if they're in the same section we can subtract the section
4331 offset relocation which ends up in a resolved value. So if @.L2 is
4332 .text + 0x50 and . is .text + 0x10, we can say that .text + 0x50 -
4333 .text + 0x40 = 0x10. */
4334int
4335arc_pcrel_adjust (fragS *fragP)
4336{
cc07cda6
CZ		 4337 pr_debug ("arc_pcrel_adjust: address=%ld, fix=%ld, PCrel %s\n",
4338 fragP->fr_address, fragP->fr_fix,
4339 fragP->tc_frag_data.pcrel ? "Y" : "N");
4340
4670103e
CZ		 4341 if (!fragP->tc_frag_data.pcrel)
4342 return fragP->fr_address + fragP->fr_fix;
4343
cc07cda6
CZ		 4344 /* Take into account the PCL rounding. */
4345 return (fragP->fr_address + fragP->fr_fix) & 0x03;
4670103e 4346}
726c18e1
CZ		 4347
4348/* Initialize the DWARF-2 unwind information for this procedure. */
4349
4350void
4351tc_arc_frame_initial_instructions (void)
4352{
4353 /* Stack pointer is register 28. */
45a54ee5 4354 cfi_add_CFA_def_cfa (28, 0);
726c18e1
CZ		 4355}
4356
4357int
4358tc_arc_regname_to_dw2regnum (char *regname)
4359{
4360 struct symbol *sym;
4361
4362 sym = hash_find (arc_reg_hash, regname);
4363 if (sym)
4364 return S_GET_VALUE (sym);
4365
4366 return -1;
4367}
37ab9779
CZ		 4368
4369/* Adjust the symbol table. Delete found AUX register symbols. */
4370
4371void
4372arc_adjust_symtab (void)
4373{
4374 symbolS * sym;
4375
4376 for (sym = symbol_rootP; sym != NULL; sym = symbol_next (sym))
4377 {
4378 /* I've created a symbol during parsing process. Now, remove
4379 the symbol as it is found to be an AUX register. */
4380 if (ARC_GET_FLAG (sym) & ARC_FLAG_AUX)
4381 symbol_remove (sym, &symbol_rootP, &symbol_lastP);
4382 }
4383
4384 /* Now do generic ELF adjustments. */
4385 elf_adjust_symtab ();
4386}
b99747ae
CZ		 4387
4388static void
4389tokenize_extinsn (extInstruction_t *einsn)
4390{
4391 char *p, c;
4392 char *insn_name;
4393 unsigned char major_opcode;
4394 unsigned char sub_opcode;
4395 unsigned char syntax_class = 0;
4396 unsigned char syntax_class_modifiers = 0;
4397 unsigned char suffix_class = 0;
4398 unsigned int i;
4399
4400 SKIP_WHITESPACE ();
4401
4402 /* 1st: get instruction name. */
4403 p = input_line_pointer;
4404 c = get_symbol_name (&p);
4405
4406 insn_name = xstrdup (p);
4407 restore_line_pointer (c);
4408
f02806be 4409 /* Convert to lower case. */
4410 for (p = insn_name; *p; ++p)
4411 *p = TOLOWER (*p);
4412
b99747ae
CZ		 4413 /* 2nd: get major opcode. */
4414 if (*input_line_pointer != ',')
4415 {
4416 as_bad (_("expected comma after instruction name"));
4417 ignore_rest_of_line ();
4418 return;
4419 }
4420 input_line_pointer++;
4421 major_opcode = get_absolute_expression ();
4422
4423 /* 3rd: get sub-opcode. */
4424 SKIP_WHITESPACE ();
4425
4426 if (*input_line_pointer != ',')
4427 {
4428 as_bad (_("expected comma after major opcode"));
4429 ignore_rest_of_line ();
4430 return;
4431 }
4432 input_line_pointer++;
4433 sub_opcode = get_absolute_expression ();
4434
4435 /* 4th: get suffix class. */
4436 SKIP_WHITESPACE ();
4437
4438 if (*input_line_pointer != ',')
4439 {
4440 as_bad ("expected comma after sub opcode");
4441 ignore_rest_of_line ();
4442 return;
4443 }
4444 input_line_pointer++;
4445
4446 while (1)
4447 {
4448 SKIP_WHITESPACE ();
4449
4450 for (i = 0; i < ARRAY_SIZE (suffixclass); i++)
4451 {
4452 if (!strncmp (suffixclass[i].name, input_line_pointer,
4453 suffixclass[i].len))
4454 {
c810e0b8 4455 suffix_class |= suffixclass[i].attr_class;
b99747ae
CZ		 4456 input_line_pointer += suffixclass[i].len;
4457 break;
4458 }
4459 }
4460
4461 if (i == ARRAY_SIZE (suffixclass))
4462 {
4463 as_bad ("invalid suffix class");
4464 ignore_rest_of_line ();
4465 return;
4466 }
4467
4468 SKIP_WHITESPACE ();
4469
4470 if (*input_line_pointer == '|')
4471 input_line_pointer++;
4472 else
4473 break;
4474 }
4475
4476 /* 5th: get syntax class and syntax class modifiers. */
4477 if (*input_line_pointer != ',')
4478 {
4479 as_bad ("expected comma after suffix class");
4480 ignore_rest_of_line ();
4481 return;
4482 }
4483 input_line_pointer++;
4484
4485 while (1)
4486 {
4487 SKIP_WHITESPACE ();
4488
4489 for (i = 0; i < ARRAY_SIZE (syntaxclassmod); i++)
4490 {
4491 if (!strncmp (syntaxclassmod[i].name,
4492 input_line_pointer,
4493 syntaxclassmod[i].len))
4494 {
c810e0b8 4495 syntax_class_modifiers |= syntaxclassmod[i].attr_class;
b99747ae
CZ		 4496 input_line_pointer += syntaxclassmod[i].len;
4497 break;
4498 }
4499 }
4500
4501 if (i == ARRAY_SIZE (syntaxclassmod))
4502 {
4503 for (i = 0; i < ARRAY_SIZE (syntaxclass); i++)
4504 {
4505 if (!strncmp (syntaxclass[i].name,
4506 input_line_pointer,
4507 syntaxclass[i].len))
4508 {
c810e0b8 4509 syntax_class |= syntaxclass[i].attr_class;
b99747ae
CZ		 4510 input_line_pointer += syntaxclass[i].len;
4511 break;
4512 }
4513 }
4514
4515 if (i == ARRAY_SIZE (syntaxclass))
4516 {
4517 as_bad ("missing syntax class");
4518 ignore_rest_of_line ();
4519 return;
4520 }
4521 }
4522
4523 SKIP_WHITESPACE ();
4524
4525 if (*input_line_pointer == '|')
4526 input_line_pointer++;
4527 else
4528 break;
4529 }
4530
4531 demand_empty_rest_of_line ();
4532
4533 einsn->name = insn_name;
4534 einsn->major = major_opcode;
4535 einsn->minor = sub_opcode;
4536 einsn->syntax = syntax_class;
4537 einsn->modsyn = syntax_class_modifiers;
4538 einsn->suffix = suffix_class;
4539 einsn->flags = syntax_class
4540 | (syntax_class_modifiers & ARC_OP1_IMM_IMPLIED ? 0x10 : 0);
4541}
4542
4543/* Generate an extension section. */
4544
4545static int
4546arc_set_ext_seg (void)
4547{
4548 if (!arcext_section)
4549 {
4550 arcext_section = subseg_new (".arcextmap", 0);
fd361982 4551 bfd_set_section_flags (arcext_section, SEC_READONLY | SEC_HAS_CONTENTS);
b99747ae
CZ		 4552 }
4553 else
4554 subseg_set (arcext_section, 0);
4555 return 1;
4556}
4557
4558/* Create an extension instruction description in the arc extension
4559 section of the output file.
4560 The structure for an instruction is like this:
4561 [0]: Length of the record.
4562 [1]: Type of the record.
4563
4564 [2]: Major opcode.
4565 [3]: Sub-opcode.
4566 [4]: Syntax (flags).
4567 [5]+ Name instruction.
4568
4569 The sequence is terminated by an empty entry. */
4570
4571static void
4572create_extinst_section (extInstruction_t *einsn)
4573{
4574
4575 segT old_sec = now_seg;
4576 int old_subsec = now_subseg;
4577 char *p;
4578 int name_len = strlen (einsn->name);
4579
4580 arc_set_ext_seg ();
4581
4582 p = frag_more (1);
4583 *p = 5 + name_len + 1;
4584 p = frag_more (1);
4585 *p = EXT_INSTRUCTION;
4586 p = frag_more (1);
4587 *p = einsn->major;
4588 p = frag_more (1);
4589 *p = einsn->minor;
4590 p = frag_more (1);
4591 *p = einsn->flags;
4592 p = frag_more (name_len + 1);
4593 strcpy (p, einsn->name);
4594
4595 subseg_set (old_sec, old_subsec);
4596}
4597
4598/* Handler .extinstruction pseudo-op. */
4599
4600static void
4601arc_extinsn (int ignore ATTRIBUTE_UNUSED)
4602{
4603 extInstruction_t einsn;
4604 struct arc_opcode *arc_ext_opcodes;
4605 const char *errmsg = NULL;
4606 unsigned char moplow, mophigh;
4607
4608 memset (&einsn, 0, sizeof (einsn));
4609 tokenize_extinsn (&einsn);
4610
4611 /* Check if the name is already used. */
4612 if (arc_find_opcode (einsn.name))
4613 as_warn (_("Pseudocode already used %s"), einsn.name);
4614
4615 /* Check the opcode ranges. */
4616 moplow = 0x05;
bb65a718
AB		 4617 mophigh = (selected_cpu.flags & (ARC_OPCODE_ARCv2EM
4618 | ARC_OPCODE_ARCv2HS)) ? 0x07 : 0x0a;
b99747ae
CZ		 4619
4620 if ((einsn.major > mophigh) || (einsn.major < moplow))
4621 as_fatal (_("major opcode not in range [0x%02x - 0x%02x]"), moplow, mophigh);
4622
4623 if ((einsn.minor > 0x3f) && (einsn.major != 0x0a)
4624 && (einsn.major != 5) && (einsn.major != 9))
4625 as_fatal (_("minor opcode not in range [0x00 - 0x3f]"));
4626
945e0f82 4627 switch (einsn.syntax & ARC_SYNTAX_MASK)
b99747ae
CZ		 4628 {
4629 case ARC_SYNTAX_3OP:
4630 if (einsn.modsyn & ARC_OP1_IMM_IMPLIED)
4631 as_fatal (_("Improper use of OP1_IMM_IMPLIED"));
4632 break;
4633 case ARC_SYNTAX_2OP:
945e0f82
CZ		 4634 case ARC_SYNTAX_1OP:
4635 case ARC_SYNTAX_NOP:
b99747ae
CZ		 4636 if (einsn.modsyn & ARC_OP1_MUST_BE_IMM)
4637 as_fatal (_("Improper use of OP1_MUST_BE_IMM"));
4638 break;
4639 default:
4640 break;
4641 }
4642
bb65a718 4643 arc_ext_opcodes = arcExtMap_genOpcode (&einsn, selected_cpu.flags, &errmsg);
b99747ae
CZ		 4644 if (arc_ext_opcodes == NULL)
4645 {
4646 if (errmsg)
4647 as_fatal ("%s", errmsg);
4648 else
4649 as_fatal (_("Couldn't generate extension instruction opcodes"));
4650 }
4651 else if (errmsg)
4652 as_warn ("%s", errmsg);
4653
4654 /* Insert the extension instruction. */
4655 arc_insert_opcode ((const struct arc_opcode *) arc_ext_opcodes);
4656
4657 create_extinst_section (&einsn);
4658}
4659
06911889 4660static bfd_boolean
f36e33da
CZ		 4661tokenize_extregister (extRegister_t *ereg, int opertype)
4662{
4663 char *name;
4664 char *mode;
4665 char c;
4666 char *p;
4667 int number, imode = 0;
4668 bfd_boolean isCore_p = (opertype == EXT_CORE_REGISTER) ? TRUE : FALSE;
4669 bfd_boolean isReg_p = (opertype == EXT_CORE_REGISTER
4670 || opertype == EXT_AUX_REGISTER) ? TRUE : FALSE;
4671
4672 /* 1st: get register name. */
4673 SKIP_WHITESPACE ();
4674 p = input_line_pointer;
4675 c = get_symbol_name (&p);
4676
4677 name = xstrdup (p);
4678 restore_line_pointer (c);
4679
4680 /* 2nd: get register number. */
4681 SKIP_WHITESPACE ();
4682
4683 if (*input_line_pointer != ',')
4684 {
06911889 4685 as_bad (_("expected comma after name"));
f36e33da
CZ		 4686 ignore_rest_of_line ();
4687 free (name);
06911889 4688 return FALSE;
f36e33da
CZ		 4689 }
4690 input_line_pointer++;
4691 number = get_absolute_expression ();
4692
06911889
CZ		 4693 if ((number < 0)
4694 && (opertype != EXT_AUX_REGISTER))
f36e33da 4695 {
06911889
CZ		 4696 as_bad (_("%s second argument cannot be a negative number %d"),
4697 isCore_p ? "extCoreRegister's" : "extCondCode's",
4698 number);
f36e33da
CZ		 4699 ignore_rest_of_line ();
4700 free (name);
06911889 4701 return FALSE;
f36e33da
CZ		 4702 }
4703
4704 if (isReg_p)
4705 {
4706 /* 3rd: get register mode. */
4707 SKIP_WHITESPACE ();
4708
4709 if (*input_line_pointer != ',')
4710 {
4711 as_bad (_("expected comma after register number"));
4712 ignore_rest_of_line ();
4713 free (name);
06911889 4714 return FALSE;
f36e33da
CZ		 4715 }
4716
4717 input_line_pointer++;
4718 mode = input_line_pointer;
4719
4720 if (!strncmp (mode, "r|w", 3))
4721 {
4722 imode = 0;
4723 input_line_pointer += 3;
4724 }
4725 else if (!strncmp (mode, "r", 1))
4726 {
4727 imode = ARC_REGISTER_READONLY;
4728 input_line_pointer += 1;
4729 }
4730 else if (strncmp (mode, "w", 1))
4731 {
4732 as_bad (_("invalid mode"));
4733 ignore_rest_of_line ();
4734 free (name);
06911889 4735 return FALSE;
f36e33da
CZ		 4736 }
4737 else
4738 {
4739 imode = ARC_REGISTER_WRITEONLY;
4740 input_line_pointer += 1;
4741 }
4742 }
4743
4744 if (isCore_p)
4745 {
4746 /* 4th: get core register shortcut. */
4747 SKIP_WHITESPACE ();
4748 if (*input_line_pointer != ',')
4749 {
4750 as_bad (_("expected comma after register mode"));
4751 ignore_rest_of_line ();
4752 free (name);
06911889 4753 return FALSE;
f36e33da
CZ		 4754 }
4755
4756 input_line_pointer++;
4757
4758 if (!strncmp (input_line_pointer, "cannot_shortcut", 15))
4759 {
4760 imode |= ARC_REGISTER_NOSHORT_CUT;
4761 input_line_pointer += 15;
4762 }
4763 else if (strncmp (input_line_pointer, "can_shortcut", 12))
4764 {
4765 as_bad (_("shortcut designator invalid"));
4766 ignore_rest_of_line ();
4767 free (name);
06911889 4768 return FALSE;
f36e33da
CZ		 4769 }
4770 else
4771 {
4772 input_line_pointer += 12;
4773 }
4774 }
4775 demand_empty_rest_of_line ();
4776
4777 ereg->name = name;
4778 ereg->number = number;
4779 ereg->imode = imode;
06911889 4780 return TRUE;
f36e33da
CZ		 4781}
4782
4783/* Create an extension register/condition description in the arc
4784 extension section of the output file.
4785
4786 The structure for an instruction is like this:
4787 [0]: Length of the record.
4788 [1]: Type of the record.
4789
4790 For core regs and condition codes:
4791 [2]: Value.
4792 [3]+ Name.
4793
33eaf5de 4794 For auxiliary registers:
f36e33da
CZ		 4795 [2..5]: Value.
4796 [6]+ Name
4797
4798 The sequence is terminated by an empty entry. */
4799
4800static void
4801create_extcore_section (extRegister_t *ereg, int opertype)
4802{
4803 segT old_sec = now_seg;
4804 int old_subsec = now_subseg;
4805 char *p;
4806 int name_len = strlen (ereg->name);
4807
4808 arc_set_ext_seg ();
4809
4810 switch (opertype)
4811 {
4812 case EXT_COND_CODE:
4813 case EXT_CORE_REGISTER:
4814 p = frag_more (1);
4815 *p = 3 + name_len + 1;
4816 p = frag_more (1);
4817 *p = opertype;
4818 p = frag_more (1);
4819 *p = ereg->number;
4820 break;
4821 case EXT_AUX_REGISTER:
4822 p = frag_more (1);
4823 *p = 6 + name_len + 1;
4824 p = frag_more (1);
4825 *p = EXT_AUX_REGISTER;
4826 p = frag_more (1);
4827 *p = (ereg->number >> 24) & 0xff;
4828 p = frag_more (1);
4829 *p = (ereg->number >> 16) & 0xff;
4830 p = frag_more (1);
4831 *p = (ereg->number >> 8) & 0xff;
4832 p = frag_more (1);
4833 *p = (ereg->number) & 0xff;
4834 break;
4835 default:
4836 break;
4837 }
4838
4839 p = frag_more (name_len + 1);
4840 strcpy (p, ereg->name);
4841
4842 subseg_set (old_sec, old_subsec);
4843}
4844
4845/* Handler .extCoreRegister pseudo-op. */
4846
4847static void
4848arc_extcorereg (int opertype)
4849{
4850 extRegister_t ereg;
4851 struct arc_aux_reg *auxr;
4852 const char *retval;
4853 struct arc_flag_operand *ccode;
4854
4855 memset (&ereg, 0, sizeof (ereg));
06911889
CZ		 4856 if (!tokenize_extregister (&ereg, opertype))
4857 return;
f36e33da
CZ		 4858
4859 switch (opertype)
4860 {
4861 case EXT_CORE_REGISTER:
4862 /* Core register. */
4863 if (ereg.number > 60)
4864 as_bad (_("core register %s value (%d) too large"), ereg.name,
4865 ereg.number);
4866 declare_register (ereg.name, ereg.number);
4867 break;
4868 case EXT_AUX_REGISTER:
4869 /* Auxiliary register. */
add39d23 4870 auxr = XNEW (struct arc_aux_reg);
f36e33da 4871 auxr->name = ereg.name;
bb65a718 4872 auxr->cpu = selected_cpu.flags;
f36e33da
CZ		 4873 auxr->subclass = NONE;
4874 auxr->address = ereg.number;
4875 retval = hash_insert (arc_aux_hash, auxr->name, (void *) auxr);
4876 if (retval)
4877 as_fatal (_("internal error: can't hash aux register '%s': %s"),
4878 auxr->name, retval);
4879 break;
4880 case EXT_COND_CODE:
4881 /* Condition code. */
4882 if (ereg.number > 31)
4883 as_bad (_("condition code %s value (%d) too large"), ereg.name,
4884 ereg.number);
4885 ext_condcode.size ++;
4886 ext_condcode.arc_ext_condcode =
add39d23
TS		 4887 XRESIZEVEC (struct arc_flag_operand, ext_condcode.arc_ext_condcode,
4888 ext_condcode.size + 1);
f36e33da
CZ		 4889 if (ext_condcode.arc_ext_condcode == NULL)
4890 as_fatal (_("Virtual memory exhausted"));
4891
4892 ccode = ext_condcode.arc_ext_condcode + ext_condcode.size - 1;
4893 ccode->name = ereg.name;
4894 ccode->code = ereg.number;
4895 ccode->bits = 5;
4896 ccode->shift = 0;
4897 ccode->favail = 0; /* not used. */
4898 ccode++;
4899 memset (ccode, 0, sizeof (struct arc_flag_operand));
4900 break;
4901 default:
4902 as_bad (_("Unknown extension"));
4903 break;
4904 }
4905 create_extcore_section (&ereg, opertype);
4906}
4907
53a346d8
CZ		 4908/* Parse a .arc_attribute directive. */
4909
4910static void
4911arc_attribute (int ignored ATTRIBUTE_UNUSED)
4912{
4913 int tag = obj_elf_vendor_attribute (OBJ_ATTR_PROC);
4914
4915 if (tag < NUM_KNOWN_OBJ_ATTRIBUTES)
4916 attributes_set_explicitly[tag] = TRUE;
4917}
4918
4919/* Set an attribute if it has not already been set by the user. */
4920
4921static void
4922arc_set_attribute_int (int tag, int value)
4923{
4924 if (tag < 1
4925 || tag >= NUM_KNOWN_OBJ_ATTRIBUTES
4926 || !attributes_set_explicitly[tag])
4927 bfd_elf_add_proc_attr_int (stdoutput, tag, value);
4928}
4929
4930static void
4931arc_set_attribute_string (int tag, const char *value)
4932{
4933 if (tag < 1
4934 || tag >= NUM_KNOWN_OBJ_ATTRIBUTES
4935 || !attributes_set_explicitly[tag])
4936 bfd_elf_add_proc_attr_string (stdoutput, tag, value);
4937}
4938
4939/* Allocate and concatenate two strings. s1 can be NULL but not
4940 s2. s1 pointer is freed at end of this procedure. */
4941
4942static char *
4943arc_stralloc (char * s1, const char * s2)
4944{
4945 char * p;
4946 int len = 0;
4947
4948 if (s1)
4949 len = strlen (s1) + 1;
4950
4951 /* Only s1 can be null. */
4952 gas_assert (s2);
4953 len += strlen (s2) + 1;
4954
4955 p = (char *) xmalloc (len);
4956 if (p == NULL)
4957 as_fatal (_("Virtual memory exhausted"));
4958
4959 if (s1)
4960 {
4961 strcpy (p, s1);
4962 strcat (p, ",");
4963 strcat (p, s2);
4964 free (s1);
4965 }
4966 else
4967 strcpy (p, s2);
4968
4969 return p;
4970}
4971
4972/* Set the public ARC object attributes. */
4973
4974static void
4975arc_set_public_attributes (void)
4976{
4977 int base = 0;
4978 char *s = NULL;
4979 unsigned int i;
4980
4981 /* Tag_ARC_CPU_name. */
4982 arc_set_attribute_string (Tag_ARC_CPU_name, selected_cpu.name);
4983
4984 /* Tag_ARC_CPU_base. */
4985 switch (selected_cpu.eflags & EF_ARC_MACH_MSK)
4986 {
4987 case E_ARC_MACH_ARC600:
4988 case E_ARC_MACH_ARC601:
4989 base = TAG_CPU_ARC6xx;
4990 break;
4991 case E_ARC_MACH_ARC700:
4992 base = TAG_CPU_ARC7xx;
4993 break;
4994 case EF_ARC_CPU_ARCV2EM:
4995 base = TAG_CPU_ARCEM;
4996 break;
4997 case EF_ARC_CPU_ARCV2HS:
4998 base = TAG_CPU_ARCHS;
4999 break;
5000 default:
5001 base = 0;
5002 break;
5003 }
5004 if (attributes_set_explicitly[Tag_ARC_CPU_base]
5005 && (base != bfd_elf_get_obj_attr_int (stdoutput, OBJ_ATTR_PROC,
5006 Tag_ARC_CPU_base)))
5007 as_warn (_("Overwrite explicitly set Tag_ARC_CPU_base"));
5008 bfd_elf_add_proc_attr_int (stdoutput, Tag_ARC_CPU_base, base);
5009
5010 /* Tag_ARC_ABI_osver. */
5011 if (attributes_set_explicitly[Tag_ARC_ABI_osver])
5012 {
5013 int val = bfd_elf_get_obj_attr_int (stdoutput, OBJ_ATTR_PROC,
5014 Tag_ARC_ABI_osver);
5015
5016 selected_cpu.eflags = ((selected_cpu.eflags & ~EF_ARC_OSABI_MSK)
5017 | (val & 0x0f << 8));
5018 }
5019 else
5020 {
5021 arc_set_attribute_int (Tag_ARC_ABI_osver, E_ARC_OSABI_CURRENT >> 8);
5022 }
5023
5024 /* Tag_ARC_ISA_config. */
5025 arc_check_feature();
5026
5027 for (i = 0; i < ARRAY_SIZE (feature_list); i++)
5028 if (selected_cpu.features & feature_list[i].feature)
5029 s = arc_stralloc (s, feature_list[i].attr);
5030
5031 if (s)
5032 arc_set_attribute_string (Tag_ARC_ISA_config, s);
5033
5034 /* Tag_ARC_ISA_mpy_option. */
5035 arc_set_attribute_int (Tag_ARC_ISA_mpy_option, mpy_option);
5036
5037 /* Tag_ARC_ABI_pic. */
5038 arc_set_attribute_int (Tag_ARC_ABI_pic, pic_option);
5039
5040 /* Tag_ARC_ABI_sda. */
5041 arc_set_attribute_int (Tag_ARC_ABI_sda, sda_option);
5042
5043 /* Tag_ARC_ABI_tls. */
5044 arc_set_attribute_int (Tag_ARC_ABI_tls, tls_option);
db1e1b45 5045
5046 /* Tag_ARC_ATR_version. */
5047 arc_set_attribute_int (Tag_ARC_ATR_version, 1);
63741043 5048
5049 /* Tag_ARC_ABI_rf16. */
5050 if (attributes_set_explicitly[Tag_ARC_ABI_rf16]
5051 && bfd_elf_get_obj_attr_int (stdoutput, OBJ_ATTR_PROC,
5052 Tag_ARC_ABI_rf16)
5053 && !rf16_only)
5054 {
5055 as_warn (_("Overwrite explicitly set Tag_ARC_ABI_rf16 to full "
5056 "register file"));
5057 bfd_elf_add_proc_attr_int (stdoutput, Tag_ARC_ABI_rf16, 0);
5058 }
53a346d8
CZ		 5059}
5060
5061/* Add the default contents for the .ARC.attributes section. */
5062
5063void
5064arc_md_end (void)
5065{
5066 arc_set_public_attributes ();
5067
5068 if (!bfd_set_arch_mach (stdoutput, bfd_arch_arc, selected_cpu.mach))
5069 as_fatal (_("could not set architecture and machine"));
5070
5071 bfd_set_private_flags (stdoutput, selected_cpu.eflags);
5072}
5073
5074void arc_copy_symbol_attributes (symbolS *dest, symbolS *src)
5075{
5076 ARC_GET_FLAG (dest) = ARC_GET_FLAG (src);
5077}
5078
5079int arc_convert_symbolic_attribute (const char *name)
5080{
5081 static const struct
5082 {
5083 const char * name;
5084 const int tag;
5085 }
5086 attribute_table[] =
5087 {
5088#define T(tag) {#tag, tag}
5089 T (Tag_ARC_PCS_config),
5090 T (Tag_ARC_CPU_base),
5091 T (Tag_ARC_CPU_variation),
5092 T (Tag_ARC_CPU_name),
5093 T (Tag_ARC_ABI_rf16),
5094 T (Tag_ARC_ABI_osver),
5095 T (Tag_ARC_ABI_sda),
5096 T (Tag_ARC_ABI_pic),
5097 T (Tag_ARC_ABI_tls),
5098 T (Tag_ARC_ABI_enumsize),
5099 T (Tag_ARC_ABI_exceptions),
5100 T (Tag_ARC_ABI_double_size),
5101 T (Tag_ARC_ISA_config),
5102 T (Tag_ARC_ISA_apex),
db1e1b45 5103 T (Tag_ARC_ISA_mpy_option),
5104 T (Tag_ARC_ATR_version)
53a346d8
CZ		 5105#undef T
5106 };
5107 unsigned int i;
5108
5109 if (name == NULL)
5110 return -1;
5111
5112 for (i = 0; i < ARRAY_SIZE (attribute_table); i++)
5113 if (streq (name, attribute_table[i].name))
5114 return attribute_table[i].tag;
5115
5116 return -1;
5117}
5118
b99747ae
CZ		 5119/* Local variables:
5120 eval: (c-set-style "gnu")
5121 indent-tabs-mode: t
5122 End: */
GDB Binutils - Deliverables
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