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* elf32-i386.c (elf_howto_table): Comments.
[deliverable/binutils-gdb.git] / gas / config / tc-i386.c
CommitLineData
252b5132 1/* i386.c -- Assemble code for the Intel 80386
f7e42eb4 2 Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
5db1645b 3 2000, 2001, 2002
47926f60 4 Free Software Foundation, Inc.
252b5132
RH		 5
6 This file is part of GAS, the GNU Assembler.
7
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
11 any later version.
12
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with GAS; see the file COPYING. If not, write to the Free
20 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
21 02111-1307, USA. */
22
47926f60
KH		 23/* Intel 80386 machine specific gas.
24 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
3e73aa7c 25 x86_64 support by Jan Hubicka (jh@suse.cz)
47926f60
KH		 26 Bugs & suggestions are completely welcome. This is free software.
27 Please help us make it better. */
252b5132 28
252b5132 29#include "as.h"
3882b010 30#include "safe-ctype.h"
252b5132 31#include "subsegs.h"
316e2c05 32#include "dwarf2dbg.h"
252b5132
RH		 33#include "opcode/i386.h"
34
252b5132
RH		 35#ifndef REGISTER_WARNINGS
36#define REGISTER_WARNINGS 1
37#endif
38
c3332e24 39#ifndef INFER_ADDR_PREFIX
eecb386c 40#define INFER_ADDR_PREFIX 1
c3332e24
AM		 41#endif
42
252b5132
RH		 43#ifndef SCALE1_WHEN_NO_INDEX
44/* Specifying a scale factor besides 1 when there is no index is
45 futile. eg. `mov (%ebx,2),%al' does exactly the same as
46 `mov (%ebx),%al'. To slavishly follow what the programmer
47 specified, set SCALE1_WHEN_NO_INDEX to 0. */
48#define SCALE1_WHEN_NO_INDEX 1
49#endif
50
29b0f896
AM		 51#ifdef BFD_ASSEMBLER
52#define RELOC_ENUM enum bfd_reloc_code_real
53#else
54#define RELOC_ENUM int
246fcdee 55#endif
29b0f896
AM		 56
57#ifndef DEFAULT_ARCH
58#define DEFAULT_ARCH "i386"
246fcdee 59#endif
252b5132 60
edde18a5
AM		 61#ifndef INLINE
62#if __GNUC__ >= 2
63#define INLINE __inline__
64#else
65#define INLINE
66#endif
67#endif
68
29b0f896
AM		 69static INLINE unsigned int mode_from_disp_size PARAMS ((unsigned int));
70static INLINE int fits_in_signed_byte PARAMS ((offsetT));
71static INLINE int fits_in_unsigned_byte PARAMS ((offsetT));
72static INLINE int fits_in_unsigned_word PARAMS ((offsetT));
73static INLINE int fits_in_signed_word PARAMS ((offsetT));
74static INLINE int fits_in_unsigned_long PARAMS ((offsetT));
75static INLINE int fits_in_signed_long PARAMS ((offsetT));
847f7ad4
AM		 76static int smallest_imm_type PARAMS ((offsetT));
77static offsetT offset_in_range PARAMS ((offsetT, int));
252b5132 78static int add_prefix PARAMS ((unsigned int));
3e73aa7c 79static void set_code_flag PARAMS ((int));
47926f60 80static void set_16bit_gcc_code_flag PARAMS ((int));
252b5132 81static void set_intel_syntax PARAMS ((int));
e413e4e9 82static void set_cpu_arch PARAMS ((int));
29b0f896
AM		 83static char *output_invalid PARAMS ((int c));
84static int i386_operand PARAMS ((char *operand_string));
85static int i386_intel_operand PARAMS ((char *operand_string, int got_a_float));
86static const reg_entry *parse_register PARAMS ((char *reg_string,
87 char **end_op));
88static char *parse_insn PARAMS ((char *, char *));
89static char *parse_operands PARAMS ((char *, const char *));
90static void swap_operands PARAMS ((void));
91static void optimize_imm PARAMS ((void));
92static void optimize_disp PARAMS ((void));
93static int match_template PARAMS ((void));
94static int check_string PARAMS ((void));
95static int process_suffix PARAMS ((void));
96static int check_byte_reg PARAMS ((void));
97static int check_long_reg PARAMS ((void));
98static int check_qword_reg PARAMS ((void));
99static int check_word_reg PARAMS ((void));
100static int finalize_imm PARAMS ((void));
101static int process_operands PARAMS ((void));
102static const seg_entry *build_modrm_byte PARAMS ((void));
103static void output_insn PARAMS ((void));
104static void output_branch PARAMS ((void));
105static void output_jump PARAMS ((void));
106static void output_interseg_jump PARAMS ((void));
107static void output_imm PARAMS ((void));
108static void output_disp PARAMS ((void));
109#ifndef I386COFF
110static void s_bss PARAMS ((int));
252b5132
RH		 111#endif
112
a847613f 113static const char *default_arch = DEFAULT_ARCH;
3e73aa7c 114
252b5132 115/* 'md_assemble ()' gathers together information and puts it into a
47926f60 116 i386_insn. */
252b5132 117
520dc8e8
AM		 118union i386_op
119 {
120 expressionS *disps;
121 expressionS *imms;
122 const reg_entry *regs;
123 };
124
252b5132
RH		 125struct _i386_insn
126 {
47926f60 127 /* TM holds the template for the insn were currently assembling. */
252b5132
RH		 128 template tm;
129
130 /* SUFFIX holds the instruction mnemonic suffix if given.
131 (e.g. 'l' for 'movl') */
132 char suffix;
133
47926f60 134 /* OPERANDS gives the number of given operands. */
252b5132
RH		 135 unsigned int operands;
136
137 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
138 of given register, displacement, memory operands and immediate
47926f60 139 operands. */
252b5132
RH		 140 unsigned int reg_operands, disp_operands, mem_operands, imm_operands;
141
142 /* TYPES [i] is the type (see above #defines) which tells us how to
520dc8e8 143 use OP[i] for the corresponding operand. */
252b5132
RH		 144 unsigned int types[MAX_OPERANDS];
145
520dc8e8
AM		 146 /* Displacement expression, immediate expression, or register for each
147 operand. */
148 union i386_op op[MAX_OPERANDS];
252b5132 149
3e73aa7c
JH		 150 /* Flags for operands. */
151 unsigned int flags[MAX_OPERANDS];
152#define Operand_PCrel 1
153
252b5132 154 /* Relocation type for operand */
f3c180ae 155 RELOC_ENUM reloc[MAX_OPERANDS];
252b5132 156
252b5132
RH		 157 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
158 the base index byte below. */
159 const reg_entry *base_reg;
160 const reg_entry *index_reg;
161 unsigned int log2_scale_factor;
162
163 /* SEG gives the seg_entries of this insn. They are zero unless
47926f60 164 explicit segment overrides are given. */
ce8a8b2f 165 const seg_entry *seg[2];
252b5132
RH		 166
167 /* PREFIX holds all the given prefix opcodes (usually null).
168 PREFIXES is the number of prefix opcodes. */
169 unsigned int prefixes;
170 unsigned char prefix[MAX_PREFIXES];
171
172 /* RM and SIB are the modrm byte and the sib byte where the
173 addressing modes of this insn are encoded. */
174
175 modrm_byte rm;
3e73aa7c 176 rex_byte rex;
252b5132
RH		 177 sib_byte sib;
178 };
179
180typedef struct _i386_insn i386_insn;
181
182/* List of chars besides those in app.c:symbol_chars that can start an
183 operand. Used to prevent the scrubber eating vital white-space. */
184#ifdef LEX_AT
200dbde8 185const char extra_symbol_chars[] = "*%-(@[";
252b5132 186#else
200dbde8 187const char extra_symbol_chars[] = "*%-([";
252b5132
RH		 188#endif
189
29b0f896
AM		 190#if (defined (TE_I386AIX) \
191 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
192 && !defined (TE_LINUX) \
193 && !defined (TE_FreeBSD) \
194 && !defined (TE_NetBSD)))
252b5132 195/* This array holds the chars that always start a comment. If the
ce8a8b2f 196 pre-processor is disabled, these aren't very useful. */
252b5132
RH		 197const char comment_chars[] = "#/";
198#define PREFIX_SEPARATOR '\\'
252b5132
RH		 199
200/* This array holds the chars that only start a comment at the beginning of
201 a line. If the line seems to have the form '# 123 filename'
ce8a8b2f
AM		 202 .line and .file directives will appear in the pre-processed output.
203 Note that input_file.c hand checks for '#' at the beginning of the
252b5132 204 first line of the input file. This is because the compiler outputs
ce8a8b2f
AM		 205 #NO_APP at the beginning of its output.
206 Also note that comments started like this one will always work if
252b5132 207 '/' isn't otherwise defined. */
252b5132 208const char line_comment_chars[] = "";
29b0f896 209
252b5132 210#else
29b0f896
AM		 211/* Putting '/' here makes it impossible to use the divide operator.
212 However, we need it for compatibility with SVR4 systems. */
213const char comment_chars[] = "#";
214#define PREFIX_SEPARATOR '/'
215
252b5132
RH		 216const char line_comment_chars[] = "/";
217#endif
218
63a0b638 219const char line_separator_chars[] = ";";
252b5132 220
ce8a8b2f
AM		 221/* Chars that can be used to separate mant from exp in floating point
222 nums. */
252b5132
RH		 223const char EXP_CHARS[] = "eE";
224
ce8a8b2f
AM		 225/* Chars that mean this number is a floating point constant
226 As in 0f12.456
227 or 0d1.2345e12. */
252b5132
RH		 228const char FLT_CHARS[] = "fFdDxX";
229
ce8a8b2f 230/* Tables for lexical analysis. */
252b5132
RH		 231static char mnemonic_chars[256];
232static char register_chars[256];
233static char operand_chars[256];
234static char identifier_chars[256];
235static char digit_chars[256];
236
ce8a8b2f 237/* Lexical macros. */
252b5132
RH		 238#define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
239#define is_operand_char(x) (operand_chars[(unsigned char) x])
240#define is_register_char(x) (register_chars[(unsigned char) x])
241#define is_space_char(x) ((x) == ' ')
242#define is_identifier_char(x) (identifier_chars[(unsigned char) x])
243#define is_digit_char(x) (digit_chars[(unsigned char) x])
244
ce8a8b2f 245/* All non-digit non-letter charcters that may occur in an operand. */
252b5132
RH		 246static char operand_special_chars[] = "%$-+(,)*._~/<>|&^!:[@]";
247
248/* md_assemble() always leaves the strings it's passed unaltered. To
249 effect this we maintain a stack of saved characters that we've smashed
250 with '\0's (indicating end of strings for various sub-fields of the
47926f60 251 assembler instruction). */
252b5132 252static char save_stack[32];
ce8a8b2f 253static char *save_stack_p;
252b5132
RH		 254#define END_STRING_AND_SAVE(s) \
255 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
256#define RESTORE_END_STRING(s) \
257 do { *(s) = *--save_stack_p; } while (0)
258
47926f60 259/* The instruction we're assembling. */
252b5132
RH		 260static i386_insn i;
261
262/* Possible templates for current insn. */
263static const templates *current_templates;
264
47926f60 265/* Per instruction expressionS buffers: 2 displacements & 2 immediate max. */
252b5132
RH		 266static expressionS disp_expressions[2], im_expressions[2];
267
47926f60
KH		 268/* Current operand we are working on. */
269static int this_operand;
252b5132 270
3e73aa7c
JH		 271/* We support four different modes. FLAG_CODE variable is used to distinguish
272 these. */
273
274enum flag_code {
275 CODE_32BIT,
276 CODE_16BIT,
277 CODE_64BIT };
f3c180ae 278#define NUM_FLAG_CODE ((int) CODE_64BIT + 1)
3e73aa7c
JH		 279
280static enum flag_code flag_code;
281static int use_rela_relocations = 0;
282
283/* The names used to print error messages. */
b77a7acd 284static const char *flag_code_names[] =
3e73aa7c
JH		 285 {
286 "32",
287 "16",
288 "64"
289 };
252b5132 290
47926f60
KH		 291/* 1 for intel syntax,
292 0 if att syntax. */
293static int intel_syntax = 0;
252b5132 294
47926f60
KH		 295/* 1 if register prefix % not required. */
296static int allow_naked_reg = 0;
252b5132 297
47926f60
KH		 298/* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
299 leave, push, and pop instructions so that gcc has the same stack
300 frame as in 32 bit mode. */
301static char stackop_size = '\0';
eecb386c 302
47926f60
KH		 303/* Non-zero to quieten some warnings. */
304static int quiet_warnings = 0;
a38cf1db 305
47926f60
KH		 306/* CPU name. */
307static const char *cpu_arch_name = NULL;
a38cf1db 308
47926f60 309/* CPU feature flags. */
29b0f896 310static unsigned int cpu_arch_flags = CpuUnknownFlags | CpuNo64;
a38cf1db 311
fddf5b5b
AM		 312/* If set, conditional jumps are not automatically promoted to handle
313 larger than a byte offset. */
314static unsigned int no_cond_jump_promotion = 0;
315
29b0f896
AM		 316/* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
317symbolS *GOT_symbol;
318
252b5132 319/* Interface to relax_segment.
fddf5b5b
AM		 320 There are 3 major relax states for 386 jump insns because the
321 different types of jumps add different sizes to frags when we're
322 figuring out what sort of jump to choose to reach a given label. */
252b5132 323
47926f60 324/* Types. */
93c2a809
AM		 325#define UNCOND_JUMP 0
326#define COND_JUMP 1
327#define COND_JUMP86 2
fddf5b5b 328
47926f60 329/* Sizes. */
252b5132
RH		 330#define CODE16 1
331#define SMALL 0
29b0f896 332#define SMALL16 (SMALL | CODE16)
252b5132 333#define BIG 2
29b0f896 334#define BIG16 (BIG | CODE16)
252b5132
RH		 335
336#ifndef INLINE
337#ifdef __GNUC__
338#define INLINE __inline__
339#else
340#define INLINE
341#endif
342#endif
343
fddf5b5b
AM		 344#define ENCODE_RELAX_STATE(type, size) \
345 ((relax_substateT) (((type) << 2) | (size)))
346#define TYPE_FROM_RELAX_STATE(s) \
347 ((s) >> 2)
348#define DISP_SIZE_FROM_RELAX_STATE(s) \
349 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
252b5132
RH		 350
351/* This table is used by relax_frag to promote short jumps to long
352 ones where necessary. SMALL (short) jumps may be promoted to BIG
353 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
354 don't allow a short jump in a 32 bit code segment to be promoted to
355 a 16 bit offset jump because it's slower (requires data size
356 prefix), and doesn't work, unless the destination is in the bottom
357 64k of the code segment (The top 16 bits of eip are zeroed). */
358
359const relax_typeS md_relax_table[] =
360{
24eab124
AM		 361 /* The fields are:
362 1) most positive reach of this state,
363 2) most negative reach of this state,
93c2a809 364 3) how many bytes this mode will have in the variable part of the frag
ce8a8b2f 365 4) which index into the table to try if we can't fit into this one. */
252b5132 366
fddf5b5b 367 /* UNCOND_JUMP states. */
93c2a809
AM		 368 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG)},
369 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16)},
370 /* dword jmp adds 4 bytes to frag:
371 0 extra opcode bytes, 4 displacement bytes. */
252b5132 372 {0, 0, 4, 0},
93c2a809
AM		 373 /* word jmp adds 2 byte2 to frag:
374 0 extra opcode bytes, 2 displacement bytes. */
252b5132
RH		 375 {0, 0, 2, 0},
376
93c2a809
AM		 377 /* COND_JUMP states. */
378 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG)},
379 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG16)},
380 /* dword conditionals adds 5 bytes to frag:
381 1 extra opcode byte, 4 displacement bytes. */
382 {0, 0, 5, 0},
fddf5b5b 383 /* word conditionals add 3 bytes to frag:
93c2a809
AM		 384 1 extra opcode byte, 2 displacement bytes. */
385 {0, 0, 3, 0},
386
387 /* COND_JUMP86 states. */
388 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG)},
389 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG16)},
390 /* dword conditionals adds 5 bytes to frag:
391 1 extra opcode byte, 4 displacement bytes. */
392 {0, 0, 5, 0},
393 /* word conditionals add 4 bytes to frag:
394 1 displacement byte and a 3 byte long branch insn. */
395 {0, 0, 4, 0}
252b5132
RH		 396};
397
e413e4e9
AM		 398static const arch_entry cpu_arch[] = {
399 {"i8086", Cpu086 },
400 {"i186", Cpu086|Cpu186 },
401 {"i286", Cpu086|Cpu186|Cpu286 },
402 {"i386", Cpu086|Cpu186|Cpu286|Cpu386 },
403 {"i486", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486 },
404 {"i586", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|CpuMMX },
405 {"i686", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuMMX|CpuSSE },
406 {"pentium", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|CpuMMX },
407 {"pentiumpro",Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuMMX|CpuSSE },
a167610d 408 {"pentium4", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX|CpuSSE|CpuSSE2 },
3e73aa7c
JH		 409 {"k6", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|CpuK6|CpuMMX|Cpu3dnow },
410 {"athlon", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6|CpuAthlon|CpuMMX|Cpu3dnow },
a167610d 411 {"sledgehammer",Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6|CpuAthlon|CpuSledgehammer|CpuMMX|Cpu3dnow|CpuSSE|CpuSSE2 },
e413e4e9
AM		 412 {NULL, 0 }
413};
414
29b0f896
AM		 415const pseudo_typeS md_pseudo_table[] =
416{
417#if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
418 {"align", s_align_bytes, 0},
419#else
420 {"align", s_align_ptwo, 0},
421#endif
422 {"arch", set_cpu_arch, 0},
423#ifndef I386COFF
424 {"bss", s_bss, 0},
425#endif
426 {"ffloat", float_cons, 'f'},
427 {"dfloat", float_cons, 'd'},
428 {"tfloat", float_cons, 'x'},
429 {"value", cons, 2},
430 {"noopt", s_ignore, 0},
431 {"optim", s_ignore, 0},
432 {"code16gcc", set_16bit_gcc_code_flag, CODE_16BIT},
433 {"code16", set_code_flag, CODE_16BIT},
434 {"code32", set_code_flag, CODE_32BIT},
435 {"code64", set_code_flag, CODE_64BIT},
436 {"intel_syntax", set_intel_syntax, 1},
437 {"att_syntax", set_intel_syntax, 0},
438 {"file", dwarf2_directive_file, 0},
439 {"loc", dwarf2_directive_loc, 0},
440 {0, 0, 0}
441};
442
443/* For interface with expression (). */
444extern char *input_line_pointer;
445
446/* Hash table for instruction mnemonic lookup. */
447static struct hash_control *op_hash;
448
449/* Hash table for register lookup. */
450static struct hash_control *reg_hash;
451\f
252b5132
RH		 452void
453i386_align_code (fragP, count)
454 fragS *fragP;
455 int count;
456{
ce8a8b2f
AM		 457 /* Various efficient no-op patterns for aligning code labels.
458 Note: Don't try to assemble the instructions in the comments.
459 0L and 0w are not legal. */
252b5132
RH		 460 static const char f32_1[] =
461 {0x90}; /* nop */
462 static const char f32_2[] =
463 {0x89,0xf6}; /* movl %esi,%esi */
464 static const char f32_3[] =
465 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
466 static const char f32_4[] =
467 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
468 static const char f32_5[] =
469 {0x90, /* nop */
470 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
471 static const char f32_6[] =
472 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
473 static const char f32_7[] =
474 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
475 static const char f32_8[] =
476 {0x90, /* nop */
477 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
478 static const char f32_9[] =
479 {0x89,0xf6, /* movl %esi,%esi */
480 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
481 static const char f32_10[] =
482 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
483 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
484 static const char f32_11[] =
485 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
486 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
487 static const char f32_12[] =
488 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
489 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
490 static const char f32_13[] =
491 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
492 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
493 static const char f32_14[] =
494 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
495 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
496 static const char f32_15[] =
497 {0xeb,0x0d,0x90,0x90,0x90,0x90,0x90, /* jmp .+15; lotsa nops */
498 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
c3332e24
AM		 499 static const char f16_3[] =
500 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
252b5132
RH		 501 static const char f16_4[] =
502 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
503 static const char f16_5[] =
504 {0x90, /* nop */
505 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
506 static const char f16_6[] =
507 {0x89,0xf6, /* mov %si,%si */
508 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
509 static const char f16_7[] =
510 {0x8d,0x74,0x00, /* lea 0(%si),%si */
511 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
512 static const char f16_8[] =
513 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
514 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
515 static const char *const f32_patt[] = {
516 f32_1, f32_2, f32_3, f32_4, f32_5, f32_6, f32_7, f32_8,
517 f32_9, f32_10, f32_11, f32_12, f32_13, f32_14, f32_15
518 };
519 static const char *const f16_patt[] = {
c3332e24 520 f32_1, f32_2, f16_3, f16_4, f16_5, f16_6, f16_7, f16_8,
252b5132
RH		 521 f32_15, f32_15, f32_15, f32_15, f32_15, f32_15, f32_15
522 };
523
3e73aa7c
JH		 524 /* ??? We can't use these fillers for x86_64, since they often kills the
525 upper halves. Solve later. */
526 if (flag_code == CODE_64BIT)
527 count = 1;
528
252b5132
RH		 529 if (count > 0 && count <= 15)
530 {
3e73aa7c 531 if (flag_code == CODE_16BIT)
252b5132 532 {
47926f60
KH		 533 memcpy (fragP->fr_literal + fragP->fr_fix,
534 f16_patt[count - 1], count);
535 if (count > 8)
536 /* Adjust jump offset. */
252b5132
RH		 537 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
538 }
539 else
47926f60
KH		 540 memcpy (fragP->fr_literal + fragP->fr_fix,
541 f32_patt[count - 1], count);
252b5132
RH		 542 fragP->fr_var = count;
543 }
544}
545
252b5132
RH		 546static INLINE unsigned int
547mode_from_disp_size (t)
548 unsigned int t;
549{
3e73aa7c 550 return (t & Disp8) ? 1 : (t & (Disp16 | Disp32 | Disp32S)) ? 2 : 0;
252b5132
RH		 551}
552
553static INLINE int
554fits_in_signed_byte (num)
847f7ad4 555 offsetT num;
252b5132
RH		 556{
557 return (num >= -128) && (num <= 127);
47926f60 558}
252b5132
RH		 559
560static INLINE int
561fits_in_unsigned_byte (num)
847f7ad4 562 offsetT num;
252b5132
RH		 563{
564 return (num & 0xff) == num;
47926f60 565}
252b5132
RH		 566
567static INLINE int
568fits_in_unsigned_word (num)
847f7ad4 569 offsetT num;
252b5132
RH		 570{
571 return (num & 0xffff) == num;
47926f60 572}
252b5132
RH		 573
574static INLINE int
575fits_in_signed_word (num)
847f7ad4 576 offsetT num;
252b5132
RH		 577{
578 return (-32768 <= num) && (num <= 32767);
47926f60 579}
3e73aa7c
JH		 580static INLINE int
581fits_in_signed_long (num)
582 offsetT num ATTRIBUTE_UNUSED;
583{
584#ifndef BFD64
585 return 1;
586#else
587 return (!(((offsetT) -1 << 31) & num)
588 || (((offsetT) -1 << 31) & num) == ((offsetT) -1 << 31));
589#endif
590} /* fits_in_signed_long() */
591static INLINE int
592fits_in_unsigned_long (num)
593 offsetT num ATTRIBUTE_UNUSED;
594{
595#ifndef BFD64
596 return 1;
597#else
598 return (num & (((offsetT) 2 << 31) - 1)) == num;
599#endif
600} /* fits_in_unsigned_long() */
252b5132
RH		 601
602static int
603smallest_imm_type (num)
847f7ad4 604 offsetT num;
252b5132 605{
a847613f 606 if (cpu_arch_flags != (Cpu086 | Cpu186 | Cpu286 | Cpu386 | Cpu486 | CpuNo64))
e413e4e9
AM		 607 {
608 /* This code is disabled on the 486 because all the Imm1 forms
609 in the opcode table are slower on the i486. They're the
610 versions with the implicitly specified single-position
611 displacement, which has another syntax if you really want to
612 use that form. */
613 if (num == 1)
3e73aa7c 614 return Imm1 | Imm8 | Imm8S | Imm16 | Imm32 | Imm32S | Imm64;
e413e4e9 615 }
252b5132 616 return (fits_in_signed_byte (num)
3e73aa7c 617 ? (Imm8S | Imm8 | Imm16 | Imm32 | Imm32S | Imm64)
252b5132 618 : fits_in_unsigned_byte (num)
3e73aa7c 619 ? (Imm8 | Imm16 | Imm32 | Imm32S | Imm64)
252b5132 620 : (fits_in_signed_word (num) || fits_in_unsigned_word (num))
3e73aa7c
JH		 621 ? (Imm16 | Imm32 | Imm32S | Imm64)
622 : fits_in_signed_long (num)
623 ? (Imm32 | Imm32S | Imm64)
624 : fits_in_unsigned_long (num)
625 ? (Imm32 | Imm64)
626 : Imm64);
47926f60 627}
252b5132 628
847f7ad4
AM		 629static offsetT
630offset_in_range (val, size)
631 offsetT val;
632 int size;
633{
508866be 634 addressT mask;
ba2adb93 635
847f7ad4
AM		 636 switch (size)
637 {
508866be
L		 638 case 1: mask = ((addressT) 1 << 8) - 1; break;
639 case 2: mask = ((addressT) 1 << 16) - 1; break;
3b0ec529 640 case 4: mask = ((addressT) 2 << 31) - 1; break;
3e73aa7c
JH		 641#ifdef BFD64
642 case 8: mask = ((addressT) 2 << 63) - 1; break;
643#endif
47926f60 644 default: abort ();
847f7ad4
AM		 645 }
646
ba2adb93 647 /* If BFD64, sign extend val. */
3e73aa7c
JH		 648 if (!use_rela_relocations)
649 if ((val & ~(((addressT) 2 << 31) - 1)) == 0)
650 val = (val ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
ba2adb93 651
47926f60 652 if ((val & ~mask) != 0 && (val & ~mask) != ~mask)
847f7ad4
AM		 653 {
654 char buf1[40], buf2[40];
655
656 sprint_value (buf1, val);
657 sprint_value (buf2, val & mask);
658 as_warn (_("%s shortened to %s"), buf1, buf2);
659 }
660 return val & mask;
661}
662
252b5132
RH		 663/* Returns 0 if attempting to add a prefix where one from the same
664 class already exists, 1 if non rep/repne added, 2 if rep/repne
665 added. */
666static int
667add_prefix (prefix)
668 unsigned int prefix;
669{
670 int ret = 1;
671 int q;
672
29b0f896
AM		 673 if (prefix >= REX_OPCODE && prefix < REX_OPCODE + 16
674 && flag_code == CODE_64BIT)
3e73aa7c
JH		 675 q = REX_PREFIX;
676 else
677 switch (prefix)
678 {
679 default:
680 abort ();
681
682 case CS_PREFIX_OPCODE:
683 case DS_PREFIX_OPCODE:
684 case ES_PREFIX_OPCODE:
685 case FS_PREFIX_OPCODE:
686 case GS_PREFIX_OPCODE:
687 case SS_PREFIX_OPCODE:
688 q = SEG_PREFIX;
689 break;
252b5132 690
3e73aa7c
JH		 691 case REPNE_PREFIX_OPCODE:
692 case REPE_PREFIX_OPCODE:
693 ret = 2;
694 /* fall thru */
695 case LOCK_PREFIX_OPCODE:
696 q = LOCKREP_PREFIX;
697 break;
252b5132 698
3e73aa7c
JH		 699 case FWAIT_OPCODE:
700 q = WAIT_PREFIX;
701 break;
252b5132 702
3e73aa7c
JH		 703 case ADDR_PREFIX_OPCODE:
704 q = ADDR_PREFIX;
705 break;
252b5132 706
3e73aa7c
JH		 707 case DATA_PREFIX_OPCODE:
708 q = DATA_PREFIX;
709 break;
710 }
252b5132 711
29b0f896 712 if (i.prefix[q] != 0)
252b5132
RH		 713 {
714 as_bad (_("same type of prefix used twice"));
715 return 0;
716 }
717
718 i.prefixes += 1;
719 i.prefix[q] = prefix;
720 return ret;
721}
722
723static void
3e73aa7c 724set_code_flag (value)
e5cb08ac 725 int value;
eecb386c 726{
3e73aa7c
JH		 727 flag_code = value;
728 cpu_arch_flags &= ~(Cpu64 | CpuNo64);
729 cpu_arch_flags |= (flag_code == CODE_64BIT ? Cpu64 : CpuNo64);
730 if (value == CODE_64BIT && !(cpu_arch_flags & CpuSledgehammer))
731 {
732 as_bad (_("64bit mode not supported on this CPU."));
733 }
734 if (value == CODE_32BIT && !(cpu_arch_flags & Cpu386))
735 {
736 as_bad (_("32bit mode not supported on this CPU."));
737 }
eecb386c
AM		 738 stackop_size = '\0';
739}
740
741static void
3e73aa7c
JH		 742set_16bit_gcc_code_flag (new_code_flag)
743 int new_code_flag;
252b5132 744{
3e73aa7c
JH		 745 flag_code = new_code_flag;
746 cpu_arch_flags &= ~(Cpu64 | CpuNo64);
747 cpu_arch_flags |= (flag_code == CODE_64BIT ? Cpu64 : CpuNo64);
748 stackop_size = 'l';
252b5132
RH		 749}
750
751static void
752set_intel_syntax (syntax_flag)
eecb386c 753 int syntax_flag;
252b5132
RH		 754{
755 /* Find out if register prefixing is specified. */
756 int ask_naked_reg = 0;
757
758 SKIP_WHITESPACE ();
29b0f896 759 if (!is_end_of_line[(unsigned char) *input_line_pointer])
252b5132
RH		 760 {
761 char *string = input_line_pointer;
762 int e = get_symbol_end ();
763
47926f60 764 if (strcmp (string, "prefix") == 0)
252b5132 765 ask_naked_reg = 1;
47926f60 766 else if (strcmp (string, "noprefix") == 0)
252b5132
RH		 767 ask_naked_reg = -1;
768 else
d0b47220 769 as_bad (_("bad argument to syntax directive."));
252b5132
RH		 770 *input_line_pointer = e;
771 }
772 demand_empty_rest_of_line ();
c3332e24 773
252b5132
RH		 774 intel_syntax = syntax_flag;
775
776 if (ask_naked_reg == 0)
777 {
778#ifdef BFD_ASSEMBLER
779 allow_naked_reg = (intel_syntax
24eab124 780 && (bfd_get_symbol_leading_char (stdoutput) != '\0'));
252b5132 781#else
47926f60
KH		 782 /* Conservative default. */
783 allow_naked_reg = 0;
252b5132
RH		 784#endif
785 }
786 else
787 allow_naked_reg = (ask_naked_reg < 0);
788}
789
e413e4e9
AM		 790static void
791set_cpu_arch (dummy)
47926f60 792 int dummy ATTRIBUTE_UNUSED;
e413e4e9 793{
47926f60 794 SKIP_WHITESPACE ();
e413e4e9 795
29b0f896 796 if (!is_end_of_line[(unsigned char) *input_line_pointer])
e413e4e9
AM		 797 {
798 char *string = input_line_pointer;
799 int e = get_symbol_end ();
800 int i;
801
802 for (i = 0; cpu_arch[i].name; i++)
803 {
804 if (strcmp (string, cpu_arch[i].name) == 0)
805 {
806 cpu_arch_name = cpu_arch[i].name;
fddf5b5b
AM		 807 cpu_arch_flags = (cpu_arch[i].flags
808 | (flag_code == CODE_64BIT ? Cpu64 : CpuNo64));
e413e4e9
AM		 809 break;
810 }
811 }
812 if (!cpu_arch[i].name)
813 as_bad (_("no such architecture: `%s'"), string);
814
815 *input_line_pointer = e;
816 }
817 else
818 as_bad (_("missing cpu architecture"));
819
fddf5b5b
AM		 820 no_cond_jump_promotion = 0;
821 if (*input_line_pointer == ','
29b0f896 822 && !is_end_of_line[(unsigned char) input_line_pointer[1]])
fddf5b5b
AM		 823 {
824 char *string = ++input_line_pointer;
825 int e = get_symbol_end ();
826
827 if (strcmp (string, "nojumps") == 0)
828 no_cond_jump_promotion = 1;
829 else if (strcmp (string, "jumps") == 0)
830 ;
831 else
832 as_bad (_("no such architecture modifier: `%s'"), string);
833
834 *input_line_pointer = e;
835 }
836
e413e4e9
AM		 837 demand_empty_rest_of_line ();
838}
839
b9d79e03
JH		 840#ifdef BFD_ASSEMBLER
841unsigned long
842i386_mach ()
843{
844 if (!strcmp (default_arch, "x86_64"))
845 return bfd_mach_x86_64;
846 else if (!strcmp (default_arch, "i386"))
847 return bfd_mach_i386_i386;
848 else
849 as_fatal (_("Unknown architecture"));
850}
851#endif
852\f
252b5132
RH		 853void
854md_begin ()
855{
856 const char *hash_err;
857
47926f60 858 /* Initialize op_hash hash table. */
252b5132
RH		 859 op_hash = hash_new ();
860
861 {
29b0f896
AM		 862 const template *optab;
863 templates *core_optab;
252b5132 864
47926f60
KH		 865 /* Setup for loop. */
866 optab = i386_optab;
252b5132
RH		 867 core_optab = (templates *) xmalloc (sizeof (templates));
868 core_optab->start = optab;
869
870 while (1)
871 {
872 ++optab;
873 if (optab->name == NULL
874 || strcmp (optab->name, (optab - 1)->name) != 0)
875 {
876 /* different name --> ship out current template list;
47926f60 877 add to hash table; & begin anew. */
252b5132
RH		 878 core_optab->end = optab;
879 hash_err = hash_insert (op_hash,
880 (optab - 1)->name,
881 (PTR) core_optab);
882 if (hash_err)
883 {
252b5132
RH		 884 as_fatal (_("Internal Error: Can't hash %s: %s"),
885 (optab - 1)->name,
886 hash_err);
887 }
888 if (optab->name == NULL)
889 break;
890 core_optab = (templates *) xmalloc (sizeof (templates));
891 core_optab->start = optab;
892 }
893 }
894 }
895
47926f60 896 /* Initialize reg_hash hash table. */
252b5132
RH		 897 reg_hash = hash_new ();
898 {
29b0f896 899 const reg_entry *regtab;
252b5132
RH		 900
901 for (regtab = i386_regtab;
902 regtab < i386_regtab + sizeof (i386_regtab) / sizeof (i386_regtab[0]);
903 regtab++)
904 {
905 hash_err = hash_insert (reg_hash, regtab->reg_name, (PTR) regtab);
906 if (hash_err)
3e73aa7c
JH		 907 as_fatal (_("Internal Error: Can't hash %s: %s"),
908 regtab->reg_name,
909 hash_err);
252b5132
RH		 910 }
911 }
912
47926f60 913 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
252b5132 914 {
29b0f896
AM		 915 int c;
916 char *p;
252b5132
RH		 917
918 for (c = 0; c < 256; c++)
919 {
3882b010 920 if (ISDIGIT (c))
252b5132
RH		 921 {
922 digit_chars[c] = c;
923 mnemonic_chars[c] = c;
924 register_chars[c] = c;
925 operand_chars[c] = c;
926 }
3882b010 927 else if (ISLOWER (c))
252b5132
RH		 928 {
929 mnemonic_chars[c] = c;
930 register_chars[c] = c;
931 operand_chars[c] = c;
932 }
3882b010 933 else if (ISUPPER (c))
252b5132 934 {
3882b010 935 mnemonic_chars[c] = TOLOWER (c);
252b5132
RH		 936 register_chars[c] = mnemonic_chars[c];
937 operand_chars[c] = c;
938 }
939
3882b010 940 if (ISALPHA (c) || ISDIGIT (c))
252b5132
RH		 941 identifier_chars[c] = c;
942 else if (c >= 128)
943 {
944 identifier_chars[c] = c;
945 operand_chars[c] = c;
946 }
947 }
948
949#ifdef LEX_AT
950 identifier_chars['@'] = '@';
951#endif
252b5132
RH		 952 digit_chars['-'] = '-';
953 identifier_chars['_'] = '_';
954 identifier_chars['.'] = '.';
955
956 for (p = operand_special_chars; *p != '\0'; p++)
957 operand_chars[(unsigned char) *p] = *p;
958 }
959
960#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
961 if (OUTPUT_FLAVOR == bfd_target_elf_flavour)
962 {
963 record_alignment (text_section, 2);
964 record_alignment (data_section, 2);
965 record_alignment (bss_section, 2);
966 }
967#endif
968}
969
970void
971i386_print_statistics (file)
972 FILE *file;
973{
974 hash_print_statistics (file, "i386 opcode", op_hash);
975 hash_print_statistics (file, "i386 register", reg_hash);
976}
977\f
252b5132
RH		 978#ifdef DEBUG386
979
ce8a8b2f 980/* Debugging routines for md_assemble. */
252b5132
RH		 981static void pi PARAMS ((char *, i386_insn *));
982static void pte PARAMS ((template *));
983static void pt PARAMS ((unsigned int));
984static void pe PARAMS ((expressionS *));
985static void ps PARAMS ((symbolS *));
986
987static void
988pi (line, x)
989 char *line;
990 i386_insn *x;
991{
09f131f2 992 unsigned int i;
252b5132
RH		 993
994 fprintf (stdout, "%s: template ", line);
995 pte (&x->tm);
09f131f2
JH		 996 fprintf (stdout, " address: base %s index %s scale %x\n",
997 x->base_reg ? x->base_reg->reg_name : "none",
998 x->index_reg ? x->index_reg->reg_name : "none",
999 x->log2_scale_factor);
1000 fprintf (stdout, " modrm: mode %x reg %x reg/mem %x\n",
252b5132 1001 x->rm.mode, x->rm.reg, x->rm.regmem);
09f131f2
JH		 1002 fprintf (stdout, " sib: base %x index %x scale %x\n",
1003 x->sib.base, x->sib.index, x->sib.scale);
1004 fprintf (stdout, " rex: 64bit %x extX %x extY %x extZ %x\n",
29b0f896
AM		 1005 (x->rex & REX_MODE64) != 0,
1006 (x->rex & REX_EXTX) != 0,
1007 (x->rex & REX_EXTY) != 0,
1008 (x->rex & REX_EXTZ) != 0);
252b5132
RH		 1009 for (i = 0; i < x->operands; i++)
1010 {
1011 fprintf (stdout, " #%d: ", i + 1);
1012 pt (x->types[i]);
1013 fprintf (stdout, "\n");
1014 if (x->types[i]
3f4438ab 1015 & (Reg | SReg2 | SReg3 | Control | Debug | Test | RegMMX | RegXMM))
520dc8e8 1016 fprintf (stdout, "%s\n", x->op[i].regs->reg_name);
252b5132 1017 if (x->types[i] & Imm)
520dc8e8 1018 pe (x->op[i].imms);
252b5132 1019 if (x->types[i] & Disp)
520dc8e8 1020 pe (x->op[i].disps);
252b5132
RH		 1021 }
1022}
1023
1024static void
1025pte (t)
1026 template *t;
1027{
09f131f2 1028 unsigned int i;
252b5132 1029 fprintf (stdout, " %d operands ", t->operands);
47926f60 1030 fprintf (stdout, "opcode %x ", t->base_opcode);
252b5132
RH		 1031 if (t->extension_opcode != None)
1032 fprintf (stdout, "ext %x ", t->extension_opcode);
1033 if (t->opcode_modifier & D)
1034 fprintf (stdout, "D");
1035 if (t->opcode_modifier & W)
1036 fprintf (stdout, "W");
1037 fprintf (stdout, "\n");
1038 for (i = 0; i < t->operands; i++)
1039 {
1040 fprintf (stdout, " #%d type ", i + 1);
1041 pt (t->operand_types[i]);
1042 fprintf (stdout, "\n");
1043 }
1044}
1045
1046static void
1047pe (e)
1048 expressionS *e;
1049{
24eab124 1050 fprintf (stdout, " operation %d\n", e->X_op);
b77ad1d4
AM		 1051 fprintf (stdout, " add_number %ld (%lx)\n",
1052 (long) e->X_add_number, (long) e->X_add_number);
252b5132
RH		 1053 if (e->X_add_symbol)
1054 {
1055 fprintf (stdout, " add_symbol ");
1056 ps (e->X_add_symbol);
1057 fprintf (stdout, "\n");
1058 }
1059 if (e->X_op_symbol)
1060 {
1061 fprintf (stdout, " op_symbol ");
1062 ps (e->X_op_symbol);
1063 fprintf (stdout, "\n");
1064 }
1065}
1066
1067static void
1068ps (s)
1069 symbolS *s;
1070{
1071 fprintf (stdout, "%s type %s%s",
1072 S_GET_NAME (s),
1073 S_IS_EXTERNAL (s) ? "EXTERNAL " : "",
1074 segment_name (S_GET_SEGMENT (s)));
1075}
1076
1077struct type_name
1078 {
1079 unsigned int mask;
1080 char *tname;
1081 }
1082
29b0f896 1083static const type_names[] =
252b5132
RH		 1084{
1085 { Reg8, "r8" },
1086 { Reg16, "r16" },
1087 { Reg32, "r32" },
09f131f2 1088 { Reg64, "r64" },
252b5132
RH		 1089 { Imm8, "i8" },
1090 { Imm8S, "i8s" },
1091 { Imm16, "i16" },
1092 { Imm32, "i32" },
09f131f2
JH		 1093 { Imm32S, "i32s" },
1094 { Imm64, "i64" },
252b5132
RH		 1095 { Imm1, "i1" },
1096 { BaseIndex, "BaseIndex" },
1097 { Disp8, "d8" },
1098 { Disp16, "d16" },
1099 { Disp32, "d32" },
09f131f2
JH		 1100 { Disp32S, "d32s" },
1101 { Disp64, "d64" },
252b5132
RH		 1102 { InOutPortReg, "InOutPortReg" },
1103 { ShiftCount, "ShiftCount" },
1104 { Control, "control reg" },
1105 { Test, "test reg" },
1106 { Debug, "debug reg" },
1107 { FloatReg, "FReg" },
1108 { FloatAcc, "FAcc" },
1109 { SReg2, "SReg2" },
1110 { SReg3, "SReg3" },
1111 { Acc, "Acc" },
1112 { JumpAbsolute, "Jump Absolute" },
1113 { RegMMX, "rMMX" },
3f4438ab 1114 { RegXMM, "rXMM" },
252b5132
RH		 1115 { EsSeg, "es" },
1116 { 0, "" }
1117};
1118
1119static void
1120pt (t)
1121 unsigned int t;
1122{
29b0f896 1123 const struct type_name *ty;
252b5132 1124
09f131f2
JH		 1125 for (ty = type_names; ty->mask; ty++)
1126 if (t & ty->mask)
1127 fprintf (stdout, "%s, ", ty->tname);
252b5132
RH		 1128 fflush (stdout);
1129}
1130
1131#endif /* DEBUG386 */
1132\f
1133int
1134tc_i386_force_relocation (fixp)
1135 struct fix *fixp;
1136{
1137#ifdef BFD_ASSEMBLER
1138 if (fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT
1139 || fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
1140 return 1;
1141 return 0;
1142#else
ce8a8b2f 1143 /* For COFF. */
f6af82bd 1144 return fixp->fx_r_type == 7;
252b5132
RH		 1145#endif
1146}
1147
1148#ifdef BFD_ASSEMBLER
29b0f896
AM		 1149static bfd_reloc_code_real_type reloc
1150 PARAMS ((int, int, int, bfd_reloc_code_real_type));
252b5132
RH		 1151
1152static bfd_reloc_code_real_type
3e73aa7c 1153reloc (size, pcrel, sign, other)
252b5132
RH		 1154 int size;
1155 int pcrel;
3e73aa7c 1156 int sign;
252b5132
RH		 1157 bfd_reloc_code_real_type other;
1158{
47926f60
KH		 1159 if (other != NO_RELOC)
1160 return other;
252b5132
RH		 1161
1162 if (pcrel)
1163 {
3e73aa7c 1164 if (!sign)
e5cb08ac 1165 as_bad (_("There are no unsigned pc-relative relocations"));
252b5132
RH		 1166 switch (size)
1167 {
1168 case 1: return BFD_RELOC_8_PCREL;
1169 case 2: return BFD_RELOC_16_PCREL;
1170 case 4: return BFD_RELOC_32_PCREL;
1171 }
d0b47220 1172 as_bad (_("can not do %d byte pc-relative relocation"), size);
252b5132
RH		 1173 }
1174 else
1175 {
3e73aa7c 1176 if (sign)
e5cb08ac 1177 switch (size)
3e73aa7c
JH		 1178 {
1179 case 4: return BFD_RELOC_X86_64_32S;
1180 }
1181 else
1182 switch (size)
1183 {
1184 case 1: return BFD_RELOC_8;
1185 case 2: return BFD_RELOC_16;
1186 case 4: return BFD_RELOC_32;
1187 case 8: return BFD_RELOC_64;
1188 }
1189 as_bad (_("can not do %s %d byte relocation"),
1190 sign ? "signed" : "unsigned", size);
252b5132
RH		 1191 }
1192
bfb32b52 1193 abort ();
252b5132
RH		 1194 return BFD_RELOC_NONE;
1195}
1196
47926f60
KH		 1197/* Here we decide which fixups can be adjusted to make them relative to
1198 the beginning of the section instead of the symbol. Basically we need
1199 to make sure that the dynamic relocations are done correctly, so in
1200 some cases we force the original symbol to be used. */
1201
252b5132 1202int
c0c949c7 1203tc_i386_fix_adjustable (fixP)
47926f60 1204 fixS *fixP;
252b5132 1205{
6d249963 1206#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
79d292aa
ILT		 1207 /* Prevent all adjustments to global symbols, or else dynamic
1208 linking will not work correctly. */
b98ef147 1209 if (S_IS_EXTERNAL (fixP->fx_addsy)
3bf057fa
AS		 1210 || S_IS_WEAK (fixP->fx_addsy)
1211 /* Don't adjust pc-relative references to merge sections in 64-bit
1212 mode. */
1213 || (use_rela_relocations
1214 && (S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_MERGE) != 0
1215 && fixP->fx_pcrel))
252b5132
RH		 1216 return 0;
1217#endif
ce8a8b2f 1218 /* adjust_reloc_syms doesn't know about the GOT. */
252b5132
RH		 1219 if (fixP->fx_r_type == BFD_RELOC_386_GOTOFF
1220 || fixP->fx_r_type == BFD_RELOC_386_PLT32
1221 || fixP->fx_r_type == BFD_RELOC_386_GOT32
3e73aa7c
JH		 1222 || fixP->fx_r_type == BFD_RELOC_X86_64_PLT32
1223 || fixP->fx_r_type == BFD_RELOC_X86_64_GOT32
80b3ee89 1224 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCREL
252b5132
RH		 1225 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
1226 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
1227 return 0;
1228 return 1;
1229}
1230#else
ec56dfb4
L		 1231#define reloc(SIZE,PCREL,SIGN,OTHER) 0
1232#define BFD_RELOC_16 0
1233#define BFD_RELOC_32 0
1234#define BFD_RELOC_16_PCREL 0
1235#define BFD_RELOC_32_PCREL 0
1236#define BFD_RELOC_386_PLT32 0
1237#define BFD_RELOC_386_GOT32 0
1238#define BFD_RELOC_386_GOTOFF 0
1239#define BFD_RELOC_X86_64_PLT32 0
1240#define BFD_RELOC_X86_64_GOT32 0
1241#define BFD_RELOC_X86_64_GOTPCREL 0
252b5132
RH		 1242#endif
1243
29b0f896 1244static int intel_float_operand PARAMS ((const char *mnemonic));
b4cac588
AM		 1245
1246static int
252b5132 1247intel_float_operand (mnemonic)
29b0f896 1248 const char *mnemonic;
252b5132 1249{
47926f60 1250 if (mnemonic[0] == 'f' && mnemonic[1] == 'i')
cc5ca5ce 1251 return 2;
252b5132
RH		 1252
1253 if (mnemonic[0] == 'f')
1254 return 1;
1255
1256 return 0;
1257}
1258
1259/* This is the guts of the machine-dependent assembler. LINE points to a
1260 machine dependent instruction. This function is supposed to emit
1261 the frags/bytes it assembles to. */
1262
1263void
1264md_assemble (line)
1265 char *line;
1266{
252b5132 1267 int j;
252b5132
RH		 1268 char mnemonic[MAX_MNEM_SIZE];
1269
47926f60 1270 /* Initialize globals. */
252b5132
RH		 1271 memset (&i, '\0', sizeof (i));
1272 for (j = 0; j < MAX_OPERANDS; j++)
1ae12ab7 1273 i.reloc[j] = NO_RELOC;
252b5132
RH		 1274 memset (disp_expressions, '\0', sizeof (disp_expressions));
1275 memset (im_expressions, '\0', sizeof (im_expressions));
ce8a8b2f 1276 save_stack_p = save_stack;
252b5132
RH		 1277
1278 /* First parse an instruction mnemonic & call i386_operand for the operands.
1279 We assume that the scrubber has arranged it so that line[0] is the valid
47926f60 1280 start of a (possibly prefixed) mnemonic. */
252b5132 1281
29b0f896
AM		 1282 line = parse_insn (line, mnemonic);
1283 if (line == NULL)
1284 return;
252b5132 1285
29b0f896
AM		 1286 line = parse_operands (line, mnemonic);
1287 if (line == NULL)
1288 return;
252b5132 1289
29b0f896
AM		 1290 /* Now we've parsed the mnemonic into a set of templates, and have the
1291 operands at hand. */
1292
1293 /* All intel opcodes have reversed operands except for "bound" and
1294 "enter". We also don't reverse intersegment "jmp" and "call"
1295 instructions with 2 immediate operands so that the immediate segment
1296 precedes the offset, as it does when in AT&T mode. "enter" and the
1297 intersegment "jmp" and "call" instructions are the only ones that
1298 have two immediate operands. */
1299 if (intel_syntax && i.operands > 1
1300 && (strcmp (mnemonic, "bound") != 0)
1301 && !((i.types[0] & Imm) && (i.types[1] & Imm)))
1302 swap_operands ();
1303
1304 if (i.imm_operands)
1305 optimize_imm ();
1306
1307 if (i.disp_operands)
1308 optimize_disp ();
1309
1310 /* Next, we find a template that matches the given insn,
1311 making sure the overlap of the given operands types is consistent
1312 with the template operand types. */
252b5132 1313
29b0f896
AM		 1314 if (!match_template ())
1315 return;
252b5132 1316
29b0f896
AM		 1317 /* Undo SYSV386_COMPAT brokenness when in Intel mode. See i386.h */
1318 if (SYSV386_COMPAT
1319 && intel_syntax
1320 && (i.tm.base_opcode & 0xfffffde0) == 0xdce0)
1321 i.tm.base_opcode ^= FloatR;
24eab124 1322
29b0f896
AM		 1323 if (i.tm.opcode_modifier & FWait)
1324 if (!add_prefix (FWAIT_OPCODE))
1325 return;
252b5132 1326
29b0f896
AM		 1327 /* Check string instruction segment overrides. */
1328 if ((i.tm.opcode_modifier & IsString) != 0 && i.mem_operands != 0)
1329 {
1330 if (!check_string ())
5dd0794d 1331 return;
29b0f896 1332 }
5dd0794d 1333
29b0f896
AM		 1334 if (!process_suffix ())
1335 return;
e413e4e9 1336
29b0f896
AM		 1337 /* Make still unresolved immediate matches conform to size of immediate
1338 given in i.suffix. */
1339 if (!finalize_imm ())
1340 return;
252b5132 1341
29b0f896
AM		 1342 if (i.types[0] & Imm1)
1343 i.imm_operands = 0; /* kludge for shift insns. */
1344 if (i.types[0] & ImplicitRegister)
1345 i.reg_operands--;
1346 if (i.types[1] & ImplicitRegister)
1347 i.reg_operands--;
1348 if (i.types[2] & ImplicitRegister)
1349 i.reg_operands--;
252b5132 1350
29b0f896
AM		 1351 if (i.tm.opcode_modifier & ImmExt)
1352 {
1353 /* These AMD 3DNow! and Intel Katmai New Instructions have an
1354 opcode suffix which is coded in the same place as an 8-bit
1355 immediate field would be. Here we fake an 8-bit immediate
1356 operand from the opcode suffix stored in tm.extension_opcode. */
252b5132 1357
29b0f896 1358 expressionS *exp;
252b5132 1359
29b0f896 1360 assert (i.imm_operands == 0 && i.operands <= 2 && 2 < MAX_OPERANDS);
252b5132 1361
29b0f896
AM		 1362 exp = &im_expressions[i.imm_operands++];
1363 i.op[i.operands].imms = exp;
1364 i.types[i.operands++] = Imm8;
1365 exp->X_op = O_constant;
1366 exp->X_add_number = i.tm.extension_opcode;
1367 i.tm.extension_opcode = None;
1368 }
252b5132 1369
29b0f896
AM		 1370 /* For insns with operands there are more diddles to do to the opcode. */
1371 if (i.operands)
1372 {
1373 if (!process_operands ())
1374 return;
1375 }
1376 else if (!quiet_warnings && (i.tm.opcode_modifier & Ugh) != 0)
1377 {
1378 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
1379 as_warn (_("translating to `%sp'"), i.tm.name);
1380 }
252b5132 1381
29b0f896
AM		 1382 /* Handle conversion of 'int $3' --> special int3 insn. */
1383 if (i.tm.base_opcode == INT_OPCODE && i.op[0].imms->X_add_number == 3)
1384 {
1385 i.tm.base_opcode = INT3_OPCODE;
1386 i.imm_operands = 0;
1387 }
252b5132 1388
29b0f896
AM		 1389 if ((i.tm.opcode_modifier & (Jump | JumpByte | JumpDword))
1390 && i.op[0].disps->X_op == O_constant)
1391 {
1392 /* Convert "jmp constant" (and "call constant") to a jump (call) to
1393 the absolute address given by the constant. Since ix86 jumps and
1394 calls are pc relative, we need to generate a reloc. */
1395 i.op[0].disps->X_add_symbol = &abs_symbol;
1396 i.op[0].disps->X_op = O_symbol;
1397 }
252b5132 1398
29b0f896
AM		 1399 if ((i.tm.opcode_modifier & Rex64) != 0)
1400 i.rex |= REX_MODE64;
252b5132 1401
29b0f896
AM		 1402 /* For 8 bit registers we need an empty rex prefix. Also if the
1403 instruction already has a prefix, we need to convert old
1404 registers to new ones. */
773f551c 1405
29b0f896
AM		 1406 if (((i.types[0] & Reg8) != 0
1407 && (i.op[0].regs->reg_flags & RegRex64) != 0)
1408 || ((i.types[1] & Reg8) != 0
1409 && (i.op[1].regs->reg_flags & RegRex64) != 0)
1410 || (((i.types[0] & Reg8) != 0 || (i.types[1] & Reg8) != 0)
1411 && i.rex != 0))
1412 {
1413 int x;
726c5dcd 1414
29b0f896
AM		 1415 i.rex |= REX_OPCODE;
1416 for (x = 0; x < 2; x++)
1417 {
1418 /* Look for 8 bit operand that uses old registers. */
1419 if ((i.types[x] & Reg8) != 0
1420 && (i.op[x].regs->reg_flags & RegRex64) == 0)
773f551c 1421 {
29b0f896
AM		 1422 /* In case it is "hi" register, give up. */
1423 if (i.op[x].regs->reg_num > 3)
1424 as_bad (_("can't encode register '%%%s' in an instruction requiring REX prefix.\n"),
1425 i.op[x].regs->reg_name);
773f551c 1426
29b0f896
AM		 1427 /* Otherwise it is equivalent to the extended register.
1428 Since the encoding doesn't change this is merely
1429 cosmetic cleanup for debug output. */
1430
1431 i.op[x].regs = i.op[x].regs + 8;
773f551c 1432 }
29b0f896
AM		 1433 }
1434 }
773f551c 1435
29b0f896
AM		 1436 if (i.rex != 0)
1437 add_prefix (REX_OPCODE | i.rex);
1438
1439 /* We are ready to output the insn. */
1440 output_insn ();
1441}
1442
1443static char *
1444parse_insn (line, mnemonic)
1445 char *line;
1446 char *mnemonic;
1447{
1448 char *l = line;
1449 char *token_start = l;
1450 char *mnem_p;
1451
1452 /* Non-zero if we found a prefix only acceptable with string insns. */
1453 const char *expecting_string_instruction = NULL;
45288df1 1454
29b0f896
AM		 1455 while (1)
1456 {
1457 mnem_p = mnemonic;
1458 while ((*mnem_p = mnemonic_chars[(unsigned char) *l]) != 0)
1459 {
1460 mnem_p++;
1461 if (mnem_p >= mnemonic + MAX_MNEM_SIZE)
45288df1 1462 {
29b0f896
AM		 1463 as_bad (_("no such instruction: `%s'"), token_start);
1464 return NULL;
1465 }
1466 l++;
1467 }
1468 if (!is_space_char (*l)
1469 && *l != END_OF_INSN
1470 && *l != PREFIX_SEPARATOR
1471 && *l != ',')
1472 {
1473 as_bad (_("invalid character %s in mnemonic"),
1474 output_invalid (*l));
1475 return NULL;
1476 }
1477 if (token_start == l)
1478 {
1479 if (*l == PREFIX_SEPARATOR)
1480 as_bad (_("expecting prefix; got nothing"));
1481 else
1482 as_bad (_("expecting mnemonic; got nothing"));
1483 return NULL;
1484 }
45288df1 1485
29b0f896
AM		 1486 /* Look up instruction (or prefix) via hash table. */
1487 current_templates = hash_find (op_hash, mnemonic);
47926f60 1488
29b0f896
AM		 1489 if (*l != END_OF_INSN
1490 && (!is_space_char (*l) || l[1] != END_OF_INSN)
1491 && current_templates
1492 && (current_templates->start->opcode_modifier & IsPrefix))
1493 {
1494 /* If we are in 16-bit mode, do not allow addr16 or data16.
1495 Similarly, in 32-bit mode, do not allow addr32 or data32. */
1496 if ((current_templates->start->opcode_modifier & (Size16 | Size32))
1497 && flag_code != CODE_64BIT
1498 && (((current_templates->start->opcode_modifier & Size32) != 0)
1499 ^ (flag_code == CODE_16BIT)))
1500 {
1501 as_bad (_("redundant %s prefix"),
1502 current_templates->start->name);
1503 return NULL;
45288df1 1504 }
29b0f896
AM		 1505 /* Add prefix, checking for repeated prefixes. */
1506 switch (add_prefix (current_templates->start->base_opcode))
1507 {
1508 case 0:
1509 return NULL;
1510 case 2:
1511 expecting_string_instruction = current_templates->start->name;
1512 break;
1513 }
1514 /* Skip past PREFIX_SEPARATOR and reset token_start. */
1515 token_start = ++l;
1516 }
1517 else
1518 break;
1519 }
45288df1 1520
29b0f896
AM		 1521 if (!current_templates)
1522 {
1523 /* See if we can get a match by trimming off a suffix. */
1524 switch (mnem_p[-1])
1525 {
1526 case WORD_MNEM_SUFFIX:
1527 case BYTE_MNEM_SUFFIX:
1528 case QWORD_MNEM_SUFFIX:
1529 i.suffix = mnem_p[-1];
1530 mnem_p[-1] = '\0';
1531 current_templates = hash_find (op_hash, mnemonic);
1532 break;
1533 case SHORT_MNEM_SUFFIX:
1534 case LONG_MNEM_SUFFIX:
1535 if (!intel_syntax)
1536 {
1537 i.suffix = mnem_p[-1];
1538 mnem_p[-1] = '\0';
1539 current_templates = hash_find (op_hash, mnemonic);
1540 }
1541 break;
252b5132 1542
29b0f896
AM		 1543 /* Intel Syntax. */
1544 case 'd':
1545 if (intel_syntax)
1546 {
1547 if (intel_float_operand (mnemonic))
1548 i.suffix = SHORT_MNEM_SUFFIX;
1549 else
1550 i.suffix = LONG_MNEM_SUFFIX;
1551 mnem_p[-1] = '\0';
1552 current_templates = hash_find (op_hash, mnemonic);
1553 }
1554 break;
1555 }
1556 if (!current_templates)
1557 {
1558 as_bad (_("no such instruction: `%s'"), token_start);
1559 return NULL;
1560 }
1561 }
252b5132 1562
29b0f896
AM		 1563 if (current_templates->start->opcode_modifier & (Jump | JumpByte))
1564 {
1565 /* Check for a branch hint. We allow ",pt" and ",pn" for
1566 predict taken and predict not taken respectively.
1567 I'm not sure that branch hints actually do anything on loop
1568 and jcxz insns (JumpByte) for current Pentium4 chips. They
1569 may work in the future and it doesn't hurt to accept them
1570 now. */
1571 if (l[0] == ',' && l[1] == 'p')
1572 {
1573 if (l[2] == 't')
1574 {
1575 if (!add_prefix (DS_PREFIX_OPCODE))
1576 return NULL;
1577 l += 3;
1578 }
1579 else if (l[2] == 'n')
1580 {
1581 if (!add_prefix (CS_PREFIX_OPCODE))
1582 return NULL;
1583 l += 3;
1584 }
1585 }
1586 }
1587 /* Any other comma loses. */
1588 if (*l == ',')
1589 {
1590 as_bad (_("invalid character %s in mnemonic"),
1591 output_invalid (*l));
1592 return NULL;
1593 }
252b5132 1594
29b0f896
AM		 1595 /* Check if instruction is supported on specified architecture. */
1596 if ((current_templates->start->cpu_flags & ~(Cpu64 | CpuNo64))
1597 & ~(cpu_arch_flags & ~(Cpu64 | CpuNo64)))
1598 {
1599 as_warn (_("`%s' is not supported on `%s'"),
1600 current_templates->start->name, cpu_arch_name);
1601 }
1602 else if ((Cpu386 & ~cpu_arch_flags) && (flag_code != CODE_16BIT))
1603 {
1604 as_warn (_("use .code16 to ensure correct addressing mode"));
1605 }
252b5132 1606
29b0f896
AM		 1607 /* Check for rep/repne without a string instruction. */
1608 if (expecting_string_instruction
1609 && !(current_templates->start->opcode_modifier & IsString))
1610 {
1611 as_bad (_("expecting string instruction after `%s'"),
1612 expecting_string_instruction);
1613 return NULL;
1614 }
252b5132 1615
29b0f896
AM		 1616 return l;
1617}
252b5132 1618
29b0f896
AM		 1619static char *
1620parse_operands (l, mnemonic)
1621 char *l;
1622 const char *mnemonic;
1623{
1624 char *token_start;
3138f287 1625
29b0f896
AM		 1626 /* 1 if operand is pending after ','. */
1627 unsigned int expecting_operand = 0;
252b5132 1628
29b0f896
AM		 1629 /* Non-zero if operand parens not balanced. */
1630 unsigned int paren_not_balanced;
1631
1632 while (*l != END_OF_INSN)
1633 {
1634 /* Skip optional white space before operand. */
1635 if (is_space_char (*l))
1636 ++l;
1637 if (!is_operand_char (*l) && *l != END_OF_INSN)
1638 {
1639 as_bad (_("invalid character %s before operand %d"),
1640 output_invalid (*l),
1641 i.operands + 1);
1642 return NULL;
1643 }
1644 token_start = l; /* after white space */
1645 paren_not_balanced = 0;
1646 while (paren_not_balanced || *l != ',')
1647 {
1648 if (*l == END_OF_INSN)
1649 {
1650 if (paren_not_balanced)
1651 {
1652 if (!intel_syntax)
1653 as_bad (_("unbalanced parenthesis in operand %d."),
1654 i.operands + 1);
1655 else
1656 as_bad (_("unbalanced brackets in operand %d."),
1657 i.operands + 1);
1658 return NULL;
1659 }
1660 else
1661 break; /* we are done */
1662 }
1663 else if (!is_operand_char (*l) && !is_space_char (*l))
1664 {
1665 as_bad (_("invalid character %s in operand %d"),
1666 output_invalid (*l),
1667 i.operands + 1);
1668 return NULL;
1669 }
1670 if (!intel_syntax)
1671 {
1672 if (*l == '(')
1673 ++paren_not_balanced;
1674 if (*l == ')')
1675 --paren_not_balanced;
1676 }
1677 else
1678 {
1679 if (*l == '[')
1680 ++paren_not_balanced;
1681 if (*l == ']')
1682 --paren_not_balanced;
1683 }
1684 l++;
1685 }
1686 if (l != token_start)
1687 { /* Yes, we've read in another operand. */
1688 unsigned int operand_ok;
1689 this_operand = i.operands++;
1690 if (i.operands > MAX_OPERANDS)
1691 {
1692 as_bad (_("spurious operands; (%d operands/instruction max)"),
1693 MAX_OPERANDS);
1694 return NULL;
1695 }
1696 /* Now parse operand adding info to 'i' as we go along. */
1697 END_STRING_AND_SAVE (l);
1698
1699 if (intel_syntax)
1700 operand_ok =
1701 i386_intel_operand (token_start,
1702 intel_float_operand (mnemonic));
1703 else
1704 operand_ok = i386_operand (token_start);
1705
1706 RESTORE_END_STRING (l);
1707 if (!operand_ok)
1708 return NULL;
1709 }
1710 else
1711 {
1712 if (expecting_operand)
1713 {
1714 expecting_operand_after_comma:
1715 as_bad (_("expecting operand after ','; got nothing"));
1716 return NULL;
1717 }
1718 if (*l == ',')
1719 {
1720 as_bad (_("expecting operand before ','; got nothing"));
1721 return NULL;
1722 }
1723 }
7f3f1ea2 1724
29b0f896
AM		 1725 /* Now *l must be either ',' or END_OF_INSN. */
1726 if (*l == ',')
1727 {
1728 if (*++l == END_OF_INSN)
1729 {
1730 /* Just skip it, if it's \n complain. */
1731 goto expecting_operand_after_comma;
1732 }
1733 expecting_operand = 1;
1734 }
1735 }
1736 return l;
1737}
7f3f1ea2 1738
29b0f896
AM		 1739static void
1740swap_operands ()
1741{
1742 union i386_op temp_op;
1743 unsigned int temp_type;
1744 RELOC_ENUM temp_reloc;
1745 int xchg1 = 0;
1746 int xchg2 = 0;
252b5132 1747
29b0f896
AM		 1748 if (i.operands == 2)
1749 {
1750 xchg1 = 0;
1751 xchg2 = 1;
1752 }
1753 else if (i.operands == 3)
1754 {
1755 xchg1 = 0;
1756 xchg2 = 2;
1757 }
1758 temp_type = i.types[xchg2];
1759 i.types[xchg2] = i.types[xchg1];
1760 i.types[xchg1] = temp_type;
1761 temp_op = i.op[xchg2];
1762 i.op[xchg2] = i.op[xchg1];
1763 i.op[xchg1] = temp_op;
1764 temp_reloc = i.reloc[xchg2];
1765 i.reloc[xchg2] = i.reloc[xchg1];
1766 i.reloc[xchg1] = temp_reloc;
1767
1768 if (i.mem_operands == 2)
1769 {
1770 const seg_entry *temp_seg;
1771 temp_seg = i.seg[0];
1772 i.seg[0] = i.seg[1];
1773 i.seg[1] = temp_seg;
1774 }
1775}
252b5132 1776
29b0f896
AM		 1777/* Try to ensure constant immediates are represented in the smallest
1778 opcode possible. */
1779static void
1780optimize_imm ()
1781{
1782 char guess_suffix = 0;
1783 int op;
252b5132 1784
29b0f896
AM		 1785 if (i.suffix)
1786 guess_suffix = i.suffix;
1787 else if (i.reg_operands)
1788 {
1789 /* Figure out a suffix from the last register operand specified.
1790 We can't do this properly yet, ie. excluding InOutPortReg,
1791 but the following works for instructions with immediates.
1792 In any case, we can't set i.suffix yet. */
1793 for (op = i.operands; --op >= 0;)
1794 if (i.types[op] & Reg)
252b5132 1795 {
29b0f896
AM		 1796 if (i.types[op] & Reg8)
1797 guess_suffix = BYTE_MNEM_SUFFIX;
1798 else if (i.types[op] & Reg16)
1799 guess_suffix = WORD_MNEM_SUFFIX;
1800 else if (i.types[op] & Reg32)
1801 guess_suffix = LONG_MNEM_SUFFIX;
1802 else if (i.types[op] & Reg64)
1803 guess_suffix = QWORD_MNEM_SUFFIX;
1804 break;
252b5132 1805 }
29b0f896
AM		 1806 }
1807 else if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
1808 guess_suffix = WORD_MNEM_SUFFIX;
1809
1810 for (op = i.operands; --op >= 0;)
1811 if (i.types[op] & Imm)
1812 {
1813 switch (i.op[op].imms->X_op)
252b5132 1814 {
29b0f896
AM		 1815 case O_constant:
1816 /* If a suffix is given, this operand may be shortened. */
1817 switch (guess_suffix)
252b5132 1818 {
29b0f896
AM		 1819 case LONG_MNEM_SUFFIX:
1820 i.types[op] |= Imm32 | Imm64;
1821 break;
1822 case WORD_MNEM_SUFFIX:
1823 i.types[op] |= Imm16 | Imm32S | Imm32 | Imm64;
1824 break;
1825 case BYTE_MNEM_SUFFIX:
1826 i.types[op] |= Imm16 | Imm8 | Imm8S | Imm32S | Imm32 | Imm64;
1827 break;
252b5132 1828 }
252b5132 1829
29b0f896
AM		 1830 /* If this operand is at most 16 bits, convert it
1831 to a signed 16 bit number before trying to see
1832 whether it will fit in an even smaller size.
1833 This allows a 16-bit operand such as $0xffe0 to
1834 be recognised as within Imm8S range. */
1835 if ((i.types[op] & Imm16)
1836 && (i.op[op].imms->X_add_number & ~(offsetT) 0xffff) == 0)
252b5132 1837 {
29b0f896
AM		 1838 i.op[op].imms->X_add_number =
1839 (((i.op[op].imms->X_add_number & 0xffff) ^ 0x8000) - 0x8000);
1840 }
1841 if ((i.types[op] & Imm32)
1842 && ((i.op[op].imms->X_add_number & ~(((offsetT) 2 << 31) - 1))
1843 == 0))
1844 {
1845 i.op[op].imms->X_add_number = ((i.op[op].imms->X_add_number
1846 ^ ((offsetT) 1 << 31))
1847 - ((offsetT) 1 << 31));
1848 }
1849 i.types[op] |= smallest_imm_type (i.op[op].imms->X_add_number);
252b5132 1850
29b0f896
AM		 1851 /* We must avoid matching of Imm32 templates when 64bit
1852 only immediate is available. */
1853 if (guess_suffix == QWORD_MNEM_SUFFIX)
1854 i.types[op] &= ~Imm32;
1855 break;
252b5132 1856
29b0f896
AM		 1857 case O_absent:
1858 case O_register:
1859 abort ();
1860
1861 /* Symbols and expressions. */
1862 default:
1863 /* Convert symbolic operand to proper sizes for matching. */
1864 switch (guess_suffix)
1865 {
1866 case QWORD_MNEM_SUFFIX:
1867 i.types[op] = Imm64 | Imm32S;
1868 break;
1869 case LONG_MNEM_SUFFIX:
1870 i.types[op] = Imm32 | Imm64;
1871 break;
1872 case WORD_MNEM_SUFFIX:
1873 i.types[op] = Imm16 | Imm32 | Imm64;
1874 break;
1875 break;
1876 case BYTE_MNEM_SUFFIX:
1877 i.types[op] = Imm8 | Imm8S | Imm16 | Imm32S | Imm32;
1878 break;
1879 break;
252b5132 1880 }
29b0f896 1881 break;
252b5132 1882 }
29b0f896
AM		 1883 }
1884}
47926f60 1885
29b0f896
AM		 1886/* Try to use the smallest displacement type too. */
1887static void
1888optimize_disp ()
1889{
1890 int op;
3e73aa7c 1891
29b0f896
AM		 1892 for (op = i.operands; --op >= 0;)
1893 if ((i.types[op] & Disp) && i.op[op].disps->X_op == O_constant)
252b5132 1894 {
29b0f896
AM		 1895 offsetT disp = i.op[op].disps->X_add_number;
1896
1897 if (i.types[op] & Disp16)
252b5132 1898 {
29b0f896
AM		 1899 /* We know this operand is at most 16 bits, so
1900 convert to a signed 16 bit number before trying
1901 to see whether it will fit in an even smaller
1902 size. */
1903
1904 disp = (((disp & 0xffff) ^ 0x8000) - 0x8000);
252b5132 1905 }
29b0f896 1906 else if (i.types[op] & Disp32)
252b5132 1907 {
29b0f896
AM		 1908 /* We know this operand is at most 32 bits, so convert to a
1909 signed 32 bit number before trying to see whether it will
1910 fit in an even smaller size. */
1911 disp &= (((offsetT) 2 << 31) - 1);
1912 disp = (disp ^ ((offsetT) 1 << 31)) - ((addressT) 1 << 31);
252b5132 1913 }
29b0f896 1914 if (flag_code == CODE_64BIT)
252b5132 1915 {
29b0f896
AM		 1916 if (fits_in_signed_long (disp))
1917 i.types[op] |= Disp32S;
1918 if (fits_in_unsigned_long (disp))
1919 i.types[op] |= Disp32;
252b5132 1920 }
29b0f896
AM		 1921 if ((i.types[op] & (Disp32 | Disp32S | Disp16))
1922 && fits_in_signed_byte (disp))
1923 i.types[op] |= Disp8;
252b5132 1924 }
29b0f896
AM		 1925}
1926
1927static int
1928match_template ()
1929{
1930 /* Points to template once we've found it. */
1931 const template *t;
1932 unsigned int overlap0, overlap1, overlap2;
1933 unsigned int found_reverse_match;
1934 int suffix_check;
1935
1936#define MATCH(overlap, given, template) \
1937 ((overlap & ~JumpAbsolute) \
1938 && (((given) & (BaseIndex | JumpAbsolute)) \
1939 == ((overlap) & (BaseIndex | JumpAbsolute))))
1940
1941 /* If given types r0 and r1 are registers they must be of the same type
1942 unless the expected operand type register overlap is null.
1943 Note that Acc in a template matches every size of reg. */
1944#define CONSISTENT_REGISTER_MATCH(m0, g0, t0, m1, g1, t1) \
1945 (((g0) & Reg) == 0 || ((g1) & Reg) == 0 \
1946 || ((g0) & Reg) == ((g1) & Reg) \
1947 || ((((m0) & Acc) ? Reg : (t0)) & (((m1) & Acc) ? Reg : (t1)) & Reg) == 0 )
1948
1949 overlap0 = 0;
1950 overlap1 = 0;
1951 overlap2 = 0;
1952 found_reverse_match = 0;
1953 suffix_check = (i.suffix == BYTE_MNEM_SUFFIX
1954 ? No_bSuf
1955 : (i.suffix == WORD_MNEM_SUFFIX
1956 ? No_wSuf
1957 : (i.suffix == SHORT_MNEM_SUFFIX
1958 ? No_sSuf
1959 : (i.suffix == LONG_MNEM_SUFFIX
1960 ? No_lSuf
1961 : (i.suffix == QWORD_MNEM_SUFFIX
1962 ? No_qSuf
1963 : (i.suffix == LONG_DOUBLE_MNEM_SUFFIX
1964 ? No_xSuf : 0))))));
1965
1966 for (t = current_templates->start;
1967 t < current_templates->end;
1968 t++)
1969 {
1970 /* Must have right number of operands. */
1971 if (i.operands != t->operands)
1972 continue;
1973
1974 /* Check the suffix, except for some instructions in intel mode. */
1975 if ((t->opcode_modifier & suffix_check)
1976 && !(intel_syntax
1977 && (t->opcode_modifier & IgnoreSize))
1978 && !(intel_syntax
1979 && t->base_opcode == 0xd9
1980 && (t->extension_opcode == 5 /* 0xd9,5 "fldcw" */
1981 || t->extension_opcode == 7))) /* 0xd9,7 "f{n}stcw" */
1982 continue;
1983
1984 /* Do not verify operands when there are none. */
1985 else if (!t->operands)
1986 {
1987 if (t->cpu_flags & ~cpu_arch_flags)
1988 continue;
1989 /* We've found a match; break out of loop. */
1990 break;
1991 }
252b5132 1992
29b0f896
AM		 1993 overlap0 = i.types[0] & t->operand_types[0];
1994 switch (t->operands)
1995 {
1996 case 1:
1997 if (!MATCH (overlap0, i.types[0], t->operand_types[0]))
1998 continue;
1999 break;
2000 case 2:
2001 case 3:
2002 overlap1 = i.types[1] & t->operand_types[1];
2003 if (!MATCH (overlap0, i.types[0], t->operand_types[0])
2004 || !MATCH (overlap1, i.types[1], t->operand_types[1])
2005 || !CONSISTENT_REGISTER_MATCH (overlap0, i.types[0],
2006 t->operand_types[0],
2007 overlap1, i.types[1],
2008 t->operand_types[1]))
2009 {
2010 /* Check if other direction is valid ... */
2011 if ((t->opcode_modifier & (D | FloatD)) == 0)
2012 continue;
2013
2014 /* Try reversing direction of operands. */
2015 overlap0 = i.types[0] & t->operand_types[1];
2016 overlap1 = i.types[1] & t->operand_types[0];
2017 if (!MATCH (overlap0, i.types[0], t->operand_types[1])
2018 || !MATCH (overlap1, i.types[1], t->operand_types[0])
2019 || !CONSISTENT_REGISTER_MATCH (overlap0, i.types[0],
2020 t->operand_types[1],
2021 overlap1, i.types[1],
2022 t->operand_types[0]))
2023 {
2024 /* Does not match either direction. */
2025 continue;
2026 }
2027 /* found_reverse_match holds which of D or FloatDR
2028 we've found. */
2029 found_reverse_match = t->opcode_modifier & (D | FloatDR);
2030 }
2031 /* Found a forward 2 operand match here. */
2032 else if (t->operands == 3)
2033 {
2034 /* Here we make use of the fact that there are no
2035 reverse match 3 operand instructions, and all 3
2036 operand instructions only need to be checked for
2037 register consistency between operands 2 and 3. */
2038 overlap2 = i.types[2] & t->operand_types[2];
2039 if (!MATCH (overlap2, i.types[2], t->operand_types[2])
2040 || !CONSISTENT_REGISTER_MATCH (overlap1, i.types[1],
2041 t->operand_types[1],
2042 overlap2, i.types[2],
2043 t->operand_types[2]))
2044
2045 continue;
2046 }
2047 /* Found either forward/reverse 2 or 3 operand match here:
2048 slip through to break. */
2049 }
2050 if (t->cpu_flags & ~cpu_arch_flags)
2051 {
2052 found_reverse_match = 0;
2053 continue;
2054 }
2055 /* We've found a match; break out of loop. */
2056 break;
2057 }
2058
2059 if (t == current_templates->end)
2060 {
2061 /* We found no match. */
2062 as_bad (_("suffix or operands invalid for `%s'"),
2063 current_templates->start->name);
2064 return 0;
2065 }
252b5132 2066
29b0f896
AM		 2067 if (!quiet_warnings)
2068 {
2069 if (!intel_syntax
2070 && ((i.types[0] & JumpAbsolute)
2071 != (t->operand_types[0] & JumpAbsolute)))
2072 {
2073 as_warn (_("indirect %s without `*'"), t->name);
2074 }
2075
2076 if ((t->opcode_modifier & (IsPrefix | IgnoreSize))
2077 == (IsPrefix | IgnoreSize))
2078 {
2079 /* Warn them that a data or address size prefix doesn't
2080 affect assembly of the next line of code. */
2081 as_warn (_("stand-alone `%s' prefix"), t->name);
2082 }
2083 }
2084
2085 /* Copy the template we found. */
2086 i.tm = *t;
2087 if (found_reverse_match)
2088 {
2089 /* If we found a reverse match we must alter the opcode
2090 direction bit. found_reverse_match holds bits to change
2091 (different for int & float insns). */
2092
2093 i.tm.base_opcode ^= found_reverse_match;
2094
2095 i.tm.operand_types[0] = t->operand_types[1];
2096 i.tm.operand_types[1] = t->operand_types[0];
2097 }
2098
2099 return 1;
2100}
2101
2102static int
2103check_string ()
2104{
2105 int mem_op = (i.types[0] & AnyMem) ? 0 : 1;
2106 if ((i.tm.operand_types[mem_op] & EsSeg) != 0)
2107 {
2108 if (i.seg[0] != NULL && i.seg[0] != &es)
2109 {
2110 as_bad (_("`%s' operand %d must use `%%es' segment"),
2111 i.tm.name,
2112 mem_op + 1);
2113 return 0;
2114 }
2115 /* There's only ever one segment override allowed per instruction.
2116 This instruction possibly has a legal segment override on the
2117 second operand, so copy the segment to where non-string
2118 instructions store it, allowing common code. */
2119 i.seg[0] = i.seg[1];
2120 }
2121 else if ((i.tm.operand_types[mem_op + 1] & EsSeg) != 0)
2122 {
2123 if (i.seg[1] != NULL && i.seg[1] != &es)
2124 {
2125 as_bad (_("`%s' operand %d must use `%%es' segment"),
2126 i.tm.name,
2127 mem_op + 2);
2128 return 0;
2129 }
2130 }
2131 return 1;
2132}
2133
2134static int
2135process_suffix ()
2136{
2137 /* If matched instruction specifies an explicit instruction mnemonic
2138 suffix, use it. */
2139 if (i.tm.opcode_modifier & (Size16 | Size32 | Size64))
2140 {
2141 if (i.tm.opcode_modifier & Size16)
2142 i.suffix = WORD_MNEM_SUFFIX;
2143 else if (i.tm.opcode_modifier & Size64)
2144 i.suffix = QWORD_MNEM_SUFFIX;
2145 else
2146 i.suffix = LONG_MNEM_SUFFIX;
2147 }
2148 else if (i.reg_operands)
2149 {
2150 /* If there's no instruction mnemonic suffix we try to invent one
2151 based on register operands. */
2152 if (!i.suffix)
2153 {
2154 /* We take i.suffix from the last register operand specified,
2155 Destination register type is more significant than source
2156 register type. */
2157 int op;
2158 for (op = i.operands; --op >= 0;)
2159 if ((i.types[op] & Reg)
2160 && !(i.tm.operand_types[op] & InOutPortReg))
2161 {
2162 i.suffix = ((i.types[op] & Reg8) ? BYTE_MNEM_SUFFIX :
2163 (i.types[op] & Reg16) ? WORD_MNEM_SUFFIX :
2164 (i.types[op] & Reg64) ? QWORD_MNEM_SUFFIX :
2165 LONG_MNEM_SUFFIX);
2166 break;
2167 }
2168 }
2169 else if (i.suffix == BYTE_MNEM_SUFFIX)
2170 {
2171 if (!check_byte_reg ())
2172 return 0;
2173 }
2174 else if (i.suffix == LONG_MNEM_SUFFIX)
2175 {
2176 if (!check_long_reg ())
2177 return 0;
2178 }
2179 else if (i.suffix == QWORD_MNEM_SUFFIX)
2180 {
2181 if (!check_qword_reg ())
2182 return 0;
2183 }
2184 else if (i.suffix == WORD_MNEM_SUFFIX)
2185 {
2186 if (!check_word_reg ())
2187 return 0;
2188 }
2189 else if (intel_syntax && (i.tm.opcode_modifier & IgnoreSize))
2190 /* Do nothing if the instruction is going to ignore the prefix. */
2191 ;
2192 else
2193 abort ();
2194 }
2195 else if ((i.tm.opcode_modifier & DefaultSize) && !i.suffix)
2196 {
2197 i.suffix = stackop_size;
2198 }
252b5132 2199
29b0f896
AM		 2200 /* Change the opcode based on the operand size given by i.suffix;
2201 We need not change things for byte insns. */
252b5132 2202
29b0f896
AM		 2203 if (!i.suffix && (i.tm.opcode_modifier & W))
2204 {
2205 as_bad (_("no instruction mnemonic suffix given and no register operands; can't size instruction"));
2206 return 0;
2207 }
252b5132 2208
29b0f896
AM		 2209 /* For movzx and movsx, need to check the register type. */
2210 if (intel_syntax
0f3f3d8b
AM		 2211 && (i.tm.base_opcode == 0xfb6 || i.tm.base_opcode == 0xfbe)
2212 && i.suffix == BYTE_MNEM_SUFFIX)
2213 {
2214 unsigned int prefix = DATA_PREFIX_OPCODE;
29b0f896 2215
0f3f3d8b
AM		 2216 if ((i.op[1].regs->reg_type & Reg16) != 0)
2217 if (!add_prefix (prefix))
2218 return 0;
2219 }
252b5132 2220
29b0f896
AM		 2221 if (i.suffix && i.suffix != BYTE_MNEM_SUFFIX)
2222 {
2223 /* It's not a byte, select word/dword operation. */
2224 if (i.tm.opcode_modifier & W)
2225 {
2226 if (i.tm.opcode_modifier & ShortForm)
2227 i.tm.base_opcode |= 8;
2228 else
2229 i.tm.base_opcode |= 1;
2230 }
0f3f3d8b 2231
29b0f896
AM		 2232 /* Now select between word & dword operations via the operand
2233 size prefix, except for instructions that will ignore this
2234 prefix anyway. */
2235 if (i.suffix != QWORD_MNEM_SUFFIX
2236 && (i.suffix == LONG_MNEM_SUFFIX) == (flag_code == CODE_16BIT)
2237 && !(i.tm.opcode_modifier & IgnoreSize))
24eab124
AM		 2238 {
2239 unsigned int prefix = DATA_PREFIX_OPCODE;
29b0f896
AM		 2240 if (i.tm.opcode_modifier & JumpByte) /* jcxz, loop */
2241 prefix = ADDR_PREFIX_OPCODE;
252b5132 2242
29b0f896
AM		 2243 if (!add_prefix (prefix))
2244 return 0;
24eab124 2245 }
252b5132 2246
29b0f896
AM		 2247 if (i.suffix != QWORD_MNEM_SUFFIX && (flag_code == CODE_64BIT)
2248 && !(i.tm.opcode_modifier & IgnoreSize)
2249 && (i.tm.opcode_modifier & JumpByte))
2250 {
2251 if (!add_prefix (ADDR_PREFIX_OPCODE))
2252 return 0;
2253 }
252b5132 2254
29b0f896
AM		 2255 /* Set mode64 for an operand. */
2256 if (i.suffix == QWORD_MNEM_SUFFIX
2257 && (i.tm.opcode_modifier & NoRex64) == 0)
2258 {
2259 i.rex |= REX_MODE64;
2260 if (flag_code < CODE_64BIT)
2261 {
2262 as_bad (_("64bit operations available only in 64bit modes."));
2263 return 0;
2264 }
2265 }
3e73aa7c 2266
29b0f896
AM		 2267 /* Size floating point instruction. */
2268 if (i.suffix == LONG_MNEM_SUFFIX)
2269 {
2270 if (i.tm.opcode_modifier & FloatMF)
2271 i.tm.base_opcode ^= 4;
2272 }
2273 }
7ecd2f8b 2274
29b0f896
AM		 2275 return 1;
2276}
3e73aa7c 2277
29b0f896
AM		 2278static int
2279check_byte_reg ()
2280{
2281 int op;
2282 for (op = i.operands; --op >= 0;)
2283 {
2284 /* If this is an eight bit register, it's OK. If it's the 16 or
2285 32 bit version of an eight bit register, we will just use the
2286 low portion, and that's OK too. */
2287 if (i.types[op] & Reg8)
2288 continue;
2289
2290 /* movzx and movsx should not generate this warning. */
2291 if (intel_syntax
2292 && (i.tm.base_opcode == 0xfb7
2293 || i.tm.base_opcode == 0xfb6
2294 || i.tm.base_opcode == 0x63
2295 || i.tm.base_opcode == 0xfbe
2296 || i.tm.base_opcode == 0xfbf))
2297 continue;
2298
2299 if ((i.types[op] & WordReg) && i.op[op].regs->reg_num < 4
2300#if 0
2301 /* Check that the template allows eight bit regs. This
2302 kills insns such as `orb $1,%edx', which maybe should be
2303 allowed. */
2304 && (i.tm.operand_types[op] & (Reg8 | InOutPortReg))
2305#endif
2306 )
2307 {
2308 /* Prohibit these changes in the 64bit mode, since the
2309 lowering is more complicated. */
2310 if (flag_code == CODE_64BIT
2311 && (i.tm.operand_types[op] & InOutPortReg) == 0)
2312 {
0f3f3d8b 2313 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
29b0f896
AM		 2314 i.op[op].regs->reg_name,
2315 i.suffix);
2316 return 0;
2317 }
2318#if REGISTER_WARNINGS
2319 if (!quiet_warnings
2320 && (i.tm.operand_types[op] & InOutPortReg) == 0)
2321 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
2322 (i.op[op].regs + (i.types[op] & Reg16
2323 ? REGNAM_AL - REGNAM_AX
2324 : REGNAM_AL - REGNAM_EAX))->reg_name,
2325 i.op[op].regs->reg_name,
2326 i.suffix);
2327#endif
2328 continue;
2329 }
2330 /* Any other register is bad. */
2331 if (i.types[op] & (Reg | RegMMX | RegXMM
2332 | SReg2 | SReg3
2333 | Control | Debug | Test
2334 | FloatReg | FloatAcc))
2335 {
2336 as_bad (_("`%%%s' not allowed with `%s%c'"),
2337 i.op[op].regs->reg_name,
2338 i.tm.name,
2339 i.suffix);
2340 return 0;
2341 }
2342 }
2343 return 1;
2344}
2345
2346static int
2347check_long_reg ()
2348{
2349 int op;
2350
2351 for (op = i.operands; --op >= 0;)
2352 /* Reject eight bit registers, except where the template requires
2353 them. (eg. movzb) */
2354 if ((i.types[op] & Reg8) != 0
2355 && (i.tm.operand_types[op] & (Reg16 | Reg32 | Acc)) != 0)
2356 {
2357 as_bad (_("`%%%s' not allowed with `%s%c'"),
2358 i.op[op].regs->reg_name,
2359 i.tm.name,
2360 i.suffix);
2361 return 0;
2362 }
2363 /* Warn if the e prefix on a general reg is missing. */
2364 else if ((!quiet_warnings || flag_code == CODE_64BIT)
2365 && (i.types[op] & Reg16) != 0
2366 && (i.tm.operand_types[op] & (Reg32 | Acc)) != 0)
2367 {
2368 /* Prohibit these changes in the 64bit mode, since the
2369 lowering is more complicated. */
2370 if (flag_code == CODE_64BIT)
252b5132 2371 {
0f3f3d8b 2372 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
29b0f896
AM		 2373 i.op[op].regs->reg_name,
2374 i.suffix);
2375 return 0;
252b5132 2376 }
29b0f896
AM		 2377#if REGISTER_WARNINGS
2378 else
2379 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
2380 (i.op[op].regs + REGNAM_EAX - REGNAM_AX)->reg_name,
2381 i.op[op].regs->reg_name,
2382 i.suffix);
2383#endif
252b5132 2384 }
29b0f896
AM		 2385 /* Warn if the r prefix on a general reg is missing. */
2386 else if ((i.types[op] & Reg64) != 0
2387 && (i.tm.operand_types[op] & (Reg32 | Acc)) != 0)
252b5132 2388 {
0f3f3d8b 2389 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
29b0f896
AM		 2390 i.op[op].regs->reg_name,
2391 i.suffix);
2392 return 0;
2393 }
2394 return 1;
2395}
252b5132 2396
29b0f896
AM		 2397static int
2398check_qword_reg ()
2399{
2400 int op;
252b5132 2401
29b0f896
AM		 2402 for (op = i.operands; --op >= 0; )
2403 /* Reject eight bit registers, except where the template requires
2404 them. (eg. movzb) */
2405 if ((i.types[op] & Reg8) != 0
2406 && (i.tm.operand_types[op] & (Reg16 | Reg32 | Acc)) != 0)
2407 {
2408 as_bad (_("`%%%s' not allowed with `%s%c'"),
2409 i.op[op].regs->reg_name,
2410 i.tm.name,
2411 i.suffix);
2412 return 0;
2413 }
2414 /* Warn if the e prefix on a general reg is missing. */
2415 else if (((i.types[op] & Reg16) != 0
2416 || (i.types[op] & Reg32) != 0)
2417 && (i.tm.operand_types[op] & (Reg32 | Acc)) != 0)
2418 {
2419 /* Prohibit these changes in the 64bit mode, since the
2420 lowering is more complicated. */
0f3f3d8b 2421 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
29b0f896
AM		 2422 i.op[op].regs->reg_name,
2423 i.suffix);
2424 return 0;
252b5132 2425 }
29b0f896
AM		 2426 return 1;
2427}
252b5132 2428
29b0f896
AM		 2429static int
2430check_word_reg ()
2431{
2432 int op;
2433 for (op = i.operands; --op >= 0;)
2434 /* Reject eight bit registers, except where the template requires
2435 them. (eg. movzb) */
2436 if ((i.types[op] & Reg8) != 0
2437 && (i.tm.operand_types[op] & (Reg16 | Reg32 | Acc)) != 0)
2438 {
2439 as_bad (_("`%%%s' not allowed with `%s%c'"),
2440 i.op[op].regs->reg_name,
2441 i.tm.name,
2442 i.suffix);
2443 return 0;
2444 }
2445 /* Warn if the e prefix on a general reg is present. */
2446 else if ((!quiet_warnings || flag_code == CODE_64BIT)
2447 && (i.types[op] & Reg32) != 0
2448 && (i.tm.operand_types[op] & (Reg16 | Acc)) != 0)
252b5132 2449 {
29b0f896
AM		 2450 /* Prohibit these changes in the 64bit mode, since the
2451 lowering is more complicated. */
2452 if (flag_code == CODE_64BIT)
252b5132 2453 {
0f3f3d8b 2454 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
29b0f896
AM		 2455 i.op[op].regs->reg_name,
2456 i.suffix);
2457 return 0;
252b5132 2458 }
29b0f896
AM		 2459 else
2460#if REGISTER_WARNINGS
2461 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
2462 (i.op[op].regs + REGNAM_AX - REGNAM_EAX)->reg_name,
2463 i.op[op].regs->reg_name,
2464 i.suffix);
2465#endif
2466 }
2467 return 1;
2468}
252b5132 2469
29b0f896
AM		 2470static int
2471finalize_imm ()
2472{
2473 unsigned int overlap0, overlap1, overlap2;
2474
2475 overlap0 = i.types[0] & i.tm.operand_types[0];
2476 if ((overlap0 & (Imm8 | Imm8S | Imm16 | Imm32 | Imm32S))
2477 && overlap0 != Imm8 && overlap0 != Imm8S
2478 && overlap0 != Imm16 && overlap0 != Imm32S
2479 && overlap0 != Imm32 && overlap0 != Imm64)
2480 {
2481 if (i.suffix)
2482 {
2483 overlap0 &= (i.suffix == BYTE_MNEM_SUFFIX
2484 ? Imm8 | Imm8S
2485 : (i.suffix == WORD_MNEM_SUFFIX
2486 ? Imm16
2487 : (i.suffix == QWORD_MNEM_SUFFIX
2488 ? Imm64 | Imm32S
2489 : Imm32)));
2490 }
2491 else if (overlap0 == (Imm16 | Imm32S | Imm32)
2492 || overlap0 == (Imm16 | Imm32)
2493 || overlap0 == (Imm16 | Imm32S))
2494 {
2495 overlap0 = ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0)
2496 ? Imm16 : Imm32S);
2497 }
2498 if (overlap0 != Imm8 && overlap0 != Imm8S
2499 && overlap0 != Imm16 && overlap0 != Imm32S
2500 && overlap0 != Imm32 && overlap0 != Imm64)
2501 {
2502 as_bad (_("no instruction mnemonic suffix given; can't determine immediate size"));
2503 return 0;
2504 }
2505 }
2506 i.types[0] = overlap0;
2507
2508 overlap1 = i.types[1] & i.tm.operand_types[1];
2509 if ((overlap1 & (Imm8 | Imm8S | Imm16 | Imm32S | Imm32))
2510 && overlap1 != Imm8 && overlap1 != Imm8S
2511 && overlap1 != Imm16 && overlap1 != Imm32S
2512 && overlap1 != Imm32 && overlap1 != Imm64)
2513 {
2514 if (i.suffix)
2515 {
2516 overlap1 &= (i.suffix == BYTE_MNEM_SUFFIX
2517 ? Imm8 | Imm8S
2518 : (i.suffix == WORD_MNEM_SUFFIX
2519 ? Imm16
2520 : (i.suffix == QWORD_MNEM_SUFFIX
2521 ? Imm64 | Imm32S
2522 : Imm32)));
2523 }
2524 else if (overlap1 == (Imm16 | Imm32 | Imm32S)
2525 || overlap1 == (Imm16 | Imm32)
2526 || overlap1 == (Imm16 | Imm32S))
2527 {
2528 overlap1 = ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0)
2529 ? Imm16 : Imm32S);
2530 }
2531 if (overlap1 != Imm8 && overlap1 != Imm8S
2532 && overlap1 != Imm16 && overlap1 != Imm32S
2533 && overlap1 != Imm32 && overlap1 != Imm64)
2534 {
2535 as_bad (_("no instruction mnemonic suffix given; can't determine immediate size %x %c"),overlap1, i.suffix);
2536 return 0;
2537 }
2538 }
2539 i.types[1] = overlap1;
2540
2541 overlap2 = i.types[2] & i.tm.operand_types[2];
2542 assert ((overlap2 & Imm) == 0);
2543 i.types[2] = overlap2;
2544
2545 return 1;
2546}
2547
2548static int
2549process_operands ()
2550{
2551 /* Default segment register this instruction will use for memory
2552 accesses. 0 means unknown. This is only for optimizing out
2553 unnecessary segment overrides. */
2554 const seg_entry *default_seg = 0;
2555
2556 /* The imul $imm, %reg instruction is converted into
2557 imul $imm, %reg, %reg, and the clr %reg instruction
2558 is converted into xor %reg, %reg. */
2559 if (i.tm.opcode_modifier & regKludge)
2560 {
2561 unsigned int first_reg_op = (i.types[0] & Reg) ? 0 : 1;
2562 /* Pretend we saw the extra register operand. */
2563 assert (i.op[first_reg_op + 1].regs == 0);
2564 i.op[first_reg_op + 1].regs = i.op[first_reg_op].regs;
2565 i.types[first_reg_op + 1] = i.types[first_reg_op];
2566 i.reg_operands = 2;
2567 }
2568
2569 if (i.tm.opcode_modifier & ShortForm)
2570 {
2571 /* The register or float register operand is in operand 0 or 1. */
2572 unsigned int op = (i.types[0] & (Reg | FloatReg)) ? 0 : 1;
2573 /* Register goes in low 3 bits of opcode. */
2574 i.tm.base_opcode |= i.op[op].regs->reg_num;
2575 if ((i.op[op].regs->reg_flags & RegRex) != 0)
2576 i.rex |= REX_EXTZ;
2577 if (!quiet_warnings && (i.tm.opcode_modifier & Ugh) != 0)
2578 {
2579 /* Warn about some common errors, but press on regardless.
2580 The first case can be generated by gcc (<= 2.8.1). */
2581 if (i.operands == 2)
2582 {
2583 /* Reversed arguments on faddp, fsubp, etc. */
2584 as_warn (_("translating to `%s %%%s,%%%s'"), i.tm.name,
2585 i.op[1].regs->reg_name,
2586 i.op[0].regs->reg_name);
2587 }
2588 else
2589 {
2590 /* Extraneous `l' suffix on fp insn. */
2591 as_warn (_("translating to `%s %%%s'"), i.tm.name,
2592 i.op[0].regs->reg_name);
2593 }
2594 }
2595 }
2596 else if (i.tm.opcode_modifier & Modrm)
2597 {
2598 /* The opcode is completed (modulo i.tm.extension_opcode which
2599 must be put into the modrm byte).
2600 Now, we make the modrm & index base bytes based on all the
2601 info we've collected. */
2602
2603 default_seg = build_modrm_byte ();
2604 }
2605 else if (i.tm.opcode_modifier & (Seg2ShortForm | Seg3ShortForm))
2606 {
2607 if (i.tm.base_opcode == POP_SEG_SHORT
2608 && i.op[0].regs->reg_num == 1)
2609 {
2610 as_bad (_("you can't `pop %%cs'"));
2611 return 0;
2612 }
2613 i.tm.base_opcode |= (i.op[0].regs->reg_num << 3);
2614 if ((i.op[0].regs->reg_flags & RegRex) != 0)
2615 i.rex |= REX_EXTZ;
2616 }
2617 else if ((i.tm.base_opcode & ~(D | W)) == MOV_AX_DISP32)
2618 {
2619 default_seg = &ds;
2620 }
2621 else if ((i.tm.opcode_modifier & IsString) != 0)
2622 {
2623 /* For the string instructions that allow a segment override
2624 on one of their operands, the default segment is ds. */
2625 default_seg = &ds;
2626 }
2627
2628 /* If a segment was explicitly specified,
2629 and the specified segment is not the default,
2630 use an opcode prefix to select it.
2631 If we never figured out what the default segment is,
2632 then default_seg will be zero at this point,
2633 and the specified segment prefix will always be used. */
2634 if ((i.seg[0]) && (i.seg[0] != default_seg))
2635 {
2636 if (!add_prefix (i.seg[0]->seg_prefix))
2637 return 0;
2638 }
2639 return 1;
2640}
2641
2642static const seg_entry *
2643build_modrm_byte ()
2644{
2645 const seg_entry *default_seg = 0;
2646
2647 /* i.reg_operands MUST be the number of real register operands;
2648 implicit registers do not count. */
2649 if (i.reg_operands == 2)
2650 {
2651 unsigned int source, dest;
2652 source = ((i.types[0]
2653 & (Reg | RegMMX | RegXMM
2654 | SReg2 | SReg3
2655 | Control | Debug | Test))
2656 ? 0 : 1);
2657 dest = source + 1;
2658
2659 i.rm.mode = 3;
2660 /* One of the register operands will be encoded in the i.tm.reg
2661 field, the other in the combined i.tm.mode and i.tm.regmem
2662 fields. If no form of this instruction supports a memory
2663 destination operand, then we assume the source operand may
2664 sometimes be a memory operand and so we need to store the
2665 destination in the i.rm.reg field. */
2666 if ((i.tm.operand_types[dest] & AnyMem) == 0)
2667 {
2668 i.rm.reg = i.op[dest].regs->reg_num;
2669 i.rm.regmem = i.op[source].regs->reg_num;
2670 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
2671 i.rex |= REX_EXTX;
2672 if ((i.op[source].regs->reg_flags & RegRex) != 0)
2673 i.rex |= REX_EXTZ;
2674 }
2675 else
2676 {
2677 i.rm.reg = i.op[source].regs->reg_num;
2678 i.rm.regmem = i.op[dest].regs->reg_num;
2679 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
2680 i.rex |= REX_EXTZ;
2681 if ((i.op[source].regs->reg_flags & RegRex) != 0)
2682 i.rex |= REX_EXTX;
2683 }
2684 }
2685 else
2686 { /* If it's not 2 reg operands... */
2687 if (i.mem_operands)
2688 {
2689 unsigned int fake_zero_displacement = 0;
2690 unsigned int op = ((i.types[0] & AnyMem)
2691 ? 0
2692 : (i.types[1] & AnyMem) ? 1 : 2);
2693
2694 default_seg = &ds;
2695
2696 if (i.base_reg == 0)
2697 {
2698 i.rm.mode = 0;
2699 if (!i.disp_operands)
2700 fake_zero_displacement = 1;
2701 if (i.index_reg == 0)
2702 {
2703 /* Operand is just <disp> */
2704 if ((flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0)
2705 && (flag_code != CODE_64BIT))
2706 {
2707 i.rm.regmem = NO_BASE_REGISTER_16;
2708 i.types[op] &= ~Disp;
2709 i.types[op] |= Disp16;
2710 }
2711 else if (flag_code != CODE_64BIT
2712 || (i.prefix[ADDR_PREFIX] != 0))
2713 {
2714 i.rm.regmem = NO_BASE_REGISTER;
2715 i.types[op] &= ~Disp;
2716 i.types[op] |= Disp32;
2717 }
2718 else
2719 {
2720 /* 64bit mode overwrites the 32bit absolute
2721 addressing by RIP relative addressing and
2722 absolute addressing is encoded by one of the
2723 redundant SIB forms. */
2724 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
2725 i.sib.base = NO_BASE_REGISTER;
2726 i.sib.index = NO_INDEX_REGISTER;
2727 i.types[op] &= ~Disp;
2728 i.types[op] |= Disp32S;
2729 }
2730 }
2731 else /* !i.base_reg && i.index_reg */
2732 {
2733 i.sib.index = i.index_reg->reg_num;
2734 i.sib.base = NO_BASE_REGISTER;
2735 i.sib.scale = i.log2_scale_factor;
2736 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
2737 i.types[op] &= ~Disp;
2738 if (flag_code != CODE_64BIT)
2739 i.types[op] |= Disp32; /* Must be 32 bit */
2740 else
2741 i.types[op] |= Disp32S;
2742 if ((i.index_reg->reg_flags & RegRex) != 0)
2743 i.rex |= REX_EXTY;
2744 }
2745 }
2746 /* RIP addressing for 64bit mode. */
2747 else if (i.base_reg->reg_type == BaseIndex)
2748 {
2749 i.rm.regmem = NO_BASE_REGISTER;
2750 i.types[op] &= ~Disp;
2751 i.types[op] |= Disp32S;
2752 i.flags[op] = Operand_PCrel;
2753 }
2754 else if (i.base_reg->reg_type & Reg16)
2755 {
2756 switch (i.base_reg->reg_num)
2757 {
2758 case 3: /* (%bx) */
2759 if (i.index_reg == 0)
2760 i.rm.regmem = 7;
2761 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
2762 i.rm.regmem = i.index_reg->reg_num - 6;
2763 break;
2764 case 5: /* (%bp) */
2765 default_seg = &ss;
2766 if (i.index_reg == 0)
2767 {
2768 i.rm.regmem = 6;
2769 if ((i.types[op] & Disp) == 0)
2770 {
2771 /* fake (%bp) into 0(%bp) */
2772 i.types[op] |= Disp8;
252b5132 2773 fake_zero_displacement = 1;
29b0f896
AM		 2774 }
2775 }
2776 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
2777 i.rm.regmem = i.index_reg->reg_num - 6 + 2;
2778 break;
2779 default: /* (%si) -> 4 or (%di) -> 5 */
2780 i.rm.regmem = i.base_reg->reg_num - 6 + 4;
2781 }
2782 i.rm.mode = mode_from_disp_size (i.types[op]);
2783 }
2784 else /* i.base_reg and 32/64 bit mode */
2785 {
2786 if (flag_code == CODE_64BIT
2787 && (i.types[op] & Disp))
2788 {
2789 if (i.types[op] & Disp8)
2790 i.types[op] = Disp8 | Disp32S;
2791 else
2792 i.types[op] = Disp32S;
2793 }
2794 i.rm.regmem = i.base_reg->reg_num;
2795 if ((i.base_reg->reg_flags & RegRex) != 0)
2796 i.rex |= REX_EXTZ;
2797 i.sib.base = i.base_reg->reg_num;
2798 /* x86-64 ignores REX prefix bit here to avoid decoder
2799 complications. */
2800 if ((i.base_reg->reg_num & 7) == EBP_REG_NUM)
2801 {
2802 default_seg = &ss;
2803 if (i.disp_operands == 0)
2804 {
2805 fake_zero_displacement = 1;
2806 i.types[op] |= Disp8;
2807 }
2808 }
2809 else if (i.base_reg->reg_num == ESP_REG_NUM)
2810 {
2811 default_seg = &ss;
2812 }
2813 i.sib.scale = i.log2_scale_factor;
2814 if (i.index_reg == 0)
2815 {
2816 /* <disp>(%esp) becomes two byte modrm with no index
2817 register. We've already stored the code for esp
2818 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
2819 Any base register besides %esp will not use the
2820 extra modrm byte. */
2821 i.sib.index = NO_INDEX_REGISTER;
2822#if !SCALE1_WHEN_NO_INDEX
2823 /* Another case where we force the second modrm byte. */
2824 if (i.log2_scale_factor)
2825 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
252b5132 2826#endif
29b0f896
AM		 2827 }
2828 else
2829 {
2830 i.sib.index = i.index_reg->reg_num;
2831 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
2832 if ((i.index_reg->reg_flags & RegRex) != 0)
2833 i.rex |= REX_EXTY;
2834 }
2835 i.rm.mode = mode_from_disp_size (i.types[op]);
2836 }
252b5132 2837
29b0f896
AM		 2838 if (fake_zero_displacement)
2839 {
2840 /* Fakes a zero displacement assuming that i.types[op]
2841 holds the correct displacement size. */
2842 expressionS *exp;
2843
2844 assert (i.op[op].disps == 0);
2845 exp = &disp_expressions[i.disp_operands++];
2846 i.op[op].disps = exp;
2847 exp->X_op = O_constant;
2848 exp->X_add_number = 0;
2849 exp->X_add_symbol = (symbolS *) 0;
2850 exp->X_op_symbol = (symbolS *) 0;
2851 }
2852 }
252b5132 2853
29b0f896
AM		 2854 /* Fill in i.rm.reg or i.rm.regmem field with register operand
2855 (if any) based on i.tm.extension_opcode. Again, we must be
2856 careful to make sure that segment/control/debug/test/MMX
2857 registers are coded into the i.rm.reg field. */
2858 if (i.reg_operands)
2859 {
2860 unsigned int op =
2861 ((i.types[0]
2862 & (Reg | RegMMX | RegXMM
2863 | SReg2 | SReg3
2864 | Control | Debug | Test))
2865 ? 0
2866 : ((i.types[1]
2867 & (Reg | RegMMX | RegXMM
2868 | SReg2 | SReg3
2869 | Control | Debug | Test))
2870 ? 1
2871 : 2));
2872 /* If there is an extension opcode to put here, the register
2873 number must be put into the regmem field. */
2874 if (i.tm.extension_opcode != None)
2875 {
2876 i.rm.regmem = i.op[op].regs->reg_num;
2877 if ((i.op[op].regs->reg_flags & RegRex) != 0)
2878 i.rex |= REX_EXTZ;
2879 }
2880 else
2881 {
2882 i.rm.reg = i.op[op].regs->reg_num;
2883 if ((i.op[op].regs->reg_flags & RegRex) != 0)
2884 i.rex |= REX_EXTX;
2885 }
252b5132 2886
29b0f896
AM		 2887 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
2888 must set it to 3 to indicate this is a register operand
2889 in the regmem field. */
2890 if (!i.mem_operands)
2891 i.rm.mode = 3;
2892 }
252b5132 2893
29b0f896
AM		 2894 /* Fill in i.rm.reg field with extension opcode (if any). */
2895 if (i.tm.extension_opcode != None)
2896 i.rm.reg = i.tm.extension_opcode;
2897 }
2898 return default_seg;
2899}
252b5132 2900
29b0f896
AM		 2901static void
2902output_branch ()
2903{
2904 char *p;
2905 int code16;
2906 int prefix;
2907 relax_substateT subtype;
2908 symbolS *sym;
2909 offsetT off;
2910
2911 code16 = 0;
2912 if (flag_code == CODE_16BIT)
2913 code16 = CODE16;
2914
2915 prefix = 0;
2916 if (i.prefix[DATA_PREFIX] != 0)
252b5132 2917 {
29b0f896
AM		 2918 prefix = 1;
2919 i.prefixes -= 1;
2920 code16 ^= CODE16;
252b5132 2921 }
29b0f896
AM		 2922 /* Pentium4 branch hints. */
2923 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
2924 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
2f66722d 2925 {
29b0f896
AM		 2926 prefix++;
2927 i.prefixes--;
2928 }
2929 if (i.prefix[REX_PREFIX] != 0)
2930 {
2931 prefix++;
2932 i.prefixes--;
2f66722d
AM		 2933 }
2934
29b0f896
AM		 2935 if (i.prefixes != 0 && !intel_syntax)
2936 as_warn (_("skipping prefixes on this instruction"));
2937
2938 /* It's always a symbol; End frag & setup for relax.
2939 Make sure there is enough room in this frag for the largest
2940 instruction we may generate in md_convert_frag. This is 2
2941 bytes for the opcode and room for the prefix and largest
2942 displacement. */
2943 frag_grow (prefix + 2 + 4);
2944 /* Prefix and 1 opcode byte go in fr_fix. */
2945 p = frag_more (prefix + 1);
2946 if (i.prefix[DATA_PREFIX] != 0)
2947 *p++ = DATA_PREFIX_OPCODE;
2948 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE
2949 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE)
2950 *p++ = i.prefix[SEG_PREFIX];
2951 if (i.prefix[REX_PREFIX] != 0)
2952 *p++ = i.prefix[REX_PREFIX];
2953 *p = i.tm.base_opcode;
2954
2955 if ((unsigned char) *p == JUMP_PC_RELATIVE)
2956 subtype = ENCODE_RELAX_STATE (UNCOND_JUMP, SMALL);
2957 else if ((cpu_arch_flags & Cpu386) != 0)
2958 subtype = ENCODE_RELAX_STATE (COND_JUMP, SMALL);
2959 else
2960 subtype = ENCODE_RELAX_STATE (COND_JUMP86, SMALL);
2961 subtype |= code16;
3e73aa7c 2962
29b0f896
AM		 2963 sym = i.op[0].disps->X_add_symbol;
2964 off = i.op[0].disps->X_add_number;
3e73aa7c 2965
29b0f896
AM		 2966 if (i.op[0].disps->X_op != O_constant
2967 && i.op[0].disps->X_op != O_symbol)
3e73aa7c 2968 {
29b0f896
AM		 2969 /* Handle complex expressions. */
2970 sym = make_expr_symbol (i.op[0].disps);
2971 off = 0;
2972 }
3e73aa7c 2973
29b0f896
AM		 2974 /* 1 possible extra opcode + 4 byte displacement go in var part.
2975 Pass reloc in fr_var. */
2976 frag_var (rs_machine_dependent, 5, i.reloc[0], subtype, sym, off, p);
2977}
3e73aa7c 2978
29b0f896
AM		 2979static void
2980output_jump ()
2981{
2982 char *p;
2983 int size;
2984
2985 if (i.tm.opcode_modifier & JumpByte)
2986 {
2987 /* This is a loop or jecxz type instruction. */
2988 size = 1;
2989 if (i.prefix[ADDR_PREFIX] != 0)
2990 {
2991 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE);
2992 i.prefixes -= 1;
2993 }
2994 /* Pentium4 branch hints. */
2995 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
2996 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
2997 {
2998 FRAG_APPEND_1_CHAR (i.prefix[SEG_PREFIX]);
2999 i.prefixes--;
3e73aa7c
JH		 3000 }
3001 }
29b0f896
AM		 3002 else
3003 {
3004 int code16;
3e73aa7c 3005
29b0f896
AM		 3006 code16 = 0;
3007 if (flag_code == CODE_16BIT)
3008 code16 = CODE16;
3e73aa7c 3009
29b0f896
AM		 3010 if (i.prefix[DATA_PREFIX] != 0)
3011 {
3012 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE);
3013 i.prefixes -= 1;
3014 code16 ^= CODE16;
3015 }
252b5132 3016
29b0f896
AM		 3017 size = 4;
3018 if (code16)
3019 size = 2;
3020 }
9fcc94b6 3021
29b0f896
AM		 3022 if (i.prefix[REX_PREFIX] != 0)
3023 {
3024 FRAG_APPEND_1_CHAR (i.prefix[REX_PREFIX]);
3025 i.prefixes -= 1;
3026 }
252b5132 3027
29b0f896
AM		 3028 if (i.prefixes != 0 && !intel_syntax)
3029 as_warn (_("skipping prefixes on this instruction"));
e0890092 3030
29b0f896
AM		 3031 p = frag_more (1 + size);
3032 *p++ = i.tm.base_opcode;
e0890092 3033
062cd5e7
AS		 3034 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
3035 i.op[0].disps, 1, reloc (size, 1, 1, i.reloc[0]));
29b0f896 3036}
e0890092 3037
29b0f896
AM		 3038static void
3039output_interseg_jump ()
3040{
3041 char *p;
3042 int size;
3043 int prefix;
3044 int code16;
252b5132 3045
29b0f896
AM		 3046 code16 = 0;
3047 if (flag_code == CODE_16BIT)
3048 code16 = CODE16;
a217f122 3049
29b0f896
AM		 3050 prefix = 0;
3051 if (i.prefix[DATA_PREFIX] != 0)
3052 {
3053 prefix = 1;
3054 i.prefixes -= 1;
3055 code16 ^= CODE16;
3056 }
3057 if (i.prefix[REX_PREFIX] != 0)
3058 {
3059 prefix++;
3060 i.prefixes -= 1;
3061 }
252b5132 3062
29b0f896
AM		 3063 size = 4;
3064 if (code16)
3065 size = 2;
252b5132 3066
29b0f896
AM		 3067 if (i.prefixes != 0 && !intel_syntax)
3068 as_warn (_("skipping prefixes on this instruction"));
252b5132 3069
29b0f896
AM		 3070 /* 1 opcode; 2 segment; offset */
3071 p = frag_more (prefix + 1 + 2 + size);
3e73aa7c 3072
29b0f896
AM		 3073 if (i.prefix[DATA_PREFIX] != 0)
3074 *p++ = DATA_PREFIX_OPCODE;
252b5132 3075
29b0f896
AM		 3076 if (i.prefix[REX_PREFIX] != 0)
3077 *p++ = i.prefix[REX_PREFIX];
252b5132 3078
29b0f896
AM		 3079 *p++ = i.tm.base_opcode;
3080 if (i.op[1].imms->X_op == O_constant)
3081 {
3082 offsetT n = i.op[1].imms->X_add_number;
252b5132 3083
29b0f896
AM		 3084 if (size == 2
3085 && !fits_in_unsigned_word (n)
3086 && !fits_in_signed_word (n))
3087 {
3088 as_bad (_("16-bit jump out of range"));
3089 return;
3090 }
3091 md_number_to_chars (p, n, size);
3092 }
3093 else
3094 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
3095 i.op[1].imms, 0, reloc (size, 0, 0, i.reloc[1]));
3096 if (i.op[0].imms->X_op != O_constant)
3097 as_bad (_("can't handle non absolute segment in `%s'"),
3098 i.tm.name);
3099 md_number_to_chars (p + size, (valueT) i.op[0].imms->X_add_number, 2);
3100}
a217f122 3101
29b0f896
AM		 3102static void
3103output_insn ()
3104{
3105 /* Tie dwarf2 debug info to the address at the start of the insn.
3106 We can't do this after the insn has been output as the current
3107 frag may have been closed off. eg. by frag_var. */
3108 dwarf2_emit_insn (0);
3109
3110 /* Output jumps. */
3111 if (i.tm.opcode_modifier & Jump)
3112 output_branch ();
3113 else if (i.tm.opcode_modifier & (JumpByte | JumpDword))
3114 output_jump ();
3115 else if (i.tm.opcode_modifier & JumpInterSegment)
3116 output_interseg_jump ();
3117 else
3118 {
3119 /* Output normal instructions here. */
3120 char *p;
3121 unsigned char *q;
252b5132 3122
29b0f896
AM		 3123 /* All opcodes on i386 have either 1 or 2 bytes. We may use third
3124 byte for the SSE instructions to specify a prefix they require. */
3125 if (i.tm.base_opcode & 0xff0000)
3126 add_prefix ((i.tm.base_opcode >> 16) & 0xff);
252b5132 3127
29b0f896
AM		 3128 /* The prefix bytes. */
3129 for (q = i.prefix;
3130 q < i.prefix + sizeof (i.prefix) / sizeof (i.prefix[0]);
3131 q++)
3132 {
3133 if (*q)
3134 {
3135 p = frag_more (1);
3136 md_number_to_chars (p, (valueT) *q, 1);
3137 }
3138 }
252b5132 3139
29b0f896
AM		 3140 /* Now the opcode; be careful about word order here! */
3141 if (fits_in_unsigned_byte (i.tm.base_opcode))
3142 {
3143 FRAG_APPEND_1_CHAR (i.tm.base_opcode);
3144 }
3145 else
3146 {
3147 p = frag_more (2);
3148 /* Put out high byte first: can't use md_number_to_chars! */
3149 *p++ = (i.tm.base_opcode >> 8) & 0xff;
3150 *p = i.tm.base_opcode & 0xff;
3151 }
3e73aa7c 3152
29b0f896
AM		 3153 /* Now the modrm byte and sib byte (if present). */
3154 if (i.tm.opcode_modifier & Modrm)
3155 {
3156 p = frag_more (1);
3157 md_number_to_chars (p,
3158 (valueT) (i.rm.regmem << 0
3159 | i.rm.reg << 3
3160 | i.rm.mode << 6),
3161 1);
3162 /* If i.rm.regmem == ESP (4)
3163 && i.rm.mode != (Register mode)
3164 && not 16 bit
3165 ==> need second modrm byte. */
3166 if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING
3167 && i.rm.mode != 3
3168 && !(i.base_reg && (i.base_reg->reg_type & Reg16) != 0))
3169 {
3170 p = frag_more (1);
3171 md_number_to_chars (p,
3172 (valueT) (i.sib.base << 0
3173 | i.sib.index << 3
3174 | i.sib.scale << 6),
3175 1);
3176 }
3177 }
3e73aa7c 3178
29b0f896
AM		 3179 if (i.disp_operands)
3180 output_disp ();
3e73aa7c 3181
29b0f896
AM		 3182 if (i.imm_operands)
3183 output_imm ();
3184 }
252b5132 3185
29b0f896
AM		 3186#ifdef DEBUG386
3187 if (flag_debug)
3188 {
3189 pi (line, &i);
3190 }
3191#endif /* DEBUG386 */
3192}
252b5132 3193
29b0f896
AM		 3194static void
3195output_disp ()
3196{
3197 char *p;
3198 unsigned int n;
252b5132 3199
29b0f896
AM		 3200 for (n = 0; n < i.operands; n++)
3201 {
3202 if (i.types[n] & Disp)
3203 {
3204 if (i.op[n].disps->X_op == O_constant)
3205 {
3206 int size;
3207 offsetT val;
252b5132 3208
29b0f896
AM		 3209 size = 4;
3210 if (i.types[n] & (Disp8 | Disp16 | Disp64))
3211 {
3212 size = 2;
3213 if (i.types[n] & Disp8)
3214 size = 1;
3215 if (i.types[n] & Disp64)
3216 size = 8;
3217 }
3218 val = offset_in_range (i.op[n].disps->X_add_number,
3219 size);
3220 p = frag_more (size);
3221 md_number_to_chars (p, val, size);
3222 }
3223 else
3224 {
3225 int size = 4;
3226 int sign = 0;
3227 int pcrel = (i.flags[n] & Operand_PCrel) != 0;
3228
3229 /* The PC relative address is computed relative
3230 to the instruction boundary, so in case immediate
3231 fields follows, we need to adjust the value. */
3232 if (pcrel && i.imm_operands)
3233 {
3234 int imm_size = 4;
3235 unsigned int n1;
252b5132 3236
29b0f896
AM		 3237 for (n1 = 0; n1 < i.operands; n1++)
3238 if (i.types[n1] & Imm)
252b5132 3239 {
29b0f896 3240 if (i.types[n1] & (Imm8 | Imm8S | Imm16 | Imm64))
252b5132 3241 {
29b0f896
AM		 3242 imm_size = 2;
3243 if (i.types[n1] & (Imm8 | Imm8S))
3244 imm_size = 1;
3245 if (i.types[n1] & Imm64)
3246 imm_size = 8;
252b5132 3247 }
29b0f896 3248 break;
252b5132 3249 }
29b0f896
AM		 3250 /* We should find the immediate. */
3251 if (n1 == i.operands)
3252 abort ();
3253 i.op[n].disps->X_add_number -= imm_size;
3254 }
520dc8e8 3255
29b0f896
AM		 3256 if (i.types[n] & Disp32S)
3257 sign = 1;
3e73aa7c 3258
29b0f896
AM		 3259 if (i.types[n] & (Disp16 | Disp64))
3260 {
3261 size = 2;
3262 if (i.types[n] & Disp64)
3263 size = 8;
3264 }
520dc8e8 3265
29b0f896 3266 p = frag_more (size);
062cd5e7
AS		 3267 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
3268 i.op[n].disps, pcrel,
3269 reloc (size, pcrel, sign, i.reloc[n]));
29b0f896
AM		 3270 }
3271 }
3272 }
3273}
252b5132 3274
29b0f896
AM		 3275static void
3276output_imm ()
3277{
3278 char *p;
3279 unsigned int n;
252b5132 3280
29b0f896
AM		 3281 for (n = 0; n < i.operands; n++)
3282 {
3283 if (i.types[n] & Imm)
3284 {
3285 if (i.op[n].imms->X_op == O_constant)
3286 {
3287 int size;
3288 offsetT val;
b4cac588 3289
29b0f896
AM		 3290 size = 4;
3291 if (i.types[n] & (Imm8 | Imm8S | Imm16 | Imm64))
3292 {
3293 size = 2;
3294 if (i.types[n] & (Imm8 | Imm8S))
3295 size = 1;
3296 else if (i.types[n] & Imm64)
3297 size = 8;
3298 }
3299 val = offset_in_range (i.op[n].imms->X_add_number,
3300 size);
3301 p = frag_more (size);
3302 md_number_to_chars (p, val, size);
3303 }
3304 else
3305 {
3306 /* Not absolute_section.
3307 Need a 32-bit fixup (don't support 8bit
3308 non-absolute imms). Try to support other
3309 sizes ... */
3310 RELOC_ENUM reloc_type;
3311 int size = 4;
3312 int sign = 0;
3313
3314 if ((i.types[n] & (Imm32S))
3315 && i.suffix == QWORD_MNEM_SUFFIX)
3316 sign = 1;
3317 if (i.types[n] & (Imm8 | Imm8S | Imm16 | Imm64))
3318 {
3319 size = 2;
3320 if (i.types[n] & (Imm8 | Imm8S))
3321 size = 1;
3322 if (i.types[n] & Imm64)
3323 size = 8;
3324 }
520dc8e8 3325
29b0f896
AM		 3326 p = frag_more (size);
3327 reloc_type = reloc (size, 0, sign, i.reloc[n]);
252b5132 3328#ifdef BFD_ASSEMBLER
29b0f896
AM		 3329 if (reloc_type == BFD_RELOC_32
3330 && GOT_symbol
3331 && GOT_symbol == i.op[n].imms->X_add_symbol
3332 && (i.op[n].imms->X_op == O_symbol
3333 || (i.op[n].imms->X_op == O_add
3334 && ((symbol_get_value_expression
3335 (i.op[n].imms->X_op_symbol)->X_op)
3336 == O_subtract))))
3337 {
3338 /* We don't support dynamic linking on x86-64 yet. */
3339 if (flag_code == CODE_64BIT)
3340 abort ();
3341 reloc_type = BFD_RELOC_386_GOTPC;
3342 i.op[n].imms->X_add_number += 3;
3343 }
252b5132 3344#endif
29b0f896
AM		 3345 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
3346 i.op[n].imms, 0, reloc_type);
3347 }
3348 }
3349 }
252b5132
RH		 3350}
3351\f
f3c180ae
AM		 3352#ifndef LEX_AT
3353static char *lex_got PARAMS ((RELOC_ENUM *, int *));
3354
3355/* Parse operands of the form
3356 <symbol>@GOTOFF+<nnn>
3357 and similar .plt or .got references.
3358
3359 If we find one, set up the correct relocation in RELOC and copy the
3360 input string, minus the `@GOTOFF' into a malloc'd buffer for
3361 parsing by the calling routine. Return this buffer, and if ADJUST
3362 is non-null set it to the length of the string we removed from the
3363 input line. Otherwise return NULL. */
3364static char *
3365lex_got (reloc, adjust)
3366 RELOC_ENUM *reloc;
3367 int *adjust;
3368{
3369 static const char * const mode_name[NUM_FLAG_CODE] = { "32", "16", "64" };
3370 static const struct {
3371 const char *str;
3372 const RELOC_ENUM rel[NUM_FLAG_CODE];
3373 } gotrel[] = {
3374 { "PLT", { BFD_RELOC_386_PLT32, 0, BFD_RELOC_X86_64_PLT32 } },
3375 { "GOTOFF", { BFD_RELOC_386_GOTOFF, 0, 0 } },
3376 { "GOTPCREL", { 0, 0, BFD_RELOC_X86_64_GOTPCREL } },
3377 { "GOT", { BFD_RELOC_386_GOT32, 0, BFD_RELOC_X86_64_GOT32 } }
3378 };
3379 char *cp;
3380 unsigned int j;
3381
3382 for (cp = input_line_pointer; *cp != '@'; cp++)
3383 if (is_end_of_line[(unsigned char) *cp])
3384 return NULL;
3385
3386 for (j = 0; j < sizeof (gotrel) / sizeof (gotrel[0]); j++)
3387 {
3388 int len;
3389
3390 len = strlen (gotrel[j].str);
28f81592 3391 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
f3c180ae
AM		 3392 {
3393 if (gotrel[j].rel[(unsigned int) flag_code] != 0)
3394 {
28f81592
AM		 3395 int first, second;
3396 char *tmpbuf, *past_reloc;
f3c180ae
AM		 3397
3398 *reloc = gotrel[j].rel[(unsigned int) flag_code];
28f81592
AM		 3399 if (adjust)
3400 *adjust = len;
f3c180ae
AM		 3401
3402 if (GOT_symbol == NULL)
3403 GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME);
3404
3405 /* Replace the relocation token with ' ', so that
3406 errors like foo@GOTOFF1 will be detected. */
28f81592
AM		 3407
3408 /* The length of the first part of our input line. */
f3c180ae 3409 first = cp - input_line_pointer;
28f81592
AM		 3410
3411 /* The second part goes from after the reloc token until
3412 (and including) an end_of_line char. Don't use strlen
3413 here as the end_of_line char may not be a NUL. */
3414 past_reloc = cp + 1 + len;
3415 for (cp = past_reloc; !is_end_of_line[(unsigned char) *cp++]; )
3416 ;
3417 second = cp - past_reloc;
3418
3419 /* Allocate and copy string. The trailing NUL shouldn't
3420 be necessary, but be safe. */
3421 tmpbuf = xmalloc (first + second + 2);
f3c180ae
AM		 3422 memcpy (tmpbuf, input_line_pointer, first);
3423 tmpbuf[first] = ' ';
28f81592
AM		 3424 memcpy (tmpbuf + first + 1, past_reloc, second);
3425 tmpbuf[first + second + 1] = '\0';
f3c180ae
AM		 3426 return tmpbuf;
3427 }
3428
3429 as_bad (_("@%s reloc is not supported in %s bit mode"),
3430 gotrel[j].str, mode_name[(unsigned int) flag_code]);
3431 return NULL;
3432 }
3433 }
3434
3435 /* Might be a symbol version string. Don't as_bad here. */
3436 return NULL;
3437}
3438
3439/* x86_cons_fix_new is called via the expression parsing code when a
3440 reloc is needed. We use this hook to get the correct .got reloc. */
3441static RELOC_ENUM got_reloc = NO_RELOC;
3442
3443void
3444x86_cons_fix_new (frag, off, len, exp)
3445 fragS *frag;
3446 unsigned int off;
3447 unsigned int len;
3448 expressionS *exp;
3449{
3450 RELOC_ENUM r = reloc (len, 0, 0, got_reloc);
3451 got_reloc = NO_RELOC;
3452 fix_new_exp (frag, off, len, exp, 0, r);
3453}
3454
3455void
3456x86_cons (exp, size)
3457 expressionS *exp;
3458 int size;
3459{
3460 if (size == 4)
3461 {
3462 /* Handle @GOTOFF and the like in an expression. */
3463 char *save;
3464 char *gotfree_input_line;
3465 int adjust;
3466
3467 save = input_line_pointer;
3468 gotfree_input_line = lex_got (&got_reloc, &adjust);
3469 if (gotfree_input_line)
3470 input_line_pointer = gotfree_input_line;
3471
3472 expression (exp);
3473
3474 if (gotfree_input_line)
3475 {
3476 /* expression () has merrily parsed up to the end of line,
3477 or a comma - in the wrong buffer. Transfer how far
3478 input_line_pointer has moved to the right buffer. */
3479 input_line_pointer = (save
3480 + (input_line_pointer - gotfree_input_line)
3481 + adjust);
3482 free (gotfree_input_line);
3483 }
3484 }
3485 else
3486 expression (exp);
3487}
3488#endif
3489
252b5132
RH		 3490static int i386_immediate PARAMS ((char *));
3491
3492static int
3493i386_immediate (imm_start)
3494 char *imm_start;
3495{
3496 char *save_input_line_pointer;
f3c180ae
AM		 3497#ifndef LEX_AT
3498 char *gotfree_input_line;
3499#endif
252b5132 3500 segT exp_seg = 0;
47926f60 3501 expressionS *exp;
252b5132
RH		 3502
3503 if (i.imm_operands == MAX_IMMEDIATE_OPERANDS)
3504 {
d0b47220 3505 as_bad (_("only 1 or 2 immediate operands are allowed"));
252b5132
RH		 3506 return 0;
3507 }
3508
3509 exp = &im_expressions[i.imm_operands++];
520dc8e8 3510 i.op[this_operand].imms = exp;
252b5132
RH		 3511
3512 if (is_space_char (*imm_start))
3513 ++imm_start;
3514
3515 save_input_line_pointer = input_line_pointer;
3516 input_line_pointer = imm_start;
3517
3518#ifndef LEX_AT
f3c180ae
AM		 3519 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL);
3520 if (gotfree_input_line)
3521 input_line_pointer = gotfree_input_line;
252b5132
RH		 3522#endif
3523
3524 exp_seg = expression (exp);
3525
83183c0c 3526 SKIP_WHITESPACE ();
252b5132 3527 if (*input_line_pointer)
f3c180ae 3528 as_bad (_("junk `%s' after expression"), input_line_pointer);
252b5132
RH		 3529
3530 input_line_pointer = save_input_line_pointer;
f3c180ae
AM		 3531#ifndef LEX_AT
3532 if (gotfree_input_line)
3533 free (gotfree_input_line);
3534#endif
252b5132 3535
2daf4fd8 3536 if (exp->X_op == O_absent || exp->X_op == O_big)
252b5132 3537 {
47926f60 3538 /* Missing or bad expr becomes absolute 0. */
d0b47220 3539 as_bad (_("missing or invalid immediate expression `%s' taken as 0"),
24eab124 3540 imm_start);
252b5132
RH		 3541 exp->X_op = O_constant;
3542 exp->X_add_number = 0;
3543 exp->X_add_symbol = (symbolS *) 0;
3544 exp->X_op_symbol = (symbolS *) 0;
252b5132 3545 }
3e73aa7c 3546 else if (exp->X_op == O_constant)
252b5132 3547 {
47926f60 3548 /* Size it properly later. */
3e73aa7c
JH		 3549 i.types[this_operand] |= Imm64;
3550 /* If BFD64, sign extend val. */
3551 if (!use_rela_relocations)
3552 if ((exp->X_add_number & ~(((addressT) 2 << 31) - 1)) == 0)
3553 exp->X_add_number = (exp->X_add_number ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
252b5132 3554 }
4c63da97 3555#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
47926f60 3556 else if (1
4c63da97 3557#ifdef BFD_ASSEMBLER
47926f60 3558 && OUTPUT_FLAVOR == bfd_target_aout_flavour
4c63da97 3559#endif
47926f60 3560 && exp_seg != text_section
24eab124
AM		 3561 && exp_seg != data_section
3562 && exp_seg != bss_section
3563 && exp_seg != undefined_section
252b5132 3564#ifdef BFD_ASSEMBLER
24eab124 3565 && !bfd_is_com_section (exp_seg)
252b5132 3566#endif
24eab124 3567 )
252b5132 3568 {
4c63da97 3569#ifdef BFD_ASSEMBLER
d0b47220 3570 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
4c63da97 3571#else
d0b47220 3572 as_bad (_("unimplemented segment type %d in operand"), exp_seg);
4c63da97 3573#endif
252b5132
RH		 3574 return 0;
3575 }
3576#endif
3577 else
3578 {
3579 /* This is an address. The size of the address will be
24eab124 3580 determined later, depending on destination register,
3e73aa7c
JH		 3581 suffix, or the default for the section. */
3582 i.types[this_operand] |= Imm8 | Imm16 | Imm32 | Imm32S | Imm64;
252b5132
RH		 3583 }
3584
3585 return 1;
3586}
3587
551c1ca1 3588static char *i386_scale PARAMS ((char *));
252b5132 3589
551c1ca1 3590static char *
252b5132
RH		 3591i386_scale (scale)
3592 char *scale;
3593{
551c1ca1
AM		 3594 offsetT val;
3595 char *save = input_line_pointer;
252b5132 3596
551c1ca1
AM		 3597 input_line_pointer = scale;
3598 val = get_absolute_expression ();
3599
3600 switch (val)
252b5132 3601 {
551c1ca1
AM		 3602 case 0:
3603 case 1:
252b5132
RH		 3604 i.log2_scale_factor = 0;
3605 break;
551c1ca1 3606 case 2:
252b5132
RH		 3607 i.log2_scale_factor = 1;
3608 break;
551c1ca1 3609 case 4:
252b5132
RH		 3610 i.log2_scale_factor = 2;
3611 break;
551c1ca1 3612 case 8:
252b5132
RH		 3613 i.log2_scale_factor = 3;
3614 break;
3615 default:
252b5132 3616 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
24eab124 3617 scale);
551c1ca1
AM		 3618 input_line_pointer = save;
3619 return NULL;
252b5132 3620 }
29b0f896 3621 if (i.log2_scale_factor != 0 && i.index_reg == 0)
252b5132
RH		 3622 {
3623 as_warn (_("scale factor of %d without an index register"),
24eab124 3624 1 << i.log2_scale_factor);
252b5132
RH		 3625#if SCALE1_WHEN_NO_INDEX
3626 i.log2_scale_factor = 0;
3627#endif
3628 }
551c1ca1
AM		 3629 scale = input_line_pointer;
3630 input_line_pointer = save;
3631 return scale;
252b5132
RH		 3632}
3633
3634static int i386_displacement PARAMS ((char *, char *));
3635
3636static int
3637i386_displacement (disp_start, disp_end)
3638 char *disp_start;
3639 char *disp_end;
3640{
29b0f896 3641 expressionS *exp;
252b5132
RH		 3642 segT exp_seg = 0;
3643 char *save_input_line_pointer;
f3c180ae
AM		 3644#ifndef LEX_AT
3645 char *gotfree_input_line;
3646#endif
252b5132
RH		 3647 int bigdisp = Disp32;
3648
3e73aa7c 3649 if (flag_code == CODE_64BIT)
7ecd2f8b 3650 {
29b0f896
AM		 3651 if (i.prefix[ADDR_PREFIX] == 0)
3652 bigdisp = Disp64;
7ecd2f8b
JH		 3653 }
3654 else if ((flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0))
3655 bigdisp = Disp16;
252b5132
RH		 3656 i.types[this_operand] |= bigdisp;
3657
3658 exp = &disp_expressions[i.disp_operands];
520dc8e8 3659 i.op[this_operand].disps = exp;
252b5132
RH		 3660 i.disp_operands++;
3661 save_input_line_pointer = input_line_pointer;
3662 input_line_pointer = disp_start;
3663 END_STRING_AND_SAVE (disp_end);
3664
3665#ifndef GCC_ASM_O_HACK
3666#define GCC_ASM_O_HACK 0
3667#endif
3668#if GCC_ASM_O_HACK
3669 END_STRING_AND_SAVE (disp_end + 1);
3670 if ((i.types[this_operand] & BaseIndex) != 0
24eab124 3671 && displacement_string_end[-1] == '+')
252b5132
RH		 3672 {
3673 /* This hack is to avoid a warning when using the "o"
24eab124
AM		 3674 constraint within gcc asm statements.
3675 For instance:
3676
3677 #define _set_tssldt_desc(n,addr,limit,type) \
3678 __asm__ __volatile__ ( \
3679 "movw %w2,%0\n\t" \
3680 "movw %w1,2+%0\n\t" \
3681 "rorl $16,%1\n\t" \
3682 "movb %b1,4+%0\n\t" \
3683 "movb %4,5+%0\n\t" \
3684 "movb $0,6+%0\n\t" \
3685 "movb %h1,7+%0\n\t" \
3686 "rorl $16,%1" \
3687 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
3688
3689 This works great except that the output assembler ends
3690 up looking a bit weird if it turns out that there is
3691 no offset. You end up producing code that looks like:
3692
3693 #APP
3694 movw $235,(%eax)
3695 movw %dx,2+(%eax)
3696 rorl $16,%edx
3697 movb %dl,4+(%eax)
3698 movb $137,5+(%eax)
3699 movb $0,6+(%eax)
3700 movb %dh,7+(%eax)
3701 rorl $16,%edx
3702 #NO_APP
3703
47926f60 3704 So here we provide the missing zero. */
24eab124
AM		 3705
3706 *displacement_string_end = '0';
252b5132
RH		 3707 }
3708#endif
3709#ifndef LEX_AT
f3c180ae
AM		 3710 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL);
3711 if (gotfree_input_line)
3712 input_line_pointer = gotfree_input_line;
252b5132
RH		 3713#endif
3714
24eab124 3715 exp_seg = expression (exp);
252b5132 3716
636c26b0
AM		 3717 SKIP_WHITESPACE ();
3718 if (*input_line_pointer)
3719 as_bad (_("junk `%s' after expression"), input_line_pointer);
3720#if GCC_ASM_O_HACK
3721 RESTORE_END_STRING (disp_end + 1);
3722#endif
3723 RESTORE_END_STRING (disp_end);
3724 input_line_pointer = save_input_line_pointer;
3725#ifndef LEX_AT
3726 if (gotfree_input_line)
3727 free (gotfree_input_line);
3728#endif
3729
252b5132 3730#ifdef BFD_ASSEMBLER
24eab124
AM		 3731 /* We do this to make sure that the section symbol is in
3732 the symbol table. We will ultimately change the relocation
47926f60 3733 to be relative to the beginning of the section. */
1ae12ab7
AM		 3734 if (i.reloc[this_operand] == BFD_RELOC_386_GOTOFF
3735 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL)
24eab124 3736 {
636c26b0
AM		 3737 if (exp->X_op != O_symbol)
3738 {
3739 as_bad (_("bad expression used with @%s"),
3740 (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL
3741 ? "GOTPCREL"
3742 : "GOTOFF"));
3743 return 0;
3744 }
3745
e5cb08ac 3746 if (S_IS_LOCAL (exp->X_add_symbol)
24eab124
AM		 3747 && S_GET_SEGMENT (exp->X_add_symbol) != undefined_section)
3748 section_symbol (S_GET_SEGMENT (exp->X_add_symbol));
24eab124
AM		 3749 exp->X_op = O_subtract;
3750 exp->X_op_symbol = GOT_symbol;
1ae12ab7 3751 if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL)
29b0f896 3752 i.reloc[this_operand] = BFD_RELOC_32_PCREL;
23df1078 3753 else
29b0f896 3754 i.reloc[this_operand] = BFD_RELOC_32;
24eab124 3755 }
252b5132
RH		 3756#endif
3757
2daf4fd8
AM		 3758 if (exp->X_op == O_absent || exp->X_op == O_big)
3759 {
47926f60 3760 /* Missing or bad expr becomes absolute 0. */
d0b47220 3761 as_bad (_("missing or invalid displacement expression `%s' taken as 0"),
2daf4fd8
AM		 3762 disp_start);
3763 exp->X_op = O_constant;
3764 exp->X_add_number = 0;
3765 exp->X_add_symbol = (symbolS *) 0;
3766 exp->X_op_symbol = (symbolS *) 0;
3767 }
3768
4c63da97 3769#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
45288df1 3770 if (exp->X_op != O_constant
4c63da97 3771#ifdef BFD_ASSEMBLER
45288df1 3772 && OUTPUT_FLAVOR == bfd_target_aout_flavour
4c63da97 3773#endif
45288df1
AM		 3774 && exp_seg != text_section
3775 && exp_seg != data_section
3776 && exp_seg != bss_section
3777 && exp_seg != undefined_section)
24eab124 3778 {
4c63da97 3779#ifdef BFD_ASSEMBLER
d0b47220 3780 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
4c63da97 3781#else
d0b47220 3782 as_bad (_("unimplemented segment type %d in operand"), exp_seg);
4c63da97 3783#endif
24eab124
AM		 3784 return 0;
3785 }
252b5132 3786#endif
3e73aa7c
JH		 3787 else if (flag_code == CODE_64BIT)
3788 i.types[this_operand] |= Disp32S | Disp32;
252b5132
RH		 3789 return 1;
3790}
3791
e5cb08ac 3792static int i386_index_check PARAMS ((const char *));
252b5132 3793
eecb386c 3794/* Make sure the memory operand we've been dealt is valid.
47926f60
KH		 3795 Return 1 on success, 0 on a failure. */
3796
252b5132 3797static int
eecb386c
AM		 3798i386_index_check (operand_string)
3799 const char *operand_string;
252b5132 3800{
3e73aa7c 3801 int ok;
24eab124 3802#if INFER_ADDR_PREFIX
eecb386c
AM		 3803 int fudged = 0;
3804
24eab124
AM		 3805 tryprefix:
3806#endif
3e73aa7c
JH		 3807 ok = 1;
3808 if (flag_code == CODE_64BIT)
3809 {
7ecd2f8b
JH		 3810 if (i.prefix[ADDR_PREFIX] == 0)
3811 {
3812 /* 64bit checks. */
3813 if ((i.base_reg
3814 && ((i.base_reg->reg_type & Reg64) == 0)
3815 && (i.base_reg->reg_type != BaseIndex
3816 || i.index_reg))
3817 || (i.index_reg
29b0f896
AM		 3818 && ((i.index_reg->reg_type & (Reg64 | BaseIndex))
3819 != (Reg64 | BaseIndex))))
7ecd2f8b
JH		 3820 ok = 0;
3821 }
3822 else
3823 {
3824 /* 32bit checks. */
3825 if ((i.base_reg
3826 && (i.base_reg->reg_type & (Reg32 | RegRex)) != Reg32)
3827 || (i.index_reg
29b0f896
AM		 3828 && ((i.index_reg->reg_type & (Reg32 | BaseIndex | RegRex))
3829 != (Reg32 | BaseIndex))))
7ecd2f8b
JH		 3830 ok = 0;
3831 }
3e73aa7c
JH		 3832 }
3833 else
3834 {
3835 if ((flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0))
3836 {
3837 /* 16bit checks. */
3838 if ((i.base_reg
29b0f896
AM		 3839 && ((i.base_reg->reg_type & (Reg16 | BaseIndex | RegRex))
3840 != (Reg16 | BaseIndex)))
3e73aa7c 3841 || (i.index_reg
29b0f896
AM		 3842 && (((i.index_reg->reg_type & (Reg16 | BaseIndex))
3843 != (Reg16 | BaseIndex))
3844 || !(i.base_reg
3845 && i.base_reg->reg_num < 6
3846 && i.index_reg->reg_num >= 6
3847 && i.log2_scale_factor == 0))))
3e73aa7c
JH		 3848 ok = 0;
3849 }
3850 else
e5cb08ac 3851 {
3e73aa7c
JH		 3852 /* 32bit checks. */
3853 if ((i.base_reg
3854 && (i.base_reg->reg_type & (Reg32 | RegRex)) != Reg32)
3855 || (i.index_reg
29b0f896
AM		 3856 && ((i.index_reg->reg_type & (Reg32 | BaseIndex | RegRex))
3857 != (Reg32 | BaseIndex))))
e5cb08ac 3858 ok = 0;
3e73aa7c
JH		 3859 }
3860 }
3861 if (!ok)
24eab124
AM		 3862 {
3863#if INFER_ADDR_PREFIX
3e73aa7c
JH		 3864 if (flag_code != CODE_64BIT
3865 && i.prefix[ADDR_PREFIX] == 0 && stackop_size != '\0')
24eab124
AM		 3866 {
3867 i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE;
3868 i.prefixes += 1;
b23bac36
AM		 3869 /* Change the size of any displacement too. At most one of
3870 Disp16 or Disp32 is set.
3871 FIXME. There doesn't seem to be any real need for separate
3872 Disp16 and Disp32 flags. The same goes for Imm16 and Imm32.
47926f60 3873 Removing them would probably clean up the code quite a lot. */
29b0f896
AM		 3874 if (i.types[this_operand] & (Disp16 | Disp32))
3875 i.types[this_operand] ^= (Disp16 | Disp32);
eecb386c 3876 fudged = 1;
24eab124
AM		 3877 goto tryprefix;
3878 }
eecb386c
AM		 3879 if (fudged)
3880 as_bad (_("`%s' is not a valid base/index expression"),
3881 operand_string);
3882 else
c388dee8 3883#endif
eecb386c
AM		 3884 as_bad (_("`%s' is not a valid %s bit base/index expression"),
3885 operand_string,
3e73aa7c 3886 flag_code_names[flag_code]);
eecb386c 3887 return 0;
24eab124
AM		 3888 }
3889 return 1;
3890}
252b5132 3891
252b5132 3892/* Parse OPERAND_STRING into the i386_insn structure I. Returns non-zero
47926f60 3893 on error. */
252b5132 3894
252b5132
RH		 3895static int
3896i386_operand (operand_string)
3897 char *operand_string;
3898{
af6bdddf
AM		 3899 const reg_entry *r;
3900 char *end_op;
24eab124 3901 char *op_string = operand_string;
252b5132 3902
24eab124 3903 if (is_space_char (*op_string))
252b5132
RH		 3904 ++op_string;
3905
24eab124 3906 /* We check for an absolute prefix (differentiating,
47926f60 3907 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
24eab124
AM		 3908 if (*op_string == ABSOLUTE_PREFIX)
3909 {
3910 ++op_string;
3911 if (is_space_char (*op_string))
3912 ++op_string;
3913 i.types[this_operand] |= JumpAbsolute;
3914 }
252b5132 3915
47926f60 3916 /* Check if operand is a register. */
af6bdddf
AM		 3917 if ((*op_string == REGISTER_PREFIX || allow_naked_reg)
3918 && (r = parse_register (op_string, &end_op)) != NULL)
24eab124 3919 {
24eab124
AM		 3920 /* Check for a segment override by searching for ':' after a
3921 segment register. */
3922 op_string = end_op;
3923 if (is_space_char (*op_string))
3924 ++op_string;
3925 if (*op_string == ':' && (r->reg_type & (SReg2 | SReg3)))
3926 {
3927 switch (r->reg_num)
3928 {
3929 case 0:
3930 i.seg[i.mem_operands] = &es;
3931 break;
3932 case 1:
3933 i.seg[i.mem_operands] = &cs;
3934 break;
3935 case 2:
3936 i.seg[i.mem_operands] = &ss;
3937 break;
3938 case 3:
3939 i.seg[i.mem_operands] = &ds;
3940 break;
3941 case 4:
3942 i.seg[i.mem_operands] = &fs;
3943 break;
3944 case 5:
3945 i.seg[i.mem_operands] = &gs;
3946 break;
3947 }
252b5132 3948
24eab124 3949 /* Skip the ':' and whitespace. */
252b5132
RH		 3950 ++op_string;
3951 if (is_space_char (*op_string))
24eab124 3952 ++op_string;
252b5132 3953
24eab124
AM		 3954 if (!is_digit_char (*op_string)
3955 && !is_identifier_char (*op_string)
3956 && *op_string != '('
3957 && *op_string != ABSOLUTE_PREFIX)
3958 {
3959 as_bad (_("bad memory operand `%s'"), op_string);
3960 return 0;
3961 }
47926f60 3962 /* Handle case of %es:*foo. */
24eab124
AM		 3963 if (*op_string == ABSOLUTE_PREFIX)
3964 {
3965 ++op_string;
3966 if (is_space_char (*op_string))
3967 ++op_string;
3968 i.types[this_operand] |= JumpAbsolute;
3969 }
3970 goto do_memory_reference;
3971 }
3972 if (*op_string)
3973 {
d0b47220 3974 as_bad (_("junk `%s' after register"), op_string);
24eab124
AM		 3975 return 0;
3976 }
3977 i.types[this_operand] |= r->reg_type & ~BaseIndex;
520dc8e8 3978 i.op[this_operand].regs = r;
24eab124
AM		 3979 i.reg_operands++;
3980 }
af6bdddf
AM		 3981 else if (*op_string == REGISTER_PREFIX)
3982 {
3983 as_bad (_("bad register name `%s'"), op_string);
3984 return 0;
3985 }
24eab124 3986 else if (*op_string == IMMEDIATE_PREFIX)
ce8a8b2f 3987 {
24eab124
AM		 3988 ++op_string;
3989 if (i.types[this_operand] & JumpAbsolute)
3990 {
d0b47220 3991 as_bad (_("immediate operand illegal with absolute jump"));
24eab124
AM		 3992 return 0;
3993 }
3994 if (!i386_immediate (op_string))
3995 return 0;
3996 }
3997 else if (is_digit_char (*op_string)
3998 || is_identifier_char (*op_string)
e5cb08ac 3999 || *op_string == '(')
24eab124 4000 {
47926f60 4001 /* This is a memory reference of some sort. */
af6bdddf 4002 char *base_string;
252b5132 4003
47926f60 4004 /* Start and end of displacement string expression (if found). */
eecb386c
AM		 4005 char *displacement_string_start;
4006 char *displacement_string_end;
252b5132 4007
24eab124 4008 do_memory_reference:
24eab124
AM		 4009 if ((i.mem_operands == 1
4010 && (current_templates->start->opcode_modifier & IsString) == 0)
4011 || i.mem_operands == 2)
4012 {
4013 as_bad (_("too many memory references for `%s'"),
4014 current_templates->start->name);
4015 return 0;
4016 }
252b5132 4017
24eab124
AM		 4018 /* Check for base index form. We detect the base index form by
4019 looking for an ')' at the end of the operand, searching
4020 for the '(' matching it, and finding a REGISTER_PREFIX or ','
4021 after the '('. */
af6bdddf 4022 base_string = op_string + strlen (op_string);
c3332e24 4023
af6bdddf
AM		 4024 --base_string;
4025 if (is_space_char (*base_string))
4026 --base_string;
252b5132 4027
47926f60 4028 /* If we only have a displacement, set-up for it to be parsed later. */
af6bdddf
AM		 4029 displacement_string_start = op_string;
4030 displacement_string_end = base_string + 1;
252b5132 4031
24eab124
AM		 4032 if (*base_string == ')')
4033 {
af6bdddf 4034 char *temp_string;
24eab124
AM		 4035 unsigned int parens_balanced = 1;
4036 /* We've already checked that the number of left & right ()'s are
47926f60 4037 equal, so this loop will not be infinite. */
24eab124
AM		 4038 do
4039 {
4040 base_string--;
4041 if (*base_string == ')')
4042 parens_balanced++;
4043 if (*base_string == '(')
4044 parens_balanced--;
4045 }
4046 while (parens_balanced);
c3332e24 4047
af6bdddf 4048 temp_string = base_string;
c3332e24 4049
24eab124 4050 /* Skip past '(' and whitespace. */
252b5132
RH		 4051 ++base_string;
4052 if (is_space_char (*base_string))
24eab124 4053 ++base_string;
252b5132 4054
af6bdddf
AM		 4055 if (*base_string == ','
4056 || ((*base_string == REGISTER_PREFIX || allow_naked_reg)
4057 && (i.base_reg = parse_register (base_string, &end_op)) != NULL))
252b5132 4058 {
af6bdddf 4059 displacement_string_end = temp_string;
252b5132 4060
af6bdddf 4061 i.types[this_operand] |= BaseIndex;
252b5132 4062
af6bdddf 4063 if (i.base_reg)
24eab124 4064 {
24eab124
AM		 4065 base_string = end_op;
4066 if (is_space_char (*base_string))
4067 ++base_string;
af6bdddf
AM		 4068 }
4069
4070 /* There may be an index reg or scale factor here. */
4071 if (*base_string == ',')
4072 {
4073 ++base_string;
4074 if (is_space_char (*base_string))
4075 ++base_string;
4076
4077 if ((*base_string == REGISTER_PREFIX || allow_naked_reg)
4078 && (i.index_reg = parse_register (base_string, &end_op)) != NULL)
24eab124 4079 {
af6bdddf 4080 base_string = end_op;
24eab124
AM		 4081 if (is_space_char (*base_string))
4082 ++base_string;
af6bdddf
AM		 4083 if (*base_string == ',')
4084 {
4085 ++base_string;
4086 if (is_space_char (*base_string))
4087 ++base_string;
4088 }
e5cb08ac 4089 else if (*base_string != ')')
af6bdddf
AM		 4090 {
4091 as_bad (_("expecting `,' or `)' after index register in `%s'"),
4092 operand_string);
4093 return 0;
4094 }
24eab124 4095 }
af6bdddf 4096 else if (*base_string == REGISTER_PREFIX)
24eab124 4097 {
af6bdddf 4098 as_bad (_("bad register name `%s'"), base_string);
24eab124
AM		 4099 return 0;
4100 }
252b5132 4101
47926f60 4102 /* Check for scale factor. */
551c1ca1 4103 if (*base_string != ')')
af6bdddf 4104 {
551c1ca1
AM		 4105 char *end_scale = i386_scale (base_string);
4106
4107 if (!end_scale)
af6bdddf 4108 return 0;
24eab124 4109
551c1ca1 4110 base_string = end_scale;
af6bdddf
AM		 4111 if (is_space_char (*base_string))
4112 ++base_string;
4113 if (*base_string != ')')
4114 {
4115 as_bad (_("expecting `)' after scale factor in `%s'"),
4116 operand_string);
4117 return 0;
4118 }
4119 }
4120 else if (!i.index_reg)
24eab124 4121 {
af6bdddf
AM		 4122 as_bad (_("expecting index register or scale factor after `,'; got '%c'"),
4123 *base_string);
24eab124
AM		 4124 return 0;
4125 }
4126 }
af6bdddf 4127 else if (*base_string != ')')
24eab124 4128 {
af6bdddf
AM		 4129 as_bad (_("expecting `,' or `)' after base register in `%s'"),
4130 operand_string);
24eab124
AM		 4131 return 0;
4132 }
c3332e24 4133 }
af6bdddf 4134 else if (*base_string == REGISTER_PREFIX)
c3332e24 4135 {
af6bdddf 4136 as_bad (_("bad register name `%s'"), base_string);
24eab124 4137 return 0;
c3332e24 4138 }
24eab124
AM		 4139 }
4140
4141 /* If there's an expression beginning the operand, parse it,
4142 assuming displacement_string_start and
4143 displacement_string_end are meaningful. */
4144 if (displacement_string_start != displacement_string_end)
4145 {
4146 if (!i386_displacement (displacement_string_start,
4147 displacement_string_end))
4148 return 0;
4149 }
4150
4151 /* Special case for (%dx) while doing input/output op. */
4152 if (i.base_reg
4153 && i.base_reg->reg_type == (Reg16 | InOutPortReg)
4154 && i.index_reg == 0
4155 && i.log2_scale_factor == 0
4156 && i.seg[i.mem_operands] == 0
4157 && (i.types[this_operand] & Disp) == 0)
4158 {
4159 i.types[this_operand] = InOutPortReg;
4160 return 1;
4161 }
4162
eecb386c
AM		 4163 if (i386_index_check (operand_string) == 0)
4164 return 0;
24eab124
AM		 4165 i.mem_operands++;
4166 }
4167 else
ce8a8b2f
AM		 4168 {
4169 /* It's not a memory operand; argh! */
24eab124
AM		 4170 as_bad (_("invalid char %s beginning operand %d `%s'"),
4171 output_invalid (*op_string),
4172 this_operand + 1,
4173 op_string);
4174 return 0;
4175 }
47926f60 4176 return 1; /* Normal return. */
252b5132
RH		 4177}
4178\f
ee7fcc42
AM		 4179/* md_estimate_size_before_relax()
4180
4181 Called just before relax() for rs_machine_dependent frags. The x86
4182 assembler uses these frags to handle variable size jump
4183 instructions.
4184
4185 Any symbol that is now undefined will not become defined.
4186 Return the correct fr_subtype in the frag.
4187 Return the initial "guess for variable size of frag" to caller.
4188 The guess is actually the growth beyond the fixed part. Whatever
4189 we do to grow the fixed or variable part contributes to our
4190 returned value. */
4191
252b5132
RH		 4192int
4193md_estimate_size_before_relax (fragP, segment)
29b0f896
AM		 4194 fragS *fragP;
4195 segT segment;
252b5132 4196{
252b5132 4197 /* We've already got fragP->fr_subtype right; all we have to do is
b98ef147
AM		 4198 check for un-relaxable symbols. On an ELF system, we can't relax
4199 an externally visible symbol, because it may be overridden by a
4200 shared library. */
4201 if (S_GET_SEGMENT (fragP->fr_symbol) != segment
6d249963 4202#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
b98ef147
AM		 4203 || S_IS_EXTERNAL (fragP->fr_symbol)
4204 || S_IS_WEAK (fragP->fr_symbol)
4205#endif
4206 )
252b5132 4207 {
b98ef147
AM		 4208 /* Symbol is undefined in this segment, or we need to keep a
4209 reloc so that weak symbols can be overridden. */
4210 int size = (fragP->fr_subtype & CODE16) ? 2 : 4;
f3c180ae 4211 RELOC_ENUM reloc_type;
ee7fcc42
AM		 4212 unsigned char *opcode;
4213 int old_fr_fix;
f6af82bd 4214
ee7fcc42
AM		 4215 if (fragP->fr_var != NO_RELOC)
4216 reloc_type = fragP->fr_var;
b98ef147 4217 else if (size == 2)
f6af82bd
AM		 4218 reloc_type = BFD_RELOC_16_PCREL;
4219 else
4220 reloc_type = BFD_RELOC_32_PCREL;
252b5132 4221
ee7fcc42
AM		 4222 old_fr_fix = fragP->fr_fix;
4223 opcode = (unsigned char *) fragP->fr_opcode;
4224
fddf5b5b 4225 switch (TYPE_FROM_RELAX_STATE (fragP->fr_subtype))
252b5132 4226 {
fddf5b5b
AM		 4227 case UNCOND_JUMP:
4228 /* Make jmp (0xeb) a (d)word displacement jump. */
47926f60 4229 opcode[0] = 0xe9;
252b5132 4230 fragP->fr_fix += size;
062cd5e7
AS		 4231 fix_new (fragP, old_fr_fix, size,
4232 fragP->fr_symbol,
4233 fragP->fr_offset, 1,
4234 reloc_type);
252b5132
RH		 4235 break;
4236
fddf5b5b
AM		 4237 case COND_JUMP86:
4238 if (no_cond_jump_promotion)
93c2a809
AM		 4239 goto relax_guess;
4240
fddf5b5b
AM		 4241 if (size == 2)
4242 {
4243 /* Negate the condition, and branch past an
4244 unconditional jump. */
4245 opcode[0] ^= 1;
4246 opcode[1] = 3;
4247 /* Insert an unconditional jump. */
4248 opcode[2] = 0xe9;
4249 /* We added two extra opcode bytes, and have a two byte
4250 offset. */
4251 fragP->fr_fix += 2 + 2;
062cd5e7
AS		 4252 fix_new (fragP, old_fr_fix + 2, 2,
4253 fragP->fr_symbol,
4254 fragP->fr_offset, 1,
4255 reloc_type);
fddf5b5b
AM		 4256 break;
4257 }
4258 /* Fall through. */
4259
4260 case COND_JUMP:
4261 if (no_cond_jump_promotion)
93c2a809
AM		 4262 goto relax_guess;
4263
24eab124 4264 /* This changes the byte-displacement jump 0x7N
fddf5b5b 4265 to the (d)word-displacement jump 0x0f,0x8N. */
252b5132 4266 opcode[1] = opcode[0] + 0x10;
f6af82bd 4267 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
47926f60
KH		 4268 /* We've added an opcode byte. */
4269 fragP->fr_fix += 1 + size;
062cd5e7
AS		 4270 fix_new (fragP, old_fr_fix + 1, size,
4271 fragP->fr_symbol,
4272 fragP->fr_offset, 1,
4273 reloc_type);
252b5132 4274 break;
fddf5b5b
AM		 4275
4276 default:
4277 BAD_CASE (fragP->fr_subtype);
4278 break;
252b5132
RH		 4279 }
4280 frag_wane (fragP);
ee7fcc42 4281 return fragP->fr_fix - old_fr_fix;
252b5132 4282 }
93c2a809
AM		 4283
4284 relax_guess:
4285 /* Guess size depending on current relax state. Initially the relax
4286 state will correspond to a short jump and we return 1, because
4287 the variable part of the frag (the branch offset) is one byte
4288 long. However, we can relax a section more than once and in that
4289 case we must either set fr_subtype back to the unrelaxed state,
4290 or return the value for the appropriate branch. */
4291 return md_relax_table[fragP->fr_subtype].rlx_length;
ee7fcc42
AM		 4292}
4293
47926f60
KH		 4294/* Called after relax() is finished.
4295
4296 In: Address of frag.
4297 fr_type == rs_machine_dependent.
4298 fr_subtype is what the address relaxed to.
4299
4300 Out: Any fixSs and constants are set up.
4301 Caller will turn frag into a ".space 0". */
4302
252b5132
RH		 4303#ifndef BFD_ASSEMBLER
4304void
4305md_convert_frag (headers, sec, fragP)
a04b544b
ILT		 4306 object_headers *headers ATTRIBUTE_UNUSED;
4307 segT sec ATTRIBUTE_UNUSED;
29b0f896 4308 fragS *fragP;
252b5132
RH		 4309#else
4310void
4311md_convert_frag (abfd, sec, fragP)
ab9da554
ILT		 4312 bfd *abfd ATTRIBUTE_UNUSED;
4313 segT sec ATTRIBUTE_UNUSED;
29b0f896 4314 fragS *fragP;
252b5132
RH		 4315#endif
4316{
29b0f896 4317 unsigned char *opcode;
252b5132 4318 unsigned char *where_to_put_displacement = NULL;
847f7ad4
AM		 4319 offsetT target_address;
4320 offsetT opcode_address;
252b5132 4321 unsigned int extension = 0;
847f7ad4 4322 offsetT displacement_from_opcode_start;
252b5132
RH		 4323
4324 opcode = (unsigned char *) fragP->fr_opcode;
4325
47926f60 4326 /* Address we want to reach in file space. */
252b5132 4327 target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset;
252b5132 4328
47926f60 4329 /* Address opcode resides at in file space. */
252b5132
RH		 4330 opcode_address = fragP->fr_address + fragP->fr_fix;
4331
47926f60 4332 /* Displacement from opcode start to fill into instruction. */
252b5132
RH		 4333 displacement_from_opcode_start = target_address - opcode_address;
4334
fddf5b5b 4335 if ((fragP->fr_subtype & BIG) == 0)
252b5132 4336 {
47926f60
KH		 4337 /* Don't have to change opcode. */
4338 extension = 1; /* 1 opcode + 1 displacement */
252b5132 4339 where_to_put_displacement = &opcode[1];
fddf5b5b
AM		 4340 }
4341 else
4342 {
4343 if (no_cond_jump_promotion
4344 && TYPE_FROM_RELAX_STATE (fragP->fr_subtype) != UNCOND_JUMP)
4345 as_warn_where (fragP->fr_file, fragP->fr_line, _("long jump required"));
252b5132 4346
fddf5b5b
AM		 4347 switch (fragP->fr_subtype)
4348 {
4349 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG):
4350 extension = 4; /* 1 opcode + 4 displacement */
4351 opcode[0] = 0xe9;
4352 where_to_put_displacement = &opcode[1];
4353 break;
252b5132 4354
fddf5b5b
AM		 4355 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16):
4356 extension = 2; /* 1 opcode + 2 displacement */
4357 opcode[0] = 0xe9;
4358 where_to_put_displacement = &opcode[1];
4359 break;
252b5132 4360
fddf5b5b
AM		 4361 case ENCODE_RELAX_STATE (COND_JUMP, BIG):
4362 case ENCODE_RELAX_STATE (COND_JUMP86, BIG):
4363 extension = 5; /* 2 opcode + 4 displacement */
4364 opcode[1] = opcode[0] + 0x10;
4365 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
4366 where_to_put_displacement = &opcode[2];
4367 break;
252b5132 4368
fddf5b5b
AM		 4369 case ENCODE_RELAX_STATE (COND_JUMP, BIG16):
4370 extension = 3; /* 2 opcode + 2 displacement */
4371 opcode[1] = opcode[0] + 0x10;
4372 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
4373 where_to_put_displacement = &opcode[2];
4374 break;
252b5132 4375
fddf5b5b
AM		 4376 case ENCODE_RELAX_STATE (COND_JUMP86, BIG16):
4377 extension = 4;
4378 opcode[0] ^= 1;
4379 opcode[1] = 3;
4380 opcode[2] = 0xe9;
4381 where_to_put_displacement = &opcode[3];
4382 break;
4383
4384 default:
4385 BAD_CASE (fragP->fr_subtype);
4386 break;
4387 }
252b5132 4388 }
fddf5b5b 4389
47926f60 4390 /* Now put displacement after opcode. */
252b5132
RH		 4391 md_number_to_chars ((char *) where_to_put_displacement,
4392 (valueT) (displacement_from_opcode_start - extension),
fddf5b5b 4393 DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype));
252b5132
RH		 4394 fragP->fr_fix += extension;
4395}
4396\f
47926f60
KH		 4397/* Size of byte displacement jmp. */
4398int md_short_jump_size = 2;
4399
4400/* Size of dword displacement jmp. */
4401int md_long_jump_size = 5;
252b5132 4402
47926f60
KH		 4403/* Size of relocation record. */
4404const int md_reloc_size = 8;
252b5132
RH		 4405
4406void
4407md_create_short_jump (ptr, from_addr, to_addr, frag, to_symbol)
4408 char *ptr;
4409 addressT from_addr, to_addr;
ab9da554
ILT		 4410 fragS *frag ATTRIBUTE_UNUSED;
4411 symbolS *to_symbol ATTRIBUTE_UNUSED;
252b5132 4412{
847f7ad4 4413 offsetT offset;
252b5132
RH		 4414
4415 offset = to_addr - (from_addr + 2);
47926f60
KH		 4416 /* Opcode for byte-disp jump. */
4417 md_number_to_chars (ptr, (valueT) 0xeb, 1);
252b5132
RH		 4418 md_number_to_chars (ptr + 1, (valueT) offset, 1);
4419}
4420
4421void
4422md_create_long_jump (ptr, from_addr, to_addr, frag, to_symbol)
4423 char *ptr;
4424 addressT from_addr, to_addr;
a38cf1db
AM		 4425 fragS *frag ATTRIBUTE_UNUSED;
4426 symbolS *to_symbol ATTRIBUTE_UNUSED;
252b5132 4427{
847f7ad4 4428 offsetT offset;
252b5132 4429
a38cf1db
AM		 4430 offset = to_addr - (from_addr + 5);
4431 md_number_to_chars (ptr, (valueT) 0xe9, 1);
4432 md_number_to_chars (ptr + 1, (valueT) offset, 4);
252b5132
RH		 4433}
4434\f
4435/* Apply a fixup (fixS) to segment data, once it has been determined
4436 by our caller that we have all the info we need to fix it up.
4437
4438 On the 386, immediates, displacements, and data pointers are all in
4439 the same (little-endian) format, so we don't need to care about which
4440 we are handling. */
4441
94f592af
NC		 4442void
4443md_apply_fix3 (fixP, valP, seg)
47926f60
KH		 4444 /* The fix we're to put in. */
4445 fixS *fixP;
47926f60 4446 /* Pointer to the value of the bits. */
94f592af 4447 valueT * valP;
47926f60
KH		 4448 /* Segment fix is from. */
4449 segT seg ATTRIBUTE_UNUSED;
252b5132 4450{
94f592af
NC		 4451 char *p = fixP->fx_where + fixP->fx_frag->fr_literal;
4452 valueT value = * valP;
252b5132 4453
e1b283bb 4454#if defined (BFD_ASSEMBLER) && !defined (TE_Mach)
93382f6d
AM		 4455 if (fixP->fx_pcrel)
4456 {
4457 switch (fixP->fx_r_type)
4458 {
5865bb77
ILT		 4459 default:
4460 break;
4461
93382f6d
AM		 4462 case BFD_RELOC_32:
4463 fixP->fx_r_type = BFD_RELOC_32_PCREL;
4464 break;
4465 case BFD_RELOC_16:
4466 fixP->fx_r_type = BFD_RELOC_16_PCREL;
4467 break;
4468 case BFD_RELOC_8:
4469 fixP->fx_r_type = BFD_RELOC_8_PCREL;
4470 break;
4471 }
4472 }
252b5132 4473
0723899b
ILT		 4474 /* This is a hack. There should be a better way to handle this.
4475 This covers for the fact that bfd_install_relocation will
4476 subtract the current location (for partial_inplace, PC relative
4477 relocations); see more below. */
93382f6d
AM		 4478 if ((fixP->fx_r_type == BFD_RELOC_32_PCREL
4479 || fixP->fx_r_type == BFD_RELOC_16_PCREL
4480 || fixP->fx_r_type == BFD_RELOC_8_PCREL)
7c44d1d3 4481 && fixP->fx_addsy && !use_rela_relocations)
252b5132
RH		 4482 {
4483#ifndef OBJ_AOUT
4484 if (OUTPUT_FLAVOR == bfd_target_elf_flavour
4485#ifdef TE_PE
4486 || OUTPUT_FLAVOR == bfd_target_coff_flavour
4487#endif
4488 )
4489 value += fixP->fx_where + fixP->fx_frag->fr_address;
4490#endif
4491#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2f66722d 4492 if (OUTPUT_FLAVOR == bfd_target_elf_flavour)
252b5132 4493 {
2f66722d
AM		 4494 segT fseg = S_GET_SEGMENT (fixP->fx_addsy);
4495
4496 if ((fseg == seg
4497 || (symbol_section_p (fixP->fx_addsy)
4498 && fseg != absolute_section))
29b0f896
AM		 4499 && !S_IS_EXTERNAL (fixP->fx_addsy)
4500 && !S_IS_WEAK (fixP->fx_addsy)
2f66722d 4501 && S_IS_DEFINED (fixP->fx_addsy)
29b0f896 4502 && !S_IS_COMMON (fixP->fx_addsy))
2f66722d
AM		 4503 {
4504 /* Yes, we add the values in twice. This is because
4505 bfd_perform_relocation subtracts them out again. I think
4506 bfd_perform_relocation is broken, but I don't dare change
4507 it. FIXME. */
4508 value += fixP->fx_where + fixP->fx_frag->fr_address;
4509 }
252b5132
RH		 4510 }
4511#endif
4512#if defined (OBJ_COFF) && defined (TE_PE)
4513 /* For some reason, the PE format does not store a section
24eab124 4514 address offset for a PC relative symbol. */
252b5132
RH		 4515 if (S_GET_SEGMENT (fixP->fx_addsy) != seg)
4516 value += md_pcrel_from (fixP);
4517#endif
4518 }
4519
4520 /* Fix a few things - the dynamic linker expects certain values here,
47926f60 4521 and we must not dissappoint it. */
252b5132
RH		 4522#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
4523 if (OUTPUT_FLAVOR == bfd_target_elf_flavour
4524 && fixP->fx_addsy)
47926f60
KH		 4525 switch (fixP->fx_r_type)
4526 {
4527 case BFD_RELOC_386_PLT32:
3e73aa7c 4528 case BFD_RELOC_X86_64_PLT32:
47926f60
KH		 4529 /* Make the jump instruction point to the address of the operand. At
4530 runtime we merely add the offset to the actual PLT entry. */
4531 value = -4;
4532 break;
4533 case BFD_RELOC_386_GOTPC:
4534
4535/* This is tough to explain. We end up with this one if we have
252b5132
RH		 4536 * operands that look like "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal
4537 * here is to obtain the absolute address of the GOT, and it is strongly
4538 * preferable from a performance point of view to avoid using a runtime
c3332e24 4539 * relocation for this. The actual sequence of instructions often look
252b5132 4540 * something like:
c3332e24 4541 *
24eab124 4542 * call .L66
252b5132 4543 * .L66:
24eab124
AM		 4544 * popl %ebx
4545 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
c3332e24 4546 *
24eab124 4547 * The call and pop essentially return the absolute address of
252b5132
RH		 4548 * the label .L66 and store it in %ebx. The linker itself will
4549 * ultimately change the first operand of the addl so that %ebx points to
4550 * the GOT, but to keep things simple, the .o file must have this operand
4551 * set so that it generates not the absolute address of .L66, but the
4552 * absolute address of itself. This allows the linker itself simply
4553 * treat a GOTPC relocation as asking for a pcrel offset to the GOT to be
4554 * added in, and the addend of the relocation is stored in the operand
4555 * field for the instruction itself.
c3332e24 4556 *
24eab124 4557 * Our job here is to fix the operand so that it would add the correct
252b5132
RH		 4558 * offset so that %ebx would point to itself. The thing that is tricky is
4559 * that .-.L66 will point to the beginning of the instruction, so we need
4560 * to further modify the operand so that it will point to itself.
4561 * There are other cases where you have something like:
c3332e24 4562 *
24eab124 4563 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
c3332e24 4564 *
252b5132 4565 * and here no correction would be required. Internally in the assembler
c3332e24 4566 * we treat operands of this form as not being pcrel since the '.' is
252b5132
RH		 4567 * explicitly mentioned, and I wonder whether it would simplify matters
4568 * to do it this way. Who knows. In earlier versions of the PIC patches,
4569 * the pcrel_adjust field was used to store the correction, but since the
47926f60
KH		 4570 * expression is not pcrel, I felt it would be confusing to do it this
4571 * way. */
4572
4573 value -= 1;
4574 break;
4575 case BFD_RELOC_386_GOT32:
3e73aa7c 4576 case BFD_RELOC_X86_64_GOT32:
47926f60
KH		 4577 value = 0; /* Fully resolved at runtime. No addend. */
4578 break;
4579 case BFD_RELOC_386_GOTOFF:
3e73aa7c 4580 case BFD_RELOC_X86_64_GOTPCREL:
47926f60
KH		 4581 break;
4582
4583 case BFD_RELOC_VTABLE_INHERIT:
4584 case BFD_RELOC_VTABLE_ENTRY:
4585 fixP->fx_done = 0;
94f592af 4586 return;
47926f60
KH		 4587
4588 default:
4589 break;
4590 }
4591#endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
94f592af 4592 * valP = value;
47926f60 4593#endif /* defined (BFD_ASSEMBLER) && !defined (TE_Mach) */
3e73aa7c 4594
3e73aa7c 4595 /* Are we finished with this relocation now? */
94f592af 4596 if (fixP->fx_addsy == NULL && fixP->fx_pcrel == 0)
3e73aa7c 4597 fixP->fx_done = 1;
94f592af 4598#ifdef BFD_ASSEMBLER
3e73aa7c
JH		 4599 else if (use_rela_relocations)
4600 {
4601 fixP->fx_no_overflow = 1;
062cd5e7
AS		 4602 /* Remember value for tc_gen_reloc. */
4603 fixP->fx_addnumber = value;
3e73aa7c
JH		 4604 value = 0;
4605 }
3e73aa7c 4606#endif
94f592af 4607 md_number_to_chars (p, value, fixP->fx_size);
252b5132 4608}
252b5132 4609\f
252b5132
RH		 4610#define MAX_LITTLENUMS 6
4611
47926f60
KH		 4612/* Turn the string pointed to by litP into a floating point constant
4613 of type TYPE, and emit the appropriate bytes. The number of
4614 LITTLENUMS emitted is stored in *SIZEP. An error message is
4615 returned, or NULL on OK. */
4616
252b5132
RH		 4617char *
4618md_atof (type, litP, sizeP)
2ab9b79e 4619 int type;
252b5132
RH		 4620 char *litP;
4621 int *sizeP;
4622{
4623 int prec;
4624 LITTLENUM_TYPE words[MAX_LITTLENUMS];
4625 LITTLENUM_TYPE *wordP;
4626 char *t;
4627
4628 switch (type)
4629 {
4630 case 'f':
4631 case 'F':
4632 prec = 2;
4633 break;
4634
4635 case 'd':
4636 case 'D':
4637 prec = 4;
4638 break;
4639
4640 case 'x':
4641 case 'X':
4642 prec = 5;
4643 break;
4644
4645 default:
4646 *sizeP = 0;
4647 return _("Bad call to md_atof ()");
4648 }
4649 t = atof_ieee (input_line_pointer, type, words);
4650 if (t)
4651 input_line_pointer = t;
4652
4653 *sizeP = prec * sizeof (LITTLENUM_TYPE);
4654 /* This loops outputs the LITTLENUMs in REVERSE order; in accord with
4655 the bigendian 386. */
4656 for (wordP = words + prec - 1; prec--;)
4657 {
4658 md_number_to_chars (litP, (valueT) (*wordP--), sizeof (LITTLENUM_TYPE));
4659 litP += sizeof (LITTLENUM_TYPE);
4660 }
4661 return 0;
4662}
4663\f
4664char output_invalid_buf[8];
4665
252b5132
RH		 4666static char *
4667output_invalid (c)
4668 int c;
4669{
3882b010 4670 if (ISPRINT (c))
252b5132
RH		 4671 sprintf (output_invalid_buf, "'%c'", c);
4672 else
4673 sprintf (output_invalid_buf, "(0x%x)", (unsigned) c);
4674 return output_invalid_buf;
4675}
4676
af6bdddf 4677/* REG_STRING starts *before* REGISTER_PREFIX. */
252b5132
RH		 4678
4679static const reg_entry *
4680parse_register (reg_string, end_op)
4681 char *reg_string;
4682 char **end_op;
4683{
af6bdddf
AM		 4684 char *s = reg_string;
4685 char *p;
252b5132
RH		 4686 char reg_name_given[MAX_REG_NAME_SIZE + 1];
4687 const reg_entry *r;
4688
4689 /* Skip possible REGISTER_PREFIX and possible whitespace. */
4690 if (*s == REGISTER_PREFIX)
4691 ++s;
4692
4693 if (is_space_char (*s))
4694 ++s;
4695
4696 p = reg_name_given;
af6bdddf 4697 while ((*p++ = register_chars[(unsigned char) *s]) != '\0')
252b5132
RH		 4698 {
4699 if (p >= reg_name_given + MAX_REG_NAME_SIZE)
af6bdddf
AM		 4700 return (const reg_entry *) NULL;
4701 s++;
252b5132
RH		 4702 }
4703
6588847e
DN		 4704 /* For naked regs, make sure that we are not dealing with an identifier.
4705 This prevents confusing an identifier like `eax_var' with register
4706 `eax'. */
4707 if (allow_naked_reg && identifier_chars[(unsigned char) *s])
4708 return (const reg_entry *) NULL;
4709
af6bdddf 4710 *end_op = s;
252b5132
RH		 4711
4712 r = (const reg_entry *) hash_find (reg_hash, reg_name_given);
4713
5f47d35b 4714 /* Handle floating point regs, allowing spaces in the (i) part. */
47926f60 4715 if (r == i386_regtab /* %st is first entry of table */)
5f47d35b 4716 {
5f47d35b
AM		 4717 if (is_space_char (*s))
4718 ++s;
4719 if (*s == '(')
4720 {
af6bdddf 4721 ++s;
5f47d35b
AM		 4722 if (is_space_char (*s))
4723 ++s;
4724 if (*s >= '0' && *s <= '7')
4725 {
4726 r = &i386_float_regtab[*s - '0'];
af6bdddf 4727 ++s;
5f47d35b
AM		 4728 if (is_space_char (*s))
4729 ++s;
4730 if (*s == ')')
4731 {
4732 *end_op = s + 1;
4733 return r;
4734 }
5f47d35b 4735 }
47926f60 4736 /* We have "%st(" then garbage. */
5f47d35b
AM		 4737 return (const reg_entry *) NULL;
4738 }
4739 }
4740
1ae00879 4741 if (r != NULL
29b0f896 4742 && (r->reg_flags & (RegRex64 | RegRex)) != 0
1ae00879
AM		 4743 && flag_code != CODE_64BIT)
4744 {
4745 return (const reg_entry *) NULL;
4746 }
4747
252b5132
RH		 4748 return r;
4749}
4750\f
4cc782b5 4751#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
65172ab8 4752const char *md_shortopts = "kVQ:sq";
252b5132 4753#else
65172ab8 4754const char *md_shortopts = "q";
252b5132 4755#endif
6e0b89ee 4756
252b5132 4757struct option md_longopts[] = {
3e73aa7c
JH		 4758#define OPTION_32 (OPTION_MD_BASE + 0)
4759 {"32", no_argument, NULL, OPTION_32},
6e0b89ee 4760#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3e73aa7c
JH		 4761#define OPTION_64 (OPTION_MD_BASE + 1)
4762 {"64", no_argument, NULL, OPTION_64},
6e0b89ee 4763#endif
252b5132
RH		 4764 {NULL, no_argument, NULL, 0}
4765};
4766size_t md_longopts_size = sizeof (md_longopts);
4767
4768int
4769md_parse_option (c, arg)
4770 int c;
ab9da554 4771 char *arg ATTRIBUTE_UNUSED;
252b5132
RH		 4772{
4773 switch (c)
4774 {
a38cf1db
AM		 4775 case 'q':
4776 quiet_warnings = 1;
252b5132
RH		 4777 break;
4778
4779#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
a38cf1db
AM		 4780 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
4781 should be emitted or not. FIXME: Not implemented. */
4782 case 'Q':
252b5132
RH		 4783 break;
4784
4785 /* -V: SVR4 argument to print version ID. */
4786 case 'V':
4787 print_version_id ();
4788 break;
4789
a38cf1db
AM		 4790 /* -k: Ignore for FreeBSD compatibility. */
4791 case 'k':
252b5132 4792 break;
4cc782b5
ILT		 4793
4794 case 's':
4795 /* -s: On i386 Solaris, this tells the native assembler to use
29b0f896 4796 .stab instead of .stab.excl. We always use .stab anyhow. */
4cc782b5 4797 break;
6e0b89ee 4798
3e73aa7c
JH		 4799 case OPTION_64:
4800 {
4801 const char **list, **l;
4802
3e73aa7c
JH		 4803 list = bfd_target_list ();
4804 for (l = list; *l != NULL; l++)
6e0b89ee
AM		 4805 if (strcmp (*l, "elf64-x86-64") == 0)
4806 {
4807 default_arch = "x86_64";
4808 break;
4809 }
3e73aa7c 4810 if (*l == NULL)
6e0b89ee 4811 as_fatal (_("No compiled in support for x86_64"));
3e73aa7c
JH		 4812 free (list);
4813 }
4814 break;
4815#endif
252b5132 4816
6e0b89ee
AM		 4817 case OPTION_32:
4818 default_arch = "i386";
4819 break;
4820
252b5132
RH		 4821 default:
4822 return 0;
4823 }
4824 return 1;
4825}
4826
4827void
4828md_show_usage (stream)
4829 FILE *stream;
4830{
4cc782b5
ILT		 4831#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
4832 fprintf (stream, _("\
a38cf1db
AM		 4833 -Q ignored\n\
4834 -V print assembler version number\n\
4835 -k ignored\n\
4836 -q quieten some warnings\n\
4837 -s ignored\n"));
4838#else
4839 fprintf (stream, _("\
4840 -q quieten some warnings\n"));
4cc782b5 4841#endif
252b5132
RH		 4842}
4843
4844#ifdef BFD_ASSEMBLER
3e73aa7c
JH		 4845#if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
4846 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
252b5132
RH		 4847
4848/* Pick the target format to use. */
4849
47926f60 4850const char *
252b5132
RH		 4851i386_target_format ()
4852{
3e73aa7c
JH		 4853 if (!strcmp (default_arch, "x86_64"))
4854 set_code_flag (CODE_64BIT);
4855 else if (!strcmp (default_arch, "i386"))
4856 set_code_flag (CODE_32BIT);
4857 else
4858 as_fatal (_("Unknown architecture"));
252b5132
RH		 4859 switch (OUTPUT_FLAVOR)
4860 {
4c63da97
AM		 4861#ifdef OBJ_MAYBE_AOUT
4862 case bfd_target_aout_flavour:
47926f60 4863 return AOUT_TARGET_FORMAT;
4c63da97
AM		 4864#endif
4865#ifdef OBJ_MAYBE_COFF
252b5132
RH		 4866 case bfd_target_coff_flavour:
4867 return "coff-i386";
4c63da97 4868#endif
3e73aa7c 4869#if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
252b5132 4870 case bfd_target_elf_flavour:
3e73aa7c 4871 {
e5cb08ac
KH		 4872 if (flag_code == CODE_64BIT)
4873 use_rela_relocations = 1;
4874 return flag_code == CODE_64BIT ? "elf64-x86-64" : "elf32-i386";
3e73aa7c 4875 }
4c63da97 4876#endif
252b5132
RH		 4877 default:
4878 abort ();
4879 return NULL;
4880 }
4881}
4882
47926f60 4883#endif /* OBJ_MAYBE_ more than one */
a847613f
AM		 4884
4885#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
4886void i386_elf_emit_arch_note ()
4887{
4888 if (OUTPUT_FLAVOR == bfd_target_elf_flavour
4889 && cpu_arch_name != NULL)
4890 {
4891 char *p;
4892 asection *seg = now_seg;
4893 subsegT subseg = now_subseg;
4894 Elf_Internal_Note i_note;
4895 Elf_External_Note e_note;
4896 asection *note_secp;
4897 int len;
4898
4899 /* Create the .note section. */
4900 note_secp = subseg_new (".note", 0);
4901 bfd_set_section_flags (stdoutput,
4902 note_secp,
4903 SEC_HAS_CONTENTS | SEC_READONLY);
4904
4905 /* Process the arch string. */
4906 len = strlen (cpu_arch_name);
4907
4908 i_note.namesz = len + 1;
4909 i_note.descsz = 0;
4910 i_note.type = NT_ARCH;
4911 p = frag_more (sizeof (e_note.namesz));
4912 md_number_to_chars (p, (valueT) i_note.namesz, sizeof (e_note.namesz));
4913 p = frag_more (sizeof (e_note.descsz));
4914 md_number_to_chars (p, (valueT) i_note.descsz, sizeof (e_note.descsz));
4915 p = frag_more (sizeof (e_note.type));
4916 md_number_to_chars (p, (valueT) i_note.type, sizeof (e_note.type));
4917 p = frag_more (len + 1);
4918 strcpy (p, cpu_arch_name);
4919
4920 frag_align (2, 0, 0);
4921
4922 subseg_set (seg, subseg);
4923 }
4924}
4925#endif
47926f60 4926#endif /* BFD_ASSEMBLER */
252b5132 4927\f
252b5132
RH		 4928symbolS *
4929md_undefined_symbol (name)
4930 char *name;
4931{
18dc2407
ILT		 4932 if (name[0] == GLOBAL_OFFSET_TABLE_NAME[0]
4933 && name[1] == GLOBAL_OFFSET_TABLE_NAME[1]
4934 && name[2] == GLOBAL_OFFSET_TABLE_NAME[2]
4935 && strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0)
24eab124
AM		 4936 {
4937 if (!GOT_symbol)
4938 {
4939 if (symbol_find (name))
4940 as_bad (_("GOT already in symbol table"));
4941 GOT_symbol = symbol_new (name, undefined_section,
4942 (valueT) 0, &zero_address_frag);
4943 };
4944 return GOT_symbol;
4945 }
252b5132
RH		 4946 return 0;
4947}
4948
4949/* Round up a section size to the appropriate boundary. */
47926f60 4950
252b5132
RH		 4951valueT
4952md_section_align (segment, size)
ab9da554 4953 segT segment ATTRIBUTE_UNUSED;
252b5132
RH		 4954 valueT size;
4955{
252b5132 4956#ifdef BFD_ASSEMBLER
4c63da97
AM		 4957#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
4958 if (OUTPUT_FLAVOR == bfd_target_aout_flavour)
4959 {
4960 /* For a.out, force the section size to be aligned. If we don't do
4961 this, BFD will align it for us, but it will not write out the
4962 final bytes of the section. This may be a bug in BFD, but it is
4963 easier to fix it here since that is how the other a.out targets
4964 work. */
4965 int align;
4966
4967 align = bfd_get_section_alignment (stdoutput, segment);
4968 size = ((size + (1 << align) - 1) & ((valueT) -1 << align));
4969 }
252b5132
RH		 4970#endif
4971#endif
4972
4973 return size;
4974}
4975
4976/* On the i386, PC-relative offsets are relative to the start of the
4977 next instruction. That is, the address of the offset, plus its
4978 size, since the offset is always the last part of the insn. */
4979
4980long
4981md_pcrel_from (fixP)
4982 fixS *fixP;
4983{
4984 return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address;
4985}
4986
4987#ifndef I386COFF
4988
4989static void
4990s_bss (ignore)
ab9da554 4991 int ignore ATTRIBUTE_UNUSED;
252b5132 4992{
29b0f896 4993 int temp;
252b5132
RH		 4994
4995 temp = get_absolute_expression ();
4996 subseg_set (bss_section, (subsegT) temp);
4997 demand_empty_rest_of_line ();
4998}
4999
5000#endif
5001
252b5132
RH		 5002#ifdef BFD_ASSEMBLER
5003
5004void
5005i386_validate_fix (fixp)
5006 fixS *fixp;
5007{
5008 if (fixp->fx_subsy && fixp->fx_subsy == GOT_symbol)
5009 {
3e73aa7c 5010 /* GOTOFF relocation are nonsense in 64bit mode. */
23df1078
JH		 5011 if (fixp->fx_r_type == BFD_RELOC_32_PCREL)
5012 {
5013 if (flag_code != CODE_64BIT)
5014 abort ();
5015 fixp->fx_r_type = BFD_RELOC_X86_64_GOTPCREL;
5016 }
5017 else
5018 {
5019 if (flag_code == CODE_64BIT)
5020 abort ();
5021 fixp->fx_r_type = BFD_RELOC_386_GOTOFF;
5022 }
252b5132
RH		 5023 fixp->fx_subsy = 0;
5024 }
5025}
5026
252b5132
RH		 5027arelent *
5028tc_gen_reloc (section, fixp)
ab9da554 5029 asection *section ATTRIBUTE_UNUSED;
252b5132
RH		 5030 fixS *fixp;
5031{
5032 arelent *rel;
5033 bfd_reloc_code_real_type code;
5034
5035 switch (fixp->fx_r_type)
5036 {
3e73aa7c
JH		 5037 case BFD_RELOC_X86_64_PLT32:
5038 case BFD_RELOC_X86_64_GOT32:
5039 case BFD_RELOC_X86_64_GOTPCREL:
252b5132
RH		 5040 case BFD_RELOC_386_PLT32:
5041 case BFD_RELOC_386_GOT32:
5042 case BFD_RELOC_386_GOTOFF:
5043 case BFD_RELOC_386_GOTPC:
3e73aa7c 5044 case BFD_RELOC_X86_64_32S:
252b5132
RH		 5045 case BFD_RELOC_RVA:
5046 case BFD_RELOC_VTABLE_ENTRY:
5047 case BFD_RELOC_VTABLE_INHERIT:
5048 code = fixp->fx_r_type;
5049 break;
5050 default:
93382f6d 5051 if (fixp->fx_pcrel)
252b5132 5052 {
93382f6d
AM		 5053 switch (fixp->fx_size)
5054 {
5055 default:
b091f402
AM		 5056 as_bad_where (fixp->fx_file, fixp->fx_line,
5057 _("can not do %d byte pc-relative relocation"),
5058 fixp->fx_size);
93382f6d
AM		 5059 code = BFD_RELOC_32_PCREL;
5060 break;
5061 case 1: code = BFD_RELOC_8_PCREL; break;
5062 case 2: code = BFD_RELOC_16_PCREL; break;
5063 case 4: code = BFD_RELOC_32_PCREL; break;
5064 }
5065 }
5066 else
5067 {
5068 switch (fixp->fx_size)
5069 {
5070 default:
b091f402
AM		 5071 as_bad_where (fixp->fx_file, fixp->fx_line,
5072 _("can not do %d byte relocation"),
5073 fixp->fx_size);
93382f6d
AM		 5074 code = BFD_RELOC_32;
5075 break;
5076 case 1: code = BFD_RELOC_8; break;
5077 case 2: code = BFD_RELOC_16; break;
5078 case 4: code = BFD_RELOC_32; break;
937149dd 5079#ifdef BFD64
3e73aa7c 5080 case 8: code = BFD_RELOC_64; break;
937149dd 5081#endif
93382f6d 5082 }
252b5132
RH		 5083 }
5084 break;
5085 }
252b5132
RH		 5086
5087 if (code == BFD_RELOC_32
5088 && GOT_symbol
5089 && fixp->fx_addsy == GOT_symbol)
3e73aa7c
JH		 5090 {
5091 /* We don't support GOTPC on 64bit targets. */
5092 if (flag_code == CODE_64BIT)
bfb32b52 5093 abort ();
3e73aa7c
JH		 5094 code = BFD_RELOC_386_GOTPC;
5095 }
252b5132
RH		 5096
5097 rel = (arelent *) xmalloc (sizeof (arelent));
49309057
ILT		 5098 rel->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
5099 *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
252b5132
RH		 5100
5101 rel->address = fixp->fx_frag->fr_address + fixp->fx_where;
3e73aa7c
JH		 5102 if (!use_rela_relocations)
5103 {
5104 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
5105 vtable entry to be used in the relocation's section offset. */
5106 if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
5107 rel->address = fixp->fx_offset;
252b5132 5108
3e73aa7c
JH		 5109 if (fixp->fx_pcrel)
5110 rel->addend = fixp->fx_addnumber;
5111 else
5112 rel->addend = 0;
5113 }
5114 /* Use the rela in 64bit mode. */
252b5132 5115 else
3e73aa7c 5116 {
062cd5e7
AS		 5117 if (!fixp->fx_pcrel)
5118 rel->addend = fixp->fx_offset;
5119 else
5120 switch (code)
5121 {
5122 case BFD_RELOC_X86_64_PLT32:
5123 case BFD_RELOC_X86_64_GOT32:
5124 case BFD_RELOC_X86_64_GOTPCREL:
5125 rel->addend = fixp->fx_offset - fixp->fx_size;
5126 break;
5127 default:
5128 rel->addend = (section->vma
5129 - fixp->fx_size
5130 + fixp->fx_addnumber
5131 + md_pcrel_from (fixp));
5132 break;
5133 }
3e73aa7c
JH		 5134 }
5135
252b5132
RH		 5136 rel->howto = bfd_reloc_type_lookup (stdoutput, code);
5137 if (rel->howto == NULL)
5138 {
5139 as_bad_where (fixp->fx_file, fixp->fx_line,
d0b47220 5140 _("cannot represent relocation type %s"),
252b5132
RH		 5141 bfd_get_reloc_code_name (code));
5142 /* Set howto to a garbage value so that we can keep going. */
5143 rel->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_32);
5144 assert (rel->howto != NULL);
5145 }
5146
5147 return rel;
5148}
5149
29b0f896 5150#else /* !BFD_ASSEMBLER */
252b5132
RH		 5151
5152#if (defined(OBJ_AOUT) | defined(OBJ_BOUT))
5153void
5154tc_aout_fix_to_chars (where, fixP, segment_address_in_file)
5155 char *where;
5156 fixS *fixP;
5157 relax_addressT segment_address_in_file;
5158{
47926f60
KH		 5159 /* In: length of relocation (or of address) in chars: 1, 2 or 4.
5160 Out: GNU LD relocation length code: 0, 1, or 2. */
252b5132 5161
47926f60 5162 static const unsigned char nbytes_r_length[] = { 42, 0, 1, 42, 2 };
252b5132
RH		 5163 long r_symbolnum;
5164
5165 know (fixP->fx_addsy != NULL);
5166
5167 md_number_to_chars (where,
5168 (valueT) (fixP->fx_frag->fr_address
5169 + fixP->fx_where - segment_address_in_file),
5170 4);
5171
5172 r_symbolnum = (S_IS_DEFINED (fixP->fx_addsy)
5173 ? S_GET_TYPE (fixP->fx_addsy)
5174 : fixP->fx_addsy->sy_number);
5175
5176 where[6] = (r_symbolnum >> 16) & 0x0ff;
5177 where[5] = (r_symbolnum >> 8) & 0x0ff;
5178 where[4] = r_symbolnum & 0x0ff;
5179 where[7] = ((((!S_IS_DEFINED (fixP->fx_addsy)) << 3) & 0x08)
5180 | ((nbytes_r_length[fixP->fx_size] << 1) & 0x06)
5181 | (((fixP->fx_pcrel << 0) & 0x01) & 0x0f));
5182}
5183
47926f60 5184#endif /* OBJ_AOUT or OBJ_BOUT. */
252b5132
RH		 5185
5186#if defined (I386COFF)
5187
5188short
5189tc_coff_fix2rtype (fixP)
5190 fixS *fixP;
5191{
5192 if (fixP->fx_r_type == R_IMAGEBASE)
5193 return R_IMAGEBASE;
5194
5195 return (fixP->fx_pcrel ?
5196 (fixP->fx_size == 1 ? R_PCRBYTE :
5197 fixP->fx_size == 2 ? R_PCRWORD :
5198 R_PCRLONG) :
5199 (fixP->fx_size == 1 ? R_RELBYTE :
5200 fixP->fx_size == 2 ? R_RELWORD :
5201 R_DIR32));
5202}
5203
5204int
5205tc_coff_sizemachdep (frag)
5206 fragS *frag;
5207{
5208 if (frag->fr_next)
5209 return (frag->fr_next->fr_address - frag->fr_address);
5210 else
5211 return 0;
5212}
5213
47926f60 5214#endif /* I386COFF */
252b5132 5215
29b0f896 5216#endif /* !BFD_ASSEMBLER */
64a0c779
DN		 5217\f
5218/* Parse operands using Intel syntax. This implements a recursive descent
5219 parser based on the BNF grammar published in Appendix B of the MASM 6.1
5220 Programmer's Guide.
5221
5222 FIXME: We do not recognize the full operand grammar defined in the MASM
5223 documentation. In particular, all the structure/union and
5224 high-level macro operands are missing.
5225
5226 Uppercase words are terminals, lower case words are non-terminals.
5227 Objects surrounded by double brackets '[[' ']]' are optional. Vertical
5228 bars '|' denote choices. Most grammar productions are implemented in
5229 functions called 'intel_<production>'.
5230
5231 Initial production is 'expr'.
5232
64a0c779
DN		 5233 addOp + | -
5234
5235 alpha [a-zA-Z]
5236
5237 byteRegister AL | AH | BL | BH | CL | CH | DL | DH
5238
5239 constant digits [[ radixOverride ]]
5240
5241 dataType BYTE | WORD | DWORD | QWORD | XWORD
5242
5243 digits decdigit
b77a7acd
AJ		 5244 | digits decdigit
5245 | digits hexdigit
64a0c779
DN		 5246
5247 decdigit [0-9]
5248
5249 e05 e05 addOp e06
b77a7acd 5250 | e06
64a0c779
DN		 5251
5252 e06 e06 mulOp e09
b77a7acd 5253 | e09
64a0c779
DN		 5254
5255 e09 OFFSET e10
5256 | e09 PTR e10
5257 | e09 : e10
5258 | e10
5259
5260 e10 e10 [ expr ]
b77a7acd 5261 | e11
64a0c779
DN		 5262
5263 e11 ( expr )
b77a7acd 5264 | [ expr ]
64a0c779
DN		 5265 | constant
5266 | dataType
5267 | id
5268 | $
5269 | register
5270
5271 => expr SHORT e05
b77a7acd 5272 | e05
64a0c779
DN		 5273
5274 gpRegister AX | EAX | BX | EBX | CX | ECX | DX | EDX
b77a7acd 5275 | BP | EBP | SP | ESP | DI | EDI | SI | ESI
64a0c779
DN		 5276
5277 hexdigit a | b | c | d | e | f
b77a7acd 5278 | A | B | C | D | E | F
64a0c779
DN		 5279
5280 id alpha
b77a7acd 5281 | id alpha
64a0c779
DN		 5282 | id decdigit
5283
5284 mulOp * | / | MOD
5285
5286 quote " | '
5287
5288 register specialRegister
b77a7acd 5289 | gpRegister
64a0c779
DN		 5290 | byteRegister
5291
5292 segmentRegister CS | DS | ES | FS | GS | SS
5293
5294 specialRegister CR0 | CR2 | CR3
b77a7acd 5295 | DR0 | DR1 | DR2 | DR3 | DR6 | DR7
64a0c779
DN		 5296 | TR3 | TR4 | TR5 | TR6 | TR7
5297
64a0c779
DN		 5298 We simplify the grammar in obvious places (e.g., register parsing is
5299 done by calling parse_register) and eliminate immediate left recursion
5300 to implement a recursive-descent parser.
5301
5302 expr SHORT e05
b77a7acd 5303 | e05
64a0c779
DN		 5304
5305 e05 e06 e05'
5306
5307 e05' addOp e06 e05'
b77a7acd 5308 | Empty
64a0c779
DN		 5309
5310 e06 e09 e06'
5311
5312 e06' mulOp e09 e06'
b77a7acd 5313 | Empty
64a0c779
DN		 5314
5315 e09 OFFSET e10 e09'
b77a7acd 5316 | e10 e09'
64a0c779
DN		 5317
5318 e09' PTR e10 e09'
b77a7acd 5319 | : e10 e09'
64a0c779
DN		 5320 | Empty
5321
5322 e10 e11 e10'
5323
5324 e10' [ expr ] e10'
b77a7acd 5325 | Empty
64a0c779
DN		 5326
5327 e11 ( expr )
b77a7acd 5328 | [ expr ]
64a0c779
DN		 5329 | BYTE
5330 | WORD
5331 | DWORD
5332 | QWORD
5333 | XWORD
5334 | .
5335 | $
5336 | register
5337 | id
5338 | constant */
5339
5340/* Parsing structure for the intel syntax parser. Used to implement the
5341 semantic actions for the operand grammar. */
5342struct intel_parser_s
5343 {
5344 char *op_string; /* The string being parsed. */
5345 int got_a_float; /* Whether the operand is a float. */
4a1805b1 5346 int op_modifier; /* Operand modifier. */
64a0c779
DN		 5347 int is_mem; /* 1 if operand is memory reference. */
5348 const reg_entry *reg; /* Last register reference found. */
5349 char *disp; /* Displacement string being built. */
5350 };
5351
5352static struct intel_parser_s intel_parser;
5353
5354/* Token structure for parsing intel syntax. */
5355struct intel_token
5356 {
5357 int code; /* Token code. */
5358 const reg_entry *reg; /* Register entry for register tokens. */
5359 char *str; /* String representation. */
5360 };
5361
5362static struct intel_token cur_token, prev_token;
5363
50705ef4
AM		 5364/* Token codes for the intel parser. Since T_SHORT is already used
5365 by COFF, undefine it first to prevent a warning. */
64a0c779
DN		 5366#define T_NIL -1
5367#define T_CONST 1
5368#define T_REG 2
5369#define T_BYTE 3
5370#define T_WORD 4
5371#define T_DWORD 5
5372#define T_QWORD 6
5373#define T_XWORD 7
50705ef4 5374#undef T_SHORT
64a0c779
DN		 5375#define T_SHORT 8
5376#define T_OFFSET 9
5377#define T_PTR 10
5378#define T_ID 11
5379
5380/* Prototypes for intel parser functions. */
5381static int intel_match_token PARAMS ((int code));
cce0cbdc
DN		 5382static void intel_get_token PARAMS ((void));
5383static void intel_putback_token PARAMS ((void));
5384static int intel_expr PARAMS ((void));
5385static int intel_e05 PARAMS ((void));
5386static int intel_e05_1 PARAMS ((void));
5387static int intel_e06 PARAMS ((void));
5388static int intel_e06_1 PARAMS ((void));
5389static int intel_e09 PARAMS ((void));
5390static int intel_e09_1 PARAMS ((void));
5391static int intel_e10 PARAMS ((void));
5392static int intel_e10_1 PARAMS ((void));
5393static int intel_e11 PARAMS ((void));
64a0c779 5394
64a0c779
DN		 5395static int
5396i386_intel_operand (operand_string, got_a_float)
5397 char *operand_string;
5398 int got_a_float;
5399{
5400 int ret;
5401 char *p;
5402
5403 /* Initialize token holders. */
5404 cur_token.code = prev_token.code = T_NIL;
5405 cur_token.reg = prev_token.reg = NULL;
5406 cur_token.str = prev_token.str = NULL;
5407
5408 /* Initialize parser structure. */
e5cb08ac 5409 p = intel_parser.op_string = (char *) malloc (strlen (operand_string) + 1);
64a0c779
DN		 5410 if (p == NULL)
5411 abort ();
5412 strcpy (intel_parser.op_string, operand_string);
5413 intel_parser.got_a_float = got_a_float;
5414 intel_parser.op_modifier = -1;
5415 intel_parser.is_mem = 0;
5416 intel_parser.reg = NULL;
e5cb08ac 5417 intel_parser.disp = (char *) malloc (strlen (operand_string) + 1);
64a0c779
DN		 5418 if (intel_parser.disp == NULL)
5419 abort ();
5420 intel_parser.disp[0] = '\0';
5421
5422 /* Read the first token and start the parser. */
5423 intel_get_token ();
5424 ret = intel_expr ();
5425
5426 if (ret)
5427 {
5428 /* If we found a memory reference, hand it over to i386_displacement
5429 to fill in the rest of the operand fields. */
5430 if (intel_parser.is_mem)
5431 {
5432 if ((i.mem_operands == 1
5433 && (current_templates->start->opcode_modifier & IsString) == 0)
5434 || i.mem_operands == 2)
5435 {
5436 as_bad (_("too many memory references for '%s'"),
5437 current_templates->start->name);
5438 ret = 0;
5439 }
5440 else
5441 {
5442 char *s = intel_parser.disp;
5443 i.mem_operands++;
5444
5445 /* Add the displacement expression. */
5446 if (*s != '\0')
5447 ret = i386_displacement (s, s + strlen (s))
5448 && i386_index_check (s);
5449 }
5450 }
5451
5452 /* Constant and OFFSET expressions are handled by i386_immediate. */
5453 else if (intel_parser.op_modifier == OFFSET_FLAT
5454 || intel_parser.reg == NULL)
5455 ret = i386_immediate (intel_parser.disp);
5456 }
5457
5458 free (p);
5459 free (intel_parser.disp);
5460
5461 return ret;
5462}
5463
64a0c779 5464/* expr SHORT e05
b77a7acd 5465 | e05 */
64a0c779
DN		 5466static int
5467intel_expr ()
5468{
5469 /* expr SHORT e05 */
5470 if (cur_token.code == T_SHORT)
5471 {
5472 intel_parser.op_modifier = SHORT;
5473 intel_match_token (T_SHORT);
5474
5475 return (intel_e05 ());
5476 }
5477
5478 /* expr e05 */
5479 else
5480 return intel_e05 ();
5481}
5482
64a0c779
DN		 5483/* e05 e06 e05'
5484
4a1805b1 5485 e05' addOp e06 e05'
64a0c779
DN		 5486 | Empty */
5487static int
5488intel_e05 ()
5489{
5490 return (intel_e06 () && intel_e05_1 ());
5491}
5492
5493static int
5494intel_e05_1 ()
5495{
5496 /* e05' addOp e06 e05' */
5497 if (cur_token.code == '+' || cur_token.code == '-')
5498 {
5499 strcat (intel_parser.disp, cur_token.str);
5500 intel_match_token (cur_token.code);
5501
5502 return (intel_e06 () && intel_e05_1 ());
5503 }
5504
5505 /* e05' Empty */
5506 else
5507 return 1;
4a1805b1 5508}
64a0c779
DN		 5509
5510/* e06 e09 e06'
5511
5512 e06' mulOp e09 e06'
b77a7acd 5513 | Empty */
64a0c779
DN		 5514static int
5515intel_e06 ()
5516{
5517 return (intel_e09 () && intel_e06_1 ());
5518}
5519
5520static int
5521intel_e06_1 ()
5522{
5523 /* e06' mulOp e09 e06' */
5524 if (cur_token.code == '*' || cur_token.code == '/')
5525 {
5526 strcat (intel_parser.disp, cur_token.str);
5527 intel_match_token (cur_token.code);
5528
5529 return (intel_e09 () && intel_e06_1 ());
5530 }
4a1805b1 5531
64a0c779 5532 /* e06' Empty */
4a1805b1 5533 else
64a0c779
DN		 5534 return 1;
5535}
5536
64a0c779 5537/* e09 OFFSET e10 e09'
b77a7acd 5538 | e10 e09'
64a0c779
DN		 5539
5540 e09' PTR e10 e09'
b77a7acd 5541 | : e10 e09'
64a0c779
DN		 5542 | Empty */
5543static int
5544intel_e09 ()
5545{
5546 /* e09 OFFSET e10 e09' */
5547 if (cur_token.code == T_OFFSET)
5548 {
5549 intel_parser.is_mem = 0;
5550 intel_parser.op_modifier = OFFSET_FLAT;
5551 intel_match_token (T_OFFSET);
5552
5553 return (intel_e10 () && intel_e09_1 ());
5554 }
5555
5556 /* e09 e10 e09' */
5557 else
5558 return (intel_e10 () && intel_e09_1 ());
5559}
5560
5561static int
5562intel_e09_1 ()
5563{
5564 /* e09' PTR e10 e09' */
5565 if (cur_token.code == T_PTR)
5566 {
5567 if (prev_token.code == T_BYTE)
5568 i.suffix = BYTE_MNEM_SUFFIX;
5569
5570 else if (prev_token.code == T_WORD)
5571 {
5572 if (intel_parser.got_a_float == 2) /* "fi..." */
5573 i.suffix = SHORT_MNEM_SUFFIX;
5574 else
5575 i.suffix = WORD_MNEM_SUFFIX;
5576 }
5577
5578 else if (prev_token.code == T_DWORD)
5579 {
5580 if (intel_parser.got_a_float == 1) /* "f..." */
5581 i.suffix = SHORT_MNEM_SUFFIX;
5582 else
5583 i.suffix = LONG_MNEM_SUFFIX;
5584 }
5585
5586 else if (prev_token.code == T_QWORD)
f16b83df
JH		 5587 {
5588 if (intel_parser.got_a_float == 1) /* "f..." */
5589 i.suffix = LONG_MNEM_SUFFIX;
5590 else
3e73aa7c 5591 i.suffix = QWORD_MNEM_SUFFIX;
f16b83df 5592 }
64a0c779
DN		 5593
5594 else if (prev_token.code == T_XWORD)
5595 i.suffix = LONG_DOUBLE_MNEM_SUFFIX;
5596
5597 else
5598 {
5599 as_bad (_("Unknown operand modifier `%s'\n"), prev_token.str);
5600 return 0;
5601 }
5602
5603 intel_match_token (T_PTR);
5604
5605 return (intel_e10 () && intel_e09_1 ());
5606 }
5607
5608 /* e09 : e10 e09' */
5609 else if (cur_token.code == ':')
5610 {
21d6c4af
DN		 5611 /* Mark as a memory operand only if it's not already known to be an
5612 offset expression. */
5613 if (intel_parser.op_modifier != OFFSET_FLAT)
5614 intel_parser.is_mem = 1;
64a0c779
DN		 5615
5616 return (intel_match_token (':') && intel_e10 () && intel_e09_1 ());
5617 }
5618
5619 /* e09' Empty */
5620 else
5621 return 1;
5622}
5623
5624/* e10 e11 e10'
5625
5626 e10' [ expr ] e10'
b77a7acd 5627 | Empty */
64a0c779
DN		 5628static int
5629intel_e10 ()
5630{
5631 return (intel_e11 () && intel_e10_1 ());
5632}
5633
5634static int
5635intel_e10_1 ()
5636{
5637 /* e10' [ expr ] e10' */
5638 if (cur_token.code == '[')
5639 {
5640 intel_match_token ('[');
21d6c4af
DN		 5641
5642 /* Mark as a memory operand only if it's not already known to be an
5643 offset expression. If it's an offset expression, we need to keep
5644 the brace in. */
5645 if (intel_parser.op_modifier != OFFSET_FLAT)
5646 intel_parser.is_mem = 1;
5647 else
5648 strcat (intel_parser.disp, "[");
4a1805b1 5649
64a0c779 5650 /* Add a '+' to the displacement string if necessary. */
21d6c4af
DN		 5651 if (*intel_parser.disp != '\0'
5652 && *(intel_parser.disp + strlen (intel_parser.disp) - 1) != '+')
64a0c779
DN		 5653 strcat (intel_parser.disp, "+");
5654
21d6c4af
DN		 5655 if (intel_expr () && intel_match_token (']'))
5656 {
5657 /* Preserve brackets when the operand is an offset expression. */
5658 if (intel_parser.op_modifier == OFFSET_FLAT)
5659 strcat (intel_parser.disp, "]");
5660
5661 return intel_e10_1 ();
5662 }
5663 else
5664 return 0;
64a0c779
DN		 5665 }
5666
5667 /* e10' Empty */
5668 else
5669 return 1;
5670}
5671
64a0c779 5672/* e11 ( expr )
b77a7acd 5673 | [ expr ]
64a0c779
DN		 5674 | BYTE
5675 | WORD
5676 | DWORD
5677 | QWORD
5678 | XWORD
4a1805b1 5679 | $
64a0c779
DN		 5680 | .
5681 | register
5682 | id
5683 | constant */
5684static int
5685intel_e11 ()
5686{
5687 /* e11 ( expr ) */
5688 if (cur_token.code == '(')
5689 {
5690 intel_match_token ('(');
5691 strcat (intel_parser.disp, "(");
5692
5693 if (intel_expr () && intel_match_token (')'))
e5cb08ac
KH		 5694 {
5695 strcat (intel_parser.disp, ")");
5696 return 1;
5697 }
64a0c779
DN		 5698 else
5699 return 0;
5700 }
5701
5702 /* e11 [ expr ] */
5703 else if (cur_token.code == '[')
5704 {
5705 intel_match_token ('[');
21d6c4af
DN		 5706
5707 /* Mark as a memory operand only if it's not already known to be an
5708 offset expression. If it's an offset expression, we need to keep
5709 the brace in. */
5710 if (intel_parser.op_modifier != OFFSET_FLAT)
5711 intel_parser.is_mem = 1;
5712 else
5713 strcat (intel_parser.disp, "[");
4a1805b1 5714
64a0c779
DN		 5715 /* Operands for jump/call inside brackets denote absolute addresses. */
5716 if (current_templates->start->opcode_modifier & Jump
5717 || current_templates->start->opcode_modifier & JumpDword
5718 || current_templates->start->opcode_modifier & JumpByte
5719 || current_templates->start->opcode_modifier & JumpInterSegment)
5720 i.types[this_operand] |= JumpAbsolute;
5721
5722 /* Add a '+' to the displacement string if necessary. */
21d6c4af
DN		 5723 if (*intel_parser.disp != '\0'
5724 && *(intel_parser.disp + strlen (intel_parser.disp) - 1) != '+')
64a0c779
DN		 5725 strcat (intel_parser.disp, "+");
5726
21d6c4af
DN		 5727 if (intel_expr () && intel_match_token (']'))
5728 {
5729 /* Preserve brackets when the operand is an offset expression. */
5730 if (intel_parser.op_modifier == OFFSET_FLAT)
5731 strcat (intel_parser.disp, "]");
5732
5733 return 1;
5734 }
5735 else
5736 return 0;
64a0c779
DN		 5737 }
5738
4a1805b1 5739 /* e11 BYTE
64a0c779
DN		 5740 | WORD
5741 | DWORD
5742 | QWORD
5743 | XWORD */
5744 else if (cur_token.code == T_BYTE
5745 || cur_token.code == T_WORD
5746 || cur_token.code == T_DWORD
5747 || cur_token.code == T_QWORD
5748 || cur_token.code == T_XWORD)
5749 {
5750 intel_match_token (cur_token.code);
5751
5752 return 1;
5753 }
5754
5755 /* e11 $
5756 | . */
5757 else if (cur_token.code == '$' || cur_token.code == '.')
5758 {
5759 strcat (intel_parser.disp, cur_token.str);
5760 intel_match_token (cur_token.code);
21d6c4af
DN		 5761
5762 /* Mark as a memory operand only if it's not already known to be an
5763 offset expression. */
5764 if (intel_parser.op_modifier != OFFSET_FLAT)
5765 intel_parser.is_mem = 1;
64a0c779
DN		 5766
5767 return 1;
5768 }
5769
5770 /* e11 register */
5771 else if (cur_token.code == T_REG)
5772 {
5773 const reg_entry *reg = intel_parser.reg = cur_token.reg;
5774
5775 intel_match_token (T_REG);
5776
5777 /* Check for segment change. */
5778 if (cur_token.code == ':')
5779 {
5780 if (reg->reg_type & (SReg2 | SReg3))
5781 {
5782 switch (reg->reg_num)
5783 {
5784 case 0:
5785 i.seg[i.mem_operands] = &es;
5786 break;
5787 case 1:
5788 i.seg[i.mem_operands] = &cs;
5789 break;
5790 case 2:
5791 i.seg[i.mem_operands] = &ss;
5792 break;
5793 case 3:
5794 i.seg[i.mem_operands] = &ds;
5795 break;
5796 case 4:
5797 i.seg[i.mem_operands] = &fs;
5798 break;
5799 case 5:
5800 i.seg[i.mem_operands] = &gs;
5801 break;
5802 }
5803 }
5804 else
5805 {
5806 as_bad (_("`%s' is not a valid segment register"), reg->reg_name);
5807 return 0;
5808 }
5809 }
5810
5811 /* Not a segment register. Check for register scaling. */
5812 else if (cur_token.code == '*')
5813 {
5814 if (!intel_parser.is_mem)
5815 {
5816 as_bad (_("Register scaling only allowed in memory operands."));
5817 return 0;
5818 }
5819
4a1805b1 5820 /* What follows must be a valid scale. */
64a0c779
DN		 5821 if (intel_match_token ('*')
5822 && strchr ("01248", *cur_token.str))
5823 {
5824 i.index_reg = reg;
5825 i.types[this_operand] |= BaseIndex;
5826
5827 /* Set the scale after setting the register (otherwise,
5828 i386_scale will complain) */
5829 i386_scale (cur_token.str);
5830 intel_match_token (T_CONST);
5831 }
5832 else
5833 {
5834 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
5835 cur_token.str);
5836 return 0;
5837 }
5838 }
5839
5840 /* No scaling. If this is a memory operand, the register is either a
5841 base register (first occurrence) or an index register (second
5842 occurrence). */
5843 else if (intel_parser.is_mem && !(reg->reg_type & (SReg2 | SReg3)))
5844 {
5845 if (i.base_reg && i.index_reg)
5846 {
5847 as_bad (_("Too many register references in memory operand.\n"));
5848 return 0;
5849 }
5850
5851 if (i.base_reg == NULL)
5852 i.base_reg = reg;
5853 else
5854 i.index_reg = reg;
5855
5856 i.types[this_operand] |= BaseIndex;
5857 }
5858
5859 /* Offset modifier. Add the register to the displacement string to be
5860 parsed as an immediate expression after we're done. */
5861 else if (intel_parser.op_modifier == OFFSET_FLAT)
5862 strcat (intel_parser.disp, reg->reg_name);
4a1805b1 5863
64a0c779
DN		 5864 /* It's neither base nor index nor offset. */
5865 else
5866 {
5867 i.types[this_operand] |= reg->reg_type & ~BaseIndex;
5868 i.op[this_operand].regs = reg;
5869 i.reg_operands++;
5870 }
5871
5872 /* Since registers are not part of the displacement string (except
5873 when we're parsing offset operands), we may need to remove any
5874 preceding '+' from the displacement string. */
5875 if (*intel_parser.disp != '\0'
5876 && intel_parser.op_modifier != OFFSET_FLAT)
5877 {
5878 char *s = intel_parser.disp;
5879 s += strlen (s) - 1;
5880 if (*s == '+')
5881 *s = '\0';
5882 }
5883
5884 return 1;
5885 }
4a1805b1 5886
64a0c779
DN		 5887 /* e11 id */
5888 else if (cur_token.code == T_ID)
5889 {
5890 /* Add the identifier to the displacement string. */
5891 strcat (intel_parser.disp, cur_token.str);
5892 intel_match_token (T_ID);
5893
5894 /* The identifier represents a memory reference only if it's not
5895 preceded by an offset modifier. */
21d6c4af 5896 if (intel_parser.op_modifier != OFFSET_FLAT)
64a0c779
DN		 5897 intel_parser.is_mem = 1;
5898
5899 return 1;
5900 }
5901
5902 /* e11 constant */
5903 else if (cur_token.code == T_CONST
e5cb08ac 5904 || cur_token.code == '-'
64a0c779
DN		 5905 || cur_token.code == '+')
5906 {
5907 char *save_str;
5908
5909 /* Allow constants that start with `+' or `-'. */
5910 if (cur_token.code == '-' || cur_token.code == '+')
5911 {
5912 strcat (intel_parser.disp, cur_token.str);
5913 intel_match_token (cur_token.code);
5914 if (cur_token.code != T_CONST)
5915 {
5916 as_bad (_("Syntax error. Expecting a constant. Got `%s'.\n"),
5917 cur_token.str);
5918 return 0;
5919 }
5920 }
5921
e5cb08ac 5922 save_str = (char *) malloc (strlen (cur_token.str) + 1);
64a0c779 5923 if (save_str == NULL)
bc805888 5924 abort ();
64a0c779
DN		 5925 strcpy (save_str, cur_token.str);
5926
5927 /* Get the next token to check for register scaling. */
5928 intel_match_token (cur_token.code);
5929
5930 /* Check if this constant is a scaling factor for an index register. */
5931 if (cur_token.code == '*')
5932 {
5933 if (intel_match_token ('*') && cur_token.code == T_REG)
5934 {
5935 if (!intel_parser.is_mem)
5936 {
5937 as_bad (_("Register scaling only allowed in memory operands."));
5938 return 0;
5939 }
5940
4a1805b1 5941 /* The constant is followed by `* reg', so it must be
64a0c779
DN		 5942 a valid scale. */
5943 if (strchr ("01248", *save_str))
5944 {
5945 i.index_reg = cur_token.reg;
5946 i.types[this_operand] |= BaseIndex;
5947
5948 /* Set the scale after setting the register (otherwise,
5949 i386_scale will complain) */
5950 i386_scale (save_str);
5951 intel_match_token (T_REG);
5952
5953 /* Since registers are not part of the displacement
5954 string, we may need to remove any preceding '+' from
5955 the displacement string. */
5956 if (*intel_parser.disp != '\0')
5957 {
5958 char *s = intel_parser.disp;
5959 s += strlen (s) - 1;
5960 if (*s == '+')
5961 *s = '\0';
5962 }
5963
5964 free (save_str);
5965
5966 return 1;
5967 }
5968 else
5969 return 0;
5970 }
5971
5972 /* The constant was not used for register scaling. Since we have
5973 already consumed the token following `*' we now need to put it
5974 back in the stream. */
5975 else
5976 intel_putback_token ();
5977 }
5978
5979 /* Add the constant to the displacement string. */
5980 strcat (intel_parser.disp, save_str);
5981 free (save_str);
5982
5983 return 1;
5984 }
5985
64a0c779
DN		 5986 as_bad (_("Unrecognized token '%s'"), cur_token.str);
5987 return 0;
5988}
5989
64a0c779
DN		 5990/* Match the given token against cur_token. If they match, read the next
5991 token from the operand string. */
5992static int
5993intel_match_token (code)
e5cb08ac 5994 int code;
64a0c779
DN		 5995{
5996 if (cur_token.code == code)
5997 {
5998 intel_get_token ();
5999 return 1;
6000 }
6001 else
6002 {
6003 as_bad (_("Unexpected token `%s'\n"), cur_token.str);
6004 return 0;
6005 }
6006}
6007
64a0c779
DN		 6008/* Read a new token from intel_parser.op_string and store it in cur_token. */
6009static void
6010intel_get_token ()
6011{
6012 char *end_op;
6013 const reg_entry *reg;
6014 struct intel_token new_token;
6015
6016 new_token.code = T_NIL;
6017 new_token.reg = NULL;
6018 new_token.str = NULL;
6019
4a1805b1 6020 /* Free the memory allocated to the previous token and move
64a0c779
DN		 6021 cur_token to prev_token. */
6022 if (prev_token.str)
6023 free (prev_token.str);
6024
6025 prev_token = cur_token;
6026
6027 /* Skip whitespace. */
6028 while (is_space_char (*intel_parser.op_string))
6029 intel_parser.op_string++;
6030
6031 /* Return an empty token if we find nothing else on the line. */
6032 if (*intel_parser.op_string == '\0')
6033 {
6034 cur_token = new_token;
6035 return;
6036 }
6037
6038 /* The new token cannot be larger than the remainder of the operand
6039 string. */
e5cb08ac 6040 new_token.str = (char *) malloc (strlen (intel_parser.op_string) + 1);
64a0c779 6041 if (new_token.str == NULL)
bc805888 6042 abort ();
64a0c779
DN		 6043 new_token.str[0] = '\0';
6044
6045 if (strchr ("0123456789", *intel_parser.op_string))
6046 {
6047 char *p = new_token.str;
6048 char *q = intel_parser.op_string;
6049 new_token.code = T_CONST;
6050
6051 /* Allow any kind of identifier char to encompass floating point and
6052 hexadecimal numbers. */
6053 while (is_identifier_char (*q))
6054 *p++ = *q++;
6055 *p = '\0';
6056
6057 /* Recognize special symbol names [0-9][bf]. */
6058 if (strlen (intel_parser.op_string) == 2
4a1805b1 6059 && (intel_parser.op_string[1] == 'b'
64a0c779
DN		 6060 || intel_parser.op_string[1] == 'f'))
6061 new_token.code = T_ID;
6062 }
6063
6064 else if (strchr ("+-/*:[]()", *intel_parser.op_string))
6065 {
6066 new_token.code = *intel_parser.op_string;
6067 new_token.str[0] = *intel_parser.op_string;
6068 new_token.str[1] = '\0';
6069 }
6070
6071 else if ((*intel_parser.op_string == REGISTER_PREFIX || allow_naked_reg)
6072 && ((reg = parse_register (intel_parser.op_string, &end_op)) != NULL))
6073 {
6074 new_token.code = T_REG;
6075 new_token.reg = reg;
6076
6077 if (*intel_parser.op_string == REGISTER_PREFIX)
6078 {
6079 new_token.str[0] = REGISTER_PREFIX;
6080 new_token.str[1] = '\0';
6081 }
6082
6083 strcat (new_token.str, reg->reg_name);
6084 }
6085
6086 else if (is_identifier_char (*intel_parser.op_string))
6087 {
6088 char *p = new_token.str;
6089 char *q = intel_parser.op_string;
6090
6091 /* A '.' or '$' followed by an identifier char is an identifier.
6092 Otherwise, it's operator '.' followed by an expression. */
6093 if ((*q == '.' || *q == '$') && !is_identifier_char (*(q + 1)))
6094 {
6095 new_token.code = *q;
6096 new_token.str[0] = *q;
6097 new_token.str[1] = '\0';
6098 }
6099 else
6100 {
6101 while (is_identifier_char (*q) || *q == '@')
6102 *p++ = *q++;
6103 *p = '\0';
6104
6105 if (strcasecmp (new_token.str, "BYTE") == 0)
6106 new_token.code = T_BYTE;
6107
6108 else if (strcasecmp (new_token.str, "WORD") == 0)
6109 new_token.code = T_WORD;
6110
6111 else if (strcasecmp (new_token.str, "DWORD") == 0)
6112 new_token.code = T_DWORD;
6113
6114 else if (strcasecmp (new_token.str, "QWORD") == 0)
6115 new_token.code = T_QWORD;
6116
6117 else if (strcasecmp (new_token.str, "XWORD") == 0)
6118 new_token.code = T_XWORD;
6119
6120 else if (strcasecmp (new_token.str, "PTR") == 0)
6121 new_token.code = T_PTR;
6122
6123 else if (strcasecmp (new_token.str, "SHORT") == 0)
6124 new_token.code = T_SHORT;
6125
6126 else if (strcasecmp (new_token.str, "OFFSET") == 0)
6127 {
6128 new_token.code = T_OFFSET;
6129
6130 /* ??? This is not mentioned in the MASM grammar but gcc
6131 makes use of it with -mintel-syntax. OFFSET may be
6132 followed by FLAT: */
6133 if (strncasecmp (q, " FLAT:", 6) == 0)
6134 strcat (new_token.str, " FLAT:");
6135 }
6136
6137 /* ??? This is not mentioned in the MASM grammar. */
6138 else if (strcasecmp (new_token.str, "FLAT") == 0)
6139 new_token.code = T_OFFSET;
6140
6141 else
6142 new_token.code = T_ID;
6143 }
6144 }
6145
6146 else
6147 as_bad (_("Unrecognized token `%s'\n"), intel_parser.op_string);
6148
6149 intel_parser.op_string += strlen (new_token.str);
6150 cur_token = new_token;
6151}
6152
64a0c779
DN		 6153/* Put cur_token back into the token stream and make cur_token point to
6154 prev_token. */
6155static void
6156intel_putback_token ()
6157{
6158 intel_parser.op_string -= strlen (cur_token.str);
6159 free (cur_token.str);
6160 cur_token = prev_token;
4a1805b1 6161
64a0c779
DN		 6162 /* Forget prev_token. */
6163 prev_token.code = T_NIL;
6164 prev_token.reg = NULL;
6165 prev_token.str = NULL;
6166}
GDB Binutils - Deliverables
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