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dbbb1059 AB |
1 | /* Target-dependent code for the RISC-V architecture, for GDB. |
2 | ||
b811d2c2 | 3 | Copyright (C) 2018-2020 Free Software Foundation, Inc. |
dbbb1059 | 4 | |
dbbb1059 AB |
5 | This file is part of GDB. |
6 | ||
7 | This program is free software; you can redistribute it and/or modify | |
8 | it under the terms of the GNU General Public License as published by | |
9 | the Free Software Foundation; either version 3 of the License, or | |
10 | (at your option) any later version. | |
11 | ||
12 | This program is distributed in the hope that it will be useful, | |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | GNU General Public License for more details. | |
16 | ||
17 | You should have received a copy of the GNU General Public License | |
18 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ | |
19 | ||
20 | #include "defs.h" | |
21 | #include "frame.h" | |
22 | #include "inferior.h" | |
23 | #include "symtab.h" | |
24 | #include "value.h" | |
25 | #include "gdbcmd.h" | |
26 | #include "language.h" | |
27 | #include "gdbcore.h" | |
28 | #include "symfile.h" | |
29 | #include "objfiles.h" | |
30 | #include "gdbtypes.h" | |
31 | #include "target.h" | |
32 | #include "arch-utils.h" | |
33 | #include "regcache.h" | |
34 | #include "osabi.h" | |
35 | #include "riscv-tdep.h" | |
36 | #include "block.h" | |
37 | #include "reggroups.h" | |
38 | #include "opcode/riscv.h" | |
39 | #include "elf/riscv.h" | |
40 | #include "elf-bfd.h" | |
41 | #include "symcat.h" | |
42 | #include "dis-asm.h" | |
43 | #include "frame-unwind.h" | |
44 | #include "frame-base.h" | |
45 | #include "trad-frame.h" | |
46 | #include "infcall.h" | |
47 | #include "floatformat.h" | |
48 | #include "remote.h" | |
49 | #include "target-descriptions.h" | |
82ca8957 | 50 | #include "dwarf2/frame.h" |
dbbb1059 AB |
51 | #include "user-regs.h" |
52 | #include "valprint.h" | |
268a13a5 | 53 | #include "gdbsupport/common-defs.h" |
dbbb1059 AB |
54 | #include "opcode/riscv-opc.h" |
55 | #include "cli/cli-decode.h" | |
76727919 | 56 | #include "observable.h" |
78a3b0fa | 57 | #include "prologue-value.h" |
b5ffee31 | 58 | #include "arch/riscv.h" |
db3ad2f0 | 59 | #include "riscv-ravenscar-thread.h" |
dbbb1059 AB |
60 | |
61 | /* The stack must be 16-byte aligned. */ | |
62 | #define SP_ALIGNMENT 16 | |
63 | ||
ef2de9e7 JW |
64 | /* The biggest alignment that the target supports. */ |
65 | #define BIGGEST_ALIGNMENT 16 | |
66 | ||
dbbb1059 AB |
67 | /* Define a series of is_XXX_insn functions to check if the value INSN |
68 | is an instance of instruction XXX. */ | |
69 | #define DECLARE_INSN(INSN_NAME, INSN_MATCH, INSN_MASK) \ | |
70 | static inline bool is_ ## INSN_NAME ## _insn (long insn) \ | |
71 | { \ | |
72 | return (insn & INSN_MASK) == INSN_MATCH; \ | |
73 | } | |
74 | #include "opcode/riscv-opc.h" | |
75 | #undef DECLARE_INSN | |
76 | ||
78a3b0fa AB |
77 | /* Cached information about a frame. */ |
78 | ||
79 | struct riscv_unwind_cache | |
80 | { | |
81 | /* The register from which we can calculate the frame base. This is | |
82 | usually $sp or $fp. */ | |
83 | int frame_base_reg; | |
84 | ||
85 | /* The offset from the current value in register FRAME_BASE_REG to the | |
86 | actual frame base address. */ | |
87 | int frame_base_offset; | |
88 | ||
89 | /* Information about previous register values. */ | |
90 | struct trad_frame_saved_reg *regs; | |
91 | ||
92 | /* The id for this frame. */ | |
93 | struct frame_id this_id; | |
94 | ||
95 | /* The base (stack) address for this frame. This is the stack pointer | |
96 | value on entry to this frame before any adjustments are made. */ | |
97 | CORE_ADDR frame_base; | |
98 | }; | |
99 | ||
b5ffee31 | 100 | /* RISC-V specific register group for CSRs. */ |
dbbb1059 | 101 | |
b5ffee31 | 102 | static reggroup *csr_reggroup = NULL; |
dbbb1059 | 103 | |
b5ffee31 AB |
104 | /* A set of registers that we expect to find in a tdesc_feature. These |
105 | are use in RISCV_GDBARCH_INIT when processing the target description. */ | |
dbbb1059 | 106 | |
b5ffee31 | 107 | struct riscv_register_feature |
dbbb1059 | 108 | { |
b5ffee31 AB |
109 | /* Information for a single register. */ |
110 | struct register_info | |
111 | { | |
112 | /* The GDB register number for this register. */ | |
113 | int regnum; | |
114 | ||
115 | /* List of names for this register. The first name in this list is the | |
116 | preferred name, the name GDB should use when describing this | |
117 | register. */ | |
4445e8f5 | 118 | std::vector<const char *> names; |
b5ffee31 AB |
119 | |
120 | /* When true this register is required in this feature set. */ | |
121 | bool required_p; | |
122 | }; | |
123 | ||
124 | /* The name for this feature. This is the name used to find this feature | |
125 | within the target description. */ | |
dbbb1059 AB |
126 | const char *name; |
127 | ||
ed69cbc8 AB |
128 | /* For x-regs and f-regs we always force GDB to use the first name from |
129 | the REGISTERS.NAMES vector, it is therefore important that we create | |
130 | user-register aliases for all of the remaining names at indexes 1+ in | |
131 | the names vector. | |
132 | ||
133 | For CSRs we take a different approach, we prefer whatever name the | |
134 | target description uses, in this case we want to create user-register | |
135 | aliases for any other names that aren't the target description | |
136 | provided name. | |
137 | ||
138 | When this flag is true we are dealing with the first case, and when | |
139 | this is false we are dealing with the latter. */ | |
140 | bool prefer_first_name; | |
141 | ||
b5ffee31 AB |
142 | /* List of all the registers that we expect that we might find in this |
143 | register set. */ | |
4445e8f5 | 144 | std::vector<struct register_info> registers; |
b5ffee31 AB |
145 | }; |
146 | ||
147 | /* The general x-registers feature set. */ | |
148 | ||
149 | static const struct riscv_register_feature riscv_xreg_feature = | |
150 | { | |
ed69cbc8 | 151 | "org.gnu.gdb.riscv.cpu", true, |
b5ffee31 AB |
152 | { |
153 | { RISCV_ZERO_REGNUM + 0, { "zero", "x0" }, true }, | |
154 | { RISCV_ZERO_REGNUM + 1, { "ra", "x1" }, true }, | |
155 | { RISCV_ZERO_REGNUM + 2, { "sp", "x2" }, true }, | |
156 | { RISCV_ZERO_REGNUM + 3, { "gp", "x3" }, true }, | |
157 | { RISCV_ZERO_REGNUM + 4, { "tp", "x4" }, true }, | |
158 | { RISCV_ZERO_REGNUM + 5, { "t0", "x5" }, true }, | |
159 | { RISCV_ZERO_REGNUM + 6, { "t1", "x6" }, true }, | |
160 | { RISCV_ZERO_REGNUM + 7, { "t2", "x7" }, true }, | |
161 | { RISCV_ZERO_REGNUM + 8, { "fp", "x8", "s0" }, true }, | |
162 | { RISCV_ZERO_REGNUM + 9, { "s1", "x9" }, true }, | |
163 | { RISCV_ZERO_REGNUM + 10, { "a0", "x10" }, true }, | |
164 | { RISCV_ZERO_REGNUM + 11, { "a1", "x11" }, true }, | |
165 | { RISCV_ZERO_REGNUM + 12, { "a2", "x12" }, true }, | |
166 | { RISCV_ZERO_REGNUM + 13, { "a3", "x13" }, true }, | |
167 | { RISCV_ZERO_REGNUM + 14, { "a4", "x14" }, true }, | |
168 | { RISCV_ZERO_REGNUM + 15, { "a5", "x15" }, true }, | |
169 | { RISCV_ZERO_REGNUM + 16, { "a6", "x16" }, true }, | |
170 | { RISCV_ZERO_REGNUM + 17, { "a7", "x17" }, true }, | |
171 | { RISCV_ZERO_REGNUM + 18, { "s2", "x18" }, true }, | |
172 | { RISCV_ZERO_REGNUM + 19, { "s3", "x19" }, true }, | |
173 | { RISCV_ZERO_REGNUM + 20, { "s4", "x20" }, true }, | |
174 | { RISCV_ZERO_REGNUM + 21, { "s5", "x21" }, true }, | |
175 | { RISCV_ZERO_REGNUM + 22, { "s6", "x22" }, true }, | |
176 | { RISCV_ZERO_REGNUM + 23, { "s7", "x23" }, true }, | |
177 | { RISCV_ZERO_REGNUM + 24, { "s8", "x24" }, true }, | |
178 | { RISCV_ZERO_REGNUM + 25, { "s9", "x25" }, true }, | |
179 | { RISCV_ZERO_REGNUM + 26, { "s10", "x26" }, true }, | |
180 | { RISCV_ZERO_REGNUM + 27, { "s11", "x27" }, true }, | |
181 | { RISCV_ZERO_REGNUM + 28, { "t3", "x28" }, true }, | |
182 | { RISCV_ZERO_REGNUM + 29, { "t4", "x29" }, true }, | |
183 | { RISCV_ZERO_REGNUM + 30, { "t5", "x30" }, true }, | |
184 | { RISCV_ZERO_REGNUM + 31, { "t6", "x31" }, true }, | |
185 | { RISCV_ZERO_REGNUM + 32, { "pc" }, true } | |
186 | } | |
187 | }; | |
188 | ||
189 | /* The f-registers feature set. */ | |
190 | ||
191 | static const struct riscv_register_feature riscv_freg_feature = | |
192 | { | |
ed69cbc8 | 193 | "org.gnu.gdb.riscv.fpu", true, |
b5ffee31 AB |
194 | { |
195 | { RISCV_FIRST_FP_REGNUM + 0, { "ft0", "f0" }, true }, | |
196 | { RISCV_FIRST_FP_REGNUM + 1, { "ft1", "f1" }, true }, | |
197 | { RISCV_FIRST_FP_REGNUM + 2, { "ft2", "f2" }, true }, | |
198 | { RISCV_FIRST_FP_REGNUM + 3, { "ft3", "f3" }, true }, | |
199 | { RISCV_FIRST_FP_REGNUM + 4, { "ft4", "f4" }, true }, | |
200 | { RISCV_FIRST_FP_REGNUM + 5, { "ft5", "f5" }, true }, | |
201 | { RISCV_FIRST_FP_REGNUM + 6, { "ft6", "f6" }, true }, | |
202 | { RISCV_FIRST_FP_REGNUM + 7, { "ft7", "f7" }, true }, | |
592d8c0a | 203 | { RISCV_FIRST_FP_REGNUM + 8, { "fs0", "f8" }, true }, |
b5ffee31 AB |
204 | { RISCV_FIRST_FP_REGNUM + 9, { "fs1", "f9" }, true }, |
205 | { RISCV_FIRST_FP_REGNUM + 10, { "fa0", "f10" }, true }, | |
206 | { RISCV_FIRST_FP_REGNUM + 11, { "fa1", "f11" }, true }, | |
207 | { RISCV_FIRST_FP_REGNUM + 12, { "fa2", "f12" }, true }, | |
208 | { RISCV_FIRST_FP_REGNUM + 13, { "fa3", "f13" }, true }, | |
209 | { RISCV_FIRST_FP_REGNUM + 14, { "fa4", "f14" }, true }, | |
210 | { RISCV_FIRST_FP_REGNUM + 15, { "fa5", "f15" }, true }, | |
211 | { RISCV_FIRST_FP_REGNUM + 16, { "fa6", "f16" }, true }, | |
212 | { RISCV_FIRST_FP_REGNUM + 17, { "fa7", "f17" }, true }, | |
213 | { RISCV_FIRST_FP_REGNUM + 18, { "fs2", "f18" }, true }, | |
214 | { RISCV_FIRST_FP_REGNUM + 19, { "fs3", "f19" }, true }, | |
215 | { RISCV_FIRST_FP_REGNUM + 20, { "fs4", "f20" }, true }, | |
216 | { RISCV_FIRST_FP_REGNUM + 21, { "fs5", "f21" }, true }, | |
217 | { RISCV_FIRST_FP_REGNUM + 22, { "fs6", "f22" }, true }, | |
218 | { RISCV_FIRST_FP_REGNUM + 23, { "fs7", "f23" }, true }, | |
219 | { RISCV_FIRST_FP_REGNUM + 24, { "fs8", "f24" }, true }, | |
220 | { RISCV_FIRST_FP_REGNUM + 25, { "fs9", "f25" }, true }, | |
221 | { RISCV_FIRST_FP_REGNUM + 26, { "fs10", "f26" }, true }, | |
222 | { RISCV_FIRST_FP_REGNUM + 27, { "fs11", "f27" }, true }, | |
223 | { RISCV_FIRST_FP_REGNUM + 28, { "ft8", "f28" }, true }, | |
224 | { RISCV_FIRST_FP_REGNUM + 29, { "ft9", "f29" }, true }, | |
225 | { RISCV_FIRST_FP_REGNUM + 30, { "ft10", "f30" }, true }, | |
226 | { RISCV_FIRST_FP_REGNUM + 31, { "ft11", "f31" }, true }, | |
227 | ||
228 | { RISCV_CSR_FFLAGS_REGNUM, { "fflags" }, true }, | |
229 | { RISCV_CSR_FRM_REGNUM, { "frm" }, true }, | |
230 | { RISCV_CSR_FCSR_REGNUM, { "fcsr" }, true }, | |
231 | ||
232 | } | |
233 | }; | |
234 | ||
235 | /* Set of virtual registers. These are not physical registers on the | |
236 | hardware, but might be available from the target. These are not pseudo | |
237 | registers, reading these really does result in a register read from the | |
238 | target, it is just that there might not be a physical register backing | |
239 | the result. */ | |
240 | ||
241 | static const struct riscv_register_feature riscv_virtual_feature = | |
242 | { | |
ed69cbc8 | 243 | "org.gnu.gdb.riscv.virtual", false, |
b5ffee31 AB |
244 | { |
245 | { RISCV_PRIV_REGNUM, { "priv" }, false } | |
246 | } | |
dbbb1059 AB |
247 | }; |
248 | ||
b5ffee31 AB |
249 | /* Feature set for CSRs. This set is NOT constant as the register names |
250 | list for each register is not complete. The aliases are computed | |
251 | during RISCV_CREATE_CSR_ALIASES. */ | |
252 | ||
253 | static struct riscv_register_feature riscv_csr_feature = | |
254 | { | |
ed69cbc8 | 255 | "org.gnu.gdb.riscv.csr", false, |
b5ffee31 | 256 | { |
8f595e9b | 257 | #define DECLARE_CSR(NAME,VALUE,CLASS,DEFINE_VER,ABORT_VER) \ |
b5ffee31 AB |
258 | { RISCV_ ## VALUE ## _REGNUM, { # NAME }, false }, |
259 | #include "opcode/riscv-opc.h" | |
260 | #undef DECLARE_CSR | |
261 | } | |
dbbb1059 AB |
262 | }; |
263 | ||
b5ffee31 AB |
264 | /* Complete RISCV_CSR_FEATURE, building the CSR alias names and adding them |
265 | to the name list for each register. */ | |
266 | ||
267 | static void | |
268 | riscv_create_csr_aliases () | |
269 | { | |
270 | for (auto ® : riscv_csr_feature.registers) | |
271 | { | |
272 | int csr_num = reg.regnum - RISCV_FIRST_CSR_REGNUM; | |
273 | const char *alias = xstrprintf ("csr%d", csr_num); | |
274 | reg.names.push_back (alias); | |
767a879e AB |
275 | |
276 | /* Setup the other csr aliases. We don't use a switch table here in | |
277 | case there are multiple aliases with the same value. Also filter | |
278 | based on ABRT_VER in order to avoid a very old alias for misa that | |
279 | duplicates the name "misa" but at a different CSR address. */ | |
280 | #define DECLARE_CSR_ALIAS(NAME,VALUE,CLASS,DEF_VER,ABRT_VER) \ | |
281 | if (csr_num == VALUE && ABRT_VER >= PRIV_SPEC_CLASS_1P11) \ | |
282 | reg.names.push_back ( # NAME ); | |
283 | #include "opcode/riscv-opc.h" | |
284 | #undef DECLARE_CSR_ALIAS | |
b5ffee31 AB |
285 | } |
286 | } | |
287 | ||
dbbb1059 AB |
288 | /* Controls whether we place compressed breakpoints or not. When in auto |
289 | mode GDB tries to determine if the target supports compressed | |
290 | breakpoints, and uses them if it does. */ | |
291 | ||
292 | static enum auto_boolean use_compressed_breakpoints; | |
293 | ||
294 | /* The show callback for 'show riscv use-compressed-breakpoints'. */ | |
295 | ||
296 | static void | |
297 | show_use_compressed_breakpoints (struct ui_file *file, int from_tty, | |
298 | struct cmd_list_element *c, | |
299 | const char *value) | |
300 | { | |
dbbb1059 AB |
301 | fprintf_filtered (file, |
302 | _("Debugger's use of compressed breakpoints is set " | |
f37bc8b1 | 303 | "to %s.\n"), value); |
dbbb1059 AB |
304 | } |
305 | ||
306 | /* The set and show lists for 'set riscv' and 'show riscv' prefixes. */ | |
307 | ||
308 | static struct cmd_list_element *setriscvcmdlist = NULL; | |
309 | static struct cmd_list_element *showriscvcmdlist = NULL; | |
310 | ||
dbbb1059 AB |
311 | /* The set and show lists for 'set riscv' and 'show riscv' prefixes. */ |
312 | ||
313 | static struct cmd_list_element *setdebugriscvcmdlist = NULL; | |
314 | static struct cmd_list_element *showdebugriscvcmdlist = NULL; | |
315 | ||
dbbb1059 AB |
316 | /* The show callback for all 'show debug riscv VARNAME' variables. */ |
317 | ||
318 | static void | |
319 | show_riscv_debug_variable (struct ui_file *file, int from_tty, | |
320 | struct cmd_list_element *c, | |
321 | const char *value) | |
322 | { | |
323 | fprintf_filtered (file, | |
324 | _("RiscV debug variable `%s' is set to: %s\n"), | |
325 | c->name, value); | |
326 | } | |
327 | ||
f37bc8b1 JB |
328 | /* When this is set to non-zero debugging information about breakpoint |
329 | kinds will be printed. */ | |
330 | ||
331 | static unsigned int riscv_debug_breakpoints = 0; | |
332 | ||
dbbb1059 AB |
333 | /* When this is set to non-zero debugging information about inferior calls |
334 | will be printed. */ | |
335 | ||
336 | static unsigned int riscv_debug_infcall = 0; | |
337 | ||
78a3b0fa AB |
338 | /* When this is set to non-zero debugging information about stack unwinding |
339 | will be printed. */ | |
340 | ||
341 | static unsigned int riscv_debug_unwinder = 0; | |
342 | ||
b5ffee31 AB |
343 | /* When this is set to non-zero debugging information about gdbarch |
344 | initialisation will be printed. */ | |
dbbb1059 | 345 | |
b5ffee31 | 346 | static unsigned int riscv_debug_gdbarch = 0; |
dbbb1059 | 347 | |
8a613826 | 348 | /* See riscv-tdep.h. */ |
dbbb1059 | 349 | |
411baa47 | 350 | int |
dbbb1059 AB |
351 | riscv_isa_xlen (struct gdbarch *gdbarch) |
352 | { | |
113b7b81 AB |
353 | return gdbarch_tdep (gdbarch)->isa_features.xlen; |
354 | } | |
355 | ||
356 | /* See riscv-tdep.h. */ | |
357 | ||
358 | int | |
359 | riscv_abi_xlen (struct gdbarch *gdbarch) | |
360 | { | |
361 | return gdbarch_tdep (gdbarch)->abi_features.xlen; | |
dbbb1059 AB |
362 | } |
363 | ||
8a613826 | 364 | /* See riscv-tdep.h. */ |
dbbb1059 | 365 | |
8a613826 | 366 | int |
dbbb1059 AB |
367 | riscv_isa_flen (struct gdbarch *gdbarch) |
368 | { | |
113b7b81 AB |
369 | return gdbarch_tdep (gdbarch)->isa_features.flen; |
370 | } | |
371 | ||
372 | /* See riscv-tdep.h. */ | |
373 | ||
374 | int | |
375 | riscv_abi_flen (struct gdbarch *gdbarch) | |
376 | { | |
377 | return gdbarch_tdep (gdbarch)->abi_features.flen; | |
dbbb1059 AB |
378 | } |
379 | ||
380 | /* Return true if the target for GDBARCH has floating point hardware. */ | |
381 | ||
382 | static bool | |
383 | riscv_has_fp_regs (struct gdbarch *gdbarch) | |
384 | { | |
385 | return (riscv_isa_flen (gdbarch) > 0); | |
386 | } | |
387 | ||
388 | /* Return true if GDBARCH is using any of the floating point hardware ABIs. */ | |
389 | ||
390 | static bool | |
391 | riscv_has_fp_abi (struct gdbarch *gdbarch) | |
392 | { | |
113b7b81 | 393 | return gdbarch_tdep (gdbarch)->abi_features.flen > 0; |
dbbb1059 AB |
394 | } |
395 | ||
8c49aa89 AB |
396 | /* Return true if REGNO is a floating pointer register. */ |
397 | ||
398 | static bool | |
399 | riscv_is_fp_regno_p (int regno) | |
400 | { | |
401 | return (regno >= RISCV_FIRST_FP_REGNUM | |
402 | && regno <= RISCV_LAST_FP_REGNUM); | |
403 | } | |
404 | ||
dbbb1059 AB |
405 | /* Implement the breakpoint_kind_from_pc gdbarch method. */ |
406 | ||
407 | static int | |
408 | riscv_breakpoint_kind_from_pc (struct gdbarch *gdbarch, CORE_ADDR *pcptr) | |
409 | { | |
410 | if (use_compressed_breakpoints == AUTO_BOOLEAN_AUTO) | |
411 | { | |
3ba2ee38 | 412 | bool unaligned_p = false; |
f37bc8b1 JB |
413 | gdb_byte buf[1]; |
414 | ||
3ba2ee38 JW |
415 | /* Some targets don't support unaligned reads. The address can only |
416 | be unaligned if the C extension is supported. So it is safe to | |
417 | use a compressed breakpoint in this case. */ | |
418 | if (*pcptr & 0x2) | |
419 | unaligned_p = true; | |
420 | else | |
421 | { | |
c01660c6 AB |
422 | /* Read the opcode byte to determine the instruction length. If |
423 | the read fails this may be because we tried to set the | |
424 | breakpoint at an invalid address, in this case we provide a | |
425 | fake result which will give a breakpoint length of 4. | |
426 | Hopefully when we try to actually insert the breakpoint we | |
427 | will see a failure then too which will be reported to the | |
428 | user. */ | |
429 | if (target_read_code (*pcptr, buf, 1) == -1) | |
430 | buf[0] = 0; | |
3ba2ee38 JW |
431 | read_code (*pcptr, buf, 1); |
432 | } | |
f37bc8b1 JB |
433 | |
434 | if (riscv_debug_breakpoints) | |
3ba2ee38 JW |
435 | { |
436 | const char *bp = (unaligned_p || riscv_insn_length (buf[0]) == 2 | |
437 | ? "C.EBREAK" : "EBREAK"); | |
438 | ||
439 | fprintf_unfiltered (gdb_stdlog, "Using %s for breakpoint at %s ", | |
440 | bp, paddress (gdbarch, *pcptr)); | |
441 | if (unaligned_p) | |
442 | fprintf_unfiltered (gdb_stdlog, "(unaligned address)\n"); | |
443 | else | |
444 | fprintf_unfiltered (gdb_stdlog, "(instruction length %d)\n", | |
445 | riscv_insn_length (buf[0])); | |
446 | } | |
447 | if (unaligned_p || riscv_insn_length (buf[0]) == 2) | |
dbbb1059 AB |
448 | return 2; |
449 | else | |
450 | return 4; | |
451 | } | |
452 | else if (use_compressed_breakpoints == AUTO_BOOLEAN_TRUE) | |
453 | return 2; | |
454 | else | |
455 | return 4; | |
456 | } | |
457 | ||
458 | /* Implement the sw_breakpoint_from_kind gdbarch method. */ | |
459 | ||
460 | static const gdb_byte * | |
461 | riscv_sw_breakpoint_from_kind (struct gdbarch *gdbarch, int kind, int *size) | |
462 | { | |
463 | static const gdb_byte ebreak[] = { 0x73, 0x00, 0x10, 0x00, }; | |
464 | static const gdb_byte c_ebreak[] = { 0x02, 0x90 }; | |
465 | ||
466 | *size = kind; | |
467 | switch (kind) | |
468 | { | |
469 | case 2: | |
470 | return c_ebreak; | |
471 | case 4: | |
472 | return ebreak; | |
473 | default: | |
89a3b63e | 474 | gdb_assert_not_reached (_("unhandled breakpoint kind")); |
dbbb1059 AB |
475 | } |
476 | } | |
477 | ||
478 | /* Callback function for user_reg_add. */ | |
479 | ||
480 | static struct value * | |
481 | value_of_riscv_user_reg (struct frame_info *frame, const void *baton) | |
482 | { | |
483 | const int *reg_p = (const int *) baton; | |
484 | return value_of_register (*reg_p, frame); | |
485 | } | |
486 | ||
b5ffee31 AB |
487 | /* Implement the register_name gdbarch method. This is used instead of |
488 | the function supplied by calling TDESC_USE_REGISTERS so that we can | |
ed69cbc8 | 489 | ensure the preferred names are offered for x-regs and f-regs. */ |
dbbb1059 AB |
490 | |
491 | static const char * | |
492 | riscv_register_name (struct gdbarch *gdbarch, int regnum) | |
493 | { | |
b5ffee31 AB |
494 | /* Lookup the name through the target description. If we get back NULL |
495 | then this is an unknown register. If we do get a name back then we | |
496 | look up the registers preferred name below. */ | |
497 | const char *name = tdesc_register_name (gdbarch, regnum); | |
498 | if (name == NULL || name[0] == '\0') | |
499 | return NULL; | |
500 | ||
ed69cbc8 AB |
501 | /* We want GDB to use the ABI names for registers even if the target |
502 | gives us a target description with the architectural name. For | |
503 | example we want to see 'ra' instead of 'x1' whatever the target | |
504 | description called it. */ | |
b5ffee31 AB |
505 | if (regnum >= RISCV_ZERO_REGNUM && regnum < RISCV_FIRST_FP_REGNUM) |
506 | { | |
507 | gdb_assert (regnum < riscv_xreg_feature.registers.size ()); | |
508 | return riscv_xreg_feature.registers[regnum].names[0]; | |
509 | } | |
510 | ||
ed69cbc8 AB |
511 | /* Like with the x-regs we prefer the abi names for the floating point |
512 | registers. */ | |
b5ffee31 | 513 | if (regnum >= RISCV_FIRST_FP_REGNUM && regnum <= RISCV_LAST_FP_REGNUM) |
dbbb1059 | 514 | { |
b5ffee31 AB |
515 | if (riscv_has_fp_regs (gdbarch)) |
516 | { | |
517 | regnum -= RISCV_FIRST_FP_REGNUM; | |
518 | gdb_assert (regnum < riscv_freg_feature.registers.size ()); | |
519 | return riscv_freg_feature.registers[regnum].names[0]; | |
520 | } | |
521 | else | |
522 | return NULL; | |
dbbb1059 AB |
523 | } |
524 | ||
ed69cbc8 AB |
525 | /* The remaining registers are different. For all other registers on the |
526 | machine we prefer to see the names that the target description | |
527 | provides. This is particularly important for CSRs which might be | |
528 | renamed over time. If GDB keeps track of the "latest" name, but a | |
529 | particular target provides an older name then we don't want to force | |
530 | users to see the newer name in register output. | |
dbbb1059 | 531 | |
ed69cbc8 AB |
532 | The other case that reaches here are any registers that the target |
533 | provided that GDB is completely unaware of. For these we have no | |
534 | choice but to accept the target description name. | |
dbbb1059 | 535 | |
ed69cbc8 | 536 | Just accept whatever name TDESC_REGISTER_NAME returned. */ |
b5ffee31 | 537 | return name; |
dbbb1059 AB |
538 | } |
539 | ||
270b9329 JW |
540 | /* Construct a type for 64-bit FP registers. */ |
541 | ||
542 | static struct type * | |
543 | riscv_fpreg_d_type (struct gdbarch *gdbarch) | |
544 | { | |
545 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
546 | ||
547 | if (tdep->riscv_fpreg_d_type == nullptr) | |
548 | { | |
549 | const struct builtin_type *bt = builtin_type (gdbarch); | |
550 | ||
551 | /* The type we're building is this: */ | |
552 | #if 0 | |
553 | union __gdb_builtin_type_fpreg_d | |
554 | { | |
555 | float f; | |
556 | double d; | |
557 | }; | |
558 | #endif | |
559 | ||
560 | struct type *t; | |
561 | ||
562 | t = arch_composite_type (gdbarch, | |
563 | "__gdb_builtin_type_fpreg_d", TYPE_CODE_UNION); | |
564 | append_composite_type_field (t, "float", bt->builtin_float); | |
565 | append_composite_type_field (t, "double", bt->builtin_double); | |
566 | TYPE_VECTOR (t) = 1; | |
d0e39ea2 | 567 | t->set_name ("builtin_type_fpreg_d"); |
270b9329 JW |
568 | tdep->riscv_fpreg_d_type = t; |
569 | } | |
570 | ||
571 | return tdep->riscv_fpreg_d_type; | |
572 | } | |
573 | ||
b5ffee31 AB |
574 | /* Implement the register_type gdbarch method. This is installed as an |
575 | for the override setup by TDESC_USE_REGISTERS, for most registers we | |
576 | delegate the type choice to the target description, but for a few | |
577 | registers we try to improve the types if the target description has | |
578 | taken a simplistic approach. */ | |
270b9329 JW |
579 | |
580 | static struct type * | |
b5ffee31 | 581 | riscv_register_type (struct gdbarch *gdbarch, int regnum) |
270b9329 | 582 | { |
b5ffee31 AB |
583 | struct type *type = tdesc_register_type (gdbarch, regnum); |
584 | int xlen = riscv_isa_xlen (gdbarch); | |
270b9329 | 585 | |
b5ffee31 AB |
586 | /* We want to perform some specific type "fixes" in cases where we feel |
587 | that we really can do better than the target description. For all | |
588 | other cases we just return what the target description says. */ | |
589 | if (riscv_is_fp_regno_p (regnum)) | |
270b9329 | 590 | { |
b5ffee31 AB |
591 | /* This spots the case for RV64 where the double is defined as |
592 | either 'ieee_double' or 'float' (which is the generic name that | |
593 | converts to 'double' on 64-bit). In these cases its better to | |
594 | present the registers using a union type. */ | |
595 | int flen = riscv_isa_flen (gdbarch); | |
596 | if (flen == 8 | |
78134374 | 597 | && type->code () == TYPE_CODE_FLT |
b5ffee31 | 598 | && TYPE_LENGTH (type) == flen |
7d93a1e0 SM |
599 | && (strcmp (type->name (), "builtin_type_ieee_double") == 0 |
600 | || strcmp (type->name (), "double") == 0)) | |
b5ffee31 | 601 | type = riscv_fpreg_d_type (gdbarch); |
270b9329 JW |
602 | } |
603 | ||
b5ffee31 AB |
604 | if ((regnum == gdbarch_pc_regnum (gdbarch) |
605 | || regnum == RISCV_RA_REGNUM | |
606 | || regnum == RISCV_FP_REGNUM | |
607 | || regnum == RISCV_SP_REGNUM | |
608 | || regnum == RISCV_GP_REGNUM | |
609 | || regnum == RISCV_TP_REGNUM) | |
78134374 | 610 | && type->code () == TYPE_CODE_INT |
b5ffee31 | 611 | && TYPE_LENGTH (type) == xlen) |
dbbb1059 | 612 | { |
b5ffee31 AB |
613 | /* This spots the case where some interesting registers are defined |
614 | as simple integers of the expected size, we force these registers | |
615 | to be pointers as we believe that is more useful. */ | |
dbbb1059 | 616 | if (regnum == gdbarch_pc_regnum (gdbarch) |
b5ffee31 AB |
617 | || regnum == RISCV_RA_REGNUM) |
618 | type = builtin_type (gdbarch)->builtin_func_ptr; | |
619 | else if (regnum == RISCV_FP_REGNUM | |
620 | || regnum == RISCV_SP_REGNUM | |
621 | || regnum == RISCV_GP_REGNUM | |
622 | || regnum == RISCV_TP_REGNUM) | |
623 | type = builtin_type (gdbarch)->builtin_data_ptr; | |
dbbb1059 | 624 | } |
dbbb1059 | 625 | |
b5ffee31 | 626 | return type; |
dbbb1059 AB |
627 | } |
628 | ||
629 | /* Helper for riscv_print_registers_info, prints info for a single register | |
630 | REGNUM. */ | |
631 | ||
632 | static void | |
633 | riscv_print_one_register_info (struct gdbarch *gdbarch, | |
634 | struct ui_file *file, | |
635 | struct frame_info *frame, | |
636 | int regnum) | |
637 | { | |
638 | const char *name = gdbarch_register_name (gdbarch, regnum); | |
b5ffee31 AB |
639 | struct value *val; |
640 | struct type *regtype; | |
dbbb1059 AB |
641 | int print_raw_format; |
642 | enum tab_stops { value_column_1 = 15 }; | |
643 | ||
644 | fputs_filtered (name, file); | |
645 | print_spaces_filtered (value_column_1 - strlen (name), file); | |
646 | ||
a70b8144 | 647 | try |
b5ffee31 AB |
648 | { |
649 | val = value_of_register (regnum, frame); | |
650 | regtype = value_type (val); | |
651 | } | |
230d2906 | 652 | catch (const gdb_exception_error &ex) |
b5ffee31 AB |
653 | { |
654 | /* Handle failure to read a register without interrupting the entire | |
655 | 'info registers' flow. */ | |
3d6e9d23 | 656 | fprintf_filtered (file, "%s\n", ex.what ()); |
b5ffee31 AB |
657 | return; |
658 | } | |
b5ffee31 | 659 | |
dbbb1059 AB |
660 | print_raw_format = (value_entirely_available (val) |
661 | && !value_optimized_out (val)); | |
662 | ||
78134374 SM |
663 | if (regtype->code () == TYPE_CODE_FLT |
664 | || (regtype->code () == TYPE_CODE_UNION | |
1f704f76 | 665 | && regtype->num_fields () == 2 |
940da03e SM |
666 | && regtype->field (0).type ()->code () == TYPE_CODE_FLT |
667 | && regtype->field (1).type ()->code () == TYPE_CODE_FLT) | |
78134374 | 668 | || (regtype->code () == TYPE_CODE_UNION |
1f704f76 | 669 | && regtype->num_fields () == 3 |
940da03e SM |
670 | && regtype->field (0).type ()->code () == TYPE_CODE_FLT |
671 | && regtype->field (1).type ()->code () == TYPE_CODE_FLT | |
672 | && regtype->field (2).type ()->code () == TYPE_CODE_FLT)) | |
dbbb1059 AB |
673 | { |
674 | struct value_print_options opts; | |
675 | const gdb_byte *valaddr = value_contents_for_printing (val); | |
34877895 | 676 | enum bfd_endian byte_order = type_byte_order (regtype); |
dbbb1059 AB |
677 | |
678 | get_user_print_options (&opts); | |
679 | opts.deref_ref = 1; | |
680 | ||
040f66bd | 681 | common_val_print (val, file, 0, &opts, current_language); |
dbbb1059 AB |
682 | |
683 | if (print_raw_format) | |
684 | { | |
685 | fprintf_filtered (file, "\t(raw "); | |
686 | print_hex_chars (file, valaddr, TYPE_LENGTH (regtype), byte_order, | |
687 | true); | |
688 | fprintf_filtered (file, ")"); | |
689 | } | |
690 | } | |
691 | else | |
692 | { | |
693 | struct value_print_options opts; | |
694 | ||
695 | /* Print the register in hex. */ | |
696 | get_formatted_print_options (&opts, 'x'); | |
697 | opts.deref_ref = 1; | |
040f66bd | 698 | common_val_print (val, file, 0, &opts, current_language); |
dbbb1059 AB |
699 | |
700 | if (print_raw_format) | |
701 | { | |
702 | if (regnum == RISCV_CSR_MSTATUS_REGNUM) | |
703 | { | |
704 | LONGEST d; | |
705 | int size = register_size (gdbarch, regnum); | |
706 | unsigned xlen; | |
707 | ||
b7c8601a JW |
708 | /* The SD field is always in the upper bit of MSTATUS, regardless |
709 | of the number of bits in MSTATUS. */ | |
dbbb1059 | 710 | d = value_as_long (val); |
b7c8601a | 711 | xlen = size * 8; |
dbbb1059 AB |
712 | fprintf_filtered (file, |
713 | "\tSD:%X VM:%02X MXR:%X PUM:%X MPRV:%X XS:%X " | |
714 | "FS:%X MPP:%x HPP:%X SPP:%X MPIE:%X HPIE:%X " | |
715 | "SPIE:%X UPIE:%X MIE:%X HIE:%X SIE:%X UIE:%X", | |
716 | (int) ((d >> (xlen - 1)) & 0x1), | |
717 | (int) ((d >> 24) & 0x1f), | |
718 | (int) ((d >> 19) & 0x1), | |
719 | (int) ((d >> 18) & 0x1), | |
720 | (int) ((d >> 17) & 0x1), | |
721 | (int) ((d >> 15) & 0x3), | |
722 | (int) ((d >> 13) & 0x3), | |
723 | (int) ((d >> 11) & 0x3), | |
724 | (int) ((d >> 9) & 0x3), | |
725 | (int) ((d >> 8) & 0x1), | |
726 | (int) ((d >> 7) & 0x1), | |
727 | (int) ((d >> 6) & 0x1), | |
728 | (int) ((d >> 5) & 0x1), | |
729 | (int) ((d >> 4) & 0x1), | |
730 | (int) ((d >> 3) & 0x1), | |
731 | (int) ((d >> 2) & 0x1), | |
732 | (int) ((d >> 1) & 0x1), | |
733 | (int) ((d >> 0) & 0x1)); | |
734 | } | |
735 | else if (regnum == RISCV_CSR_MISA_REGNUM) | |
736 | { | |
737 | int base; | |
738 | unsigned xlen, i; | |
739 | LONGEST d; | |
b7c8601a | 740 | int size = register_size (gdbarch, regnum); |
dbbb1059 | 741 | |
b7c8601a JW |
742 | /* The MXL field is always in the upper two bits of MISA, |
743 | regardless of the number of bits in MISA. Mask out other | |
744 | bits to ensure we have a positive value. */ | |
dbbb1059 | 745 | d = value_as_long (val); |
b7c8601a | 746 | base = (d >> ((size * 8) - 2)) & 0x3; |
dbbb1059 AB |
747 | xlen = 16; |
748 | ||
749 | for (; base > 0; base--) | |
750 | xlen *= 2; | |
751 | fprintf_filtered (file, "\tRV%d", xlen); | |
752 | ||
753 | for (i = 0; i < 26; i++) | |
754 | { | |
755 | if (d & (1 << i)) | |
756 | fprintf_filtered (file, "%c", 'A' + i); | |
757 | } | |
758 | } | |
759 | else if (regnum == RISCV_CSR_FCSR_REGNUM | |
760 | || regnum == RISCV_CSR_FFLAGS_REGNUM | |
761 | || regnum == RISCV_CSR_FRM_REGNUM) | |
762 | { | |
763 | LONGEST d; | |
764 | ||
765 | d = value_as_long (val); | |
766 | ||
767 | fprintf_filtered (file, "\t"); | |
768 | if (regnum != RISCV_CSR_FRM_REGNUM) | |
769 | fprintf_filtered (file, | |
770 | "RD:%01X NV:%d DZ:%d OF:%d UF:%d NX:%d", | |
771 | (int) ((d >> 5) & 0x7), | |
772 | (int) ((d >> 4) & 0x1), | |
773 | (int) ((d >> 3) & 0x1), | |
774 | (int) ((d >> 2) & 0x1), | |
775 | (int) ((d >> 1) & 0x1), | |
776 | (int) ((d >> 0) & 0x1)); | |
777 | ||
778 | if (regnum != RISCV_CSR_FFLAGS_REGNUM) | |
779 | { | |
780 | static const char * const sfrm[] = | |
781 | { | |
782 | "RNE (round to nearest; ties to even)", | |
783 | "RTZ (Round towards zero)", | |
784 | "RDN (Round down towards -INF)", | |
785 | "RUP (Round up towards +INF)", | |
786 | "RMM (Round to nearest; ties to max magnitude)", | |
787 | "INVALID[5]", | |
788 | "INVALID[6]", | |
789 | "dynamic rounding mode", | |
790 | }; | |
791 | int frm = ((regnum == RISCV_CSR_FCSR_REGNUM) | |
792 | ? (d >> 5) : d) & 0x3; | |
793 | ||
794 | fprintf_filtered (file, "%sFRM:%i [%s]", | |
795 | (regnum == RISCV_CSR_FCSR_REGNUM | |
796 | ? " " : ""), | |
797 | frm, sfrm[frm]); | |
798 | } | |
799 | } | |
800 | else if (regnum == RISCV_PRIV_REGNUM) | |
801 | { | |
802 | LONGEST d; | |
803 | uint8_t priv; | |
804 | ||
805 | d = value_as_long (val); | |
806 | priv = d & 0xff; | |
807 | ||
808 | if (priv < 4) | |
809 | { | |
810 | static const char * const sprv[] = | |
811 | { | |
812 | "User/Application", | |
813 | "Supervisor", | |
814 | "Hypervisor", | |
815 | "Machine" | |
816 | }; | |
817 | fprintf_filtered (file, "\tprv:%d [%s]", | |
818 | priv, sprv[priv]); | |
819 | } | |
820 | else | |
821 | fprintf_filtered (file, "\tprv:%d [INVALID]", priv); | |
822 | } | |
823 | else | |
824 | { | |
825 | /* If not a vector register, print it also according to its | |
826 | natural format. */ | |
827 | if (TYPE_VECTOR (regtype) == 0) | |
828 | { | |
829 | get_user_print_options (&opts); | |
830 | opts.deref_ref = 1; | |
831 | fprintf_filtered (file, "\t"); | |
040f66bd | 832 | common_val_print (val, file, 0, &opts, current_language); |
dbbb1059 AB |
833 | } |
834 | } | |
835 | } | |
836 | } | |
837 | fprintf_filtered (file, "\n"); | |
838 | } | |
839 | ||
0dbfcfff AB |
840 | /* Return true if REGNUM is a valid CSR register. The CSR register space |
841 | is sparsely populated, so not every number is a named CSR. */ | |
842 | ||
843 | static bool | |
844 | riscv_is_regnum_a_named_csr (int regnum) | |
845 | { | |
846 | gdb_assert (regnum >= RISCV_FIRST_CSR_REGNUM | |
847 | && regnum <= RISCV_LAST_CSR_REGNUM); | |
848 | ||
849 | switch (regnum) | |
850 | { | |
8f595e9b | 851 | #define DECLARE_CSR(name, num, class, define_ver, abort_ver) case RISCV_ ## num ## _REGNUM: |
0dbfcfff AB |
852 | #include "opcode/riscv-opc.h" |
853 | #undef DECLARE_CSR | |
854 | return true; | |
855 | ||
856 | default: | |
857 | return false; | |
858 | } | |
859 | } | |
860 | ||
dbbb1059 AB |
861 | /* Implement the register_reggroup_p gdbarch method. Is REGNUM a member |
862 | of REGGROUP? */ | |
863 | ||
864 | static int | |
865 | riscv_register_reggroup_p (struct gdbarch *gdbarch, int regnum, | |
866 | struct reggroup *reggroup) | |
867 | { | |
dbbb1059 AB |
868 | /* Used by 'info registers' and 'info registers <groupname>'. */ |
869 | ||
870 | if (gdbarch_register_name (gdbarch, regnum) == NULL | |
871 | || gdbarch_register_name (gdbarch, regnum)[0] == '\0') | |
872 | return 0; | |
873 | ||
b5ffee31 AB |
874 | if (regnum > RISCV_LAST_REGNUM) |
875 | { | |
876 | int ret = tdesc_register_in_reggroup_p (gdbarch, regnum, reggroup); | |
877 | if (ret != -1) | |
878 | return ret; | |
879 | ||
880 | return default_register_reggroup_p (gdbarch, regnum, reggroup); | |
881 | } | |
882 | ||
dbbb1059 AB |
883 | if (reggroup == all_reggroup) |
884 | { | |
885 | if (regnum < RISCV_FIRST_CSR_REGNUM || regnum == RISCV_PRIV_REGNUM) | |
886 | return 1; | |
0dbfcfff AB |
887 | if (riscv_is_regnum_a_named_csr (regnum)) |
888 | return 1; | |
dbbb1059 AB |
889 | return 0; |
890 | } | |
891 | else if (reggroup == float_reggroup) | |
8c49aa89 AB |
892 | return (riscv_is_fp_regno_p (regnum) |
893 | || regnum == RISCV_CSR_FCSR_REGNUM | |
894 | || regnum == RISCV_CSR_FFLAGS_REGNUM | |
895 | || regnum == RISCV_CSR_FRM_REGNUM); | |
dbbb1059 AB |
896 | else if (reggroup == general_reggroup) |
897 | return regnum < RISCV_FIRST_FP_REGNUM; | |
898 | else if (reggroup == restore_reggroup || reggroup == save_reggroup) | |
899 | { | |
900 | if (riscv_has_fp_regs (gdbarch)) | |
ecc82c05 AB |
901 | return (regnum <= RISCV_LAST_FP_REGNUM |
902 | || regnum == RISCV_CSR_FCSR_REGNUM | |
903 | || regnum == RISCV_CSR_FFLAGS_REGNUM | |
904 | || regnum == RISCV_CSR_FRM_REGNUM); | |
dbbb1059 AB |
905 | else |
906 | return regnum < RISCV_FIRST_FP_REGNUM; | |
907 | } | |
b5ffee31 | 908 | else if (reggroup == system_reggroup || reggroup == csr_reggroup) |
dbbb1059 AB |
909 | { |
910 | if (regnum == RISCV_PRIV_REGNUM) | |
911 | return 1; | |
912 | if (regnum < RISCV_FIRST_CSR_REGNUM || regnum > RISCV_LAST_CSR_REGNUM) | |
913 | return 0; | |
0dbfcfff AB |
914 | if (riscv_is_regnum_a_named_csr (regnum)) |
915 | return 1; | |
dbbb1059 AB |
916 | return 0; |
917 | } | |
918 | else if (reggroup == vector_reggroup) | |
919 | return 0; | |
920 | else | |
921 | return 0; | |
922 | } | |
923 | ||
924 | /* Implement the print_registers_info gdbarch method. This is used by | |
925 | 'info registers' and 'info all-registers'. */ | |
926 | ||
927 | static void | |
928 | riscv_print_registers_info (struct gdbarch *gdbarch, | |
929 | struct ui_file *file, | |
930 | struct frame_info *frame, | |
931 | int regnum, int print_all) | |
932 | { | |
933 | if (regnum != -1) | |
934 | { | |
935 | /* Print one specified register. */ | |
dbbb1059 AB |
936 | if (gdbarch_register_name (gdbarch, regnum) == NULL |
937 | || *(gdbarch_register_name (gdbarch, regnum)) == '\0') | |
938 | error (_("Not a valid register for the current processor type")); | |
939 | riscv_print_one_register_info (gdbarch, file, frame, regnum); | |
940 | } | |
941 | else | |
942 | { | |
943 | struct reggroup *reggroup; | |
944 | ||
945 | if (print_all) | |
946 | reggroup = all_reggroup; | |
947 | else | |
948 | reggroup = general_reggroup; | |
949 | ||
950 | for (regnum = 0; regnum <= RISCV_LAST_REGNUM; ++regnum) | |
951 | { | |
952 | /* Zero never changes, so might as well hide by default. */ | |
953 | if (regnum == RISCV_ZERO_REGNUM && !print_all) | |
954 | continue; | |
955 | ||
956 | /* Registers with no name are not valid on this ISA. */ | |
957 | if (gdbarch_register_name (gdbarch, regnum) == NULL | |
958 | || *(gdbarch_register_name (gdbarch, regnum)) == '\0') | |
959 | continue; | |
960 | ||
961 | /* Is the register in the group we're interested in? */ | |
b5ffee31 | 962 | if (!gdbarch_register_reggroup_p (gdbarch, regnum, reggroup)) |
dbbb1059 AB |
963 | continue; |
964 | ||
965 | riscv_print_one_register_info (gdbarch, file, frame, regnum); | |
966 | } | |
967 | } | |
968 | } | |
969 | ||
970 | /* Class that handles one decoded RiscV instruction. */ | |
971 | ||
972 | class riscv_insn | |
973 | { | |
974 | public: | |
975 | ||
976 | /* Enum of all the opcodes that GDB cares about during the prologue scan. */ | |
977 | enum opcode | |
978 | { | |
979 | /* Unknown value is used at initialisation time. */ | |
980 | UNKNOWN = 0, | |
981 | ||
982 | /* These instructions are all the ones we are interested in during the | |
983 | prologue scan. */ | |
984 | ADD, | |
985 | ADDI, | |
986 | ADDIW, | |
987 | ADDW, | |
988 | AUIPC, | |
989 | LUI, | |
990 | SD, | |
991 | SW, | |
405feb71 | 992 | /* These are needed for software breakpoint support. */ |
5c720ed8 JW |
993 | JAL, |
994 | JALR, | |
995 | BEQ, | |
996 | BNE, | |
997 | BLT, | |
998 | BGE, | |
999 | BLTU, | |
1000 | BGEU, | |
1001 | /* These are needed for stepping over atomic sequences. */ | |
1002 | LR, | |
1003 | SC, | |
dbbb1059 AB |
1004 | |
1005 | /* Other instructions are not interesting during the prologue scan, and | |
1006 | are ignored. */ | |
1007 | OTHER | |
1008 | }; | |
1009 | ||
1010 | riscv_insn () | |
1011 | : m_length (0), | |
1012 | m_opcode (OTHER), | |
1013 | m_rd (0), | |
1014 | m_rs1 (0), | |
1015 | m_rs2 (0) | |
1016 | { | |
1017 | /* Nothing. */ | |
1018 | } | |
1019 | ||
1020 | void decode (struct gdbarch *gdbarch, CORE_ADDR pc); | |
1021 | ||
1022 | /* Get the length of the instruction in bytes. */ | |
1023 | int length () const | |
1024 | { return m_length; } | |
1025 | ||
1026 | /* Get the opcode for this instruction. */ | |
1027 | enum opcode opcode () const | |
1028 | { return m_opcode; } | |
1029 | ||
1030 | /* Get destination register field for this instruction. This is only | |
1031 | valid if the OPCODE implies there is such a field for this | |
1032 | instruction. */ | |
1033 | int rd () const | |
1034 | { return m_rd; } | |
1035 | ||
1036 | /* Get the RS1 register field for this instruction. This is only valid | |
1037 | if the OPCODE implies there is such a field for this instruction. */ | |
1038 | int rs1 () const | |
1039 | { return m_rs1; } | |
1040 | ||
1041 | /* Get the RS2 register field for this instruction. This is only valid | |
1042 | if the OPCODE implies there is such a field for this instruction. */ | |
1043 | int rs2 () const | |
1044 | { return m_rs2; } | |
1045 | ||
1046 | /* Get the immediate for this instruction in signed form. This is only | |
1047 | valid if the OPCODE implies there is such a field for this | |
1048 | instruction. */ | |
1049 | int imm_signed () const | |
1050 | { return m_imm.s; } | |
1051 | ||
1052 | private: | |
1053 | ||
1054 | /* Extract 5 bit register field at OFFSET from instruction OPCODE. */ | |
1055 | int decode_register_index (unsigned long opcode, int offset) | |
1056 | { | |
1057 | return (opcode >> offset) & 0x1F; | |
1058 | } | |
1059 | ||
5c720ed8 JW |
1060 | /* Extract 5 bit register field at OFFSET from instruction OPCODE. */ |
1061 | int decode_register_index_short (unsigned long opcode, int offset) | |
1062 | { | |
1063 | return ((opcode >> offset) & 0x7) + 8; | |
1064 | } | |
1065 | ||
dbbb1059 AB |
1066 | /* Helper for DECODE, decode 32-bit R-type instruction. */ |
1067 | void decode_r_type_insn (enum opcode opcode, ULONGEST ival) | |
1068 | { | |
1069 | m_opcode = opcode; | |
1070 | m_rd = decode_register_index (ival, OP_SH_RD); | |
1071 | m_rs1 = decode_register_index (ival, OP_SH_RS1); | |
1072 | m_rs2 = decode_register_index (ival, OP_SH_RS2); | |
1073 | } | |
1074 | ||
1075 | /* Helper for DECODE, decode 16-bit compressed R-type instruction. */ | |
1076 | void decode_cr_type_insn (enum opcode opcode, ULONGEST ival) | |
1077 | { | |
1078 | m_opcode = opcode; | |
1079 | m_rd = m_rs1 = decode_register_index (ival, OP_SH_CRS1S); | |
1080 | m_rs2 = decode_register_index (ival, OP_SH_CRS2); | |
1081 | } | |
1082 | ||
1083 | /* Helper for DECODE, decode 32-bit I-type instruction. */ | |
1084 | void decode_i_type_insn (enum opcode opcode, ULONGEST ival) | |
1085 | { | |
1086 | m_opcode = opcode; | |
1087 | m_rd = decode_register_index (ival, OP_SH_RD); | |
1088 | m_rs1 = decode_register_index (ival, OP_SH_RS1); | |
1089 | m_imm.s = EXTRACT_ITYPE_IMM (ival); | |
1090 | } | |
1091 | ||
1092 | /* Helper for DECODE, decode 16-bit compressed I-type instruction. */ | |
1093 | void decode_ci_type_insn (enum opcode opcode, ULONGEST ival) | |
1094 | { | |
1095 | m_opcode = opcode; | |
1096 | m_rd = m_rs1 = decode_register_index (ival, OP_SH_CRS1S); | |
1097 | m_imm.s = EXTRACT_RVC_IMM (ival); | |
1098 | } | |
1099 | ||
1100 | /* Helper for DECODE, decode 32-bit S-type instruction. */ | |
1101 | void decode_s_type_insn (enum opcode opcode, ULONGEST ival) | |
1102 | { | |
1103 | m_opcode = opcode; | |
1104 | m_rs1 = decode_register_index (ival, OP_SH_RS1); | |
1105 | m_rs2 = decode_register_index (ival, OP_SH_RS2); | |
1106 | m_imm.s = EXTRACT_STYPE_IMM (ival); | |
1107 | } | |
1108 | ||
ff3a05b3 AB |
1109 | /* Helper for DECODE, decode 16-bit CS-type instruction. The immediate |
1110 | encoding is different for each CS format instruction, so extracting | |
1111 | the immediate is left up to the caller, who should pass the extracted | |
1112 | immediate value through in IMM. */ | |
1113 | void decode_cs_type_insn (enum opcode opcode, ULONGEST ival, int imm) | |
1114 | { | |
1115 | m_opcode = opcode; | |
1116 | m_imm.s = imm; | |
1117 | m_rs1 = decode_register_index_short (ival, OP_SH_CRS1S); | |
1118 | m_rs2 = decode_register_index_short (ival, OP_SH_CRS2S); | |
1119 | } | |
1120 | ||
1121 | /* Helper for DECODE, decode 16-bit CSS-type instruction. The immediate | |
1122 | encoding is different for each CSS format instruction, so extracting | |
1123 | the immediate is left up to the caller, who should pass the extracted | |
1124 | immediate value through in IMM. */ | |
1125 | void decode_css_type_insn (enum opcode opcode, ULONGEST ival, int imm) | |
1126 | { | |
1127 | m_opcode = opcode; | |
1128 | m_imm.s = imm; | |
1129 | m_rs1 = RISCV_SP_REGNUM; | |
1130 | /* Not a compressed register number in this case. */ | |
1131 | m_rs2 = decode_register_index (ival, OP_SH_CRS2); | |
1132 | } | |
1133 | ||
dbbb1059 AB |
1134 | /* Helper for DECODE, decode 32-bit U-type instruction. */ |
1135 | void decode_u_type_insn (enum opcode opcode, ULONGEST ival) | |
1136 | { | |
1137 | m_opcode = opcode; | |
1138 | m_rd = decode_register_index (ival, OP_SH_RD); | |
1139 | m_imm.s = EXTRACT_UTYPE_IMM (ival); | |
1140 | } | |
1141 | ||
5c720ed8 JW |
1142 | /* Helper for DECODE, decode 32-bit J-type instruction. */ |
1143 | void decode_j_type_insn (enum opcode opcode, ULONGEST ival) | |
1144 | { | |
1145 | m_opcode = opcode; | |
1146 | m_rd = decode_register_index (ival, OP_SH_RD); | |
1147 | m_imm.s = EXTRACT_UJTYPE_IMM (ival); | |
1148 | } | |
1149 | ||
1150 | /* Helper for DECODE, decode 32-bit J-type instruction. */ | |
1151 | void decode_cj_type_insn (enum opcode opcode, ULONGEST ival) | |
1152 | { | |
1153 | m_opcode = opcode; | |
1154 | m_imm.s = EXTRACT_RVC_J_IMM (ival); | |
1155 | } | |
1156 | ||
1157 | void decode_b_type_insn (enum opcode opcode, ULONGEST ival) | |
1158 | { | |
1159 | m_opcode = opcode; | |
1160 | m_rs1 = decode_register_index (ival, OP_SH_RS1); | |
1161 | m_rs2 = decode_register_index (ival, OP_SH_RS2); | |
1162 | m_imm.s = EXTRACT_SBTYPE_IMM (ival); | |
1163 | } | |
1164 | ||
1165 | void decode_cb_type_insn (enum opcode opcode, ULONGEST ival) | |
1166 | { | |
1167 | m_opcode = opcode; | |
1168 | m_rs1 = decode_register_index_short (ival, OP_SH_CRS1S); | |
1169 | m_imm.s = EXTRACT_RVC_B_IMM (ival); | |
1170 | } | |
1171 | ||
dbbb1059 AB |
1172 | /* Fetch instruction from target memory at ADDR, return the content of |
1173 | the instruction, and update LEN with the instruction length. */ | |
1174 | static ULONGEST fetch_instruction (struct gdbarch *gdbarch, | |
1175 | CORE_ADDR addr, int *len); | |
1176 | ||
1177 | /* The length of the instruction in bytes. Should be 2 or 4. */ | |
1178 | int m_length; | |
1179 | ||
1180 | /* The instruction opcode. */ | |
1181 | enum opcode m_opcode; | |
1182 | ||
1183 | /* The three possible registers an instruction might reference. Not | |
1184 | every instruction fills in all of these registers. Which fields are | |
1185 | valid depends on the opcode. The naming of these fields matches the | |
1186 | naming in the riscv isa manual. */ | |
1187 | int m_rd; | |
1188 | int m_rs1; | |
1189 | int m_rs2; | |
1190 | ||
1191 | /* Possible instruction immediate. This is only valid if the instruction | |
1192 | format contains an immediate, not all instruction, whether this is | |
1193 | valid depends on the opcode. Despite only having one format for now | |
1194 | the immediate is packed into a union, later instructions might require | |
1195 | an unsigned formatted immediate, having the union in place now will | |
1196 | reduce the need for code churn later. */ | |
1197 | union riscv_insn_immediate | |
1198 | { | |
1199 | riscv_insn_immediate () | |
1200 | : s (0) | |
1201 | { | |
1202 | /* Nothing. */ | |
1203 | } | |
1204 | ||
1205 | int s; | |
1206 | } m_imm; | |
1207 | }; | |
1208 | ||
1209 | /* Fetch instruction from target memory at ADDR, return the content of the | |
1210 | instruction, and update LEN with the instruction length. */ | |
1211 | ||
1212 | ULONGEST | |
1213 | riscv_insn::fetch_instruction (struct gdbarch *gdbarch, | |
1214 | CORE_ADDR addr, int *len) | |
1215 | { | |
1216 | enum bfd_endian byte_order = gdbarch_byte_order_for_code (gdbarch); | |
1217 | gdb_byte buf[8]; | |
1218 | int instlen, status; | |
1219 | ||
1220 | /* All insns are at least 16 bits. */ | |
1221 | status = target_read_memory (addr, buf, 2); | |
1222 | if (status) | |
1223 | memory_error (TARGET_XFER_E_IO, addr); | |
1224 | ||
1225 | /* If we need more, grab it now. */ | |
1226 | instlen = riscv_insn_length (buf[0]); | |
89a3b63e | 1227 | gdb_assert (instlen <= sizeof (buf)); |
dbbb1059 | 1228 | *len = instlen; |
89a3b63e AB |
1229 | |
1230 | if (instlen > 2) | |
dbbb1059 AB |
1231 | { |
1232 | status = target_read_memory (addr + 2, buf + 2, instlen - 2); | |
1233 | if (status) | |
1234 | memory_error (TARGET_XFER_E_IO, addr + 2); | |
1235 | } | |
1236 | ||
1237 | return extract_unsigned_integer (buf, instlen, byte_order); | |
1238 | } | |
1239 | ||
17cf2897 AB |
1240 | /* Fetch from target memory an instruction at PC and decode it. This can |
1241 | throw an error if the memory access fails, callers are responsible for | |
1242 | handling this error if that is appropriate. */ | |
dbbb1059 AB |
1243 | |
1244 | void | |
1245 | riscv_insn::decode (struct gdbarch *gdbarch, CORE_ADDR pc) | |
1246 | { | |
1247 | ULONGEST ival; | |
1248 | ||
1249 | /* Fetch the instruction, and the instructions length. */ | |
1250 | ival = fetch_instruction (gdbarch, pc, &m_length); | |
1251 | ||
1252 | if (m_length == 4) | |
1253 | { | |
1254 | if (is_add_insn (ival)) | |
1255 | decode_r_type_insn (ADD, ival); | |
1256 | else if (is_addw_insn (ival)) | |
1257 | decode_r_type_insn (ADDW, ival); | |
1258 | else if (is_addi_insn (ival)) | |
1259 | decode_i_type_insn (ADDI, ival); | |
1260 | else if (is_addiw_insn (ival)) | |
1261 | decode_i_type_insn (ADDIW, ival); | |
1262 | else if (is_auipc_insn (ival)) | |
1263 | decode_u_type_insn (AUIPC, ival); | |
1264 | else if (is_lui_insn (ival)) | |
1265 | decode_u_type_insn (LUI, ival); | |
1266 | else if (is_sd_insn (ival)) | |
1267 | decode_s_type_insn (SD, ival); | |
1268 | else if (is_sw_insn (ival)) | |
1269 | decode_s_type_insn (SW, ival); | |
5c720ed8 JW |
1270 | else if (is_jal_insn (ival)) |
1271 | decode_j_type_insn (JAL, ival); | |
1272 | else if (is_jalr_insn (ival)) | |
1273 | decode_i_type_insn (JALR, ival); | |
1274 | else if (is_beq_insn (ival)) | |
1275 | decode_b_type_insn (BEQ, ival); | |
1276 | else if (is_bne_insn (ival)) | |
1277 | decode_b_type_insn (BNE, ival); | |
1278 | else if (is_blt_insn (ival)) | |
1279 | decode_b_type_insn (BLT, ival); | |
1280 | else if (is_bge_insn (ival)) | |
1281 | decode_b_type_insn (BGE, ival); | |
1282 | else if (is_bltu_insn (ival)) | |
1283 | decode_b_type_insn (BLTU, ival); | |
1284 | else if (is_bgeu_insn (ival)) | |
1285 | decode_b_type_insn (BGEU, ival); | |
1286 | else if (is_lr_w_insn (ival)) | |
1287 | decode_r_type_insn (LR, ival); | |
1288 | else if (is_lr_d_insn (ival)) | |
1289 | decode_r_type_insn (LR, ival); | |
1290 | else if (is_sc_w_insn (ival)) | |
1291 | decode_r_type_insn (SC, ival); | |
1292 | else if (is_sc_d_insn (ival)) | |
1293 | decode_r_type_insn (SC, ival); | |
dbbb1059 AB |
1294 | else |
1295 | /* None of the other fields are valid in this case. */ | |
1296 | m_opcode = OTHER; | |
1297 | } | |
1298 | else if (m_length == 2) | |
1299 | { | |
5c720ed8 JW |
1300 | int xlen = riscv_isa_xlen (gdbarch); |
1301 | ||
1302 | /* C_ADD and C_JALR have the same opcode. If RS2 is 0, then this is a | |
1303 | C_JALR. So must try to match C_JALR first as it has more bits in | |
1304 | mask. */ | |
1305 | if (is_c_jalr_insn (ival)) | |
1306 | decode_cr_type_insn (JALR, ival); | |
1307 | else if (is_c_add_insn (ival)) | |
dbbb1059 | 1308 | decode_cr_type_insn (ADD, ival); |
5c720ed8 JW |
1309 | /* C_ADDW is RV64 and RV128 only. */ |
1310 | else if (xlen != 4 && is_c_addw_insn (ival)) | |
dbbb1059 AB |
1311 | decode_cr_type_insn (ADDW, ival); |
1312 | else if (is_c_addi_insn (ival)) | |
1313 | decode_ci_type_insn (ADDI, ival); | |
5c720ed8 JW |
1314 | /* C_ADDIW and C_JAL have the same opcode. C_ADDIW is RV64 and RV128 |
1315 | only and C_JAL is RV32 only. */ | |
1316 | else if (xlen != 4 && is_c_addiw_insn (ival)) | |
dbbb1059 | 1317 | decode_ci_type_insn (ADDIW, ival); |
5c720ed8 JW |
1318 | else if (xlen == 4 && is_c_jal_insn (ival)) |
1319 | decode_cj_type_insn (JAL, ival); | |
1320 | /* C_ADDI16SP and C_LUI have the same opcode. If RD is 2, then this is a | |
1321 | C_ADDI16SP. So must try to match C_ADDI16SP first as it has more bits | |
1322 | in mask. */ | |
dbbb1059 AB |
1323 | else if (is_c_addi16sp_insn (ival)) |
1324 | { | |
1325 | m_opcode = ADDI; | |
1326 | m_rd = m_rs1 = decode_register_index (ival, OP_SH_RD); | |
1327 | m_imm.s = EXTRACT_RVC_ADDI16SP_IMM (ival); | |
1328 | } | |
ff3a05b3 AB |
1329 | else if (is_c_addi4spn_insn (ival)) |
1330 | { | |
1331 | m_opcode = ADDI; | |
1332 | m_rd = decode_register_index_short (ival, OP_SH_CRS2S); | |
1333 | m_rs1 = RISCV_SP_REGNUM; | |
1334 | m_imm.s = EXTRACT_RVC_ADDI4SPN_IMM (ival); | |
1335 | } | |
5c720ed8 | 1336 | else if (is_c_lui_insn (ival)) |
d354055e AB |
1337 | { |
1338 | m_opcode = LUI; | |
1339 | m_rd = decode_register_index (ival, OP_SH_CRS1S); | |
1340 | m_imm.s = EXTRACT_RVC_LUI_IMM (ival); | |
1341 | } | |
5c720ed8 JW |
1342 | /* C_SD and C_FSW have the same opcode. C_SD is RV64 and RV128 only, |
1343 | and C_FSW is RV32 only. */ | |
1344 | else if (xlen != 4 && is_c_sd_insn (ival)) | |
ff3a05b3 | 1345 | decode_cs_type_insn (SD, ival, EXTRACT_RVC_LD_IMM (ival)); |
5c720ed8 | 1346 | else if (is_c_sw_insn (ival)) |
ff3a05b3 AB |
1347 | decode_cs_type_insn (SW, ival, EXTRACT_RVC_LW_IMM (ival)); |
1348 | else if (is_c_swsp_insn (ival)) | |
1349 | decode_css_type_insn (SW, ival, EXTRACT_RVC_SWSP_IMM (ival)); | |
1350 | else if (xlen != 4 && is_c_sdsp_insn (ival)) | |
1351 | decode_css_type_insn (SW, ival, EXTRACT_RVC_SDSP_IMM (ival)); | |
5c720ed8 JW |
1352 | /* C_JR and C_MV have the same opcode. If RS2 is 0, then this is a C_JR. |
1353 | So must try to match C_JR first as it ahs more bits in mask. */ | |
1354 | else if (is_c_jr_insn (ival)) | |
1355 | decode_cr_type_insn (JALR, ival); | |
1356 | else if (is_c_j_insn (ival)) | |
1357 | decode_cj_type_insn (JAL, ival); | |
1358 | else if (is_c_beqz_insn (ival)) | |
1359 | decode_cb_type_insn (BEQ, ival); | |
1360 | else if (is_c_bnez_insn (ival)) | |
1361 | decode_cb_type_insn (BNE, ival); | |
dbbb1059 AB |
1362 | else |
1363 | /* None of the other fields of INSN are valid in this case. */ | |
1364 | m_opcode = OTHER; | |
1365 | } | |
1366 | else | |
312617a3 AB |
1367 | { |
1368 | /* This must be a 6 or 8 byte instruction, we don't currently decode | |
1369 | any of these, so just ignore it. */ | |
1370 | gdb_assert (m_length == 6 || m_length == 8); | |
1371 | m_opcode = OTHER; | |
1372 | } | |
dbbb1059 AB |
1373 | } |
1374 | ||
1375 | /* The prologue scanner. This is currently only used for skipping the | |
1376 | prologue of a function when the DWARF information is not sufficient. | |
1377 | However, it is written with filling of the frame cache in mind, which | |
1378 | is why different groups of stack setup instructions are split apart | |
1379 | during the core of the inner loop. In the future, the intention is to | |
1380 | extend this function to fully support building up a frame cache that | |
1381 | can unwind register values when there is no DWARF information. */ | |
1382 | ||
1383 | static CORE_ADDR | |
1384 | riscv_scan_prologue (struct gdbarch *gdbarch, | |
78a3b0fa AB |
1385 | CORE_ADDR start_pc, CORE_ADDR end_pc, |
1386 | struct riscv_unwind_cache *cache) | |
dbbb1059 | 1387 | { |
78a3b0fa | 1388 | CORE_ADDR cur_pc, next_pc, after_prologue_pc; |
dbbb1059 AB |
1389 | CORE_ADDR end_prologue_addr = 0; |
1390 | ||
78a3b0fa AB |
1391 | /* Find an upper limit on the function prologue using the debug |
1392 | information. If the debug information could not be used to provide | |
1393 | that bound, then use an arbitrary large number as the upper bound. */ | |
1394 | after_prologue_pc = skip_prologue_using_sal (gdbarch, start_pc); | |
1395 | if (after_prologue_pc == 0) | |
1396 | after_prologue_pc = start_pc + 100; /* Arbitrary large number. */ | |
1397 | if (after_prologue_pc < end_pc) | |
1398 | end_pc = after_prologue_pc; | |
1399 | ||
1400 | pv_t regs[RISCV_NUM_INTEGER_REGS]; /* Number of GPR. */ | |
1401 | for (int regno = 0; regno < RISCV_NUM_INTEGER_REGS; regno++) | |
1402 | regs[regno] = pv_register (regno, 0); | |
1403 | pv_area stack (RISCV_SP_REGNUM, gdbarch_addr_bit (gdbarch)); | |
1404 | ||
1405 | if (riscv_debug_unwinder) | |
1406 | fprintf_unfiltered | |
1407 | (gdb_stdlog, | |
1408 | "Prologue scan for function starting at %s (limit %s)\n", | |
1409 | core_addr_to_string (start_pc), | |
1410 | core_addr_to_string (end_pc)); | |
1411 | ||
1412 | for (next_pc = cur_pc = start_pc; cur_pc < end_pc; cur_pc = next_pc) | |
dbbb1059 AB |
1413 | { |
1414 | struct riscv_insn insn; | |
1415 | ||
1416 | /* Decode the current instruction, and decide where the next | |
1417 | instruction lives based on the size of this instruction. */ | |
1418 | insn.decode (gdbarch, cur_pc); | |
1419 | gdb_assert (insn.length () > 0); | |
1420 | next_pc = cur_pc + insn.length (); | |
1421 | ||
1422 | /* Look for common stack adjustment insns. */ | |
1423 | if ((insn.opcode () == riscv_insn::ADDI | |
1424 | || insn.opcode () == riscv_insn::ADDIW) | |
1425 | && insn.rd () == RISCV_SP_REGNUM | |
1426 | && insn.rs1 () == RISCV_SP_REGNUM) | |
1427 | { | |
1428 | /* Handle: addi sp, sp, -i | |
1429 | or: addiw sp, sp, -i */ | |
78a3b0fa AB |
1430 | gdb_assert (insn.rd () < RISCV_NUM_INTEGER_REGS); |
1431 | gdb_assert (insn.rs1 () < RISCV_NUM_INTEGER_REGS); | |
1432 | regs[insn.rd ()] | |
1433 | = pv_add_constant (regs[insn.rs1 ()], insn.imm_signed ()); | |
dbbb1059 AB |
1434 | } |
1435 | else if ((insn.opcode () == riscv_insn::SW | |
1436 | || insn.opcode () == riscv_insn::SD) | |
1437 | && (insn.rs1 () == RISCV_SP_REGNUM | |
1438 | || insn.rs1 () == RISCV_FP_REGNUM)) | |
1439 | { | |
1440 | /* Handle: sw reg, offset(sp) | |
1441 | or: sd reg, offset(sp) | |
1442 | or: sw reg, offset(s0) | |
1443 | or: sd reg, offset(s0) */ | |
1444 | /* Instruction storing a register onto the stack. */ | |
78a3b0fa AB |
1445 | gdb_assert (insn.rs1 () < RISCV_NUM_INTEGER_REGS); |
1446 | gdb_assert (insn.rs2 () < RISCV_NUM_INTEGER_REGS); | |
1447 | stack.store (pv_add_constant (regs[insn.rs1 ()], insn.imm_signed ()), | |
1448 | (insn.opcode () == riscv_insn::SW ? 4 : 8), | |
1449 | regs[insn.rs2 ()]); | |
dbbb1059 AB |
1450 | } |
1451 | else if (insn.opcode () == riscv_insn::ADDI | |
1452 | && insn.rd () == RISCV_FP_REGNUM | |
1453 | && insn.rs1 () == RISCV_SP_REGNUM) | |
1454 | { | |
1455 | /* Handle: addi s0, sp, size */ | |
1456 | /* Instructions setting up the frame pointer. */ | |
78a3b0fa AB |
1457 | gdb_assert (insn.rd () < RISCV_NUM_INTEGER_REGS); |
1458 | gdb_assert (insn.rs1 () < RISCV_NUM_INTEGER_REGS); | |
1459 | regs[insn.rd ()] | |
1460 | = pv_add_constant (regs[insn.rs1 ()], insn.imm_signed ()); | |
dbbb1059 AB |
1461 | } |
1462 | else if ((insn.opcode () == riscv_insn::ADD | |
1463 | || insn.opcode () == riscv_insn::ADDW) | |
1464 | && insn.rd () == RISCV_FP_REGNUM | |
1465 | && insn.rs1 () == RISCV_SP_REGNUM | |
1466 | && insn.rs2 () == RISCV_ZERO_REGNUM) | |
1467 | { | |
1468 | /* Handle: add s0, sp, 0 | |
1469 | or: addw s0, sp, 0 */ | |
1470 | /* Instructions setting up the frame pointer. */ | |
78a3b0fa AB |
1471 | gdb_assert (insn.rd () < RISCV_NUM_INTEGER_REGS); |
1472 | gdb_assert (insn.rs1 () < RISCV_NUM_INTEGER_REGS); | |
1473 | regs[insn.rd ()] = pv_add_constant (regs[insn.rs1 ()], 0); | |
dbbb1059 | 1474 | } |
d354055e AB |
1475 | else if ((insn.opcode () == riscv_insn::ADDI |
1476 | && insn.rd () == RISCV_ZERO_REGNUM | |
1477 | && insn.rs1 () == RISCV_ZERO_REGNUM | |
1478 | && insn.imm_signed () == 0)) | |
dbbb1059 | 1479 | { |
d354055e | 1480 | /* Handle: add x0, x0, 0 (NOP) */ |
dbbb1059 | 1481 | } |
d354055e AB |
1482 | else if (insn.opcode () == riscv_insn::AUIPC) |
1483 | { | |
1484 | gdb_assert (insn.rd () < RISCV_NUM_INTEGER_REGS); | |
1485 | regs[insn.rd ()] = pv_constant (cur_pc + insn.imm_signed ()); | |
1486 | } | |
1487 | else if (insn.opcode () == riscv_insn::LUI) | |
1488 | { | |
1489 | /* Handle: lui REG, n | |
1490 | Where REG is not gp register. */ | |
1491 | gdb_assert (insn.rd () < RISCV_NUM_INTEGER_REGS); | |
1492 | regs[insn.rd ()] = pv_constant (insn.imm_signed ()); | |
1493 | } | |
1494 | else if (insn.opcode () == riscv_insn::ADDI) | |
1495 | { | |
1496 | /* Handle: addi REG1, REG2, IMM */ | |
1497 | gdb_assert (insn.rd () < RISCV_NUM_INTEGER_REGS); | |
1498 | gdb_assert (insn.rs1 () < RISCV_NUM_INTEGER_REGS); | |
1499 | regs[insn.rd ()] | |
1500 | = pv_add_constant (regs[insn.rs1 ()], insn.imm_signed ()); | |
1501 | } | |
1502 | else if (insn.opcode () == riscv_insn::ADD) | |
1503 | { | |
1504 | /* Handle: addi REG1, REG2, IMM */ | |
1505 | gdb_assert (insn.rd () < RISCV_NUM_INTEGER_REGS); | |
1506 | gdb_assert (insn.rs1 () < RISCV_NUM_INTEGER_REGS); | |
1507 | gdb_assert (insn.rs2 () < RISCV_NUM_INTEGER_REGS); | |
1508 | regs[insn.rd ()] = pv_add (regs[insn.rs1 ()], regs[insn.rs2 ()]); | |
1509 | } | |
dbbb1059 AB |
1510 | else |
1511 | { | |
78a3b0fa AB |
1512 | end_prologue_addr = cur_pc; |
1513 | break; | |
dbbb1059 AB |
1514 | } |
1515 | } | |
1516 | ||
1517 | if (end_prologue_addr == 0) | |
1518 | end_prologue_addr = cur_pc; | |
1519 | ||
78a3b0fa AB |
1520 | if (riscv_debug_unwinder) |
1521 | fprintf_unfiltered (gdb_stdlog, "End of prologue at %s\n", | |
1522 | core_addr_to_string (end_prologue_addr)); | |
1523 | ||
1524 | if (cache != NULL) | |
1525 | { | |
1526 | /* Figure out if it is a frame pointer or just a stack pointer. Also | |
1527 | the offset held in the pv_t is from the original register value to | |
1528 | the current value, which for a grows down stack means a negative | |
1529 | value. The FRAME_BASE_OFFSET is the negation of this, how to get | |
1530 | from the current value to the original value. */ | |
1531 | if (pv_is_register (regs[RISCV_FP_REGNUM], RISCV_SP_REGNUM)) | |
1532 | { | |
1533 | cache->frame_base_reg = RISCV_FP_REGNUM; | |
1534 | cache->frame_base_offset = -regs[RISCV_FP_REGNUM].k; | |
1535 | } | |
1536 | else | |
1537 | { | |
1538 | cache->frame_base_reg = RISCV_SP_REGNUM; | |
1539 | cache->frame_base_offset = -regs[RISCV_SP_REGNUM].k; | |
1540 | } | |
1541 | ||
1542 | /* Assign offset from old SP to all saved registers. As we don't | |
1543 | have the previous value for the frame base register at this | |
1544 | point, we store the offset as the address in the trad_frame, and | |
1545 | then convert this to an actual address later. */ | |
1546 | for (int i = 0; i <= RISCV_NUM_INTEGER_REGS; i++) | |
1547 | { | |
1548 | CORE_ADDR offset; | |
1549 | if (stack.find_reg (gdbarch, i, &offset)) | |
1550 | { | |
1551 | if (riscv_debug_unwinder) | |
a96bd1cc AB |
1552 | { |
1553 | /* Display OFFSET as a signed value, the offsets are from | |
1554 | the frame base address to the registers location on | |
1555 | the stack, with a descending stack this means the | |
1556 | offsets are always negative. */ | |
1557 | fprintf_unfiltered (gdb_stdlog, | |
1558 | "Register $%s at stack offset %s\n", | |
1559 | gdbarch_register_name (gdbarch, i), | |
1560 | plongest ((LONGEST) offset)); | |
1561 | } | |
78a3b0fa AB |
1562 | trad_frame_set_addr (cache->regs, i, offset); |
1563 | } | |
1564 | } | |
1565 | } | |
1566 | ||
dbbb1059 AB |
1567 | return end_prologue_addr; |
1568 | } | |
1569 | ||
1570 | /* Implement the riscv_skip_prologue gdbarch method. */ | |
1571 | ||
1572 | static CORE_ADDR | |
78a3b0fa | 1573 | riscv_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc) |
dbbb1059 | 1574 | { |
dbbb1059 AB |
1575 | CORE_ADDR func_addr; |
1576 | ||
1577 | /* See if we can determine the end of the prologue via the symbol | |
1578 | table. If so, then return either PC, or the PC after the | |
1579 | prologue, whichever is greater. */ | |
1580 | if (find_pc_partial_function (pc, NULL, &func_addr, NULL)) | |
1581 | { | |
1582 | CORE_ADDR post_prologue_pc | |
1583 | = skip_prologue_using_sal (gdbarch, func_addr); | |
1584 | ||
1585 | if (post_prologue_pc != 0) | |
1586 | return std::max (pc, post_prologue_pc); | |
1587 | } | |
1588 | ||
1589 | /* Can't determine prologue from the symbol table, need to examine | |
78a3b0fa AB |
1590 | instructions. Pass -1 for the end address to indicate the prologue |
1591 | scanner can scan as far as it needs to find the end of the prologue. */ | |
1592 | return riscv_scan_prologue (gdbarch, pc, ((CORE_ADDR) -1), NULL); | |
dbbb1059 AB |
1593 | } |
1594 | ||
1595 | /* Implement the gdbarch push dummy code callback. */ | |
1596 | ||
1597 | static CORE_ADDR | |
1598 | riscv_push_dummy_code (struct gdbarch *gdbarch, CORE_ADDR sp, | |
1599 | CORE_ADDR funaddr, struct value **args, int nargs, | |
1600 | struct type *value_type, CORE_ADDR *real_pc, | |
1601 | CORE_ADDR *bp_addr, struct regcache *regcache) | |
1602 | { | |
01e175fe AB |
1603 | /* A nop instruction is 'add x0, x0, 0'. */ |
1604 | static const gdb_byte nop_insn[] = { 0x13, 0x00, 0x00, 0x00 }; | |
1605 | ||
dbbb1059 | 1606 | /* Allocate space for a breakpoint, and keep the stack correctly |
01e175fe AB |
1607 | aligned. The space allocated here must be at least big enough to |
1608 | accommodate the NOP_INSN defined above. */ | |
dbbb1059 AB |
1609 | sp -= 16; |
1610 | *bp_addr = sp; | |
1611 | *real_pc = funaddr; | |
01e175fe AB |
1612 | |
1613 | /* When we insert a breakpoint we select whether to use a compressed | |
1614 | breakpoint or not based on the existing contents of the memory. | |
1615 | ||
1616 | If the breakpoint is being placed onto the stack as part of setting up | |
1617 | for an inferior call from GDB, then the existing stack contents may | |
1618 | randomly appear to be a compressed instruction, causing GDB to insert | |
1619 | a compressed breakpoint. If this happens on a target that does not | |
1620 | support compressed instructions then this could cause problems. | |
1621 | ||
1622 | To prevent this issue we write an uncompressed nop onto the stack at | |
1623 | the location where the breakpoint will be inserted. In this way we | |
1624 | ensure that we always use an uncompressed breakpoint, which should | |
1625 | work on all targets. | |
1626 | ||
1627 | We call TARGET_WRITE_MEMORY here so that if the write fails we don't | |
1628 | throw an exception. Instead we ignore the error and move on. The | |
1629 | assumption is that either GDB will error later when actually trying to | |
1630 | insert a software breakpoint, or GDB will use hardware breakpoints and | |
1631 | there will be no need to write to memory later. */ | |
1632 | int status = target_write_memory (*bp_addr, nop_insn, sizeof (nop_insn)); | |
1633 | ||
1634 | if (riscv_debug_breakpoints || riscv_debug_infcall) | |
1635 | fprintf_unfiltered (gdb_stdlog, | |
a83d4ef6 JW |
1636 | "Writing %s-byte nop instruction to %s: %s\n", |
1637 | plongest (sizeof (nop_insn)), | |
01e175fe AB |
1638 | paddress (gdbarch, *bp_addr), |
1639 | (status == 0 ? "success" : "failed")); | |
1640 | ||
dbbb1059 AB |
1641 | return sp; |
1642 | } | |
1643 | ||
a9158a86 AB |
1644 | /* Implement the gdbarch type alignment method, overrides the generic |
1645 | alignment algorithm for anything that is RISC-V specific. */ | |
dbbb1059 | 1646 | |
a9158a86 AB |
1647 | static ULONGEST |
1648 | riscv_type_align (gdbarch *gdbarch, type *type) | |
dbbb1059 | 1649 | { |
a9158a86 | 1650 | type = check_typedef (type); |
78134374 | 1651 | if (type->code () == TYPE_CODE_ARRAY && TYPE_VECTOR (type)) |
a9158a86 | 1652 | return std::min (TYPE_LENGTH (type), (ULONGEST) BIGGEST_ALIGNMENT); |
dbbb1059 | 1653 | |
a9158a86 AB |
1654 | /* Anything else will be aligned by the generic code. */ |
1655 | return 0; | |
dbbb1059 AB |
1656 | } |
1657 | ||
1658 | /* Holds information about a single argument either being passed to an | |
1659 | inferior function, or returned from an inferior function. This includes | |
1660 | information about the size, type, etc of the argument, and also | |
1661 | information about how the argument will be passed (or returned). */ | |
1662 | ||
1663 | struct riscv_arg_info | |
1664 | { | |
1665 | /* Contents of the argument. */ | |
1666 | const gdb_byte *contents; | |
1667 | ||
1668 | /* Length of argument. */ | |
1669 | int length; | |
1670 | ||
1671 | /* Alignment required for an argument of this type. */ | |
1672 | int align; | |
1673 | ||
1674 | /* The type for this argument. */ | |
1675 | struct type *type; | |
1676 | ||
1677 | /* Each argument can have either 1 or 2 locations assigned to it. Each | |
1678 | location describes where part of the argument will be placed. The | |
1679 | second location is valid based on the LOC_TYPE and C_LENGTH fields | |
1680 | of the first location (which is always valid). */ | |
1681 | struct location | |
1682 | { | |
1683 | /* What type of location this is. */ | |
1684 | enum location_type | |
1685 | { | |
1686 | /* Argument passed in a register. */ | |
1687 | in_reg, | |
1688 | ||
1689 | /* Argument passed as an on stack argument. */ | |
1690 | on_stack, | |
1691 | ||
1692 | /* Argument passed by reference. The second location is always | |
1693 | valid for a BY_REF argument, and describes where the address | |
1694 | of the BY_REF argument should be placed. */ | |
1695 | by_ref | |
1696 | } loc_type; | |
1697 | ||
1698 | /* Information that depends on the location type. */ | |
1699 | union | |
1700 | { | |
1701 | /* Which register number to use. */ | |
1702 | int regno; | |
1703 | ||
1704 | /* The offset into the stack region. */ | |
1705 | int offset; | |
1706 | } loc_data; | |
1707 | ||
1708 | /* The length of contents covered by this location. If this is less | |
1709 | than the total length of the argument, then the second location | |
1710 | will be valid, and will describe where the rest of the argument | |
1711 | will go. */ | |
1712 | int c_length; | |
1713 | ||
dd895392 AB |
1714 | /* The offset within CONTENTS for this part of the argument. This can |
1715 | be non-zero even for the first part (the first field of a struct can | |
1716 | have a non-zero offset due to padding). For the second part of the | |
dbbb1059 AB |
1717 | argument, this might be the C_LENGTH value of the first part, |
1718 | however, if we are passing a structure in two registers, and there's | |
1719 | is padding between the first and second field, then this offset | |
1720 | might be greater than the length of the first argument part. When | |
1721 | the second argument location is not holding part of the argument | |
1722 | value, but is instead holding the address of a reference argument, | |
1723 | then this offset will be set to 0. */ | |
1724 | int c_offset; | |
1725 | } argloc[2]; | |
8b2d40cb JW |
1726 | |
1727 | /* TRUE if this is an unnamed argument. */ | |
1728 | bool is_unnamed; | |
dbbb1059 AB |
1729 | }; |
1730 | ||
1731 | /* Information about a set of registers being used for passing arguments as | |
1732 | part of a function call. The register set must be numerically | |
1733 | sequential from NEXT_REGNUM to LAST_REGNUM. The register set can be | |
1734 | disabled from use by setting NEXT_REGNUM greater than LAST_REGNUM. */ | |
1735 | ||
1736 | struct riscv_arg_reg | |
1737 | { | |
1738 | riscv_arg_reg (int first, int last) | |
1739 | : next_regnum (first), | |
1740 | last_regnum (last) | |
1741 | { | |
1742 | /* Nothing. */ | |
1743 | } | |
1744 | ||
1745 | /* The GDB register number to use in this set. */ | |
1746 | int next_regnum; | |
1747 | ||
1748 | /* The last GDB register number to use in this set. */ | |
1749 | int last_regnum; | |
1750 | }; | |
1751 | ||
1752 | /* Arguments can be passed as on stack arguments, or by reference. The | |
1753 | on stack arguments must be in a continuous region starting from $sp, | |
1754 | while the by reference arguments can be anywhere, but we'll put them | |
1755 | on the stack after (at higher address) the on stack arguments. | |
1756 | ||
1757 | This might not be the right approach to take. The ABI is clear that | |
1758 | an argument passed by reference can be modified by the callee, which | |
1759 | us placing the argument (temporarily) onto the stack will not achieve | |
1760 | (changes will be lost). There's also the possibility that very large | |
1761 | arguments could overflow the stack. | |
1762 | ||
1763 | This struct is used to track offset into these two areas for where | |
1764 | arguments are to be placed. */ | |
1765 | struct riscv_memory_offsets | |
1766 | { | |
1767 | riscv_memory_offsets () | |
1768 | : arg_offset (0), | |
1769 | ref_offset (0) | |
1770 | { | |
1771 | /* Nothing. */ | |
1772 | } | |
1773 | ||
1774 | /* Offset into on stack argument area. */ | |
1775 | int arg_offset; | |
1776 | ||
1777 | /* Offset into the pass by reference area. */ | |
1778 | int ref_offset; | |
1779 | }; | |
1780 | ||
1781 | /* Holds information about where arguments to a call will be placed. This | |
1782 | is updated as arguments are added onto the call, and can be used to | |
1783 | figure out where the next argument should be placed. */ | |
1784 | ||
1785 | struct riscv_call_info | |
1786 | { | |
1787 | riscv_call_info (struct gdbarch *gdbarch) | |
1788 | : int_regs (RISCV_A0_REGNUM, RISCV_A0_REGNUM + 7), | |
1789 | float_regs (RISCV_FA0_REGNUM, RISCV_FA0_REGNUM + 7) | |
1790 | { | |
113b7b81 AB |
1791 | xlen = riscv_abi_xlen (gdbarch); |
1792 | flen = riscv_abi_flen (gdbarch); | |
dbbb1059 AB |
1793 | |
1794 | /* Disable use of floating point registers if needed. */ | |
1795 | if (!riscv_has_fp_abi (gdbarch)) | |
1796 | float_regs.next_regnum = float_regs.last_regnum + 1; | |
1797 | } | |
1798 | ||
1799 | /* Track the memory areas used for holding in-memory arguments to a | |
1800 | call. */ | |
1801 | struct riscv_memory_offsets memory; | |
1802 | ||
1803 | /* Holds information about the next integer register to use for passing | |
1804 | an argument. */ | |
1805 | struct riscv_arg_reg int_regs; | |
1806 | ||
1807 | /* Holds information about the next floating point register to use for | |
1808 | passing an argument. */ | |
1809 | struct riscv_arg_reg float_regs; | |
1810 | ||
1811 | /* The XLEN and FLEN are copied in to this structure for convenience, and | |
113b7b81 | 1812 | are just the results of calling RISCV_ABI_XLEN and RISCV_ABI_FLEN. */ |
dbbb1059 AB |
1813 | int xlen; |
1814 | int flen; | |
1815 | }; | |
1816 | ||
1817 | /* Return the number of registers available for use as parameters in the | |
1818 | register set REG. Returned value can be 0 or more. */ | |
1819 | ||
1820 | static int | |
1821 | riscv_arg_regs_available (struct riscv_arg_reg *reg) | |
1822 | { | |
1823 | if (reg->next_regnum > reg->last_regnum) | |
1824 | return 0; | |
1825 | ||
1826 | return (reg->last_regnum - reg->next_regnum + 1); | |
1827 | } | |
1828 | ||
1829 | /* If there is at least one register available in the register set REG then | |
1830 | the next register from REG is assigned to LOC and the length field of | |
1831 | LOC is updated to LENGTH. The register set REG is updated to indicate | |
1832 | that the assigned register is no longer available and the function | |
1833 | returns true. | |
1834 | ||
1835 | If there are no registers available in REG then the function returns | |
1836 | false, and LOC and REG are unchanged. */ | |
1837 | ||
1838 | static bool | |
1839 | riscv_assign_reg_location (struct riscv_arg_info::location *loc, | |
1840 | struct riscv_arg_reg *reg, | |
1841 | int length, int offset) | |
1842 | { | |
1843 | if (reg->next_regnum <= reg->last_regnum) | |
1844 | { | |
1845 | loc->loc_type = riscv_arg_info::location::in_reg; | |
1846 | loc->loc_data.regno = reg->next_regnum; | |
1847 | reg->next_regnum++; | |
1848 | loc->c_length = length; | |
1849 | loc->c_offset = offset; | |
1850 | return true; | |
1851 | } | |
1852 | ||
1853 | return false; | |
1854 | } | |
1855 | ||
1856 | /* Assign LOC a location as the next stack parameter, and update MEMORY to | |
1857 | record that an area of stack has been used to hold the parameter | |
1858 | described by LOC. | |
1859 | ||
1860 | The length field of LOC is updated to LENGTH, the length of the | |
1861 | parameter being stored, and ALIGN is the alignment required by the | |
1862 | parameter, which will affect how memory is allocated out of MEMORY. */ | |
1863 | ||
1864 | static void | |
1865 | riscv_assign_stack_location (struct riscv_arg_info::location *loc, | |
1866 | struct riscv_memory_offsets *memory, | |
1867 | int length, int align) | |
1868 | { | |
1869 | loc->loc_type = riscv_arg_info::location::on_stack; | |
1870 | memory->arg_offset | |
1871 | = align_up (memory->arg_offset, align); | |
1872 | loc->loc_data.offset = memory->arg_offset; | |
1873 | memory->arg_offset += length; | |
1874 | loc->c_length = length; | |
1875 | ||
1876 | /* Offset is always 0, either we're the first location part, in which | |
1877 | case we're reading content from the start of the argument, or we're | |
1878 | passing the address of a reference argument, so 0. */ | |
1879 | loc->c_offset = 0; | |
1880 | } | |
1881 | ||
1882 | /* Update AINFO, which describes an argument that should be passed or | |
1883 | returned using the integer ABI. The argloc fields within AINFO are | |
1884 | updated to describe the location in which the argument will be passed to | |
1885 | a function, or returned from a function. | |
1886 | ||
1887 | The CINFO structure contains the ongoing call information, the holds | |
1888 | information such as which argument registers are remaining to be | |
1889 | assigned to parameter, and how much memory has been used by parameters | |
1890 | so far. | |
1891 | ||
1892 | By examining the state of CINFO a suitable location can be selected, | |
1893 | and assigned to AINFO. */ | |
1894 | ||
1895 | static void | |
1896 | riscv_call_arg_scalar_int (struct riscv_arg_info *ainfo, | |
1897 | struct riscv_call_info *cinfo) | |
1898 | { | |
1899 | if (ainfo->length > (2 * cinfo->xlen)) | |
1900 | { | |
1901 | /* Argument is going to be passed by reference. */ | |
1902 | ainfo->argloc[0].loc_type | |
1903 | = riscv_arg_info::location::by_ref; | |
1904 | cinfo->memory.ref_offset | |
1905 | = align_up (cinfo->memory.ref_offset, ainfo->align); | |
1906 | ainfo->argloc[0].loc_data.offset = cinfo->memory.ref_offset; | |
1907 | cinfo->memory.ref_offset += ainfo->length; | |
1908 | ainfo->argloc[0].c_length = ainfo->length; | |
1909 | ||
1910 | /* The second location for this argument is given over to holding the | |
1911 | address of the by-reference data. Pass 0 for the offset as this | |
1912 | is not part of the actual argument value. */ | |
1913 | if (!riscv_assign_reg_location (&ainfo->argloc[1], | |
1914 | &cinfo->int_regs, | |
1915 | cinfo->xlen, 0)) | |
1916 | riscv_assign_stack_location (&ainfo->argloc[1], | |
1917 | &cinfo->memory, cinfo->xlen, | |
1918 | cinfo->xlen); | |
1919 | } | |
1920 | else | |
1921 | { | |
174f8ac8 JW |
1922 | int len = std::min (ainfo->length, cinfo->xlen); |
1923 | int align = std::max (ainfo->align, cinfo->xlen); | |
dbbb1059 | 1924 | |
8b2d40cb JW |
1925 | /* Unnamed arguments in registers that require 2*XLEN alignment are |
1926 | passed in an aligned register pair. */ | |
1927 | if (ainfo->is_unnamed && (align == cinfo->xlen * 2) | |
1928 | && cinfo->int_regs.next_regnum & 1) | |
1929 | cinfo->int_regs.next_regnum++; | |
1930 | ||
dbbb1059 AB |
1931 | if (!riscv_assign_reg_location (&ainfo->argloc[0], |
1932 | &cinfo->int_regs, len, 0)) | |
1933 | riscv_assign_stack_location (&ainfo->argloc[0], | |
174f8ac8 | 1934 | &cinfo->memory, len, align); |
dbbb1059 AB |
1935 | |
1936 | if (len < ainfo->length) | |
1937 | { | |
1938 | len = ainfo->length - len; | |
1939 | if (!riscv_assign_reg_location (&ainfo->argloc[1], | |
1940 | &cinfo->int_regs, len, | |
1941 | cinfo->xlen)) | |
1942 | riscv_assign_stack_location (&ainfo->argloc[1], | |
1943 | &cinfo->memory, len, cinfo->xlen); | |
1944 | } | |
1945 | } | |
1946 | } | |
1947 | ||
1948 | /* Like RISCV_CALL_ARG_SCALAR_INT, except the argument described by AINFO | |
1949 | is being passed with the floating point ABI. */ | |
1950 | ||
1951 | static void | |
1952 | riscv_call_arg_scalar_float (struct riscv_arg_info *ainfo, | |
1953 | struct riscv_call_info *cinfo) | |
1954 | { | |
4de3d8d0 | 1955 | if (ainfo->length > cinfo->flen || ainfo->is_unnamed) |
dbbb1059 AB |
1956 | return riscv_call_arg_scalar_int (ainfo, cinfo); |
1957 | else | |
1958 | { | |
1959 | if (!riscv_assign_reg_location (&ainfo->argloc[0], | |
1960 | &cinfo->float_regs, | |
1961 | ainfo->length, 0)) | |
1962 | return riscv_call_arg_scalar_int (ainfo, cinfo); | |
1963 | } | |
1964 | } | |
1965 | ||
1966 | /* Like RISCV_CALL_ARG_SCALAR_INT, except the argument described by AINFO | |
1967 | is a complex floating point argument, and is therefore handled | |
1968 | differently to other argument types. */ | |
1969 | ||
1970 | static void | |
1971 | riscv_call_arg_complex_float (struct riscv_arg_info *ainfo, | |
1972 | struct riscv_call_info *cinfo) | |
1973 | { | |
1974 | if (ainfo->length <= (2 * cinfo->flen) | |
4de3d8d0 AB |
1975 | && riscv_arg_regs_available (&cinfo->float_regs) >= 2 |
1976 | && !ainfo->is_unnamed) | |
dbbb1059 AB |
1977 | { |
1978 | bool result; | |
1979 | int len = ainfo->length / 2; | |
1980 | ||
1981 | result = riscv_assign_reg_location (&ainfo->argloc[0], | |
9f0272f8 | 1982 | &cinfo->float_regs, len, 0); |
dbbb1059 AB |
1983 | gdb_assert (result); |
1984 | ||
1985 | result = riscv_assign_reg_location (&ainfo->argloc[1], | |
1986 | &cinfo->float_regs, len, len); | |
1987 | gdb_assert (result); | |
1988 | } | |
1989 | else | |
1990 | return riscv_call_arg_scalar_int (ainfo, cinfo); | |
1991 | } | |
1992 | ||
1993 | /* A structure used for holding information about a structure type within | |
1994 | the inferior program. The RiscV ABI has special rules for handling some | |
1995 | structures with a single field or with two fields. The counting of | |
1996 | fields here is done after flattening out all nested structures. */ | |
1997 | ||
1998 | class riscv_struct_info | |
1999 | { | |
2000 | public: | |
2001 | riscv_struct_info () | |
2002 | : m_number_of_fields (0), | |
9f0272f8 AB |
2003 | m_types { nullptr, nullptr }, |
2004 | m_offsets { 0, 0 } | |
dbbb1059 AB |
2005 | { |
2006 | /* Nothing. */ | |
2007 | } | |
2008 | ||
2009 | /* Analyse TYPE descending into nested structures, count the number of | |
2010 | scalar fields and record the types of the first two fields found. */ | |
9f0272f8 AB |
2011 | void analyse (struct type *type) |
2012 | { | |
2013 | analyse_inner (type, 0); | |
2014 | } | |
dbbb1059 AB |
2015 | |
2016 | /* The number of scalar fields found in the analysed type. This is | |
2017 | currently only accurate if the value returned is 0, 1, or 2 as the | |
2018 | analysis stops counting when the number of fields is 3. This is | |
2019 | because the RiscV ABI only has special cases for 1 or 2 fields, | |
2020 | anything else we just don't care about. */ | |
2021 | int number_of_fields () const | |
2022 | { return m_number_of_fields; } | |
2023 | ||
2024 | /* Return the type for scalar field INDEX within the analysed type. Will | |
2025 | return nullptr if there is no field at that index. Only INDEX values | |
2026 | 0 and 1 can be requested as the RiscV ABI only has special cases for | |
2027 | structures with 1 or 2 fields. */ | |
2028 | struct type *field_type (int index) const | |
2029 | { | |
2030 | gdb_assert (index < (sizeof (m_types) / sizeof (m_types[0]))); | |
2031 | return m_types[index]; | |
2032 | } | |
2033 | ||
9f0272f8 AB |
2034 | /* Return the offset of scalar field INDEX within the analysed type. Will |
2035 | return 0 if there is no field at that index. Only INDEX values 0 and | |
2036 | 1 can be requested as the RiscV ABI only has special cases for | |
2037 | structures with 1 or 2 fields. */ | |
2038 | int field_offset (int index) const | |
2039 | { | |
2040 | gdb_assert (index < (sizeof (m_offsets) / sizeof (m_offsets[0]))); | |
2041 | return m_offsets[index]; | |
2042 | } | |
2043 | ||
dbbb1059 AB |
2044 | private: |
2045 | /* The number of scalar fields found within the structure after recursing | |
2046 | into nested structures. */ | |
2047 | int m_number_of_fields; | |
2048 | ||
2049 | /* The types of the first two scalar fields found within the structure | |
2050 | after recursing into nested structures. */ | |
2051 | struct type *m_types[2]; | |
9f0272f8 AB |
2052 | |
2053 | /* The offsets of the first two scalar fields found within the structure | |
2054 | after recursing into nested structures. */ | |
2055 | int m_offsets[2]; | |
2056 | ||
2057 | /* Recursive core for ANALYSE, the OFFSET parameter tracks the byte | |
2058 | offset from the start of the top level structure being analysed. */ | |
2059 | void analyse_inner (struct type *type, int offset); | |
dbbb1059 AB |
2060 | }; |
2061 | ||
9f0272f8 | 2062 | /* See description in class declaration. */ |
dbbb1059 AB |
2063 | |
2064 | void | |
9f0272f8 | 2065 | riscv_struct_info::analyse_inner (struct type *type, int offset) |
dbbb1059 | 2066 | { |
1f704f76 | 2067 | unsigned int count = type->num_fields (); |
dbbb1059 AB |
2068 | unsigned int i; |
2069 | ||
2070 | for (i = 0; i < count; ++i) | |
2071 | { | |
2072 | if (TYPE_FIELD_LOC_KIND (type, i) != FIELD_LOC_KIND_BITPOS) | |
2073 | continue; | |
2074 | ||
940da03e | 2075 | struct type *field_type = type->field (i).type (); |
dbbb1059 | 2076 | field_type = check_typedef (field_type); |
9f0272f8 AB |
2077 | int field_offset |
2078 | = offset + TYPE_FIELD_BITPOS (type, i) / TARGET_CHAR_BIT; | |
dbbb1059 | 2079 | |
78134374 | 2080 | switch (field_type->code ()) |
dbbb1059 AB |
2081 | { |
2082 | case TYPE_CODE_STRUCT: | |
9f0272f8 | 2083 | analyse_inner (field_type, field_offset); |
dbbb1059 AB |
2084 | break; |
2085 | ||
2086 | default: | |
2087 | /* RiscV only flattens out structures. Anything else does not | |
2088 | need to be flattened, we just record the type, and when we | |
2089 | look at the analysis results we'll realise this is not a | |
2090 | structure we can special case, and pass the structure in | |
2091 | memory. */ | |
2092 | if (m_number_of_fields < 2) | |
9f0272f8 AB |
2093 | { |
2094 | m_types[m_number_of_fields] = field_type; | |
2095 | m_offsets[m_number_of_fields] = field_offset; | |
2096 | } | |
dbbb1059 AB |
2097 | m_number_of_fields++; |
2098 | break; | |
2099 | } | |
2100 | ||
2101 | /* RiscV only has special handling for structures with 1 or 2 scalar | |
2102 | fields, any more than that and the structure is just passed in | |
2103 | memory. We can safely drop out early when we find 3 or more | |
2104 | fields then. */ | |
2105 | ||
2106 | if (m_number_of_fields > 2) | |
2107 | return; | |
2108 | } | |
2109 | } | |
2110 | ||
2111 | /* Like RISCV_CALL_ARG_SCALAR_INT, except the argument described by AINFO | |
2112 | is a structure. Small structures on RiscV have some special case | |
2113 | handling in order that the structure might be passed in register. | |
2114 | Larger structures are passed in memory. After assigning location | |
2115 | information to AINFO, CINFO will have been updated. */ | |
2116 | ||
2117 | static void | |
2118 | riscv_call_arg_struct (struct riscv_arg_info *ainfo, | |
2119 | struct riscv_call_info *cinfo) | |
2120 | { | |
2121 | if (riscv_arg_regs_available (&cinfo->float_regs) >= 1) | |
2122 | { | |
2123 | struct riscv_struct_info sinfo; | |
2124 | ||
2125 | sinfo.analyse (ainfo->type); | |
2126 | if (sinfo.number_of_fields () == 1 | |
78134374 | 2127 | && sinfo.field_type(0)->code () == TYPE_CODE_COMPLEX) |
dbbb1059 | 2128 | { |
9f0272f8 AB |
2129 | /* The following is similar to RISCV_CALL_ARG_COMPLEX_FLOAT, |
2130 | except we use the type of the complex field instead of the | |
2131 | type from AINFO, and the first location might be at a non-zero | |
2132 | offset. */ | |
2133 | if (TYPE_LENGTH (sinfo.field_type (0)) <= (2 * cinfo->flen) | |
2134 | && riscv_arg_regs_available (&cinfo->float_regs) >= 2 | |
2135 | && !ainfo->is_unnamed) | |
2136 | { | |
2137 | bool result; | |
2138 | int len = TYPE_LENGTH (sinfo.field_type (0)) / 2; | |
2139 | int offset = sinfo.field_offset (0); | |
2140 | ||
2141 | result = riscv_assign_reg_location (&ainfo->argloc[0], | |
2142 | &cinfo->float_regs, len, | |
2143 | offset); | |
2144 | gdb_assert (result); | |
2145 | ||
2146 | result = riscv_assign_reg_location (&ainfo->argloc[1], | |
2147 | &cinfo->float_regs, len, | |
2148 | (offset + len)); | |
2149 | gdb_assert (result); | |
2150 | } | |
2151 | else | |
2152 | riscv_call_arg_scalar_int (ainfo, cinfo); | |
2153 | return; | |
dbbb1059 AB |
2154 | } |
2155 | ||
2156 | if (sinfo.number_of_fields () == 1 | |
78134374 | 2157 | && sinfo.field_type(0)->code () == TYPE_CODE_FLT) |
dbbb1059 | 2158 | { |
9f0272f8 AB |
2159 | /* The following is similar to RISCV_CALL_ARG_SCALAR_FLOAT, |
2160 | except we use the type of the first scalar field instead of | |
2161 | the type from AINFO. Also the location might be at a non-zero | |
2162 | offset. */ | |
2163 | if (TYPE_LENGTH (sinfo.field_type (0)) > cinfo->flen | |
2164 | || ainfo->is_unnamed) | |
2165 | riscv_call_arg_scalar_int (ainfo, cinfo); | |
2166 | else | |
2167 | { | |
2168 | int offset = sinfo.field_offset (0); | |
2169 | int len = TYPE_LENGTH (sinfo.field_type (0)); | |
2170 | ||
2171 | if (!riscv_assign_reg_location (&ainfo->argloc[0], | |
2172 | &cinfo->float_regs, | |
2173 | len, offset)) | |
2174 | riscv_call_arg_scalar_int (ainfo, cinfo); | |
2175 | } | |
2176 | return; | |
dbbb1059 AB |
2177 | } |
2178 | ||
2179 | if (sinfo.number_of_fields () == 2 | |
78134374 | 2180 | && sinfo.field_type(0)->code () == TYPE_CODE_FLT |
dbbb1059 | 2181 | && TYPE_LENGTH (sinfo.field_type (0)) <= cinfo->flen |
78134374 | 2182 | && sinfo.field_type(1)->code () == TYPE_CODE_FLT |
dbbb1059 AB |
2183 | && TYPE_LENGTH (sinfo.field_type (1)) <= cinfo->flen |
2184 | && riscv_arg_regs_available (&cinfo->float_regs) >= 2) | |
2185 | { | |
9f0272f8 AB |
2186 | int len0 = TYPE_LENGTH (sinfo.field_type (0)); |
2187 | int offset = sinfo.field_offset (0); | |
dbbb1059 | 2188 | if (!riscv_assign_reg_location (&ainfo->argloc[0], |
9f0272f8 | 2189 | &cinfo->float_regs, len0, offset)) |
dbbb1059 AB |
2190 | error (_("failed during argument setup")); |
2191 | ||
9f0272f8 AB |
2192 | int len1 = TYPE_LENGTH (sinfo.field_type (1)); |
2193 | offset = sinfo.field_offset (1); | |
dbbb1059 AB |
2194 | gdb_assert (len1 <= (TYPE_LENGTH (ainfo->type) |
2195 | - TYPE_LENGTH (sinfo.field_type (0)))); | |
2196 | ||
2197 | if (!riscv_assign_reg_location (&ainfo->argloc[1], | |
2198 | &cinfo->float_regs, | |
2199 | len1, offset)) | |
2200 | error (_("failed during argument setup")); | |
2201 | return; | |
2202 | } | |
2203 | ||
2204 | if (sinfo.number_of_fields () == 2 | |
2205 | && riscv_arg_regs_available (&cinfo->int_regs) >= 1 | |
78134374 | 2206 | && (sinfo.field_type(0)->code () == TYPE_CODE_FLT |
dbbb1059 AB |
2207 | && TYPE_LENGTH (sinfo.field_type (0)) <= cinfo->flen |
2208 | && is_integral_type (sinfo.field_type (1)) | |
2209 | && TYPE_LENGTH (sinfo.field_type (1)) <= cinfo->xlen)) | |
2210 | { | |
9f0272f8 AB |
2211 | int len0 = TYPE_LENGTH (sinfo.field_type (0)); |
2212 | int offset = sinfo.field_offset (0); | |
dbbb1059 | 2213 | if (!riscv_assign_reg_location (&ainfo->argloc[0], |
9f0272f8 | 2214 | &cinfo->float_regs, len0, offset)) |
dbbb1059 AB |
2215 | error (_("failed during argument setup")); |
2216 | ||
9f0272f8 AB |
2217 | int len1 = TYPE_LENGTH (sinfo.field_type (1)); |
2218 | offset = sinfo.field_offset (1); | |
dbbb1059 AB |
2219 | gdb_assert (len1 <= cinfo->xlen); |
2220 | if (!riscv_assign_reg_location (&ainfo->argloc[1], | |
2221 | &cinfo->int_regs, len1, offset)) | |
2222 | error (_("failed during argument setup")); | |
2223 | return; | |
2224 | } | |
2225 | ||
2226 | if (sinfo.number_of_fields () == 2 | |
2227 | && riscv_arg_regs_available (&cinfo->int_regs) >= 1 | |
2228 | && (is_integral_type (sinfo.field_type (0)) | |
2229 | && TYPE_LENGTH (sinfo.field_type (0)) <= cinfo->xlen | |
78134374 | 2230 | && sinfo.field_type(1)->code () == TYPE_CODE_FLT |
dbbb1059 AB |
2231 | && TYPE_LENGTH (sinfo.field_type (1)) <= cinfo->flen)) |
2232 | { | |
9f0272f8 AB |
2233 | int len0 = TYPE_LENGTH (sinfo.field_type (0)); |
2234 | int len1 = TYPE_LENGTH (sinfo.field_type (1)); | |
dbbb1059 AB |
2235 | |
2236 | gdb_assert (len0 <= cinfo->xlen); | |
2237 | gdb_assert (len1 <= cinfo->flen); | |
2238 | ||
9f0272f8 | 2239 | int offset = sinfo.field_offset (0); |
dbbb1059 | 2240 | if (!riscv_assign_reg_location (&ainfo->argloc[0], |
9f0272f8 | 2241 | &cinfo->int_regs, len0, offset)) |
dbbb1059 AB |
2242 | error (_("failed during argument setup")); |
2243 | ||
9f0272f8 | 2244 | offset = sinfo.field_offset (1); |
dbbb1059 AB |
2245 | if (!riscv_assign_reg_location (&ainfo->argloc[1], |
2246 | &cinfo->float_regs, | |
2247 | len1, offset)) | |
2248 | error (_("failed during argument setup")); | |
2249 | ||
2250 | return; | |
2251 | } | |
2252 | } | |
2253 | ||
2254 | /* Non of the structure flattening cases apply, so we just pass using | |
2255 | the integer ABI. */ | |
dbbb1059 AB |
2256 | riscv_call_arg_scalar_int (ainfo, cinfo); |
2257 | } | |
2258 | ||
2259 | /* Assign a location to call (or return) argument AINFO, the location is | |
2260 | selected from CINFO which holds information about what call argument | |
2261 | locations are available for use next. The TYPE is the type of the | |
2262 | argument being passed, this information is recorded into AINFO (along | |
8b2d40cb JW |
2263 | with some additional information derived from the type). IS_UNNAMED |
2264 | is true if this is an unnamed (stdarg) argument, this info is also | |
2265 | recorded into AINFO. | |
dbbb1059 AB |
2266 | |
2267 | After assigning a location to AINFO, CINFO will have been updated. */ | |
2268 | ||
2269 | static void | |
2270 | riscv_arg_location (struct gdbarch *gdbarch, | |
2271 | struct riscv_arg_info *ainfo, | |
2272 | struct riscv_call_info *cinfo, | |
8b2d40cb | 2273 | struct type *type, bool is_unnamed) |
dbbb1059 AB |
2274 | { |
2275 | ainfo->type = type; | |
2276 | ainfo->length = TYPE_LENGTH (ainfo->type); | |
a9158a86 | 2277 | ainfo->align = type_align (ainfo->type); |
8b2d40cb | 2278 | ainfo->is_unnamed = is_unnamed; |
dbbb1059 | 2279 | ainfo->contents = nullptr; |
9f0272f8 AB |
2280 | ainfo->argloc[0].c_length = 0; |
2281 | ainfo->argloc[1].c_length = 0; | |
dbbb1059 | 2282 | |
78134374 | 2283 | switch (ainfo->type->code ()) |
dbbb1059 AB |
2284 | { |
2285 | case TYPE_CODE_INT: | |
2286 | case TYPE_CODE_BOOL: | |
2287 | case TYPE_CODE_CHAR: | |
2288 | case TYPE_CODE_RANGE: | |
2289 | case TYPE_CODE_ENUM: | |
2290 | case TYPE_CODE_PTR: | |
2291 | if (ainfo->length <= cinfo->xlen) | |
2292 | { | |
2293 | ainfo->type = builtin_type (gdbarch)->builtin_long; | |
2294 | ainfo->length = cinfo->xlen; | |
2295 | } | |
2296 | else if (ainfo->length <= (2 * cinfo->xlen)) | |
2297 | { | |
2298 | ainfo->type = builtin_type (gdbarch)->builtin_long_long; | |
2299 | ainfo->length = 2 * cinfo->xlen; | |
2300 | } | |
2301 | ||
2302 | /* Recalculate the alignment requirement. */ | |
a9158a86 | 2303 | ainfo->align = type_align (ainfo->type); |
dbbb1059 AB |
2304 | riscv_call_arg_scalar_int (ainfo, cinfo); |
2305 | break; | |
2306 | ||
2307 | case TYPE_CODE_FLT: | |
2308 | riscv_call_arg_scalar_float (ainfo, cinfo); | |
2309 | break; | |
2310 | ||
2311 | case TYPE_CODE_COMPLEX: | |
2312 | riscv_call_arg_complex_float (ainfo, cinfo); | |
2313 | break; | |
2314 | ||
2315 | case TYPE_CODE_STRUCT: | |
2316 | riscv_call_arg_struct (ainfo, cinfo); | |
2317 | break; | |
2318 | ||
2319 | default: | |
2320 | riscv_call_arg_scalar_int (ainfo, cinfo); | |
2321 | break; | |
2322 | } | |
2323 | } | |
2324 | ||
cab5bb9d AB |
2325 | /* Used for printing debug information about the call argument location in |
2326 | INFO to STREAM. The addresses in SP_REFS and SP_ARGS are the base | |
2327 | addresses for the location of pass-by-reference and | |
2328 | arguments-on-the-stack memory areas. */ | |
2329 | ||
dbbb1059 | 2330 | static void |
cab5bb9d | 2331 | riscv_print_arg_location (ui_file *stream, struct gdbarch *gdbarch, |
dbbb1059 AB |
2332 | struct riscv_arg_info *info, |
2333 | CORE_ADDR sp_refs, CORE_ADDR sp_args) | |
2334 | { | |
cab5bb9d | 2335 | fprintf_unfiltered (stream, "type: '%s', length: 0x%x, alignment: 0x%x", |
42ecac17 | 2336 | TYPE_SAFE_NAME (info->type), info->length, info->align); |
dbbb1059 AB |
2337 | switch (info->argloc[0].loc_type) |
2338 | { | |
2339 | case riscv_arg_info::location::in_reg: | |
cab5bb9d AB |
2340 | fprintf_unfiltered |
2341 | (stream, ", register %s", | |
2342 | gdbarch_register_name (gdbarch, info->argloc[0].loc_data.regno)); | |
dbbb1059 AB |
2343 | if (info->argloc[0].c_length < info->length) |
2344 | { | |
2345 | switch (info->argloc[1].loc_type) | |
2346 | { | |
2347 | case riscv_arg_info::location::in_reg: | |
cab5bb9d AB |
2348 | fprintf_unfiltered |
2349 | (stream, ", register %s", | |
2350 | gdbarch_register_name (gdbarch, | |
2351 | info->argloc[1].loc_data.regno)); | |
dbbb1059 AB |
2352 | break; |
2353 | ||
2354 | case riscv_arg_info::location::on_stack: | |
cab5bb9d AB |
2355 | fprintf_unfiltered (stream, ", on stack at offset 0x%x", |
2356 | info->argloc[1].loc_data.offset); | |
dbbb1059 AB |
2357 | break; |
2358 | ||
2359 | case riscv_arg_info::location::by_ref: | |
2360 | default: | |
2361 | /* The second location should never be a reference, any | |
2362 | argument being passed by reference just places its address | |
2363 | in the first location and is done. */ | |
2364 | error (_("invalid argument location")); | |
2365 | break; | |
2366 | } | |
2367 | ||
2368 | if (info->argloc[1].c_offset > info->argloc[0].c_length) | |
cab5bb9d AB |
2369 | fprintf_unfiltered (stream, " (offset 0x%x)", |
2370 | info->argloc[1].c_offset); | |
dbbb1059 AB |
2371 | } |
2372 | break; | |
2373 | ||
2374 | case riscv_arg_info::location::on_stack: | |
cab5bb9d AB |
2375 | fprintf_unfiltered (stream, ", on stack at offset 0x%x", |
2376 | info->argloc[0].loc_data.offset); | |
dbbb1059 AB |
2377 | break; |
2378 | ||
2379 | case riscv_arg_info::location::by_ref: | |
cab5bb9d AB |
2380 | fprintf_unfiltered |
2381 | (stream, ", by reference, data at offset 0x%x (%s)", | |
2382 | info->argloc[0].loc_data.offset, | |
2383 | core_addr_to_string (sp_refs + info->argloc[0].loc_data.offset)); | |
dbbb1059 AB |
2384 | if (info->argloc[1].loc_type |
2385 | == riscv_arg_info::location::in_reg) | |
cab5bb9d AB |
2386 | fprintf_unfiltered |
2387 | (stream, ", address in register %s", | |
2388 | gdbarch_register_name (gdbarch, info->argloc[1].loc_data.regno)); | |
dbbb1059 AB |
2389 | else |
2390 | { | |
2391 | gdb_assert (info->argloc[1].loc_type | |
2392 | == riscv_arg_info::location::on_stack); | |
cab5bb9d AB |
2393 | fprintf_unfiltered |
2394 | (stream, ", address on stack at offset 0x%x (%s)", | |
2395 | info->argloc[1].loc_data.offset, | |
2396 | core_addr_to_string (sp_args + info->argloc[1].loc_data.offset)); | |
dbbb1059 AB |
2397 | } |
2398 | break; | |
2399 | ||
2400 | default: | |
89a3b63e | 2401 | gdb_assert_not_reached (_("unknown argument location type")); |
dbbb1059 AB |
2402 | } |
2403 | } | |
2404 | ||
dd895392 AB |
2405 | /* Wrapper around REGCACHE->cooked_write. Places the LEN bytes of DATA |
2406 | into a buffer that is at least as big as the register REGNUM, padding | |
2407 | out the DATA with either 0x00, or 0xff. For floating point registers | |
2408 | 0xff is used, for everyone else 0x00 is used. */ | |
2409 | ||
2410 | static void | |
2411 | riscv_regcache_cooked_write (int regnum, const gdb_byte *data, int len, | |
2412 | struct regcache *regcache, int flen) | |
2413 | { | |
2414 | gdb_byte tmp [sizeof (ULONGEST)]; | |
2415 | ||
2416 | /* FP values in FP registers must be NaN-boxed. */ | |
2417 | if (riscv_is_fp_regno_p (regnum) && len < flen) | |
2418 | memset (tmp, -1, sizeof (tmp)); | |
2419 | else | |
2420 | memset (tmp, 0, sizeof (tmp)); | |
2421 | memcpy (tmp, data, len); | |
2422 | regcache->cooked_write (regnum, tmp); | |
2423 | } | |
2424 | ||
dbbb1059 AB |
2425 | /* Implement the push dummy call gdbarch callback. */ |
2426 | ||
2427 | static CORE_ADDR | |
2428 | riscv_push_dummy_call (struct gdbarch *gdbarch, | |
2429 | struct value *function, | |
2430 | struct regcache *regcache, | |
2431 | CORE_ADDR bp_addr, | |
2432 | int nargs, | |
2433 | struct value **args, | |
2434 | CORE_ADDR sp, | |
cf84fa6b | 2435 | function_call_return_method return_method, |
dbbb1059 AB |
2436 | CORE_ADDR struct_addr) |
2437 | { | |
2438 | int i; | |
2439 | CORE_ADDR sp_args, sp_refs; | |
2440 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
dbbb1059 AB |
2441 | |
2442 | struct riscv_arg_info *arg_info = | |
2443 | (struct riscv_arg_info *) alloca (nargs * sizeof (struct riscv_arg_info)); | |
dbbb1059 AB |
2444 | |
2445 | struct riscv_call_info call_info (gdbarch); | |
2446 | ||
2447 | CORE_ADDR osp = sp; | |
2448 | ||
8b2d40cb JW |
2449 | struct type *ftype = check_typedef (value_type (function)); |
2450 | ||
78134374 | 2451 | if (ftype->code () == TYPE_CODE_PTR) |
8b2d40cb JW |
2452 | ftype = check_typedef (TYPE_TARGET_TYPE (ftype)); |
2453 | ||
dbbb1059 | 2454 | /* We'll use register $a0 if we're returning a struct. */ |
cf84fa6b | 2455 | if (return_method == return_method_struct) |
dbbb1059 AB |
2456 | ++call_info.int_regs.next_regnum; |
2457 | ||
b926417a | 2458 | for (i = 0; i < nargs; ++i) |
dbbb1059 AB |
2459 | { |
2460 | struct value *arg_value; | |
2461 | struct type *arg_type; | |
b926417a | 2462 | struct riscv_arg_info *info = &arg_info[i]; |
dbbb1059 AB |
2463 | |
2464 | arg_value = args[i]; | |
2465 | arg_type = check_typedef (value_type (arg_value)); | |
2466 | ||
8b2d40cb | 2467 | riscv_arg_location (gdbarch, info, &call_info, arg_type, |
1f704f76 | 2468 | TYPE_VARARGS (ftype) && i >= ftype->num_fields ()); |
dbbb1059 AB |
2469 | |
2470 | if (info->type != arg_type) | |
2471 | arg_value = value_cast (info->type, arg_value); | |
2472 | info->contents = value_contents (arg_value); | |
2473 | } | |
2474 | ||
2475 | /* Adjust the stack pointer and align it. */ | |
2476 | sp = sp_refs = align_down (sp - call_info.memory.ref_offset, SP_ALIGNMENT); | |
2477 | sp = sp_args = align_down (sp - call_info.memory.arg_offset, SP_ALIGNMENT); | |
2478 | ||
2479 | if (riscv_debug_infcall > 0) | |
2480 | { | |
2481 | fprintf_unfiltered (gdb_stdlog, "dummy call args:\n"); | |
2482 | fprintf_unfiltered (gdb_stdlog, ": floating point ABI %s in use\n", | |
2483 | (riscv_has_fp_abi (gdbarch) ? "is" : "is not")); | |
2484 | fprintf_unfiltered (gdb_stdlog, ": xlen: %d\n: flen: %d\n", | |
2485 | call_info.xlen, call_info.flen); | |
cf84fa6b | 2486 | if (return_method == return_method_struct) |
dbbb1059 AB |
2487 | fprintf_unfiltered (gdb_stdlog, |
2488 | "[*] struct return pointer in register $A0\n"); | |
2489 | for (i = 0; i < nargs; ++i) | |
2490 | { | |
2491 | struct riscv_arg_info *info = &arg_info [i]; | |
2492 | ||
2493 | fprintf_unfiltered (gdb_stdlog, "[%2d] ", i); | |
cab5bb9d | 2494 | riscv_print_arg_location (gdb_stdlog, gdbarch, info, sp_refs, sp_args); |
dbbb1059 AB |
2495 | fprintf_unfiltered (gdb_stdlog, "\n"); |
2496 | } | |
2497 | if (call_info.memory.arg_offset > 0 | |
2498 | || call_info.memory.ref_offset > 0) | |
2499 | { | |
cab5bb9d AB |
2500 | fprintf_unfiltered (gdb_stdlog, " Original sp: %s\n", |
2501 | core_addr_to_string (osp)); | |
dbbb1059 | 2502 | fprintf_unfiltered (gdb_stdlog, "Stack required (for args): 0x%x\n", |
cab5bb9d | 2503 | call_info.memory.arg_offset); |
dbbb1059 | 2504 | fprintf_unfiltered (gdb_stdlog, "Stack required (for refs): 0x%x\n", |
cab5bb9d | 2505 | call_info.memory.ref_offset); |
fb294655 AB |
2506 | fprintf_unfiltered (gdb_stdlog, " Stack allocated: %s\n", |
2507 | core_addr_to_string_nz (osp - sp)); | |
dbbb1059 AB |
2508 | } |
2509 | } | |
2510 | ||
2511 | /* Now load the argument into registers, or onto the stack. */ | |
2512 | ||
cf84fa6b | 2513 | if (return_method == return_method_struct) |
dbbb1059 AB |
2514 | { |
2515 | gdb_byte buf[sizeof (LONGEST)]; | |
2516 | ||
2517 | store_unsigned_integer (buf, call_info.xlen, byte_order, struct_addr); | |
b66f5587 | 2518 | regcache->cooked_write (RISCV_A0_REGNUM, buf); |
dbbb1059 AB |
2519 | } |
2520 | ||
2521 | for (i = 0; i < nargs; ++i) | |
2522 | { | |
2523 | CORE_ADDR dst; | |
2524 | int second_arg_length = 0; | |
2525 | const gdb_byte *second_arg_data; | |
2526 | struct riscv_arg_info *info = &arg_info [i]; | |
2527 | ||
2528 | gdb_assert (info->length > 0); | |
2529 | ||
2530 | switch (info->argloc[0].loc_type) | |
2531 | { | |
2532 | case riscv_arg_info::location::in_reg: | |
2533 | { | |
dbbb1059 | 2534 | gdb_assert (info->argloc[0].c_length <= info->length); |
dd895392 AB |
2535 | |
2536 | riscv_regcache_cooked_write (info->argloc[0].loc_data.regno, | |
2537 | (info->contents | |
2538 | + info->argloc[0].c_offset), | |
2539 | info->argloc[0].c_length, | |
2540 | regcache, call_info.flen); | |
dbbb1059 | 2541 | second_arg_length = |
9f0272f8 | 2542 | (((info->argloc[0].c_length + info->argloc[0].c_offset) < info->length) |
dbbb1059 AB |
2543 | ? info->argloc[1].c_length : 0); |
2544 | second_arg_data = info->contents + info->argloc[1].c_offset; | |
2545 | } | |
2546 | break; | |
2547 | ||
2548 | case riscv_arg_info::location::on_stack: | |
2549 | dst = sp_args + info->argloc[0].loc_data.offset; | |
2550 | write_memory (dst, info->contents, info->length); | |
2551 | second_arg_length = 0; | |
2552 | break; | |
2553 | ||
2554 | case riscv_arg_info::location::by_ref: | |
2555 | dst = sp_refs + info->argloc[0].loc_data.offset; | |
2556 | write_memory (dst, info->contents, info->length); | |
2557 | ||
2558 | second_arg_length = call_info.xlen; | |
2559 | second_arg_data = (gdb_byte *) &dst; | |
2560 | break; | |
2561 | ||
2562 | default: | |
89a3b63e | 2563 | gdb_assert_not_reached (_("unknown argument location type")); |
dbbb1059 AB |
2564 | } |
2565 | ||
2566 | if (second_arg_length > 0) | |
2567 | { | |
2568 | switch (info->argloc[1].loc_type) | |
2569 | { | |
2570 | case riscv_arg_info::location::in_reg: | |
2571 | { | |
8c49aa89 AB |
2572 | gdb_assert ((riscv_is_fp_regno_p (info->argloc[1].loc_data.regno) |
2573 | && second_arg_length <= call_info.flen) | |
2574 | || second_arg_length <= call_info.xlen); | |
dd895392 AB |
2575 | riscv_regcache_cooked_write (info->argloc[1].loc_data.regno, |
2576 | second_arg_data, | |
2577 | second_arg_length, | |
2578 | regcache, call_info.flen); | |
dbbb1059 AB |
2579 | } |
2580 | break; | |
2581 | ||
2582 | case riscv_arg_info::location::on_stack: | |
2583 | { | |
2584 | CORE_ADDR arg_addr; | |
2585 | ||
2586 | arg_addr = sp_args + info->argloc[1].loc_data.offset; | |
2587 | write_memory (arg_addr, second_arg_data, second_arg_length); | |
2588 | break; | |
2589 | } | |
2590 | ||
2591 | case riscv_arg_info::location::by_ref: | |
2592 | default: | |
2593 | /* The second location should never be a reference, any | |
2594 | argument being passed by reference just places its address | |
2595 | in the first location and is done. */ | |
2596 | error (_("invalid argument location")); | |
2597 | break; | |
2598 | } | |
2599 | } | |
2600 | } | |
2601 | ||
2602 | /* Set the dummy return value to bp_addr. | |
2603 | A dummy breakpoint will be setup to execute the call. */ | |
2604 | ||
2605 | if (riscv_debug_infcall > 0) | |
cab5bb9d AB |
2606 | fprintf_unfiltered (gdb_stdlog, ": writing $ra = %s\n", |
2607 | core_addr_to_string (bp_addr)); | |
dbbb1059 AB |
2608 | regcache_cooked_write_unsigned (regcache, RISCV_RA_REGNUM, bp_addr); |
2609 | ||
2610 | /* Finally, update the stack pointer. */ | |
2611 | ||
2612 | if (riscv_debug_infcall > 0) | |
cab5bb9d AB |
2613 | fprintf_unfiltered (gdb_stdlog, ": writing $sp = %s\n", |
2614 | core_addr_to_string (sp)); | |
dbbb1059 AB |
2615 | regcache_cooked_write_unsigned (regcache, RISCV_SP_REGNUM, sp); |
2616 | ||
2617 | return sp; | |
2618 | } | |
2619 | ||
2620 | /* Implement the return_value gdbarch method. */ | |
2621 | ||
2622 | static enum return_value_convention | |
2623 | riscv_return_value (struct gdbarch *gdbarch, | |
2624 | struct value *function, | |
2625 | struct type *type, | |
2626 | struct regcache *regcache, | |
2627 | gdb_byte *readbuf, | |
2628 | const gdb_byte *writebuf) | |
2629 | { | |
dbbb1059 AB |
2630 | struct riscv_call_info call_info (gdbarch); |
2631 | struct riscv_arg_info info; | |
2632 | struct type *arg_type; | |
2633 | ||
2634 | arg_type = check_typedef (type); | |
8b2d40cb | 2635 | riscv_arg_location (gdbarch, &info, &call_info, arg_type, false); |
dbbb1059 AB |
2636 | |
2637 | if (riscv_debug_infcall > 0) | |
2638 | { | |
2639 | fprintf_unfiltered (gdb_stdlog, "riscv return value:\n"); | |
2640 | fprintf_unfiltered (gdb_stdlog, "[R] "); | |
cab5bb9d | 2641 | riscv_print_arg_location (gdb_stdlog, gdbarch, &info, 0, 0); |
dbbb1059 AB |
2642 | fprintf_unfiltered (gdb_stdlog, "\n"); |
2643 | } | |
2644 | ||
2645 | if (readbuf != nullptr || writebuf != nullptr) | |
2646 | { | |
74e3300d AB |
2647 | unsigned int arg_len; |
2648 | struct value *abi_val; | |
2649 | gdb_byte *old_readbuf = nullptr; | |
2650 | int regnum; | |
2651 | ||
2652 | /* We only do one thing at a time. */ | |
2653 | gdb_assert (readbuf == nullptr || writebuf == nullptr); | |
2654 | ||
2655 | /* In some cases the argument is not returned as the declared type, | |
2656 | and we need to cast to or from the ABI type in order to | |
2657 | correctly access the argument. When writing to the machine we | |
2658 | do the cast here, when reading from the machine the cast occurs | |
2659 | later, after extracting the value. As the ABI type can be | |
2660 | larger than the declared type, then the read or write buffers | |
2661 | passed in might be too small. Here we ensure that we are using | |
2662 | buffers of sufficient size. */ | |
2663 | if (writebuf != nullptr) | |
2664 | { | |
2665 | struct value *arg_val = value_from_contents (arg_type, writebuf); | |
2666 | abi_val = value_cast (info.type, arg_val); | |
2667 | writebuf = value_contents_raw (abi_val); | |
2668 | } | |
2669 | else | |
2670 | { | |
2671 | abi_val = allocate_value (info.type); | |
2672 | old_readbuf = readbuf; | |
2673 | readbuf = value_contents_raw (abi_val); | |
2674 | } | |
2675 | arg_len = TYPE_LENGTH (info.type); | |
dbbb1059 AB |
2676 | |
2677 | switch (info.argloc[0].loc_type) | |
2678 | { | |
2679 | /* Return value in register(s). */ | |
2680 | case riscv_arg_info::location::in_reg: | |
2681 | { | |
2682 | regnum = info.argloc[0].loc_data.regno; | |
74e3300d AB |
2683 | gdb_assert (info.argloc[0].c_length <= arg_len); |
2684 | gdb_assert (info.argloc[0].c_length | |
2685 | <= register_size (gdbarch, regnum)); | |
dbbb1059 AB |
2686 | |
2687 | if (readbuf) | |
9f0272f8 AB |
2688 | { |
2689 | gdb_byte *ptr = readbuf + info.argloc[0].c_offset; | |
2690 | regcache->cooked_read_part (regnum, 0, | |
2691 | info.argloc[0].c_length, | |
2692 | ptr); | |
2693 | } | |
dbbb1059 AB |
2694 | |
2695 | if (writebuf) | |
9f0272f8 AB |
2696 | { |
2697 | const gdb_byte *ptr = writebuf + info.argloc[0].c_offset; | |
dd895392 | 2698 | riscv_regcache_cooked_write (regnum, ptr, |
9f0272f8 | 2699 | info.argloc[0].c_length, |
dd895392 | 2700 | regcache, call_info.flen); |
9f0272f8 | 2701 | } |
dbbb1059 AB |
2702 | |
2703 | /* A return value in register can have a second part in a | |
2704 | second register. */ | |
9f0272f8 | 2705 | if (info.argloc[1].c_length > 0) |
dbbb1059 AB |
2706 | { |
2707 | switch (info.argloc[1].loc_type) | |
2708 | { | |
2709 | case riscv_arg_info::location::in_reg: | |
2710 | regnum = info.argloc[1].loc_data.regno; | |
2711 | ||
74e3300d AB |
2712 | gdb_assert ((info.argloc[0].c_length |
2713 | + info.argloc[1].c_length) <= arg_len); | |
2714 | gdb_assert (info.argloc[1].c_length | |
2715 | <= register_size (gdbarch, regnum)); | |
2716 | ||
dbbb1059 AB |
2717 | if (readbuf) |
2718 | { | |
2719 | readbuf += info.argloc[1].c_offset; | |
74e3300d AB |
2720 | regcache->cooked_read_part (regnum, 0, |
2721 | info.argloc[1].c_length, | |
2722 | readbuf); | |
dbbb1059 AB |
2723 | } |
2724 | ||
2725 | if (writebuf) | |
2726 | { | |
dd895392 AB |
2727 | const gdb_byte *ptr |
2728 | = writebuf + info.argloc[1].c_offset; | |
2729 | riscv_regcache_cooked_write | |
2730 | (regnum, ptr, info.argloc[1].c_length, | |
2731 | regcache, call_info.flen); | |
dbbb1059 AB |
2732 | } |
2733 | break; | |
2734 | ||
2735 | case riscv_arg_info::location::by_ref: | |
2736 | case riscv_arg_info::location::on_stack: | |
2737 | default: | |
2738 | error (_("invalid argument location")); | |
2739 | break; | |
2740 | } | |
2741 | } | |
2742 | } | |
2743 | break; | |
2744 | ||
2745 | /* Return value by reference will have its address in A0. */ | |
2746 | case riscv_arg_info::location::by_ref: | |
2747 | { | |
b2970c23 | 2748 | ULONGEST addr; |
dbbb1059 AB |
2749 | |
2750 | regcache_cooked_read_unsigned (regcache, RISCV_A0_REGNUM, | |
2751 | &addr); | |
2752 | if (readbuf != nullptr) | |
2753 | read_memory (addr, readbuf, info.length); | |
2754 | if (writebuf != nullptr) | |
2755 | write_memory (addr, writebuf, info.length); | |
2756 | } | |
2757 | break; | |
2758 | ||
2759 | case riscv_arg_info::location::on_stack: | |
2760 | default: | |
2761 | error (_("invalid argument location")); | |
2762 | break; | |
2763 | } | |
74e3300d AB |
2764 | |
2765 | /* This completes the cast from abi type back to the declared type | |
2766 | in the case that we are reading from the machine. See the | |
2767 | comment at the head of this block for more details. */ | |
2768 | if (readbuf != nullptr) | |
2769 | { | |
2770 | struct value *arg_val = value_cast (arg_type, abi_val); | |
2771 | memcpy (old_readbuf, value_contents_raw (arg_val), | |
2772 | TYPE_LENGTH (arg_type)); | |
2773 | } | |
dbbb1059 AB |
2774 | } |
2775 | ||
2776 | switch (info.argloc[0].loc_type) | |
2777 | { | |
2778 | case riscv_arg_info::location::in_reg: | |
2779 | return RETURN_VALUE_REGISTER_CONVENTION; | |
2780 | case riscv_arg_info::location::by_ref: | |
2781 | return RETURN_VALUE_ABI_RETURNS_ADDRESS; | |
2782 | case riscv_arg_info::location::on_stack: | |
2783 | default: | |
2784 | error (_("invalid argument location")); | |
2785 | } | |
2786 | } | |
2787 | ||
2788 | /* Implement the frame_align gdbarch method. */ | |
2789 | ||
2790 | static CORE_ADDR | |
2791 | riscv_frame_align (struct gdbarch *gdbarch, CORE_ADDR addr) | |
2792 | { | |
2793 | return align_down (addr, 16); | |
2794 | } | |
2795 | ||
dbbb1059 AB |
2796 | /* Generate, or return the cached frame cache for the RiscV frame |
2797 | unwinder. */ | |
2798 | ||
78a3b0fa | 2799 | static struct riscv_unwind_cache * |
dbbb1059 AB |
2800 | riscv_frame_cache (struct frame_info *this_frame, void **this_cache) |
2801 | { | |
78a3b0fa AB |
2802 | CORE_ADDR pc, start_addr; |
2803 | struct riscv_unwind_cache *cache; | |
dbbb1059 | 2804 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
78a3b0fa | 2805 | int numregs, regno; |
dbbb1059 AB |
2806 | |
2807 | if ((*this_cache) != NULL) | |
78a3b0fa | 2808 | return (struct riscv_unwind_cache *) *this_cache; |
dbbb1059 | 2809 | |
78a3b0fa AB |
2810 | cache = FRAME_OBSTACK_ZALLOC (struct riscv_unwind_cache); |
2811 | cache->regs = trad_frame_alloc_saved_regs (this_frame); | |
2812 | (*this_cache) = cache; | |
dbbb1059 | 2813 | |
78a3b0fa AB |
2814 | /* Scan the prologue, filling in the cache. */ |
2815 | start_addr = get_frame_func (this_frame); | |
dbbb1059 | 2816 | pc = get_frame_pc (this_frame); |
78a3b0fa AB |
2817 | riscv_scan_prologue (gdbarch, start_addr, pc, cache); |
2818 | ||
2819 | /* We can now calculate the frame base address. */ | |
2820 | cache->frame_base | |
6c9d681b AB |
2821 | = (get_frame_register_signed (this_frame, cache->frame_base_reg) |
2822 | + cache->frame_base_offset); | |
78a3b0fa AB |
2823 | if (riscv_debug_unwinder) |
2824 | fprintf_unfiltered (gdb_stdlog, "Frame base is %s ($%s + 0x%x)\n", | |
2825 | core_addr_to_string (cache->frame_base), | |
2826 | gdbarch_register_name (gdbarch, | |
2827 | cache->frame_base_reg), | |
2828 | cache->frame_base_offset); | |
2829 | ||
2830 | /* The prologue scanner sets the address of registers stored to the stack | |
2831 | as the offset of that register from the frame base. The prologue | |
2832 | scanner doesn't know the actual frame base value, and so is unable to | |
2833 | compute the exact address. We do now know the frame base value, so | |
2834 | update the address of registers stored to the stack. */ | |
2835 | numregs = gdbarch_num_regs (gdbarch) + gdbarch_num_pseudo_regs (gdbarch); | |
2836 | for (regno = 0; regno < numregs; ++regno) | |
2837 | { | |
2838 | if (trad_frame_addr_p (cache->regs, regno)) | |
2839 | cache->regs[regno].addr += cache->frame_base; | |
2840 | } | |
2841 | ||
2842 | /* The previous $pc can be found wherever the $ra value can be found. | |
2843 | The previous $ra value is gone, this would have been stored be the | |
2844 | previous frame if required. */ | |
2845 | cache->regs[gdbarch_pc_regnum (gdbarch)] = cache->regs[RISCV_RA_REGNUM]; | |
2846 | trad_frame_set_unknown (cache->regs, RISCV_RA_REGNUM); | |
2847 | ||
2848 | /* Build the frame id. */ | |
2849 | cache->this_id = frame_id_build (cache->frame_base, start_addr); | |
dbbb1059 | 2850 | |
78a3b0fa AB |
2851 | /* The previous $sp value is the frame base value. */ |
2852 | trad_frame_set_value (cache->regs, gdbarch_sp_regnum (gdbarch), | |
2853 | cache->frame_base); | |
dbbb1059 | 2854 | |
78a3b0fa | 2855 | return cache; |
dbbb1059 AB |
2856 | } |
2857 | ||
2858 | /* Implement the this_id callback for RiscV frame unwinder. */ | |
2859 | ||
2860 | static void | |
2861 | riscv_frame_this_id (struct frame_info *this_frame, | |
2862 | void **prologue_cache, | |
2863 | struct frame_id *this_id) | |
2864 | { | |
78a3b0fa | 2865 | struct riscv_unwind_cache *cache; |
dbbb1059 | 2866 | |
a70b8144 | 2867 | try |
17cf2897 AB |
2868 | { |
2869 | cache = riscv_frame_cache (this_frame, prologue_cache); | |
2870 | *this_id = cache->this_id; | |
2871 | } | |
230d2906 | 2872 | catch (const gdb_exception_error &ex) |
17cf2897 AB |
2873 | { |
2874 | /* Ignore errors, this leaves the frame id as the predefined outer | |
2875 | frame id which terminates the backtrace at this point. */ | |
2876 | } | |
dbbb1059 AB |
2877 | } |
2878 | ||
2879 | /* Implement the prev_register callback for RiscV frame unwinder. */ | |
2880 | ||
2881 | static struct value * | |
2882 | riscv_frame_prev_register (struct frame_info *this_frame, | |
2883 | void **prologue_cache, | |
2884 | int regnum) | |
2885 | { | |
78a3b0fa | 2886 | struct riscv_unwind_cache *cache; |
dbbb1059 | 2887 | |
78a3b0fa AB |
2888 | cache = riscv_frame_cache (this_frame, prologue_cache); |
2889 | return trad_frame_get_prev_register (this_frame, cache->regs, regnum); | |
dbbb1059 AB |
2890 | } |
2891 | ||
2892 | /* Structure defining the RiscV normal frame unwind functions. Since we | |
2893 | are the fallback unwinder (DWARF unwinder is used first), we use the | |
2894 | default frame sniffer, which always accepts the frame. */ | |
2895 | ||
2896 | static const struct frame_unwind riscv_frame_unwind = | |
2897 | { | |
2898 | /*.type =*/ NORMAL_FRAME, | |
2899 | /*.stop_reason =*/ default_frame_unwind_stop_reason, | |
2900 | /*.this_id =*/ riscv_frame_this_id, | |
2901 | /*.prev_register =*/ riscv_frame_prev_register, | |
2902 | /*.unwind_data =*/ NULL, | |
2903 | /*.sniffer =*/ default_frame_sniffer, | |
2904 | /*.dealloc_cache =*/ NULL, | |
2905 | /*.prev_arch =*/ NULL, | |
2906 | }; | |
2907 | ||
90af0679 AB |
2908 | /* Extract a set of required target features out of INFO, specifically the |
2909 | bfd being executed is examined to see what target features it requires. | |
2910 | IF there is no current bfd, or the bfd doesn't indicate any useful | |
2911 | features then a RISCV_GDBARCH_FEATURES is returned in its default state. */ | |
dbbb1059 | 2912 | |
90af0679 AB |
2913 | static struct riscv_gdbarch_features |
2914 | riscv_features_from_gdbarch_info (const struct gdbarch_info info) | |
dbbb1059 | 2915 | { |
b5ffee31 | 2916 | struct riscv_gdbarch_features features; |
dbbb1059 | 2917 | |
b5ffee31 AB |
2918 | /* Now try to improve on the defaults by looking at the binary we are |
2919 | going to execute. We assume the user knows what they are doing and | |
2920 | that the target will match the binary. Remember, this code path is | |
2921 | only used at all if the target hasn't given us a description, so this | |
2922 | is really a last ditched effort to do something sane before giving | |
2923 | up. */ | |
dbbb1059 AB |
2924 | if (info.abfd != NULL |
2925 | && bfd_get_flavour (info.abfd) == bfd_target_elf_flavour) | |
2926 | { | |
2927 | unsigned char eclass = elf_elfheader (info.abfd)->e_ident[EI_CLASS]; | |
2928 | int e_flags = elf_elfheader (info.abfd)->e_flags; | |
2929 | ||
2930 | if (eclass == ELFCLASS32) | |
b5ffee31 | 2931 | features.xlen = 4; |
dbbb1059 | 2932 | else if (eclass == ELFCLASS64) |
b5ffee31 | 2933 | features.xlen = 8; |
dbbb1059 | 2934 | else |
b5ffee31 | 2935 | internal_error (__FILE__, __LINE__, |
dbbb1059 AB |
2936 | _("unknown ELF header class %d"), eclass); |
2937 | ||
dbbb1059 | 2938 | if (e_flags & EF_RISCV_FLOAT_ABI_DOUBLE) |
113b7b81 | 2939 | features.flen = 8; |
dbbb1059 | 2940 | else if (e_flags & EF_RISCV_FLOAT_ABI_SINGLE) |
113b7b81 | 2941 | features.flen = 4; |
dbbb1059 | 2942 | } |
dbbb1059 | 2943 | |
90af0679 AB |
2944 | return features; |
2945 | } | |
2946 | ||
2947 | /* Find a suitable default target description. Use the contents of INFO, | |
2948 | specifically the bfd object being executed, to guide the selection of a | |
2949 | suitable default target description. */ | |
2950 | ||
2951 | static const struct target_desc * | |
2952 | riscv_find_default_target_description (const struct gdbarch_info info) | |
2953 | { | |
2954 | /* Extract desired feature set from INFO. */ | |
2955 | struct riscv_gdbarch_features features | |
2956 | = riscv_features_from_gdbarch_info (info); | |
2957 | ||
2958 | /* If the XLEN field is still 0 then we got nothing useful from INFO. In | |
2959 | this case we fall back to a minimal useful target, 8-byte x-registers, | |
2960 | with no floating point. */ | |
2961 | if (features.xlen == 0) | |
2962 | features.xlen = 8; | |
2963 | ||
b5ffee31 | 2964 | /* Now build a target description based on the feature set. */ |
d1c9b20f | 2965 | return riscv_lookup_target_description (features); |
b5ffee31 AB |
2966 | } |
2967 | ||
767a879e AB |
2968 | /* Information about a register alias that needs to be set up for this |
2969 | target. These are collected when the target's XML description is | |
2970 | analysed, and then processed later, once the gdbarch has been created. */ | |
2971 | ||
2972 | class riscv_pending_register_alias | |
2973 | { | |
2974 | public: | |
2975 | /* Constructor. */ | |
2976 | ||
2977 | riscv_pending_register_alias (const char *name, const void *baton) | |
2978 | : m_name (name), | |
2979 | m_baton (baton) | |
2980 | { /* Nothing. */ } | |
2981 | ||
2982 | /* Convert this into a user register for GDBARCH. */ | |
2983 | ||
2984 | void create (struct gdbarch *gdbarch) const | |
2985 | { | |
2986 | user_reg_add (gdbarch, m_name, value_of_riscv_user_reg, m_baton); | |
2987 | } | |
2988 | ||
2989 | private: | |
2990 | /* The name for this alias. */ | |
2991 | const char *m_name; | |
2992 | ||
2993 | /* The baton value for passing to user_reg_add. This must point to some | |
2994 | data that will live for at least as long as the gdbarch object to | |
2995 | which the user register is attached. */ | |
2996 | const void *m_baton; | |
2997 | }; | |
2998 | ||
b5ffee31 AB |
2999 | /* All of the registers in REG_SET are checked for in FEATURE, TDESC_DATA |
3000 | is updated with the register numbers for each register as listed in | |
3001 | REG_SET. If any register marked as required in REG_SET is not found in | |
3002 | FEATURE then this function returns false, otherwise, it returns true. */ | |
3003 | ||
3004 | static bool | |
3005 | riscv_check_tdesc_feature (struct tdesc_arch_data *tdesc_data, | |
3006 | const struct tdesc_feature *feature, | |
767a879e AB |
3007 | const struct riscv_register_feature *reg_set, |
3008 | std::vector<riscv_pending_register_alias> *aliases) | |
b5ffee31 AB |
3009 | { |
3010 | for (const auto ® : reg_set->registers) | |
3011 | { | |
3012 | bool found = false; | |
3013 | ||
3014 | for (const char *name : reg.names) | |
3015 | { | |
ed69cbc8 AB |
3016 | found = tdesc_numbered_register (feature, tdesc_data, reg.regnum, |
3017 | name); | |
b5ffee31 AB |
3018 | |
3019 | if (found) | |
767a879e AB |
3020 | { |
3021 | /* We know that the target description mentions this | |
3022 | register. In RISCV_REGISTER_NAME we ensure that GDB | |
3023 | always uses the first name for each register, so here we | |
3024 | add aliases for all of the remaining names. */ | |
ed69cbc8 AB |
3025 | bool prefer_first_name = reg_set->prefer_first_name; |
3026 | int start_index = prefer_first_name ? 1 : 0; | |
3027 | for (int i = start_index; i < reg.names.size (); ++i) | |
3028 | { | |
3029 | const char *alias = reg.names[i]; | |
3030 | if (alias == name && !prefer_first_name) | |
3031 | continue; | |
3032 | aliases->emplace_back (alias, (void *) ®.regnum); | |
3033 | } | |
767a879e AB |
3034 | break; |
3035 | } | |
b5ffee31 AB |
3036 | } |
3037 | ||
3038 | if (!found && reg.required_p) | |
3039 | return false; | |
3040 | } | |
3041 | ||
3042 | return true; | |
3043 | } | |
3044 | ||
3045 | /* Add all the expected register sets into GDBARCH. */ | |
3046 | ||
3047 | static void | |
3048 | riscv_add_reggroups (struct gdbarch *gdbarch) | |
3049 | { | |
3050 | /* Add predefined register groups. */ | |
3051 | reggroup_add (gdbarch, all_reggroup); | |
3052 | reggroup_add (gdbarch, save_reggroup); | |
3053 | reggroup_add (gdbarch, restore_reggroup); | |
3054 | reggroup_add (gdbarch, system_reggroup); | |
3055 | reggroup_add (gdbarch, vector_reggroup); | |
3056 | reggroup_add (gdbarch, general_reggroup); | |
3057 | reggroup_add (gdbarch, float_reggroup); | |
3058 | ||
3059 | /* Add RISC-V specific register groups. */ | |
3060 | reggroup_add (gdbarch, csr_reggroup); | |
3061 | } | |
3062 | ||
fb44d95a AB |
3063 | /* Implement the "dwarf2_reg_to_regnum" gdbarch method. */ |
3064 | ||
3065 | static int | |
3066 | riscv_dwarf_reg_to_regnum (struct gdbarch *gdbarch, int reg) | |
3067 | { | |
3068 | if (reg < RISCV_DWARF_REGNUM_X31) | |
3069 | return RISCV_ZERO_REGNUM + (reg - RISCV_DWARF_REGNUM_X0); | |
3070 | ||
3071 | else if (reg < RISCV_DWARF_REGNUM_F31) | |
3072 | return RISCV_FIRST_FP_REGNUM + (reg - RISCV_DWARF_REGNUM_F0); | |
3073 | ||
3074 | return -1; | |
3075 | } | |
3076 | ||
ff371ec9 JW |
3077 | /* Implement the gcc_target_options method. We have to select the arch and abi |
3078 | from the feature info. We have enough feature info to select the abi, but | |
3079 | not enough info for the arch given all of the possible architecture | |
3080 | extensions. So choose reasonable defaults for now. */ | |
3081 | ||
3082 | static std::string | |
3083 | riscv_gcc_target_options (struct gdbarch *gdbarch) | |
3084 | { | |
3085 | int isa_xlen = riscv_isa_xlen (gdbarch); | |
3086 | int isa_flen = riscv_isa_flen (gdbarch); | |
3087 | int abi_xlen = riscv_abi_xlen (gdbarch); | |
3088 | int abi_flen = riscv_abi_flen (gdbarch); | |
3089 | std::string target_options; | |
3090 | ||
3091 | target_options = "-march=rv"; | |
3092 | if (isa_xlen == 8) | |
3093 | target_options += "64"; | |
3094 | else | |
3095 | target_options += "32"; | |
3096 | if (isa_flen == 8) | |
3097 | target_options += "gc"; | |
3098 | else if (isa_flen == 4) | |
3099 | target_options += "imafc"; | |
3100 | else | |
3101 | target_options += "imac"; | |
3102 | ||
3103 | target_options += " -mabi="; | |
3104 | if (abi_xlen == 8) | |
3105 | target_options += "lp64"; | |
3106 | else | |
3107 | target_options += "ilp32"; | |
3108 | if (abi_flen == 8) | |
3109 | target_options += "d"; | |
3110 | else if (abi_flen == 4) | |
3111 | target_options += "f"; | |
3112 | ||
3113 | /* The gdb loader doesn't handle link-time relaxation relocations. */ | |
3114 | target_options += " -mno-relax"; | |
3115 | ||
3116 | return target_options; | |
3117 | } | |
3118 | ||
3119 | /* Implement the gnu_triplet_regexp method. A single compiler supports both | |
3120 | 32-bit and 64-bit code, and may be named riscv32 or riscv64 or (not | |
3121 | recommended) riscv. */ | |
3122 | ||
3123 | static const char * | |
3124 | riscv_gnu_triplet_regexp (struct gdbarch *gdbarch) | |
3125 | { | |
3126 | return "riscv(32|64)?"; | |
3127 | } | |
3128 | ||
b5ffee31 AB |
3129 | /* Initialize the current architecture based on INFO. If possible, |
3130 | re-use an architecture from ARCHES, which is a list of | |
3131 | architectures already created during this debugging session. | |
3132 | ||
3133 | Called e.g. at program startup, when reading a core file, and when | |
3134 | reading a binary file. */ | |
3135 | ||
3136 | static struct gdbarch * | |
3137 | riscv_gdbarch_init (struct gdbarch_info info, | |
3138 | struct gdbarch_list *arches) | |
3139 | { | |
3140 | struct gdbarch *gdbarch; | |
3141 | struct gdbarch_tdep *tdep; | |
3142 | struct riscv_gdbarch_features features; | |
3143 | const struct target_desc *tdesc = info.target_desc; | |
3144 | ||
3145 | /* Ensure we always have a target description. */ | |
3146 | if (!tdesc_has_registers (tdesc)) | |
3147 | tdesc = riscv_find_default_target_description (info); | |
3148 | gdb_assert (tdesc); | |
3149 | ||
3150 | if (riscv_debug_gdbarch) | |
3151 | fprintf_unfiltered (gdb_stdlog, "Have got a target description\n"); | |
3152 | ||
3153 | const struct tdesc_feature *feature_cpu | |
3154 | = tdesc_find_feature (tdesc, riscv_xreg_feature.name); | |
3155 | const struct tdesc_feature *feature_fpu | |
3156 | = tdesc_find_feature (tdesc, riscv_freg_feature.name); | |
3157 | const struct tdesc_feature *feature_virtual | |
3158 | = tdesc_find_feature (tdesc, riscv_virtual_feature.name); | |
3159 | const struct tdesc_feature *feature_csr | |
3160 | = tdesc_find_feature (tdesc, riscv_csr_feature.name); | |
3161 | ||
3162 | if (feature_cpu == NULL) | |
3163 | return NULL; | |
3164 | ||
3165 | struct tdesc_arch_data *tdesc_data = tdesc_data_alloc (); | |
767a879e | 3166 | std::vector<riscv_pending_register_alias> pending_aliases; |
b5ffee31 AB |
3167 | |
3168 | bool valid_p = riscv_check_tdesc_feature (tdesc_data, | |
3169 | feature_cpu, | |
767a879e AB |
3170 | &riscv_xreg_feature, |
3171 | &pending_aliases); | |
b5ffee31 AB |
3172 | if (valid_p) |
3173 | { | |
3174 | /* Check that all of the core cpu registers have the same bitsize. */ | |
3175 | int xlen_bitsize = tdesc_register_bitsize (feature_cpu, "pc"); | |
3176 | ||
3177 | for (auto &tdesc_reg : feature_cpu->registers) | |
3178 | valid_p &= (tdesc_reg->bitsize == xlen_bitsize); | |
3179 | ||
3180 | if (riscv_debug_gdbarch) | |
3181 | fprintf_filtered | |
3182 | (gdb_stdlog, | |
3183 | "From target-description, xlen = %d\n", xlen_bitsize); | |
3184 | ||
3185 | features.xlen = (xlen_bitsize / 8); | |
3186 | } | |
3187 | ||
3188 | if (feature_fpu != NULL) | |
3189 | { | |
3190 | valid_p &= riscv_check_tdesc_feature (tdesc_data, feature_fpu, | |
767a879e AB |
3191 | &riscv_freg_feature, |
3192 | &pending_aliases); | |
b5ffee31 | 3193 | |
0a5954bd SC |
3194 | /* Search for the first floating point register (by any alias), to |
3195 | determine the bitsize. */ | |
3196 | int bitsize = -1; | |
3197 | const auto &fp0 = riscv_freg_feature.registers[0]; | |
3198 | ||
3199 | for (const char *name : fp0.names) | |
3200 | { | |
3201 | if (tdesc_unnumbered_register (feature_fpu, name)) | |
3202 | { | |
3203 | bitsize = tdesc_register_bitsize (feature_fpu, name); | |
3204 | break; | |
3205 | } | |
3206 | } | |
3207 | ||
3208 | gdb_assert (bitsize != -1); | |
b5ffee31 | 3209 | features.flen = (bitsize / 8); |
b5ffee31 AB |
3210 | |
3211 | if (riscv_debug_gdbarch) | |
3212 | fprintf_filtered | |
3213 | (gdb_stdlog, | |
3214 | "From target-description, flen = %d\n", bitsize); | |
3215 | } | |
3216 | else | |
3217 | { | |
3218 | features.flen = 0; | |
b5ffee31 AB |
3219 | |
3220 | if (riscv_debug_gdbarch) | |
3221 | fprintf_filtered | |
3222 | (gdb_stdlog, | |
3223 | "No FPU in target-description, assume soft-float ABI\n"); | |
3224 | } | |
3225 | ||
3226 | if (feature_virtual) | |
3227 | riscv_check_tdesc_feature (tdesc_data, feature_virtual, | |
767a879e AB |
3228 | &riscv_virtual_feature, |
3229 | &pending_aliases); | |
b5ffee31 AB |
3230 | |
3231 | if (feature_csr) | |
3232 | riscv_check_tdesc_feature (tdesc_data, feature_csr, | |
767a879e AB |
3233 | &riscv_csr_feature, |
3234 | &pending_aliases); | |
b5ffee31 AB |
3235 | |
3236 | if (!valid_p) | |
3237 | { | |
3238 | if (riscv_debug_gdbarch) | |
3239 | fprintf_unfiltered (gdb_stdlog, "Target description is not valid\n"); | |
3240 | tdesc_data_cleanup (tdesc_data); | |
3241 | return NULL; | |
3242 | } | |
3243 | ||
90af0679 AB |
3244 | /* Have a look at what the supplied (if any) bfd object requires of the |
3245 | target, then check that this matches with what the target is | |
3246 | providing. */ | |
113b7b81 | 3247 | struct riscv_gdbarch_features abi_features |
90af0679 | 3248 | = riscv_features_from_gdbarch_info (info); |
113b7b81 AB |
3249 | /* In theory a binary compiled for RV32 could run on an RV64 target, |
3250 | however, this has not been tested in GDB yet, so for now we require | |
3251 | that the requested xlen match the targets xlen. */ | |
3252 | if (abi_features.xlen != 0 && abi_features.xlen != features.xlen) | |
90af0679 | 3253 | error (_("bfd requires xlen %d, but target has xlen %d"), |
113b7b81 AB |
3254 | abi_features.xlen, features.xlen); |
3255 | /* We do support running binaries compiled for 32-bit float on targets | |
3256 | with 64-bit float, so we only complain if the binary requires more | |
3257 | than the target has available. */ | |
3258 | if (abi_features.flen > features.flen) | |
90af0679 | 3259 | error (_("bfd requires flen %d, but target has flen %d"), |
113b7b81 | 3260 | abi_features.flen, features.flen); |
90af0679 | 3261 | |
113b7b81 AB |
3262 | /* If the ABI_FEATURES xlen is 0 then this indicates we got no useful abi |
3263 | features from the INFO object. In this case we assume that the xlen | |
3264 | abi matches the hardware. */ | |
3265 | if (abi_features.xlen == 0) | |
3266 | abi_features.xlen = features.xlen; | |
90af0679 | 3267 | |
dbbb1059 AB |
3268 | /* Find a candidate among the list of pre-declared architectures. */ |
3269 | for (arches = gdbarch_list_lookup_by_info (arches, &info); | |
3270 | arches != NULL; | |
3271 | arches = gdbarch_list_lookup_by_info (arches->next, &info)) | |
b5ffee31 AB |
3272 | { |
3273 | /* Check that the feature set of the ARCHES matches the feature set | |
3274 | we are looking for. If it doesn't then we can't reuse this | |
3275 | gdbarch. */ | |
3276 | struct gdbarch_tdep *other_tdep = gdbarch_tdep (arches->gdbarch); | |
3277 | ||
113b7b81 AB |
3278 | if (other_tdep->isa_features != features |
3279 | || other_tdep->abi_features != abi_features) | |
b5ffee31 AB |
3280 | continue; |
3281 | ||
3282 | break; | |
3283 | } | |
3284 | ||
3285 | if (arches != NULL) | |
3286 | { | |
3287 | tdesc_data_cleanup (tdesc_data); | |
dbbb1059 | 3288 | return arches->gdbarch; |
b5ffee31 | 3289 | } |
dbbb1059 AB |
3290 | |
3291 | /* None found, so create a new architecture from the information provided. */ | |
b5ffee31 | 3292 | tdep = new (struct gdbarch_tdep); |
dbbb1059 | 3293 | gdbarch = gdbarch_alloc (&info, tdep); |
113b7b81 AB |
3294 | tdep->isa_features = features; |
3295 | tdep->abi_features = abi_features; | |
dbbb1059 AB |
3296 | |
3297 | /* Target data types. */ | |
3298 | set_gdbarch_short_bit (gdbarch, 16); | |
3299 | set_gdbarch_int_bit (gdbarch, 32); | |
3300 | set_gdbarch_long_bit (gdbarch, riscv_isa_xlen (gdbarch) * 8); | |
3301 | set_gdbarch_long_long_bit (gdbarch, 64); | |
3302 | set_gdbarch_float_bit (gdbarch, 32); | |
3303 | set_gdbarch_double_bit (gdbarch, 64); | |
3304 | set_gdbarch_long_double_bit (gdbarch, 128); | |
3305 | set_gdbarch_long_double_format (gdbarch, floatformats_ia64_quad); | |
3306 | set_gdbarch_ptr_bit (gdbarch, riscv_isa_xlen (gdbarch) * 8); | |
3307 | set_gdbarch_char_signed (gdbarch, 0); | |
a9158a86 | 3308 | set_gdbarch_type_align (gdbarch, riscv_type_align); |
dbbb1059 AB |
3309 | |
3310 | /* Information about the target architecture. */ | |
3311 | set_gdbarch_return_value (gdbarch, riscv_return_value); | |
3312 | set_gdbarch_breakpoint_kind_from_pc (gdbarch, riscv_breakpoint_kind_from_pc); | |
3313 | set_gdbarch_sw_breakpoint_from_kind (gdbarch, riscv_sw_breakpoint_from_kind); | |
5a77b1b4 | 3314 | set_gdbarch_have_nonsteppable_watchpoint (gdbarch, 1); |
dbbb1059 | 3315 | |
dbbb1059 | 3316 | /* Functions to analyze frames. */ |
dbbb1059 AB |
3317 | set_gdbarch_skip_prologue (gdbarch, riscv_skip_prologue); |
3318 | set_gdbarch_inner_than (gdbarch, core_addr_lessthan); | |
3319 | set_gdbarch_frame_align (gdbarch, riscv_frame_align); | |
3320 | ||
dbbb1059 AB |
3321 | /* Functions handling dummy frames. */ |
3322 | set_gdbarch_call_dummy_location (gdbarch, ON_STACK); | |
3323 | set_gdbarch_push_dummy_code (gdbarch, riscv_push_dummy_code); | |
3324 | set_gdbarch_push_dummy_call (gdbarch, riscv_push_dummy_call); | |
dbbb1059 AB |
3325 | |
3326 | /* Frame unwinders. Use DWARF debug info if available, otherwise use our own | |
3327 | unwinder. */ | |
3328 | dwarf2_append_unwinders (gdbarch); | |
3329 | frame_unwind_append_unwinder (gdbarch, &riscv_frame_unwind); | |
3330 | ||
b5ffee31 AB |
3331 | /* Register architecture. */ |
3332 | riscv_add_reggroups (gdbarch); | |
3333 | ||
fb44d95a AB |
3334 | /* Internal <-> external register number maps. */ |
3335 | set_gdbarch_dwarf2_reg_to_regnum (gdbarch, riscv_dwarf_reg_to_regnum); | |
3336 | ||
b5ffee31 AB |
3337 | /* We reserve all possible register numbers for the known registers. |
3338 | This means the target description mechanism will add any target | |
3339 | specific registers after this number. This helps make debugging GDB | |
3340 | just a little easier. */ | |
3341 | set_gdbarch_num_regs (gdbarch, RISCV_LAST_REGNUM + 1); | |
3342 | ||
3343 | /* We don't have to provide the count of 0 here (its the default) but | |
3344 | include this line to make it explicit that, right now, we don't have | |
3345 | any pseudo registers on RISC-V. */ | |
3346 | set_gdbarch_num_pseudo_regs (gdbarch, 0); | |
3347 | ||
3348 | /* Some specific register numbers GDB likes to know about. */ | |
3349 | set_gdbarch_sp_regnum (gdbarch, RISCV_SP_REGNUM); | |
3350 | set_gdbarch_pc_regnum (gdbarch, RISCV_PC_REGNUM); | |
3351 | ||
3352 | set_gdbarch_print_registers_info (gdbarch, riscv_print_registers_info); | |
3353 | ||
3354 | /* Finalise the target description registers. */ | |
3355 | tdesc_use_registers (gdbarch, tdesc, tdesc_data); | |
3356 | ||
3357 | /* Override the register type callback setup by the target description | |
3358 | mechanism. This allows us to provide special type for floating point | |
3359 | registers. */ | |
3360 | set_gdbarch_register_type (gdbarch, riscv_register_type); | |
3361 | ||
3362 | /* Override the register name callback setup by the target description | |
3363 | mechanism. This allows us to force our preferred names for the | |
3364 | registers, no matter what the target description called them. */ | |
3365 | set_gdbarch_register_name (gdbarch, riscv_register_name); | |
3366 | ||
3367 | /* Override the register group callback setup by the target description | |
3368 | mechanism. This allows us to force registers into the groups we | |
3369 | want, ignoring what the target tells us. */ | |
3370 | set_gdbarch_register_reggroup_p (gdbarch, riscv_register_reggroup_p); | |
3371 | ||
767a879e AB |
3372 | /* Create register aliases for alternative register names. We only |
3373 | create aliases for registers which were mentioned in the target | |
3374 | description. */ | |
3375 | for (const auto &alias : pending_aliases) | |
3376 | alias.create (gdbarch); | |
dbbb1059 | 3377 | |
ff371ec9 JW |
3378 | /* Compile command hooks. */ |
3379 | set_gdbarch_gcc_target_options (gdbarch, riscv_gcc_target_options); | |
3380 | set_gdbarch_gnu_triplet_regexp (gdbarch, riscv_gnu_triplet_regexp); | |
3381 | ||
117a0e99 JW |
3382 | /* Hook in OS ABI-specific overrides, if they have been registered. */ |
3383 | gdbarch_init_osabi (info, gdbarch); | |
3384 | ||
db3ad2f0 TT |
3385 | register_riscv_ravenscar_ops (gdbarch); |
3386 | ||
dbbb1059 AB |
3387 | return gdbarch; |
3388 | } | |
3389 | ||
5c720ed8 JW |
3390 | /* This decodes the current instruction and determines the address of the |
3391 | next instruction. */ | |
3392 | ||
3393 | static CORE_ADDR | |
3394 | riscv_next_pc (struct regcache *regcache, CORE_ADDR pc) | |
3395 | { | |
3396 | struct gdbarch *gdbarch = regcache->arch (); | |
3397 | struct riscv_insn insn; | |
3398 | CORE_ADDR next_pc; | |
3399 | ||
3400 | insn.decode (gdbarch, pc); | |
3401 | next_pc = pc + insn.length (); | |
3402 | ||
3403 | if (insn.opcode () == riscv_insn::JAL) | |
3404 | next_pc = pc + insn.imm_signed (); | |
3405 | else if (insn.opcode () == riscv_insn::JALR) | |
3406 | { | |
3407 | LONGEST source; | |
3408 | regcache->cooked_read (insn.rs1 (), &source); | |
3409 | next_pc = (source + insn.imm_signed ()) & ~(CORE_ADDR) 0x1; | |
3410 | } | |
3411 | else if (insn.opcode () == riscv_insn::BEQ) | |
3412 | { | |
3413 | LONGEST src1, src2; | |
3414 | regcache->cooked_read (insn.rs1 (), &src1); | |
3415 | regcache->cooked_read (insn.rs2 (), &src2); | |
3416 | if (src1 == src2) | |
3417 | next_pc = pc + insn.imm_signed (); | |
3418 | } | |
3419 | else if (insn.opcode () == riscv_insn::BNE) | |
3420 | { | |
3421 | LONGEST src1, src2; | |
3422 | regcache->cooked_read (insn.rs1 (), &src1); | |
3423 | regcache->cooked_read (insn.rs2 (), &src2); | |
3424 | if (src1 != src2) | |
3425 | next_pc = pc + insn.imm_signed (); | |
3426 | } | |
3427 | else if (insn.opcode () == riscv_insn::BLT) | |
3428 | { | |
3429 | LONGEST src1, src2; | |
3430 | regcache->cooked_read (insn.rs1 (), &src1); | |
3431 | regcache->cooked_read (insn.rs2 (), &src2); | |
3432 | if (src1 < src2) | |
3433 | next_pc = pc + insn.imm_signed (); | |
3434 | } | |
3435 | else if (insn.opcode () == riscv_insn::BGE) | |
3436 | { | |
3437 | LONGEST src1, src2; | |
3438 | regcache->cooked_read (insn.rs1 (), &src1); | |
3439 | regcache->cooked_read (insn.rs2 (), &src2); | |
3440 | if (src1 >= src2) | |
3441 | next_pc = pc + insn.imm_signed (); | |
3442 | } | |
3443 | else if (insn.opcode () == riscv_insn::BLTU) | |
3444 | { | |
3445 | ULONGEST src1, src2; | |
3446 | regcache->cooked_read (insn.rs1 (), &src1); | |
3447 | regcache->cooked_read (insn.rs2 (), &src2); | |
3448 | if (src1 < src2) | |
3449 | next_pc = pc + insn.imm_signed (); | |
3450 | } | |
3451 | else if (insn.opcode () == riscv_insn::BGEU) | |
3452 | { | |
3453 | ULONGEST src1, src2; | |
3454 | regcache->cooked_read (insn.rs1 (), &src1); | |
3455 | regcache->cooked_read (insn.rs2 (), &src2); | |
3456 | if (src1 >= src2) | |
3457 | next_pc = pc + insn.imm_signed (); | |
3458 | } | |
3459 | ||
3460 | return next_pc; | |
3461 | } | |
3462 | ||
3463 | /* We can't put a breakpoint in the middle of a lr/sc atomic sequence, so look | |
3464 | for the end of the sequence and put the breakpoint there. */ | |
3465 | ||
3466 | static bool | |
3467 | riscv_next_pc_atomic_sequence (struct regcache *regcache, CORE_ADDR pc, | |
3468 | CORE_ADDR *next_pc) | |
3469 | { | |
3470 | struct gdbarch *gdbarch = regcache->arch (); | |
3471 | struct riscv_insn insn; | |
3472 | CORE_ADDR cur_step_pc = pc; | |
3473 | CORE_ADDR last_addr = 0; | |
3474 | ||
3475 | /* First instruction has to be a load reserved. */ | |
3476 | insn.decode (gdbarch, cur_step_pc); | |
3477 | if (insn.opcode () != riscv_insn::LR) | |
3478 | return false; | |
3479 | cur_step_pc = cur_step_pc + insn.length (); | |
3480 | ||
3481 | /* Next instruction should be branch to exit. */ | |
3482 | insn.decode (gdbarch, cur_step_pc); | |
3483 | if (insn.opcode () != riscv_insn::BNE) | |
3484 | return false; | |
3485 | last_addr = cur_step_pc + insn.imm_signed (); | |
3486 | cur_step_pc = cur_step_pc + insn.length (); | |
3487 | ||
3488 | /* Next instruction should be store conditional. */ | |
3489 | insn.decode (gdbarch, cur_step_pc); | |
3490 | if (insn.opcode () != riscv_insn::SC) | |
3491 | return false; | |
3492 | cur_step_pc = cur_step_pc + insn.length (); | |
3493 | ||
3494 | /* Next instruction should be branch to start. */ | |
3495 | insn.decode (gdbarch, cur_step_pc); | |
3496 | if (insn.opcode () != riscv_insn::BNE) | |
3497 | return false; | |
3498 | if (pc != (cur_step_pc + insn.imm_signed ())) | |
3499 | return false; | |
3500 | cur_step_pc = cur_step_pc + insn.length (); | |
3501 | ||
3502 | /* We should now be at the end of the sequence. */ | |
3503 | if (cur_step_pc != last_addr) | |
3504 | return false; | |
3505 | ||
3506 | *next_pc = cur_step_pc; | |
3507 | return true; | |
3508 | } | |
3509 | ||
3510 | /* This is called just before we want to resume the inferior, if we want to | |
3511 | single-step it but there is no hardware or kernel single-step support. We | |
3512 | find the target of the coming instruction and breakpoint it. */ | |
3513 | ||
3514 | std::vector<CORE_ADDR> | |
3515 | riscv_software_single_step (struct regcache *regcache) | |
3516 | { | |
3517 | CORE_ADDR pc, next_pc; | |
3518 | ||
3519 | pc = regcache_read_pc (regcache); | |
3520 | ||
3521 | if (riscv_next_pc_atomic_sequence (regcache, pc, &next_pc)) | |
3522 | return {next_pc}; | |
3523 | ||
3524 | next_pc = riscv_next_pc (regcache, pc); | |
3525 | ||
3526 | return {next_pc}; | |
3527 | } | |
3528 | ||
b5ffee31 AB |
3529 | /* Create RISC-V specific reggroups. */ |
3530 | ||
3531 | static void | |
3532 | riscv_init_reggroups () | |
3533 | { | |
3534 | csr_reggroup = reggroup_new ("csr", USER_REGGROUP); | |
3535 | } | |
3536 | ||
6c265988 | 3537 | void _initialize_riscv_tdep (); |
dbbb1059 | 3538 | void |
6c265988 | 3539 | _initialize_riscv_tdep () |
dbbb1059 | 3540 | { |
b5ffee31 AB |
3541 | riscv_create_csr_aliases (); |
3542 | riscv_init_reggroups (); | |
3543 | ||
dbbb1059 AB |
3544 | gdbarch_register (bfd_arch_riscv, riscv_gdbarch_init, NULL); |
3545 | ||
dbbb1059 AB |
3546 | /* Add root prefix command for all "set debug riscv" and "show debug |
3547 | riscv" commands. */ | |
0743fc83 TT |
3548 | add_basic_prefix_cmd ("riscv", no_class, |
3549 | _("RISC-V specific debug commands."), | |
3550 | &setdebugriscvcmdlist, "set debug riscv ", 0, | |
3551 | &setdebuglist); | |
dbbb1059 | 3552 | |
0743fc83 TT |
3553 | add_show_prefix_cmd ("riscv", no_class, |
3554 | _("RISC-V specific debug commands."), | |
3555 | &showdebugriscvcmdlist, "show debug riscv ", 0, | |
3556 | &showdebuglist); | |
dbbb1059 | 3557 | |
f37bc8b1 JB |
3558 | add_setshow_zuinteger_cmd ("breakpoints", class_maintenance, |
3559 | &riscv_debug_breakpoints, _("\ | |
3560 | Set riscv breakpoint debugging."), _("\ | |
3561 | Show riscv breakpoint debugging."), _("\ | |
3562 | When non-zero, print debugging information for the riscv specific parts\n\ | |
3563 | of the breakpoint mechanism."), | |
3564 | NULL, | |
3565 | show_riscv_debug_variable, | |
3566 | &setdebugriscvcmdlist, &showdebugriscvcmdlist); | |
3567 | ||
dbbb1059 AB |
3568 | add_setshow_zuinteger_cmd ("infcall", class_maintenance, |
3569 | &riscv_debug_infcall, _("\ | |
3570 | Set riscv inferior call debugging."), _("\ | |
3571 | Show riscv inferior call debugging."), _("\ | |
3572 | When non-zero, print debugging information for the riscv specific parts\n\ | |
3573 | of the inferior call mechanism."), | |
3574 | NULL, | |
3575 | show_riscv_debug_variable, | |
3576 | &setdebugriscvcmdlist, &showdebugriscvcmdlist); | |
78a3b0fa AB |
3577 | |
3578 | add_setshow_zuinteger_cmd ("unwinder", class_maintenance, | |
3579 | &riscv_debug_unwinder, _("\ | |
3580 | Set riscv stack unwinding debugging."), _("\ | |
3581 | Show riscv stack unwinding debugging."), _("\ | |
3582 | When non-zero, print debugging information for the riscv specific parts\n\ | |
3583 | of the stack unwinding mechanism."), | |
3584 | NULL, | |
3585 | show_riscv_debug_variable, | |
3586 | &setdebugriscvcmdlist, &showdebugriscvcmdlist); | |
b5ffee31 AB |
3587 | |
3588 | add_setshow_zuinteger_cmd ("gdbarch", class_maintenance, | |
3589 | &riscv_debug_gdbarch, _("\ | |
3590 | Set riscv gdbarch initialisation debugging."), _("\ | |
3591 | Show riscv gdbarch initialisation debugging."), _("\ | |
3592 | When non-zero, print debugging information for the riscv gdbarch\n\ | |
3593 | initialisation process."), | |
3594 | NULL, | |
3595 | show_riscv_debug_variable, | |
3596 | &setdebugriscvcmdlist, &showdebugriscvcmdlist); | |
dbbb1059 AB |
3597 | |
3598 | /* Add root prefix command for all "set riscv" and "show riscv" commands. */ | |
0743fc83 TT |
3599 | add_basic_prefix_cmd ("riscv", no_class, |
3600 | _("RISC-V specific commands."), | |
3601 | &setriscvcmdlist, "set riscv ", 0, &setlist); | |
dbbb1059 | 3602 | |
0743fc83 TT |
3603 | add_show_prefix_cmd ("riscv", no_class, |
3604 | _("RISC-V specific commands."), | |
3605 | &showriscvcmdlist, "show riscv ", 0, &showlist); | |
dbbb1059 AB |
3606 | |
3607 | ||
3608 | use_compressed_breakpoints = AUTO_BOOLEAN_AUTO; | |
3609 | add_setshow_auto_boolean_cmd ("use-compressed-breakpoints", no_class, | |
3610 | &use_compressed_breakpoints, | |
3611 | _("\ | |
3612 | Set debugger's use of compressed breakpoints."), _(" \ | |
3613 | Show debugger's use of compressed breakpoints."), _("\ | |
f37bc8b1 JB |
3614 | Debugging compressed code requires compressed breakpoints to be used. If\n\ |
3615 | left to 'auto' then gdb will use them if the existing instruction is a\n\ | |
3616 | compressed instruction. If that doesn't give the correct behavior, then\n\ | |
3617 | this option can be used."), | |
dbbb1059 AB |
3618 | NULL, |
3619 | show_use_compressed_breakpoints, | |
3620 | &setriscvcmdlist, | |
3621 | &showriscvcmdlist); | |
3622 | } |