projects / deliverable / binutils-gdb.git / blame
| Commit | Line | Data |
|---|---|---|
| 35c08157 | 1 | /* nds32.h -- Header file for nds32 opcode table |
| 82704155 | 2 | Copyright (C) 2012-2019 Free Software Foundation, Inc. |
| 35c08157 KLC |
3 | Contributed by Andes Technology Corporation. |
| 4 | ||
| 5 | This program is free software; you can redistribute it and/or modify | |
| 6 | it under the terms of the GNU General Public License as published by | |
| 7 | the Free Software Foundation; either version 3, or (at your option) | |
| 8 | any later version. | |
| 9 | ||
| 10 | This program is distributed in the hope that it will be useful, | |
| 11 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
| 12 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
| 13 | GNU General Public License for more details. | |
| 14 | ||
| 15 | You should have received a copy of the GNU General Public License | |
| 16 | along with this program; if not, write to the Free Software | |
| 17 | Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA | |
| 18 | 02110-1301, USA. */ | |
| 19 | ||
| 20 | #ifndef OPCODE_NDS32_H | |
| 21 | #define OPCODE_NDS32_H | |
| 22 | ||
| 23 | /* Registers. */ | |
| fbaf61ad NC |
24 | #define REG_R0 (0) |
| 25 | #define REG_R5 (5) | |
| 26 | #define REG_R8 (8) | |
| 27 | #define REG_R10 (10) | |
| 28 | #define REG_R12 (12) | |
| 29 | #define REG_R15 (15) | |
| 30 | #define REG_R16 (16) | |
| 31 | #define REG_R20 (20) | |
| 32 | #define REG_TA (15) | |
| 33 | #define REG_TP (25) | |
| 34 | #define REG_FP (28) | |
| 35 | #define REG_GP (29) | |
| 36 | #define REG_LP (30) | |
| 37 | #define REG_SP (31) | |
| 35c08157 KLC |
38 | \f |
| 39 | /* Macros for extracting fields or making an instruction. */ | |
| 609332f1 | 40 | static const int nds32_r45map[] ATTRIBUTE_UNUSED = |
| 35c08157 KLC |
41 | { |
| 42 | 0, 1, 2, 3, 4, 5, 6, 7, | |
| 43 | 8, 9, 10, 11, 16, 17, 18, 19 | |
| 44 | }; | |
| 45 | ||
| 609332f1 | 46 | static const int nds32_r54map[] ATTRIBUTE_UNUSED = |
| 35c08157 KLC |
47 | { |
| 48 | 0, 1, 2, 3, 4, 5, 6, 7, | |
| 49 | 8, 9, 10, 11, -1, -1, -1, -1, | |
| 50 | 12, 13, 14, 15, -1, -1, -1, -1, | |
| 51 | -1, -1, -1, -1, -1, -1, -1, -1 | |
| 52 | }; | |
| 53 | ||
| 4bdb25fe | 54 | #define N32_BIT(n) (1u << (n)) |
| 4ec521f2 | 55 | #define __MASK(n) (N32_BIT (n) - 1) |
| 35c08157 KLC |
56 | #define __MF(v, off, bs) (((v) & __MASK (bs)) << (off)) |
| 57 | #define __GF(v, off, bs) (((v) >> off) & __MASK (bs)) | |
| 4bdb25fe AM |
58 | #define __SEXT(v, bs) \ |
| 59 | ((((v) & __MASK ((bs))) ^ N32_BIT ((bs) - 1)) - N32_BIT ((bs) - 1)) | |
| 35c08157 KLC |
60 | |
| 61 | /* Make nds32 instructions. */ | |
| 62 | ||
| 63 | #define N32_TYPE4(op6, rt5, ra5, rb5, rd5, sub5) \ | |
| 64 | (__MF (N32_OP6_##op6, 25, 6) | __MF (rt5, 20, 5) \ | |
| 65 | | __MF (ra5, 15, 5) | __MF (rb5, 10, 5) \ | |
| 66 | | __MF (rd5, 5, 5) | __MF (sub5, 0, 5)) | |
| 67 | #define N32_TYPE3(op6, rt5, ra5, rb5, sub10) \ | |
| 68 | (N32_TYPE4 (op6, rt5, ra5, rb5, 0, 0) \ | |
| 69 | | __MF (sub10, 0, 10)) | |
| 70 | #define N32_TYPE2(op6, rt5, ra5, imm15) \ | |
| 71 | (N32_TYPE3 (op6, rt5, ra5, 0, 0) | __MF (imm15, 0, 15)) | |
| 72 | #define N32_TYPE1(op6, rt5, imm20) \ | |
| 73 | (N32_TYPE2 (op6, rt5, 0, 0) | __MF (imm20, 0, 20)) | |
| 74 | #define N32_TYPE0(op6, imm25) \ | |
| 75 | (N32_TYPE1 (op6, 0, 0) | __MF (imm25, 0, 25)) | |
| 76 | #define N32_ALU1(sub, rt, ra, rb) \ | |
| 77 | N32_TYPE4 (ALU1, rt, ra, rb, 0, N32_ALU1_##sub) | |
| 78 | #define N32_ALU1_SH(sub, rt, ra, rb, rd) \ | |
| 79 | N32_TYPE4 (ALU1, rt, ra, rb, rd, N32_ALU1_##sub) | |
| 80 | #define N32_ALU2(sub, rt, ra, rb) \ | |
| 81 | N32_TYPE3 (ALU2, rt, ra, rb, N32_ALU2_##sub) | |
| 82 | #define N32_BR1(sub, rt, ra, imm14s) \ | |
| 83 | N32_TYPE2 (BR1, rt, ra, (N32_BR1_##sub << 14) | (imm14s & __MASK (14))) | |
| 84 | #define N32_BR2(sub, rt, imm16s) \ | |
| 85 | N32_TYPE1 (BR2, rt, (N32_BR2_##sub << 16) | (imm16s & __MASK (16))) | |
| 86 | #define N32_BR3(sub, rt, imm11s, imm8s) \ | |
| 87 | N32_TYPE1 (BR3, rt, (N32_BR3_##sub << 19) \ | |
| 88 | | ((imm11s & __MASK (11)) << 8) \ | |
| 89 | | (imm8s & __MASK (8))) | |
| 90 | #define N32_JI(sub, imm24s) \ | |
| 91 | N32_TYPE0 (JI, (N32_JI_##sub << 24) | (imm24s & __MASK (24))) | |
| 92 | #define N32_JREG(sub, rt, rb, dtit, hint) \ | |
| 93 | N32_TYPE4(JREG, rt, 0, rb, (dtit << 3) | (hint & 7), N32_JREG_##sub) | |
| 94 | #define N32_MEM(sub, rt, ra, rb, sv) \ | |
| 95 | N32_TYPE3 (MEM, rt, ra, rb, (sv << 8) | N32_MEM_##sub) | |
| 96 | ||
| 97 | #define N16_TYPE55(op5, rt5, ra5) \ | |
| 98 | (0x8000 | __MF (N16_T55_##op5, 10, 5) | __MF (rt5, 5, 5) \ | |
| 99 | | __MF (ra5, 0, 5)) | |
| 100 | #define N16_TYPE45(op6, rt4, ra5) \ | |
| 101 | (0x8000 | __MF (N16_T45_##op6, 9, 6) | __MF (rt4, 5, 4) \ | |
| 102 | | __MF (ra5, 0, 5)) | |
| 103 | #define N16_TYPE333(op6, rt3, ra3, rb3) \ | |
| 104 | (0x8000 | __MF (N16_T333_##op6, 9, 6) | __MF (rt3, 6, 3) \ | |
| 105 | | __MF (ra3, 3, 3) | __MF (rb3, 0, 3)) | |
| 106 | #define N16_TYPE36(op6, rt3, imm6) \ | |
| 107 | (0x8000 | __MF (N16_T36_##op6, 9, 6) | __MF (rt3, 6, 3) \ | |
| 108 | | __MF (imm6, 0, 6)) | |
| 109 | #define N16_TYPE38(op4, rt3, imm8) \ | |
| 110 | (0x8000 | __MF (N16_T38_##op4, 11, 4) | __MF (rt3, 8, 3) \ | |
| 111 | | __MF (imm8, 0, 8)) | |
| 112 | #define N16_TYPE37(op4, rt3, ls, imm7) \ | |
| 113 | (0x8000 | __MF (N16_T37_##op4, 11, 4) | __MF (rt3, 8, 3) \ | |
| 114 | | __MF (imm7, 0, 7) | __MF (ls, 7, 1)) | |
| 115 | #define N16_TYPE5(op10, imm5) \ | |
| 116 | (0x8000 | __MF (N16_T5_##op10, 5, 10) | __MF (imm5, 0, 5)) | |
| 117 | #define N16_TYPE8(op7, imm8) \ | |
| 118 | (0x8000 | __MF (N16_T8_##op7, 8, 7) | __MF (imm8, 0, 8)) | |
| 119 | #define N16_TYPE9(op6, imm9) \ | |
| 120 | (0x8000 | __MF (N16_T9_##op6, 9, 6) | __MF (imm9, 0, 9)) | |
| 121 | #define N16_TYPE10(op5, imm10) \ | |
| 122 | (0x8000 | __MF (N16_T10_##op5, 10, 5) | __MF (imm10, 0, 10)) | |
| 123 | #define N16_TYPE25(op8, re, imm5) \ | |
| 124 | (0x8000 | __MF (N16_T25_##op8, 7, 8) | __MF (re, 5, 2) \ | |
| 125 | | __MF (imm5, 0, 5)) | |
| 126 | ||
| 127 | #define N16_MISC33(sub, rt, ra) \ | |
| 128 | N16_TYPE333 (MISC33, rt, ra, N16_MISC33_##sub) | |
| 129 | #define N16_BFMI333(sub, rt, ra) \ | |
| 130 | N16_TYPE333 (BFMI333, rt, ra, N16_BFMI333_##sub) | |
| 131 | ||
| 132 | /* Get instruction fields. | |
| 133 | ||
| 134 | Macros used for handling 32-bit and 16-bit instructions are | |
| 135 | prefixed with N32_ and N16_ respectively. */ | |
| 136 | ||
| 137 | #define N32_OP6(insn) (((insn) >> 25) & 0x3f) | |
| 138 | #define N32_RT5(insn) (((insn) >> 20) & 0x1f) | |
| 139 | #define N32_RT53(insn) (N32_RT5 (insn) & 0x7) | |
| 140 | #define N32_RT54(insn) nds32_r54map[N32_RT5 (insn)] | |
| 141 | #define N32_RA5(insn) (((insn) >> 15) & 0x1f) | |
| 142 | #define N32_RA53(insn) (N32_RA5 (insn) & 0x7) | |
| 143 | #define N32_RA54(insn) nds32_r54map[N32_RA5 (insn)] | |
| 144 | #define N32_RB5(insn) (((insn) >> 10) & 0x1f) | |
| 145 | #define N32_UB5(insn) (((insn) >> 10) & 0x1f) | |
| 146 | #define N32_RB53(insn) (N32_RB5 (insn) & 0x7) | |
| 147 | #define N32_RB54(insn) nds32_r54map[N32_RB5 (insn)] | |
| 148 | #define N32_RD5(insn) (((insn) >> 5) & 0x1f) | |
| 149 | #define N32_SH5(insn) (((insn) >> 5) & 0x1f) | |
| 150 | #define N32_SUB5(insn) (((insn) >> 0) & 0x1f) | |
| fbaf61ad | 151 | #define N32_SUB6(insn) (((insn) >> 0) & 0x3f) |
| 35c08157 KLC |
152 | #define N32_SWID(insn) (((insn) >> 5) & 0x3ff) |
| 153 | #define N32_IMMU(insn, bs) ((insn) & __MASK (bs)) | |
| 4bdb25fe | 154 | #define N32_IMMS(insn, bs) ((signed) __SEXT ((insn), (bs))) |
| 35c08157 KLC |
155 | #define N32_IMM5U(insn) N32_IMMU (insn, 5) |
| 156 | #define N32_IMM12S(insn) N32_IMMS (insn, 12) | |
| 157 | #define N32_IMM14S(insn) N32_IMMS (insn, 14) | |
| 158 | #define N32_IMM15U(insn) N32_IMMU (insn, 15) | |
| 159 | #define N32_IMM15S(insn) N32_IMMS (insn, 15) | |
| 160 | #define N32_IMM16S(insn) N32_IMMS (insn, 16) | |
| 161 | #define N32_IMM17S(insn) N32_IMMS (insn, 17) | |
| 162 | #define N32_IMM20S(insn) N32_IMMS (insn, 20) | |
| 163 | #define N32_IMM20U(insn) N32_IMMU (insn, 20) | |
| 164 | #define N32_IMM24S(insn) N32_IMMS (insn, 24) | |
| 165 | ||
| 166 | #define N16_RT5(insn) (((insn) >> 5) & 0x1f) | |
| 167 | #define N16_RT4(insn) nds32_r45map[(((insn) >> 5) & 0xf)] | |
| 168 | #define N16_RT3(insn) (((insn) >> 6) & 0x7) | |
| 169 | #define N16_RT38(insn) (((insn) >> 8) & 0x7) | |
| 170 | #define N16_RT8(insn) (((insn) >> 8) & 0x7) | |
| 171 | #define N16_RA5(insn) ((insn) & 0x1f) | |
| 172 | #define N16_RA3(insn) (((insn) >> 3) & 0x7) | |
| 173 | #define N16_RB3(insn) ((insn) & 0x7) | |
| 174 | #define N16_IMM3U(insn) N32_IMMU (insn, 3) | |
| 175 | #define N16_IMM5U(insn) N32_IMMU (insn, 5) | |
| 176 | #define N16_IMM5S(insn) N32_IMMS (insn, 5) | |
| 177 | #define N16_IMM6U(insn) N32_IMMU (insn, 6) | |
| 178 | #define N16_IMM7U(insn) N32_IMMU (insn, 7) | |
| 179 | #define N16_IMM8S(insn) N32_IMMS (insn, 8) | |
| 180 | #define N16_IMM9U(insn) N32_IMMU (insn, 9) | |
| 181 | #define N16_IMM10S(insn) N32_IMMS (insn, 10) | |
| 182 | ||
| 183 | #define IS_WITHIN_U(v, n) (((v) >> n) == 0) | |
| 184 | #define IS_WITHIN_S(v, n) IS_WITHIN_U ((v) + (1 << ((n) - 1)), n) | |
| 185 | ||
| 186 | /* Get fields for specific instruction. */ | |
| 187 | #define N32_JREG_T(insn) (((insn) >> 8) & 0x3) | |
| 188 | #define N32_JREG_HINT(insn) (((insn) >> 5) & 0x7) | |
| 189 | #define N32_BR2_SUB(insn) (((insn) >> 16) & 0xf) | |
| 190 | #define N32_COP_SUB(insn) ((insn) & 0xf) | |
| 191 | #define N32_COP_CP(insn) (((insn) >> 4) & 0x3) | |
| 192 | ||
| 193 | /* Check fields. */ | |
| 194 | #define N32_IS_RT3(insn) (N32_RT5 (insn) < 8) | |
| 195 | #define N32_IS_RA3(insn) (N32_RA5 (insn) < 8) | |
| 196 | #define N32_IS_RB3(insn) (N32_RB5 (insn) < 8) | |
| 197 | #define N32_IS_RT4(insn) (nds32_r54map[N32_RT5 (insn)] != -1) | |
| 198 | #define N32_IS_RA4(insn) (nds32_r54map[N32_RA5 (insn)] != -1) | |
| 199 | #define N32_IS_RB4(insn) (nds32_r54map[N32_RB5 (insn)] != -1) | |
| 200 | ||
| 201 | ||
| 202 | /* These are opcodes for Nxx_TYPE macros. | |
| 203 | They are prefixed by corresponding TYPE to avoid misusing. */ | |
| 204 | ||
| 205 | enum n32_opcodes | |
| 206 | { | |
| 207 | /* Main opcodes (OP6). */ | |
| 208 | ||
| 209 | N32_OP6_LBI = 0x0, | |
| 210 | N32_OP6_LHI, | |
| 211 | N32_OP6_LWI, | |
| 212 | N32_OP6_LDI, | |
| 213 | N32_OP6_LBI_BI, | |
| 214 | N32_OP6_LHI_BI, | |
| 215 | N32_OP6_LWI_BI, | |
| 216 | N32_OP6_LDI_BI, | |
| 217 | ||
| 218 | N32_OP6_SBI = 0x8, | |
| 219 | N32_OP6_SHI, | |
| 220 | N32_OP6_SWI, | |
| 221 | N32_OP6_SDI, | |
| 222 | N32_OP6_SBI_BI, | |
| 223 | N32_OP6_SHI_BI, | |
| 224 | N32_OP6_SWI_BI, | |
| 225 | N32_OP6_SDI_BI, | |
| 226 | ||
| 227 | N32_OP6_LBSI = 0x10, | |
| 228 | N32_OP6_LHSI, | |
| 229 | N32_OP6_LWSI, | |
| 230 | N32_OP6_DPREFI, | |
| 231 | N32_OP6_LBSI_BI, | |
| 232 | N32_OP6_LHSI_BI, | |
| 233 | N32_OP6_LWSI_BI, | |
| 234 | N32_OP6_LBGP, | |
| 235 | ||
| 236 | N32_OP6_LWC = 0x18, | |
| 237 | N32_OP6_SWC, | |
| 238 | N32_OP6_LDC, | |
| 239 | N32_OP6_SDC, | |
| 240 | N32_OP6_MEM, | |
| 241 | N32_OP6_LSMW, | |
| 242 | N32_OP6_HWGP, | |
| 243 | N32_OP6_SBGP, | |
| 244 | ||
| 245 | N32_OP6_ALU1 = 0x20, | |
| 246 | N32_OP6_ALU2, | |
| 247 | N32_OP6_MOVI, | |
| 248 | N32_OP6_SETHI, | |
| 249 | N32_OP6_JI, | |
| 250 | N32_OP6_JREG, | |
| 251 | N32_OP6_BR1, | |
| 252 | N32_OP6_BR2, | |
| 253 | ||
| 254 | N32_OP6_ADDI = 0x28, | |
| 255 | N32_OP6_SUBRI, | |
| 256 | N32_OP6_ANDI, | |
| 257 | N32_OP6_XORI, | |
| 258 | N32_OP6_ORI, | |
| 259 | N32_OP6_BR3, | |
| 260 | N32_OP6_SLTI, | |
| 261 | N32_OP6_SLTSI, | |
| 262 | ||
| 263 | N32_OP6_AEXT = 0x30, | |
| 264 | N32_OP6_CEXT, | |
| 265 | N32_OP6_MISC, | |
| 266 | N32_OP6_BITCI, | |
| 267 | N32_OP6_0x34, | |
| 268 | N32_OP6_COP, | |
| 269 | N32_OP6_0x36, | |
| 270 | N32_OP6_0x37, | |
| 271 | ||
| 272 | N32_OP6_SIMD = 0x38, | |
| 273 | ||
| 274 | /* Sub-opcodes of specific opcode. */ | |
| 275 | ||
| 276 | /* bit-24 */ | |
| 277 | N32_BR1_BEQ = 0, | |
| 278 | N32_BR1_BNE = 1, | |
| 279 | ||
| 280 | /* bit[16:19] */ | |
| fbaf61ad | 281 | N32_BR2_SOP0 = 0, |
| 35c08157 KLC |
282 | N32_BR2_BEQZ = 2, |
| 283 | N32_BR2_BNEZ = 3, | |
| 284 | N32_BR2_BGEZ = 4, | |
| 285 | N32_BR2_BLTZ = 5, | |
| 286 | N32_BR2_BGTZ = 6, | |
| 287 | N32_BR2_BLEZ = 7, | |
| 288 | N32_BR2_BGEZAL = 0xc, | |
| 289 | N32_BR2_BLTZAL = 0xd, | |
| 290 | ||
| 291 | /* bit-19 */ | |
| 292 | N32_BR3_BEQC = 0, | |
| 293 | N32_BR3_BNEC = 1, | |
| 294 | ||
| 295 | /* bit-24 */ | |
| 296 | N32_JI_J = 0, | |
| 297 | N32_JI_JAL = 1, | |
| 298 | ||
| 299 | /* bit[0:4] */ | |
| 300 | N32_JREG_JR = 0, | |
| 301 | N32_JREG_JRAL = 1, | |
| 302 | N32_JREG_JRNEZ = 2, | |
| 303 | N32_JREG_JRALNEZ = 3, | |
| 304 | ||
| 305 | /* bit[0:4] */ | |
| 306 | N32_ALU1_ADD_SLLI = 0x0, | |
| 307 | N32_ALU1_SUB_SLLI, | |
| 308 | N32_ALU1_AND_SLLI, | |
| 309 | N32_ALU1_XOR_SLLI, | |
| 310 | N32_ALU1_OR_SLLI, | |
| 311 | N32_ALU1_ADD = 0x0, | |
| 312 | N32_ALU1_SUB, | |
| 313 | N32_ALU1_AND, | |
| 314 | N32_ALU1_XOR, | |
| 315 | N32_ALU1_OR, | |
| 316 | N32_ALU1_NOR, | |
| 317 | N32_ALU1_SLT, | |
| 318 | N32_ALU1_SLTS, | |
| 319 | N32_ALU1_SLLI = 0x8, | |
| 320 | N32_ALU1_SRLI, | |
| 321 | N32_ALU1_SRAI, | |
| 322 | N32_ALU1_ROTRI, | |
| 323 | N32_ALU1_SLL, | |
| 324 | N32_ALU1_SRL, | |
| 325 | N32_ALU1_SRA, | |
| 326 | N32_ALU1_ROTR, | |
| 327 | N32_ALU1_SEB = 0x10, | |
| 328 | N32_ALU1_SEH, | |
| 329 | N32_ALU1_BITC, | |
| 330 | N32_ALU1_ZEH, | |
| 331 | N32_ALU1_WSBH, | |
| 332 | N32_ALU1_OR_SRLI, | |
| 333 | N32_ALU1_DIVSR, | |
| 334 | N32_ALU1_DIVR, | |
| 335 | N32_ALU1_SVA = 0x18, | |
| 336 | N32_ALU1_SVS, | |
| 337 | N32_ALU1_CMOVZ, | |
| 338 | N32_ALU1_CMOVN, | |
| 339 | N32_ALU1_ADD_SRLI, | |
| 340 | N32_ALU1_SUB_SRLI, | |
| 341 | N32_ALU1_AND_SRLI, | |
| 342 | N32_ALU1_XOR_SRLI, | |
| 343 | ||
| 344 | /* bit[0:5], where bit[6:9] == 0 */ | |
| 345 | N32_ALU2_MAX = 0, | |
| 346 | N32_ALU2_MIN, | |
| 347 | N32_ALU2_AVE, | |
| 348 | N32_ALU2_ABS, | |
| 349 | N32_ALU2_CLIPS, | |
| 350 | N32_ALU2_CLIP, | |
| 351 | N32_ALU2_CLO, | |
| 352 | N32_ALU2_CLZ, | |
| 353 | N32_ALU2_BSET = 0x8, | |
| 354 | N32_ALU2_BCLR, | |
| 355 | N32_ALU2_BTGL, | |
| 356 | N32_ALU2_BTST, | |
| 357 | N32_ALU2_BSE, | |
| 358 | N32_ALU2_BSP, | |
| 359 | N32_ALU2_FFB, | |
| 360 | N32_ALU2_FFMISM, | |
| 361 | N32_ALU2_ADD_SC = 0x10, | |
| 362 | N32_ALU2_SUB_SC, | |
| 363 | N32_ALU2_ADD_WC, | |
| 364 | N32_ALU2_SUB_WC, | |
| 40c7a7cb | 365 | N32_ALU2_KMxy, |
| 35c08157 KLC |
366 | N32_ALU2_0x15, |
| 367 | N32_ALU2_0x16, | |
| 368 | N32_ALU2_FFZMISM, | |
| 40c7a7cb KLC |
369 | N32_ALU2_KADD = 0x18, |
| 370 | N32_ALU2_KSUB, | |
| fbaf61ad NC |
371 | N32_ALU2_KSLRAW, |
| 372 | N32_ALU2_KSLRAWu, | |
| 35c08157 KLC |
373 | N32_ALU2_MFUSR = 0x20, |
| 374 | N32_ALU2_MTUSR, | |
| 375 | N32_ALU2_0x22, | |
| 376 | N32_ALU2_0x23, | |
| 377 | N32_ALU2_MUL, | |
| 378 | N32_ALU2_0x25, | |
| 379 | N32_ALU2_0x26, | |
| 380 | N32_ALU2_MULTS64 = 0x28, | |
| 381 | N32_ALU2_MULT64, | |
| 382 | N32_ALU2_MADDS64, | |
| 383 | N32_ALU2_MADD64, | |
| 384 | N32_ALU2_MSUBS64, | |
| 385 | N32_ALU2_MSUB64, | |
| 386 | N32_ALU2_DIVS, | |
| 387 | N32_ALU2_DIV, | |
| fbaf61ad | 388 | N32_ALU2_ADD64 = 0x30, |
| 35c08157 | 389 | N32_ALU2_MULT32, |
| fbaf61ad | 390 | N32_ALU2_SMAL, |
| 35c08157 | 391 | N32_ALU2_MADD32, |
| fbaf61ad | 392 | N32_ALU2_SUB64, |
| 35c08157 | 393 | N32_ALU2_MSUB32, |
| fbaf61ad NC |
394 | N32_ALU2_0x36, |
| 395 | N32_ALU2_0x37, | |
| 396 | N32_ALU2_RADD64 = 0x38, | |
| 397 | N32_ALU2_URADD64, | |
| 398 | N32_ALU2_KADD64, | |
| 399 | N32_ALU2_UKADD64, | |
| 400 | N32_ALU2_RSUB64, | |
| 401 | N32_ALU2_URSUB64, | |
| 402 | N32_ALU2_KSUB64, | |
| 403 | N32_ALU2_UKSUB64, | |
| 404 | ||
| 405 | /* bit[0:5], where bit[6:9] = 0001 */ | |
| 406 | N32_ALU2_SMAR64 = 0x0, | |
| 407 | N32_ALU2_UMAR64, | |
| 408 | N32_ALU2_SMSR64, | |
| 409 | N32_ALU2_UMSR64, | |
| 410 | N32_ALU2_KMAR64, | |
| 411 | N32_ALU2_UKMAR64, | |
| 412 | N32_ALU2_KMSR64, | |
| 413 | N32_ALU2_UKMSR64, | |
| 414 | N32_ALU2_SMALDA = 0x8, | |
| 415 | N32_ALU2_SMSLDA, | |
| 416 | N32_ALU2_SMALDS, | |
| 417 | N32_ALU2_SMALBB, | |
| 35c08157 KLC |
418 | N32_ALU2_FFBI = 0xe, |
| 419 | N32_ALU2_FLMISM = 0xf, | |
| fbaf61ad NC |
420 | N32_ALU2_SMALXDA = 0x10, |
| 421 | N32_ALU2_SMSLXDA, | |
| 422 | N32_ALU2_SMALXDS, | |
| 423 | N32_ALU2_SMALBT, | |
| 424 | N32_ALU2_SMALDRS = 0x1a, | |
| 425 | N32_ALU2_SMALTT, | |
| 426 | N32_ALU2_RDOV = 0x20, | |
| 427 | N32_ALU2_CLROV, | |
| 35c08157 KLC |
428 | N32_ALU2_MULSR64 = 0x28, |
| 429 | N32_ALU2_MULR64 = 0x29, | |
| fbaf61ad NC |
430 | N32_ALU2_SMDS = 0x30, |
| 431 | N32_ALU2_SMXDS, | |
| 432 | N32_ALU2_SMDRS, | |
| 433 | N32_ALU2_MADDR32, | |
| 434 | N32_ALU2_KMADRS, | |
| 435 | N32_ALU2_MSUBR32, | |
| 436 | N32_ALU2_KMADS, | |
| 437 | N32_ALU2_KMAXDS, | |
| 438 | ||
| 439 | /* bit[0:5], where bit[6:9] = 0010 */ | |
| 440 | N32_ALU2_KADD16 = 0x0, | |
| 441 | N32_ALU2_KSUB16, | |
| 442 | N32_ALU2_KCRAS16, | |
| 443 | N32_ALU2_KCRSA16, | |
| 444 | N32_ALU2_KADD8, | |
| 445 | N32_ALU2_KSUB8, | |
| 446 | N32_ALU2_WEXT, | |
| 447 | N32_ALU2_WEXTI, | |
| 448 | N32_ALU2_UKADD16 = 0x8, | |
| 449 | N32_ALU2_UKSUB16, | |
| 450 | N32_ALU2_UKCRAS16, | |
| 451 | N32_ALU2_UKCRSA16, | |
| 452 | N32_ALU2_UKADD8, | |
| 453 | N32_ALU2_UKSUB8, | |
| 454 | N32_ALU2_ONEOP = 0xf, | |
| 455 | N32_ALU2_SMBB = 0x10, | |
| 456 | N32_ALU2_SMBT, | |
| 457 | N32_ALU2_SMTT, | |
| 458 | N32_ALU2_KMABB = 0x15, | |
| 459 | N32_ALU2_KMABT, | |
| 460 | N32_ALU2_KMATT, | |
| 461 | N32_ALU2_KMDA = 0x18, | |
| 462 | N32_ALU2_KMXDA, | |
| 463 | N32_ALU2_KMADA, | |
| 464 | N32_ALU2_KMAXDA, | |
| 465 | N32_ALU2_KMSDA, | |
| 466 | N32_ALU2_KMSXDA, | |
| 467 | N32_ALU2_RADD16 = 0x20, | |
| 468 | N32_ALU2_RSUB16, | |
| 469 | N32_ALU2_RCRAS16, | |
| 470 | N32_ALU2_RCRSA16, | |
| 471 | N32_ALU2_RADD8, | |
| 472 | N32_ALU2_RSUB8, | |
| 473 | N32_ALU2_RADDW, | |
| 474 | N32_ALU2_RSUBW, | |
| 475 | N32_ALU2_URADD16 = 0x28, | |
| 476 | N32_ALU2_URSUB16, | |
| 477 | N32_ALU2_URCRAS16, | |
| 478 | N32_ALU2_URCRSA16, | |
| 479 | N32_ALU2_URADD8, | |
| 480 | N32_ALU2_URSUB8, | |
| 481 | N32_ALU2_URADDW, | |
| 482 | N32_ALU2_URSUBW, | |
| 483 | N32_ALU2_ADD16 = 0x30, | |
| 484 | N32_ALU2_SUB16, | |
| 485 | N32_ALU2_CRAS16, | |
| 486 | N32_ALU2_CRSA16, | |
| 487 | N32_ALU2_ADD8, | |
| 488 | N32_ALU2_SUB8, | |
| 489 | N32_ALU2_BITREV, | |
| 490 | N32_ALU2_BITREVI, | |
| 491 | N32_ALU2_SMMUL = 0x38, | |
| 492 | N32_ALU2_SMMULu, | |
| 493 | N32_ALU2_KMMAC, | |
| 494 | N32_ALU2_KMMACu, | |
| 495 | N32_ALU2_KMMSB, | |
| 496 | N32_ALU2_KMMSBu, | |
| 497 | N32_ALU2_KWMMUL, | |
| 498 | N32_ALU2_KWMMULu, | |
| 499 | ||
| 500 | /* bit[0:5], where bit[6:9] = 0011 */ | |
| 501 | N32_ALU2_SMMWB = 0x0, | |
| 502 | N32_ALU2_SMMWBu, | |
| 503 | N32_ALU2_SMMWT, | |
| 504 | N32_ALU2_SMMWTu, | |
| 505 | N32_ALU2_KMMAWB, | |
| 506 | N32_ALU2_KMMAWBu, | |
| 507 | N32_ALU2_KMMAWT, | |
| 508 | N32_ALU2_KMMAWTu, | |
| 509 | N32_ALU2_PKTT16 = 0x8, | |
| 510 | N32_ALU2_PKTB16, | |
| 511 | N32_ALU2_PKBT16, | |
| 512 | N32_ALU2_PKBB16, | |
| 513 | N32_ALU2_0x10 = 0x10, | |
| 514 | N32_ALU2_SCLIP16, | |
| 515 | N32_ALU2_0x12, | |
| 516 | N32_ALU2_SMAX16, | |
| 517 | N32_ALU2_SMAX8 = 0x17, | |
| 518 | N32_ALU2_0x18 = 0x18, | |
| 519 | N32_ALU2_UCLIP16, | |
| 520 | N32_ALU2_0x1a, | |
| 521 | N32_ALU2_UMAX16, | |
| 522 | N32_ALU2_UMAX8 = 0x1f, | |
| 523 | N32_ALU2_SRA16 = 0x20, | |
| 524 | N32_ALU2_SRA16u, | |
| 525 | N32_ALU2_SRL16, | |
| 526 | N32_ALU2_SRL16u, | |
| 527 | N32_ALU2_SLL16, | |
| 528 | N32_ALU2_KSLRA16, | |
| 529 | N32_ALU2_KSLRA16u, | |
| 530 | N32_ALU2_SRAu, | |
| 531 | N32_ALU2_SRAI16 = 0x28, | |
| 532 | N32_ALU2_SRAI16u, | |
| 533 | N32_ALU2_SRLI16, | |
| 534 | N32_ALU2_SRLI16u, | |
| 535 | N32_ALU2_SLLI16, | |
| 536 | N32_ALU2_KSLLI16, | |
| 537 | N32_ALU2_KSLLI, | |
| 538 | N32_ALU2_SRAIu, | |
| 539 | N32_ALU2_CMPEQ16 = 0x30, | |
| 540 | N32_ALU2_SCMPLT16, | |
| 541 | N32_ALU2_SCMPLE16, | |
| 542 | N32_ALU2_SMIN16, | |
| 543 | N32_ALU2_CMPEQ8, | |
| 544 | N32_ALU2_SCMPLT8, | |
| 545 | N32_ALU2_SCMPLE8, | |
| 546 | N32_ALU2_SMIN8, | |
| 547 | N32_ALU2_0x38, | |
| 548 | N32_ALU2_UCMPLT16 = 0x39, | |
| 549 | N32_ALU2_UCMPLE16, | |
| 550 | N32_ALU2_UMIN16, | |
| 551 | N32_ALU2_0x3c, | |
| 552 | N32_ALU2_UCMPLT8, | |
| 553 | N32_ALU2_UCMPLE8, | |
| 554 | N32_ALU2_UMIN8, | |
| 35c08157 KLC |
555 | |
| 556 | /* bit[0:5] */ | |
| 557 | N32_MEM_LB = 0, | |
| 558 | N32_MEM_LH, | |
| 559 | N32_MEM_LW, | |
| 560 | N32_MEM_LD, | |
| 561 | N32_MEM_LB_BI, | |
| 562 | N32_MEM_LH_BI, | |
| 563 | N32_MEM_LW_BI, | |
| 564 | N32_MEM_LD_BI, | |
| 565 | N32_MEM_SB, | |
| 566 | N32_MEM_SH, | |
| 567 | N32_MEM_SW, | |
| 568 | N32_MEM_SD, | |
| 569 | N32_MEM_SB_BI, | |
| 570 | N32_MEM_SH_BI, | |
| 571 | N32_MEM_SW_BI, | |
| 572 | N32_MEM_SD_BI, | |
| 573 | N32_MEM_LBS, | |
| 574 | N32_MEM_LHS, | |
| 575 | N32_MEM_LWS, /* Not used. */ | |
| 576 | N32_MEM_DPREF, | |
| 577 | N32_MEM_LBS_BI, | |
| 578 | N32_MEM_LHS_BI, | |
| 579 | N32_MEM_LWS_BI, /* Not used. */ | |
| 580 | N32_MEM_0x17, /* Not used. */ | |
| 581 | N32_MEM_LLW, | |
| 582 | N32_MEM_SCW, | |
| 583 | N32_MEM_LBUP = 0x20, | |
| 584 | N32_MEM_LWUP = 0x22, | |
| 585 | N32_MEM_SBUP = 0x28, | |
| 586 | N32_MEM_SWUP = 0x2a, | |
| 587 | ||
| 588 | /* bit[0:1] */ | |
| 589 | N32_LSMW_LSMW = 0, | |
| 590 | N32_LSMW_LSMWA, | |
| 591 | N32_LSMW_LSMWZB, | |
| 592 | ||
| 593 | /* bit[2:4] */ | |
| 594 | N32_LSMW_BI = 0, | |
| 595 | N32_LSMW_BIM, | |
| 596 | N32_LSMW_BD, | |
| 597 | N32_LSMW_BDM, | |
| 598 | N32_LSMW_AI, | |
| 599 | N32_LSMW_AIM, | |
| 600 | N32_LSMW_AD, | |
| 601 | N32_LSMW_ADM, | |
| 602 | ||
| 603 | /* bit[0:4] */ | |
| 604 | N32_MISC_STANDBY = 0, | |
| 605 | N32_MISC_CCTL, | |
| 606 | N32_MISC_MFSR, | |
| 607 | N32_MISC_MTSR, | |
| 608 | N32_MISC_IRET, | |
| 609 | N32_MISC_TRAP, | |
| 610 | N32_MISC_TEQZ, | |
| 611 | N32_MISC_TNEZ, | |
| 612 | N32_MISC_DSB = 0x8, | |
| 613 | N32_MISC_ISB, | |
| 614 | N32_MISC_BREAK, | |
| 615 | N32_MISC_SYSCALL, | |
| 616 | N32_MISC_MSYNC, | |
| 617 | N32_MISC_ISYNC, | |
| 618 | N32_MISC_TLBOP, | |
| fbaf61ad NC |
619 | N32_MISC_SPECL, |
| 620 | N32_MISC_BPICK = 0x10, | |
| 35c08157 | 621 | |
| 40c7a7cb | 622 | /* bit[0:4] */ |
| 35c08157 KLC |
623 | N32_SIMD_PBSAD = 0, |
| 624 | N32_SIMD_PBSADA = 1, | |
| 625 | ||
| 626 | /* bit[0:3] */ | |
| 627 | N32_COP_CPE1 = 0, | |
| 628 | N32_COP_MFCP, | |
| 629 | N32_COP_CPLW, | |
| 630 | N32_COP_CPLD, | |
| 631 | N32_COP_CPE2, | |
| 632 | N32_COP_CPE3 = 8, | |
| 633 | N32_COP_MTCP, | |
| 634 | N32_COP_CPSW, | |
| 635 | N32_COP_CPSD, | |
| 636 | N32_COP_CPE4, | |
| 637 | ||
| 638 | /* cop/0 b[3:0] */ | |
| 639 | N32_FPU_FS1 = 0, | |
| 640 | N32_FPU_MFCP, | |
| 641 | N32_FPU_FLS, | |
| 642 | N32_FPU_FLD, | |
| 643 | N32_FPU_FS2, | |
| 644 | N32_FPU_FD1 = 8, | |
| 645 | N32_FPU_MTCP, | |
| 646 | N32_FPU_FSS, | |
| 647 | N32_FPU_FSD, | |
| 648 | N32_FPU_FD2, | |
| 649 | ||
| 650 | /* FS1 b[9:6] */ | |
| 651 | N32_FPU_FS1_FADDS = 0, | |
| 652 | N32_FPU_FS1_FSUBS, | |
| 653 | N32_FPU_FS1_FCPYNSS, | |
| 654 | N32_FPU_FS1_FCPYSS, | |
| 655 | N32_FPU_FS1_FMADDS, | |
| 656 | N32_FPU_FS1_FMSUBS, | |
| 657 | N32_FPU_FS1_FCMOVNS, | |
| 658 | N32_FPU_FS1_FCMOVZS, | |
| 659 | N32_FPU_FS1_FNMADDS, | |
| 660 | N32_FPU_FS1_FNMSUBS, | |
| 661 | N32_FPU_FS1_10, | |
| 662 | N32_FPU_FS1_11, | |
| 663 | N32_FPU_FS1_FMULS = 12, | |
| 664 | N32_FPU_FS1_FDIVS, | |
| 665 | N32_FPU_FS1_14, | |
| 666 | N32_FPU_FS1_F2OP = 15, | |
| 667 | ||
| 668 | /* FS1/F2OP b[14:10] */ | |
| 669 | N32_FPU_FS1_F2OP_FS2D = 0x00, | |
| 670 | N32_FPU_FS1_F2OP_FSQRTS = 0x01, | |
| 671 | N32_FPU_FS1_F2OP_FABSS = 0x05, | |
| 672 | N32_FPU_FS1_F2OP_FUI2S = 0x08, | |
| 673 | N32_FPU_FS1_F2OP_FSI2S = 0x0c, | |
| 674 | N32_FPU_FS1_F2OP_FS2UI = 0x10, | |
| 675 | N32_FPU_FS1_F2OP_FS2UI_Z = 0x14, | |
| 676 | N32_FPU_FS1_F2OP_FS2SI = 0x18, | |
| 677 | N32_FPU_FS1_F2OP_FS2SI_Z = 0x1c, | |
| 678 | ||
| 679 | /* FS2 b[9:6] */ | |
| 680 | N32_FPU_FS2_FCMPEQS = 0x0, | |
| 681 | N32_FPU_FS2_FCMPLTS = 0x2, | |
| 682 | N32_FPU_FS2_FCMPLES = 0x4, | |
| 683 | N32_FPU_FS2_FCMPUNS = 0x6, | |
| 684 | N32_FPU_FS2_FCMPEQS_E = 0x1, | |
| 685 | N32_FPU_FS2_FCMPLTS_E = 0x3, | |
| 686 | N32_FPU_FS2_FCMPLES_E = 0x5, | |
| 687 | N32_FPU_FS2_FCMPUNS_E = 0x7, | |
| 688 | ||
| 689 | /* FD1 b[9:6] */ | |
| 690 | N32_FPU_FD1_FADDD = 0, | |
| 691 | N32_FPU_FD1_FSUBD, | |
| 692 | N32_FPU_FD1_FCPYNSD, | |
| 693 | N32_FPU_FD1_FCPYSD, | |
| 694 | N32_FPU_FD1_FMADDD, | |
| 695 | N32_FPU_FD1_FMSUBD, | |
| 696 | N32_FPU_FD1_FCMOVND, | |
| 697 | N32_FPU_FD1_FCMOVZD, | |
| 698 | N32_FPU_FD1_FNMADDD, | |
| 699 | N32_FPU_FD1_FNMSUBD, | |
| 700 | N32_FPU_FD1_10, | |
| 701 | N32_FPU_FD1_11, | |
| 702 | N32_FPU_FD1_FMULD = 12, | |
| 703 | N32_FPU_FD1_FDIVD, | |
| 704 | N32_FPU_FD1_14, | |
| 705 | N32_FPU_FD1_F2OP = 15, | |
| 706 | ||
| 707 | /* FD1/F2OP b[14:10] */ | |
| 708 | N32_FPU_FD1_F2OP_FD2S = 0x00, | |
| 709 | N32_FPU_FD1_F2OP_FSQRTD = 0x01, | |
| 710 | N32_FPU_FD1_F2OP_FABSD = 0x05, | |
| 711 | N32_FPU_FD1_F2OP_FUI2D = 0x08, | |
| 712 | N32_FPU_FD1_F2OP_FSI2D = 0x0c, | |
| 713 | N32_FPU_FD1_F2OP_FD2UI = 0x10, | |
| 714 | N32_FPU_FD1_F2OP_FD2UI_Z = 0x14, | |
| 715 | N32_FPU_FD1_F2OP_FD2SI = 0x18, | |
| 716 | N32_FPU_FD1_F2OP_FD2SI_Z = 0x1c, | |
| 717 | ||
| 718 | /* FD2 b[9:6] */ | |
| 719 | N32_FPU_FD2_FCMPEQD = 0x0, | |
| 720 | N32_FPU_FD2_FCMPLTD = 0x2, | |
| 721 | N32_FPU_FD2_FCMPLED = 0x4, | |
| 722 | N32_FPU_FD2_FCMPUND = 0x6, | |
| 723 | N32_FPU_FD2_FCMPEQD_E = 0x1, | |
| 724 | N32_FPU_FD2_FCMPLTD_E = 0x3, | |
| 725 | N32_FPU_FD2_FCMPLED_E = 0x5, | |
| 726 | N32_FPU_FD2_FCMPUND_E = 0x7, | |
| 727 | ||
| 728 | /* MFCP b[9:6] */ | |
| 729 | N32_FPU_MFCP_FMFSR = 0x0, | |
| 730 | N32_FPU_MFCP_FMFDR = 0x1, | |
| 731 | N32_FPU_MFCP_XR = 0xc, | |
| 732 | ||
| 733 | /* MFCP/XR b[14:10] */ | |
| 734 | N32_FPU_MFCP_XR_FMFCFG = 0x0, | |
| 735 | N32_FPU_MFCP_XR_FMFCSR = 0x1, | |
| 736 | ||
| 737 | /* MTCP b[9:6] */ | |
| 738 | N32_FPU_MTCP_FMTSR = 0x0, | |
| 739 | N32_FPU_MTCP_FMTDR = 0x1, | |
| 740 | N32_FPU_MTCP_XR = 0xc, | |
| 741 | ||
| 742 | /* MTCP/XR b[14:10] */ | |
| 743 | N32_FPU_MTCP_XR_FMTCSR = 0x1 | |
| 744 | }; | |
| 745 | ||
| 746 | enum n16_opcodes | |
| 747 | { | |
| 748 | N16_T55_MOV55 = 0x0, | |
| 749 | N16_T55_MOVI55 = 0x1, | |
| 750 | ||
| 751 | N16_T45_0 = 0, | |
| 752 | N16_T45_ADD45 = 0x4, | |
| 753 | N16_T45_SUB45 = 0x5, | |
| 754 | N16_T45_ADDI45 = 0x6, | |
| 755 | N16_T45_SUBI45 = 0x7, | |
| 756 | N16_T45_SRAI45 = 0x8, | |
| 757 | N16_T45_SRLI45 = 0x9, | |
| 758 | N16_T45_LWI45_FE = 0x19, | |
| 759 | N16_T45_LWI450 = 0x1a, | |
| 760 | N16_T45_SWI450 = 0x1b, | |
| 761 | N16_T45_SLTS45 = 0x30, | |
| 762 | N16_T45_SLT45 = 0x31, | |
| 763 | N16_T45_SLTSI45 = 0x32, | |
| 764 | N16_T45_SLTI45 = 0x33, | |
| 765 | N16_T45_MOVPI45 = 0x3d, | |
| 766 | ||
| 767 | N15_T44_MOVD44 = 0x7d, | |
| 768 | ||
| 769 | N16_T333_0 = 0, | |
| 770 | N16_T333_SLLI333 = 0xa, | |
| 771 | N16_T333_BFMI333 = 0xb, | |
| 772 | N16_T333_ADD333 = 0xc, | |
| 773 | N16_T333_SUB333 = 0xd, | |
| 774 | N16_T333_ADDI333 = 0xe, | |
| 775 | N16_T333_SUBI333 = 0xf, | |
| 776 | N16_T333_LWI333 = 0x10, | |
| 777 | N16_T333_LWI333_BI = 0x11, | |
| 778 | N16_T333_LHI333 = 0x12, | |
| 779 | N16_T333_LBI333 = 0x13, | |
| 780 | N16_T333_SWI333 = 0x14, | |
| 781 | N16_T333_SWI333_BI = 0x15, | |
| 782 | N16_T333_SHI333 = 0x16, | |
| 783 | N16_T333_SBI333 = 0x17, | |
| 784 | N16_T333_MISC33 = 0x3f, | |
| 785 | ||
| 786 | N16_T36_ADDRI36_SP = 0x18, | |
| 787 | ||
| 788 | N16_T37_XWI37 = 0x7, | |
| 789 | N16_T37_XWI37SP = 0xe, | |
| 790 | ||
| 791 | N16_T38_BEQZ38 = 0x8, | |
| 792 | N16_T38_BNEZ38 = 0x9, | |
| 793 | N16_T38_BEQS38 = 0xa, | |
| 794 | N16_T38_BNES38 = 0xb, | |
| 795 | ||
| 796 | N16_T5_JR5 = 0x2e8, | |
| 797 | N16_T5_JRAL5 = 0x2e9, | |
| 798 | N16_T5_EX9IT = 0x2ea, | |
| 799 | /* 0x2eb reserved. */ | |
| 800 | N16_T5_RET5 = 0x2ec, | |
| 801 | N16_T5_ADD5PC = 0x2ed, | |
| 802 | /* 0x2e[ef] reserved. */ | |
| 803 | N16_T5_BREAK16 = 0x350, | |
| 804 | ||
| 805 | N16_T8_J8 = 0x55, | |
| 806 | N16_T8_BEQZS8 = 0x68, | |
| 807 | N16_T8_BNEZS8 = 0x69, | |
| 808 | ||
| 809 | /* N16_T9_BREAK16 = 0x35 | |
| 810 | Since v3, SWID of BREAK16 above 32 are used for encoding EX9.IT. */ | |
| 811 | N16_T9_EX9IT = 0x35, | |
| 812 | N16_T9_IFCALL9 = 0x3c, | |
| 813 | ||
| 814 | N16_T10_ADDI10S = 0x1b, | |
| 815 | ||
| 816 | N16_T25_PUSH25 = 0xf8, | |
| 817 | N16_T25_POP25 = 0xf9, | |
| 818 | ||
| 819 | /* Sub-opcodes. */ | |
| 820 | N16_MISC33_0 = 0, | |
| 821 | N16_MISC33_1 = 1, | |
| 822 | N16_MISC33_NEG33 = 2, | |
| 823 | N16_MISC33_NOT33 = 3, | |
| 824 | N16_MISC33_MUL33 = 4, | |
| 825 | N16_MISC33_XOR33 = 5, | |
| 826 | N16_MISC33_AND33 = 6, | |
| 827 | N16_MISC33_OR33 = 7, | |
| 828 | ||
| 829 | N16_BFMI333_ZEB33 = 0, | |
| 830 | N16_BFMI333_ZEH33 = 1, | |
| 831 | N16_BFMI333_SEB33 = 2, | |
| 832 | N16_BFMI333_SEH33 = 3, | |
| 833 | N16_BFMI333_XLSB33 = 4, | |
| 834 | N16_BFMI333_X11B33 = 5, | |
| 835 | N16_BFMI333_BMSKI33 = 6, | |
| 836 | N16_BFMI333_FEXTI33 = 7 | |
| 837 | }; | |
| 838 | \f | |
| 839 | /* These macros a deprecated. DO NOT use them anymore. | |
| 840 | And please help rewrite code used them. */ | |
| 841 | ||
| 842 | /* 32-bit instructions without operands. */ | |
| 843 | #define INSN_SETHI 0x46000000 | |
| 844 | #define INSN_ORI 0x58000000 | |
| 845 | #define INSN_JR 0x4a000000 | |
| 846 | #define INSN_RET 0x4a000020 | |
| 847 | #define INSN_JAL 0x49000000 | |
| 848 | #define INSN_J 0x48000000 | |
| 849 | #define INSN_JRAL 0x4a000001 | |
| 850 | #define INSN_BGEZAL 0x4e0c0000 | |
| 851 | #define INSN_BLTZAL 0x4e0d0000 | |
| 852 | #define INSN_BEQ 0x4c000000 | |
| 853 | #define INSN_BNE 0x4c004000 | |
| 854 | #define INSN_BEQZ 0x4e020000 | |
| 855 | #define INSN_BNEZ 0x4e030000 | |
| 856 | #define INSN_BGEZ 0x4e040000 | |
| 857 | #define INSN_BLTZ 0x4e050000 | |
| 858 | #define INSN_BGTZ 0x4e060000 | |
| 859 | #define INSN_BLEZ 0x4e070000 | |
| 860 | #define INSN_MOVI 0x44000000 | |
| 861 | #define INSN_ADDI 0x50000000 | |
| 862 | #define INSN_ANDI 0x54000000 | |
| 863 | #define INSN_LDI 0x06000000 | |
| 864 | #define INSN_SDI 0x16000000 | |
| fbaf61ad | 865 | #define INSN_LW 0x38000002 |
| 35c08157 KLC |
866 | #define INSN_LWI 0x04000000 |
| 867 | #define INSN_LWSI 0x24000000 | |
| 868 | #define INSN_LWIP 0x0c000000 | |
| 869 | #define INSN_LHI 0x02000000 | |
| 870 | #define INSN_LHSI 0x22000000 | |
| 871 | #define INSN_LBI 0x00000000 | |
| 872 | #define INSN_LBSI 0x20000000 | |
| 873 | #define INSN_SWI 0x14000000 | |
| 874 | #define INSN_SWIP 0x1c000000 | |
| 875 | #define INSN_SHI 0x12000000 | |
| 876 | #define INSN_SBI 0x10000000 | |
| 877 | #define INSN_SLTI 0x5c000000 | |
| 878 | #define INSN_SLTSI 0x5e000000 | |
| 879 | #define INSN_ADD 0x40000000 | |
| 880 | #define INSN_SUB 0x40000001 | |
| 881 | #define INSN_SLT 0x40000006 | |
| 882 | #define INSN_SLTS 0x40000007 | |
| 883 | #define INSN_SLLI 0x40000008 | |
| 884 | #define INSN_SRLI 0x40000009 | |
| 885 | #define INSN_SRAI 0x4000000a | |
| 886 | #define INSN_SEB 0x40000010 | |
| 887 | #define INSN_SEH 0x40000011 | |
| 888 | #define INSN_ZEB INSN_ANDI + 0xFF | |
| 889 | #define INSN_ZEH 0x40000013 | |
| 890 | #define INSN_BREAK 0x6400000a | |
| 891 | #define INSN_NOP 0x40000009 | |
| 892 | #define INSN_FLSI 0x30000000 | |
| 893 | #define INSN_FSSI 0x32000000 | |
| 894 | #define INSN_FLDI 0x34000000 | |
| 895 | #define INSN_FSDI 0x36000000 | |
| 896 | #define INSN_BEQC 0x5a000000 | |
| 897 | #define INSN_BNEC 0x5a080000 | |
| 898 | #define INSN_DSB 0x64000008 | |
| 899 | #define INSN_IFCALL 0x4e000000 | |
| 900 | #define INSN_IFRET 0x4a000060 | |
| 901 | #define INSN_BR1 0x4c000000 | |
| 902 | #define INSN_BR2 0x4e000000 | |
| 903 | ||
| 904 | /* 16-bit instructions without operand. */ | |
| 905 | #define INSN_MOV55 0x8000 | |
| 906 | #define INSN_MOVI55 0x8400 | |
| 907 | #define INSN_ADD45 0x8800 | |
| 908 | #define INSN_SUB45 0x8a00 | |
| 909 | #define INSN_ADDI45 0x8c00 | |
| 910 | #define INSN_SUBI45 0x8e00 | |
| 911 | #define INSN_SRAI45 0x9000 | |
| 912 | #define INSN_SRLI45 0x9200 | |
| 913 | #define INSN_SLLI333 0x9400 | |
| 914 | #define INSN_BFMI333 0x9600 | |
| 915 | #define INSN_ADD333 0x9800 | |
| 916 | #define INSN_SUB333 0x9a00 | |
| 917 | #define INSN_ADDI333 0x9c00 | |
| 918 | #define INSN_SUBI333 0x9e00 | |
| 919 | #define INSN_LWI333 0xa000 | |
| 920 | #define INSN_LWI333P 0xa200 | |
| 921 | #define INSN_LHI333 0xa400 | |
| 922 | #define INSN_LBI333 0xa600 | |
| 923 | #define INSN_SWI333 0xa800 | |
| 924 | #define INSN_SWI333P 0xaa00 | |
| 925 | #define INSN_SHI333 0xac00 | |
| 926 | #define INSN_SBI333 0xae00 | |
| 927 | #define INSN_RSV01 0xb000 | |
| 928 | #define INSN_RSV02 0xb200 | |
| 929 | #define INSN_LWI450 0xb400 | |
| 930 | #define INSN_SWI450 0xb600 | |
| 931 | #define INSN_LWI37 0xb800 | |
| 932 | #define INSN_SWI37 0xb880 | |
| 933 | #define INSN_BEQZ38 0xc000 | |
| 934 | #define INSN_BNEZ38 0xc800 | |
| 935 | #define INSN_BEQS38 0xd000 | |
| 936 | #define INSN_J8 0xd500 | |
| 937 | #define INSN_BNES38 0xd800 | |
| 938 | #define INSN_JR5 0xdd00 | |
| 939 | #define INSN_RET5 0xdd80 | |
| 940 | #define INSN_JRAL5 0xdd20 | |
| 941 | #define INSN_EX9_IT_2 0xdd40 | |
| 942 | #define INSN_SLTS45 0xe000 | |
| 943 | #define INSN_SLT45 0xe200 | |
| 944 | #define INSN_SLTSI45 0xe400 | |
| 945 | #define INSN_SLTI45 0xe600 | |
| 946 | #define INSN_BEQZS8 0xe800 | |
| 947 | #define INSN_BNEZS8 0xe900 | |
| 948 | #define INSN_BREAK16 0xea00 | |
| 949 | #define INSN_EX9_IT_1 0xea00 | |
| 950 | #define INSN_NOP16 0x9200 | |
| 951 | /* 16-bit version 2. */ | |
| 952 | #define INSN_ADDI10_SP 0xec00 | |
| 953 | #define INSN_LWI37SP 0xf000 | |
| 954 | #define INSN_SWI37SP 0xf080 | |
| 955 | /* 16-bit version 3. */ | |
| 956 | #define INSN_IFRET16 0x83ff | |
| 957 | #define INSN_ADDRI36_SP 0xb000 | |
| 958 | #define INSN_LWI45_FE 0xb200 | |
| 959 | #define INSN_IFCALL9 0xf800 | |
| 960 | #define INSN_MISC33 0xfe00 | |
| 961 | ||
| 962 | /* Instruction with specific operands. */ | |
| 963 | #define INSN_ADDI_GP_TO_FP 0x51cd8000 /* BASELINE_V1. */ | |
| 964 | #define INSN_ADDIGP_TO_FP 0x3fc80000 /* BASELINE_V2. */ | |
| 965 | #define INSN_MOVI_TO_FP 0x45c00000 | |
| 966 | #define INSN_MFUSR_PC 0x420F8020 | |
| 967 | #define INSN_MFUSR_PC_MASK 0xFE0FFFFF | |
| 968 | ||
| 969 | /* Instructions use $ta register as operand. */ | |
| 970 | #define INSN_SETHI_TA (INSN_SETHI | (REG_TA << 20)) | |
| 971 | #define INSN_ORI_TA (INSN_ORI | (REG_TA << 20) | (REG_TA << 15)) | |
| 972 | #define INSN_ADD_TA (INSN_ADD | (REG_TA << 20)) | |
| 973 | #define INSN_ADD45_TA (INSN_ADD45 | (REG_TA << 5)) | |
| 974 | #define INSN_JR5_TA (INSN_JR5 | (REG_TA << 0)) | |
| 975 | #define INSN_RET5_TA (INSN_RET5 | (REG_TA << 0)) | |
| 976 | #define INSN_JR_TA (INSN_JR | (REG_TA << 10)) | |
| 977 | #define INSN_RET_TA (INSN_RET | (REG_TA << 10)) | |
| 978 | #define INSN_JRAL_TA (INSN_JRAL | (REG_LP << 20) | (REG_TA << 10)) | |
| 979 | #define INSN_JRAL5_TA (INSN_JRAL5 | (REG_TA << 0)) | |
| 980 | #define INSN_BEQZ_TA (INSN_BEQZ | (REG_TA << 20)) | |
| 981 | #define INSN_BNEZ_TA (INSN_BNEZ | (REG_TA << 20)) | |
| 982 | #define INSN_MOVI_TA (INSN_MOVI | (REG_TA << 20)) | |
| 983 | #define INSN_BEQ_TA (INSN_BEQ | (REG_TA << 15)) | |
| 984 | #define INSN_BNE_TA (INSN_BNE | (REG_TA << 15)) | |
| 985 | ||
| 986 | /* Instructions use $r5 register as operand. */ | |
| 987 | #define INSN_BNE_R5 (INSN_BNE | (REG_R5 << 15)) | |
| 988 | #define INSN_BEQ_R5 (INSN_BEQ | (REG_R5 << 15)) | |
| 989 | ||
| 990 | #endif |