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gdb: add target_ops::supports_displaced_step
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
4ee4189f
NC		 12020-06-03 Nick Clifton <nickc@redhat.com>
2
3 * po/sr.po: Updated Serbian translation.
4
44730156
NC		 52020-06-03 Nelson Chu <nelson.chu@sifive.com>
6
7 * riscv-opc.c (riscv_get_isa_spec_class): Change bfd_boolean to int.
8 (riscv_get_priv_spec_class): Likewise.
9
3c3d0376
AM		 102020-06-01 Alan Modra <amodra@gmail.com>
11
12 * bpf-desc.c: Regenerate.
13
78c1c354
JM		 142020-05-28 Jose E. Marchesi <jose.marchesi@oracle.com>
15 David Faust <david.faust@oracle.com>
16
17 * bpf-desc.c: Regenerate.
18 * bpf-opc.h: Likewise.
19 * bpf-opc.c: Likewise.
20 * bpf-dis.c: Likewise.
21
efcf5fb5
AM		 222020-05-28 Alan Modra <amodra@gmail.com>
23
24 * nios2-dis.c (nios2_print_insn_arg): Avoid shift left of negative
25 values.
26
ab382d64
AM		 272020-05-28 Alan Modra <amodra@gmail.com>
28
29 * ns32k-dis.c (print_insn_arg): Handle d value of 'f' for
30 immediates.
31 (print_insn_ns32k): Revert last change.
32
151f5de4
NC		 332020-05-28 Nick Clifton <nickc@redhat.com>
34
35 * ns32k-dis.c (print_insn_ns32k): Change the arg_bufs array to
36 static.
37
25e1eca8
SL		 382020-05-26 Sandra Loosemore <sandra@codesourcery.com>
39
40 Fix extraction of signed constants in nios2 disassembler (again).
41
42 * nios2-dis.c (nios2_print_insn_arg): Add explicit casts to
43 extractions of signed fields.
44
57b17940
SSF		 452020-05-26 Stefan Schulze Frielinghaus <stefansf@linux.ibm.com>
46
47 * s390-opc.txt: Relocate vector load/store instructions with
48 additional alignment parameter and change architecture level
49 constraint from z14 to z13.
50
d96bf37b
AM		 512020-05-21 Alan Modra <amodra@gmail.com>
52
53 * arc-ext.c: Replace "if (x) free (x)" with "free (x)" throughout.
54 * sparc-dis.c: Likewise.
55 * tic4x-dis.c: Likewise.
56 * xtensa-dis.c: Likewise.
57 * bpf-desc.c: Regenerate.
58 * epiphany-desc.c: Regenerate.
59 * fr30-desc.c: Regenerate.
60 * frv-desc.c: Regenerate.
61 * ip2k-desc.c: Regenerate.
62 * iq2000-desc.c: Regenerate.
63 * lm32-desc.c: Regenerate.
64 * m32c-desc.c: Regenerate.
65 * m32r-desc.c: Regenerate.
66 * mep-asm.c: Regenerate.
67 * mep-desc.c: Regenerate.
68 * mt-desc.c: Regenerate.
69 * or1k-desc.c: Regenerate.
70 * xc16x-desc.c: Regenerate.
71 * xstormy16-desc.c: Regenerate.
72
8f595e9b
NC		 732020-05-20 Nelson Chu <nelson.chu@sifive.com>
74
75 * riscv-opc.c (riscv_ext_version_table): The table used to store
76 all information about the supported spec and the corresponding ISA
77 versions. Currently, only Zicsr is supported to verify the
78 correctness of Z sub extension settings. Others will be supported
79 in the future patches.
80 (struct isa_spec_t, isa_specs): List for all supported ISA spec
81 classes and the corresponding strings.
82 (riscv_get_isa_spec_class): New function. Get the corresponding ISA
83 spec class by giving a ISA spec string.
84 * riscv-opc.c (struct priv_spec_t): New structure.
85 (struct priv_spec_t priv_specs): List for all supported privilege spec
86 classes and the corresponding strings.
87 (riscv_get_priv_spec_class): New function. Get the corresponding
88 privilege spec class by giving a spec string.
89 (riscv_get_priv_spec_name): New function. Get the corresponding
90 privilege spec string by giving a CSR version class.
91 * riscv-dis.c: Updated since DECLARE_CSR is changed.
92 * riscv-dis.c: Add new disassembler option -Mpriv-spec to dump the CSR
93 according to the chosen version. Build a hash table riscv_csr_hash to
94 store the valid CSR for the chosen pirv verison. Dump the direct
95 CSR address rather than it's name if it is invalid.
96 (parse_riscv_dis_option_without_args): New function. Parse the options
97 without arguments.
98 (parse_riscv_dis_option): Call parse_riscv_dis_option_without_args to
99 parse the options without arguments first, and then handle the options
100 with arguments. Add the new option -Mpriv-spec, which has argument.
101 * riscv-dis.c (print_riscv_disassembler_options): Add description
102 about the new OBJDUMP option.
103
3d205eb4
PB		 1042020-05-19 Peter Bergner <bergner@linux.ibm.com>
105
106 * ppc-opc.c (insert_ls, extract_ls): Handle 3-bit L fields and new
107 WC values on POWER10 sync, dcbf and wait instructions.
108 (insert_pl, extract_pl): New functions.
109 (L2OPT, LS, WC): Use insert_ls and extract_ls.
110 (LS3): New , 3-bit L for sync.
111 (LS3, L3OPT): New, 3-bit L for sync and dcbf.
112 (SC2, PL): New, 2-bit SC and PL for sync and wait.
113 (XWCPL_MASK, XL3RT_MASK, XSYNCLS_MASK): New instruction masks.
114 (XOPL3, XWCPL, XSYNCLS): New opcode macros.
115 (powerpc_opcodes) <dcbflp, dcbfps, dcbstps pause_short, phwsync,
116 plwsync, stcisync, stncisync, stsync, waitrsv>: New extended mnemonics.
117 <wait>: Enable PL operand on POWER10.
118 <dcbf>: Enable L3OPT operand on POWER10.
119 <sync>: Enable SC2 operand on POWER10.
120
a501eb44
SH		 1212020-05-19 Stafford Horne <shorne@gmail.com>
122
123 PR 25184
124 * or1k-asm.c: Regenerate.
125 * or1k-desc.c: Regenerate.
126 * or1k-desc.h: Regenerate.
127 * or1k-dis.c: Regenerate.
128 * or1k-ibld.c: Regenerate.
129 * or1k-opc.c: Regenerate.
130 * or1k-opc.h: Regenerate.
131 * or1k-opinst.c: Regenerate.
132
3b646889
AM		 1332020-05-11 Alan Modra <amodra@gmail.com>
134
135 * ppc-opc (powerpc_opcodes): Add xscmpeqqp, xscmpgeqp, xscmpgtqp,
136 xsmaxcqp, xsmincqp.
137
9cc4ce88
AM		 1382020-05-11 Alan Modra <amodra@gmail.com>
139
140 * ppc-opc.c (powerpc_opcodes): Add lxvrbx, lxvrhx, lxvrwx, lxvrdx,
141 stxvrbx, stxvrhx, stxvrwx, stxvrdx.
142
5d57bc3f
AM		 1432020-05-11 Alan Modra <amodra@gmail.com>
144
145 * ppc-opc.c (powerpc_opcodes): Add xvtlsbb.
146
66ef5847
AM		 1472020-05-11 Alan Modra <amodra@gmail.com>
148
149 * ppc-opc.c (powerpc_opcodes): Add vstribl, vstribr, vstrihl, vstrihr,
150 vclrlb, vclrrb, vstribl., vstribr., vstrihl., vstrihr..
151
4f3e9537
PB		 1522020-05-11 Peter Bergner <bergner@linux.ibm.com>
153
154 * ppc-opc.c (powerpc_opcodes) <setbc, setbcr, setnbc, setnbcr>: New
155 mnemonics.
156
ec40e91c
AM		 1572020-05-11 Alan Modra <amodra@gmail.com>
158
159 * ppc-opc.c (UIM8, P_U8XX4_MASK): Define.
160 (powerpc_opcodes): Add vgnb, vcfuged, vpextd, vpdepd, vclzdm,
161 vctzdm, cntlzdm, pdepd, pextd, cfuged, cnttzdm.
162 (prefix_opcodes): Add xxeval.
163
d7e97a76
AM		 1642020-05-11 Alan Modra <amodra@gmail.com>
165
166 * ppc-opc.c (powerpc_opcodes): Add xxgenpcvbm, xxgenpcvhm,
167 xxgenpcvwm, xxgenpcvdm.
168
fdefed7c
AM		 1692020-05-11 Alan Modra <amodra@gmail.com>
170
171 * ppc-opc.c (MP, VXVAM_MASK): Define.
172 (VXVAPS_MASK): Use VXVA_MASK.
173 (powerpc_opcodes): Add mtvsrbmi, vexpandbm, vexpandhm, vexpandwm,
174 vexpanddm, vexpandqm, vextractbm, vextracthm, vextractwm,
175 vextractdm, vextractqm, mtvsrbm, mtvsrhm, mtvsrwm, mtvsrdm, mtvsrqm,
176 vcntmbb, vcntmbh, vcntmbw, vcntmbd.
177
aa3c112f
AM		 1782020-05-11 Alan Modra <amodra@gmail.com>
179 Peter Bergner <bergner@linux.ibm.com>
180
181 * ppc-opc.c (insert_xa6a, extract_xa6a, insert_xb6a, extract_xb6a):
182 New functions.
183 (powerpc_operands): Define ACC, PMSK8, PMSK4, PMSK2, XMSK, YMSK,
184 YMSK2, XA6a, XA6ap, XB6a entries.
185 (PMMIRR, P_X_MASK, P_XX1_MASK, P_GER_MASK): Define
186 (P_GER2_MASK, P_GER4_MASK, P_GER8_MASK, P_GER64_MASK): Define.
187 (PPCVSX4): Define.
188 (powerpc_opcodes): Add xxmfacc, xxmtacc, xxsetaccz,
189 xvi8ger4pp, xvi8ger4, xvf16ger2pp, xvf16ger2, xvf32gerpp, xvf32ger,
190 xvi4ger8pp, xvi4ger8, xvi16ger2spp, xvi16ger2s, xvbf16ger2pp,
191 xvbf16ger2, xvf64gerpp, xvf64ger, xvi16ger2, xvf16ger2np,
192 xvf32gernp, xvi8ger4spp, xvi16ger2pp, xvbf16ger2np, xvf64gernp,
193 xvf16ger2pn, xvf32gerpn, xvbf16ger2pn, xvf64gerpn, xvf16ger2nn,
194 xvf32gernn, xvbf16ger2nn, xvf64gernn, xvcvbf16sp, xvcvspbf16.
195 (prefix_opcodes): Add pmxvi8ger4pp, pmxvi8ger4, pmxvf16ger2pp,
196 pmxvf16ger2, pmxvf32gerpp, pmxvf32ger, pmxvi4ger8pp, pmxvi4ger8,
197 pmxvi16ger2spp, pmxvi16ger2s, pmxvbf16ger2pp, pmxvbf16ger2,
198 pmxvf64gerpp, pmxvf64ger, pmxvi16ger2, pmxvf16ger2np, pmxvf32gernp,
199 pmxvi8ger4spp, pmxvi16ger2pp, pmxvbf16ger2np, pmxvf64gernp,
200 pmxvf16ger2pn, pmxvf32gerpn, pmxvbf16ger2pn, pmxvf64gerpn,
201 pmxvf16ger2nn, pmxvf32gernn, pmxvbf16ger2nn, pmxvf64gernn.
202
6edbfd3b
AM		 2032020-05-11 Alan Modra <amodra@gmail.com>
204
205 * ppc-opc.c (insert_imm32, extract_imm32): New functions.
206 (insert_xts, extract_xts): New functions.
207 (IMM32, UIM3, IX, UIM5, SH3, XTS, P8RR): Define.
208 (P_XX4_MASK, P_UXX4_MASK, VSOP, P_VS_MASK, P_VSI_MASK): Define.
209 (VXRC_MASK, VXSH_MASK): Define.
210 (powerpc_opcodes): Add vinsbvlx, vsldbi, vextdubvlx, vextdubvrx,
211 vextduhvlx, vextduhvrx, vextduwvlx, vextduwvrx, vextddvlx,
212 vextddvrx, vinshvlx, vinswvlx, vinsw, vinsbvrx, vinshvrx,
213 vinswvrx, vinsd, vinsblx, vsrdbi, vinshlx, vinswlx, vinsdlx,
214 vinsbrx, vinshrx, vinswrx, vinsdrx, lxvkq.
215 (prefix_opcodes): Add xxsplti32dx, xxspltidp, xxspltiw, xxblendvb,
216 xxblendvh, xxblendvw, xxblendvd, xxpermx.
217
c7d7aea2
AM		 2182020-05-11 Alan Modra <amodra@gmail.com>
219
220 * ppc-opc.c (powerpc_opcodes): Add vrlq, vdivuq, vmsumcud, vrlqmi,
221 vmuloud, vcmpuq, vslq, vdivsq, vcmpsq, vrlqnm, vcmpequq, vmulosd,
222 vsrq, vdiveuq, vcmpgtuq, vmuleud, vsraq, vdivesq, vcmpgtsq, vmulesd,
223 vcmpequq., vextsd2q, vmoduq, vcmpgtuq., vmodsq, vcmpgtsq., xscvqpuqz,
224 xscvuqqp, xscvqpsqz, xscvsqqp, dcffixqq, dctfixqq.
225
94ba9882
AM		 2262020-05-11 Alan Modra <amodra@gmail.com>
227
228 * ppc-opc.c (insert_xtp, extract_xtp): New functions.
229 (XTP, DQXP, DQXP_MASK): Define.
230 (powerpc_opcodes): Add lxvp, stxvp, lxvpx, stxvpx.
231 (prefix_opcodes): Add plxvp and pstxvp.
232
f4791f1a
AM		 2332020-05-11 Alan Modra <amodra@gmail.com>
234
235 * ppc-opc.c (powerpc_opcodes): Add vdivuw, vdivud, vdivsw, vmulld,
236 vdivsd, vmulhuw, vdiveuw, vmulhud, vdiveud, vmulhsw, vdivesw,
237 vmulhsd, vdivesd, vmoduw, vmodud, vmodsw, vmodsd.
238
3ff0a5ba
PB		 2392020-05-11 Peter Bergner <bergner@linux.ibm.com>
240
241 * ppc-opc.c (powerpc_opcodes) <brd, brh, brw>: New mnemonics.
242
afef4fe9
PB		 2432020-05-11 Peter Bergner <bergner@linux.ibm.com>
244
245 * ppc-opc.c (insert_l1opt, extract_l1opt): New functions.
246 (L1OPT): Define.
247 (powerpc_opcodes) <paste.>: Add L operand for cpu POWER10.
248
1224c05d
PB		 2492020-05-11 Peter Bergner <bergner@linux.ibm.com>
250
251 * ppc-opc.c (powerpc_opcodes) <slbiag>: Add variant with L operand.
252
6bbb0c05
AM		 2532020-05-11 Alan Modra <amodra@gmail.com>
254
255 * ppc-dis.c (powerpc_init_dialect): Default to "power10".
256
7c1f4227
AM		 2572020-05-11 Alan Modra <amodra@gmail.com>
258
259 * ppc-dis.c (ppc_opts): Add "power10" entry.
260 (print_insn_powerpc): Update for PPC_OPCODE_POWER10 renaming.
261 * ppc-opc.c (POWER10): Rename from POWERXX. Update all uses.
262
73199c2b
NC		 2632020-05-11 Nick Clifton <nickc@redhat.com>
264
265 * po/fr.po: Updated French translation.
266
09c1e68a
AC		 2672020-04-30 Alex Coplan <alex.coplan@arm.com>
268
269 * aarch64-opc.h (enum aarch64_field_kind): Add FLD_imm16_2.
270 * aarch64-opc.c (fields): Add entry for FLD_imm16_2.
271 (operand_general_constraint_met_p): validate
272 AARCH64_OPND_UNDEFINED.
273 * aarch64-tbl.h (aarch64_opcode_table): Add udf instruction, entry
274 for FLD_imm16_2.
275 * aarch64-asm-2.c: Regenerated.
276 * aarch64-dis-2.c: Regenerated.
277 * aarch64-opc-2.c: Regenerated.
278
9654d51a
NC		 2792020-04-29 Nick Clifton <nickc@redhat.com>
280
281 PR 22699
282 * sh-opc.h: Also use unsigned 8-bit immediate values for the LDRC
283 and SETRC insns.
284
c2e71e57
NC		 2852020-04-29 Nick Clifton <nickc@redhat.com>
286
287 * po/sv.po: Updated Swedish translation.
288
5c936ef5
NC		 2892020-04-29 Nick Clifton <nickc@redhat.com>
290
291 PR 22699
292 * sh-opc.h (IMM0_8): Replace with IMM0_8S and IMM0_8U. Use
293 IMM0_8S for arithmetic insns and IMM0_8U for logical insns.
294 * sh-dis.c (print_insn_sh): Change IMM0_8 case to IMM0_8S and add
295 IMM0_8U case.
296
bb2a1453
AS		 2972020-04-21 Andreas Schwab <schwab@linux-m68k.org>
298
299 PR 25848
300 * m68k-opc.c (m68k_opcodes): Allow pc-rel for second operand of
301 cmpi only on m68020up and cpu32.
302
c2e5c986
SD		 3032020-04-20 Sudakshina Das <sudi.das@arm.com>
304
305 * aarch64-asm.c (aarch64_ins_none): New.
306 * aarch64-asm.h (ins_none): New declaration.
307 * aarch64-dis.c (aarch64_ext_none): New.
308 * aarch64-dis.h (ext_none): New declaration.
309 * aarch64-opc.c (aarch64_print_operand): Update case for
310 AARCH64_OPND_BARRIER_PSB.
311 * aarch64-tbl.h (aarch64_opcode_table): Add tsb.
312 (AARCH64_OPERANDS): Update inserter/extracter for
313 AARCH64_OPND_BARRIER_PSB to use new dummy functions.
314 * aarch64-asm-2.c: Regenerated.
315 * aarch64-dis-2.c: Regenerated.
316 * aarch64-opc-2.c: Regenerated.
317
8a6e1d1d
SD		 3182020-04-20 Sudakshina Das <sudi.das@arm.com>
319
320 * aarch64-tbl.h (aarch64_feature_bti, BTI, BTI_INSN): Remove.
321 (aarch64_feature_ras, RAS): Likewise.
322 (aarch64_feature_stat_profile, STAT_PROFILE): Likewise.
323 (aarch64_opcode_table): Update bti, xpaclri, pacia1716, pacib1716,
324 autia1716, autib1716, esb, psb, dgh, paciaz, paciasp, pacibz, pacibsp,
325 autiaz, autiasp, autibz, autibsp to be CORE_INSN.
326 * aarch64-asm-2.c: Regenerated.
327 * aarch64-dis-2.c: Regenerated.
328 * aarch64-opc-2.c: Regenerated.
329
e409955d
FS		 3302020-04-17 Fredrik Strupe <fredrik@strupe.net>
331
332 * arm-dis.c (neon_opcodes): Fix VDUP instruction masks.
333 (print_insn_neon): Support disassembly of conditional
334 instructions.
335
c54a9b56
DF		 3362020-02-16 David Faust <david.faust@oracle.com>
337
338 * bpf-desc.c: Regenerate.
339 * bpf-desc.h: Likewise.
340 * bpf-opc.c: Regenerate.
341 * bpf-opc.h: Likewise.
342
bb651e8b
CL		 3432020-04-07 Lili Cui <lili.cui@intel.com>
344
345 * i386-dis.c (enum): Add PREFIX_0F01_REG_5_MOD_3_RM_1,
346 (prefix_table): New instructions (see prefixes above).
347 (rm_table): Likewise
348 * i386-gen.c (cpu_flag_init): Add CPU_TSXLDTRK_FLAGS,
349 CPU_ANY_TSXLDTRK_FLAGS.
350 (cpu_flags): Add CpuTSXLDTRK.
351 * i386-opc.h (enum): Add CpuTSXLDTRK.
352 (i386_cpu_flags): Add cputsxldtrk.
353 * i386-opc.tbl: Add XSUSPLDTRK insns.
354 * i386-init.h: Regenerate.
355 * i386-tbl.h: Likewise.
356
4b27d27c
L		 3572020-04-02 Lili Cui <lili.cui@intel.com>
358
359 * i386-dis.c (prefix_table): New instructions serialize.
360 * i386-gen.c (cpu_flag_init): Add CPU_SERIALIZE_FLAGS,
361 CPU_ANY_SERIALIZE_FLAGS.
362 (cpu_flags): Add CpuSERIALIZE.
363 * i386-opc.h (enum): Add CpuSERIALIZE.
364 (i386_cpu_flags): Add cpuserialize.
365 * i386-opc.tbl: Add SERIALIZE insns.
366 * i386-init.h: Regenerate.
367 * i386-tbl.h: Likewise.
368
832a5807
AM		 3692020-03-26 Alan Modra <amodra@gmail.com>
370
371 * disassemble.h (opcodes_assert): Declare.
372 (OPCODES_ASSERT): Define.
373 * disassemble.c: Don't include assert.h. Include opintl.h.
374 (opcodes_assert): New function.
375 * h8300-dis.c (bfd_h8_disassemble_init): Use OPCODES_ASSERT.
376 (bfd_h8_disassemble): Reduce size of data array. Correctly
377 calculate maxlen. Omit insn decoding when insn length exceeds
378 maxlen. Exit from nibble loop when looking for E, before
379 accessing next data byte. Move processing of E outside loop.
380 Replace tests of maxlen in loop with assertions.
381
4c4addbe
AM		 3822020-03-26 Alan Modra <amodra@gmail.com>
383
384 * arc-dis.c (find_format): Init needs_limm. Simplify use of limm.
385
a18cd0ca
AM		 3862020-03-25 Alan Modra <amodra@gmail.com>
387
388 * z80-dis.c (suffix): Init mybuf.
389
57cb32b3
AM		 3902020-03-22 Alan Modra <amodra@gmail.com>
391
392 * h8300-dis.c (bfd_h8_disassemble): Limit data[] access to that
393 successflly read from section.
394
beea5cc1
AM		 3952020-03-22 Alan Modra <amodra@gmail.com>
396
397 * arc-dis.c (find_format): Use ISO C string concatenation rather
398 than line continuation within a string. Don't access needs_limm
399 before testing opcode != NULL.
400
03704c77
AM		 4012020-03-22 Alan Modra <amodra@gmail.com>
402
403 * ns32k-dis.c (print_insn_arg): Update comment.
404 (print_insn_ns32k): Reduce size of index_offset array, and
405 initialize, passing -1 to print_insn_arg for args that are not
406 an index. Don't exit arg loop early. Abort on bad arg number.
407
d1023b5d
AM		 4082020-03-22 Alan Modra <amodra@gmail.com>
409
410 * s12z-dis.c (abstract_read_memory): Don't print error on EOI.
411 * s12z-opc.c: Formatting.
412 (operands_f): Return an int.
413 (opr_n_bytes_p1): Return -1 on reaching buffer memory limit.
414 (opr_n_bytes2, bfextins_n_bytes, mul_n_bytes, bm_n_bytes),
415 (shift_n_bytes, mov_imm_opr_n_bytes, loop_prim_n_bytes),
416 (exg_sex_discrim): Likewise.
417 (create_immediate_operand, create_bitfield_operand),
418 (create_register_operand_with_size, create_register_all_operand),
419 (create_register_all16_operand, create_simple_memory_operand),
420 (create_memory_operand, create_memory_auto_operand): Don't
421 segfault on malloc failure.
422 (z_ext24_decode): Return an int status, negative on fail, zero
423 on success.
424 (x_imm1, imm1_decode, trap_decode, z_opr_decode, z_opr_decode2),
425 (imm1234, reg_s_imm, reg_s_opr, z_imm1234_8base, z_imm1234_0base),
426 (z_tfr, z_reg, reg_xy, lea_reg_xys_opr, lea_reg_xys, rel_15_7),
427 (decode_rel_15_7, cmp_xy, sub_d6_x_y, sub_d6_y_x),
428 (ld_18bit_decode, mul_decode, bm_decode, bm_rel_decode),
429 (mov_imm_opr, ld_18bit_decode, exg_sex_decode),
430 (loop_primitive_decode, shift_decode, psh_pul_decode),
431 (bit_field_decode): Similarly.
432 (z_decode_signed_value, decode_signed_value): Similarly. Add arg
433 to return value, update callers.
434 (x_opr_decode_with_size): Check all reads, returning NULL on fail.
435 Don't segfault on NULL operand.
436 (decode_operation): Return OP_INVALID on first fail.
437 (decode_s12z): Check all reads, returning -1 on fail.
438
340f3ac8
AM		 4392020-03-20 Alan Modra <amodra@gmail.com>
440
441 * metag-dis.c (print_insn_metag): Don't ignore status from
442 read_memory_func.
443
fe90ae8a
AM		 4442020-03-20 Alan Modra <amodra@gmail.com>
445
446 * nds32-dis.c (print_insn_nds32): Remove unnecessary casts.
447 Initialize parts of buffer not written when handling a possible
448 2-byte insn at end of section. Don't attempt decoding of such
449 an insn by the 4-byte machinery.
450
833d919c
AM		 4512020-03-20 Alan Modra <amodra@gmail.com>
452
453 * ppc-dis.c (print_insn_powerpc): Only clear needed bytes of
454 partially filled buffer. Prevent lookup of 4-byte insns when
455 only VLE 2-byte insns are possible due to section size. Print
456 ".word" rather than ".long" for 2-byte leftovers.
457
327ef784
NC		 4582020-03-17 Sergey Belyashov <sergey.belyashov@gmail.com>
459
460 PR 25641
461 * z80-dis.c: Fix disassembling ED+A4/AC/B4/BC opcodes.
462
1673df32
JB		 4632020-03-13 Jan Beulich <jbeulich@suse.com>
464
465 * i386-dis.c (X86_64_0D): Rename to ...
466 (X86_64_0E): ... this.
467
384f3689
L		 4682020-03-09 H.J. Lu <hongjiu.lu@intel.com>
469
470 * Makefile.am ($(srcdir)/i386-init.h): Also pass -P to $(CPP).
471 * Makefile.in: Regenerated.
472
865e2027
JB		 4732020-03-09 Jan Beulich <jbeulich@suse.com>
474
475 * i386-opc.tbl (avx_irel): New. Use is for AVX512 vpcmp*
476 3-operand pseudos.
477 * i386-tbl.h: Re-generate.
478
2f13234b
JB		 4792020-03-09 Jan Beulich <jbeulich@suse.com>
480
481 * i386-opc.tbl (xop_elem, xop_irel, xop_sign): New. Use them for XOP vpcom*,
482 vprot*, vpsha*, and vpshl*.
483 * i386-tbl.h: Re-generate.
484
3fabc179
JB		 4852020-03-09 Jan Beulich <jbeulich@suse.com>
486
487 * i386-opc.tbl (avx_frel): New. Use it for AVX/AVX512 vcmpps,
488 vcmpss, vcmppd, and vcmpsd 3-operand pseudo-ops.
489 * i386-tbl.h: Re-generate.
490
3677e4c1
JB		 4912020-03-09 Jan Beulich <jbeulich@suse.com>
492
493 * i386-gen.c (set_bitfield): Ignore zero-length field names.
494 * i386-opc.tbl (sse_frel): New. Use it for SSE/SSE2 cmpps,
495 cmpss, cmppd, and cmpsd 2-operand pseudo-ops.
496 * i386-tbl.h: Re-generate.
497
4c4898e8
JB		 4982020-03-09 Jan Beulich <jbeulich@suse.com>
499
500 * i386-gen.c (struct template_arg, struct template_instance,
501 struct template_param, struct template, templates,
502 parse_template, expand_templates): New.
503 (process_i386_opcodes): Various local variables moved to
504 expand_templates. Call parse_template and expand_templates.
505 * i386-opc.tbl (cc): New. Use it for Jcc, SETcc, and CMOVcc.
506 * i386-tbl.h: Re-generate.
507
bc49bfd8
JB		 5082020-03-06 Jan Beulich <jbeulich@suse.com>
509
510 * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd, vcvtps2ph,
511 vcvtps2qq, vcvtps2uqq, vcvttps2qq, vcvttps2uqq): Fold separate
512 register and memory source templates. Replace VexW= by VexW*
513 where applicable.
514 * i386-tbl.h: Re-generate.
515
4873e243
JB		 5162020-03-06 Jan Beulich <jbeulich@suse.com>
517
518 * i386-opc.tbl: Drop IgnoreSize from various SIMD insns. Replace
519 VexW= by VexW* and VexVVVV=1 by just VexVVVV where applicable.
520 * i386-tbl.h: Re-generate.
521
672a349b
JB		 5222020-03-06 Jan Beulich <jbeulich@suse.com>
523
524 * i386-opc.tbl (fildll, fistpll, fisttpll): Add ATTSyntax.
525 * i386-tbl.h: Re-generate.
526
4ed21b58
JB		 5272020-03-06 Jan Beulich <jbeulich@suse.com>
528
529 * i386-opc.tbl (movq): Drop NoRex64 from XMM/XMM SSE2AVX variants.
530 (movmskps, pextrw, pinsrw, pmovmskb, movmskpd, extractps,
531 pextrb, pinsrb, roundsd): Drop NoRex64 and where applicable use
532 VexW0 on SSE2AVX variants.
533 (vmovq): Drop NoRex64 from XMM/XMM variants.
534 (vextractps, vmovmskpd, vmovmskps, vpextrb, vpextrw, vpinsrb,
535 vpinsrw, vpmovmskb, vroundsd, vpmovmskb): Drop NoRex64 and where
536 applicable use VexW0.
537 * i386-tbl.h: Re-generate.
538
643bb870
JB		 5392020-03-06 Jan Beulich <jbeulich@suse.com>
540
541 * i386-gen.c (opcode_modifiers): Remove Rex64 field.
542 * i386-opc.h (Rex64): Delete.
543 (struct i386_opcode_modifier): Remove rex64 field.
544 * i386-opc.tbl (crc32): Drop Rex64.
545 Replace Rex64 with Size64 everywhere else.
546 * i386-tbl.h: Re-generate.
547
a23b33b3
JB		 5482020-03-06 Jan Beulich <jbeulich@suse.com>
549
550 * i386-dis.c (OP_E_memory): Exclude recording of used address
551 prefix for "bnd" modes only in 64-bit mode. Don't decode 16-bit
552 addressed memory operands for MPX insns.
553
a0497384
JB		 5542020-03-06 Jan Beulich <jbeulich@suse.com>
555
556 * i386-opc.tbl (movmskps, mwait, vmread, vmwrite, invept,
557 invvpid, invpcid, rdfsbase, rdgsbase, wrfsbase, wrgsbase, adcx,
558 adox, mwaitx, rdpid, movdiri): Add IgnoreSize.
559 (ptwrite): Split into non-64-bit and 64-bit forms.
560 * i386-tbl.h: Re-generate.
561
b630c145
JB		 5622020-03-06 Jan Beulich <jbeulich@suse.com>
563
564 * i386-opc.tbl (tpause, umwait): Add IgnoreSize. Add 3-operand
565 template.
566 * i386-tbl.h: Re-generate.
567
a847e322
JB		 5682020-03-04 Jan Beulich <jbeulich@suse.com>
569
570 * i386-dis.c (PREFIX_0F01_REG_3_RM_1): New.
571 (prefix_table): Move vmmcall here. Add vmgexit.
572 (rm_table): Replace vmmcall entry by prefix_table[] escape.
573 * i386-gen.c (cpu_flag_init): Add CPU_SEV_ES_FLAGS entry.
574 (cpu_flags): Add CpuSEV_ES entry.
575 * i386-opc.h (CpuSEV_ES): New.
576 (union i386_cpu_flags): Add cpusev_es field.
577 * i386-opc.tbl (vmgexit): New.
578 * i386-init.h, i386-tbl.h: Re-generate.
579
3cd7f3e3
L		 5802020-03-03 H.J. Lu <hongjiu.lu@intel.com>
581
582 * i386-gen.c (opcode_modifiers): Replace IgnoreSize/DefaultSize
583 with MnemonicSize.
584 * i386-opc.h (IGNORESIZE): New.
585 (DEFAULTSIZE): Likewise.
586 (IgnoreSize): Removed.
587 (DefaultSize): Likewise.
588 (MnemonicSize): New.
589 (i386_opcode_modifier): Replace ignoresize/defaultsize with
590 mnemonicsize.
591 * i386-opc.tbl (IgnoreSize): New.
592 (DefaultSize): Likewise.
593 * i386-tbl.h: Regenerated.
594
b8ba1385
SB		 5952020-03-03 Sergey Belyashov <sergey.belyashov@gmail.com>
596
597 PR 25627
598 * z80-dis.c: Fix disassembly of LD IY,(HL) and D (HL),IX
599 instructions.
600
10d97a0f
L		 6012020-03-03 H.J. Lu <hongjiu.lu@intel.com>
602
603 PR gas/25622
604 * i386-opc.tbl: Add IgnoreSize to cvtsi2sd, cvtsi2ss, vcvtsi2sd,
605 vcvtsi2ss, vcvtusi2sd and vcvtusi2ss for AT&T syntax.
606 * i386-tbl.h: Regenerated.
607
dc1e8a47
AM		 6082020-02-26 Alan Modra <amodra@gmail.com>
609
610 * aarch64-asm.c: Indent labels correctly.
611 * aarch64-dis.c: Likewise.
612 * aarch64-gen.c: Likewise.
613 * aarch64-opc.c: Likewise.
614 * alpha-dis.c: Likewise.
615 * i386-dis.c: Likewise.
616 * nds32-asm.c: Likewise.
617 * nfp-dis.c: Likewise.
618 * visium-dis.c: Likewise.
619
265b4673
CZ		 6202020-02-25 Claudiu Zissulescu <claziss@gmail.com>
621
622 * arc-regs.h (int_vector_base): Make it available for all ARC
623 CPUs.
624
bd0cf5a6
NC		 6252020-02-20 Nelson Chu <nelson.chu@sifive.com>
626
627 * riscv-dis.c (print_insn_args): Updated since the DECLARE_CSR is
628 changed.
629
fa164239
JW		 6302020-02-19 Nelson Chu <nelson.chu@sifive.com>
631
632 * riscv-opc.c (riscv_opcodes): Convert add/addi to the compressed
633 c.mv/c.li if rs1 is zero.
634
272a84b1
L		 6352020-02-17 H.J. Lu <hongjiu.lu@intel.com>
636
637 * i386-gen.c (cpu_flag_init): Replace CpuABM with
638 CpuLZCNT|CpuPOPCNT. Add CpuPOPCNT to CPU_SSE4_2_FLAGS. Add
639 CPU_POPCNT_FLAGS.
640 (cpu_flags): Remove CpuABM. Add CpuPOPCNT.
641 * i386-opc.h (CpuABM): Removed.
642 (CpuPOPCNT): New.
643 (i386_cpu_flags): Remove cpuabm. Add cpupopcnt.
644 * i386-opc.tbl: Replace CpuABM|CpuSSE4_2 with CpuPOPCNT on
645 popcnt. Remove CpuABM from lzcnt.
646 * i386-init.h: Regenerated.
647 * i386-tbl.h: Likewise.
648
1f730c46
JB		 6492020-02-17 Jan Beulich <jbeulich@suse.com>
650
651 * i386-opc.tbl (vcvtsi2sd, vcvtsi2ss, vcvtusi2sd, vcvtusi2ss):
652 Fold CpuNo64 and Cpu64 templates. Use VexLIG/EVexLIG and VexW0/
653 VexW1 instead of open-coding them.
654 * i386-tbl.h: Re-generate.
655
c8f8eebc
JB		 6562020-02-17 Jan Beulich <jbeulich@suse.com>
657
658 * i386-opc.tbl (AddrPrefixOpReg): Define.
659 (monitor, invlpga, vmload, vmrun, vmsave, clzero, monitorx,
660 umonitor, movdir64b, enqcmd, enqcmds): Fold Cpu64 and CpuNo64
661 templates. Drop NoRex64.
662 * i386-tbl.h: Re-generate.
663
b9915cbc
JB		 6642020-02-17 Jan Beulich <jbeulich@suse.com>
665
666 PR gas/6518
667 * i386-opc.tbl (vcvtpd2dq, vcvtpd2ps, vcvttpd2dq, vcvtpd2udq,
668 vcvttpd2udq, vcvtqq2ps, vcvtuqq2ps): Split XMM/YMM source forms
669 into Intel syntax instance (with Unpsecified) and AT&T one
670 (without).
671 (vcvtneps2bf16): Likewise, along with folding the two so far
672 separate ones.
673 * i386-tbl.h: Re-generate.
674
ce504911
L		 6752020-02-16 H.J. Lu <hongjiu.lu@intel.com>
676
677 * i386-gen.c (cpu_flag_init): Remove CPU_ANY_SSE3_FLAGS from
678 CPU_ANY_SSE4A_FLAGS.
679
dabec65d
AM		 6802020-02-17 Alan Modra <amodra@gmail.com>
681
682 * i386-gen.c (cpu_flag_init): Correct last change.
683
af5c13b0
L		 6842020-02-16 H.J. Lu <hongjiu.lu@intel.com>
685
686 * i386-gen.c (cpu_flag_init): Add CPU_ANY_SSE4A_FLAGS. Remove
687 CPU_ANY_SSE4_FLAGS.
688
6867aac0
L		 6892020-02-14 H.J. Lu <hongjiu.lu@intel.com>
690
691 * i386-opc.tbl (movsx): Remove Intel syntax comments.
692 (movzx): Likewise.
693
65fca059
JB		 6942020-02-14 Jan Beulich <jbeulich@suse.com>
695
696 PR gas/25438
697 * i386-opc.tbl (movsx): Fold patterns. Also allow Reg32 as
698 destination for Cpu64-only variant.
699 (movzx): Fold patterns.
700 * i386-tbl.h: Re-generate.
701
7deea9aa
JB		 7022020-02-13 Jan Beulich <jbeulich@suse.com>
703
704 * i386-gen.c (cpu_flag_init): Move CpuSSE4a from
705 CPU_ANY_SSE_FLAGS entry to CPU_ANY_SSE3_FLAGS one. Add
706 CPU_ANY_SSE4_FLAGS entry.
707 * i386-init.h: Re-generate.
708
6c0946d0
JB		 7092020-02-12 Jan Beulich <jbeulich@suse.com>
710
711 * i386-opc.tbl (vfpclasspd, vfpclassps): Add Intel sytax form
712 with Unspecified, making the present one AT&T syntax only.
713 * i386-tbl.h: Re-generate.
714
ddb56fe6
JB		 7152020-02-12 Jan Beulich <jbeulich@suse.com>
716
717 * i386-opc.tbl (jmp): Fold CpuNo64 and Amd64 direct variants.
718 * i386-tbl.h: Re-generate.
719
5990e377
JB		 7202020-02-12 Jan Beulich <jbeulich@suse.com>
721
722 PR gas/24546
723 * i386-dis.c (putop): Handle REX.W in '^' case for Intel64 mode.
724 * i386-opc.tbl (lfs, lgs, lss, lcall, ljmp): Split into
725 Amd64 and Intel64 templates.
726 (call, jmp): Likewise for far indirect variants. Dro
727 Unspecified.
728 * i386-tbl.h: Re-generate.
729
50128d0c
JB		 7302020-02-11 Jan Beulich <jbeulich@suse.com>
731
732 * i386-gen.c (opcode_modifiers): Remove ShortForm entry.
733 * i386-opc.h (ShortForm): Delete.
734 (struct i386_opcode_modifier): Remove shortform field.
735 * i386-opc.tbl (mov, movabs, push, pop, xchg, inc, dec, fld,
736 fst, fstp, fxch, fcom, fcomp, fucom, fucomp, fadd, faddp, fsub,
737 fsubp, fsubr, fsubrp, fmul, fmulp, fdiv, fdivp, fdivr, fdivrp,
738 ffreep, bswap, fcmov*, fcomi, fcomip, fucomi, fucomip, movq):
739 Drop ShortForm.
740 * i386-tbl.h: Re-generate.
741
1e05b5c4
JB		 7422020-02-11 Jan Beulich <jbeulich@suse.com>
743
744 * i386-opc.tbl (fcomi, fucomi, fcomip, fcompi, fucomip,
745 fucompi): Drop ShortForm from operand-less templates.
746 * i386-tbl.h: Re-generate.
747
2f5dd314
AM		 7482020-02-11 Alan Modra <amodra@gmail.com>
749
750 * cgen-ibld.in (extract_normal): Set *valuep on all return paths.
751 * bpf-ibld.c, * epiphany-ibld.c, * fr30-ibld.c, * frv-ibld.c,
752 * ip2k-ibld.c, * iq2000-ibld.c, * lm32-ibld.c, * m32c-ibld.c,
753 * m32r-ibld.c, * mep-ibld.c, * mt-ibld.c, * or1k-ibld.c,
754 * xc16x-ibld.c, * xstormy16-ibld.c: Regenerate.
755
5aae9ae9
MM		 7562020-02-10 Matthew Malcomson <matthew.malcomson@arm.com>
757
758 * arm-dis.c (print_insn_cde): Define 'V' parse character.
759 (cde_opcodes): Add VCX* instructions.
760
4934a27c
MM		 7612020-02-10 Stam Markianos-Wright <stam.markianos-wright@arm.com>
762 Matthew Malcomson <matthew.malcomson@arm.com>
763
764 * arm-dis.c (struct cdeopcode32): New.
765 (CDE_OPCODE): New macro.
766 (cde_opcodes): New disassembly table.
767 (regnames): New option to table.
768 (cde_coprocs): New global variable.
769 (print_insn_cde): New
770 (print_insn_thumb32): Use print_insn_cde.
771 (parse_arm_disassembler_options): Parse coprocN args.
772
4b5aaf5f
L		 7732020-02-10 H.J. Lu <hongjiu.lu@intel.com>
774
775 PR gas/25516
776 * i386-gen.c (opcode_modifiers): Replace AMD64 and Intel64
777 with ISA64.
778 * i386-opc.h (AMD64): Removed.
779 (Intel64): Likewose.
780 (AMD64): New.
781 (INTEL64): Likewise.
782 (INTEL64ONLY): Likewise.
783 (i386_opcode_modifier): Replace amd64 and intel64 with isa64.
784 * i386-opc.tbl (Amd64): New.
785 (Intel64): Likewise.
786 (Intel64Only): Likewise.
787 Replace AMD64 with Amd64. Update sysenter/sysenter with
788 Cpu64 and Intel64Only. Remove AMD64 from sysenter/sysenter.
789 * i386-tbl.h: Regenerated.
790
9fc0b501
SB		 7912020-02-07 Sergey Belyashov <sergey.belyashov@gmail.com>
792
793 PR 25469
794 * z80-dis.c: Add support for GBZ80 opcodes.
795
c5d7be0c
AM		 7962020-02-04 Alan Modra <amodra@gmail.com>
797
798 * d30v-dis.c (print_insn): Make "val" and "opnum" unsigned.
799
44e4546f
AM		 8002020-02-03 Alan Modra <amodra@gmail.com>
801
802 * m32c-ibld.c: Regenerate.
803
b2b1453a
AM		 8042020-02-01 Alan Modra <amodra@gmail.com>
805
806 * frv-ibld.c: Regenerate.
807
4102be5c
JB		 8082020-01-31 Jan Beulich <jbeulich@suse.com>
809
810 * i386-dis.c (EXxmm_mdq, xmm_mdq_mode): Delete.
811 (intel_operand_size, OP_EX): Drop xmm_mdq_mode case label.
812 (OP_E_memory): Replace xmm_mdq_mode case label by
813 vex_scalar_w_dq_mode one.
814 * i386-dis-evex-prefix.h: Replace EXxmm_mdq by EXVexWdqScalar.
815
825bd36c
JB		 8162020-01-31 Jan Beulich <jbeulich@suse.com>
817
818 * i386-dis.c (EXVexWdq, vex_w_dq_mode): Delete.
819 (vex_vsib_d_w_dq_mode, vex_vsib_q_w_dq_mode,
820 vex_scalar_w_dq_mode): Don't refer to vex_w_dq_mode in comments.
821 (intel_operand_size): Drop vex_w_dq_mode case label.
822
c3036ed0
RS		 8232020-01-31 Richard Sandiford <richard.sandiford@arm.com>
824
825 * aarch64-tbl.h (aarch64_opcode): Set C_MAX_ELEM for SVE bfcvt.
826 Remove C_SCAN_MOVPRFX for SVE bfcvtnt.
827
0c115f84
AM		 8282020-01-30 Alan Modra <amodra@gmail.com>
829
830 * m32c-ibld.c: Regenerate.
831
bd434cc4
JM		 8322020-01-30 Jose E. Marchesi <jose.marchesi@oracle.com>
833
834 * bpf-opc.c: Regenerate.
835
aeab2b26
JB		 8362020-01-30 Jan Beulich <jbeulich@suse.com>
837
838 * i386-dis.c (X86_64_C2, X86_64_C3): New enumerators.
839 (dis386): Use them to replace C2/C3 table entries.
840 (x86_64_table): Add X86_64_C2 and X86_64_C3 entries.
841 * i386-opc.tbl (ret): Split Cpu64 entries into AMD64 and Intel64
842 ones. Use Size64 instead of DefaultSize on Intel64 ones.
843 * i386-tbl.h: Re-generate.
844
62b3f548
JB		 8452020-01-30 Jan Beulich <jbeulich@suse.com>
846
847 * i386-opc.tbl (call): Drop DefaultSize from Intel64 JumpDword
848 forms.
849 (fldenv, fnstenv, fstenv, fnsave, fsave, frstor): Drop
850 DefaultSize.
851 * i386-tbl.h: Re-generate.
852
1bd8ae10
AM		 8532020-01-30 Alan Modra <amodra@gmail.com>
854
855 * tic4x-dis.c (tic4x_dp): Make unsigned.
856
bc31405e
L		 8572020-01-27 H.J. Lu <hongjiu.lu@intel.com>
858 Jan Beulich <jbeulich@suse.com>
859
860 PR binutils/25445
861 * i386-dis.c (MOVSXD_Fixup): New function.
862 (movsxd_mode): New enum.
863 (x86_64_table): Use MOVSXD_Fixup and movsxd_mode on movsxd.
864 (intel_operand_size): Handle movsxd_mode.
865 (OP_E_register): Likewise.
866 (OP_G): Likewise.
867 * i386-opc.tbl: Remove Rex64 and allow 32-bit destination
868 register on movsxd. Add movsxd with 16-bit destination register
869 for AMD64 and Intel64 ISAs.
870 * i386-tbl.h: Regenerated.
871
7568c93b
TC		 8722020-01-27 Tamar Christina <tamar.christina@arm.com>
873
874 PR 25403
875 * aarch64-tbl.h (struct aarch64_opcode): Re-order cfinv.
876 * aarch64-asm-2.c: Regenerate
877 * aarch64-dis-2.c: Likewise.
878 * aarch64-opc-2.c: Likewise.
879
c006a730
JB		 8802020-01-21 Jan Beulich <jbeulich@suse.com>
881
882 * i386-opc.tbl (sysret): Drop DefaultSize.
883 * i386-tbl.h: Re-generate.
884
c906a69a
JB		 8852020-01-21 Jan Beulich <jbeulich@suse.com>
886
887 * i386-opc.tbl (vcvtneps2bf16x): Add Broadcast, Xmmword, and
888 Dword.
889 (vcvtneps2bf16y): Add Broadcast, Ymmword, and Dword.
890 * i386-tbl.h: Re-generate.
891
26916852
NC		 8922020-01-20 Nick Clifton <nickc@redhat.com>
893
894 * po/de.po: Updated German translation.
895 * po/pt_BR.po: Updated Brazilian Portuguese translation.
896 * po/uk.po: Updated Ukranian translation.
897
4d6cbb64
AM		 8982020-01-20 Alan Modra <amodra@gmail.com>
899
900 * hppa-dis.c (fput_const): Remove useless cast.
901
2bddb71a
AM		 9022020-01-20 Alan Modra <amodra@gmail.com>
903
904 * arm-dis.c (print_insn_arm): Wrap 'T' value.
905
1b1bb2c6
NC		 9062020-01-18 Nick Clifton <nickc@redhat.com>
907
908 * configure: Regenerate.
909 * po/opcodes.pot: Regenerate.
910
ae774686
NC		 9112020-01-18 Nick Clifton <nickc@redhat.com>
912
913 Binutils 2.34 branch created.
914
07f1f3aa
CB		 9152020-01-17 Christian Biesinger <cbiesinger@google.com>
916
917 * opintl.h: Fix spelling error (seperate).
918
42e04b36
L		 9192020-01-17 H.J. Lu <hongjiu.lu@intel.com>
920
921 * i386-opc.tbl: Add {vex} pseudo prefix.
922 * i386-tbl.h: Regenerated.
923
2da2eaf4
AV		 9242020-01-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
925
926 PR 25376
927 * opcodes/arm-dis.c (coprocessor_opcodes): Use CORE_HIGH for MVE bits.
928 (neon_opcodes): Likewise.
929 (select_arm_features): Make sure we enable MVE bits when selecting
930 armv8.1-m.main. Make sure we do not enable MVE bits when not selecting
931 any architecture.
932
d0849eed
JB		 9332020-01-16 Jan Beulich <jbeulich@suse.com>
934
935 * i386-opc.tbl: Drop stale comment from XOP section.
936
9cf70a44
JB		 9372020-01-16 Jan Beulich <jbeulich@suse.com>
938
939 * i386-opc.tbl (movq): Add VexWIG to SSE2AVX XMM->XMM forms.
940 (extractps): Add VexWIG to SSE2AVX forms.
941 * i386-tbl.h: Re-generate.
942
4814632e
JB		 9432020-01-16 Jan Beulich <jbeulich@suse.com>
944
945 * i386-opc.tbl (pextrq, pinsrq): Drop IgnoreSize and Qword. Drop
946 Size64 from and use VexW1 on SSE2AVX forms.
947 (vpextrq, vpinsrq): Drop IgnoreSize and Qword. Drop Size64 from
948 VEX-encoded forms. Add Cpu64 to EVEX-encoded forms. Use VexW1.
949 * i386-tbl.h: Re-generate.
950
aad09917
AM		 9512020-01-15 Alan Modra <amodra@gmail.com>
952
953 * tic4x-dis.c (tic4x_version): Make unsigned long.
954 (optab, optab_special, registernames): New file scope vars.
955 (tic4x_print_register): Set up registernames rather than
956 malloc'd registertable.
957 (tic4x_disassemble): Delete optable and optable_special. Use
958 optab and optab_special instead. Throw away old optab,
959 optab_special and registernames when info->mach changes.
960
7a6bf3be
SB		 9612020-01-14 Sergey Belyashov <sergey.belyashov@gmail.com>
962
963 PR 25377
964 * z80-dis.c (suffix): Use .db instruction to generate double
965 prefix.
966
ca1eaac0
AM		 9672020-01-14 Alan Modra <amodra@gmail.com>
968
969 * z8k-dis.c (unpack_instr): Formatting. Cast unsigned short
970 values to unsigned before shifting.
971
1d67fe3b
TT		 9722020-01-13 Thomas Troeger <tstroege@gmx.de>
973
974 * arm-dis.c (print_insn_arm): Fill in insn info fields for control
975 flow instructions.
976 (print_insn_thumb16, print_insn_thumb32): Likewise.
977 (print_insn): Initialize the insn info.
978 * i386-dis.c (print_insn): Initialize the insn info fields, and
979 detect jumps.
980
5e4f7e05
CZ		 9812012-01-13 Claudiu Zissulescu <claziss@gmail.com>
982
983 * arc-opc.c (C_NE): Make it required.
984
b9fe6b8a
CZ		 9852012-01-13 Claudiu Zissulescu <claziss@gmail.com>
986
987 * opcode/arc-dis.c (regnames): Correct ACCL/ACCH naming, fix typo
988 reserved register name.
989
90dee485
AM		 9902020-01-13 Alan Modra <amodra@gmail.com>
991
992 * ns32k-dis.c (Is_gen): Use strchr, add 'f'.
993 (print_insn_ns32k): Adjust ioffset for 'f' index_offset.
994
febda64f
AM		 9952020-01-13 Alan Modra <amodra@gmail.com>
996
997 * wasm32-dis.c (print_insn_wasm32): Localise variables. Store
998 result of wasm_read_leb128 in a uint64_t and check that bits
999 are not lost when copying to other locals. Use uint32_t for
1000 most locals. Use PRId64 when printing int64_t.
1001
df08b588
AM		 10022020-01-13 Alan Modra <amodra@gmail.com>
1003
1004 * score-dis.c: Formatting.
1005 * score7-dis.c: Formatting.
1006
b2c759ce
AM		 10072020-01-13 Alan Modra <amodra@gmail.com>
1008
1009 * score-dis.c (print_insn_score48): Use unsigned variables for
1010 unsigned values. Don't left shift negative values.
1011 (print_insn_score32): Likewise.
1012 * score7-dis.c (print_insn_score32, print_insn_score16): Likewise.
1013
5496abe1
AM		 10142020-01-13 Alan Modra <amodra@gmail.com>
1015
1016 * tic4x-dis.c (tic4x_print_register): Remove dead code.
1017
202e762b
AM		 10182020-01-13 Alan Modra <amodra@gmail.com>
1019
1020 * fr30-ibld.c: Regenerate.
1021
7ef412cf
AM		 10222020-01-13 Alan Modra <amodra@gmail.com>
1023
1024 * xgate-dis.c (print_insn): Don't left shift signed value.
1025 (ripBits): Formatting, use 1u.
1026
7f578b95
AM		 10272020-01-10 Alan Modra <amodra@gmail.com>
1028
1029 * tilepro-opc.c (parse_insn_tilepro): Make opval unsigned.
1030 * tilegx-opc.c (parse_insn_tilegx): Likewise. Delete raw_opval.
1031
441af85b
AM		 10322020-01-10 Alan Modra <amodra@gmail.com>
1033
1034 * m10300-dis.c (disassemble): Move extraction of DREG, AREG, RREG,
1035 and XRREG value earlier to avoid a shift with negative exponent.
1036 * m10200-dis.c (disassemble): Similarly.
1037
bce58db4
NC		 10382020-01-09 Nick Clifton <nickc@redhat.com>
1039
1040 PR 25224
1041 * z80-dis.c (ld_ii_ii): Use correct cast.
1042
40c75bc8
SB		 10432020-01-03 Sergey Belyashov <sergey.belyashov@gmail.com>
1044
1045 PR 25224
1046 * z80-dis.c (ld_ii_ii): Use character constant when checking
1047 opcode byte value.
1048
d835a58b
JB		 10492020-01-09 Jan Beulich <jbeulich@suse.com>
1050
1051 * i386-dis.c (SEP_Fixup): New.
1052 (SEP): Define.
1053 (dis386_twobyte): Use it for sysenter/sysexit.
1054 (enum x86_64_isa): Change amd64 enumerator to value 1.
1055 (OP_J): Compare isa64 against intel64 instead of amd64.
1056 * i386-opc.tbl (sysenter, sysexit): Split into AMD64 and Intel64
1057 forms.
1058 * i386-tbl.h: Re-generate.
1059
030a2e78
AM		 10602020-01-08 Alan Modra <amodra@gmail.com>
1061
1062 * z8k-dis.c: Include libiberty.h
1063 (instr_data_s): Make max_fetched unsigned.
1064 (z8k_lookup_instr): Make nibl_index and tabl_index unsigned.
1065 Don't exceed byte_info bounds.
1066 (output_instr): Make num_bytes unsigned.
1067 (unpack_instr): Likewise for nibl_count and loop.
1068 * z8kgen.c (gas <opcode_entry_type>): Make noperands, length and
1069 idx unsigned.
1070 * z8k-opc.h: Regenerate.
1071
bb82aefe
SV		 10722020-01-07 Shahab Vahedi <shahab@synopsys.com>
1073
1074 * arc-tbl.h (llock): Use 'LLOCK' as class.
1075 (llockd): Likewise.
1076 (scond): Use 'SCOND' as class.
1077 (scondd): Likewise.
1078 (llockd): Set data_size_mode to 'C_ZZ_D' which is 64-bit.
1079 (scondd): Likewise.
1080
cc6aa1a6
AM		 10812020-01-06 Alan Modra <amodra@gmail.com>
1082
1083 * m32c-ibld.c: Regenerate.
1084
660e62b1
AM		 10852020-01-06 Alan Modra <amodra@gmail.com>
1086
1087 PR 25344
1088 * z80-dis.c (suffix): Don't use a local struct buffer copy.
1089 Peek at next byte to prevent recursion on repeated prefix bytes.
1090 Ensure uninitialised "mybuf" is not accessed.
1091 (print_insn_z80): Don't zero n_fetch and n_used here,..
1092 (print_insn_z80_buf): ..do it here instead.
1093
c9ae58fe
AM		 10942020-01-04 Alan Modra <amodra@gmail.com>
1095
1096 * m32r-ibld.c: Regenerate.
1097
5f57d4ec
AM		 10982020-01-04 Alan Modra <amodra@gmail.com>
1099
1100 * cr16-dis.c (cr16_match_opcode): Avoid shift left of signed value.
1101
2c5c1196
AM		 11022020-01-04 Alan Modra <amodra@gmail.com>
1103
1104 * crx-dis.c (match_opcode): Avoid shift left of signed value.
1105
2e98c6c5
AM		 11062020-01-04 Alan Modra <amodra@gmail.com>
1107
1108 * d30v-dis.c (print_insn): Avoid signed overflow in left shift.
1109
567dfba2
JB		 11102020-01-03 Jan Beulich <jbeulich@suse.com>
1111
5437a02a
JB		 1112 * aarch64-tbl.h (aarch64_opcode_table): Use
1113 SVE_ADDR_RX_LSL{1,2,3} for LD1RO{H,W,D}.
1114
11152020-01-03 Jan Beulich <jbeulich@suse.com>
1116
1117 * aarch64-tbl.h (aarch64_opcode_table): Correct SIMD
567dfba2
JB		 1118 forms of SUDOT and USDOT.
1119
8c45011a
JB		 11202020-01-03 Jan Beulich <jbeulich@suse.com>
1121
5437a02a 1122 * aarch64-tbl.h (aarch64_opcode_table): Drop 'i' from
8c45011a
JB		 1123 uzip{1,2}.
1124 * opcodes/aarch64-dis-2.c: Re-generate.
1125
f4950f76
JB		 11262020-01-03 Jan Beulich <jbeulich@suse.com>
1127
5437a02a 1128 * aarch64-tbl.h (aarch64_opcode_table): Correct 64-bit
f4950f76
JB		 1129 FMMLA encoding.
1130 * opcodes/aarch64-dis-2.c: Re-generate.
1131
6655dba2
SB		 11322020-01-02 Sergey Belyashov <sergey.belyashov@gmail.com>
1133
1134 * z80-dis.c: Add support for eZ80 and Z80 instructions.
1135
b14ce8bf
AM		 11362020-01-01 Alan Modra <amodra@gmail.com>
1137
1138 Update year range in copyright notice of all files.
1139
0b114740 1140For older changes see ChangeLog-2019
3499769a 1141\f
0b114740 1142Copyright (C) 2020 Free Software Foundation, Inc.
3499769a
AM		 1143
1144Copying and distribution of this file, with or without modification,
1145are permitted in any medium without royalty provided the copyright
1146notice and this notice are preserved.
1147
1148Local Variables:
1149mode: change-log
1150left-margin: 8
1151fill-column: 74
1152version-control: never
1153End:
GDB Binutils - Deliverables
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