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x86: replace EXxmm_mdq by EXVexWdqScalar
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
4102be5c
JB		 12020-01-31 Jan Beulich <jbeulich@suse.com>
2
3 * i386-dis.c (EXxmm_mdq, xmm_mdq_mode): Delete.
4 (intel_operand_size, OP_EX): Drop xmm_mdq_mode case label.
5 (OP_E_memory): Replace xmm_mdq_mode case label by
6 vex_scalar_w_dq_mode one.
7 * i386-dis-evex-prefix.h: Replace EXxmm_mdq by EXVexWdqScalar.
8
825bd36c
JB		 92020-01-31 Jan Beulich <jbeulich@suse.com>
10
11 * i386-dis.c (EXVexWdq, vex_w_dq_mode): Delete.
12 (vex_vsib_d_w_dq_mode, vex_vsib_q_w_dq_mode,
13 vex_scalar_w_dq_mode): Don't refer to vex_w_dq_mode in comments.
14 (intel_operand_size): Drop vex_w_dq_mode case label.
15
c3036ed0
RS		 162020-01-31 Richard Sandiford <richard.sandiford@arm.com>
17
18 * aarch64-tbl.h (aarch64_opcode): Set C_MAX_ELEM for SVE bfcvt.
19 Remove C_SCAN_MOVPRFX for SVE bfcvtnt.
20
0c115f84
AM		 212020-01-30 Alan Modra <amodra@gmail.com>
22
23 * m32c-ibld.c: Regenerate.
24
bd434cc4
JM		 252020-01-30 Jose E. Marchesi <jose.marchesi@oracle.com>
26
27 * bpf-opc.c: Regenerate.
28
aeab2b26
JB		 292020-01-30 Jan Beulich <jbeulich@suse.com>
30
31 * i386-dis.c (X86_64_C2, X86_64_C3): New enumerators.
32 (dis386): Use them to replace C2/C3 table entries.
33 (x86_64_table): Add X86_64_C2 and X86_64_C3 entries.
34 * i386-opc.tbl (ret): Split Cpu64 entries into AMD64 and Intel64
35 ones. Use Size64 instead of DefaultSize on Intel64 ones.
36 * i386-tbl.h: Re-generate.
37
62b3f548
JB		 382020-01-30 Jan Beulich <jbeulich@suse.com>
39
40 * i386-opc.tbl (call): Drop DefaultSize from Intel64 JumpDword
41 forms.
42 (fldenv, fnstenv, fstenv, fnsave, fsave, frstor): Drop
43 DefaultSize.
44 * i386-tbl.h: Re-generate.
45
1bd8ae10
AM		 462020-01-30 Alan Modra <amodra@gmail.com>
47
48 * tic4x-dis.c (tic4x_dp): Make unsigned.
49
bc31405e
L		 502020-01-27 H.J. Lu <hongjiu.lu@intel.com>
51 Jan Beulich <jbeulich@suse.com>
52
53 PR binutils/25445
54 * i386-dis.c (MOVSXD_Fixup): New function.
55 (movsxd_mode): New enum.
56 (x86_64_table): Use MOVSXD_Fixup and movsxd_mode on movsxd.
57 (intel_operand_size): Handle movsxd_mode.
58 (OP_E_register): Likewise.
59 (OP_G): Likewise.
60 * i386-opc.tbl: Remove Rex64 and allow 32-bit destination
61 register on movsxd. Add movsxd with 16-bit destination register
62 for AMD64 and Intel64 ISAs.
63 * i386-tbl.h: Regenerated.
64
7568c93b
TC		 652020-01-27 Tamar Christina <tamar.christina@arm.com>
66
67 PR 25403
68 * aarch64-tbl.h (struct aarch64_opcode): Re-order cfinv.
69 * aarch64-asm-2.c: Regenerate
70 * aarch64-dis-2.c: Likewise.
71 * aarch64-opc-2.c: Likewise.
72
c006a730
JB		 732020-01-21 Jan Beulich <jbeulich@suse.com>
74
75 * i386-opc.tbl (sysret): Drop DefaultSize.
76 * i386-tbl.h: Re-generate.
77
c906a69a
JB		 782020-01-21 Jan Beulich <jbeulich@suse.com>
79
80 * i386-opc.tbl (vcvtneps2bf16x): Add Broadcast, Xmmword, and
81 Dword.
82 (vcvtneps2bf16y): Add Broadcast, Ymmword, and Dword.
83 * i386-tbl.h: Re-generate.
84
26916852
NC		 852020-01-20 Nick Clifton <nickc@redhat.com>
86
87 * po/de.po: Updated German translation.
88 * po/pt_BR.po: Updated Brazilian Portuguese translation.
89 * po/uk.po: Updated Ukranian translation.
90
4d6cbb64
AM		 912020-01-20 Alan Modra <amodra@gmail.com>
92
93 * hppa-dis.c (fput_const): Remove useless cast.
94
2bddb71a
AM		 952020-01-20 Alan Modra <amodra@gmail.com>
96
97 * arm-dis.c (print_insn_arm): Wrap 'T' value.
98
1b1bb2c6
NC		 992020-01-18 Nick Clifton <nickc@redhat.com>
100
101 * configure: Regenerate.
102 * po/opcodes.pot: Regenerate.
103
ae774686
NC		 1042020-01-18 Nick Clifton <nickc@redhat.com>
105
106 Binutils 2.34 branch created.
107
07f1f3aa
CB		 1082020-01-17 Christian Biesinger <cbiesinger@google.com>
109
110 * opintl.h: Fix spelling error (seperate).
111
42e04b36
L		 1122020-01-17 H.J. Lu <hongjiu.lu@intel.com>
113
114 * i386-opc.tbl: Add {vex} pseudo prefix.
115 * i386-tbl.h: Regenerated.
116
2da2eaf4
AV		 1172020-01-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
118
119 PR 25376
120 * opcodes/arm-dis.c (coprocessor_opcodes): Use CORE_HIGH for MVE bits.
121 (neon_opcodes): Likewise.
122 (select_arm_features): Make sure we enable MVE bits when selecting
123 armv8.1-m.main. Make sure we do not enable MVE bits when not selecting
124 any architecture.
125
d0849eed
JB		 1262020-01-16 Jan Beulich <jbeulich@suse.com>
127
128 * i386-opc.tbl: Drop stale comment from XOP section.
129
9cf70a44
JB		 1302020-01-16 Jan Beulich <jbeulich@suse.com>
131
132 * i386-opc.tbl (movq): Add VexWIG to SSE2AVX XMM->XMM forms.
133 (extractps): Add VexWIG to SSE2AVX forms.
134 * i386-tbl.h: Re-generate.
135
4814632e
JB		 1362020-01-16 Jan Beulich <jbeulich@suse.com>
137
138 * i386-opc.tbl (pextrq, pinsrq): Drop IgnoreSize and Qword. Drop
139 Size64 from and use VexW1 on SSE2AVX forms.
140 (vpextrq, vpinsrq): Drop IgnoreSize and Qword. Drop Size64 from
141 VEX-encoded forms. Add Cpu64 to EVEX-encoded forms. Use VexW1.
142 * i386-tbl.h: Re-generate.
143
aad09917
AM		 1442020-01-15 Alan Modra <amodra@gmail.com>
145
146 * tic4x-dis.c (tic4x_version): Make unsigned long.
147 (optab, optab_special, registernames): New file scope vars.
148 (tic4x_print_register): Set up registernames rather than
149 malloc'd registertable.
150 (tic4x_disassemble): Delete optable and optable_special. Use
151 optab and optab_special instead. Throw away old optab,
152 optab_special and registernames when info->mach changes.
153
7a6bf3be
SB		 1542020-01-14 Sergey Belyashov <sergey.belyashov@gmail.com>
155
156 PR 25377
157 * z80-dis.c (suffix): Use .db instruction to generate double
158 prefix.
159
ca1eaac0
AM		 1602020-01-14 Alan Modra <amodra@gmail.com>
161
162 * z8k-dis.c (unpack_instr): Formatting. Cast unsigned short
163 values to unsigned before shifting.
164
1d67fe3b
TT		 1652020-01-13 Thomas Troeger <tstroege@gmx.de>
166
167 * arm-dis.c (print_insn_arm): Fill in insn info fields for control
168 flow instructions.
169 (print_insn_thumb16, print_insn_thumb32): Likewise.
170 (print_insn): Initialize the insn info.
171 * i386-dis.c (print_insn): Initialize the insn info fields, and
172 detect jumps.
173
5e4f7e05
CZ		 1742012-01-13 Claudiu Zissulescu <claziss@gmail.com>
175
176 * arc-opc.c (C_NE): Make it required.
177
b9fe6b8a
CZ		 1782012-01-13 Claudiu Zissulescu <claziss@gmail.com>
179
180 * opcode/arc-dis.c (regnames): Correct ACCL/ACCH naming, fix typo
181 reserved register name.
182
90dee485
AM		 1832020-01-13 Alan Modra <amodra@gmail.com>
184
185 * ns32k-dis.c (Is_gen): Use strchr, add 'f'.
186 (print_insn_ns32k): Adjust ioffset for 'f' index_offset.
187
febda64f
AM		 1882020-01-13 Alan Modra <amodra@gmail.com>
189
190 * wasm32-dis.c (print_insn_wasm32): Localise variables. Store
191 result of wasm_read_leb128 in a uint64_t and check that bits
192 are not lost when copying to other locals. Use uint32_t for
193 most locals. Use PRId64 when printing int64_t.
194
df08b588
AM		 1952020-01-13 Alan Modra <amodra@gmail.com>
196
197 * score-dis.c: Formatting.
198 * score7-dis.c: Formatting.
199
b2c759ce
AM		 2002020-01-13 Alan Modra <amodra@gmail.com>
201
202 * score-dis.c (print_insn_score48): Use unsigned variables for
203 unsigned values. Don't left shift negative values.
204 (print_insn_score32): Likewise.
205 * score7-dis.c (print_insn_score32, print_insn_score16): Likewise.
206
5496abe1
AM		 2072020-01-13 Alan Modra <amodra@gmail.com>
208
209 * tic4x-dis.c (tic4x_print_register): Remove dead code.
210
202e762b
AM		 2112020-01-13 Alan Modra <amodra@gmail.com>
212
213 * fr30-ibld.c: Regenerate.
214
7ef412cf
AM		 2152020-01-13 Alan Modra <amodra@gmail.com>
216
217 * xgate-dis.c (print_insn): Don't left shift signed value.
218 (ripBits): Formatting, use 1u.
219
7f578b95
AM		 2202020-01-10 Alan Modra <amodra@gmail.com>
221
222 * tilepro-opc.c (parse_insn_tilepro): Make opval unsigned.
223 * tilegx-opc.c (parse_insn_tilegx): Likewise. Delete raw_opval.
224
441af85b
AM		 2252020-01-10 Alan Modra <amodra@gmail.com>
226
227 * m10300-dis.c (disassemble): Move extraction of DREG, AREG, RREG,
228 and XRREG value earlier to avoid a shift with negative exponent.
229 * m10200-dis.c (disassemble): Similarly.
230
bce58db4
NC		 2312020-01-09 Nick Clifton <nickc@redhat.com>
232
233 PR 25224
234 * z80-dis.c (ld_ii_ii): Use correct cast.
235
40c75bc8
SB		 2362020-01-03 Sergey Belyashov <sergey.belyashov@gmail.com>
237
238 PR 25224
239 * z80-dis.c (ld_ii_ii): Use character constant when checking
240 opcode byte value.
241
d835a58b
JB		 2422020-01-09 Jan Beulich <jbeulich@suse.com>
243
244 * i386-dis.c (SEP_Fixup): New.
245 (SEP): Define.
246 (dis386_twobyte): Use it for sysenter/sysexit.
247 (enum x86_64_isa): Change amd64 enumerator to value 1.
248 (OP_J): Compare isa64 against intel64 instead of amd64.
249 * i386-opc.tbl (sysenter, sysexit): Split into AMD64 and Intel64
250 forms.
251 * i386-tbl.h: Re-generate.
252
030a2e78
AM		 2532020-01-08 Alan Modra <amodra@gmail.com>
254
255 * z8k-dis.c: Include libiberty.h
256 (instr_data_s): Make max_fetched unsigned.
257 (z8k_lookup_instr): Make nibl_index and tabl_index unsigned.
258 Don't exceed byte_info bounds.
259 (output_instr): Make num_bytes unsigned.
260 (unpack_instr): Likewise for nibl_count and loop.
261 * z8kgen.c (gas <opcode_entry_type>): Make noperands, length and
262 idx unsigned.
263 * z8k-opc.h: Regenerate.
264
bb82aefe
SV		 2652020-01-07 Shahab Vahedi <shahab@synopsys.com>
266
267 * arc-tbl.h (llock): Use 'LLOCK' as class.
268 (llockd): Likewise.
269 (scond): Use 'SCOND' as class.
270 (scondd): Likewise.
271 (llockd): Set data_size_mode to 'C_ZZ_D' which is 64-bit.
272 (scondd): Likewise.
273
cc6aa1a6
AM		 2742020-01-06 Alan Modra <amodra@gmail.com>
275
276 * m32c-ibld.c: Regenerate.
277
660e62b1
AM		 2782020-01-06 Alan Modra <amodra@gmail.com>
279
280 PR 25344
281 * z80-dis.c (suffix): Don't use a local struct buffer copy.
282 Peek at next byte to prevent recursion on repeated prefix bytes.
283 Ensure uninitialised "mybuf" is not accessed.
284 (print_insn_z80): Don't zero n_fetch and n_used here,..
285 (print_insn_z80_buf): ..do it here instead.
286
c9ae58fe
AM		 2872020-01-04 Alan Modra <amodra@gmail.com>
288
289 * m32r-ibld.c: Regenerate.
290
5f57d4ec
AM		 2912020-01-04 Alan Modra <amodra@gmail.com>
292
293 * cr16-dis.c (cr16_match_opcode): Avoid shift left of signed value.
294
2c5c1196
AM		 2952020-01-04 Alan Modra <amodra@gmail.com>
296
297 * crx-dis.c (match_opcode): Avoid shift left of signed value.
298
2e98c6c5
AM		 2992020-01-04 Alan Modra <amodra@gmail.com>
300
301 * d30v-dis.c (print_insn): Avoid signed overflow in left shift.
302
567dfba2
JB		 3032020-01-03 Jan Beulich <jbeulich@suse.com>
304
5437a02a
JB		 305 * aarch64-tbl.h (aarch64_opcode_table): Use
306 SVE_ADDR_RX_LSL{1,2,3} for LD1RO{H,W,D}.
307
3082020-01-03 Jan Beulich <jbeulich@suse.com>
309
310 * aarch64-tbl.h (aarch64_opcode_table): Correct SIMD
567dfba2
JB		 311 forms of SUDOT and USDOT.
312
8c45011a
JB		 3132020-01-03 Jan Beulich <jbeulich@suse.com>
314
5437a02a 315 * aarch64-tbl.h (aarch64_opcode_table): Drop 'i' from
8c45011a
JB		 316 uzip{1,2}.
317 * opcodes/aarch64-dis-2.c: Re-generate.
318
f4950f76
JB		 3192020-01-03 Jan Beulich <jbeulich@suse.com>
320
5437a02a 321 * aarch64-tbl.h (aarch64_opcode_table): Correct 64-bit
f4950f76
JB		 322 FMMLA encoding.
323 * opcodes/aarch64-dis-2.c: Re-generate.
324
6655dba2
SB		 3252020-01-02 Sergey Belyashov <sergey.belyashov@gmail.com>
326
327 * z80-dis.c: Add support for eZ80 and Z80 instructions.
328
b14ce8bf
AM		 3292020-01-01 Alan Modra <amodra@gmail.com>
330
331 Update year range in copyright notice of all files.
332
0b114740 333For older changes see ChangeLog-2019
3499769a 334\f
0b114740 335Copyright (C) 2020 Free Software Foundation, Inc.
3499769a
AM		 336
337Copying and distribution of this file, with or without modification,
338are permitted in any medium without royalty provided the copyright
339notice and this notice are preserved.
340
341Local Variables:
342mode: change-log
343left-margin: 8
344fill-column: 74
345version-control: never
346End:
GDB Binutils - Deliverables
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