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[Patch][binutils][arm] Armv8.6-A Matrix Multiply extension [9/10]
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
616ce08e
MM		 12019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
2
3 * arm-dis.c (neon_opcodes): Add i8mm SIMD instructions.
4
5
8382113f
MM		 62019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
7
8 * aarch64-tbl.h (aarch64_feature_i8mm_sve, aarch64_feature_f32mm_sve,
9 aarch64_feature_f64mm_sve, aarch64_feature_i8mm, aarch64_feature_f32mm,
10 aarch64_feature_f64mm): New feature sets.
11 (INT8MATMUL_INSN, F64MATMUL_SVE_INSN, F64MATMUL_INSN,
12 F32MATMUL_SVE_INSN, F32MATMUL_INSN): New macros to define matrix multiply
13 instructions.
14 (I8MM_SVE, F32MM_SVE, F64MM_SVE, I8MM, F32MM, F64MM): New feature set
15 macros.
16 (QL_MMLA64, OP_SVE_SBB): New qualifiers.
17 (OP_SVE_QQQ): New qualifier.
18 (INT8MATMUL_SVE_INSNC, F64MATMUL_SVE_INSNC,
19 F32MATMUL_SVE_INSNC): New feature set for bfloat16 instructions to support
20 the movprfx constraint.
21 (aarch64_opcode_table): Support for SVE_ADDR_RI_S4x32.
22 (aarch64_opcode_table): Define new instructions smmla,
23 ummla, usmmla, usdot, sudot, fmmla, ld1rob, ld1roh, ld1row, ld1rod,
24 uzip{1/2}, trn{1/2}.
25 * aarch64-opc.c (operand_general_constraint_met_p): Handle
26 AARCH64_OPND_SVE_ADDR_RI_S4x32.
27 (aarch64_print_operand): Handle AARCH64_OPND_SVE_ADDR_RI_S4x32.
28 * aarch64-dis-2.c (aarch64_opcode_lookup_1, aarch64_find_next_opcode):
29 Account for new instructions.
30 * opcodes/aarch64-asm-2.c (aarch64_insert_operand): Support the new
31 S4x32 operand.
32 * aarch64-opc-2.c (aarch64_operands): Support the new S4x32 operand.
33
aab2c27d
MM		 342019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
352019-11-07 Matthew Malcomson <matthew.malcomson@arm.com>
36
37 * arm-dis.c (select_arm_features): Update bfd_march_arm_8 with
38 Armv8.6-A.
39 (coprocessor_opcodes): Add bfloat16 vcvt{t,b}.
40 (neon_opcodes): Add bfloat SIMD instructions.
41 (print_insn_coprocessor): Add new control character %b to print
42 condition code without checking cp_num.
43 (print_insn_neon): Account for BFloat16 instructions that have no
44 special top-byte handling.
45
33593eaf
MM		 462019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
472019-11-07 Matthew Malcomson <matthew.malcomson@arm.com>
48
49 * arm-dis.c (print_insn_coprocessor,
50 print_insn_generic_coprocessor): Create wrapper functions around
51 the implementation of the print_insn_coprocessor control codes.
52 (print_insn_coprocessor_1): Original print_insn_coprocessor
53 function that now takes which array to look at as an argument.
54 (print_insn_arm): Use both print_insn_coprocessor and
55 print_insn_generic_coprocessor.
56 (print_insn_thumb32): As above.
57
df678013
MM		 582019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
592019-11-07 Matthew Malcomson <matthew.malcomson@arm.com>
60
61 * aarch64-asm.c (aarch64_ins_reglane): Use AARCH64_OPND_QLF_S_2H
62 in reglane special case.
63 * aarch64-dis-2.c (aarch64_opcode_lookup_1,
64 aarch64_find_next_opcode): Account for new instructions.
65 * aarch64-dis.c (aarch64_ext_reglane): Use AARCH64_OPND_QLF_S_2H
66 in reglane special case.
67 * aarch64-opc.c (struct operand_qualifier_data): Add data for
68 new AARCH64_OPND_QLF_S_2H qualifier.
69 * aarch64-tbl.h (QL_BFDOT QL_BFDOT64, QL_BFDOT64I, QL_BFMMLA2,
70 QL_BFCVT64, QL_BFCVTN64, QL_BFCVTN2_64): New qualifiers.
71 (aarch64_feature_bfloat16, aarch64_feature_bfloat16_sve): New feature
72 sets.
73 (BFLOAT_SVE, BFLOAT): New feature set macros.
74 (BFLOAT_SVE_INSN, BFLOAT_INSN): New macros to define BFloat16
75 instructions.
76 (aarch64_opcode_table): Define new instructions bfdot,
77 bfmmla, bfcvt, bfcvtnt, bfdot, bfdot, bfcvtn, bfmlal[b/t]
78 bfcvtn2, bfcvt.
79
8ae2d3d9
MM		 802019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
812019-11-07 Matthew Malcomson <matthew.malcomson@arm.com>
82
83 * aarch64-tbl.h (ARMV8_6): New macro.
84
142861df
JB		 852019-11-07 Jan Beulich <jbeulich@suse.com>
86
87 * i386-dis.c (prefix_table): Add mcommit.
88 (rm_table): Add rdpru.
89 * i386-gen.c (cpu_flag_init): Adjust CPU_ZNVER2_FLAGS entry. Add
90 CPU_RDPRU_FLAGS and CPU_MCOMMIT_FLAGS entries.
91 (cpu_flags): Add CpuRDPRU and CpuMCOMMIT entries.
92 * i386-opc.h (CpuRDPRU, CpuMCOMMIT): New.
93 (union i386_cpu_flags): Add cpurdpru and cpumcommit fields.
94 * i386-opc.tbl (mcommit, rdpru): New.
95 * i386-init.h, i386-tbl.h: Re-generate.
96
081e283f
JB		 972019-11-07 Jan Beulich <jbeulich@suse.com>
98
99 * i386-dis.c (OP_Mwait): Drop local variable "names", use
100 "names32" instead.
101 (OP_Monitor): Drop local variable "op1_names", re-purpose
102 "names" for it instead, and replace former "names" uses by
103 "names32" ones.
104
c050c89a
JB		 1052019-11-07 Jan Beulich <jbeulich@suse.com>
106
107 PR/gas 25167
108 * opcodes/i386-opc.tbl (movsd, cmpsd): Drop IgnoreSize from
109 operand-less forms.
110 * opcodes/i386-tbl.h: Re-generate.
111
7abb8d81
JB		 1122019-11-05 Jan Beulich <jbeulich@suse.com>
113
114 * i386-dis.c (OP_Mwaitx): Delete.
115 (prefix_table): Use OP_Mwait for mwaitx entry.
116 (OP_Mwait): Also handle mwaitx.
117
267b8516
JB		 1182019-11-05 Jan Beulich <jbeulich@suse.com>
119
120 * i386-dis.c (PREFIX_0F01_REG_7_MOD_3_RM_2,
121 PREFIX_0F01_REG_7_MOD_3_RM_3): New.
122 (prefix_table): Add respective entries.
123 (rm_table): Link to those entries.
124
f8687e93
JB		 1252019-11-05 Jan Beulich <jbeulich@suse.com>
126
127 * i386-dis.c (REG_0F1C_MOD_0): Rename to ...
128 (REG_0F1C_P_0_MOD_0): ... this.
129 (REG_0F1E_MOD_3): Rename to ...
130 (REG_0F1E_P_1_MOD_3): ... this.
131 (RM_0F01_REG_5): Rename to ...
132 (RM_0F01_REG_5_MOD_3): ... this.
133 (RM_0F01_REG_7): Rename to ...
134 (RM_0F01_REG_7_MOD_3): ... this.
135 (RM_0F1E_MOD_3_REG_7): Rename to ...
136 (RM_0F1E_P_1_MOD_3_REG_7): ... this.
137 (RM_0FAE_REG_6): Rename to ...
138 (RM_0FAE_REG_6_MOD_3_P_0): ... this.
139 (RM_0FAE_REG_7): Rename to ...
140 (RM_0FAE_REG_7_MOD_3): ... this.
141 (PREFIX_MOD_0_0F01_REG_5): Rename to ...
142 (PREFIX_0F01_REG_5_MOD_0): ... this.
143 (PREFIX_MOD_3_0F01_REG_5_RM_0): Rename to ...
144 (PREFIX_0F01_REG_5_MOD_3_RM_0): ... this.
145 (PREFIX_MOD_3_0F01_REG_5_RM_2): Rename to ...
146 (PREFIX_0F01_REG_5_MOD_3_RM_2): ... this.
147 (PREFIX_0FAE_REG_0): Rename to ...
148 (PREFIX_0FAE_REG_0_MOD_3): ... this.
149 (PREFIX_0FAE_REG_1): Rename to ...
150 (PREFIX_0FAE_REG_1_MOD_3): ... this.
151 (PREFIX_0FAE_REG_2): Rename to ...
152 (PREFIX_0FAE_REG_2_MOD_3): ... this.
153 (PREFIX_0FAE_REG_3): Rename to ...
154 (PREFIX_0FAE_REG_3_MOD_3): ... this.
155 (PREFIX_MOD_0_0FAE_REG_4): Rename to ...
156 (PREFIX_0FAE_REG_4_MOD_0): ... this.
157 (PREFIX_MOD_3_0FAE_REG_4): Rename to ...
158 (PREFIX_0FAE_REG_4_MOD_3): ... this.
159 (PREFIX_MOD_0_0FAE_REG_5): Rename to ...
160 (PREFIX_0FAE_REG_5_MOD_0): ... this.
161 (PREFIX_MOD_3_0FAE_REG_5): Rename to ...
162 (PREFIX_0FAE_REG_5_MOD_3): ... this.
163 (PREFIX_MOD_0_0FAE_REG_6): Rename to ...
164 (PREFIX_0FAE_REG_6_MOD_0): ... this.
165 (PREFIX_MOD_1_0FAE_REG_6): Rename to ...
166 (PREFIX_0FAE_REG_6_MOD_3): ... this.
167 (PREFIX_0FAE_REG_7): Rename to ...
168 (PREFIX_0FAE_REG_7_MOD_0): ... this.
169 (PREFIX_MOD_0_0FC3): Rename to ...
170 (PREFIX_0FC3_MOD_0): ... this.
171 (PREFIX_MOD_0_0FC7_REG_6): Rename to ...
172 (PREFIX_0FC7_REG_6_MOD_0): ... this.
173 (PREFIX_MOD_3_0FC7_REG_6): Rename to ...
174 (PREFIX_0FC7_REG_6_MOD_3): ... this.
175 (PREFIX_MOD_3_0FC7_REG_7): Rename to ...
176 (PREFIX_0FC7_REG_7_MOD_3): ... this.
177 (reg_table, prefix_table, mod_table, rm_table): Adjust
178 accordingly.
179
5103274f
NC		 1802019-11-04 Nick Clifton <nickc@redhat.com>
181
182 * v850-dis.c (get_v850_sreg_name): New function. Returns the name
183 of a v850 system register. Move the v850_sreg_names array into
184 this function.
185 (get_v850_reg_name): Likewise for ordinary register names.
186 (get_v850_vreg_name): Likewise for vector register names.
187 (get_v850_cc_name): Likewise for condition codes.
188 * get_v850_float_cc_name): Likewise for floating point condition
189 codes.
190 (get_v850_cacheop_name): Likewise for cache-ops.
191 (get_v850_prefop_name): Likewise for pref-ops.
192 (disassemble): Use the new accessor functions.
193
1820262b
DB		 1942019-10-30 Delia Burduv <delia.burduv@arm.com>
195
196 * aarch64-opc.c (print_immediate_offset_address): Don't print the
197 immediate for the writeback form of ldraa/ldrab if it is 0.
198 * aarch64-tbl.h: Updated the documentation for ADDR_SIMM10.
199 * aarch64-opc-2.c: Regenerated.
200
3cc17af5
JB		 2012019-10-30 Jan Beulich <jbeulich@suse.com>
202
203 * i386-gen.c (operand_type_shorthands): Delete.
204 (operand_type_init): Expand previous shorthands.
205 (set_bitfield_from_shorthand): Rename back to ...
206 (set_bitfield_from_cpu_flag_init): ... this. Drop processing
207 of operand_type_init[].
208 (set_bitfield): Adjust call to the above function.
209 * i386-opc.tbl (Reg8, Reg16, Reg32, Reg64, FloatAcc, FloatReg,
210 RegXMM, RegYMM, RegZMM): Define.
211 * i386-reg.tbl: Expand prior shorthands.
212
a2cebd03
JB		 2132019-10-30 Jan Beulich <jbeulich@suse.com>
214
215 * i386-gen.c (output_i386_opcode): Change order of fields
216 emitted to output.
217 * i386-opc.h (struct insn_template): Move operands field.
218 Convert extension_opcode field to unsigned short.
219 * i386-tbl.h: Re-generate.
220
507916b8
JB		 2212019-10-30 Jan Beulich <jbeulich@suse.com>
222
223 * i386-gen.c (process_i386_opcode_modifier): Report bogus uses
224 of W.
225 * i386-opc.h (W): Extend comment.
226 * i386-opc.tbl (mov, movabs, movq): Drop W and adjust opcodes of
227 general purpose variants not allowing for byte operands.
228 * i386-tbl.h: Re-generate.
229
efea62b4
NC		 2302019-10-29 Nick Clifton <nickc@redhat.com>
231
232 * tic30-dis.c (print_branch): Correct size of operand array.
233
9adb2591
NC		 2342019-10-29 Nick Clifton <nickc@redhat.com>
235
236 * d30v-dis.c (print_insn): Check that operand index is valid
237 before attempting to access the operands array.
238
993a00a9
NC		 2392019-10-29 Nick Clifton <nickc@redhat.com>
240
241 * ia64-opc.c (locate_opcode_ent): Prevent a negative shift when
242 locating the bit to be tested.
243
66a66a17
NC		 2442019-10-29 Nick Clifton <nickc@redhat.com>
245
246 * s12z-dis.c (opr_emit_disassembly): Check for illegal register
247 values.
248 (shift_size_table): Use a fixed size defined as S12Z_N_SIZES.
249 (print_insn_s12z): Check for illegal size values.
250
1ee3542c
NC		 2512019-10-28 Nick Clifton <nickc@redhat.com>
252
253 * csky-dis.c (csky_chars_to_number): Check for a negative
254 count. Use an unsigned integer to construct the return value.
255
bbf9a0b5
NC		 2562019-10-28 Nick Clifton <nickc@redhat.com>
257
258 * tic30-dis.c (OPERAND_BUFFER_LEN): Define. Use as length of
259 operand buffer. Set value to 15 not 13.
260 (get_register_operand): Use OPERAND_BUFFER_LEN.
261 (get_indirect_operand): Likewise.
262 (print_two_operand): Likewise.
263 (print_three_operand): Likewise.
264 (print_oar_insn): Likewise.
265
d1e304bc
NC		 2662019-10-28 Nick Clifton <nickc@redhat.com>
267
268 * ns32k-dis.c (bit_extract): Add sanitiy check of parameters.
269 (bit_extract_simple): Likewise.
270 (bit_copy): Likewise.
271 (pirnt_insn_ns32k): Ensure that uninitialised elements in the
272 index_offset array are not accessed.
273
dee33451
NC		 2742019-10-28 Nick Clifton <nickc@redhat.com>
275
276 * xgate-dis.c (print_insn): Fix decoding of the XGATE_OP_DYA
277 operand.
278
27cee81d
NC		 2792019-10-25 Nick Clifton <nickc@redhat.com>
280
281 * rx-dis.c (print_insn_rx): Use parenthesis to ensure correct
282 access to opcodes.op array element.
283
de6d8dc2
NC		 2842019-10-23 Nick Clifton <nickc@redhat.com>
285
286 * rx-dis.c (get_register_name): Fix spelling typo in error
287 message.
288 (get_condition_name, get_flag_name, get_double_register_name)
289 (get_double_register_high_name, get_double_register_low_name)
290 (get_double_control_register_name, get_double_condition_name)
291 (get_opsize_name, get_size_name): Likewise.
292
6207ed28
NC		 2932019-10-22 Nick Clifton <nickc@redhat.com>
294
295 * rx-dis.c (get_size_name): New function. Provides safe
296 access to name array.
297 (get_opsize_name): Likewise.
298 (print_insn_rx): Use the accessor functions.
299
12234dfd
NC		 3002019-10-16 Nick Clifton <nickc@redhat.com>
301
302 * rx-dis.c (get_register_name): New function. Provides safe
303 access to name array.
304 (get_condition_name, get_flag_name, get_double_register_name)
305 (get_double_register_high_name, get_double_register_low_name)
306 (get_double_control_register_name, get_double_condition_name):
307 Likewise.
308 (print_insn_rx): Use the accessor functions.
309
1d378749
NC		 3102019-10-09 Nick Clifton <nickc@redhat.com>
311
312 PR 25041
313 * avr-dis.c (avr_operand): Fix construction of address for lds/sts
314 instructions.
315
d241b910
JB		 3162019-10-07 Jan Beulich <jbeulich@suse.com>
317
318 * opcodes/i386-opc.tbl (movsd): Add Dword and IgnoreSize.
319 (cmpsd): Likewise. Move EsSeg to other operand.
320 * opcodes/i386-tbl.h: Re-generate.
321
f5c5b7c1
AM		 3222019-09-23 Alan Modra <amodra@gmail.com>
323
324 * m68k-dis.c: Include cpu-m68k.h
325
7beeaeb8
AM		 3262019-09-23 Alan Modra <amodra@gmail.com>
327
328 * mips-dis.c: Include elfxx-mips.h. Move "elf-bfd.h" and
329 "elf/mips.h" earlier.
330
3f9aad11
JB		 3312018-09-20 Jan Beulich <jbeulich@suse.com>
332
333 PR gas/25012
334 * i386-opc.tbl (push, pop): Re-instate distinct Cpu64 templates
335 with SReg operand.
336 * i386-tbl.h: Re-generate.
337
fd361982
AM		 3382019-09-18 Alan Modra <amodra@gmail.com>
339
340 * arc-ext.c: Update throughout for bfd section macro changes.
341
e0b2a78c
SM		 3422019-09-18 Simon Marchi <simon.marchi@polymtl.ca>
343
344 * Makefile.in: Re-generate.
345 * configure: Re-generate.
346
7e9ad3a3
JW		 3472019-09-17 Maxim Blinov <maxim.blinov@embecosm.com>
348
349 * riscv-opc.c (riscv_opcodes): Change subset field
350 to insn_class field for all instructions.
351 (riscv_insn_types): Likewise.
352
bb695960
PB		 3532019-09-16 Phil Blundell <pb@pbcl.net>
354
355 * configure: Regenerated.
356
8063ab7e
MV		 3572019-09-10 Miod Vallat <miod@online.fr>
358
359 PR 24982
360 * m68k-opc.c: Correct aliases for tdivsl and tdivul.
361
60391a25
PB		 3622019-09-09 Phil Blundell <pb@pbcl.net>
363
364 binutils 2.33 branch created.
365
f44b758d
NC		 3662019-09-03 Nick Clifton <nickc@redhat.com>
367
368 PR 24961
369 * tic30-dis.c (get_indirect_operand): Check for bufcnt being
370 greater than zero before indexing via (bufcnt -1).
371
1e4b5e7d
NC		 3722019-09-03 Nick Clifton <nickc@redhat.com>
373
374 PR 24958
375 * mmix-dis.c (MAX_REG_NAME_LEN): Define.
376 (MAX_SPEC_REG_NAME_LEN): Define.
377 (struct mmix_dis_info): Use defined constants for array lengths.
378 (get_reg_name): New function.
379 (get_sprec_reg_name): New function.
380 (print_insn_mmix): Use new functions.
381
c4a23bf8
SP		 3822019-08-27 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
383
384 * arm-dis.c (mve_opcodes): Add entry for MVE_VMOV_VEC_TO_VEC.
385 (is_mve_undefined): Add case for MVE_VMOV_VEC_TO_VEC.
386 (print_insn_mve): Add condition to check Qm==Qn of VORR instruction.
387
a051e2f3
KT		 3882019-08-22 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
389
390 * aarch64-opc.c (aarch64_sys_regs): Update encoding of tfsre0_el1,
391 tfsr_el1, tfsr_el2, tfsr_el3, tfsr_el12.
392 (aarch64_sys_reg_supported_p): Update checks for the above.
393
08132bdd
SP		 3942019-08-12 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
395
396 * arm-dis.c (struct mopcode32 mve_opcodes): Modify the mask for
397 cases MVE_SQRSHRL and MVE_UQRSHLL.
398 (print_insn_mve): Add case for specifier 'k' to check
399 specific bit of the instruction.
400
d88bdcb4
PA		 4012019-08-07 Phillipe Antoine <p.antoine@catenacyber.fr>
402
403 PR 24854
404 * arc-dis.c (arc_insn_length): Return 0 rather than aborting when
405 encountering an unknown machine type.
406 (print_insn_arc): Handle arc_insn_length returning 0. In error
407 cases return -1 rather than calling abort.
408
bc750500
JB		 4092019-08-07 Jan Beulich <jbeulich@suse.com>
410
411 * i386-opc.tbl (fld, fstp): Drop FloatMF from extended forms.
412 (fldcw, fnstcw, fstcw, fnstsw, fstsw): Replace FloatMF by
413 IgnoreSize.
414 * i386-tbl.h: Re-generate.
415
23d188c7
BW		 4162019-08-05 Barnaby Wilks <barnaby.wilks@arm.com>
417
418 * arm-dis.c: Only accept signed variants of VQ(R)DMLAH and VQ(R)DMLASH
419 instructions.
420
c0d6f62f
JW		 4212019-07-30 Mel Chen <mel.chen@sifive.com>
422
423 * riscv-opc.c (riscv_opcodes): Set frsr, fssr, frcsr, fscsr, frrm,
424 fsrm, fsrmi, frflags, fsflags, fsflagsi to alias instructions.
425
426 * riscv-opc.c (riscv_opcodes): Adjust order of frsr, frcsr, fssr,
427 fscsr.
428
0f3f7167
CZ		 4292019-07-24 Claudiu Zissulescu <claziss@synopsys.com>
430
431 * arc-dis.c (skip_this_opcode): Check also for 0x07 major opcodes,
432 and MPY class instructions.
433 (parse_option): Add nps400 option.
434 (print_arc_disassembler_options): Add nps400 info.
435
7e126ba3
CZ		 4362019-07-24 Claudiu Zissulescu <claziss@synopsys.com>
437
438 * arc-ext-tbl.h (bspeek): Remove it, added to main table.
439 (bspop): Likewise.
440 (modapp): Likewise.
441 * arc-opc.c (RAD_CHK): Add.
442 * arc-tbl.h: Regenerate.
443
a028026d
KT		 4442019-07-23 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
445
446 * aarch64-opc.c (aarch64_sys_regs): Add gmid_el1 entry.
447 (aarch64_sys_reg_supported_p): Handle gmid_el1 encoding.
448
ac79ff9e
NC		 4492019-07-22 Barnaby Wilks <barnaby.wilks@arm.com>
450
451 * arm-dis.c (is_mve_unpredictable): Stop marking some MVE
452 instructions as UNPREDICTABLE.
453
231097b0
JM		 4542019-07-19 Jose E. Marchesi <jose.marchesi@oracle.com>
455
456 * bpf-desc.c: Regenerated.
457
1d942ae9
JB		 4582019-07-17 Jan Beulich <jbeulich@suse.com>
459
460 * i386-gen.c (static_assert): Define.
461 (main): Use it.
462 * i386-opc.h (Opcode_Modifier_Max): Rename to ...
463 (Opcode_Modifier_Num): ... this.
464 (Mem): Delete.
465
dfd69174
JB		 4662019-07-16 Jan Beulich <jbeulich@suse.com>
467
468 * i386-gen.c (operand_types): Move RegMem ...
469 (opcode_modifiers): ... here.
470 * i386-opc.h (RegMem): Move to opcode modifer enum.
471 (union i386_operand_type): Move regmem field ...
472 (struct i386_opcode_modifier): ... here.
473 * i386-opc.tbl (RegMem): Define.
474 (mov, movq): Move RegMem on segment, control, debug, and test
475 register flavors.
476 (pextrb): Move RegMem on register only flavors. Add IgnoreSize
477 to non-SSE2AVX flavor.
478 (extractps, pextrw, vcvtps2ph, vextractps, vpextrb, vpextrw):
479 Move RegMem on register only flavors. Drop IgnoreSize from
480 legacy encoding flavors.
481 (movss, movsd, vmovss, vmovsd): Drop RegMem from register only
482 flavors.
483 (vpinsrb, vpinsrw): Drop IgnoreSize where still present on
484 register only flavors.
485 (vmovd): Move RegMem and drop IgnoreSize on register only
486 flavor. Change opcode and operand order to store form.
487 * opcodes/i386-init.h, i386-tbl.h: Re-generate.
488
21df382b
JB		 4892019-07-16 Jan Beulich <jbeulich@suse.com>
490
491 * i386-gen.c (operand_type_init, operand_types): Replace SReg
492 entries.
493 * i386-opc.h (SReg2, SReg3): Replace by ...
494 (SReg): ... this.
495 (union i386_operand_type): Replace sreg fields.
496 * i386-opc.tbl (mov, ): Use SReg.
497 (push, pop): Likewies. Drop i386 and x86-64 specific segment
498 register flavors.
499 * i386-reg.tbl (cs, ds, es, fs, gs, ss, flat): Use SReg.
500 * opcodes/i386-init.h, i386-tbl.h: Re-generate.
501
3719fd55
JM		 5022019-07-15 Jose E. Marchesi <jose.marchesi@oracle.com>
503
504 * bpf-desc.c: Regenerate.
505 * bpf-opc.c: Likewise.
506 * bpf-opc.h: Likewise.
507
92434a14
JM		 5082019-07-14 Jose E. Marchesi <jose.marchesi@oracle.com>
509
510 * bpf-desc.c: Regenerate.
511 * bpf-opc.c: Likewise.
512
43dd7626
HPN		 5132019-07-10 Hans-Peter Nilsson <hp@bitrange.com>
514
515 * arm-dis.c (print_insn_coprocessor): Rename index to
516 index_operand.
517
98602811
JW		 5182019-07-05 Kito Cheng <kito.cheng@sifive.com>
519
520 * riscv-opc.c (riscv_insn_types): Add r4 type.
521
522 * riscv-opc.c (riscv_insn_types): Add b and j type.
523
524 * opcodes/riscv-opc.c (riscv_insn_types): Remove incorrect
525 format for sb type and correct s type.
526
01c1ee4a
RS		 5272019-07-02 Richard Sandiford <richard.sandiford@arm.com>
528
529 * aarch64-tbl.h (aarch64_opcode): Set C_SCAN_MOVPRFX for the
530 SVE FMOV alias of FCPY.
531
83adff69
RS		 5322019-07-02 Richard Sandiford <richard.sandiford@arm.com>
533
534 * aarch64-tbl.h (aarch64_opcode_table): Add C_MAX_ELEM flags
535 to SVE fcvtzs, fcvtzu, scvtf and ucvtf entries.
536
89418844
RS		 5372019-07-02 Richard Sandiford <richard.sandiford@arm.com>
538
539 * aarch64-opc.c (verify_constraints): Skip GPRs when scanning the
540 registers in an instruction prefixed by MOVPRFX.
541
41be57ca
MM		 5422019-07-01 Matthew Malcomson <matthew.malcomson@arm.com>
543
544 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Use new
545 sve_size_13 icode to account for variant behaviour of
546 pmull{t,b}.
547 * aarch64-dis-2.c: Regenerate.
548 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Use new
549 sve_size_13 icode to account for variant behaviour of
550 pmull{t,b}.
551 * aarch64-tbl.h (OP_SVE_VVV_HD_BS): Add new qualifier.
552 (OP_SVE_VVV_Q_D): Add new qualifier.
553 (OP_SVE_VVV_QHD_DBS): Remove now unused qualifier.
554 (struct aarch64_opcode): Split pmull{t,b} into those requiring
555 AES and those not.
556
9d3bf266
JB		 5572019-07-01 Jan Beulich <jbeulich@suse.com>
558
559 * opcodes/i386-gen.c (operand_type_init): Remove
560 OPERAND_TYPE_VEC_IMM4 entry.
561 (operand_types): Remove Vec_Imm4.
562 * opcodes/i386-opc.h (Vec_Imm4): Delete.
563 (union i386_operand_type): Remove vec_imm4.
564 * i386-opc.tbl (vpermil2pd, vpermil2ps): Remove Vec_Imm4.
565 * opcodes/i386-init.h, i386-tbl.h: Re-generate.
566
c3949f43
JB		 5672019-07-01 Jan Beulich <jbeulich@suse.com>
568
569 * i386-opc.tbl (lfence, mfence, sfence, monitor, mwait, vmcall,
570 vmlaunch, vmresume, vmxoff, vmfunc, xgetbv, xsetbv, swapgs,
571 rdtscp, clgi, invlpga, skinit, stgi, vmload, vmmcall, vmrun,
572 vmsave, montmul, xsha1, xsha256, xstorerng, xcryptecb,
573 xcryptcbc, xcryptctr, xcryptcfb, xcryptofb, xstore, clac, stac,
574 monitorx, mwaitx): Drop ImmExt from operand-less forms.
575 * i386-tbl.h: Re-generate.
576
5641ec01
JB		 5772019-07-01 Jan Beulich <jbeulich@suse.com>
578
579 * i386-opc.tbl (and, or): Add Optimize to forms allowing two
580 register operands.
581 * i386-tbl.h: Re-generate.
582
79dec6b7
JB		 5832019-07-01 Jan Beulich <jbeulich@suse.com>
584
585 * i386-opc.tbl (C): New.
586 (paddb, paddw, paddd, paddq, paddsb, paddsw, paddusb, paddusw,
587 pand, pcmpeqb, pcmpeqw, pcmpeqd, pmaddwd, pmulhw, pmullw,
588 por, pxor, andps, cmpeqps, cmpeqss, cmpneqps, cmpneqss,
589 cmpordps, cmpordss, cmpunordps, cmpunordss, orps, pavgb, pavgw,
590 pmaxsw, pmaxub, pminsw, pminub, pmulhuw, xorps, andpd, cmpeqpd,
591 cmpeqsd, cmpneqpd, cmpneqsd, cmpordpd, cmpordsd, cmpunordpd,
592 cmpunordsd, orpd, xorpd, pmuludq, vandpd, vandps, vcmpeq_ospd,
593 vcmpeq_osps, vcmpeq_ossd, vcmpeq_osss, vcmpeqpd, vcmpeqps,
594 vcmpeqsd, vcmpeqss, vcmpeq_uqpd, vcmpeq_uqps, vcmpeq_uqsd,
595 vcmpeq_uqss, vcmpeq_uspd, vcmpeq_usps, vcmpeq_ussd,
596 vcmpeq_usss, vcmpfalse_ospd, vcmpfalse_osps, vcmpfalse_ossd,
597 vcmpfalse_osss, vcmpfalsepd, vcmpfalseps, vcmpfalsesd,
598 vcmpfalsess, vcmpneq_oqpd, vcmpneq_oqps, vcmpneq_oqsd,
599 vcmpneq_oqss, vcmpneq_ospd, vcmpneq_osps, vcmpneq_ossd,
600 vcmpneq_osss, vcmpneqpd, vcmpneqps, vcmpneqsd, vcmpneqss,
601 vcmpneq_uspd, vcmpneq_usps, vcmpneq_ussd, vcmpneq_usss,
602 vcmpordpd, vcmpordps, vcmpordsd, vcmpord_spd, vcmpord_sps,
603 vcmpordss, vcmpord_ssd, vcmpord_sss, vcmptruepd, vcmptrueps,
604 vcmptruesd, vcmptruess, vcmptrue_uspd, vcmptrue_usps,
605 vcmptrue_ussd, vcmptrue_usss, vcmpunordpd, vcmpunordps,
606 vcmpunordsd, vcmpunord_spd, vcmpunord_sps, vcmpunordss,
607 vcmpunord_ssd, vcmpunord_sss, vorpd, vorps, vpaddsb, vpaddsw,
608 vpaddb, vpaddd, vpaddq, vpaddw, vpaddusb, vpaddusw, vpand,
609 vpavgb, vpavgw, vpcmpeqb, vpcmpeqd, vpcmpeqw, vpmaddwd,
610 vpmaxsw, vpmaxub, vpminsw, vpminub, vpmulhuw, vpmulhw, vpmullw,
611 vpmuludq, vpor, vpxor, vxorpd, vxorps): Add C to VEX-encoded
612 flavors.
613 * i386-tbl.h: Re-generate.
614
a0a1771e
JB		 6152019-07-01 Jan Beulich <jbeulich@suse.com>
616
617 * i386-opc.tbl (and, or): Add Optimize to forms allowing two
618 register operands.
619 * i386-tbl.h: Re-generate.
620
cd546e7b
JB		 6212019-07-01 Jan Beulich <jbeulich@suse.com>
622
623 * i386-dis-evex-prefix.h: Use PCLMUL for vpclmulqdq.
624 * i386-opc.tbl (vpclmullqlqdq, vpclmulhqlqdq, vpclmullqhqdq,
625 vpclmulhqhqdq): Add CpuVPCLMULQDQ flavors.
626 * i386-tbl.h: Re-generate.
627
e3bba3fc
JB		 6282019-07-01 Jan Beulich <jbeulich@suse.com>
629
630 * i386-opc.tbl (vextractps, vpextrw, vpinsrw): Remove
631 Disp8MemShift from register only templates.
632 * i386-tbl.h: Re-generate.
633
36cc073e
JB		 6342019-07-01 Jan Beulich <jbeulich@suse.com>
635
636 * i386-dis.c (EXdScalarS, MOD_EVEX_0F10_PREFIX_1,
637 MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1,
638 MOD_EVEX_0F11_PREFIX_3, EVEX_W_0F10_P_1_M_0,
639 EVEX_W_0F10_P_1_M_1, EVEX_W_0F10_P_3_M_0, EVEX_W_0F10_P_3_M_1,
640 EVEX_W_0F11_P_1_M_0, EVEX_W_0F11_P_1_M_1, EVEX_W_0F11_P_3_M_0,
641 EVEX_W_0F11_P_3_M_1): Delete.
642 (EVEX_W_0F10_P_1, EVEX_W_0F10_P_3, EVEX_W_0F11_P_1,
643 EVEX_W_0F11_P_3): New.
644 * i386-dis-evex-mod.h: Remove MOD_EVEX_0F10_PREFIX_1,
645 MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1, and
646 MOD_EVEX_0F11_PREFIX_3 table entries.
647 * i386-dis-evex-prefix.h: Adjust PREFIX_EVEX_0F10 and
648 PREFIX_EVEX_0F11 table entries.
649 * i386-dis-evex-w.h: Replace EVEX_W_0F10_P_1_M_{0,1},
650 EVEX_W_0F10_P_3_M_{0,1}, EVEX_W_0F11_P_1_M_{0,1}, and
651 EVEX_W_0F11_P_3_M_{0,1} table entries.
652
219920a7
JB		 6532019-07-01 Jan Beulich <jbeulich@suse.com>
654
655 * i386-dis.c (EXdVex, EXdVexS, EXqVex, EXqVexS, XMVex):
656 Delete.
657
e395f487
L		 6582019-06-27 H.J. Lu <hongjiu.lu@intel.com>
659
660 PR binutils/24719
661 * i386-dis-evex-len.h: Add EVEX_LEN_0F38C6_REG_1_PREFIX_2,
662 EVEX_LEN_0F38C6_REG_2_PREFIX_2, EVEX_LEN_0F38C6_REG_5_PREFIX_2,
663 EVEX_LEN_0F38C6_REG_6_PREFIX_2, EVEX_LEN_0F38C7_R_1_P_2_W_0,
664 EVEX_LEN_0F38C7_R_1_P_2_W_1, EVEX_LEN_0F38C7_R_2_P_2_W_0,
665 EVEX_LEN_0F38C7_R_2_P_2_W_1, EVEX_LEN_0F38C7_R_5_P_2_W_0,
666 EVEX_LEN_0F38C7_R_5_P_2_W_1, EVEX_LEN_0F38C7_R_6_P_2_W_0 and
667 EVEX_LEN_0F38C7_R_6_P_2_W_1.
668 * i386-dis-evex-prefix.h: Update PREFIX_EVEX_0F38C6_REG_1,
669 PREFIX_EVEX_0F38C6_REG_2, PREFIX_EVEX_0F38C6_REG_5 and
670 PREFIX_EVEX_0F38C6_REG_6 entries.
671 * i386-dis-evex-w.h: Update EVEX_W_0F38C7_R_1_P_2,
672 EVEX_W_0F38C7_R_2_P_2, EVEX_W_0F38C7_R_5_P_2 and
673 EVEX_W_0F38C7_R_6_P_2 entries.
674 * i386-dis.c: Add EVEX_LEN_0F38C6_REG_1_PREFIX_2,
675 EVEX_LEN_0F38C6_REG_2_PREFIX_2, EVEX_LEN_0F38C6_REG_5_PREFIX_2,
676 EVEX_LEN_0F38C6_REG_6_PREFIX_2, EVEX_LEN_0F38C7_R_1_P_2_W_0,
677 EVEX_LEN_0F38C7_R_1_P_2_W_1, EVEX_LEN_0F38C7_R_2_P_2_W_0,
678 EVEX_LEN_0F38C7_R_2_P_2_W_1, EVEX_LEN_0F38C7_R_5_P_2_W_0,
679 EVEX_LEN_0F38C7_R_5_P_2_W_1, EVEX_LEN_0F38C7_R_6_P_2_W_0 and
680 EVEX_LEN_0F38C7_R_6_P_2_W_1 enums.
681
2b7bcc87
JB		 6822019-06-27 Jan Beulich <jbeulich@suse.com>
683
684 * i386-dis.c (VEX_LEN_0F2A_P_1, VEX_LEN_0F2A_P_3,
685 VEX_LEN_0F2C_P_1, VEX_LEN_0F2C_P_3, VEX_LEN_0F2D_P_1,
686 VEX_LEN_0F2D_P_3): Delete.
687 (vex_len_table): Move vcvtsi2ss, vcvtsi2sd, vcvttss2si,
688 vcvttsd2si, vcvtss2si, and vcvtsd2si leaf entries ...
689 (prefix_table): ... here.
690
c1dc7af5
JB		 6912019-06-27 Jan Beulich <jbeulich@suse.com>
692
693 * i386-dis.c (Iq): Delete.
694 (Id): New.
695 (reg_table): Use it for lwpins, lwpval, and bextr. Use Edq for
696 TBM insns.
697 (vex_len_table): Use Edq for vcvtsi2ss, vcvtsi2sd. Use Gdq for
698 vcvttss2si, vcvttsd2si, vcvtss2si, and vcvtsd2si.
699 (OP_E_memory): Also honor needindex when deciding whether an
700 address size prefix needs printing.
701 (OP_I): Remove handling of q_mode. Add handling of d_mode.
702
d7560e2d
JW		 7032019-06-26 Jim Wilson <jimw@sifive.com>
704
705 PR binutils/24739
706 * riscv-dis.c (riscv_disasemble_insn): Set info->endian_code.
707 Set info->display_endian to info->endian_code.
708
2c703856
JB		 7092019-06-25 Jan Beulich <jbeulich@suse.com>
710
711 * i386-gen.c (operand_type_init): Correct OPERAND_TYPE_DEBUG
712 entry. Drop OPERAND_TYPE_ACC entry. Add OPERAND_TYPE_ACC8 and
713 OPERAND_TYPE_ACC16 entries. Adjust OPERAND_TYPE_ACC32 and
714 OPERAND_TYPE_ACC64 entries.
715 * i386-init.h: Re-generate.
716
54fbadc0
JB		 7172019-06-25 Jan Beulich <jbeulich@suse.com>
718
719 * i386-dis.c (Edqa, dqa_mode, EVEX_W_0F2A_P_1, EVEX_W_0F7B_P_1):
720 Delete.
721 (intel_operand_size, OP_E_register, OP_E_memory): Drop handling
722 of dqa_mode.
723 * i386-dis-evex-prefix.h: Move vcvtsi2ss and vcvtusi2ss leaf
724 entries here.
725 * i386-dis-evex-w.h: Drop EVEX_W_0F2A_P_1 and EVEX_W_0F7B_P_1
726 entries. Use Edq for vcvtsi2sd and vcvtusi2sd.
727
a280ab8e
JB		 7282019-06-25 Jan Beulich <jbeulich@suse.com>
729
730 * i386-dis.c (OP_I64): Forword more cases to OP_I(). Drop local
731 variables.
732
e1a1babd
JB		 7332019-06-25 Jan Beulich <jbeulich@suse.com>
734
735 * i386-dis.c (prefix_table): Use Edq for cvtsi2ss and cvtsi2sd.
736 Use Gdq for cvttss2si, cvttsd2si, cvtss2si, and cvtsd2si, and
737 movnti.
d7560e2d 738 * i386-opc.tbl (movnti): Add IgnoreSize.
e1a1babd
JB		 739 * i386-tbl.h: Re-generate.
740
b8364fa7
JB		 7412019-06-25 Jan Beulich <jbeulich@suse.com>
742
743 * i386-opc.tbl (and): Mark Imm8S form for optimization.
744 * i386-tbl.h: Re-generate.
745
ad692897
L		 7462019-06-21 H.J. Lu <hongjiu.lu@intel.com>
747
748 * i386-dis-evex.h: Break into ...
749 * i386-dis-evex-len.h: New file.
750 * i386-dis-evex-mod.h: Likewise.
751 * i386-dis-evex-prefix.h: Likewise.
752 * i386-dis-evex-reg.h: Likewise.
753 * i386-dis-evex-w.h: Likewise.
754 * i386-dis.c: Include i386-dis-evex-reg.h, i386-dis-evex-prefix.h,
755 i386-dis-evex.h, i386-dis-evex-len.h, i386-dis-evex-w.h and
756 i386-dis-evex-mod.h.
757
f0a6222e
L		 7582019-06-19 H.J. Lu <hongjiu.lu@intel.com>
759
760 PR binutils/24700
761 * i386-dis-evex.h (evex_table): Update EVEX_W_0F3819_P_2,
762 EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2, EVEX_W_0F385A_P_2 and
763 EVEX_W_0F385B_P_2.
764 (evex_len_table): Add EVEX_LEN_0F3819_P_2_W_0,
765 EVEX_LEN_0F3819_P_2_W_1, EVEX_LEN_0F381A_P_2_W_0,
766 EVEX_LEN_0F381A_P_2_W_1, EVEX_LEN_0F381B_P_2_W_0,
767 EVEX_LEN_0F381B_P_2_W_1, EVEX_LEN_0F385A_P_2_W_0,
768 EVEX_LEN_0F385A_P_2_W_1, EVEX_LEN_0F385B_P_2_W_0 and
769 EVEX_LEN_0F385B_P_2_W_1.
770 * i386-dis.c (EVEX_LEN_0F3819_P_2_W_0): New enum.
771 (EVEX_LEN_0F3819_P_2_W_1): Likewise.
772 (EVEX_LEN_0F381A_P_2_W_0): Likewise.
773 (EVEX_LEN_0F381A_P_2_W_1): Likewise.
774 (EVEX_LEN_0F381B_P_2_W_0): Likewise.
775 (EVEX_LEN_0F381B_P_2_W_1): Likewise.
776 (EVEX_LEN_0F385A_P_2_W_0): Likewise.
777 (EVEX_LEN_0F385A_P_2_W_1): Likewise.
778 (EVEX_LEN_0F385B_P_2_W_0): Likewise.
779 (EVEX_LEN_0F385B_P_2_W_1): Likewise.
780
6e1c90b7
L		 7812019-06-17 H.J. Lu <hongjiu.lu@intel.com>
782
783 PR binutils/24691
784 * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A23_P_2,
785 EVEX_W_0F3A38_P_2, EVEX_W_0F3A39_P_2, EVEX_W_0F3A3A_P_2,
786 EVEX_W_0F3A3B_P_2 and EVEX_W_0F3A43_P_2.
787 (evex_len_table): Add EVEX_LEN_0F3A23_P_2_W_0,
788 EVEX_LEN_0F3A23_P_2_W_1, EVEX_LEN_0F3A38_P_2_W_0,
789 EVEX_LEN_0F3A38_P_2_W_1, EVEX_LEN_0F3A39_P_2_W_0,
790 EVEX_LEN_0F3A39_P_2_W_1, EVEX_LEN_0F3A3A_P_2_W_0,
791 EVEX_LEN_0F3A3A_P_2_W_1, EVEX_LEN_0F3A3B_P_2_W_0,
792 EVEX_LEN_0F3A3B_P_2_W_1, EVEX_LEN_0F3A43_P_2_W_0 and
793 EVEX_LEN_0F3A43_P_2_W_1.
794 * i386-dis.c (EVEX_LEN_0F3A23_P_2_W_0): New enum.
795 (EVEX_LEN_0F3A23_P_2_W_1): Likewise.
796 (EVEX_LEN_0F3A38_P_2_W_0): Likewise.
797 (EVEX_LEN_0F3A38_P_2_W_1): Likewise.
798 (EVEX_LEN_0F3A39_P_2_W_0): Likewise.
799 (EVEX_LEN_0F3A39_P_2_W_1): Likewise.
800 (EVEX_LEN_0F3A3A_P_2_W_0): Likewise.
801 (EVEX_LEN_0F3A3A_P_2_W_1): Likewise.
802 (EVEX_LEN_0F3A3B_P_2_W_0): Likewise.
803 (EVEX_LEN_0F3A3B_P_2_W_1): Likewise.
804 (EVEX_LEN_0F3A43_P_2_W_0): Likewise.
805 (EVEX_LEN_0F3A43_P_2_W_1): Likewise.
806
bcc5a6eb
NC		 8072019-06-14 Nick Clifton <nickc@redhat.com>
808
809 * po/fr.po; Updated French translation.
810
e4c4ac46
SH		 8112019-06-13 Stafford Horne <shorne@gmail.com>
812
813 * or1k-asm.c: Regenerated.
814 * or1k-desc.c: Regenerated.
815 * or1k-desc.h: Regenerated.
816 * or1k-dis.c: Regenerated.
817 * or1k-ibld.c: Regenerated.
818 * or1k-opc.c: Regenerated.
819 * or1k-opc.h: Regenerated.
820 * or1k-opinst.c: Regenerated.
821
a0e44ef5
PB		 8222019-06-12 Peter Bergner <bergner@linux.ibm.com>
823
824 * ppc-opc.c (powerpc_opcodes) <ldmx>: Delete mnemonic.
825
12efd68d
L		 8262019-06-05 H.J. Lu <hongjiu.lu@intel.com>
827
828 PR binutils/24633
829 * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A18_P_2,
830 EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2 and EVEX_W_0F3A1B_P_2.
831 (evex_len_table): EVEX_LEN_0F3A18_P_2_W_0,
832 EVEX_LEN_0F3A18_P_2_W_1, EVEX_LEN_0F3A19_P_2_W_0,
833 EVEX_LEN_0F3A19_P_2_W_1, EVEX_LEN_0F3A1A_P_2_W_0,
834 EVEX_LEN_0F3A1A_P_2_W_1, EVEX_LEN_0F3A1B_P_2_W_0,
835 EVEX_LEN_0F3A1B_P_2_W_1.
836 * i386-dis.c (EVEX_LEN_0F3A18_P_2_W_0): New enum.
837 (EVEX_LEN_0F3A18_P_2_W_1): Likewise.
838 (EVEX_LEN_0F3A19_P_2_W_0): Likewise.
839 (EVEX_LEN_0F3A19_P_2_W_1): Likewise.
840 (EVEX_LEN_0F3A1A_P_2_W_0): Likewise.
841 (EVEX_LEN_0F3A1A_P_2_W_1): Likewise.
842 (EVEX_LEN_0F3A1B_P_2_W_0): Likewise.
843 (EVEX_LEN_0F3A1B_P_2_W_1): Likewise.
844
63c6fc6c
L		 8452019-06-04 H.J. Lu <hongjiu.lu@intel.com>
846
847 PR binutils/24626
848 * i386-dis.c (print_insn): Check for unused VEX.vvvv and
849 EVEX.vvvv when disassembling VEX and EVEX instructions.
850 (OP_VEX): Set vex.register_specifier to 0 after readding
851 vex.register_specifier.
852 (OP_Vex_2src_1): Likewise.
853 (OP_Vex_2src_2): Likewise.
854 (OP_LWP_E): Likewise.
855 (OP_EX_Vex): Don't check vex.register_specifier.
856 (OP_XMM_Vex): Likewise.
857
9186c494
L		 8582019-06-04 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
859 Lili Cui <lili.cui@intel.com>
860
861 * i386-dis.c (enum): Add PREFIX_EVEX_0F3868, EVEX_W_0F3868_P_3.
862 * i386-dis-evex.h (evex_table): Add AVX512_VP2INTERSECT
863 instructions.
864 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VP2INTERSECT_FLAGS,
865 CPU_ANY_AVX512_VP2INTERSECT_FLAGS.
866 (cpu_flags): Add CpuAVX512_VP2INTERSECT.
867 * i386-opc.h (enum): Add CpuAVX512_VP2INTERSECT.
868 (i386_cpu_flags): Add cpuavx512_vp2intersect.
869 * i386-opc.tbl: Add AVX512_VP2INTERSECT insns.
870 * i386-init.h: Regenerated.
871 * i386-tbl.h: Likewise.
872
5d79adc4
L		 8732019-06-04 Xuepeng Guo <xuepeng.guo@intel.com>
874 Lili Cui <lili.cui@intel.com>
875
876 * doc/c-i386.texi: Document enqcmd.
877 * testsuite/gas/i386/enqcmd-intel.d: New file.
878 * testsuite/gas/i386/enqcmd-inval.l: Likewise.
879 * testsuite/gas/i386/enqcmd-inval.s: Likewise.
880 * testsuite/gas/i386/enqcmd.d: Likewise.
881 * testsuite/gas/i386/enqcmd.s: Likewise.
882 * testsuite/gas/i386/x86-64-enqcmd-intel.d: Likewise.
883 * testsuite/gas/i386/x86-64-enqcmd-inval.l: Likewise.
884 * testsuite/gas/i386/x86-64-enqcmd-inval.s: Likewise.
885 * testsuite/gas/i386/x86-64-enqcmd.d: Likewise.
886 * testsuite/gas/i386/x86-64-enqcmd.s: Likewise.
887 * testsuite/gas/i386/i386.exp: Run enqcmd-intel, enqcmd-inval,
888 enqcmd, x86-64-enqcmd-intel, x86-64-enqcmd-inval,
889 and x86-64-enqcmd.
890
a9d96ab9
AH		 8912019-06-04 Alan Hayward <alan.hayward@arm.com>
892
893 * arm-dis.c (is_mve_unpredictable): Remove spurious paranthesis.
894
4f6d070a
AM		 8952019-06-03 Alan Modra <amodra@gmail.com>
896
897 * ppc-dis.c (prefix_opcd_indices): Correct size.
898
a2f4b66c
L		 8992019-05-28 H.J. Lu <hongjiu.lu@intel.com>
900
901 PR gas/24625
902 * i386-opc.tbl: Add CheckRegSize to AVX512_BF16 instructions with
903 Disp8ShiftVL.
904 * i386-tbl.h: Regenerated.
905
405b5bd8
AM		 9062019-05-24 Alan Modra <amodra@gmail.com>
907
908 * po/POTFILES.in: Regenerate.
909
8acf1435
PB		 9102019-05-24 Peter Bergner <bergner@linux.ibm.com>
911 Alan Modra <amodra@gmail.com>
912
913 * ppc-opc.c (insert_d34, extract_d34, insert_nsi34, extract_nsi34),
914 (insert_pcrel, extract_pcrel, extract_pcrel0): New functions.
915 (extract_esync, extract_raq, extract_tbr, extract_sxl): Comment.
916 (powerpc_operands <D34, SI34, NSI34, PRA0, PRAQ, PCREL, PCREL0,
917 XTOP>): Define and add entries.
918 (P8LS, PMLS, P_D_MASK, P_DRAPCREL_MASK): Define.
919 (prefix_opcodes): Add pli, paddi, pla, psubi, plwz, plbz, pstw,
920 pstb, plhz, plha, psth, plfs, plfd, pstfs, pstfd, plq, plxsd,
921 plxssp, pld, plwa, pstxsd, pstxssp, pstxv, pstd, and pstq.
922
dd7efa79
PB		 9232019-05-24 Peter Bergner <bergner@linux.ibm.com>
924 Alan Modra <amodra@gmail.com>
925
926 * ppc-dis.c (ppc_opts): Add "future" entry.
927 (PREFIX_OPCD_SEGS): Define.
928 (prefix_opcd_indices): New array.
929 (disassemble_init_powerpc): Initialize prefix_opcd_indices.
930 (lookup_prefix): New function.
931 (print_insn_powerpc): Handle 64-bit prefix instructions.
932 * ppc-opc.c (PREFIX_OP, PREFIX_FORM, SUFFIX_MASK, PREFIX_MASK),
933 (PMRR, POWERXX): Define.
934 (prefix_opcodes): New instruction table.
935 (prefix_num_opcodes): New constant.
936
79472b45
JM		 9372019-05-23 Jose E. Marchesi <jose.marchesi@oracle.com>
938
939 * configure.ac (SHARED_DEPENDENCIES): Add case for bfd_bpf_arch.
940 * configure: Regenerated.
941 * Makefile.am: Add rules for the files generated from cpu/bpf.cpu
942 and cpu/bpf.opc.
943 (HFILES): Add bpf-desc.h and bpf-opc.h.
944 (TARGET_LIBOPCODES_CFILES): Add bpf-asm.c, bpf-desc.c, bpf-dis.c,
945 bpf-ibld.c and bpf-opc.c.
946 (BPF_DEPS): Define.
947 * Makefile.in: Regenerated.
948 * disassemble.c (ARCH_bpf): Define.
949 (disassembler): Add case for bfd_arch_bpf.
950 (disassemble_init_for_target): Likewise.
951 (enum epbf_isa_attr): Define.
952 * disassemble.h: extern print_insn_bpf.
953 * bpf-asm.c: Generated.
954 * bpf-opc.h: Likewise.
955 * bpf-opc.c: Likewise.
956 * bpf-ibld.c: Likewise.
957 * bpf-dis.c: Likewise.
958 * bpf-desc.h: Likewise.
959 * bpf-desc.c: Likewise.
960
ba6cd17f
SD		 9612019-05-21 Sudakshina Das <sudi.das@arm.com>
962
963 * arm-dis.c (coprocessor_opcodes): New instructions for VMRS
964 and VMSR with the new operands.
965
e39c1607
SD		 9662019-05-21 Sudakshina Das <sudi.das@arm.com>
967
968 * arm-dis.c (enum mve_instructions): New enum
969 for csinc, csinv, csneg, csel, cset, csetm, cinv, cinv
970 and cneg.
971 (mve_opcodes): New instructions as above.
972 (is_mve_encoding_conflict): Add cases for csinc, csinv,
973 csneg and csel.
974 (print_insn_mve): Accept new %<bitfield>c and %<bitfield>C.
975
23d00a41
SD		 9762019-05-21 Sudakshina Das <sudi.das@arm.com>
977
978 * arm-dis.c (emun mve_instructions): Updated for new instructions.
979 (mve_opcodes): New instructions for asrl, lsll, lsrl, sqrshrl,
980 sqrshr, sqshl, sqshll, srshr, srshrl, uqrshll, uqrshl, uqshll,
981 uqshl, urshrl and urshr.
982 (is_mve_okay_in_it): Add new instructions to TRUE list.
983 (is_mve_unpredictable): Add cases for UNPRED_R13 and UNPRED_R15.
984 (print_insn_mve): Updated to accept new %j,
985 %<bitfield>m and %<bitfield>n patterns.
986
cd4797ee
FS		 9872019-05-21 Faraz Shahbazker <fshahbazker@wavecomp.com>
988
989 * mips-opc.c (mips_builtin_opcodes): Change source register
990 constraint for DAUI.
991
999b073b
NC		 9922019-05-20 Nick Clifton <nickc@redhat.com>
993
994 * po/fr.po: Updated French translation.
995
14b456f2
AV		 9962019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
997 Michael Collison <michael.collison@arm.com>
998
999 * arm-dis.c (thumb32_opcodes): Add new instructions.
1000 (enum mve_instructions): Likewise.
1001 (enum mve_undefined): Add new reasons.
1002 (is_mve_encoding_conflict): Handle new instructions.
1003 (is_mve_undefined): Likewise.
1004 (is_mve_unpredictable): Likewise.
1005 (print_mve_undefined): Likewise.
1006 (print_mve_size): Likewise.
1007
f49bb598
AV		 10082019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1009 Michael Collison <michael.collison@arm.com>
1010
1011 * arm-dis.c (thumb32_opcodes): Add new instructions.
1012 (enum mve_instructions): Likewise.
1013 (is_mve_encoding_conflict): Handle new instructions.
1014 (is_mve_undefined): Likewise.
1015 (is_mve_unpredictable): Likewise.
1016 (print_mve_size): Likewise.
1017
56858bea
AV		 10182019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1019 Michael Collison <michael.collison@arm.com>
1020
1021 * arm-dis.c (thumb32_opcodes): Add new instructions.
1022 (enum mve_instructions): Likewise.
1023 (is_mve_encoding_conflict): Likewise.
1024 (is_mve_unpredictable): Likewise.
1025 (print_mve_size): Likewise.
1026
e523f101
AV		 10272019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1028 Michael Collison <michael.collison@arm.com>
1029
1030 * arm-dis.c (thumb32_opcodes): Add new instructions.
1031 (enum mve_instructions): Likewise.
1032 (is_mve_encoding_conflict): Handle new instructions.
1033 (is_mve_undefined): Likewise.
1034 (is_mve_unpredictable): Likewise.
1035 (print_mve_size): Likewise.
1036
66dcaa5d
AV		 10372019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1038 Michael Collison <michael.collison@arm.com>
1039
1040 * arm-dis.c (thumb32_opcodes): Add new instructions.
1041 (enum mve_instructions): Likewise.
1042 (is_mve_encoding_conflict): Handle new instructions.
1043 (is_mve_undefined): Likewise.
1044 (is_mve_unpredictable): Likewise.
1045 (print_mve_size): Likewise.
1046 (print_insn_mve): Likewise.
1047
d052b9b7
AV		 10482019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1049 Michael Collison <michael.collison@arm.com>
1050
1051 * arm-dis.c (thumb32_opcodes): Add new instructions.
1052 (print_insn_thumb32): Handle new instructions.
1053
ed63aa17
AV		 10542019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1055 Michael Collison <michael.collison@arm.com>
1056
1057 * arm-dis.c (enum mve_instructions): Add new instructions.
1058 (enum mve_undefined): Add new reasons.
1059 (is_mve_encoding_conflict): Handle new instructions.
1060 (is_mve_undefined): Likewise.
1061 (is_mve_unpredictable): Likewise.
1062 (print_mve_undefined): Likewise.
1063 (print_mve_size): Likewise.
1064 (print_mve_shift_n): Likewise.
1065 (print_insn_mve): Likewise.
1066
897b9bbc
AV		 10672019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1068 Michael Collison <michael.collison@arm.com>
1069
1070 * arm-dis.c (enum mve_instructions): Add new instructions.
1071 (is_mve_encoding_conflict): Handle new instructions.
1072 (is_mve_unpredictable): Likewise.
1073 (print_mve_rotate): Likewise.
1074 (print_mve_size): Likewise.
1075 (print_insn_mve): Likewise.
1076
1c8f2df8
AV		 10772019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1078 Michael Collison <michael.collison@arm.com>
1079
1080 * arm-dis.c (enum mve_instructions): Add new instructions.
1081 (is_mve_encoding_conflict): Handle new instructions.
1082 (is_mve_unpredictable): Likewise.
1083 (print_mve_size): Likewise.
1084 (print_insn_mve): Likewise.
1085
d3b63143
AV		 10862019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1087 Michael Collison <michael.collison@arm.com>
1088
1089 * arm-dis.c (enum mve_instructions): Add new instructions.
1090 (enum mve_undefined): Add new reasons.
1091 (is_mve_encoding_conflict): Handle new instructions.
1092 (is_mve_undefined): Likewise.
1093 (is_mve_unpredictable): Likewise.
1094 (print_mve_undefined): Likewise.
1095 (print_mve_size): Likewise.
1096 (print_insn_mve): Likewise.
1097
14925797
AV		 10982019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1099 Michael Collison <michael.collison@arm.com>
1100
1101 * arm-dis.c (enum mve_instructions): Add new instructions.
1102 (is_mve_encoding_conflict): Handle new instructions.
1103 (is_mve_undefined): Likewise.
1104 (is_mve_unpredictable): Likewise.
1105 (print_mve_size): Likewise.
1106 (print_insn_mve): Likewise.
1107
c507f10b
AV		 11082019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1109 Michael Collison <michael.collison@arm.com>
1110
1111 * arm-dis.c (enum mve_instructions): Add new instructions.
1112 (enum mve_unpredictable): Add new reasons.
1113 (enum mve_undefined): Likewise.
1114 (is_mve_okay_in_it): Handle new isntructions.
1115 (is_mve_encoding_conflict): Likewise.
1116 (is_mve_undefined): Likewise.
1117 (is_mve_unpredictable): Likewise.
1118 (print_mve_vmov_index): Likewise.
1119 (print_simd_imm8): Likewise.
1120 (print_mve_undefined): Likewise.
1121 (print_mve_unpredictable): Likewise.
1122 (print_mve_size): Likewise.
1123 (print_insn_mve): Likewise.
1124
bf0b396d
AV		 11252019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1126 Michael Collison <michael.collison@arm.com>
1127
1128 * arm-dis.c (enum mve_instructions): Add new instructions.
1129 (enum mve_unpredictable): Add new reasons.
1130 (enum mve_undefined): Likewise.
1131 (is_mve_encoding_conflict): Handle new instructions.
1132 (is_mve_undefined): Likewise.
1133 (is_mve_unpredictable): Likewise.
1134 (print_mve_undefined): Likewise.
1135 (print_mve_unpredictable): Likewise.
1136 (print_mve_rounding_mode): Likewise.
1137 (print_mve_vcvt_size): Likewise.
1138 (print_mve_size): Likewise.
1139 (print_insn_mve): Likewise.
1140
ef1576a1
AV		 11412019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1142 Michael Collison <michael.collison@arm.com>
1143
1144 * arm-dis.c (enum mve_instructions): Add new instructions.
1145 (enum mve_unpredictable): Add new reasons.
1146 (enum mve_undefined): Likewise.
1147 (is_mve_undefined): Handle new instructions.
1148 (is_mve_unpredictable): Likewise.
1149 (print_mve_undefined): Likewise.
1150 (print_mve_unpredictable): Likewise.
1151 (print_mve_size): Likewise.
1152 (print_insn_mve): Likewise.
1153
aef6d006
AV		 11542019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1155 Michael Collison <michael.collison@arm.com>
1156
1157 * arm-dis.c (enum mve_instructions): Add new instructions.
1158 (enum mve_undefined): Add new reasons.
1159 (insns): Add new instructions.
1160 (is_mve_encoding_conflict):
1161 (print_mve_vld_str_addr): New print function.
1162 (is_mve_undefined): Handle new instructions.
1163 (is_mve_unpredictable): Likewise.
1164 (print_mve_undefined): Likewise.
1165 (print_mve_size): Likewise.
1166 (print_insn_coprocessor_1): Handle MVE VLDR, VSTR instructions.
1167 (print_insn_mve): Handle new operands.
1168
04d54ace
AV		 11692019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1170 Michael Collison <michael.collison@arm.com>
1171
1172 * arm-dis.c (enum mve_instructions): Add new instructions.
1173 (enum mve_unpredictable): Add new reasons.
1174 (is_mve_encoding_conflict): Handle new instructions.
1175 (is_mve_unpredictable): Likewise.
1176 (mve_opcodes): Add new instructions.
1177 (print_mve_unpredictable): Handle new reasons.
1178 (print_mve_register_blocks): New print function.
1179 (print_mve_size): Handle new instructions.
1180 (print_insn_mve): Likewise.
1181
9743db03
AV		 11822019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1183 Michael Collison <michael.collison@arm.com>
1184
1185 * arm-dis.c (enum mve_instructions): Add new instructions.
1186 (enum mve_unpredictable): Add new reasons.
1187 (enum mve_undefined): Likewise.
1188 (is_mve_encoding_conflict): Handle new instructions.
1189 (is_mve_undefined): Likewise.
1190 (is_mve_unpredictable): Likewise.
1191 (coprocessor_opcodes): Move NEON VDUP from here...
1192 (neon_opcodes): ... to here.
1193 (mve_opcodes): Add new instructions.
1194 (print_mve_undefined): Handle new reasons.
1195 (print_mve_unpredictable): Likewise.
1196 (print_mve_size): Handle new instructions.
1197 (print_insn_neon): Handle vdup.
1198 (print_insn_mve): Handle new operands.
1199
143275ea
AV		 12002019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1201 Michael Collison <michael.collison@arm.com>
1202
1203 * arm-dis.c (enum mve_instructions): Add new instructions.
1204 (enum mve_unpredictable): Add new values.
1205 (mve_opcodes): Add new instructions.
1206 (vec_condnames): New array with vector conditions.
1207 (mve_predicatenames): New array with predicate suffixes.
1208 (mve_vec_sizename): New array with vector sizes.
1209 (enum vpt_pred_state): New enum with vector predication states.
1210 (struct vpt_block): New struct type for vpt blocks.
1211 (vpt_block_state): Global struct to keep track of state.
1212 (mve_extract_pred_mask): New helper function.
1213 (num_instructions_vpt_block): Likewise.
1214 (mark_outside_vpt_block): Likewise.
1215 (mark_inside_vpt_block): Likewise.
1216 (invert_next_predicate_state): Likewise.
1217 (update_next_predicate_state): Likewise.
1218 (update_vpt_block_state): Likewise.
1219 (is_vpt_instruction): Likewise.
1220 (is_mve_encoding_conflict): Add entries for new instructions.
1221 (is_mve_unpredictable): Likewise.
1222 (print_mve_unpredictable): Handle new cases.
1223 (print_instruction_predicate): Likewise.
1224 (print_mve_size): New function.
1225 (print_vec_condition): New function.
1226 (print_insn_mve): Handle vpt blocks and new print operands.
1227
f08d8ce3
AV		 12282019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1229
1230 * arm-dis.c (print_insn_coprocessor_1): Disable the use of coprocessors
1231 8, 14 and 15 for Armv8.1-M Mainline.
1232
73cd51e5
AV		 12332019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1234 Michael Collison <michael.collison@arm.com>
1235
1236 * arm-dis.c (enum mve_instructions): New enum.
1237 (enum mve_unpredictable): Likewise.
1238 (enum mve_undefined): Likewise.
1239 (struct mopcode32): New struct.
1240 (is_mve_okay_in_it): New function.
1241 (is_mve_architecture): Likewise.
1242 (arm_decode_field): Likewise.
1243 (arm_decode_field_multiple): Likewise.
1244 (is_mve_encoding_conflict): Likewise.
1245 (is_mve_undefined): Likewise.
1246 (is_mve_unpredictable): Likewise.
1247 (print_mve_undefined): Likewise.
1248 (print_mve_unpredictable): Likewise.
1249 (print_insn_coprocessor_1): Use arm_decode_field_multiple.
1250 (print_insn_mve): New function.
1251 (print_insn_thumb32): Handle MVE architecture.
1252 (select_arm_features): Force thumb for Armv8.1-m Mainline.
1253
3076e594
NC		 12542019-05-10 Nick Clifton <nickc@redhat.com>
1255
1256 PR 24538
1257 * ia64-opc.c (ia64_find_matching_opcode): Check for reaching the
1258 end of the table prematurely.
1259
387e7624
FS		 12602019-05-10 Faraz Shahbazker <fshahbazker@wavecomp.com>
1261
1262 * mips-opc.c (mips_opcodes): Enable ADD, SUB, DADD and DSUB
1263 macros for R6.
1264
0067be51
AM		 12652019-05-11 Alan Modra <amodra@gmail.com>
1266
1267 * ppc-dis.c (print_insn_powerpc) Don't skip optional operands
1268 when -Mraw is in effect.
1269
42e6288f
MM		 12702019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1271
1272 * aarch64-dis-2.c: Regenerate.
1273 * aarch64-tbl.h (OP_SVE_BBU): New variant set.
1274 (OP_SVE_BBB): New variant set.
1275 (OP_SVE_DDDD): New variant set.
1276 (OP_SVE_HHH): New variant set.
1277 (OP_SVE_HHHU): New variant set.
1278 (OP_SVE_SSS): New variant set.
1279 (OP_SVE_SSSU): New variant set.
1280 (OP_SVE_SHH): New variant set.
1281 (OP_SVE_SBBU): New variant set.
1282 (OP_SVE_DSS): New variant set.
1283 (OP_SVE_DHHU): New variant set.
1284 (OP_SVE_VMV_HSD_BHS): New variant set.
1285 (OP_SVE_VVU_HSD_BHS): New variant set.
1286 (OP_SVE_VVVU_SD_BH): New variant set.
1287 (OP_SVE_VVVU_BHSD): New variant set.
1288 (OP_SVE_VVV_QHD_DBS): New variant set.
1289 (OP_SVE_VVV_HSD_BHS): New variant set.
1290 (OP_SVE_VVV_HSD_BHS2): New variant set.
1291 (OP_SVE_VVV_BHS_HSD): New variant set.
1292 (OP_SVE_VV_BHS_HSD): New variant set.
1293 (OP_SVE_VVV_SD): New variant set.
1294 (OP_SVE_VVU_BHS_HSD): New variant set.
1295 (OP_SVE_VZVV_SD): New variant set.
1296 (OP_SVE_VZVV_BH): New variant set.
1297 (OP_SVE_VZV_SD): New variant set.
1298 (aarch64_opcode_table): Add sve2 instructions.
1299
28ed815a
MM		 13002019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1301
1302 * aarch64-asm-2.c: Regenerated.
1303 * aarch64-dis-2.c: Regenerated.
1304 * aarch64-opc-2.c: Regenerated.
1305 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1306 for SVE_SHLIMM_UNPRED_22.
1307 (aarch64_print_operand): Add printing for SVE_SHLIMM_UNPRED_22.
1308 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHLIMM_UNPRED_22
1309 operand.
1310
fd1dc4a0
MM		 13112019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1312
1313 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1314 sve_size_tsz_bhs iclass encode.
1315 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1316 sve_size_tsz_bhs iclass decode.
1317
31e36ab3
MM		 13182019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1319
1320 * aarch64-asm-2.c: Regenerated.
1321 * aarch64-dis-2.c: Regenerated.
1322 * aarch64-opc-2.c: Regenerated.
1323 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1324 for SVE_Zm4_11_INDEX.
1325 (aarch64_print_operand): Add printing for SVE_Zm4_11_INDEX.
1326 (fields): Handle SVE_i2h field.
1327 * aarch64-opc.h (enum aarch64_field_kind): New SVE_i2h field.
1328 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm4_11_INDEX operand.
1329
1be5f94f
MM		 13302019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1331
1332 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1333 sve_shift_tsz_bhsd iclass encode.
1334 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1335 sve_shift_tsz_bhsd iclass decode.
1336
3c17238b
MM		 13372019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1338
1339 * aarch64-asm-2.c: Regenerated.
1340 * aarch64-dis-2.c: Regenerated.
1341 * aarch64-opc-2.c: Regenerated.
1342 * aarch64-asm.c (aarch64_ins_sve_shrimm):
1343 (aarch64_encode_variant_using_iclass): Handle
1344 sve_shift_tsz_hsd iclass encode.
1345 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1346 sve_shift_tsz_hsd iclass decode.
1347 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1348 for SVE_SHRIMM_UNPRED_22.
1349 (aarch64_print_operand): Add printing for SVE_SHRIMM_UNPRED_22.
1350 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHRIMM_UNPRED_22
1351 operand.
1352
cd50a87a
MM		 13532019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1354
1355 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1356 sve_size_013 iclass encode.
1357 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1358 sve_size_013 iclass decode.
1359
3c705960
MM		 13602019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1361
1362 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1363 sve_size_bh iclass encode.
1364 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1365 sve_size_bh iclass decode.
1366
0a57e14f
MM		 13672019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1368
1369 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1370 sve_size_sd2 iclass encode.
1371 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1372 sve_size_sd2 iclass decode.
1373 * aarch64-opc.c (fields): Handle SVE_sz2 field.
1374 * aarch64-opc.h (enum aarch64_field_kind): New SVE_sz2 field.
1375
c469c864
MM		 13762019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1377
1378 * aarch64-asm-2.c: Regenerated.
1379 * aarch64-dis-2.c: Regenerated.
1380 * aarch64-opc-2.c: Regenerated.
1381 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1382 for SVE_ADDR_ZX.
1383 (aarch64_print_operand): Add printing for SVE_ADDR_ZX.
1384 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_ADDR_ZX operand.
1385
116adc27
MM		 13862019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1387
1388 * aarch64-asm-2.c: Regenerated.
1389 * aarch64-dis-2.c: Regenerated.
1390 * aarch64-opc-2.c: Regenerated.
1391 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1392 for SVE_Zm3_11_INDEX.
1393 (aarch64_print_operand): Add printing for SVE_Zm3_11_INDEX.
1394 (fields): Handle SVE_i3l and SVE_i3h2 fields.
1395 * aarch64-opc.h (enum aarch64_field_kind): New SVE_i3l and SVE_i3h2
1396 fields.
1397 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm3_11_INDEX operand.
1398
3bd82c86
MM		 13992019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1400
1401 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1402 sve_size_hsd2 iclass encode.
1403 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1404 sve_size_hsd2 iclass decode.
1405 * aarch64-opc.c (fields): Handle SVE_size field.
1406 * aarch64-opc.h (enum aarch64_field_kind): New SVE_size field.
1407
adccc507
MM		 14082019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1409
1410 * aarch64-asm-2.c: Regenerated.
1411 * aarch64-dis-2.c: Regenerated.
1412 * aarch64-opc-2.c: Regenerated.
1413 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1414 for SVE_IMM_ROT3.
1415 (aarch64_print_operand): Add printing for SVE_IMM_ROT3.
1416 (fields): Handle SVE_rot3 field.
1417 * aarch64-opc.h (enum aarch64_field_kind): New SVE_rot3 field.
1418 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_IMM_ROT3 operand.
1419
5cd99750
MM		 14202019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1421
1422 * aarch64-opc.c (verify_constraints): Check for movprfx for sve2
1423 instructions.
1424
7ce2460a
MM		 14252019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1426
1427 * aarch64-tbl.h
1428 (aarch64_feature_sve2, aarch64_feature_sve2aes,
1429 aarch64_feature_sve2sha3, aarch64_feature_sve2sm4,
1430 aarch64_feature_sve2bitperm): New feature sets.
1431 (SVE2, SVE2_AES, SVE2_SHA3, SVE2_SM4, SVE2_BITPERM): New macros
1432 for feature set addresses.
1433 (SVE2_INSN, SVE2_INSNC, SVE2AES_INSN, SVE2SHA3_INSN,
1434 SVE2SM4_INSN, SVE2SM4_INSNC, SVE2BITPERM_INSN): New macros.
1435
41cee089
FS		 14362019-05-06 Andrew Bennett <andrew.bennett@imgtec.com>
1437 Faraz Shahbazker <fshahbazker@wavecomp.com>
1438
1439 * mips-dis.c (mips_calculate_combination_ases): Add ISA
1440 argument and set ASE_EVA_R6 appropriately.
1441 (set_default_mips_dis_options): Pass ISA to above.
1442 (parse_mips_dis_option): Likewise.
1443 * mips-opc.c (EVAR6): New macro.
1444 (mips_builtin_opcodes): Add llwpe, scwpe.
1445
b83b4b13
SD		 14462019-05-01 Sudakshina Das <sudi.das@arm.com>
1447
1448 * aarch64-asm-2.c: Regenerated.
1449 * aarch64-dis-2.c: Regenerated.
1450 * aarch64-opc-2.c: Regenerated.
1451 * aarch64-opc.c (operand_general_constraint_met_p): Add case for
1452 AARCH64_OPND_TME_UIMM16.
1453 (aarch64_print_operand): Likewise.
1454 * aarch64-tbl.h (QL_IMM_NIL): New.
1455 (TME): New.
1456 (_TME_INSN): New.
1457 (struct aarch64_opcode): Add tstart, tcommit, ttest and tcancel.
1458
4a90ce95
JD		 14592019-04-29 John Darrington <john@darrington.wattle.id.au>
1460
1461 * s12z-opc.c (shift_discrim): Return OP_INVALID when reading fails.
1462
a45328b9
AB		 14632019-04-26 Andrew Bennett <andrew.bennett@imgtec.com>
1464 Faraz Shahbazker <fshahbazker@wavecomp.com>
1465
1466 * mips-opc.c (mips_builtin_opcodes): Add llwp, lldp, scwp, scdp.
1467
d10be0cb
JD		 14682019-04-24 John Darrington <john@darrington.wattle.id.au>
1469
1470 * s12z-opc.h: Add extern "C" bracketing to help
1471 users who wish to use this interface in c++ code.
1472
a679f24e
JD		 14732019-04-24 John Darrington <john@darrington.wattle.id.au>
1474
1475 * s12z-opc.c (bm_decode): Handle bit map operations with the
1476 "reserved0" mode.
1477
32c36c3c
AV		 14782019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
1479
1480 * arm-dis.c (coprocessor_opcodes): Document new %J and %K format
1481 specifier. Add entries for VLDR and VSTR of system registers.
1482 (print_insn_coprocessor): Forbid coprocessor numbers 8, 14 and 15 in
1483 coprocessor instructions on Armv8.1-M Mainline targets. Add handling
1484 of %J and %K format specifier.
1485
efd6b359
AV		 14862019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
1487
1488 * arm-dis.c (coprocessor_opcodes): Document new %C format control code.
1489 Add new entries for VSCCLRM instruction.
1490 (print_insn_coprocessor): Handle new %C format control code.
1491
6b0dd094
AV		 14922019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
1493
1494 * arm-dis.c (enum isa): New enum.
1495 (struct sopcode32): New structure.
1496 (coprocessor_opcodes): change type of entries to struct sopcode32 and
1497 set isa field of all current entries to ANY.
1498 (print_insn_coprocessor): Change type of insn to struct sopcode32.
1499 Only match an entry if its isa field allows the current mode.
1500
4b5a202f
AV		 15012019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
1502
1503 * arm-dis.c (thumb_opcodes): Document %n control code. Add entry for
1504 CLRM.
1505 (print_insn_thumb32): Add logic to print %n CLRM register list.
1506
60f993ce
AV		 15072019-04-15 Sudakshina Das <sudi.das@arm.com>
1508
1509 * arm-dis.c (print_insn_thumb32): Updated to accept new %P
1510 and %Q patterns.
1511
f6b2b12d
AV		 15122019-04-15 Sudakshina Das <sudi.das@arm.com>
1513
1514 * arm-dis.c (thumb32_opcodes): New instruction bfcsel.
1515 (print_insn_thumb32): Edit the switch case for %Z.
1516
1889da70
AV		 15172019-04-15 Sudakshina Das <sudi.das@arm.com>
1518
1519 * arm-dis.c (print_insn_thumb32): Updated to accept new %Z pattern.
1520
65d1bc05
AV		 15212019-04-15 Sudakshina Das <sudi.das@arm.com>
1522
1523 * arm-dis.c (thumb32_opcodes): New instruction bfl.
1524
1caf72a5
AV		 15252019-04-15 Sudakshina Das <sudi.das@arm.com>
1526
1527 * arm-dis.c (print_insn_thumb32): Updated to accept new %Y pattern.
1528
f1c7f421
AV		 15292019-04-15 Sudakshina Das <sudi.das@arm.com>
1530
1531 * arm-dis.c (print_insn_thumb32): Add '%<bitfield>S' to print an
1532 Arm register with r13 and r15 unpredictable.
1533 (thumb32_opcodes): New instructions for bfx and bflx.
1534
4389b29a
AV		 15352019-04-15 Sudakshina Das <sudi.das@arm.com>
1536
1537 * arm-dis.c (thumb32_opcodes): New instructions for bf.
1538
e5d6e09e
AV		 15392019-04-15 Sudakshina Das <sudi.das@arm.com>
1540
1541 * arm-dis.c (print_insn_thumb32): Updated to accept new %W pattern.
1542
e12437dc
AV		 15432019-04-15 Sudakshina Das <sudi.das@arm.com>
1544
1545 * arm-dis.c (print_insn_thumb32): Updated to accept new %G pattern.
1546
031254f2
AV		 15472019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
1548
1549 * arm-dis.c (select_arm_features): Add logic for Armv8.1-M Mainline.
1550
e5a557ac
JD		 15512019-04-12 John Darrington <john@darrington.wattle.id.au>
1552
1553 s12z-dis.c, s12z-opc.c, s12z-opc.h: Replace "operator" with
1554 "optr". ("operator" is a reserved word in c++).
1555
bd7ceb8d
SD		 15562019-04-11 Sudakshina Das <sudi.das@arm.com>
1557
1558 * aarch64-opc.c (aarch64_print_operand): Add case for
1559 AARCH64_OPND_Rt_SP.
1560 (verify_constraints): Likewise.
1561 * aarch64-tbl.h (QL_LDST_AT): Update to add SP qualifier.
1562 (struct aarch64_opcode): Update stg, stzg, st2g, stz2g instructions
1563 to accept Rt|SP as first operand.
1564 (AARCH64_OPERANDS): Add new Rt_SP.
1565 * aarch64-asm-2.c: Regenerated.
1566 * aarch64-dis-2.c: Regenerated.
1567 * aarch64-opc-2.c: Regenerated.
1568
e54010f1
SD		 15692019-04-11 Sudakshina Das <sudi.das@arm.com>
1570
1571 * aarch64-asm-2.c: Regenerated.
1572 * aarch64-dis-2.c: Likewise.
1573 * aarch64-opc-2.c: Likewise.
1574 * aarch64-tbl.h (aarch64_opcode): Add new ldgm and stgm.
1575
7e96e219
RS		 15762019-04-09 Robert Suchanek <robert.suchanek@mips.com>
1577
1578 * mips-opc.c (mips_builtin_opcodes): Add RDHWR rt rd sel.
1579
6f2791d5
L		 15802019-04-08 H.J. Lu <hongjiu.lu@intel.com>
1581
1582 * i386-opc.tbl: Consolidate AVX512 BF16 entries.
1583 * i386-init.h: Regenerated.
1584
e392bad3
AM		 15852019-04-07 Alan Modra <amodra@gmail.com>
1586
1587 * ppc-dis.c (print_insn_powerpc): Use a tiny state machine
1588 op_separator to control printing of spaces, comma and parens
1589 rather than need_comma, need_paren and spaces vars.
1590
dffaa15c
AM		 15912019-04-07 Alan Modra <amodra@gmail.com>
1592
1593 PR 24421
1594 * arm-dis.c (print_insn_coprocessor): Correct bracket placement.
1595 (print_insn_neon, print_insn_arm): Likewise.
1596
d6aab7a1
XG		 15972019-04-05 Xuepeng Guo <xuepeng.guo@intel.com>
1598
1599 * i386-dis-evex.h (evex_table): Updated to support BF16
1600 instructions.
1601 * i386-dis.c (enum): Add EVEX_W_0F3852_P_1, EVEX_W_0F3872_P_1
1602 and EVEX_W_0F3872_P_3.
1603 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_BF16_FLAGS.
1604 (cpu_flags): Add bitfield for CpuAVX512_BF16.
1605 * i386-opc.h (enum): Add CpuAVX512_BF16.
1606 (i386_cpu_flags): Add bitfield for cpuavx512_bf16.
1607 * i386-opc.tbl: Add AVX512 BF16 instructions.
1608 * i386-init.h: Regenerated.
1609 * i386-tbl.h: Likewise.
1610
66e85460
AM		 16112019-04-05 Alan Modra <amodra@gmail.com>
1612
1613 * ppc-opc.c (XLBH_MASK): Subtract off BH field from BB_MASK.
1614 (powerpc_opcodes): Reorder bcctr and bclr extended mnemonics
1615 to favour printing of "-" branch hint when using the "y" bit.
1616 Allow BH field on bc{ctr,lr,tar}{,l}{-,+}.
1617
c2b1c275
AM		 16182019-04-05 Alan Modra <amodra@gmail.com>
1619
1620 * ppc-dis.c (print_insn_powerpc): Delay printing spaces after
1621 opcode until first operand is output.
1622
aae9718e
PB		 16232019-04-04 Peter Bergner <bergner@linux.ibm.com>
1624
1625 PR gas/24349
1626 * ppc-opc.c (valid_bo_pre_v2): Add comments.
1627 (valid_bo_post_v2): Add support for 'at' branch hints.
1628 (insert_bo): Only error on branch on ctr.
1629 (get_bo_hint_mask): New function.
1630 (insert_boe): Add new 'branch_taken' formal argument. Add support
1631 for inserting 'at' branch hints.
1632 (extract_boe): Add new 'branch_taken' formal argument. Add support
1633 for extracting 'at' branch hints.
1634 (insert_bom, extract_bom, insert_bop, extract_bop): New functions.
1635 (BOE): Delete operand.
1636 (BOM, BOP): New operands.
1637 (RM): Update value.
1638 (XLYLK, XLYLK_MASK, XLYBB_MASK): Delete.
1639 (powerpc_opcodes) <bc-, bcl-, bca-, bcla-, bclr-, bclrl-, bcctr-,
1640 bcctrl-, bctar-, bctarl->: Replace BOE with BOM.
1641 (powerpc_opcodes) <bc+, bcl+, bca+, bcla+, bclr+, bclrl+, bcctr+,
1642 bcctrl+, bctar+, bctarl+>: Replace BOE with BOP.
1643 <bdnztar, bdnztarl, bdztar, bdztarl, btar, btarl, bdnztar-, bdnztarl-,
1644 bdnztar+, bdnztarl+, bdztar-, bdztarl-, bdztar+, bdztarl+, bgetar,
1645 bnltar, bgetarl, bnltarl, bletar, bngtar, bletarl, bngtarl, bnetar,
1646 bnetarl, bnstar, bnutar, bnstarl, bnutarl, bgetar-, bnltar-, bgetarl-,
1647 bnltarl-, bletar-, bngtar-, bletarl-, bngtarl-, bnetar-, bnetarl-,
1648 bnstar-, bnutar-, bnstarl-, bnutarl-, bgetar+, bnltar+, bgetarl+,
1649 bnltarl+, bletar+, bngtar+, bletarl+, bngtarl+, bnetar+, bnetarl+,
1650 bnstar+, bnutar+, bnstarl+, bnutarl+, blttar, blttarl, bgttar, bgttarl,
1651 beqtar, beqtarl, bsotar, buntar, bsotarl, buntarl, blttar-, blttarl-,
1652 bgttar-, bgttarl-, beqtar-, beqtarl-, bsotar-, buntar-, bsotarl-,
1653 buntarl-, blttar+, blttarl+, bgttar+, bgttarl+, beqtar+, beqtarl+,
1654 bsotar+, buntar+, bsotarl+, buntarl+, bdnzftar, bdnzftarl, bdzftar,
1655 bdzftarl, bftar, bftarl, bftar-, bftarl-, bftar+, bftarl+, bdnzttar,
1656 bdnzttarl, bdzttar, bdzttarl, bttar, bttarl, bttar-, bttarl-, bttar+,
1657 bttarl+>: New extended mnemonics.
1658
96a86c01
AM		 16592019-03-28 Alan Modra <amodra@gmail.com>
1660
1661 PR 24390
1662 * ppc-opc.c (BTF): Define.
1663 (powerpc_opcodes): Use for mtfsb*.
1664 * ppc-dis.c (print_insn_powerpc): Print fields with both
1665 PPC_OPERAND_CR_REG and PPC_OPERAND_CR_BIT as a plain number.
1666
796d6298
TC		 16672019-03-25 Tamar Christina <tamar.christina@arm.com>
1668
1669 * arm-dis.c (struct arm_private_data): Remove has_mapping_symbols.
1670 (mapping_symbol_for_insn): Implement new algorithm.
1671 (print_insn): Remove duplicate code.
1672
60df3720
TC		 16732019-03-25 Tamar Christina <tamar.christina@arm.com>
1674
1675 * aarch64-dis.c (print_insn_aarch64):
1676 Implement override.
1677
51457761
TC		 16782019-03-25 Tamar Christina <tamar.christina@arm.com>
1679
1680 * aarch64-dis.c (print_insn_aarch64): Update the mapping symbol search
1681 order.
1682
53b2f36b
TC		 16832019-03-25 Tamar Christina <tamar.christina@arm.com>
1684
1685 * aarch64-dis.c (last_stop_offset): New.
1686 (print_insn_aarch64): Use stop_offset.
1687
89199bb5
L		 16882019-03-19 H.J. Lu <hongjiu.lu@intel.com>
1689
1690 PR gas/24359
1691 * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS to
1692 CPU_ANY_AVX2_FLAGS.
1693 * i386-init.h: Regenerated.
1694
97ed31ae
L		 16952019-03-18 H.J. Lu <hongjiu.lu@intel.com>
1696
1697 PR gas/24348
1698 * i386-opc.tbl: Add Optimize to vmovdqa32, vmovdqa64, vmovdqu8,
1699 vmovdqu16, vmovdqu32 and vmovdqu64.
1700 * i386-tbl.h: Regenerated.
1701
0919bfe9
AK		 17022019-03-12 Andreas Krebbel <krebbel@linux.ibm.com>
1703
1704 * s390-opc.txt: Rename selhhhr to selfhr. Remove optional operand
1705 from vstrszb, vstrszh, and vstrszf.
1706
17072019-03-12 Andreas Krebbel <krebbel@linux.ibm.com>
1708
1709 * s390-opc.txt: Add instruction descriptions.
1710
21820ebe
JW		 17112019-02-08 Jim Wilson <jimw@sifive.com>
1712
1713 * riscv-opc.c (riscv_opcodes) <beq>: Use Cz to compress 3 operand form.
1714 <bne>: Likewise.
1715
f7dd2fb2
TC		 17162019-02-07 Tamar Christina <tamar.christina@arm.com>
1717
1718 * arm-dis.c (arm_opcodes): Redefine hlt to armv1.
1719
6456d318
TC		 17202019-02-07 Tamar Christina <tamar.christina@arm.com>
1721
1722 PR binutils/23212
1723 * aarch64-opc.h (enum aarch64_field_kind): Add FLD_sz.
1724 * aarch64-opc.c (verify_elem_sd): New.
1725 (fields): Add FLD_sz entr.
1726 * aarch64-tbl.h (_SIMD_INSN): New.
1727 (aarch64_opcode_table): Add elem_sd verifier to fmla, fmls, fmul and
1728 fmulx scalar and vector by element isns.
1729
4a83b610
NC		 17302019-02-07 Nick Clifton <nickc@redhat.com>
1731
1732 * po/sv.po: Updated Swedish translation.
1733
fc60b8c8
AK		 17342019-01-31 Andreas Krebbel <krebbel@linux.ibm.com>
1735
1736 * s390-mkopc.c (main): Accept arch13 as cpu string.
1737 * s390-opc.c: Add new instruction formats and instruction opcode
1738 masks.
1739 * s390-opc.txt: Add new arch13 instructions.
1740
e10620d3
TC		 17412019-01-25 Sudakshina Das <sudi.das@arm.com>
1742
1743 * aarch64-tbl.h (QL_LDST_AT): Update macro.
1744 (aarch64_opcode): Change encoding for stg, stzg
1745 st2g and st2zg.
1746 * aarch64-asm-2.c: Regenerated.
1747 * aarch64-dis-2.c: Regenerated.
1748 * aarch64-opc-2.c: Regenerated.
1749
20a4ca55
SD		 17502019-01-25 Sudakshina Das <sudi.das@arm.com>
1751
1752 * aarch64-asm-2.c: Regenerated.
1753 * aarch64-dis-2.c: Likewise.
1754 * aarch64-opc-2.c: Likewise.
1755 * aarch64-tbl.h (aarch64_opcode): Add new stzgm.
1756
550fd7bf
SD		 17572019-01-25 Sudakshina Das <sudi.das@arm.com>
1758 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
1759
1760 * aarch64-asm.c (aarch64_ins_addr_simple_2): Remove.
1761 * aarch64-asm.h (ins_addr_simple_2): Likeiwse.
1762 * aarch64-dis.c (aarch64_ext_addr_simple_2): Likewise.
1763 * aarch64-dis.h (ext_addr_simple_2): Likewise.
1764 * aarch64-opc.c (operand_general_constraint_met_p): Remove
1765 case for ldstgv_indexed.
1766 (aarch64_print_operand): Remove case for AARCH64_OPND_ADDR_SIMPLE_2.
1767 * aarch64-tbl.h (struct aarch64_opcode): Remove ldgv and stgv.
1768 (AARCH64_OPERANDS): Remove ADDR_SIMPLE_2.
1769 * aarch64-asm-2.c: Regenerated.
1770 * aarch64-dis-2.c: Regenerated.
1771 * aarch64-opc-2.c: Regenerated.
1772
d9938630
NC		 17732019-01-23 Nick Clifton <nickc@redhat.com>
1774
1775 * po/pt_BR.po: Updated Brazilian Portuguese translation.
1776
375cd423
NC		 17772019-01-21 Nick Clifton <nickc@redhat.com>
1778
1779 * po/de.po: Updated German translation.
1780 * po/uk.po: Updated Ukranian translation.
1781
57299f48
CX		 17822019-01-20 Chenghua Xu <paul.hua.gm@gmail.com>
1783 * mips-dis.c (mips_arch_choices): Fix typo in
1784 gs464, gs464e and gs264e descriptors.
1785
f48dfe41
NC		 17862019-01-19 Nick Clifton <nickc@redhat.com>
1787
1788 * configure: Regenerate.
1789 * po/opcodes.pot: Regenerate.
1790
f974f26c
NC		 17912018-06-24 Nick Clifton <nickc@redhat.com>
1792
1793 2.32 branch created.
1794
39f286cd
JD		 17952019-01-09 John Darrington <john@darrington.wattle.id.au>
1796
448b8ca8
JD		 1797 * s12z-dis.c (print_insn_s12z): Do not dereference an operand
1798 if it is null.
1799 -dis.c (opr_emit_disassembly): Do not omit an index if it is
39f286cd
JD		 1800 zero.
1801
3107326d
AP		 18022019-01-09 Andrew Paprocki <andrew@ishiboo.com>
1803
1804 * configure: Regenerate.
1805
7e9ca91e
AM		 18062019-01-07 Alan Modra <amodra@gmail.com>
1807
1808 * configure: Regenerate.
1809 * po/POTFILES.in: Regenerate.
1810
ef1ad42b
JD		 18112019-01-03 John Darrington <john@darrington.wattle.id.au>
1812
1813 * s12z-opc.c: New file.
1814 * s12z-opc.h: New file.
1815 * s12z-dis.c: Removed all code not directly related to display
1816 of instructions. Used the interface provided by the new files
1817 instead.
1818 * Makefile.am (TARGET_LIBOPCODES_CFILES) Add s12z-opc.c.
7e9ca91e 1819 * Makefile.in: Regenerate.
ef1ad42b 1820 * configure.ac (bfd_s12z_arch): Correct the dependencies.
7e9ca91e 1821 * configure: Regenerate.
ef1ad42b 1822
82704155
AM		 18232019-01-01 Alan Modra <amodra@gmail.com>
1824
1825 Update year range in copyright notice of all files.
1826
d5c04e1b 1827For older changes see ChangeLog-2018
3499769a 1828\f
d5c04e1b 1829Copyright (C) 2019 Free Software Foundation, Inc.
3499769a
AM		 1830
1831Copying and distribution of this file, with or without modification,
1832are permitted in any medium without royalty provided the copyright
1833notice and this notice are preserved.
1834
1835Local Variables:
1836mode: change-log
1837left-margin: 8
1838fill-column: 74
1839version-control: never
1840End:
GDB Binutils - Deliverables
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