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ubsan: nios2: left shift cannot be represented in type 'int'
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
8a92faab
AM		 12019-12-16 Alan Modra <amodra@gmail.com>
2
3 * nios2-dis.c (nios2_print_insn_arg): Avoid signed overflow
4
e6ced26a
AM		 52019-12-16 Alan Modra <amodra@gmail.com>
6
7 * xstormy16-ibld.c: Regenerate.
8
84e098cd
AM		 92019-12-16 Alan Modra <amodra@gmail.com>
10
11 * score-dis.c (print_insn_score16): Move rpush/rpop imm field
12 value adjustment so that it doesn't affect reg field too.
13
36bd8ea7
AM		 142019-12-16 Alan Modra <amodra@gmail.com>
15
16 * crx-dis.c (EXTRACT, SBM): Avoid signed overflow.
17 (get_number_of_operands, getargtype, getbits, getregname),
18 (getcopregname, getprocregname, gettrapstring, getcinvstring),
19 (getregliststring, get_word_at_PC, get_words_at_PC, build_mask),
20 (powerof2, match_opcode, make_instruction, print_arguments),
21 (print_arg): Delete forward declarations, moving static to..
22 (getregname, getcopregname, getregliststring): ..these definitions.
23 (build_mask): Return unsigned int mask.
24 (match_opcode): Use unsigned int vars.
25
cedfc774
AM		 262019-12-16 Alan Modra <amodra@gmail.com>
27
28 * bfin-dis.c (fmtconst, fmtconst_val): Avoid signed overflow.
29
4bdb25fe
AM		 302019-12-16 Alan Modra <amodra@gmail.com>
31
32 * nds32-dis.c (print_insn16, print_insn32): Remove forward decls.
33 (struct objdump_disasm_info): Delete.
34 (nds32_parse_audio_ext, nds32_parse_opcode): Cast result of
35 N32_IMMS to unsigned before shifting left.
36
cf950fd4
AM		 372019-12-16 Alan Modra <amodra@gmail.com>
38
39 * moxie-dis.c (INST2OFFSET): Don't left shift a signed value.
40 (print_insn_moxie): Remove unnecessary cast.
41
967354c3
AM		 422019-12-12 Alan Modra <amodra@gmail.com>
43
44 * csky-dis.c (csky_chars_to_number): Remove abort and unnecessary
45 mask.
46
1d61b032
AM		 472019-12-11 Alan Modra <amodra@gmail.com>
48
49 * arc-dis.c (BITS): Don't truncate high bits with shifts.
50 * nios2-dis.c (nios2_print_insn_arg): Don't sign extend with shifts.
51 * tic54x-dis.c (print_instruction): Likewise.
52 * tilegx-opc.c (parse_insn_tilegx): Likewise.
53 * tilepro-opc.c (parse_insn_tilepro): Likewise.
54 * visium-dis.c (disassem_class0): Likewise.
55 * pdp11-dis.c (sign_extend): Likewise.
56 (SIGN_BITS): Delete.
57 * epiphany-ibld.c: Regenerate.
58 * lm32-ibld.c: Regenerate.
59 * m32c-ibld.c: Regenerate.
60
5afa80e9
AM		 612019-12-11 Alan Modra <amodra@gmail.com>
62
63 * ns32k-dis.c (sign_extend): Correct last patch.
64
5c05618a
AM		 652019-12-11 Alan Modra <amodra@gmail.com>
66
67 * vax-dis.c (NEXTLONG): Avoid signed overflow.
68
2a81ccbb
AM		 692019-12-11 Alan Modra <amodra@gmail.com>
70
71 * v850-dis.c (get_operand_value): Use unsigned arithmetic. Don't
72 sign extend using shifts.
73
b84f6152
AM		 742019-12-11 Alan Modra <amodra@gmail.com>
75
76 * tic6x-dis.c (tic6x_extract_32): Avoid signed overflow.
77
66152f16
AM		 782019-12-11 Alan Modra <amodra@gmail.com>
79
80 * tic4x-dis.c (tic4x_print_register): Formatting. Don't segfault
81 on NULL registertable entry.
82 (tic4x_hash_opcode): Use unsigned arithmetic.
83
205c426a
AM		 842019-12-11 Alan Modra <amodra@gmail.com>
85
86 * s12z-opc.c (z_decode_signed_value): Avoid signed overflow.
87
fb4cb4e2
AM		 882019-12-11 Alan Modra <amodra@gmail.com>
89
90 * ns32k-dis.c (bit_extract): Use unsigned arithmetic.
91 (bit_extract_simple, sign_extend): Likewise.
92
96f1f604
AM		 932019-12-11 Alan Modra <amodra@gmail.com>
94
95 * nios2-dis.c (nios2_print_insn_arg): Use 1u << 31.
96
8c9b4171
AM		 972019-12-11 Alan Modra <amodra@gmail.com>
98
99 * moxie-dis.c (INST2OFFSET): Don't sign extend using shifts.
100
334175b6
AM		 1012019-12-11 Alan Modra <amodra@gmail.com>
102
103 * m68k-dis.c (COERCE32): Cast value first.
104 (NEXTLONG, NEXTULONG): Avoid signed overflow.
105
f8a87c78
AM		 1062019-12-11 Alan Modra <amodra@gmail.com>
107
108 * h8300-dis.c (extract_immediate): Avoid signed overflow.
109 (bfd_h8_disassemble): Likewise.
110
159653d8
AM		 1112019-12-11 Alan Modra <amodra@gmail.com>
112
113 * d30v-dis.c (print_insn): Make opind unsigned. Don't access
114 past end of operands array.
115
d93bba9e
AM		 1162019-12-11 Alan Modra <amodra@gmail.com>
117
118 * csky-dis.c (csky_chars_to_number): Rewrite. Avoid signed
119 overflow when collecting bytes of a number.
120
c202f69e
AM		 1212019-12-11 Alan Modra <amodra@gmail.com>
122
123 * cris-dis.c (print_with_operands): Avoid signed integer
124 overflow when collecting bytes of a 32-bit integer.
125
0ef562a4
AM		 1262019-12-11 Alan Modra <amodra@gmail.com>
127
128 * cr16-dis.c (EXTRACT, SBM): Rewrite.
129 (cr16_match_opcode): Delete duplicate bcond test.
130
2fd2b153
AM		 1312019-12-11 Alan Modra <amodra@gmail.com>
132
133 * bfin-dis.c (HOST_LONG_WORD_SIZE, XFIELD): Delete.
134 (SIGNBIT): New.
135 (MASKBITS, SIGNEXTEND): Rewrite.
136 (fmtconst): Don't use ? expression now that SIGNEXTEND uses
137 unsigned arithmetic, instead assign result of SIGNEXTEND back
138 to x.
139 (fmtconst_val): Use 1u in shift expression.
140
a11db3e9
AM		 1412019-12-11 Alan Modra <amodra@gmail.com>
142
143 * arc-dis.c (find_format_from_table): Use ull constant when
144 shifting by up to 32.
145
9d48687b
AM		 1462019-12-11 Alan Modra <amodra@gmail.com>
147
148 PR 25270
149 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Return
150 false when field is zero for sve_size_tsz_bhs.
151
b8e61daa
AM		 1522019-12-11 Alan Modra <amodra@gmail.com>
153
154 * epiphany-ibld.c: Regenerate.
155
20135676
AM		 1562019-12-10 Alan Modra <amodra@gmail.com>
157
158 PR 24960
159 * disassemble.c (disassemble_free_target): New function.
160
103ebbc3
AM		 1612019-12-10 Alan Modra <amodra@gmail.com>
162
163 * cgen-dis.in (print_insn_@arch@): Replace insn_sets with private_data.
164 * disassemble.c (disassemble_init_for_target): Likewise.
165 * bpf-dis.c: Regenerate.
166 * epiphany-dis.c: Regenerate.
167 * fr30-dis.c: Regenerate.
168 * frv-dis.c: Regenerate.
169 * ip2k-dis.c: Regenerate.
170 * iq2000-dis.c: Regenerate.
171 * lm32-dis.c: Regenerate.
172 * m32c-dis.c: Regenerate.
173 * m32r-dis.c: Regenerate.
174 * mep-dis.c: Regenerate.
175 * mt-dis.c: Regenerate.
176 * or1k-dis.c: Regenerate.
177 * xc16x-dis.c: Regenerate.
178 * xstormy16-dis.c: Regenerate.
179
6f0e0752
AM		 1802019-12-10 Alan Modra <amodra@gmail.com>
181
182 * ppc-dis.c (private): Delete variable.
183 (get_powerpc_dialect): Don't segfault on NULL info->private_data.
184 (powerpc_init_dialect): Don't use global private.
185
e7c22a69
AM		 1862019-12-10 Alan Modra <amodra@gmail.com>
187
188 * s12z-opc.c: Formatting.
189
0a6aef6b
AM		 1902019-12-08 Alan Modra <amodra@gmail.com>
191
192 * s12z-opc.c (exg_sex_discrim): Don't leak memory on invalid
193 registers.
194
2dc4b12f
JB		 1952019-12-05 Jan Beulich <jbeulich@suse.com>
196
197 * aarch64-tbl.h (aarch64_feature_crypto,
198 aarch64_feature_crypto_v8_2, CRYPTO, CRYPTO_V8_2, CRYP_INSN,
199 CRYPTO_V8_2_INSN): Delete.
200
378fd436
AM		 2012019-12-05 Alan Modra <amodra@gmail.com>
202
203 PR 25249
204 * microblaze-dis.c (NUM_STRBUFS, STRBUF_SIZE): Define.
205 (struct string_buf): New.
206 (strbuf): New function.
207 (get_field): Use strbuf rather than strdup of local temp.
208 (get_field_imm, get_field_imm5, get_field_imm5_mbar): Likewise.
209 (get_field_rfsl, get_field_imm15): Likewise.
210 (get_field_rd, get_field_r1, get_field_r2): Update macros.
211 (get_field_special): Likewise. Don't strcpy spr. Formatting.
212 (print_insn_microblaze): Formatting. Init and pass string_buf to
213 get_field functions.
214
0ba59a29
JB		 2152019-12-04 Jan Beulich <jbeulich@suse.com>
216
217 * i386-opc.tbl (lfs, lgs, lss): Drop No_qSuf.
218 * i386-tbl.h: Re-generate.
219
77ad8092
JB		 2202019-12-04 Jan Beulich <jbeulich@suse.com>
221
222 * i386-dis.c (mod_table): Use Ev instead of Em for movdiri.
223
3036c899
JB		 2242019-12-04 Jan Beulich <jbeulich@suse.com>
225
226 * i386-opc.tbl (push, pop): Drop DefaultSize from GPR-only
227 forms.
228 (xbegin): Drop DefaultSize.
229 * i386-tbl.h: Re-generate.
230
8b301fbb
MI		 2312019-11-22 Mihail Ionescu <mihail.ionescu@arm.com>
232
233 * opcodes/arm-dis.c (arm_opcodes, thumb32_opcodes):
234 Change the coproc CRC conditions to use the extension
235 feature set, second word, base on ARM_EXT2_CRC.
236
6aa385b9
JB		 2372019-11-14 Jan Beulich <jbeulich@suse.com>
238
239 * i386-opc.tbl (syscall, sysret): Drop Cpu64 forms.
240 * i386-tbl.h: Re-generate.
241
0cfa3eb3
JB		 2422019-11-14 Jan Beulich <jbeulich@suse.com>
243
244 * i386-gen.c (opcode_modifiers): Remove JumpDword, JumpByte,
245 JumpInterSegment, and JumpAbsolute entries.
246 * i386-opc.h (JUMP, JUMP_DWORD, JUMP_BYTE, JUMP_INTERSEGMENT,
247 JUMP_ABSOLUTE): Define.
248 (struct i386_opcode_modifier): Extend jump field to 3 bits.
249 Remove jumpdword, jumpbyte, jumpintersegment, and jumpabsolute
250 fields.
251 * i386-opc.tbl (JumpByte, JumpDword, JumpAbsolute,
252 JumpInterSegment): Define.
253 * i386-tbl.h: Re-generate.
254
6f2f06be
JB		 2552019-11-14 Jan Beulich <jbeulich@suse.com>
256
257 * i386-gen.c (operand_type_init): Remove
258 OPERAND_TYPE_JUMPABSOLUTE entry.
259 (opcode_modifiers): Add JumpAbsolute entry.
260 (operand_types): Remove JumpAbsolute entry.
261 * i386-opc.h (JumpAbsolute): Move between enums.
262 (struct i386_opcode_modifier): Add jumpabsolute field.
263 (union i386_operand_type): Remove jumpabsolute field.
264 * i386-opc.tbl (call, lcall, jmp, ljmp): Move JumpAbsolute.
265 * i386-init.h, i386-tbl.h: Re-generate.
266
601e8564
JB		 2672019-11-14 Jan Beulich <jbeulich@suse.com>
268
269 * i386-gen.c (opcode_modifiers): Add AnySize entry.
270 (operand_types): Remove AnySize entry.
271 * i386-opc.h (AnySize): Move between enums.
272 (struct i386_opcode_modifier): Add anysize field.
273 (OTUnused): Un-comment.
274 (union i386_operand_type): Remove anysize field.
275 * i386-opc.tbl (lea, invlpg, clflush, prefetchnta, prefetcht0,
276 prefetcht1, prefetcht2, prefetchtw, bndmk, bndcl, bndcu, bndcn,
277 bndstx, bndldx, prefetchwt1, clflushopt, clwb, cldemote): Move
278 AnySize.
279 * i386-tbl.h: Re-generate.
280
7722d40a
JW		 2812019-11-12 Nelson Chu <nelson.chu@sifive.com>
282
283 * riscv-opc.c (riscv_insn_types): Replace the INSN_CLASS_I with
284 INSN_CLASS_F and the INSN_CLASS_C with INSN_CLASS_F_AND_C if we
285 use the floating point register (FPR).
286
ce760a76
MI		 2872019-11-12 Mihail Ionescu <mihail.ionescu@arm.com>
288
289 * opcodes/arm-dis.c (mve_opcodes): Enable VMOV imm to vec with
290 cmode 1101.
291 (is_mve_encoding_conflict): Update cmode conflict checks for
292 MVE_VMVN_IMM.
293
51c8edf6
JB		 2942019-11-12 Jan Beulich <jbeulich@suse.com>
295
296 * i386-gen.c (operand_type_init): Remove OPERAND_TYPE_ESSEG
297 entry.
298 (operand_types): Remove EsSeg entry.
299 (main): Replace stale use of OTMax.
300 * i386-opc.h (IS_STRING_ES_OP0, IS_STRING_ES_OP1): Define.
301 (struct i386_opcode_modifier): Expand isstring field to 2 bits.
302 (EsSeg): Delete.
303 (OTUnused): Comment out.
304 (union i386_operand_type): Remove esseg field.
305 * i386-opc.tbl (IsStringEsOp0, IsStringEsOp1): Define.
306 (cmps, scmp, scas, ssca, cmpsd): Add IsStringEsOp0.
307 (ins, movs, smov, movsd): Add IsStringEsOpOp1.
308 (stos, ssto): Add IsStringEsOp0/IsStringEsOpOp1.
309 * i386-init.h, i386-tbl.h: Re-generate.
310
474da251
JB		 3112019-11-12 Jan Beulich <jbeulich@suse.com>
312
313 * i386-gen.c (operand_instances): Add RegB entry.
314 * i386-opc.h (enum operand_instance): Add RegB.
315 * i386-opc.tbl (RegC, RegD, RegB): Define.
316 (Acc, ShiftCount, InOutPortReg): Adjust definitions.
317 (monitor, mwait, invlpga, skinit, vmload, vmrun, vmsave, clzero,
318 monitorx, mwaitx): Drop ImmExt and convert encodings
319 accordingly.
320 * i386-reg.tbl (ecx, rcx): Add Instance=RegC.
321 (edx, rdx): Add Instance=RegD.
322 (ebx, rbx): Add Instance=RegB.
323 * i386-tbl.h: Re-generate.
324
75e5731b
JB		 3252019-11-12 Jan Beulich <jbeulich@suse.com>
326
327 * i386-gen.c (operand_type_init): Adjust
328 OPERAND_TYPE_INOUTPORTREG, OPERAND_TYPE_SHIFTCOUNT,
329 OPERAND_TYPE_FLOATACC, OPERAND_TYPE_ACC8, OPERAND_TYPE_ACC16,
330 OPERAND_TYPE_ACC32, and OPERAND_TYPE_ACC64 entries.
331 (operand_instances): New.
332 (operand_types): Drop InOutPortReg, ShiftCount, and Acc entries.
333 (output_operand_type): New parameter "instance". Process it.
334 (process_i386_operand_type): New local variable "instance".
335 (main): Adjust static assertions.
336 * i386-opc.h (INSTANCE_WIDTH): Define.
337 (enum operand_instance): New.
338 (Acc, InOutPortReg, ShiftCount): Replace by ClassInstance.
339 (union i386_operand_type): Replace acc, inoutportreg, and
340 shiftcount by instance.
341 * i386-opc.tbl (Acc, InOutPortReg, ShiftCount): Define.
342 * i386-reg.tbl (st, al, cl, ax, dx, eax, rax, xmm0, st(0)):
343 Add Instance=.
344 * i386-init.h, i386-tbl.h: Re-generate.
345
91802f3c
JB		 3462019-11-11 Jan Beulich <jbeulich@suse.com>
347
348 * aarch64-tbl.h (aarch64_opcode_table): Switch SVE2's
349 smaxp/sminp entries' "tied_operand" field to 2.
350
4f5fc85d
JB		 3512019-11-11 Jan Beulich <jbeulich@suse.com>
352
353 * aarch64-opc.c (operand_general_constraint_met_p): Replace
354 "index" local variable by that of the already existing "num".
355
dc2be329
L		 3562019-11-08 H.J. Lu <hongjiu.lu@intel.com>
357
358 PR gas/25167
359 * i386-opc.tbl: Remove IgnoreSize from cmpsd and movsd.
360 * i386-tbl.h: Regenerated.
361
f74a6307
JB		 3622019-11-08 Jan Beulich <jbeulich@suse.com>
363
364 * i386-gen.c (operand_type_init): Add Class= to
365 OPERAND_TYPE_REGMASK and OPERAND_TYPE_REGBND entries. Move up
366 OPERAND_TYPE_REGBND entry.
367 (operand_classes): Add RegMask and RegBND entries.
368 (operand_types): Drop RegMask and RegBND entry.
369 * i386-opc.h (enum operand_class): Add RegMask and RegBND.
370 (RegMask, RegBND): Delete.
371 (union i386_operand_type): Remove regmask and regbnd fields.
372 * i386-opc.tbl (RegMask, RegBND): Define.
373 * i386-reg.tbl: Replace RegMask by Class=RegMask and RegBND by
374 Class=RegBND.
375 * i386-init.h, i386-tbl.h: Re-generate.
376
3528c362
JB		 3772019-11-08 Jan Beulich <jbeulich@suse.com>
378
379 * i386-gen.c (operand_type_init): Add Class= to
380 OPERAND_TYPE_REGMMX, OPERAND_TYPE_REGXMM, OPERAND_TYPE_REGYMM, and
381 OPERAND_TYPE_REGZMM entries.
382 (operand_classes): Add RegMMX and RegSIMD entries.
383 (operand_types): Drop RegMMX and RegSIMD entries.
384 * i386-opc.h (enum operand_class): Add RegMMX and RegSIMD.
385 (RegMMX, RegSIMD): Delete.
386 (union i386_operand_type): Remove regmmx and regsimd fields.
387 * i386-opc.tbl (RegMMX): Define.
388 (RegXMM, RegYMM, RegZMM): Add Class=.
389 * i386-reg.tbl: Replace RegMMX by Class=RegMMX and RegSIMD by
390 Class=RegSIMD.
391 * i386-init.h, i386-tbl.h: Re-generate.
392
4a5c67ed
JB		 3932019-11-08 Jan Beulich <jbeulich@suse.com>
394
395 * i386-gen.c (operand_type_init): Add Class= to
396 OPERAND_TYPE_CONTROL, OPERAND_TYPE_TEST, and OPERAND_TYPE_DEBUG
397 entries.
398 (operand_classes): Add RegCR, RegDR, and RegTR entries.
399 (operand_types): Drop Control, Debug, and Test entries.
400 * i386-opc.h (enum operand_class): Add RegCR, RegDR, and RegTR.
401 (Control, Debug, Test): Delete.
402 (union i386_operand_type): Remove control, debug, and test
403 fields.
404 * i386-opc.tbl (Control, Debug, Test): Define.
405 * i386-reg.tbl: Replace Control by Class=RegCR, Debug by
406 Class=RegDR, and Test by Class=RegTR.
407 * i386-init.h, i386-tbl.h: Re-generate.
408
00cee14f
JB		 4092019-11-08 Jan Beulich <jbeulich@suse.com>
410
411 * i386-gen.c (operand_type_init): Add Class= to
412 OPERAND_TYPE_SREG entry.
413 (operand_classes): Add SReg entry.
414 (operand_types): Drop SReg entry.
415 * i386-opc.h (enum operand_class): Add SReg.
416 (SReg): Delete.
417 (union i386_operand_type): Remove sreg field.
418 * i386-opc.tbl (SReg): Define.
419 * i386-reg.tbl: Replace SReg by Class=SReg.
420 * i386-init.h, i386-tbl.h: Re-generate.
421
bab6aec1
JB		 4222019-11-08 Jan Beulich <jbeulich@suse.com>
423
424 * i386-gen.c (operand_type_init): Add Class=. New
425 OPERAND_TYPE_ANYIMM entry.
426 (operand_classes): New.
427 (operand_types): Drop Reg entry.
428 (output_operand_type): New parameter "class". Process it.
429 (process_i386_operand_type): New local variable "class".
430 (main): Adjust static assertions.
431 * i386-opc.h (CLASS_WIDTH): Define.
432 (enum operand_class): New.
433 (Reg): Replace by Class. Adjust comment.
434 (union i386_operand_type): Replace reg by class.
435 * i386-opc.tbl (Reg8, Reg16, Reg32, Reg64, FloatReg): Add
436 Class=.
437 * i386-reg.tbl: Replace Reg by Class=Reg.
438 * i386-init.h: Re-generate.
439
1f4cd317
MM		 4402019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
441
442 * opcodes/aarch64-tbl.h (V8_6_INSN): New macro for v8.6 instructions.
443 (aarch64_opcode_table): Add data gathering hint mnemonic.
444 * opcodes/aarch64-dis-2.c: Account for new instruction.
445
616ce08e
MM		 4462019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
447
448 * arm-dis.c (neon_opcodes): Add i8mm SIMD instructions.
449
450
8382113f
MM		 4512019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
452
453 * aarch64-tbl.h (aarch64_feature_i8mm_sve, aarch64_feature_f32mm_sve,
454 aarch64_feature_f64mm_sve, aarch64_feature_i8mm, aarch64_feature_f32mm,
455 aarch64_feature_f64mm): New feature sets.
456 (INT8MATMUL_INSN, F64MATMUL_SVE_INSN, F64MATMUL_INSN,
457 F32MATMUL_SVE_INSN, F32MATMUL_INSN): New macros to define matrix multiply
458 instructions.
459 (I8MM_SVE, F32MM_SVE, F64MM_SVE, I8MM, F32MM, F64MM): New feature set
460 macros.
461 (QL_MMLA64, OP_SVE_SBB): New qualifiers.
462 (OP_SVE_QQQ): New qualifier.
463 (INT8MATMUL_SVE_INSNC, F64MATMUL_SVE_INSNC,
464 F32MATMUL_SVE_INSNC): New feature set for bfloat16 instructions to support
465 the movprfx constraint.
466 (aarch64_opcode_table): Support for SVE_ADDR_RI_S4x32.
467 (aarch64_opcode_table): Define new instructions smmla,
468 ummla, usmmla, usdot, sudot, fmmla, ld1rob, ld1roh, ld1row, ld1rod,
469 uzip{1/2}, trn{1/2}.
470 * aarch64-opc.c (operand_general_constraint_met_p): Handle
471 AARCH64_OPND_SVE_ADDR_RI_S4x32.
472 (aarch64_print_operand): Handle AARCH64_OPND_SVE_ADDR_RI_S4x32.
473 * aarch64-dis-2.c (aarch64_opcode_lookup_1, aarch64_find_next_opcode):
474 Account for new instructions.
475 * opcodes/aarch64-asm-2.c (aarch64_insert_operand): Support the new
476 S4x32 operand.
477 * aarch64-opc-2.c (aarch64_operands): Support the new S4x32 operand.
478
aab2c27d
MM		 4792019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
4802019-11-07 Matthew Malcomson <matthew.malcomson@arm.com>
481
482 * arm-dis.c (select_arm_features): Update bfd_march_arm_8 with
483 Armv8.6-A.
484 (coprocessor_opcodes): Add bfloat16 vcvt{t,b}.
485 (neon_opcodes): Add bfloat SIMD instructions.
486 (print_insn_coprocessor): Add new control character %b to print
487 condition code without checking cp_num.
488 (print_insn_neon): Account for BFloat16 instructions that have no
489 special top-byte handling.
490
33593eaf
MM		 4912019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
4922019-11-07 Matthew Malcomson <matthew.malcomson@arm.com>
493
494 * arm-dis.c (print_insn_coprocessor,
495 print_insn_generic_coprocessor): Create wrapper functions around
496 the implementation of the print_insn_coprocessor control codes.
497 (print_insn_coprocessor_1): Original print_insn_coprocessor
498 function that now takes which array to look at as an argument.
499 (print_insn_arm): Use both print_insn_coprocessor and
500 print_insn_generic_coprocessor.
501 (print_insn_thumb32): As above.
502
df678013
MM		 5032019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
5042019-11-07 Matthew Malcomson <matthew.malcomson@arm.com>
505
506 * aarch64-asm.c (aarch64_ins_reglane): Use AARCH64_OPND_QLF_S_2H
507 in reglane special case.
508 * aarch64-dis-2.c (aarch64_opcode_lookup_1,
509 aarch64_find_next_opcode): Account for new instructions.
510 * aarch64-dis.c (aarch64_ext_reglane): Use AARCH64_OPND_QLF_S_2H
511 in reglane special case.
512 * aarch64-opc.c (struct operand_qualifier_data): Add data for
513 new AARCH64_OPND_QLF_S_2H qualifier.
514 * aarch64-tbl.h (QL_BFDOT QL_BFDOT64, QL_BFDOT64I, QL_BFMMLA2,
515 QL_BFCVT64, QL_BFCVTN64, QL_BFCVTN2_64): New qualifiers.
516 (aarch64_feature_bfloat16, aarch64_feature_bfloat16_sve): New feature
517 sets.
518 (BFLOAT_SVE, BFLOAT): New feature set macros.
519 (BFLOAT_SVE_INSN, BFLOAT_INSN): New macros to define BFloat16
520 instructions.
521 (aarch64_opcode_table): Define new instructions bfdot,
522 bfmmla, bfcvt, bfcvtnt, bfdot, bfdot, bfcvtn, bfmlal[b/t]
523 bfcvtn2, bfcvt.
524
8ae2d3d9
MM		 5252019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
5262019-11-07 Matthew Malcomson <matthew.malcomson@arm.com>
527
528 * aarch64-tbl.h (ARMV8_6): New macro.
529
142861df
JB		 5302019-11-07 Jan Beulich <jbeulich@suse.com>
531
532 * i386-dis.c (prefix_table): Add mcommit.
533 (rm_table): Add rdpru.
534 * i386-gen.c (cpu_flag_init): Adjust CPU_ZNVER2_FLAGS entry. Add
535 CPU_RDPRU_FLAGS and CPU_MCOMMIT_FLAGS entries.
536 (cpu_flags): Add CpuRDPRU and CpuMCOMMIT entries.
537 * i386-opc.h (CpuRDPRU, CpuMCOMMIT): New.
538 (union i386_cpu_flags): Add cpurdpru and cpumcommit fields.
539 * i386-opc.tbl (mcommit, rdpru): New.
540 * i386-init.h, i386-tbl.h: Re-generate.
541
081e283f
JB		 5422019-11-07 Jan Beulich <jbeulich@suse.com>
543
544 * i386-dis.c (OP_Mwait): Drop local variable "names", use
545 "names32" instead.
546 (OP_Monitor): Drop local variable "op1_names", re-purpose
547 "names" for it instead, and replace former "names" uses by
548 "names32" ones.
549
c050c89a
JB		 5502019-11-07 Jan Beulich <jbeulich@suse.com>
551
552 PR/gas 25167
553 * opcodes/i386-opc.tbl (movsd, cmpsd): Drop IgnoreSize from
554 operand-less forms.
555 * opcodes/i386-tbl.h: Re-generate.
556
7abb8d81
JB		 5572019-11-05 Jan Beulich <jbeulich@suse.com>
558
559 * i386-dis.c (OP_Mwaitx): Delete.
560 (prefix_table): Use OP_Mwait for mwaitx entry.
561 (OP_Mwait): Also handle mwaitx.
562
267b8516
JB		 5632019-11-05 Jan Beulich <jbeulich@suse.com>
564
565 * i386-dis.c (PREFIX_0F01_REG_7_MOD_3_RM_2,
566 PREFIX_0F01_REG_7_MOD_3_RM_3): New.
567 (prefix_table): Add respective entries.
568 (rm_table): Link to those entries.
569
f8687e93
JB		 5702019-11-05 Jan Beulich <jbeulich@suse.com>
571
572 * i386-dis.c (REG_0F1C_MOD_0): Rename to ...
573 (REG_0F1C_P_0_MOD_0): ... this.
574 (REG_0F1E_MOD_3): Rename to ...
575 (REG_0F1E_P_1_MOD_3): ... this.
576 (RM_0F01_REG_5): Rename to ...
577 (RM_0F01_REG_5_MOD_3): ... this.
578 (RM_0F01_REG_7): Rename to ...
579 (RM_0F01_REG_7_MOD_3): ... this.
580 (RM_0F1E_MOD_3_REG_7): Rename to ...
581 (RM_0F1E_P_1_MOD_3_REG_7): ... this.
582 (RM_0FAE_REG_6): Rename to ...
583 (RM_0FAE_REG_6_MOD_3_P_0): ... this.
584 (RM_0FAE_REG_7): Rename to ...
585 (RM_0FAE_REG_7_MOD_3): ... this.
586 (PREFIX_MOD_0_0F01_REG_5): Rename to ...
587 (PREFIX_0F01_REG_5_MOD_0): ... this.
588 (PREFIX_MOD_3_0F01_REG_5_RM_0): Rename to ...
589 (PREFIX_0F01_REG_5_MOD_3_RM_0): ... this.
590 (PREFIX_MOD_3_0F01_REG_5_RM_2): Rename to ...
591 (PREFIX_0F01_REG_5_MOD_3_RM_2): ... this.
592 (PREFIX_0FAE_REG_0): Rename to ...
593 (PREFIX_0FAE_REG_0_MOD_3): ... this.
594 (PREFIX_0FAE_REG_1): Rename to ...
595 (PREFIX_0FAE_REG_1_MOD_3): ... this.
596 (PREFIX_0FAE_REG_2): Rename to ...
597 (PREFIX_0FAE_REG_2_MOD_3): ... this.
598 (PREFIX_0FAE_REG_3): Rename to ...
599 (PREFIX_0FAE_REG_3_MOD_3): ... this.
600 (PREFIX_MOD_0_0FAE_REG_4): Rename to ...
601 (PREFIX_0FAE_REG_4_MOD_0): ... this.
602 (PREFIX_MOD_3_0FAE_REG_4): Rename to ...
603 (PREFIX_0FAE_REG_4_MOD_3): ... this.
604 (PREFIX_MOD_0_0FAE_REG_5): Rename to ...
605 (PREFIX_0FAE_REG_5_MOD_0): ... this.
606 (PREFIX_MOD_3_0FAE_REG_5): Rename to ...
607 (PREFIX_0FAE_REG_5_MOD_3): ... this.
608 (PREFIX_MOD_0_0FAE_REG_6): Rename to ...
609 (PREFIX_0FAE_REG_6_MOD_0): ... this.
610 (PREFIX_MOD_1_0FAE_REG_6): Rename to ...
611 (PREFIX_0FAE_REG_6_MOD_3): ... this.
612 (PREFIX_0FAE_REG_7): Rename to ...
613 (PREFIX_0FAE_REG_7_MOD_0): ... this.
614 (PREFIX_MOD_0_0FC3): Rename to ...
615 (PREFIX_0FC3_MOD_0): ... this.
616 (PREFIX_MOD_0_0FC7_REG_6): Rename to ...
617 (PREFIX_0FC7_REG_6_MOD_0): ... this.
618 (PREFIX_MOD_3_0FC7_REG_6): Rename to ...
619 (PREFIX_0FC7_REG_6_MOD_3): ... this.
620 (PREFIX_MOD_3_0FC7_REG_7): Rename to ...
621 (PREFIX_0FC7_REG_7_MOD_3): ... this.
622 (reg_table, prefix_table, mod_table, rm_table): Adjust
623 accordingly.
624
5103274f
NC		 6252019-11-04 Nick Clifton <nickc@redhat.com>
626
627 * v850-dis.c (get_v850_sreg_name): New function. Returns the name
628 of a v850 system register. Move the v850_sreg_names array into
629 this function.
630 (get_v850_reg_name): Likewise for ordinary register names.
631 (get_v850_vreg_name): Likewise for vector register names.
632 (get_v850_cc_name): Likewise for condition codes.
633 * get_v850_float_cc_name): Likewise for floating point condition
634 codes.
635 (get_v850_cacheop_name): Likewise for cache-ops.
636 (get_v850_prefop_name): Likewise for pref-ops.
637 (disassemble): Use the new accessor functions.
638
1820262b
DB		 6392019-10-30 Delia Burduv <delia.burduv@arm.com>
640
641 * aarch64-opc.c (print_immediate_offset_address): Don't print the
642 immediate for the writeback form of ldraa/ldrab if it is 0.
643 * aarch64-tbl.h: Updated the documentation for ADDR_SIMM10.
644 * aarch64-opc-2.c: Regenerated.
645
3cc17af5
JB		 6462019-10-30 Jan Beulich <jbeulich@suse.com>
647
648 * i386-gen.c (operand_type_shorthands): Delete.
649 (operand_type_init): Expand previous shorthands.
650 (set_bitfield_from_shorthand): Rename back to ...
651 (set_bitfield_from_cpu_flag_init): ... this. Drop processing
652 of operand_type_init[].
653 (set_bitfield): Adjust call to the above function.
654 * i386-opc.tbl (Reg8, Reg16, Reg32, Reg64, FloatAcc, FloatReg,
655 RegXMM, RegYMM, RegZMM): Define.
656 * i386-reg.tbl: Expand prior shorthands.
657
a2cebd03
JB		 6582019-10-30 Jan Beulich <jbeulich@suse.com>
659
660 * i386-gen.c (output_i386_opcode): Change order of fields
661 emitted to output.
662 * i386-opc.h (struct insn_template): Move operands field.
663 Convert extension_opcode field to unsigned short.
664 * i386-tbl.h: Re-generate.
665
507916b8
JB		 6662019-10-30 Jan Beulich <jbeulich@suse.com>
667
668 * i386-gen.c (process_i386_opcode_modifier): Report bogus uses
669 of W.
670 * i386-opc.h (W): Extend comment.
671 * i386-opc.tbl (mov, movabs, movq): Drop W and adjust opcodes of
672 general purpose variants not allowing for byte operands.
673 * i386-tbl.h: Re-generate.
674
efea62b4
NC		 6752019-10-29 Nick Clifton <nickc@redhat.com>
676
677 * tic30-dis.c (print_branch): Correct size of operand array.
678
9adb2591
NC		 6792019-10-29 Nick Clifton <nickc@redhat.com>
680
681 * d30v-dis.c (print_insn): Check that operand index is valid
682 before attempting to access the operands array.
683
993a00a9
NC		 6842019-10-29 Nick Clifton <nickc@redhat.com>
685
686 * ia64-opc.c (locate_opcode_ent): Prevent a negative shift when
687 locating the bit to be tested.
688
66a66a17
NC		 6892019-10-29 Nick Clifton <nickc@redhat.com>
690
691 * s12z-dis.c (opr_emit_disassembly): Check for illegal register
692 values.
693 (shift_size_table): Use a fixed size defined as S12Z_N_SIZES.
694 (print_insn_s12z): Check for illegal size values.
695
1ee3542c
NC		 6962019-10-28 Nick Clifton <nickc@redhat.com>
697
698 * csky-dis.c (csky_chars_to_number): Check for a negative
699 count. Use an unsigned integer to construct the return value.
700
bbf9a0b5
NC		 7012019-10-28 Nick Clifton <nickc@redhat.com>
702
703 * tic30-dis.c (OPERAND_BUFFER_LEN): Define. Use as length of
704 operand buffer. Set value to 15 not 13.
705 (get_register_operand): Use OPERAND_BUFFER_LEN.
706 (get_indirect_operand): Likewise.
707 (print_two_operand): Likewise.
708 (print_three_operand): Likewise.
709 (print_oar_insn): Likewise.
710
d1e304bc
NC		 7112019-10-28 Nick Clifton <nickc@redhat.com>
712
713 * ns32k-dis.c (bit_extract): Add sanitiy check of parameters.
714 (bit_extract_simple): Likewise.
715 (bit_copy): Likewise.
716 (pirnt_insn_ns32k): Ensure that uninitialised elements in the
717 index_offset array are not accessed.
718
dee33451
NC		 7192019-10-28 Nick Clifton <nickc@redhat.com>
720
721 * xgate-dis.c (print_insn): Fix decoding of the XGATE_OP_DYA
722 operand.
723
27cee81d
NC		 7242019-10-25 Nick Clifton <nickc@redhat.com>
725
726 * rx-dis.c (print_insn_rx): Use parenthesis to ensure correct
727 access to opcodes.op array element.
728
de6d8dc2
NC		 7292019-10-23 Nick Clifton <nickc@redhat.com>
730
731 * rx-dis.c (get_register_name): Fix spelling typo in error
732 message.
733 (get_condition_name, get_flag_name, get_double_register_name)
734 (get_double_register_high_name, get_double_register_low_name)
735 (get_double_control_register_name, get_double_condition_name)
736 (get_opsize_name, get_size_name): Likewise.
737
6207ed28
NC		 7382019-10-22 Nick Clifton <nickc@redhat.com>
739
740 * rx-dis.c (get_size_name): New function. Provides safe
741 access to name array.
742 (get_opsize_name): Likewise.
743 (print_insn_rx): Use the accessor functions.
744
12234dfd
NC		 7452019-10-16 Nick Clifton <nickc@redhat.com>
746
747 * rx-dis.c (get_register_name): New function. Provides safe
748 access to name array.
749 (get_condition_name, get_flag_name, get_double_register_name)
750 (get_double_register_high_name, get_double_register_low_name)
751 (get_double_control_register_name, get_double_condition_name):
752 Likewise.
753 (print_insn_rx): Use the accessor functions.
754
1d378749
NC		 7552019-10-09 Nick Clifton <nickc@redhat.com>
756
757 PR 25041
758 * avr-dis.c (avr_operand): Fix construction of address for lds/sts
759 instructions.
760
d241b910
JB		 7612019-10-07 Jan Beulich <jbeulich@suse.com>
762
763 * opcodes/i386-opc.tbl (movsd): Add Dword and IgnoreSize.
764 (cmpsd): Likewise. Move EsSeg to other operand.
765 * opcodes/i386-tbl.h: Re-generate.
766
f5c5b7c1
AM		 7672019-09-23 Alan Modra <amodra@gmail.com>
768
769 * m68k-dis.c: Include cpu-m68k.h
770
7beeaeb8
AM		 7712019-09-23 Alan Modra <amodra@gmail.com>
772
773 * mips-dis.c: Include elfxx-mips.h. Move "elf-bfd.h" and
774 "elf/mips.h" earlier.
775
3f9aad11
JB		 7762018-09-20 Jan Beulich <jbeulich@suse.com>
777
778 PR gas/25012
779 * i386-opc.tbl (push, pop): Re-instate distinct Cpu64 templates
780 with SReg operand.
781 * i386-tbl.h: Re-generate.
782
fd361982
AM		 7832019-09-18 Alan Modra <amodra@gmail.com>
784
785 * arc-ext.c: Update throughout for bfd section macro changes.
786
e0b2a78c
SM		 7872019-09-18 Simon Marchi <simon.marchi@polymtl.ca>
788
789 * Makefile.in: Re-generate.
790 * configure: Re-generate.
791
7e9ad3a3
JW		 7922019-09-17 Maxim Blinov <maxim.blinov@embecosm.com>
793
794 * riscv-opc.c (riscv_opcodes): Change subset field
795 to insn_class field for all instructions.
796 (riscv_insn_types): Likewise.
797
bb695960
PB		 7982019-09-16 Phil Blundell <pb@pbcl.net>
799
800 * configure: Regenerated.
801
8063ab7e
MV		 8022019-09-10 Miod Vallat <miod@online.fr>
803
804 PR 24982
805 * m68k-opc.c: Correct aliases for tdivsl and tdivul.
806
60391a25
PB		 8072019-09-09 Phil Blundell <pb@pbcl.net>
808
809 binutils 2.33 branch created.
810
f44b758d
NC		 8112019-09-03 Nick Clifton <nickc@redhat.com>
812
813 PR 24961
814 * tic30-dis.c (get_indirect_operand): Check for bufcnt being
815 greater than zero before indexing via (bufcnt -1).
816
1e4b5e7d
NC		 8172019-09-03 Nick Clifton <nickc@redhat.com>
818
819 PR 24958
820 * mmix-dis.c (MAX_REG_NAME_LEN): Define.
821 (MAX_SPEC_REG_NAME_LEN): Define.
822 (struct mmix_dis_info): Use defined constants for array lengths.
823 (get_reg_name): New function.
824 (get_sprec_reg_name): New function.
825 (print_insn_mmix): Use new functions.
826
c4a23bf8
SP		 8272019-08-27 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
828
829 * arm-dis.c (mve_opcodes): Add entry for MVE_VMOV_VEC_TO_VEC.
830 (is_mve_undefined): Add case for MVE_VMOV_VEC_TO_VEC.
831 (print_insn_mve): Add condition to check Qm==Qn of VORR instruction.
832
a051e2f3
KT		 8332019-08-22 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
834
835 * aarch64-opc.c (aarch64_sys_regs): Update encoding of tfsre0_el1,
836 tfsr_el1, tfsr_el2, tfsr_el3, tfsr_el12.
837 (aarch64_sys_reg_supported_p): Update checks for the above.
838
08132bdd
SP		 8392019-08-12 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
840
841 * arm-dis.c (struct mopcode32 mve_opcodes): Modify the mask for
842 cases MVE_SQRSHRL and MVE_UQRSHLL.
843 (print_insn_mve): Add case for specifier 'k' to check
844 specific bit of the instruction.
845
d88bdcb4
PA		 8462019-08-07 Phillipe Antoine <p.antoine@catenacyber.fr>
847
848 PR 24854
849 * arc-dis.c (arc_insn_length): Return 0 rather than aborting when
850 encountering an unknown machine type.
851 (print_insn_arc): Handle arc_insn_length returning 0. In error
852 cases return -1 rather than calling abort.
853
bc750500
JB		 8542019-08-07 Jan Beulich <jbeulich@suse.com>
855
856 * i386-opc.tbl (fld, fstp): Drop FloatMF from extended forms.
857 (fldcw, fnstcw, fstcw, fnstsw, fstsw): Replace FloatMF by
858 IgnoreSize.
859 * i386-tbl.h: Re-generate.
860
23d188c7
BW		 8612019-08-05 Barnaby Wilks <barnaby.wilks@arm.com>
862
863 * arm-dis.c: Only accept signed variants of VQ(R)DMLAH and VQ(R)DMLASH
864 instructions.
865
c0d6f62f
JW		 8662019-07-30 Mel Chen <mel.chen@sifive.com>
867
868 * riscv-opc.c (riscv_opcodes): Set frsr, fssr, frcsr, fscsr, frrm,
869 fsrm, fsrmi, frflags, fsflags, fsflagsi to alias instructions.
870
871 * riscv-opc.c (riscv_opcodes): Adjust order of frsr, frcsr, fssr,
872 fscsr.
873
0f3f7167
CZ		 8742019-07-24 Claudiu Zissulescu <claziss@synopsys.com>
875
876 * arc-dis.c (skip_this_opcode): Check also for 0x07 major opcodes,
877 and MPY class instructions.
878 (parse_option): Add nps400 option.
879 (print_arc_disassembler_options): Add nps400 info.
880
7e126ba3
CZ		 8812019-07-24 Claudiu Zissulescu <claziss@synopsys.com>
882
883 * arc-ext-tbl.h (bspeek): Remove it, added to main table.
884 (bspop): Likewise.
885 (modapp): Likewise.
886 * arc-opc.c (RAD_CHK): Add.
887 * arc-tbl.h: Regenerate.
888
a028026d
KT		 8892019-07-23 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
890
891 * aarch64-opc.c (aarch64_sys_regs): Add gmid_el1 entry.
892 (aarch64_sys_reg_supported_p): Handle gmid_el1 encoding.
893
ac79ff9e
NC		 8942019-07-22 Barnaby Wilks <barnaby.wilks@arm.com>
895
896 * arm-dis.c (is_mve_unpredictable): Stop marking some MVE
897 instructions as UNPREDICTABLE.
898
231097b0
JM		 8992019-07-19 Jose E. Marchesi <jose.marchesi@oracle.com>
900
901 * bpf-desc.c: Regenerated.
902
1d942ae9
JB		 9032019-07-17 Jan Beulich <jbeulich@suse.com>
904
905 * i386-gen.c (static_assert): Define.
906 (main): Use it.
907 * i386-opc.h (Opcode_Modifier_Max): Rename to ...
908 (Opcode_Modifier_Num): ... this.
909 (Mem): Delete.
910
dfd69174
JB		 9112019-07-16 Jan Beulich <jbeulich@suse.com>
912
913 * i386-gen.c (operand_types): Move RegMem ...
914 (opcode_modifiers): ... here.
915 * i386-opc.h (RegMem): Move to opcode modifer enum.
916 (union i386_operand_type): Move regmem field ...
917 (struct i386_opcode_modifier): ... here.
918 * i386-opc.tbl (RegMem): Define.
919 (mov, movq): Move RegMem on segment, control, debug, and test
920 register flavors.
921 (pextrb): Move RegMem on register only flavors. Add IgnoreSize
922 to non-SSE2AVX flavor.
923 (extractps, pextrw, vcvtps2ph, vextractps, vpextrb, vpextrw):
924 Move RegMem on register only flavors. Drop IgnoreSize from
925 legacy encoding flavors.
926 (movss, movsd, vmovss, vmovsd): Drop RegMem from register only
927 flavors.
928 (vpinsrb, vpinsrw): Drop IgnoreSize where still present on
929 register only flavors.
930 (vmovd): Move RegMem and drop IgnoreSize on register only
931 flavor. Change opcode and operand order to store form.
932 * opcodes/i386-init.h, i386-tbl.h: Re-generate.
933
21df382b
JB		 9342019-07-16 Jan Beulich <jbeulich@suse.com>
935
936 * i386-gen.c (operand_type_init, operand_types): Replace SReg
937 entries.
938 * i386-opc.h (SReg2, SReg3): Replace by ...
939 (SReg): ... this.
940 (union i386_operand_type): Replace sreg fields.
941 * i386-opc.tbl (mov, ): Use SReg.
942 (push, pop): Likewies. Drop i386 and x86-64 specific segment
943 register flavors.
944 * i386-reg.tbl (cs, ds, es, fs, gs, ss, flat): Use SReg.
945 * opcodes/i386-init.h, i386-tbl.h: Re-generate.
946
3719fd55
JM		 9472019-07-15 Jose E. Marchesi <jose.marchesi@oracle.com>
948
949 * bpf-desc.c: Regenerate.
950 * bpf-opc.c: Likewise.
951 * bpf-opc.h: Likewise.
952
92434a14
JM		 9532019-07-14 Jose E. Marchesi <jose.marchesi@oracle.com>
954
955 * bpf-desc.c: Regenerate.
956 * bpf-opc.c: Likewise.
957
43dd7626
HPN		 9582019-07-10 Hans-Peter Nilsson <hp@bitrange.com>
959
960 * arm-dis.c (print_insn_coprocessor): Rename index to
961 index_operand.
962
98602811
JW		 9632019-07-05 Kito Cheng <kito.cheng@sifive.com>
964
965 * riscv-opc.c (riscv_insn_types): Add r4 type.
966
967 * riscv-opc.c (riscv_insn_types): Add b and j type.
968
969 * opcodes/riscv-opc.c (riscv_insn_types): Remove incorrect
970 format for sb type and correct s type.
971
01c1ee4a
RS		 9722019-07-02 Richard Sandiford <richard.sandiford@arm.com>
973
974 * aarch64-tbl.h (aarch64_opcode): Set C_SCAN_MOVPRFX for the
975 SVE FMOV alias of FCPY.
976
83adff69
RS		 9772019-07-02 Richard Sandiford <richard.sandiford@arm.com>
978
979 * aarch64-tbl.h (aarch64_opcode_table): Add C_MAX_ELEM flags
980 to SVE fcvtzs, fcvtzu, scvtf and ucvtf entries.
981
89418844
RS		 9822019-07-02 Richard Sandiford <richard.sandiford@arm.com>
983
984 * aarch64-opc.c (verify_constraints): Skip GPRs when scanning the
985 registers in an instruction prefixed by MOVPRFX.
986
41be57ca
MM		 9872019-07-01 Matthew Malcomson <matthew.malcomson@arm.com>
988
989 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Use new
990 sve_size_13 icode to account for variant behaviour of
991 pmull{t,b}.
992 * aarch64-dis-2.c: Regenerate.
993 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Use new
994 sve_size_13 icode to account for variant behaviour of
995 pmull{t,b}.
996 * aarch64-tbl.h (OP_SVE_VVV_HD_BS): Add new qualifier.
997 (OP_SVE_VVV_Q_D): Add new qualifier.
998 (OP_SVE_VVV_QHD_DBS): Remove now unused qualifier.
999 (struct aarch64_opcode): Split pmull{t,b} into those requiring
1000 AES and those not.
1001
9d3bf266
JB		 10022019-07-01 Jan Beulich <jbeulich@suse.com>
1003
1004 * opcodes/i386-gen.c (operand_type_init): Remove
1005 OPERAND_TYPE_VEC_IMM4 entry.
1006 (operand_types): Remove Vec_Imm4.
1007 * opcodes/i386-opc.h (Vec_Imm4): Delete.
1008 (union i386_operand_type): Remove vec_imm4.
1009 * i386-opc.tbl (vpermil2pd, vpermil2ps): Remove Vec_Imm4.
1010 * opcodes/i386-init.h, i386-tbl.h: Re-generate.
1011
c3949f43
JB		 10122019-07-01 Jan Beulich <jbeulich@suse.com>
1013
1014 * i386-opc.tbl (lfence, mfence, sfence, monitor, mwait, vmcall,
1015 vmlaunch, vmresume, vmxoff, vmfunc, xgetbv, xsetbv, swapgs,
1016 rdtscp, clgi, invlpga, skinit, stgi, vmload, vmmcall, vmrun,
1017 vmsave, montmul, xsha1, xsha256, xstorerng, xcryptecb,
1018 xcryptcbc, xcryptctr, xcryptcfb, xcryptofb, xstore, clac, stac,
1019 monitorx, mwaitx): Drop ImmExt from operand-less forms.
1020 * i386-tbl.h: Re-generate.
1021
5641ec01
JB		 10222019-07-01 Jan Beulich <jbeulich@suse.com>
1023
1024 * i386-opc.tbl (and, or): Add Optimize to forms allowing two
1025 register operands.
1026 * i386-tbl.h: Re-generate.
1027
79dec6b7
JB		 10282019-07-01 Jan Beulich <jbeulich@suse.com>
1029
1030 * i386-opc.tbl (C): New.
1031 (paddb, paddw, paddd, paddq, paddsb, paddsw, paddusb, paddusw,
1032 pand, pcmpeqb, pcmpeqw, pcmpeqd, pmaddwd, pmulhw, pmullw,
1033 por, pxor, andps, cmpeqps, cmpeqss, cmpneqps, cmpneqss,
1034 cmpordps, cmpordss, cmpunordps, cmpunordss, orps, pavgb, pavgw,
1035 pmaxsw, pmaxub, pminsw, pminub, pmulhuw, xorps, andpd, cmpeqpd,
1036 cmpeqsd, cmpneqpd, cmpneqsd, cmpordpd, cmpordsd, cmpunordpd,
1037 cmpunordsd, orpd, xorpd, pmuludq, vandpd, vandps, vcmpeq_ospd,
1038 vcmpeq_osps, vcmpeq_ossd, vcmpeq_osss, vcmpeqpd, vcmpeqps,
1039 vcmpeqsd, vcmpeqss, vcmpeq_uqpd, vcmpeq_uqps, vcmpeq_uqsd,
1040 vcmpeq_uqss, vcmpeq_uspd, vcmpeq_usps, vcmpeq_ussd,
1041 vcmpeq_usss, vcmpfalse_ospd, vcmpfalse_osps, vcmpfalse_ossd,
1042 vcmpfalse_osss, vcmpfalsepd, vcmpfalseps, vcmpfalsesd,
1043 vcmpfalsess, vcmpneq_oqpd, vcmpneq_oqps, vcmpneq_oqsd,
1044 vcmpneq_oqss, vcmpneq_ospd, vcmpneq_osps, vcmpneq_ossd,
1045 vcmpneq_osss, vcmpneqpd, vcmpneqps, vcmpneqsd, vcmpneqss,
1046 vcmpneq_uspd, vcmpneq_usps, vcmpneq_ussd, vcmpneq_usss,
1047 vcmpordpd, vcmpordps, vcmpordsd, vcmpord_spd, vcmpord_sps,
1048 vcmpordss, vcmpord_ssd, vcmpord_sss, vcmptruepd, vcmptrueps,
1049 vcmptruesd, vcmptruess, vcmptrue_uspd, vcmptrue_usps,
1050 vcmptrue_ussd, vcmptrue_usss, vcmpunordpd, vcmpunordps,
1051 vcmpunordsd, vcmpunord_spd, vcmpunord_sps, vcmpunordss,
1052 vcmpunord_ssd, vcmpunord_sss, vorpd, vorps, vpaddsb, vpaddsw,
1053 vpaddb, vpaddd, vpaddq, vpaddw, vpaddusb, vpaddusw, vpand,
1054 vpavgb, vpavgw, vpcmpeqb, vpcmpeqd, vpcmpeqw, vpmaddwd,
1055 vpmaxsw, vpmaxub, vpminsw, vpminub, vpmulhuw, vpmulhw, vpmullw,
1056 vpmuludq, vpor, vpxor, vxorpd, vxorps): Add C to VEX-encoded
1057 flavors.
1058 * i386-tbl.h: Re-generate.
1059
a0a1771e
JB		 10602019-07-01 Jan Beulich <jbeulich@suse.com>
1061
1062 * i386-opc.tbl (and, or): Add Optimize to forms allowing two
1063 register operands.
1064 * i386-tbl.h: Re-generate.
1065
cd546e7b
JB		 10662019-07-01 Jan Beulich <jbeulich@suse.com>
1067
1068 * i386-dis-evex-prefix.h: Use PCLMUL for vpclmulqdq.
1069 * i386-opc.tbl (vpclmullqlqdq, vpclmulhqlqdq, vpclmullqhqdq,
1070 vpclmulhqhqdq): Add CpuVPCLMULQDQ flavors.
1071 * i386-tbl.h: Re-generate.
1072
e3bba3fc
JB		 10732019-07-01 Jan Beulich <jbeulich@suse.com>
1074
1075 * i386-opc.tbl (vextractps, vpextrw, vpinsrw): Remove
1076 Disp8MemShift from register only templates.
1077 * i386-tbl.h: Re-generate.
1078
36cc073e
JB		 10792019-07-01 Jan Beulich <jbeulich@suse.com>
1080
1081 * i386-dis.c (EXdScalarS, MOD_EVEX_0F10_PREFIX_1,
1082 MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1,
1083 MOD_EVEX_0F11_PREFIX_3, EVEX_W_0F10_P_1_M_0,
1084 EVEX_W_0F10_P_1_M_1, EVEX_W_0F10_P_3_M_0, EVEX_W_0F10_P_3_M_1,
1085 EVEX_W_0F11_P_1_M_0, EVEX_W_0F11_P_1_M_1, EVEX_W_0F11_P_3_M_0,
1086 EVEX_W_0F11_P_3_M_1): Delete.
1087 (EVEX_W_0F10_P_1, EVEX_W_0F10_P_3, EVEX_W_0F11_P_1,
1088 EVEX_W_0F11_P_3): New.
1089 * i386-dis-evex-mod.h: Remove MOD_EVEX_0F10_PREFIX_1,
1090 MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1, and
1091 MOD_EVEX_0F11_PREFIX_3 table entries.
1092 * i386-dis-evex-prefix.h: Adjust PREFIX_EVEX_0F10 and
1093 PREFIX_EVEX_0F11 table entries.
1094 * i386-dis-evex-w.h: Replace EVEX_W_0F10_P_1_M_{0,1},
1095 EVEX_W_0F10_P_3_M_{0,1}, EVEX_W_0F11_P_1_M_{0,1}, and
1096 EVEX_W_0F11_P_3_M_{0,1} table entries.
1097
219920a7
JB		 10982019-07-01 Jan Beulich <jbeulich@suse.com>
1099
1100 * i386-dis.c (EXdVex, EXdVexS, EXqVex, EXqVexS, XMVex):
1101 Delete.
1102
e395f487
L		 11032019-06-27 H.J. Lu <hongjiu.lu@intel.com>
1104
1105 PR binutils/24719
1106 * i386-dis-evex-len.h: Add EVEX_LEN_0F38C6_REG_1_PREFIX_2,
1107 EVEX_LEN_0F38C6_REG_2_PREFIX_2, EVEX_LEN_0F38C6_REG_5_PREFIX_2,
1108 EVEX_LEN_0F38C6_REG_6_PREFIX_2, EVEX_LEN_0F38C7_R_1_P_2_W_0,
1109 EVEX_LEN_0F38C7_R_1_P_2_W_1, EVEX_LEN_0F38C7_R_2_P_2_W_0,
1110 EVEX_LEN_0F38C7_R_2_P_2_W_1, EVEX_LEN_0F38C7_R_5_P_2_W_0,
1111 EVEX_LEN_0F38C7_R_5_P_2_W_1, EVEX_LEN_0F38C7_R_6_P_2_W_0 and
1112 EVEX_LEN_0F38C7_R_6_P_2_W_1.
1113 * i386-dis-evex-prefix.h: Update PREFIX_EVEX_0F38C6_REG_1,
1114 PREFIX_EVEX_0F38C6_REG_2, PREFIX_EVEX_0F38C6_REG_5 and
1115 PREFIX_EVEX_0F38C6_REG_6 entries.
1116 * i386-dis-evex-w.h: Update EVEX_W_0F38C7_R_1_P_2,
1117 EVEX_W_0F38C7_R_2_P_2, EVEX_W_0F38C7_R_5_P_2 and
1118 EVEX_W_0F38C7_R_6_P_2 entries.
1119 * i386-dis.c: Add EVEX_LEN_0F38C6_REG_1_PREFIX_2,
1120 EVEX_LEN_0F38C6_REG_2_PREFIX_2, EVEX_LEN_0F38C6_REG_5_PREFIX_2,
1121 EVEX_LEN_0F38C6_REG_6_PREFIX_2, EVEX_LEN_0F38C7_R_1_P_2_W_0,
1122 EVEX_LEN_0F38C7_R_1_P_2_W_1, EVEX_LEN_0F38C7_R_2_P_2_W_0,
1123 EVEX_LEN_0F38C7_R_2_P_2_W_1, EVEX_LEN_0F38C7_R_5_P_2_W_0,
1124 EVEX_LEN_0F38C7_R_5_P_2_W_1, EVEX_LEN_0F38C7_R_6_P_2_W_0 and
1125 EVEX_LEN_0F38C7_R_6_P_2_W_1 enums.
1126
2b7bcc87
JB		 11272019-06-27 Jan Beulich <jbeulich@suse.com>
1128
1129 * i386-dis.c (VEX_LEN_0F2A_P_1, VEX_LEN_0F2A_P_3,
1130 VEX_LEN_0F2C_P_1, VEX_LEN_0F2C_P_3, VEX_LEN_0F2D_P_1,
1131 VEX_LEN_0F2D_P_3): Delete.
1132 (vex_len_table): Move vcvtsi2ss, vcvtsi2sd, vcvttss2si,
1133 vcvttsd2si, vcvtss2si, and vcvtsd2si leaf entries ...
1134 (prefix_table): ... here.
1135
c1dc7af5
JB		 11362019-06-27 Jan Beulich <jbeulich@suse.com>
1137
1138 * i386-dis.c (Iq): Delete.
1139 (Id): New.
1140 (reg_table): Use it for lwpins, lwpval, and bextr. Use Edq for
1141 TBM insns.
1142 (vex_len_table): Use Edq for vcvtsi2ss, vcvtsi2sd. Use Gdq for
1143 vcvttss2si, vcvttsd2si, vcvtss2si, and vcvtsd2si.
1144 (OP_E_memory): Also honor needindex when deciding whether an
1145 address size prefix needs printing.
1146 (OP_I): Remove handling of q_mode. Add handling of d_mode.
1147
d7560e2d
JW		 11482019-06-26 Jim Wilson <jimw@sifive.com>
1149
1150 PR binutils/24739
1151 * riscv-dis.c (riscv_disasemble_insn): Set info->endian_code.
1152 Set info->display_endian to info->endian_code.
1153
2c703856
JB		 11542019-06-25 Jan Beulich <jbeulich@suse.com>
1155
1156 * i386-gen.c (operand_type_init): Correct OPERAND_TYPE_DEBUG
1157 entry. Drop OPERAND_TYPE_ACC entry. Add OPERAND_TYPE_ACC8 and
1158 OPERAND_TYPE_ACC16 entries. Adjust OPERAND_TYPE_ACC32 and
1159 OPERAND_TYPE_ACC64 entries.
1160 * i386-init.h: Re-generate.
1161
54fbadc0
JB		 11622019-06-25 Jan Beulich <jbeulich@suse.com>
1163
1164 * i386-dis.c (Edqa, dqa_mode, EVEX_W_0F2A_P_1, EVEX_W_0F7B_P_1):
1165 Delete.
1166 (intel_operand_size, OP_E_register, OP_E_memory): Drop handling
1167 of dqa_mode.
1168 * i386-dis-evex-prefix.h: Move vcvtsi2ss and vcvtusi2ss leaf
1169 entries here.
1170 * i386-dis-evex-w.h: Drop EVEX_W_0F2A_P_1 and EVEX_W_0F7B_P_1
1171 entries. Use Edq for vcvtsi2sd and vcvtusi2sd.
1172
a280ab8e
JB		 11732019-06-25 Jan Beulich <jbeulich@suse.com>
1174
1175 * i386-dis.c (OP_I64): Forword more cases to OP_I(). Drop local
1176 variables.
1177
e1a1babd
JB		 11782019-06-25 Jan Beulich <jbeulich@suse.com>
1179
1180 * i386-dis.c (prefix_table): Use Edq for cvtsi2ss and cvtsi2sd.
1181 Use Gdq for cvttss2si, cvttsd2si, cvtss2si, and cvtsd2si, and
1182 movnti.
d7560e2d 1183 * i386-opc.tbl (movnti): Add IgnoreSize.
e1a1babd
JB		 1184 * i386-tbl.h: Re-generate.
1185
b8364fa7
JB		 11862019-06-25 Jan Beulich <jbeulich@suse.com>
1187
1188 * i386-opc.tbl (and): Mark Imm8S form for optimization.
1189 * i386-tbl.h: Re-generate.
1190
ad692897
L		 11912019-06-21 H.J. Lu <hongjiu.lu@intel.com>
1192
1193 * i386-dis-evex.h: Break into ...
1194 * i386-dis-evex-len.h: New file.
1195 * i386-dis-evex-mod.h: Likewise.
1196 * i386-dis-evex-prefix.h: Likewise.
1197 * i386-dis-evex-reg.h: Likewise.
1198 * i386-dis-evex-w.h: Likewise.
1199 * i386-dis.c: Include i386-dis-evex-reg.h, i386-dis-evex-prefix.h,
1200 i386-dis-evex.h, i386-dis-evex-len.h, i386-dis-evex-w.h and
1201 i386-dis-evex-mod.h.
1202
f0a6222e
L		 12032019-06-19 H.J. Lu <hongjiu.lu@intel.com>
1204
1205 PR binutils/24700
1206 * i386-dis-evex.h (evex_table): Update EVEX_W_0F3819_P_2,
1207 EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2, EVEX_W_0F385A_P_2 and
1208 EVEX_W_0F385B_P_2.
1209 (evex_len_table): Add EVEX_LEN_0F3819_P_2_W_0,
1210 EVEX_LEN_0F3819_P_2_W_1, EVEX_LEN_0F381A_P_2_W_0,
1211 EVEX_LEN_0F381A_P_2_W_1, EVEX_LEN_0F381B_P_2_W_0,
1212 EVEX_LEN_0F381B_P_2_W_1, EVEX_LEN_0F385A_P_2_W_0,
1213 EVEX_LEN_0F385A_P_2_W_1, EVEX_LEN_0F385B_P_2_W_0 and
1214 EVEX_LEN_0F385B_P_2_W_1.
1215 * i386-dis.c (EVEX_LEN_0F3819_P_2_W_0): New enum.
1216 (EVEX_LEN_0F3819_P_2_W_1): Likewise.
1217 (EVEX_LEN_0F381A_P_2_W_0): Likewise.
1218 (EVEX_LEN_0F381A_P_2_W_1): Likewise.
1219 (EVEX_LEN_0F381B_P_2_W_0): Likewise.
1220 (EVEX_LEN_0F381B_P_2_W_1): Likewise.
1221 (EVEX_LEN_0F385A_P_2_W_0): Likewise.
1222 (EVEX_LEN_0F385A_P_2_W_1): Likewise.
1223 (EVEX_LEN_0F385B_P_2_W_0): Likewise.
1224 (EVEX_LEN_0F385B_P_2_W_1): Likewise.
1225
6e1c90b7
L		 12262019-06-17 H.J. Lu <hongjiu.lu@intel.com>
1227
1228 PR binutils/24691
1229 * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A23_P_2,
1230 EVEX_W_0F3A38_P_2, EVEX_W_0F3A39_P_2, EVEX_W_0F3A3A_P_2,
1231 EVEX_W_0F3A3B_P_2 and EVEX_W_0F3A43_P_2.
1232 (evex_len_table): Add EVEX_LEN_0F3A23_P_2_W_0,
1233 EVEX_LEN_0F3A23_P_2_W_1, EVEX_LEN_0F3A38_P_2_W_0,
1234 EVEX_LEN_0F3A38_P_2_W_1, EVEX_LEN_0F3A39_P_2_W_0,
1235 EVEX_LEN_0F3A39_P_2_W_1, EVEX_LEN_0F3A3A_P_2_W_0,
1236 EVEX_LEN_0F3A3A_P_2_W_1, EVEX_LEN_0F3A3B_P_2_W_0,
1237 EVEX_LEN_0F3A3B_P_2_W_1, EVEX_LEN_0F3A43_P_2_W_0 and
1238 EVEX_LEN_0F3A43_P_2_W_1.
1239 * i386-dis.c (EVEX_LEN_0F3A23_P_2_W_0): New enum.
1240 (EVEX_LEN_0F3A23_P_2_W_1): Likewise.
1241 (EVEX_LEN_0F3A38_P_2_W_0): Likewise.
1242 (EVEX_LEN_0F3A38_P_2_W_1): Likewise.
1243 (EVEX_LEN_0F3A39_P_2_W_0): Likewise.
1244 (EVEX_LEN_0F3A39_P_2_W_1): Likewise.
1245 (EVEX_LEN_0F3A3A_P_2_W_0): Likewise.
1246 (EVEX_LEN_0F3A3A_P_2_W_1): Likewise.
1247 (EVEX_LEN_0F3A3B_P_2_W_0): Likewise.
1248 (EVEX_LEN_0F3A3B_P_2_W_1): Likewise.
1249 (EVEX_LEN_0F3A43_P_2_W_0): Likewise.
1250 (EVEX_LEN_0F3A43_P_2_W_1): Likewise.
1251
bcc5a6eb
NC		 12522019-06-14 Nick Clifton <nickc@redhat.com>
1253
1254 * po/fr.po; Updated French translation.
1255
e4c4ac46
SH		 12562019-06-13 Stafford Horne <shorne@gmail.com>
1257
1258 * or1k-asm.c: Regenerated.
1259 * or1k-desc.c: Regenerated.
1260 * or1k-desc.h: Regenerated.
1261 * or1k-dis.c: Regenerated.
1262 * or1k-ibld.c: Regenerated.
1263 * or1k-opc.c: Regenerated.
1264 * or1k-opc.h: Regenerated.
1265 * or1k-opinst.c: Regenerated.
1266
a0e44ef5
PB		 12672019-06-12 Peter Bergner <bergner@linux.ibm.com>
1268
1269 * ppc-opc.c (powerpc_opcodes) <ldmx>: Delete mnemonic.
1270
12efd68d
L		 12712019-06-05 H.J. Lu <hongjiu.lu@intel.com>
1272
1273 PR binutils/24633
1274 * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A18_P_2,
1275 EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2 and EVEX_W_0F3A1B_P_2.
1276 (evex_len_table): EVEX_LEN_0F3A18_P_2_W_0,
1277 EVEX_LEN_0F3A18_P_2_W_1, EVEX_LEN_0F3A19_P_2_W_0,
1278 EVEX_LEN_0F3A19_P_2_W_1, EVEX_LEN_0F3A1A_P_2_W_0,
1279 EVEX_LEN_0F3A1A_P_2_W_1, EVEX_LEN_0F3A1B_P_2_W_0,
1280 EVEX_LEN_0F3A1B_P_2_W_1.
1281 * i386-dis.c (EVEX_LEN_0F3A18_P_2_W_0): New enum.
1282 (EVEX_LEN_0F3A18_P_2_W_1): Likewise.
1283 (EVEX_LEN_0F3A19_P_2_W_0): Likewise.
1284 (EVEX_LEN_0F3A19_P_2_W_1): Likewise.
1285 (EVEX_LEN_0F3A1A_P_2_W_0): Likewise.
1286 (EVEX_LEN_0F3A1A_P_2_W_1): Likewise.
1287 (EVEX_LEN_0F3A1B_P_2_W_0): Likewise.
1288 (EVEX_LEN_0F3A1B_P_2_W_1): Likewise.
1289
63c6fc6c
L		 12902019-06-04 H.J. Lu <hongjiu.lu@intel.com>
1291
1292 PR binutils/24626
1293 * i386-dis.c (print_insn): Check for unused VEX.vvvv and
1294 EVEX.vvvv when disassembling VEX and EVEX instructions.
1295 (OP_VEX): Set vex.register_specifier to 0 after readding
1296 vex.register_specifier.
1297 (OP_Vex_2src_1): Likewise.
1298 (OP_Vex_2src_2): Likewise.
1299 (OP_LWP_E): Likewise.
1300 (OP_EX_Vex): Don't check vex.register_specifier.
1301 (OP_XMM_Vex): Likewise.
1302
9186c494
L		 13032019-06-04 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1304 Lili Cui <lili.cui@intel.com>
1305
1306 * i386-dis.c (enum): Add PREFIX_EVEX_0F3868, EVEX_W_0F3868_P_3.
1307 * i386-dis-evex.h (evex_table): Add AVX512_VP2INTERSECT
1308 instructions.
1309 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VP2INTERSECT_FLAGS,
1310 CPU_ANY_AVX512_VP2INTERSECT_FLAGS.
1311 (cpu_flags): Add CpuAVX512_VP2INTERSECT.
1312 * i386-opc.h (enum): Add CpuAVX512_VP2INTERSECT.
1313 (i386_cpu_flags): Add cpuavx512_vp2intersect.
1314 * i386-opc.tbl: Add AVX512_VP2INTERSECT insns.
1315 * i386-init.h: Regenerated.
1316 * i386-tbl.h: Likewise.
1317
5d79adc4
L		 13182019-06-04 Xuepeng Guo <xuepeng.guo@intel.com>
1319 Lili Cui <lili.cui@intel.com>
1320
1321 * doc/c-i386.texi: Document enqcmd.
1322 * testsuite/gas/i386/enqcmd-intel.d: New file.
1323 * testsuite/gas/i386/enqcmd-inval.l: Likewise.
1324 * testsuite/gas/i386/enqcmd-inval.s: Likewise.
1325 * testsuite/gas/i386/enqcmd.d: Likewise.
1326 * testsuite/gas/i386/enqcmd.s: Likewise.
1327 * testsuite/gas/i386/x86-64-enqcmd-intel.d: Likewise.
1328 * testsuite/gas/i386/x86-64-enqcmd-inval.l: Likewise.
1329 * testsuite/gas/i386/x86-64-enqcmd-inval.s: Likewise.
1330 * testsuite/gas/i386/x86-64-enqcmd.d: Likewise.
1331 * testsuite/gas/i386/x86-64-enqcmd.s: Likewise.
1332 * testsuite/gas/i386/i386.exp: Run enqcmd-intel, enqcmd-inval,
1333 enqcmd, x86-64-enqcmd-intel, x86-64-enqcmd-inval,
1334 and x86-64-enqcmd.
1335
a9d96ab9
AH		 13362019-06-04 Alan Hayward <alan.hayward@arm.com>
1337
1338 * arm-dis.c (is_mve_unpredictable): Remove spurious paranthesis.
1339
4f6d070a
AM		 13402019-06-03 Alan Modra <amodra@gmail.com>
1341
1342 * ppc-dis.c (prefix_opcd_indices): Correct size.
1343
a2f4b66c
L		 13442019-05-28 H.J. Lu <hongjiu.lu@intel.com>
1345
1346 PR gas/24625
1347 * i386-opc.tbl: Add CheckRegSize to AVX512_BF16 instructions with
1348 Disp8ShiftVL.
1349 * i386-tbl.h: Regenerated.
1350
405b5bd8
AM		 13512019-05-24 Alan Modra <amodra@gmail.com>
1352
1353 * po/POTFILES.in: Regenerate.
1354
8acf1435
PB		 13552019-05-24 Peter Bergner <bergner@linux.ibm.com>
1356 Alan Modra <amodra@gmail.com>
1357
1358 * ppc-opc.c (insert_d34, extract_d34, insert_nsi34, extract_nsi34),
1359 (insert_pcrel, extract_pcrel, extract_pcrel0): New functions.
1360 (extract_esync, extract_raq, extract_tbr, extract_sxl): Comment.
1361 (powerpc_operands <D34, SI34, NSI34, PRA0, PRAQ, PCREL, PCREL0,
1362 XTOP>): Define and add entries.
1363 (P8LS, PMLS, P_D_MASK, P_DRAPCREL_MASK): Define.
1364 (prefix_opcodes): Add pli, paddi, pla, psubi, plwz, plbz, pstw,
1365 pstb, plhz, plha, psth, plfs, plfd, pstfs, pstfd, plq, plxsd,
1366 plxssp, pld, plwa, pstxsd, pstxssp, pstxv, pstd, and pstq.
1367
dd7efa79
PB		 13682019-05-24 Peter Bergner <bergner@linux.ibm.com>
1369 Alan Modra <amodra@gmail.com>
1370
1371 * ppc-dis.c (ppc_opts): Add "future" entry.
1372 (PREFIX_OPCD_SEGS): Define.
1373 (prefix_opcd_indices): New array.
1374 (disassemble_init_powerpc): Initialize prefix_opcd_indices.
1375 (lookup_prefix): New function.
1376 (print_insn_powerpc): Handle 64-bit prefix instructions.
1377 * ppc-opc.c (PREFIX_OP, PREFIX_FORM, SUFFIX_MASK, PREFIX_MASK),
1378 (PMRR, POWERXX): Define.
1379 (prefix_opcodes): New instruction table.
1380 (prefix_num_opcodes): New constant.
1381
79472b45
JM		 13822019-05-23 Jose E. Marchesi <jose.marchesi@oracle.com>
1383
1384 * configure.ac (SHARED_DEPENDENCIES): Add case for bfd_bpf_arch.
1385 * configure: Regenerated.
1386 * Makefile.am: Add rules for the files generated from cpu/bpf.cpu
1387 and cpu/bpf.opc.
1388 (HFILES): Add bpf-desc.h and bpf-opc.h.
1389 (TARGET_LIBOPCODES_CFILES): Add bpf-asm.c, bpf-desc.c, bpf-dis.c,
1390 bpf-ibld.c and bpf-opc.c.
1391 (BPF_DEPS): Define.
1392 * Makefile.in: Regenerated.
1393 * disassemble.c (ARCH_bpf): Define.
1394 (disassembler): Add case for bfd_arch_bpf.
1395 (disassemble_init_for_target): Likewise.
1396 (enum epbf_isa_attr): Define.
1397 * disassemble.h: extern print_insn_bpf.
1398 * bpf-asm.c: Generated.
1399 * bpf-opc.h: Likewise.
1400 * bpf-opc.c: Likewise.
1401 * bpf-ibld.c: Likewise.
1402 * bpf-dis.c: Likewise.
1403 * bpf-desc.h: Likewise.
1404 * bpf-desc.c: Likewise.
1405
ba6cd17f
SD		 14062019-05-21 Sudakshina Das <sudi.das@arm.com>
1407
1408 * arm-dis.c (coprocessor_opcodes): New instructions for VMRS
1409 and VMSR with the new operands.
1410
e39c1607
SD		 14112019-05-21 Sudakshina Das <sudi.das@arm.com>
1412
1413 * arm-dis.c (enum mve_instructions): New enum
1414 for csinc, csinv, csneg, csel, cset, csetm, cinv, cinv
1415 and cneg.
1416 (mve_opcodes): New instructions as above.
1417 (is_mve_encoding_conflict): Add cases for csinc, csinv,
1418 csneg and csel.
1419 (print_insn_mve): Accept new %<bitfield>c and %<bitfield>C.
1420
23d00a41
SD		 14212019-05-21 Sudakshina Das <sudi.das@arm.com>
1422
1423 * arm-dis.c (emun mve_instructions): Updated for new instructions.
1424 (mve_opcodes): New instructions for asrl, lsll, lsrl, sqrshrl,
1425 sqrshr, sqshl, sqshll, srshr, srshrl, uqrshll, uqrshl, uqshll,
1426 uqshl, urshrl and urshr.
1427 (is_mve_okay_in_it): Add new instructions to TRUE list.
1428 (is_mve_unpredictable): Add cases for UNPRED_R13 and UNPRED_R15.
1429 (print_insn_mve): Updated to accept new %j,
1430 %<bitfield>m and %<bitfield>n patterns.
1431
cd4797ee
FS		 14322019-05-21 Faraz Shahbazker <fshahbazker@wavecomp.com>
1433
1434 * mips-opc.c (mips_builtin_opcodes): Change source register
1435 constraint for DAUI.
1436
999b073b
NC		 14372019-05-20 Nick Clifton <nickc@redhat.com>
1438
1439 * po/fr.po: Updated French translation.
1440
14b456f2
AV		 14412019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1442 Michael Collison <michael.collison@arm.com>
1443
1444 * arm-dis.c (thumb32_opcodes): Add new instructions.
1445 (enum mve_instructions): Likewise.
1446 (enum mve_undefined): Add new reasons.
1447 (is_mve_encoding_conflict): Handle new instructions.
1448 (is_mve_undefined): Likewise.
1449 (is_mve_unpredictable): Likewise.
1450 (print_mve_undefined): Likewise.
1451 (print_mve_size): Likewise.
1452
f49bb598
AV		 14532019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1454 Michael Collison <michael.collison@arm.com>
1455
1456 * arm-dis.c (thumb32_opcodes): Add new instructions.
1457 (enum mve_instructions): Likewise.
1458 (is_mve_encoding_conflict): Handle new instructions.
1459 (is_mve_undefined): Likewise.
1460 (is_mve_unpredictable): Likewise.
1461 (print_mve_size): Likewise.
1462
56858bea
AV		 14632019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1464 Michael Collison <michael.collison@arm.com>
1465
1466 * arm-dis.c (thumb32_opcodes): Add new instructions.
1467 (enum mve_instructions): Likewise.
1468 (is_mve_encoding_conflict): Likewise.
1469 (is_mve_unpredictable): Likewise.
1470 (print_mve_size): Likewise.
1471
e523f101
AV		 14722019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1473 Michael Collison <michael.collison@arm.com>
1474
1475 * arm-dis.c (thumb32_opcodes): Add new instructions.
1476 (enum mve_instructions): Likewise.
1477 (is_mve_encoding_conflict): Handle new instructions.
1478 (is_mve_undefined): Likewise.
1479 (is_mve_unpredictable): Likewise.
1480 (print_mve_size): Likewise.
1481
66dcaa5d
AV		 14822019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1483 Michael Collison <michael.collison@arm.com>
1484
1485 * arm-dis.c (thumb32_opcodes): Add new instructions.
1486 (enum mve_instructions): Likewise.
1487 (is_mve_encoding_conflict): Handle new instructions.
1488 (is_mve_undefined): Likewise.
1489 (is_mve_unpredictable): Likewise.
1490 (print_mve_size): Likewise.
1491 (print_insn_mve): Likewise.
1492
d052b9b7
AV		 14932019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1494 Michael Collison <michael.collison@arm.com>
1495
1496 * arm-dis.c (thumb32_opcodes): Add new instructions.
1497 (print_insn_thumb32): Handle new instructions.
1498
ed63aa17
AV		 14992019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1500 Michael Collison <michael.collison@arm.com>
1501
1502 * arm-dis.c (enum mve_instructions): Add new instructions.
1503 (enum mve_undefined): Add new reasons.
1504 (is_mve_encoding_conflict): Handle new instructions.
1505 (is_mve_undefined): Likewise.
1506 (is_mve_unpredictable): Likewise.
1507 (print_mve_undefined): Likewise.
1508 (print_mve_size): Likewise.
1509 (print_mve_shift_n): Likewise.
1510 (print_insn_mve): Likewise.
1511
897b9bbc
AV		 15122019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1513 Michael Collison <michael.collison@arm.com>
1514
1515 * arm-dis.c (enum mve_instructions): Add new instructions.
1516 (is_mve_encoding_conflict): Handle new instructions.
1517 (is_mve_unpredictable): Likewise.
1518 (print_mve_rotate): Likewise.
1519 (print_mve_size): Likewise.
1520 (print_insn_mve): Likewise.
1521
1c8f2df8
AV		 15222019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1523 Michael Collison <michael.collison@arm.com>
1524
1525 * arm-dis.c (enum mve_instructions): Add new instructions.
1526 (is_mve_encoding_conflict): Handle new instructions.
1527 (is_mve_unpredictable): Likewise.
1528 (print_mve_size): Likewise.
1529 (print_insn_mve): Likewise.
1530
d3b63143
AV		 15312019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1532 Michael Collison <michael.collison@arm.com>
1533
1534 * arm-dis.c (enum mve_instructions): Add new instructions.
1535 (enum mve_undefined): Add new reasons.
1536 (is_mve_encoding_conflict): Handle new instructions.
1537 (is_mve_undefined): Likewise.
1538 (is_mve_unpredictable): Likewise.
1539 (print_mve_undefined): Likewise.
1540 (print_mve_size): Likewise.
1541 (print_insn_mve): Likewise.
1542
14925797
AV		 15432019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1544 Michael Collison <michael.collison@arm.com>
1545
1546 * arm-dis.c (enum mve_instructions): Add new instructions.
1547 (is_mve_encoding_conflict): Handle new instructions.
1548 (is_mve_undefined): Likewise.
1549 (is_mve_unpredictable): Likewise.
1550 (print_mve_size): Likewise.
1551 (print_insn_mve): Likewise.
1552
c507f10b
AV		 15532019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1554 Michael Collison <michael.collison@arm.com>
1555
1556 * arm-dis.c (enum mve_instructions): Add new instructions.
1557 (enum mve_unpredictable): Add new reasons.
1558 (enum mve_undefined): Likewise.
1559 (is_mve_okay_in_it): Handle new isntructions.
1560 (is_mve_encoding_conflict): Likewise.
1561 (is_mve_undefined): Likewise.
1562 (is_mve_unpredictable): Likewise.
1563 (print_mve_vmov_index): Likewise.
1564 (print_simd_imm8): Likewise.
1565 (print_mve_undefined): Likewise.
1566 (print_mve_unpredictable): Likewise.
1567 (print_mve_size): Likewise.
1568 (print_insn_mve): Likewise.
1569
bf0b396d
AV		 15702019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1571 Michael Collison <michael.collison@arm.com>
1572
1573 * arm-dis.c (enum mve_instructions): Add new instructions.
1574 (enum mve_unpredictable): Add new reasons.
1575 (enum mve_undefined): Likewise.
1576 (is_mve_encoding_conflict): Handle new instructions.
1577 (is_mve_undefined): Likewise.
1578 (is_mve_unpredictable): Likewise.
1579 (print_mve_undefined): Likewise.
1580 (print_mve_unpredictable): Likewise.
1581 (print_mve_rounding_mode): Likewise.
1582 (print_mve_vcvt_size): Likewise.
1583 (print_mve_size): Likewise.
1584 (print_insn_mve): Likewise.
1585
ef1576a1
AV		 15862019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1587 Michael Collison <michael.collison@arm.com>
1588
1589 * arm-dis.c (enum mve_instructions): Add new instructions.
1590 (enum mve_unpredictable): Add new reasons.
1591 (enum mve_undefined): Likewise.
1592 (is_mve_undefined): Handle new instructions.
1593 (is_mve_unpredictable): Likewise.
1594 (print_mve_undefined): Likewise.
1595 (print_mve_unpredictable): Likewise.
1596 (print_mve_size): Likewise.
1597 (print_insn_mve): Likewise.
1598
aef6d006
AV		 15992019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1600 Michael Collison <michael.collison@arm.com>
1601
1602 * arm-dis.c (enum mve_instructions): Add new instructions.
1603 (enum mve_undefined): Add new reasons.
1604 (insns): Add new instructions.
1605 (is_mve_encoding_conflict):
1606 (print_mve_vld_str_addr): New print function.
1607 (is_mve_undefined): Handle new instructions.
1608 (is_mve_unpredictable): Likewise.
1609 (print_mve_undefined): Likewise.
1610 (print_mve_size): Likewise.
1611 (print_insn_coprocessor_1): Handle MVE VLDR, VSTR instructions.
1612 (print_insn_mve): Handle new operands.
1613
04d54ace
AV		 16142019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1615 Michael Collison <michael.collison@arm.com>
1616
1617 * arm-dis.c (enum mve_instructions): Add new instructions.
1618 (enum mve_unpredictable): Add new reasons.
1619 (is_mve_encoding_conflict): Handle new instructions.
1620 (is_mve_unpredictable): Likewise.
1621 (mve_opcodes): Add new instructions.
1622 (print_mve_unpredictable): Handle new reasons.
1623 (print_mve_register_blocks): New print function.
1624 (print_mve_size): Handle new instructions.
1625 (print_insn_mve): Likewise.
1626
9743db03
AV		 16272019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1628 Michael Collison <michael.collison@arm.com>
1629
1630 * arm-dis.c (enum mve_instructions): Add new instructions.
1631 (enum mve_unpredictable): Add new reasons.
1632 (enum mve_undefined): Likewise.
1633 (is_mve_encoding_conflict): Handle new instructions.
1634 (is_mve_undefined): Likewise.
1635 (is_mve_unpredictable): Likewise.
1636 (coprocessor_opcodes): Move NEON VDUP from here...
1637 (neon_opcodes): ... to here.
1638 (mve_opcodes): Add new instructions.
1639 (print_mve_undefined): Handle new reasons.
1640 (print_mve_unpredictable): Likewise.
1641 (print_mve_size): Handle new instructions.
1642 (print_insn_neon): Handle vdup.
1643 (print_insn_mve): Handle new operands.
1644
143275ea
AV		 16452019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1646 Michael Collison <michael.collison@arm.com>
1647
1648 * arm-dis.c (enum mve_instructions): Add new instructions.
1649 (enum mve_unpredictable): Add new values.
1650 (mve_opcodes): Add new instructions.
1651 (vec_condnames): New array with vector conditions.
1652 (mve_predicatenames): New array with predicate suffixes.
1653 (mve_vec_sizename): New array with vector sizes.
1654 (enum vpt_pred_state): New enum with vector predication states.
1655 (struct vpt_block): New struct type for vpt blocks.
1656 (vpt_block_state): Global struct to keep track of state.
1657 (mve_extract_pred_mask): New helper function.
1658 (num_instructions_vpt_block): Likewise.
1659 (mark_outside_vpt_block): Likewise.
1660 (mark_inside_vpt_block): Likewise.
1661 (invert_next_predicate_state): Likewise.
1662 (update_next_predicate_state): Likewise.
1663 (update_vpt_block_state): Likewise.
1664 (is_vpt_instruction): Likewise.
1665 (is_mve_encoding_conflict): Add entries for new instructions.
1666 (is_mve_unpredictable): Likewise.
1667 (print_mve_unpredictable): Handle new cases.
1668 (print_instruction_predicate): Likewise.
1669 (print_mve_size): New function.
1670 (print_vec_condition): New function.
1671 (print_insn_mve): Handle vpt blocks and new print operands.
1672
f08d8ce3
AV		 16732019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1674
1675 * arm-dis.c (print_insn_coprocessor_1): Disable the use of coprocessors
1676 8, 14 and 15 for Armv8.1-M Mainline.
1677
73cd51e5
AV		 16782019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1679 Michael Collison <michael.collison@arm.com>
1680
1681 * arm-dis.c (enum mve_instructions): New enum.
1682 (enum mve_unpredictable): Likewise.
1683 (enum mve_undefined): Likewise.
1684 (struct mopcode32): New struct.
1685 (is_mve_okay_in_it): New function.
1686 (is_mve_architecture): Likewise.
1687 (arm_decode_field): Likewise.
1688 (arm_decode_field_multiple): Likewise.
1689 (is_mve_encoding_conflict): Likewise.
1690 (is_mve_undefined): Likewise.
1691 (is_mve_unpredictable): Likewise.
1692 (print_mve_undefined): Likewise.
1693 (print_mve_unpredictable): Likewise.
1694 (print_insn_coprocessor_1): Use arm_decode_field_multiple.
1695 (print_insn_mve): New function.
1696 (print_insn_thumb32): Handle MVE architecture.
1697 (select_arm_features): Force thumb for Armv8.1-m Mainline.
1698
3076e594
NC		 16992019-05-10 Nick Clifton <nickc@redhat.com>
1700
1701 PR 24538
1702 * ia64-opc.c (ia64_find_matching_opcode): Check for reaching the
1703 end of the table prematurely.
1704
387e7624
FS		 17052019-05-10 Faraz Shahbazker <fshahbazker@wavecomp.com>
1706
1707 * mips-opc.c (mips_opcodes): Enable ADD, SUB, DADD and DSUB
1708 macros for R6.
1709
0067be51
AM		 17102019-05-11 Alan Modra <amodra@gmail.com>
1711
1712 * ppc-dis.c (print_insn_powerpc) Don't skip optional operands
1713 when -Mraw is in effect.
1714
42e6288f
MM		 17152019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1716
1717 * aarch64-dis-2.c: Regenerate.
1718 * aarch64-tbl.h (OP_SVE_BBU): New variant set.
1719 (OP_SVE_BBB): New variant set.
1720 (OP_SVE_DDDD): New variant set.
1721 (OP_SVE_HHH): New variant set.
1722 (OP_SVE_HHHU): New variant set.
1723 (OP_SVE_SSS): New variant set.
1724 (OP_SVE_SSSU): New variant set.
1725 (OP_SVE_SHH): New variant set.
1726 (OP_SVE_SBBU): New variant set.
1727 (OP_SVE_DSS): New variant set.
1728 (OP_SVE_DHHU): New variant set.
1729 (OP_SVE_VMV_HSD_BHS): New variant set.
1730 (OP_SVE_VVU_HSD_BHS): New variant set.
1731 (OP_SVE_VVVU_SD_BH): New variant set.
1732 (OP_SVE_VVVU_BHSD): New variant set.
1733 (OP_SVE_VVV_QHD_DBS): New variant set.
1734 (OP_SVE_VVV_HSD_BHS): New variant set.
1735 (OP_SVE_VVV_HSD_BHS2): New variant set.
1736 (OP_SVE_VVV_BHS_HSD): New variant set.
1737 (OP_SVE_VV_BHS_HSD): New variant set.
1738 (OP_SVE_VVV_SD): New variant set.
1739 (OP_SVE_VVU_BHS_HSD): New variant set.
1740 (OP_SVE_VZVV_SD): New variant set.
1741 (OP_SVE_VZVV_BH): New variant set.
1742 (OP_SVE_VZV_SD): New variant set.
1743 (aarch64_opcode_table): Add sve2 instructions.
1744
28ed815a
MM		 17452019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1746
1747 * aarch64-asm-2.c: Regenerated.
1748 * aarch64-dis-2.c: Regenerated.
1749 * aarch64-opc-2.c: Regenerated.
1750 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1751 for SVE_SHLIMM_UNPRED_22.
1752 (aarch64_print_operand): Add printing for SVE_SHLIMM_UNPRED_22.
1753 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHLIMM_UNPRED_22
1754 operand.
1755
fd1dc4a0
MM		 17562019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1757
1758 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1759 sve_size_tsz_bhs iclass encode.
1760 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1761 sve_size_tsz_bhs iclass decode.
1762
31e36ab3
MM		 17632019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1764
1765 * aarch64-asm-2.c: Regenerated.
1766 * aarch64-dis-2.c: Regenerated.
1767 * aarch64-opc-2.c: Regenerated.
1768 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1769 for SVE_Zm4_11_INDEX.
1770 (aarch64_print_operand): Add printing for SVE_Zm4_11_INDEX.
1771 (fields): Handle SVE_i2h field.
1772 * aarch64-opc.h (enum aarch64_field_kind): New SVE_i2h field.
1773 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm4_11_INDEX operand.
1774
1be5f94f
MM		 17752019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1776
1777 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1778 sve_shift_tsz_bhsd iclass encode.
1779 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1780 sve_shift_tsz_bhsd iclass decode.
1781
3c17238b
MM		 17822019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1783
1784 * aarch64-asm-2.c: Regenerated.
1785 * aarch64-dis-2.c: Regenerated.
1786 * aarch64-opc-2.c: Regenerated.
1787 * aarch64-asm.c (aarch64_ins_sve_shrimm):
1788 (aarch64_encode_variant_using_iclass): Handle
1789 sve_shift_tsz_hsd iclass encode.
1790 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1791 sve_shift_tsz_hsd iclass decode.
1792 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1793 for SVE_SHRIMM_UNPRED_22.
1794 (aarch64_print_operand): Add printing for SVE_SHRIMM_UNPRED_22.
1795 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHRIMM_UNPRED_22
1796 operand.
1797
cd50a87a
MM		 17982019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1799
1800 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1801 sve_size_013 iclass encode.
1802 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1803 sve_size_013 iclass decode.
1804
3c705960
MM		 18052019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1806
1807 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1808 sve_size_bh iclass encode.
1809 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1810 sve_size_bh iclass decode.
1811
0a57e14f
MM		 18122019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1813
1814 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1815 sve_size_sd2 iclass encode.
1816 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1817 sve_size_sd2 iclass decode.
1818 * aarch64-opc.c (fields): Handle SVE_sz2 field.
1819 * aarch64-opc.h (enum aarch64_field_kind): New SVE_sz2 field.
1820
c469c864
MM		 18212019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1822
1823 * aarch64-asm-2.c: Regenerated.
1824 * aarch64-dis-2.c: Regenerated.
1825 * aarch64-opc-2.c: Regenerated.
1826 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1827 for SVE_ADDR_ZX.
1828 (aarch64_print_operand): Add printing for SVE_ADDR_ZX.
1829 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_ADDR_ZX operand.
1830
116adc27
MM		 18312019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1832
1833 * aarch64-asm-2.c: Regenerated.
1834 * aarch64-dis-2.c: Regenerated.
1835 * aarch64-opc-2.c: Regenerated.
1836 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1837 for SVE_Zm3_11_INDEX.
1838 (aarch64_print_operand): Add printing for SVE_Zm3_11_INDEX.
1839 (fields): Handle SVE_i3l and SVE_i3h2 fields.
1840 * aarch64-opc.h (enum aarch64_field_kind): New SVE_i3l and SVE_i3h2
1841 fields.
1842 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm3_11_INDEX operand.
1843
3bd82c86
MM		 18442019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1845
1846 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1847 sve_size_hsd2 iclass encode.
1848 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1849 sve_size_hsd2 iclass decode.
1850 * aarch64-opc.c (fields): Handle SVE_size field.
1851 * aarch64-opc.h (enum aarch64_field_kind): New SVE_size field.
1852
adccc507
MM		 18532019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1854
1855 * aarch64-asm-2.c: Regenerated.
1856 * aarch64-dis-2.c: Regenerated.
1857 * aarch64-opc-2.c: Regenerated.
1858 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1859 for SVE_IMM_ROT3.
1860 (aarch64_print_operand): Add printing for SVE_IMM_ROT3.
1861 (fields): Handle SVE_rot3 field.
1862 * aarch64-opc.h (enum aarch64_field_kind): New SVE_rot3 field.
1863 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_IMM_ROT3 operand.
1864
5cd99750
MM		 18652019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1866
1867 * aarch64-opc.c (verify_constraints): Check for movprfx for sve2
1868 instructions.
1869
7ce2460a
MM		 18702019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1871
1872 * aarch64-tbl.h
1873 (aarch64_feature_sve2, aarch64_feature_sve2aes,
1874 aarch64_feature_sve2sha3, aarch64_feature_sve2sm4,
1875 aarch64_feature_sve2bitperm): New feature sets.
1876 (SVE2, SVE2_AES, SVE2_SHA3, SVE2_SM4, SVE2_BITPERM): New macros
1877 for feature set addresses.
1878 (SVE2_INSN, SVE2_INSNC, SVE2AES_INSN, SVE2SHA3_INSN,
1879 SVE2SM4_INSN, SVE2SM4_INSNC, SVE2BITPERM_INSN): New macros.
1880
41cee089
FS		 18812019-05-06 Andrew Bennett <andrew.bennett@imgtec.com>
1882 Faraz Shahbazker <fshahbazker@wavecomp.com>
1883
1884 * mips-dis.c (mips_calculate_combination_ases): Add ISA
1885 argument and set ASE_EVA_R6 appropriately.
1886 (set_default_mips_dis_options): Pass ISA to above.
1887 (parse_mips_dis_option): Likewise.
1888 * mips-opc.c (EVAR6): New macro.
1889 (mips_builtin_opcodes): Add llwpe, scwpe.
1890
b83b4b13
SD		 18912019-05-01 Sudakshina Das <sudi.das@arm.com>
1892
1893 * aarch64-asm-2.c: Regenerated.
1894 * aarch64-dis-2.c: Regenerated.
1895 * aarch64-opc-2.c: Regenerated.
1896 * aarch64-opc.c (operand_general_constraint_met_p): Add case for
1897 AARCH64_OPND_TME_UIMM16.
1898 (aarch64_print_operand): Likewise.
1899 * aarch64-tbl.h (QL_IMM_NIL): New.
1900 (TME): New.
1901 (_TME_INSN): New.
1902 (struct aarch64_opcode): Add tstart, tcommit, ttest and tcancel.
1903
4a90ce95
JD		 19042019-04-29 John Darrington <john@darrington.wattle.id.au>
1905
1906 * s12z-opc.c (shift_discrim): Return OP_INVALID when reading fails.
1907
a45328b9
AB		 19082019-04-26 Andrew Bennett <andrew.bennett@imgtec.com>
1909 Faraz Shahbazker <fshahbazker@wavecomp.com>
1910
1911 * mips-opc.c (mips_builtin_opcodes): Add llwp, lldp, scwp, scdp.
1912
d10be0cb
JD		 19132019-04-24 John Darrington <john@darrington.wattle.id.au>
1914
1915 * s12z-opc.h: Add extern "C" bracketing to help
1916 users who wish to use this interface in c++ code.
1917
a679f24e
JD		 19182019-04-24 John Darrington <john@darrington.wattle.id.au>
1919
1920 * s12z-opc.c (bm_decode): Handle bit map operations with the
1921 "reserved0" mode.
1922
32c36c3c
AV		 19232019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
1924
1925 * arm-dis.c (coprocessor_opcodes): Document new %J and %K format
1926 specifier. Add entries for VLDR and VSTR of system registers.
1927 (print_insn_coprocessor): Forbid coprocessor numbers 8, 14 and 15 in
1928 coprocessor instructions on Armv8.1-M Mainline targets. Add handling
1929 of %J and %K format specifier.
1930
efd6b359
AV		 19312019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
1932
1933 * arm-dis.c (coprocessor_opcodes): Document new %C format control code.
1934 Add new entries for VSCCLRM instruction.
1935 (print_insn_coprocessor): Handle new %C format control code.
1936
6b0dd094
AV		 19372019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
1938
1939 * arm-dis.c (enum isa): New enum.
1940 (struct sopcode32): New structure.
1941 (coprocessor_opcodes): change type of entries to struct sopcode32 and
1942 set isa field of all current entries to ANY.
1943 (print_insn_coprocessor): Change type of insn to struct sopcode32.
1944 Only match an entry if its isa field allows the current mode.
1945
4b5a202f
AV		 19462019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
1947
1948 * arm-dis.c (thumb_opcodes): Document %n control code. Add entry for
1949 CLRM.
1950 (print_insn_thumb32): Add logic to print %n CLRM register list.
1951
60f993ce
AV		 19522019-04-15 Sudakshina Das <sudi.das@arm.com>
1953
1954 * arm-dis.c (print_insn_thumb32): Updated to accept new %P
1955 and %Q patterns.
1956
f6b2b12d
AV		 19572019-04-15 Sudakshina Das <sudi.das@arm.com>
1958
1959 * arm-dis.c (thumb32_opcodes): New instruction bfcsel.
1960 (print_insn_thumb32): Edit the switch case for %Z.
1961
1889da70
AV		 19622019-04-15 Sudakshina Das <sudi.das@arm.com>
1963
1964 * arm-dis.c (print_insn_thumb32): Updated to accept new %Z pattern.
1965
65d1bc05
AV		 19662019-04-15 Sudakshina Das <sudi.das@arm.com>
1967
1968 * arm-dis.c (thumb32_opcodes): New instruction bfl.
1969
1caf72a5
AV		 19702019-04-15 Sudakshina Das <sudi.das@arm.com>
1971
1972 * arm-dis.c (print_insn_thumb32): Updated to accept new %Y pattern.
1973
f1c7f421
AV		 19742019-04-15 Sudakshina Das <sudi.das@arm.com>
1975
1976 * arm-dis.c (print_insn_thumb32): Add '%<bitfield>S' to print an
1977 Arm register with r13 and r15 unpredictable.
1978 (thumb32_opcodes): New instructions for bfx and bflx.
1979
4389b29a
AV		 19802019-04-15 Sudakshina Das <sudi.das@arm.com>
1981
1982 * arm-dis.c (thumb32_opcodes): New instructions for bf.
1983
e5d6e09e
AV		 19842019-04-15 Sudakshina Das <sudi.das@arm.com>
1985
1986 * arm-dis.c (print_insn_thumb32): Updated to accept new %W pattern.
1987
e12437dc
AV		 19882019-04-15 Sudakshina Das <sudi.das@arm.com>
1989
1990 * arm-dis.c (print_insn_thumb32): Updated to accept new %G pattern.
1991
031254f2
AV		 19922019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
1993
1994 * arm-dis.c (select_arm_features): Add logic for Armv8.1-M Mainline.
1995
e5a557ac
JD		 19962019-04-12 John Darrington <john@darrington.wattle.id.au>
1997
1998 s12z-dis.c, s12z-opc.c, s12z-opc.h: Replace "operator" with
1999 "optr". ("operator" is a reserved word in c++).
2000
bd7ceb8d
SD		 20012019-04-11 Sudakshina Das <sudi.das@arm.com>
2002
2003 * aarch64-opc.c (aarch64_print_operand): Add case for
2004 AARCH64_OPND_Rt_SP.
2005 (verify_constraints): Likewise.
2006 * aarch64-tbl.h (QL_LDST_AT): Update to add SP qualifier.
2007 (struct aarch64_opcode): Update stg, stzg, st2g, stz2g instructions
2008 to accept Rt|SP as first operand.
2009 (AARCH64_OPERANDS): Add new Rt_SP.
2010 * aarch64-asm-2.c: Regenerated.
2011 * aarch64-dis-2.c: Regenerated.
2012 * aarch64-opc-2.c: Regenerated.
2013
e54010f1
SD		 20142019-04-11 Sudakshina Das <sudi.das@arm.com>
2015
2016 * aarch64-asm-2.c: Regenerated.
2017 * aarch64-dis-2.c: Likewise.
2018 * aarch64-opc-2.c: Likewise.
2019 * aarch64-tbl.h (aarch64_opcode): Add new ldgm and stgm.
2020
7e96e219
RS		 20212019-04-09 Robert Suchanek <robert.suchanek@mips.com>
2022
2023 * mips-opc.c (mips_builtin_opcodes): Add RDHWR rt rd sel.
2024
6f2791d5
L		 20252019-04-08 H.J. Lu <hongjiu.lu@intel.com>
2026
2027 * i386-opc.tbl: Consolidate AVX512 BF16 entries.
2028 * i386-init.h: Regenerated.
2029
e392bad3
AM		 20302019-04-07 Alan Modra <amodra@gmail.com>
2031
2032 * ppc-dis.c (print_insn_powerpc): Use a tiny state machine
2033 op_separator to control printing of spaces, comma and parens
2034 rather than need_comma, need_paren and spaces vars.
2035
dffaa15c
AM		 20362019-04-07 Alan Modra <amodra@gmail.com>
2037
2038 PR 24421
2039 * arm-dis.c (print_insn_coprocessor): Correct bracket placement.
2040 (print_insn_neon, print_insn_arm): Likewise.
2041
d6aab7a1
XG		 20422019-04-05 Xuepeng Guo <xuepeng.guo@intel.com>
2043
2044 * i386-dis-evex.h (evex_table): Updated to support BF16
2045 instructions.
2046 * i386-dis.c (enum): Add EVEX_W_0F3852_P_1, EVEX_W_0F3872_P_1
2047 and EVEX_W_0F3872_P_3.
2048 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_BF16_FLAGS.
2049 (cpu_flags): Add bitfield for CpuAVX512_BF16.
2050 * i386-opc.h (enum): Add CpuAVX512_BF16.
2051 (i386_cpu_flags): Add bitfield for cpuavx512_bf16.
2052 * i386-opc.tbl: Add AVX512 BF16 instructions.
2053 * i386-init.h: Regenerated.
2054 * i386-tbl.h: Likewise.
2055
66e85460
AM		 20562019-04-05 Alan Modra <amodra@gmail.com>
2057
2058 * ppc-opc.c (XLBH_MASK): Subtract off BH field from BB_MASK.
2059 (powerpc_opcodes): Reorder bcctr and bclr extended mnemonics
2060 to favour printing of "-" branch hint when using the "y" bit.
2061 Allow BH field on bc{ctr,lr,tar}{,l}{-,+}.
2062
c2b1c275
AM		 20632019-04-05 Alan Modra <amodra@gmail.com>
2064
2065 * ppc-dis.c (print_insn_powerpc): Delay printing spaces after
2066 opcode until first operand is output.
2067
aae9718e
PB		 20682019-04-04 Peter Bergner <bergner@linux.ibm.com>
2069
2070 PR gas/24349
2071 * ppc-opc.c (valid_bo_pre_v2): Add comments.
2072 (valid_bo_post_v2): Add support for 'at' branch hints.
2073 (insert_bo): Only error on branch on ctr.
2074 (get_bo_hint_mask): New function.
2075 (insert_boe): Add new 'branch_taken' formal argument. Add support
2076 for inserting 'at' branch hints.
2077 (extract_boe): Add new 'branch_taken' formal argument. Add support
2078 for extracting 'at' branch hints.
2079 (insert_bom, extract_bom, insert_bop, extract_bop): New functions.
2080 (BOE): Delete operand.
2081 (BOM, BOP): New operands.
2082 (RM): Update value.
2083 (XLYLK, XLYLK_MASK, XLYBB_MASK): Delete.
2084 (powerpc_opcodes) <bc-, bcl-, bca-, bcla-, bclr-, bclrl-, bcctr-,
2085 bcctrl-, bctar-, bctarl->: Replace BOE with BOM.
2086 (powerpc_opcodes) <bc+, bcl+, bca+, bcla+, bclr+, bclrl+, bcctr+,
2087 bcctrl+, bctar+, bctarl+>: Replace BOE with BOP.
2088 <bdnztar, bdnztarl, bdztar, bdztarl, btar, btarl, bdnztar-, bdnztarl-,
2089 bdnztar+, bdnztarl+, bdztar-, bdztarl-, bdztar+, bdztarl+, bgetar,
2090 bnltar, bgetarl, bnltarl, bletar, bngtar, bletarl, bngtarl, bnetar,
2091 bnetarl, bnstar, bnutar, bnstarl, bnutarl, bgetar-, bnltar-, bgetarl-,
2092 bnltarl-, bletar-, bngtar-, bletarl-, bngtarl-, bnetar-, bnetarl-,
2093 bnstar-, bnutar-, bnstarl-, bnutarl-, bgetar+, bnltar+, bgetarl+,
2094 bnltarl+, bletar+, bngtar+, bletarl+, bngtarl+, bnetar+, bnetarl+,
2095 bnstar+, bnutar+, bnstarl+, bnutarl+, blttar, blttarl, bgttar, bgttarl,
2096 beqtar, beqtarl, bsotar, buntar, bsotarl, buntarl, blttar-, blttarl-,
2097 bgttar-, bgttarl-, beqtar-, beqtarl-, bsotar-, buntar-, bsotarl-,
2098 buntarl-, blttar+, blttarl+, bgttar+, bgttarl+, beqtar+, beqtarl+,
2099 bsotar+, buntar+, bsotarl+, buntarl+, bdnzftar, bdnzftarl, bdzftar,
2100 bdzftarl, bftar, bftarl, bftar-, bftarl-, bftar+, bftarl+, bdnzttar,
2101 bdnzttarl, bdzttar, bdzttarl, bttar, bttarl, bttar-, bttarl-, bttar+,
2102 bttarl+>: New extended mnemonics.
2103
96a86c01
AM		 21042019-03-28 Alan Modra <amodra@gmail.com>
2105
2106 PR 24390
2107 * ppc-opc.c (BTF): Define.
2108 (powerpc_opcodes): Use for mtfsb*.
2109 * ppc-dis.c (print_insn_powerpc): Print fields with both
2110 PPC_OPERAND_CR_REG and PPC_OPERAND_CR_BIT as a plain number.
2111
796d6298
TC		 21122019-03-25 Tamar Christina <tamar.christina@arm.com>
2113
2114 * arm-dis.c (struct arm_private_data): Remove has_mapping_symbols.
2115 (mapping_symbol_for_insn): Implement new algorithm.
2116 (print_insn): Remove duplicate code.
2117
60df3720
TC		 21182019-03-25 Tamar Christina <tamar.christina@arm.com>
2119
2120 * aarch64-dis.c (print_insn_aarch64):
2121 Implement override.
2122
51457761
TC		 21232019-03-25 Tamar Christina <tamar.christina@arm.com>
2124
2125 * aarch64-dis.c (print_insn_aarch64): Update the mapping symbol search
2126 order.
2127
53b2f36b
TC		 21282019-03-25 Tamar Christina <tamar.christina@arm.com>
2129
2130 * aarch64-dis.c (last_stop_offset): New.
2131 (print_insn_aarch64): Use stop_offset.
2132
89199bb5
L		 21332019-03-19 H.J. Lu <hongjiu.lu@intel.com>
2134
2135 PR gas/24359
2136 * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS to
2137 CPU_ANY_AVX2_FLAGS.
2138 * i386-init.h: Regenerated.
2139
97ed31ae
L		 21402019-03-18 H.J. Lu <hongjiu.lu@intel.com>
2141
2142 PR gas/24348
2143 * i386-opc.tbl: Add Optimize to vmovdqa32, vmovdqa64, vmovdqu8,
2144 vmovdqu16, vmovdqu32 and vmovdqu64.
2145 * i386-tbl.h: Regenerated.
2146
0919bfe9
AK		 21472019-03-12 Andreas Krebbel <krebbel@linux.ibm.com>
2148
2149 * s390-opc.txt: Rename selhhhr to selfhr. Remove optional operand
2150 from vstrszb, vstrszh, and vstrszf.
2151
21522019-03-12 Andreas Krebbel <krebbel@linux.ibm.com>
2153
2154 * s390-opc.txt: Add instruction descriptions.
2155
21820ebe
JW		 21562019-02-08 Jim Wilson <jimw@sifive.com>
2157
2158 * riscv-opc.c (riscv_opcodes) <beq>: Use Cz to compress 3 operand form.
2159 <bne>: Likewise.
2160
f7dd2fb2
TC		 21612019-02-07 Tamar Christina <tamar.christina@arm.com>
2162
2163 * arm-dis.c (arm_opcodes): Redefine hlt to armv1.
2164
6456d318
TC		 21652019-02-07 Tamar Christina <tamar.christina@arm.com>
2166
2167 PR binutils/23212
2168 * aarch64-opc.h (enum aarch64_field_kind): Add FLD_sz.
2169 * aarch64-opc.c (verify_elem_sd): New.
2170 (fields): Add FLD_sz entr.
2171 * aarch64-tbl.h (_SIMD_INSN): New.
2172 (aarch64_opcode_table): Add elem_sd verifier to fmla, fmls, fmul and
2173 fmulx scalar and vector by element isns.
2174
4a83b610
NC		 21752019-02-07 Nick Clifton <nickc@redhat.com>
2176
2177 * po/sv.po: Updated Swedish translation.
2178
fc60b8c8
AK		 21792019-01-31 Andreas Krebbel <krebbel@linux.ibm.com>
2180
2181 * s390-mkopc.c (main): Accept arch13 as cpu string.
2182 * s390-opc.c: Add new instruction formats and instruction opcode
2183 masks.
2184 * s390-opc.txt: Add new arch13 instructions.
2185
e10620d3
TC		 21862019-01-25 Sudakshina Das <sudi.das@arm.com>
2187
2188 * aarch64-tbl.h (QL_LDST_AT): Update macro.
2189 (aarch64_opcode): Change encoding for stg, stzg
2190 st2g and st2zg.
2191 * aarch64-asm-2.c: Regenerated.
2192 * aarch64-dis-2.c: Regenerated.
2193 * aarch64-opc-2.c: Regenerated.
2194
20a4ca55
SD		 21952019-01-25 Sudakshina Das <sudi.das@arm.com>
2196
2197 * aarch64-asm-2.c: Regenerated.
2198 * aarch64-dis-2.c: Likewise.
2199 * aarch64-opc-2.c: Likewise.
2200 * aarch64-tbl.h (aarch64_opcode): Add new stzgm.
2201
550fd7bf
SD		 22022019-01-25 Sudakshina Das <sudi.das@arm.com>
2203 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
2204
2205 * aarch64-asm.c (aarch64_ins_addr_simple_2): Remove.
2206 * aarch64-asm.h (ins_addr_simple_2): Likeiwse.
2207 * aarch64-dis.c (aarch64_ext_addr_simple_2): Likewise.
2208 * aarch64-dis.h (ext_addr_simple_2): Likewise.
2209 * aarch64-opc.c (operand_general_constraint_met_p): Remove
2210 case for ldstgv_indexed.
2211 (aarch64_print_operand): Remove case for AARCH64_OPND_ADDR_SIMPLE_2.
2212 * aarch64-tbl.h (struct aarch64_opcode): Remove ldgv and stgv.
2213 (AARCH64_OPERANDS): Remove ADDR_SIMPLE_2.
2214 * aarch64-asm-2.c: Regenerated.
2215 * aarch64-dis-2.c: Regenerated.
2216 * aarch64-opc-2.c: Regenerated.
2217
d9938630
NC		 22182019-01-23 Nick Clifton <nickc@redhat.com>
2219
2220 * po/pt_BR.po: Updated Brazilian Portuguese translation.
2221
375cd423
NC		 22222019-01-21 Nick Clifton <nickc@redhat.com>
2223
2224 * po/de.po: Updated German translation.
2225 * po/uk.po: Updated Ukranian translation.
2226
57299f48
CX		 22272019-01-20 Chenghua Xu <paul.hua.gm@gmail.com>
2228 * mips-dis.c (mips_arch_choices): Fix typo in
2229 gs464, gs464e and gs264e descriptors.
2230
f48dfe41
NC		 22312019-01-19 Nick Clifton <nickc@redhat.com>
2232
2233 * configure: Regenerate.
2234 * po/opcodes.pot: Regenerate.
2235
f974f26c
NC		 22362018-06-24 Nick Clifton <nickc@redhat.com>
2237
2238 2.32 branch created.
2239
39f286cd
JD		 22402019-01-09 John Darrington <john@darrington.wattle.id.au>
2241
448b8ca8
JD		 2242 * s12z-dis.c (print_insn_s12z): Do not dereference an operand
2243 if it is null.
2244 -dis.c (opr_emit_disassembly): Do not omit an index if it is
39f286cd
JD		 2245 zero.
2246
3107326d
AP		 22472019-01-09 Andrew Paprocki <andrew@ishiboo.com>
2248
2249 * configure: Regenerate.
2250
7e9ca91e
AM		 22512019-01-07 Alan Modra <amodra@gmail.com>
2252
2253 * configure: Regenerate.
2254 * po/POTFILES.in: Regenerate.
2255
ef1ad42b
JD		 22562019-01-03 John Darrington <john@darrington.wattle.id.au>
2257
2258 * s12z-opc.c: New file.
2259 * s12z-opc.h: New file.
2260 * s12z-dis.c: Removed all code not directly related to display
2261 of instructions. Used the interface provided by the new files
2262 instead.
2263 * Makefile.am (TARGET_LIBOPCODES_CFILES) Add s12z-opc.c.
7e9ca91e 2264 * Makefile.in: Regenerate.
ef1ad42b 2265 * configure.ac (bfd_s12z_arch): Correct the dependencies.
7e9ca91e 2266 * configure: Regenerate.
ef1ad42b 2267
82704155
AM		 22682019-01-01 Alan Modra <amodra@gmail.com>
2269
2270 Update year range in copyright notice of all files.
2271
d5c04e1b 2272For older changes see ChangeLog-2018
3499769a 2273\f
d5c04e1b 2274Copyright (C) 2019 Free Software Foundation, Inc.
3499769a
AM		 2275
2276Copying and distribution of this file, with or without modification,
2277are permitted in any medium without royalty provided the copyright
2278notice and this notice are preserved.
2279
2280Local Variables:
2281mode: change-log
2282left-margin: 8
2283fill-column: 74
2284version-control: never
2285End:
GDB Binutils - Deliverables
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