projects / deliverable / binutils-gdb.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
vax decoding of indexed addressing mode
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
f0090188
AM		 12019-12-19 Alan Modra <amodra@gmail.com>
2
3 * vax-dis.c (print_insn_mode): Stop index mode recursion.
4
1d29ab86
DF		 52019-12-19 Dr N.W. Filardo <nwf20@cam.ac.uk>
6
7 PR 25277
8 * microblaze-opcm.h (enum microblaze_instr): Prefix fadd, fmul and
9 fdiv with "mbi_".
10 * microblaze-opc.h (opcodes): Adjust to suit.
11
2480b6fa
AM		 122019-12-18 Alan Modra <amodra@gmail.com>
13
14 * alpha-opc.c (OP): Avoid signed overflow.
15 * arm-dis.c (print_insn): Likewise.
16 * mcore-dis.c (print_insn_mcore): Likewise.
17 * pj-dis.c (get_int): Likewise.
18 * ppc-opc.c (EBD15, EBD15BI): Likewise.
19 * score7-dis.c (s7_print_insn): Likewise.
20 * tic30-dis.c (print_insn_tic30): Likewise.
21 * v850-opc.c (insert_SELID): Likewise.
22 * vax-dis.c (print_insn_vax): Likewise.
23 * arc-ext.c (create_map): Likewise.
24 (struct ExtAuxRegister): Make "address" field unsigned int.
25 (arcExtMap_auxRegName): Pass unsigned address.
26 (dump_ARC_extmap): Adjust.
27 * arc-ext.h (arcExtMap_auxRegName): Update prototype.
28
eb7b5046
AM		 292019-12-17 Alan Modra <amodra@gmail.com>
30
31 * visium-dis.c (print_insn_visium): Avoid signed overflow.
32
29298bf6
AM		 332019-12-17 Alan Modra <amodra@gmail.com>
34
35 * aarch64-opc.c (value_fit_signed_field_p): Avoid signed overflow.
36 (value_fit_unsigned_field_p): Likewise.
37 (aarch64_wide_constant_p): Likewise.
38 (operand_general_constraint_met_p): Likewise.
39 * aarch64-opc.h (aarch64_wide_constant_p): Update prototype.
40
e46d79a7
AM		 412019-12-17 Alan Modra <amodra@gmail.com>
42
43 * nds32-dis.c (nds32_mask_opcode): Avoid signed overflow.
44 (print_insn_nds32): Use uint64_t for "given" and "given1".
45
5b660084
AM		 462019-12-17 Alan Modra <amodra@gmail.com>
47
48 * tic80-dis.c: Delete file.
49 * tic80-opc.c: Delete file.
50 * disassemble.c: Remove tic80 support.
51 * disassemble.h: Likewise.
52 * Makefile.am: Likewise.
53 * configure.ac: Likewise.
54 * Makefile.in: Regenerate.
55 * configure: Regenerate.
56 * po/POTFILES.in: Regenerate.
57
62e65990
AM		 582019-12-17 Alan Modra <amodra@gmail.com>
59
60 * bpf-ibld.c: Regenerate.
61
f81e7e2d
AM		 622019-12-16 Alan Modra <amodra@gmail.com>
63
64 * aarch64-dis.c (sign_extend): Return uint64_t. Rewrite without
65 conditional.
66 (aarch64_ext_imm): Avoid signed overflow.
67
488d02fe
AM		 682019-12-16 Alan Modra <amodra@gmail.com>
69
70 * microblaze-dis.c (read_insn_microblaze): Avoid signed overflow.
71
8a92faab
AM		 722019-12-16 Alan Modra <amodra@gmail.com>
73
74 * nios2-dis.c (nios2_print_insn_arg): Avoid signed overflow
75
e6ced26a
AM		 762019-12-16 Alan Modra <amodra@gmail.com>
77
78 * xstormy16-ibld.c: Regenerate.
79
84e098cd
AM		 802019-12-16 Alan Modra <amodra@gmail.com>
81
82 * score-dis.c (print_insn_score16): Move rpush/rpop imm field
83 value adjustment so that it doesn't affect reg field too.
84
36bd8ea7
AM		 852019-12-16 Alan Modra <amodra@gmail.com>
86
87 * crx-dis.c (EXTRACT, SBM): Avoid signed overflow.
88 (get_number_of_operands, getargtype, getbits, getregname),
89 (getcopregname, getprocregname, gettrapstring, getcinvstring),
90 (getregliststring, get_word_at_PC, get_words_at_PC, build_mask),
91 (powerof2, match_opcode, make_instruction, print_arguments),
92 (print_arg): Delete forward declarations, moving static to..
93 (getregname, getcopregname, getregliststring): ..these definitions.
94 (build_mask): Return unsigned int mask.
95 (match_opcode): Use unsigned int vars.
96
cedfc774
AM		 972019-12-16 Alan Modra <amodra@gmail.com>
98
99 * bfin-dis.c (fmtconst, fmtconst_val): Avoid signed overflow.
100
4bdb25fe
AM		 1012019-12-16 Alan Modra <amodra@gmail.com>
102
103 * nds32-dis.c (print_insn16, print_insn32): Remove forward decls.
104 (struct objdump_disasm_info): Delete.
105 (nds32_parse_audio_ext, nds32_parse_opcode): Cast result of
106 N32_IMMS to unsigned before shifting left.
107
cf950fd4
AM		 1082019-12-16 Alan Modra <amodra@gmail.com>
109
110 * moxie-dis.c (INST2OFFSET): Don't left shift a signed value.
111 (print_insn_moxie): Remove unnecessary cast.
112
967354c3
AM		 1132019-12-12 Alan Modra <amodra@gmail.com>
114
115 * csky-dis.c (csky_chars_to_number): Remove abort and unnecessary
116 mask.
117
1d61b032
AM		 1182019-12-11 Alan Modra <amodra@gmail.com>
119
120 * arc-dis.c (BITS): Don't truncate high bits with shifts.
121 * nios2-dis.c (nios2_print_insn_arg): Don't sign extend with shifts.
122 * tic54x-dis.c (print_instruction): Likewise.
123 * tilegx-opc.c (parse_insn_tilegx): Likewise.
124 * tilepro-opc.c (parse_insn_tilepro): Likewise.
125 * visium-dis.c (disassem_class0): Likewise.
126 * pdp11-dis.c (sign_extend): Likewise.
127 (SIGN_BITS): Delete.
128 * epiphany-ibld.c: Regenerate.
129 * lm32-ibld.c: Regenerate.
130 * m32c-ibld.c: Regenerate.
131
5afa80e9
AM		 1322019-12-11 Alan Modra <amodra@gmail.com>
133
134 * ns32k-dis.c (sign_extend): Correct last patch.
135
5c05618a
AM		 1362019-12-11 Alan Modra <amodra@gmail.com>
137
138 * vax-dis.c (NEXTLONG): Avoid signed overflow.
139
2a81ccbb
AM		 1402019-12-11 Alan Modra <amodra@gmail.com>
141
142 * v850-dis.c (get_operand_value): Use unsigned arithmetic. Don't
143 sign extend using shifts.
144
b84f6152
AM		 1452019-12-11 Alan Modra <amodra@gmail.com>
146
147 * tic6x-dis.c (tic6x_extract_32): Avoid signed overflow.
148
66152f16
AM		 1492019-12-11 Alan Modra <amodra@gmail.com>
150
151 * tic4x-dis.c (tic4x_print_register): Formatting. Don't segfault
152 on NULL registertable entry.
153 (tic4x_hash_opcode): Use unsigned arithmetic.
154
205c426a
AM		 1552019-12-11 Alan Modra <amodra@gmail.com>
156
157 * s12z-opc.c (z_decode_signed_value): Avoid signed overflow.
158
fb4cb4e2
AM		 1592019-12-11 Alan Modra <amodra@gmail.com>
160
161 * ns32k-dis.c (bit_extract): Use unsigned arithmetic.
162 (bit_extract_simple, sign_extend): Likewise.
163
96f1f604
AM		 1642019-12-11 Alan Modra <amodra@gmail.com>
165
166 * nios2-dis.c (nios2_print_insn_arg): Use 1u << 31.
167
8c9b4171
AM		 1682019-12-11 Alan Modra <amodra@gmail.com>
169
170 * moxie-dis.c (INST2OFFSET): Don't sign extend using shifts.
171
334175b6
AM		 1722019-12-11 Alan Modra <amodra@gmail.com>
173
174 * m68k-dis.c (COERCE32): Cast value first.
175 (NEXTLONG, NEXTULONG): Avoid signed overflow.
176
f8a87c78
AM		 1772019-12-11 Alan Modra <amodra@gmail.com>
178
179 * h8300-dis.c (extract_immediate): Avoid signed overflow.
180 (bfd_h8_disassemble): Likewise.
181
159653d8
AM		 1822019-12-11 Alan Modra <amodra@gmail.com>
183
184 * d30v-dis.c (print_insn): Make opind unsigned. Don't access
185 past end of operands array.
186
d93bba9e
AM		 1872019-12-11 Alan Modra <amodra@gmail.com>
188
189 * csky-dis.c (csky_chars_to_number): Rewrite. Avoid signed
190 overflow when collecting bytes of a number.
191
c202f69e
AM		 1922019-12-11 Alan Modra <amodra@gmail.com>
193
194 * cris-dis.c (print_with_operands): Avoid signed integer
195 overflow when collecting bytes of a 32-bit integer.
196
0ef562a4
AM		 1972019-12-11 Alan Modra <amodra@gmail.com>
198
199 * cr16-dis.c (EXTRACT, SBM): Rewrite.
200 (cr16_match_opcode): Delete duplicate bcond test.
201
2fd2b153
AM		 2022019-12-11 Alan Modra <amodra@gmail.com>
203
204 * bfin-dis.c (HOST_LONG_WORD_SIZE, XFIELD): Delete.
205 (SIGNBIT): New.
206 (MASKBITS, SIGNEXTEND): Rewrite.
207 (fmtconst): Don't use ? expression now that SIGNEXTEND uses
208 unsigned arithmetic, instead assign result of SIGNEXTEND back
209 to x.
210 (fmtconst_val): Use 1u in shift expression.
211
a11db3e9
AM		 2122019-12-11 Alan Modra <amodra@gmail.com>
213
214 * arc-dis.c (find_format_from_table): Use ull constant when
215 shifting by up to 32.
216
9d48687b
AM		 2172019-12-11 Alan Modra <amodra@gmail.com>
218
219 PR 25270
220 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Return
221 false when field is zero for sve_size_tsz_bhs.
222
b8e61daa
AM		 2232019-12-11 Alan Modra <amodra@gmail.com>
224
225 * epiphany-ibld.c: Regenerate.
226
20135676
AM		 2272019-12-10 Alan Modra <amodra@gmail.com>
228
229 PR 24960
230 * disassemble.c (disassemble_free_target): New function.
231
103ebbc3
AM		 2322019-12-10 Alan Modra <amodra@gmail.com>
233
234 * cgen-dis.in (print_insn_@arch@): Replace insn_sets with private_data.
235 * disassemble.c (disassemble_init_for_target): Likewise.
236 * bpf-dis.c: Regenerate.
237 * epiphany-dis.c: Regenerate.
238 * fr30-dis.c: Regenerate.
239 * frv-dis.c: Regenerate.
240 * ip2k-dis.c: Regenerate.
241 * iq2000-dis.c: Regenerate.
242 * lm32-dis.c: Regenerate.
243 * m32c-dis.c: Regenerate.
244 * m32r-dis.c: Regenerate.
245 * mep-dis.c: Regenerate.
246 * mt-dis.c: Regenerate.
247 * or1k-dis.c: Regenerate.
248 * xc16x-dis.c: Regenerate.
249 * xstormy16-dis.c: Regenerate.
250
6f0e0752
AM		 2512019-12-10 Alan Modra <amodra@gmail.com>
252
253 * ppc-dis.c (private): Delete variable.
254 (get_powerpc_dialect): Don't segfault on NULL info->private_data.
255 (powerpc_init_dialect): Don't use global private.
256
e7c22a69
AM		 2572019-12-10 Alan Modra <amodra@gmail.com>
258
259 * s12z-opc.c: Formatting.
260
0a6aef6b
AM		 2612019-12-08 Alan Modra <amodra@gmail.com>
262
263 * s12z-opc.c (exg_sex_discrim): Don't leak memory on invalid
264 registers.
265
2dc4b12f
JB		 2662019-12-05 Jan Beulich <jbeulich@suse.com>
267
268 * aarch64-tbl.h (aarch64_feature_crypto,
269 aarch64_feature_crypto_v8_2, CRYPTO, CRYPTO_V8_2, CRYP_INSN,
270 CRYPTO_V8_2_INSN): Delete.
271
378fd436
AM		 2722019-12-05 Alan Modra <amodra@gmail.com>
273
274 PR 25249
275 * microblaze-dis.c (NUM_STRBUFS, STRBUF_SIZE): Define.
276 (struct string_buf): New.
277 (strbuf): New function.
278 (get_field): Use strbuf rather than strdup of local temp.
279 (get_field_imm, get_field_imm5, get_field_imm5_mbar): Likewise.
280 (get_field_rfsl, get_field_imm15): Likewise.
281 (get_field_rd, get_field_r1, get_field_r2): Update macros.
282 (get_field_special): Likewise. Don't strcpy spr. Formatting.
283 (print_insn_microblaze): Formatting. Init and pass string_buf to
284 get_field functions.
285
0ba59a29
JB		 2862019-12-04 Jan Beulich <jbeulich@suse.com>
287
288 * i386-opc.tbl (lfs, lgs, lss): Drop No_qSuf.
289 * i386-tbl.h: Re-generate.
290
77ad8092
JB		 2912019-12-04 Jan Beulich <jbeulich@suse.com>
292
293 * i386-dis.c (mod_table): Use Ev instead of Em for movdiri.
294
3036c899
JB		 2952019-12-04 Jan Beulich <jbeulich@suse.com>
296
297 * i386-opc.tbl (push, pop): Drop DefaultSize from GPR-only
298 forms.
299 (xbegin): Drop DefaultSize.
300 * i386-tbl.h: Re-generate.
301
8b301fbb
MI		 3022019-11-22 Mihail Ionescu <mihail.ionescu@arm.com>
303
304 * opcodes/arm-dis.c (arm_opcodes, thumb32_opcodes):
305 Change the coproc CRC conditions to use the extension
306 feature set, second word, base on ARM_EXT2_CRC.
307
6aa385b9
JB		 3082019-11-14 Jan Beulich <jbeulich@suse.com>
309
310 * i386-opc.tbl (syscall, sysret): Drop Cpu64 forms.
311 * i386-tbl.h: Re-generate.
312
0cfa3eb3
JB		 3132019-11-14 Jan Beulich <jbeulich@suse.com>
314
315 * i386-gen.c (opcode_modifiers): Remove JumpDword, JumpByte,
316 JumpInterSegment, and JumpAbsolute entries.
317 * i386-opc.h (JUMP, JUMP_DWORD, JUMP_BYTE, JUMP_INTERSEGMENT,
318 JUMP_ABSOLUTE): Define.
319 (struct i386_opcode_modifier): Extend jump field to 3 bits.
320 Remove jumpdword, jumpbyte, jumpintersegment, and jumpabsolute
321 fields.
322 * i386-opc.tbl (JumpByte, JumpDword, JumpAbsolute,
323 JumpInterSegment): Define.
324 * i386-tbl.h: Re-generate.
325
6f2f06be
JB		 3262019-11-14 Jan Beulich <jbeulich@suse.com>
327
328 * i386-gen.c (operand_type_init): Remove
329 OPERAND_TYPE_JUMPABSOLUTE entry.
330 (opcode_modifiers): Add JumpAbsolute entry.
331 (operand_types): Remove JumpAbsolute entry.
332 * i386-opc.h (JumpAbsolute): Move between enums.
333 (struct i386_opcode_modifier): Add jumpabsolute field.
334 (union i386_operand_type): Remove jumpabsolute field.
335 * i386-opc.tbl (call, lcall, jmp, ljmp): Move JumpAbsolute.
336 * i386-init.h, i386-tbl.h: Re-generate.
337
601e8564
JB		 3382019-11-14 Jan Beulich <jbeulich@suse.com>
339
340 * i386-gen.c (opcode_modifiers): Add AnySize entry.
341 (operand_types): Remove AnySize entry.
342 * i386-opc.h (AnySize): Move between enums.
343 (struct i386_opcode_modifier): Add anysize field.
344 (OTUnused): Un-comment.
345 (union i386_operand_type): Remove anysize field.
346 * i386-opc.tbl (lea, invlpg, clflush, prefetchnta, prefetcht0,
347 prefetcht1, prefetcht2, prefetchtw, bndmk, bndcl, bndcu, bndcn,
348 bndstx, bndldx, prefetchwt1, clflushopt, clwb, cldemote): Move
349 AnySize.
350 * i386-tbl.h: Re-generate.
351
7722d40a
JW		 3522019-11-12 Nelson Chu <nelson.chu@sifive.com>
353
354 * riscv-opc.c (riscv_insn_types): Replace the INSN_CLASS_I with
355 INSN_CLASS_F and the INSN_CLASS_C with INSN_CLASS_F_AND_C if we
356 use the floating point register (FPR).
357
ce760a76
MI		 3582019-11-12 Mihail Ionescu <mihail.ionescu@arm.com>
359
360 * opcodes/arm-dis.c (mve_opcodes): Enable VMOV imm to vec with
361 cmode 1101.
362 (is_mve_encoding_conflict): Update cmode conflict checks for
363 MVE_VMVN_IMM.
364
51c8edf6
JB		 3652019-11-12 Jan Beulich <jbeulich@suse.com>
366
367 * i386-gen.c (operand_type_init): Remove OPERAND_TYPE_ESSEG
368 entry.
369 (operand_types): Remove EsSeg entry.
370 (main): Replace stale use of OTMax.
371 * i386-opc.h (IS_STRING_ES_OP0, IS_STRING_ES_OP1): Define.
372 (struct i386_opcode_modifier): Expand isstring field to 2 bits.
373 (EsSeg): Delete.
374 (OTUnused): Comment out.
375 (union i386_operand_type): Remove esseg field.
376 * i386-opc.tbl (IsStringEsOp0, IsStringEsOp1): Define.
377 (cmps, scmp, scas, ssca, cmpsd): Add IsStringEsOp0.
378 (ins, movs, smov, movsd): Add IsStringEsOpOp1.
379 (stos, ssto): Add IsStringEsOp0/IsStringEsOpOp1.
380 * i386-init.h, i386-tbl.h: Re-generate.
381
474da251
JB		 3822019-11-12 Jan Beulich <jbeulich@suse.com>
383
384 * i386-gen.c (operand_instances): Add RegB entry.
385 * i386-opc.h (enum operand_instance): Add RegB.
386 * i386-opc.tbl (RegC, RegD, RegB): Define.
387 (Acc, ShiftCount, InOutPortReg): Adjust definitions.
388 (monitor, mwait, invlpga, skinit, vmload, vmrun, vmsave, clzero,
389 monitorx, mwaitx): Drop ImmExt and convert encodings
390 accordingly.
391 * i386-reg.tbl (ecx, rcx): Add Instance=RegC.
392 (edx, rdx): Add Instance=RegD.
393 (ebx, rbx): Add Instance=RegB.
394 * i386-tbl.h: Re-generate.
395
75e5731b
JB		 3962019-11-12 Jan Beulich <jbeulich@suse.com>
397
398 * i386-gen.c (operand_type_init): Adjust
399 OPERAND_TYPE_INOUTPORTREG, OPERAND_TYPE_SHIFTCOUNT,
400 OPERAND_TYPE_FLOATACC, OPERAND_TYPE_ACC8, OPERAND_TYPE_ACC16,
401 OPERAND_TYPE_ACC32, and OPERAND_TYPE_ACC64 entries.
402 (operand_instances): New.
403 (operand_types): Drop InOutPortReg, ShiftCount, and Acc entries.
404 (output_operand_type): New parameter "instance". Process it.
405 (process_i386_operand_type): New local variable "instance".
406 (main): Adjust static assertions.
407 * i386-opc.h (INSTANCE_WIDTH): Define.
408 (enum operand_instance): New.
409 (Acc, InOutPortReg, ShiftCount): Replace by ClassInstance.
410 (union i386_operand_type): Replace acc, inoutportreg, and
411 shiftcount by instance.
412 * i386-opc.tbl (Acc, InOutPortReg, ShiftCount): Define.
413 * i386-reg.tbl (st, al, cl, ax, dx, eax, rax, xmm0, st(0)):
414 Add Instance=.
415 * i386-init.h, i386-tbl.h: Re-generate.
416
91802f3c
JB		 4172019-11-11 Jan Beulich <jbeulich@suse.com>
418
419 * aarch64-tbl.h (aarch64_opcode_table): Switch SVE2's
420 smaxp/sminp entries' "tied_operand" field to 2.
421
4f5fc85d
JB		 4222019-11-11 Jan Beulich <jbeulich@suse.com>
423
424 * aarch64-opc.c (operand_general_constraint_met_p): Replace
425 "index" local variable by that of the already existing "num".
426
dc2be329
L		 4272019-11-08 H.J. Lu <hongjiu.lu@intel.com>
428
429 PR gas/25167
430 * i386-opc.tbl: Remove IgnoreSize from cmpsd and movsd.
431 * i386-tbl.h: Regenerated.
432
f74a6307
JB		 4332019-11-08 Jan Beulich <jbeulich@suse.com>
434
435 * i386-gen.c (operand_type_init): Add Class= to
436 OPERAND_TYPE_REGMASK and OPERAND_TYPE_REGBND entries. Move up
437 OPERAND_TYPE_REGBND entry.
438 (operand_classes): Add RegMask and RegBND entries.
439 (operand_types): Drop RegMask and RegBND entry.
440 * i386-opc.h (enum operand_class): Add RegMask and RegBND.
441 (RegMask, RegBND): Delete.
442 (union i386_operand_type): Remove regmask and regbnd fields.
443 * i386-opc.tbl (RegMask, RegBND): Define.
444 * i386-reg.tbl: Replace RegMask by Class=RegMask and RegBND by
445 Class=RegBND.
446 * i386-init.h, i386-tbl.h: Re-generate.
447
3528c362
JB		 4482019-11-08 Jan Beulich <jbeulich@suse.com>
449
450 * i386-gen.c (operand_type_init): Add Class= to
451 OPERAND_TYPE_REGMMX, OPERAND_TYPE_REGXMM, OPERAND_TYPE_REGYMM, and
452 OPERAND_TYPE_REGZMM entries.
453 (operand_classes): Add RegMMX and RegSIMD entries.
454 (operand_types): Drop RegMMX and RegSIMD entries.
455 * i386-opc.h (enum operand_class): Add RegMMX and RegSIMD.
456 (RegMMX, RegSIMD): Delete.
457 (union i386_operand_type): Remove regmmx and regsimd fields.
458 * i386-opc.tbl (RegMMX): Define.
459 (RegXMM, RegYMM, RegZMM): Add Class=.
460 * i386-reg.tbl: Replace RegMMX by Class=RegMMX and RegSIMD by
461 Class=RegSIMD.
462 * i386-init.h, i386-tbl.h: Re-generate.
463
4a5c67ed
JB		 4642019-11-08 Jan Beulich <jbeulich@suse.com>
465
466 * i386-gen.c (operand_type_init): Add Class= to
467 OPERAND_TYPE_CONTROL, OPERAND_TYPE_TEST, and OPERAND_TYPE_DEBUG
468 entries.
469 (operand_classes): Add RegCR, RegDR, and RegTR entries.
470 (operand_types): Drop Control, Debug, and Test entries.
471 * i386-opc.h (enum operand_class): Add RegCR, RegDR, and RegTR.
472 (Control, Debug, Test): Delete.
473 (union i386_operand_type): Remove control, debug, and test
474 fields.
475 * i386-opc.tbl (Control, Debug, Test): Define.
476 * i386-reg.tbl: Replace Control by Class=RegCR, Debug by
477 Class=RegDR, and Test by Class=RegTR.
478 * i386-init.h, i386-tbl.h: Re-generate.
479
00cee14f
JB		 4802019-11-08 Jan Beulich <jbeulich@suse.com>
481
482 * i386-gen.c (operand_type_init): Add Class= to
483 OPERAND_TYPE_SREG entry.
484 (operand_classes): Add SReg entry.
485 (operand_types): Drop SReg entry.
486 * i386-opc.h (enum operand_class): Add SReg.
487 (SReg): Delete.
488 (union i386_operand_type): Remove sreg field.
489 * i386-opc.tbl (SReg): Define.
490 * i386-reg.tbl: Replace SReg by Class=SReg.
491 * i386-init.h, i386-tbl.h: Re-generate.
492
bab6aec1
JB		 4932019-11-08 Jan Beulich <jbeulich@suse.com>
494
495 * i386-gen.c (operand_type_init): Add Class=. New
496 OPERAND_TYPE_ANYIMM entry.
497 (operand_classes): New.
498 (operand_types): Drop Reg entry.
499 (output_operand_type): New parameter "class". Process it.
500 (process_i386_operand_type): New local variable "class".
501 (main): Adjust static assertions.
502 * i386-opc.h (CLASS_WIDTH): Define.
503 (enum operand_class): New.
504 (Reg): Replace by Class. Adjust comment.
505 (union i386_operand_type): Replace reg by class.
506 * i386-opc.tbl (Reg8, Reg16, Reg32, Reg64, FloatReg): Add
507 Class=.
508 * i386-reg.tbl: Replace Reg by Class=Reg.
509 * i386-init.h: Re-generate.
510
1f4cd317
MM		 5112019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
512
513 * opcodes/aarch64-tbl.h (V8_6_INSN): New macro for v8.6 instructions.
514 (aarch64_opcode_table): Add data gathering hint mnemonic.
515 * opcodes/aarch64-dis-2.c: Account for new instruction.
516
616ce08e
MM		 5172019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
518
519 * arm-dis.c (neon_opcodes): Add i8mm SIMD instructions.
520
521
8382113f
MM		 5222019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
523
524 * aarch64-tbl.h (aarch64_feature_i8mm_sve, aarch64_feature_f32mm_sve,
525 aarch64_feature_f64mm_sve, aarch64_feature_i8mm, aarch64_feature_f32mm,
526 aarch64_feature_f64mm): New feature sets.
527 (INT8MATMUL_INSN, F64MATMUL_SVE_INSN, F64MATMUL_INSN,
528 F32MATMUL_SVE_INSN, F32MATMUL_INSN): New macros to define matrix multiply
529 instructions.
530 (I8MM_SVE, F32MM_SVE, F64MM_SVE, I8MM, F32MM, F64MM): New feature set
531 macros.
532 (QL_MMLA64, OP_SVE_SBB): New qualifiers.
533 (OP_SVE_QQQ): New qualifier.
534 (INT8MATMUL_SVE_INSNC, F64MATMUL_SVE_INSNC,
535 F32MATMUL_SVE_INSNC): New feature set for bfloat16 instructions to support
536 the movprfx constraint.
537 (aarch64_opcode_table): Support for SVE_ADDR_RI_S4x32.
538 (aarch64_opcode_table): Define new instructions smmla,
539 ummla, usmmla, usdot, sudot, fmmla, ld1rob, ld1roh, ld1row, ld1rod,
540 uzip{1/2}, trn{1/2}.
541 * aarch64-opc.c (operand_general_constraint_met_p): Handle
542 AARCH64_OPND_SVE_ADDR_RI_S4x32.
543 (aarch64_print_operand): Handle AARCH64_OPND_SVE_ADDR_RI_S4x32.
544 * aarch64-dis-2.c (aarch64_opcode_lookup_1, aarch64_find_next_opcode):
545 Account for new instructions.
546 * opcodes/aarch64-asm-2.c (aarch64_insert_operand): Support the new
547 S4x32 operand.
548 * aarch64-opc-2.c (aarch64_operands): Support the new S4x32 operand.
549
aab2c27d
MM		 5502019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
5512019-11-07 Matthew Malcomson <matthew.malcomson@arm.com>
552
553 * arm-dis.c (select_arm_features): Update bfd_march_arm_8 with
554 Armv8.6-A.
555 (coprocessor_opcodes): Add bfloat16 vcvt{t,b}.
556 (neon_opcodes): Add bfloat SIMD instructions.
557 (print_insn_coprocessor): Add new control character %b to print
558 condition code without checking cp_num.
559 (print_insn_neon): Account for BFloat16 instructions that have no
560 special top-byte handling.
561
33593eaf
MM		 5622019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
5632019-11-07 Matthew Malcomson <matthew.malcomson@arm.com>
564
565 * arm-dis.c (print_insn_coprocessor,
566 print_insn_generic_coprocessor): Create wrapper functions around
567 the implementation of the print_insn_coprocessor control codes.
568 (print_insn_coprocessor_1): Original print_insn_coprocessor
569 function that now takes which array to look at as an argument.
570 (print_insn_arm): Use both print_insn_coprocessor and
571 print_insn_generic_coprocessor.
572 (print_insn_thumb32): As above.
573
df678013
MM		 5742019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
5752019-11-07 Matthew Malcomson <matthew.malcomson@arm.com>
576
577 * aarch64-asm.c (aarch64_ins_reglane): Use AARCH64_OPND_QLF_S_2H
578 in reglane special case.
579 * aarch64-dis-2.c (aarch64_opcode_lookup_1,
580 aarch64_find_next_opcode): Account for new instructions.
581 * aarch64-dis.c (aarch64_ext_reglane): Use AARCH64_OPND_QLF_S_2H
582 in reglane special case.
583 * aarch64-opc.c (struct operand_qualifier_data): Add data for
584 new AARCH64_OPND_QLF_S_2H qualifier.
585 * aarch64-tbl.h (QL_BFDOT QL_BFDOT64, QL_BFDOT64I, QL_BFMMLA2,
586 QL_BFCVT64, QL_BFCVTN64, QL_BFCVTN2_64): New qualifiers.
587 (aarch64_feature_bfloat16, aarch64_feature_bfloat16_sve): New feature
588 sets.
589 (BFLOAT_SVE, BFLOAT): New feature set macros.
590 (BFLOAT_SVE_INSN, BFLOAT_INSN): New macros to define BFloat16
591 instructions.
592 (aarch64_opcode_table): Define new instructions bfdot,
593 bfmmla, bfcvt, bfcvtnt, bfdot, bfdot, bfcvtn, bfmlal[b/t]
594 bfcvtn2, bfcvt.
595
8ae2d3d9
MM		 5962019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
5972019-11-07 Matthew Malcomson <matthew.malcomson@arm.com>
598
599 * aarch64-tbl.h (ARMV8_6): New macro.
600
142861df
JB		 6012019-11-07 Jan Beulich <jbeulich@suse.com>
602
603 * i386-dis.c (prefix_table): Add mcommit.
604 (rm_table): Add rdpru.
605 * i386-gen.c (cpu_flag_init): Adjust CPU_ZNVER2_FLAGS entry. Add
606 CPU_RDPRU_FLAGS and CPU_MCOMMIT_FLAGS entries.
607 (cpu_flags): Add CpuRDPRU and CpuMCOMMIT entries.
608 * i386-opc.h (CpuRDPRU, CpuMCOMMIT): New.
609 (union i386_cpu_flags): Add cpurdpru and cpumcommit fields.
610 * i386-opc.tbl (mcommit, rdpru): New.
611 * i386-init.h, i386-tbl.h: Re-generate.
612
081e283f
JB		 6132019-11-07 Jan Beulich <jbeulich@suse.com>
614
615 * i386-dis.c (OP_Mwait): Drop local variable "names", use
616 "names32" instead.
617 (OP_Monitor): Drop local variable "op1_names", re-purpose
618 "names" for it instead, and replace former "names" uses by
619 "names32" ones.
620
c050c89a
JB		 6212019-11-07 Jan Beulich <jbeulich@suse.com>
622
623 PR/gas 25167
624 * opcodes/i386-opc.tbl (movsd, cmpsd): Drop IgnoreSize from
625 operand-less forms.
626 * opcodes/i386-tbl.h: Re-generate.
627
7abb8d81
JB		 6282019-11-05 Jan Beulich <jbeulich@suse.com>
629
630 * i386-dis.c (OP_Mwaitx): Delete.
631 (prefix_table): Use OP_Mwait for mwaitx entry.
632 (OP_Mwait): Also handle mwaitx.
633
267b8516
JB		 6342019-11-05 Jan Beulich <jbeulich@suse.com>
635
636 * i386-dis.c (PREFIX_0F01_REG_7_MOD_3_RM_2,
637 PREFIX_0F01_REG_7_MOD_3_RM_3): New.
638 (prefix_table): Add respective entries.
639 (rm_table): Link to those entries.
640
f8687e93
JB		 6412019-11-05 Jan Beulich <jbeulich@suse.com>
642
643 * i386-dis.c (REG_0F1C_MOD_0): Rename to ...
644 (REG_0F1C_P_0_MOD_0): ... this.
645 (REG_0F1E_MOD_3): Rename to ...
646 (REG_0F1E_P_1_MOD_3): ... this.
647 (RM_0F01_REG_5): Rename to ...
648 (RM_0F01_REG_5_MOD_3): ... this.
649 (RM_0F01_REG_7): Rename to ...
650 (RM_0F01_REG_7_MOD_3): ... this.
651 (RM_0F1E_MOD_3_REG_7): Rename to ...
652 (RM_0F1E_P_1_MOD_3_REG_7): ... this.
653 (RM_0FAE_REG_6): Rename to ...
654 (RM_0FAE_REG_6_MOD_3_P_0): ... this.
655 (RM_0FAE_REG_7): Rename to ...
656 (RM_0FAE_REG_7_MOD_3): ... this.
657 (PREFIX_MOD_0_0F01_REG_5): Rename to ...
658 (PREFIX_0F01_REG_5_MOD_0): ... this.
659 (PREFIX_MOD_3_0F01_REG_5_RM_0): Rename to ...
660 (PREFIX_0F01_REG_5_MOD_3_RM_0): ... this.
661 (PREFIX_MOD_3_0F01_REG_5_RM_2): Rename to ...
662 (PREFIX_0F01_REG_5_MOD_3_RM_2): ... this.
663 (PREFIX_0FAE_REG_0): Rename to ...
664 (PREFIX_0FAE_REG_0_MOD_3): ... this.
665 (PREFIX_0FAE_REG_1): Rename to ...
666 (PREFIX_0FAE_REG_1_MOD_3): ... this.
667 (PREFIX_0FAE_REG_2): Rename to ...
668 (PREFIX_0FAE_REG_2_MOD_3): ... this.
669 (PREFIX_0FAE_REG_3): Rename to ...
670 (PREFIX_0FAE_REG_3_MOD_3): ... this.
671 (PREFIX_MOD_0_0FAE_REG_4): Rename to ...
672 (PREFIX_0FAE_REG_4_MOD_0): ... this.
673 (PREFIX_MOD_3_0FAE_REG_4): Rename to ...
674 (PREFIX_0FAE_REG_4_MOD_3): ... this.
675 (PREFIX_MOD_0_0FAE_REG_5): Rename to ...
676 (PREFIX_0FAE_REG_5_MOD_0): ... this.
677 (PREFIX_MOD_3_0FAE_REG_5): Rename to ...
678 (PREFIX_0FAE_REG_5_MOD_3): ... this.
679 (PREFIX_MOD_0_0FAE_REG_6): Rename to ...
680 (PREFIX_0FAE_REG_6_MOD_0): ... this.
681 (PREFIX_MOD_1_0FAE_REG_6): Rename to ...
682 (PREFIX_0FAE_REG_6_MOD_3): ... this.
683 (PREFIX_0FAE_REG_7): Rename to ...
684 (PREFIX_0FAE_REG_7_MOD_0): ... this.
685 (PREFIX_MOD_0_0FC3): Rename to ...
686 (PREFIX_0FC3_MOD_0): ... this.
687 (PREFIX_MOD_0_0FC7_REG_6): Rename to ...
688 (PREFIX_0FC7_REG_6_MOD_0): ... this.
689 (PREFIX_MOD_3_0FC7_REG_6): Rename to ...
690 (PREFIX_0FC7_REG_6_MOD_3): ... this.
691 (PREFIX_MOD_3_0FC7_REG_7): Rename to ...
692 (PREFIX_0FC7_REG_7_MOD_3): ... this.
693 (reg_table, prefix_table, mod_table, rm_table): Adjust
694 accordingly.
695
5103274f
NC		 6962019-11-04 Nick Clifton <nickc@redhat.com>
697
698 * v850-dis.c (get_v850_sreg_name): New function. Returns the name
699 of a v850 system register. Move the v850_sreg_names array into
700 this function.
701 (get_v850_reg_name): Likewise for ordinary register names.
702 (get_v850_vreg_name): Likewise for vector register names.
703 (get_v850_cc_name): Likewise for condition codes.
704 * get_v850_float_cc_name): Likewise for floating point condition
705 codes.
706 (get_v850_cacheop_name): Likewise for cache-ops.
707 (get_v850_prefop_name): Likewise for pref-ops.
708 (disassemble): Use the new accessor functions.
709
1820262b
DB		 7102019-10-30 Delia Burduv <delia.burduv@arm.com>
711
712 * aarch64-opc.c (print_immediate_offset_address): Don't print the
713 immediate for the writeback form of ldraa/ldrab if it is 0.
714 * aarch64-tbl.h: Updated the documentation for ADDR_SIMM10.
715 * aarch64-opc-2.c: Regenerated.
716
3cc17af5
JB		 7172019-10-30 Jan Beulich <jbeulich@suse.com>
718
719 * i386-gen.c (operand_type_shorthands): Delete.
720 (operand_type_init): Expand previous shorthands.
721 (set_bitfield_from_shorthand): Rename back to ...
722 (set_bitfield_from_cpu_flag_init): ... this. Drop processing
723 of operand_type_init[].
724 (set_bitfield): Adjust call to the above function.
725 * i386-opc.tbl (Reg8, Reg16, Reg32, Reg64, FloatAcc, FloatReg,
726 RegXMM, RegYMM, RegZMM): Define.
727 * i386-reg.tbl: Expand prior shorthands.
728
a2cebd03
JB		 7292019-10-30 Jan Beulich <jbeulich@suse.com>
730
731 * i386-gen.c (output_i386_opcode): Change order of fields
732 emitted to output.
733 * i386-opc.h (struct insn_template): Move operands field.
734 Convert extension_opcode field to unsigned short.
735 * i386-tbl.h: Re-generate.
736
507916b8
JB		 7372019-10-30 Jan Beulich <jbeulich@suse.com>
738
739 * i386-gen.c (process_i386_opcode_modifier): Report bogus uses
740 of W.
741 * i386-opc.h (W): Extend comment.
742 * i386-opc.tbl (mov, movabs, movq): Drop W and adjust opcodes of
743 general purpose variants not allowing for byte operands.
744 * i386-tbl.h: Re-generate.
745
efea62b4
NC		 7462019-10-29 Nick Clifton <nickc@redhat.com>
747
748 * tic30-dis.c (print_branch): Correct size of operand array.
749
9adb2591
NC		 7502019-10-29 Nick Clifton <nickc@redhat.com>
751
752 * d30v-dis.c (print_insn): Check that operand index is valid
753 before attempting to access the operands array.
754
993a00a9
NC		 7552019-10-29 Nick Clifton <nickc@redhat.com>
756
757 * ia64-opc.c (locate_opcode_ent): Prevent a negative shift when
758 locating the bit to be tested.
759
66a66a17
NC		 7602019-10-29 Nick Clifton <nickc@redhat.com>
761
762 * s12z-dis.c (opr_emit_disassembly): Check for illegal register
763 values.
764 (shift_size_table): Use a fixed size defined as S12Z_N_SIZES.
765 (print_insn_s12z): Check for illegal size values.
766
1ee3542c
NC		 7672019-10-28 Nick Clifton <nickc@redhat.com>
768
769 * csky-dis.c (csky_chars_to_number): Check for a negative
770 count. Use an unsigned integer to construct the return value.
771
bbf9a0b5
NC		 7722019-10-28 Nick Clifton <nickc@redhat.com>
773
774 * tic30-dis.c (OPERAND_BUFFER_LEN): Define. Use as length of
775 operand buffer. Set value to 15 not 13.
776 (get_register_operand): Use OPERAND_BUFFER_LEN.
777 (get_indirect_operand): Likewise.
778 (print_two_operand): Likewise.
779 (print_three_operand): Likewise.
780 (print_oar_insn): Likewise.
781
d1e304bc
NC		 7822019-10-28 Nick Clifton <nickc@redhat.com>
783
784 * ns32k-dis.c (bit_extract): Add sanitiy check of parameters.
785 (bit_extract_simple): Likewise.
786 (bit_copy): Likewise.
787 (pirnt_insn_ns32k): Ensure that uninitialised elements in the
788 index_offset array are not accessed.
789
dee33451
NC		 7902019-10-28 Nick Clifton <nickc@redhat.com>
791
792 * xgate-dis.c (print_insn): Fix decoding of the XGATE_OP_DYA
793 operand.
794
27cee81d
NC		 7952019-10-25 Nick Clifton <nickc@redhat.com>
796
797 * rx-dis.c (print_insn_rx): Use parenthesis to ensure correct
798 access to opcodes.op array element.
799
de6d8dc2
NC		 8002019-10-23 Nick Clifton <nickc@redhat.com>
801
802 * rx-dis.c (get_register_name): Fix spelling typo in error
803 message.
804 (get_condition_name, get_flag_name, get_double_register_name)
805 (get_double_register_high_name, get_double_register_low_name)
806 (get_double_control_register_name, get_double_condition_name)
807 (get_opsize_name, get_size_name): Likewise.
808
6207ed28
NC		 8092019-10-22 Nick Clifton <nickc@redhat.com>
810
811 * rx-dis.c (get_size_name): New function. Provides safe
812 access to name array.
813 (get_opsize_name): Likewise.
814 (print_insn_rx): Use the accessor functions.
815
12234dfd
NC		 8162019-10-16 Nick Clifton <nickc@redhat.com>
817
818 * rx-dis.c (get_register_name): New function. Provides safe
819 access to name array.
820 (get_condition_name, get_flag_name, get_double_register_name)
821 (get_double_register_high_name, get_double_register_low_name)
822 (get_double_control_register_name, get_double_condition_name):
823 Likewise.
824 (print_insn_rx): Use the accessor functions.
825
1d378749
NC		 8262019-10-09 Nick Clifton <nickc@redhat.com>
827
828 PR 25041
829 * avr-dis.c (avr_operand): Fix construction of address for lds/sts
830 instructions.
831
d241b910
JB		 8322019-10-07 Jan Beulich <jbeulich@suse.com>
833
834 * opcodes/i386-opc.tbl (movsd): Add Dword and IgnoreSize.
835 (cmpsd): Likewise. Move EsSeg to other operand.
836 * opcodes/i386-tbl.h: Re-generate.
837
f5c5b7c1
AM		 8382019-09-23 Alan Modra <amodra@gmail.com>
839
840 * m68k-dis.c: Include cpu-m68k.h
841
7beeaeb8
AM		 8422019-09-23 Alan Modra <amodra@gmail.com>
843
844 * mips-dis.c: Include elfxx-mips.h. Move "elf-bfd.h" and
845 "elf/mips.h" earlier.
846
3f9aad11
JB		 8472018-09-20 Jan Beulich <jbeulich@suse.com>
848
849 PR gas/25012
850 * i386-opc.tbl (push, pop): Re-instate distinct Cpu64 templates
851 with SReg operand.
852 * i386-tbl.h: Re-generate.
853
fd361982
AM		 8542019-09-18 Alan Modra <amodra@gmail.com>
855
856 * arc-ext.c: Update throughout for bfd section macro changes.
857
e0b2a78c
SM		 8582019-09-18 Simon Marchi <simon.marchi@polymtl.ca>
859
860 * Makefile.in: Re-generate.
861 * configure: Re-generate.
862
7e9ad3a3
JW		 8632019-09-17 Maxim Blinov <maxim.blinov@embecosm.com>
864
865 * riscv-opc.c (riscv_opcodes): Change subset field
866 to insn_class field for all instructions.
867 (riscv_insn_types): Likewise.
868
bb695960
PB		 8692019-09-16 Phil Blundell <pb@pbcl.net>
870
871 * configure: Regenerated.
872
8063ab7e
MV		 8732019-09-10 Miod Vallat <miod@online.fr>
874
875 PR 24982
876 * m68k-opc.c: Correct aliases for tdivsl and tdivul.
877
60391a25
PB		 8782019-09-09 Phil Blundell <pb@pbcl.net>
879
880 binutils 2.33 branch created.
881
f44b758d
NC		 8822019-09-03 Nick Clifton <nickc@redhat.com>
883
884 PR 24961
885 * tic30-dis.c (get_indirect_operand): Check for bufcnt being
886 greater than zero before indexing via (bufcnt -1).
887
1e4b5e7d
NC		 8882019-09-03 Nick Clifton <nickc@redhat.com>
889
890 PR 24958
891 * mmix-dis.c (MAX_REG_NAME_LEN): Define.
892 (MAX_SPEC_REG_NAME_LEN): Define.
893 (struct mmix_dis_info): Use defined constants for array lengths.
894 (get_reg_name): New function.
895 (get_sprec_reg_name): New function.
896 (print_insn_mmix): Use new functions.
897
c4a23bf8
SP		 8982019-08-27 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
899
900 * arm-dis.c (mve_opcodes): Add entry for MVE_VMOV_VEC_TO_VEC.
901 (is_mve_undefined): Add case for MVE_VMOV_VEC_TO_VEC.
902 (print_insn_mve): Add condition to check Qm==Qn of VORR instruction.
903
a051e2f3
KT		 9042019-08-22 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
905
906 * aarch64-opc.c (aarch64_sys_regs): Update encoding of tfsre0_el1,
907 tfsr_el1, tfsr_el2, tfsr_el3, tfsr_el12.
908 (aarch64_sys_reg_supported_p): Update checks for the above.
909
08132bdd
SP		 9102019-08-12 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
911
912 * arm-dis.c (struct mopcode32 mve_opcodes): Modify the mask for
913 cases MVE_SQRSHRL and MVE_UQRSHLL.
914 (print_insn_mve): Add case for specifier 'k' to check
915 specific bit of the instruction.
916
d88bdcb4
PA		 9172019-08-07 Phillipe Antoine <p.antoine@catenacyber.fr>
918
919 PR 24854
920 * arc-dis.c (arc_insn_length): Return 0 rather than aborting when
921 encountering an unknown machine type.
922 (print_insn_arc): Handle arc_insn_length returning 0. In error
923 cases return -1 rather than calling abort.
924
bc750500
JB		 9252019-08-07 Jan Beulich <jbeulich@suse.com>
926
927 * i386-opc.tbl (fld, fstp): Drop FloatMF from extended forms.
928 (fldcw, fnstcw, fstcw, fnstsw, fstsw): Replace FloatMF by
929 IgnoreSize.
930 * i386-tbl.h: Re-generate.
931
23d188c7
BW		 9322019-08-05 Barnaby Wilks <barnaby.wilks@arm.com>
933
934 * arm-dis.c: Only accept signed variants of VQ(R)DMLAH and VQ(R)DMLASH
935 instructions.
936
c0d6f62f
JW		 9372019-07-30 Mel Chen <mel.chen@sifive.com>
938
939 * riscv-opc.c (riscv_opcodes): Set frsr, fssr, frcsr, fscsr, frrm,
940 fsrm, fsrmi, frflags, fsflags, fsflagsi to alias instructions.
941
942 * riscv-opc.c (riscv_opcodes): Adjust order of frsr, frcsr, fssr,
943 fscsr.
944
0f3f7167
CZ		 9452019-07-24 Claudiu Zissulescu <claziss@synopsys.com>
946
947 * arc-dis.c (skip_this_opcode): Check also for 0x07 major opcodes,
948 and MPY class instructions.
949 (parse_option): Add nps400 option.
950 (print_arc_disassembler_options): Add nps400 info.
951
7e126ba3
CZ		 9522019-07-24 Claudiu Zissulescu <claziss@synopsys.com>
953
954 * arc-ext-tbl.h (bspeek): Remove it, added to main table.
955 (bspop): Likewise.
956 (modapp): Likewise.
957 * arc-opc.c (RAD_CHK): Add.
958 * arc-tbl.h: Regenerate.
959
a028026d
KT		 9602019-07-23 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
961
962 * aarch64-opc.c (aarch64_sys_regs): Add gmid_el1 entry.
963 (aarch64_sys_reg_supported_p): Handle gmid_el1 encoding.
964
ac79ff9e
NC		 9652019-07-22 Barnaby Wilks <barnaby.wilks@arm.com>
966
967 * arm-dis.c (is_mve_unpredictable): Stop marking some MVE
968 instructions as UNPREDICTABLE.
969
231097b0
JM		 9702019-07-19 Jose E. Marchesi <jose.marchesi@oracle.com>
971
972 * bpf-desc.c: Regenerated.
973
1d942ae9
JB		 9742019-07-17 Jan Beulich <jbeulich@suse.com>
975
976 * i386-gen.c (static_assert): Define.
977 (main): Use it.
978 * i386-opc.h (Opcode_Modifier_Max): Rename to ...
979 (Opcode_Modifier_Num): ... this.
980 (Mem): Delete.
981
dfd69174
JB		 9822019-07-16 Jan Beulich <jbeulich@suse.com>
983
984 * i386-gen.c (operand_types): Move RegMem ...
985 (opcode_modifiers): ... here.
986 * i386-opc.h (RegMem): Move to opcode modifer enum.
987 (union i386_operand_type): Move regmem field ...
988 (struct i386_opcode_modifier): ... here.
989 * i386-opc.tbl (RegMem): Define.
990 (mov, movq): Move RegMem on segment, control, debug, and test
991 register flavors.
992 (pextrb): Move RegMem on register only flavors. Add IgnoreSize
993 to non-SSE2AVX flavor.
994 (extractps, pextrw, vcvtps2ph, vextractps, vpextrb, vpextrw):
995 Move RegMem on register only flavors. Drop IgnoreSize from
996 legacy encoding flavors.
997 (movss, movsd, vmovss, vmovsd): Drop RegMem from register only
998 flavors.
999 (vpinsrb, vpinsrw): Drop IgnoreSize where still present on
1000 register only flavors.
1001 (vmovd): Move RegMem and drop IgnoreSize on register only
1002 flavor. Change opcode and operand order to store form.
1003 * opcodes/i386-init.h, i386-tbl.h: Re-generate.
1004
21df382b
JB		 10052019-07-16 Jan Beulich <jbeulich@suse.com>
1006
1007 * i386-gen.c (operand_type_init, operand_types): Replace SReg
1008 entries.
1009 * i386-opc.h (SReg2, SReg3): Replace by ...
1010 (SReg): ... this.
1011 (union i386_operand_type): Replace sreg fields.
1012 * i386-opc.tbl (mov, ): Use SReg.
1013 (push, pop): Likewies. Drop i386 and x86-64 specific segment
1014 register flavors.
1015 * i386-reg.tbl (cs, ds, es, fs, gs, ss, flat): Use SReg.
1016 * opcodes/i386-init.h, i386-tbl.h: Re-generate.
1017
3719fd55
JM		 10182019-07-15 Jose E. Marchesi <jose.marchesi@oracle.com>
1019
1020 * bpf-desc.c: Regenerate.
1021 * bpf-opc.c: Likewise.
1022 * bpf-opc.h: Likewise.
1023
92434a14
JM		 10242019-07-14 Jose E. Marchesi <jose.marchesi@oracle.com>
1025
1026 * bpf-desc.c: Regenerate.
1027 * bpf-opc.c: Likewise.
1028
43dd7626
HPN		 10292019-07-10 Hans-Peter Nilsson <hp@bitrange.com>
1030
1031 * arm-dis.c (print_insn_coprocessor): Rename index to
1032 index_operand.
1033
98602811
JW		 10342019-07-05 Kito Cheng <kito.cheng@sifive.com>
1035
1036 * riscv-opc.c (riscv_insn_types): Add r4 type.
1037
1038 * riscv-opc.c (riscv_insn_types): Add b and j type.
1039
1040 * opcodes/riscv-opc.c (riscv_insn_types): Remove incorrect
1041 format for sb type and correct s type.
1042
01c1ee4a
RS		 10432019-07-02 Richard Sandiford <richard.sandiford@arm.com>
1044
1045 * aarch64-tbl.h (aarch64_opcode): Set C_SCAN_MOVPRFX for the
1046 SVE FMOV alias of FCPY.
1047
83adff69
RS		 10482019-07-02 Richard Sandiford <richard.sandiford@arm.com>
1049
1050 * aarch64-tbl.h (aarch64_opcode_table): Add C_MAX_ELEM flags
1051 to SVE fcvtzs, fcvtzu, scvtf and ucvtf entries.
1052
89418844
RS		 10532019-07-02 Richard Sandiford <richard.sandiford@arm.com>
1054
1055 * aarch64-opc.c (verify_constraints): Skip GPRs when scanning the
1056 registers in an instruction prefixed by MOVPRFX.
1057
41be57ca
MM		 10582019-07-01 Matthew Malcomson <matthew.malcomson@arm.com>
1059
1060 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Use new
1061 sve_size_13 icode to account for variant behaviour of
1062 pmull{t,b}.
1063 * aarch64-dis-2.c: Regenerate.
1064 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Use new
1065 sve_size_13 icode to account for variant behaviour of
1066 pmull{t,b}.
1067 * aarch64-tbl.h (OP_SVE_VVV_HD_BS): Add new qualifier.
1068 (OP_SVE_VVV_Q_D): Add new qualifier.
1069 (OP_SVE_VVV_QHD_DBS): Remove now unused qualifier.
1070 (struct aarch64_opcode): Split pmull{t,b} into those requiring
1071 AES and those not.
1072
9d3bf266
JB		 10732019-07-01 Jan Beulich <jbeulich@suse.com>
1074
1075 * opcodes/i386-gen.c (operand_type_init): Remove
1076 OPERAND_TYPE_VEC_IMM4 entry.
1077 (operand_types): Remove Vec_Imm4.
1078 * opcodes/i386-opc.h (Vec_Imm4): Delete.
1079 (union i386_operand_type): Remove vec_imm4.
1080 * i386-opc.tbl (vpermil2pd, vpermil2ps): Remove Vec_Imm4.
1081 * opcodes/i386-init.h, i386-tbl.h: Re-generate.
1082
c3949f43
JB		 10832019-07-01 Jan Beulich <jbeulich@suse.com>
1084
1085 * i386-opc.tbl (lfence, mfence, sfence, monitor, mwait, vmcall,
1086 vmlaunch, vmresume, vmxoff, vmfunc, xgetbv, xsetbv, swapgs,
1087 rdtscp, clgi, invlpga, skinit, stgi, vmload, vmmcall, vmrun,
1088 vmsave, montmul, xsha1, xsha256, xstorerng, xcryptecb,
1089 xcryptcbc, xcryptctr, xcryptcfb, xcryptofb, xstore, clac, stac,
1090 monitorx, mwaitx): Drop ImmExt from operand-less forms.
1091 * i386-tbl.h: Re-generate.
1092
5641ec01
JB		 10932019-07-01 Jan Beulich <jbeulich@suse.com>
1094
1095 * i386-opc.tbl (and, or): Add Optimize to forms allowing two
1096 register operands.
1097 * i386-tbl.h: Re-generate.
1098
79dec6b7
JB		 10992019-07-01 Jan Beulich <jbeulich@suse.com>
1100
1101 * i386-opc.tbl (C): New.
1102 (paddb, paddw, paddd, paddq, paddsb, paddsw, paddusb, paddusw,
1103 pand, pcmpeqb, pcmpeqw, pcmpeqd, pmaddwd, pmulhw, pmullw,
1104 por, pxor, andps, cmpeqps, cmpeqss, cmpneqps, cmpneqss,
1105 cmpordps, cmpordss, cmpunordps, cmpunordss, orps, pavgb, pavgw,
1106 pmaxsw, pmaxub, pminsw, pminub, pmulhuw, xorps, andpd, cmpeqpd,
1107 cmpeqsd, cmpneqpd, cmpneqsd, cmpordpd, cmpordsd, cmpunordpd,
1108 cmpunordsd, orpd, xorpd, pmuludq, vandpd, vandps, vcmpeq_ospd,
1109 vcmpeq_osps, vcmpeq_ossd, vcmpeq_osss, vcmpeqpd, vcmpeqps,
1110 vcmpeqsd, vcmpeqss, vcmpeq_uqpd, vcmpeq_uqps, vcmpeq_uqsd,
1111 vcmpeq_uqss, vcmpeq_uspd, vcmpeq_usps, vcmpeq_ussd,
1112 vcmpeq_usss, vcmpfalse_ospd, vcmpfalse_osps, vcmpfalse_ossd,
1113 vcmpfalse_osss, vcmpfalsepd, vcmpfalseps, vcmpfalsesd,
1114 vcmpfalsess, vcmpneq_oqpd, vcmpneq_oqps, vcmpneq_oqsd,
1115 vcmpneq_oqss, vcmpneq_ospd, vcmpneq_osps, vcmpneq_ossd,
1116 vcmpneq_osss, vcmpneqpd, vcmpneqps, vcmpneqsd, vcmpneqss,
1117 vcmpneq_uspd, vcmpneq_usps, vcmpneq_ussd, vcmpneq_usss,
1118 vcmpordpd, vcmpordps, vcmpordsd, vcmpord_spd, vcmpord_sps,
1119 vcmpordss, vcmpord_ssd, vcmpord_sss, vcmptruepd, vcmptrueps,
1120 vcmptruesd, vcmptruess, vcmptrue_uspd, vcmptrue_usps,
1121 vcmptrue_ussd, vcmptrue_usss, vcmpunordpd, vcmpunordps,
1122 vcmpunordsd, vcmpunord_spd, vcmpunord_sps, vcmpunordss,
1123 vcmpunord_ssd, vcmpunord_sss, vorpd, vorps, vpaddsb, vpaddsw,
1124 vpaddb, vpaddd, vpaddq, vpaddw, vpaddusb, vpaddusw, vpand,
1125 vpavgb, vpavgw, vpcmpeqb, vpcmpeqd, vpcmpeqw, vpmaddwd,
1126 vpmaxsw, vpmaxub, vpminsw, vpminub, vpmulhuw, vpmulhw, vpmullw,
1127 vpmuludq, vpor, vpxor, vxorpd, vxorps): Add C to VEX-encoded
1128 flavors.
1129 * i386-tbl.h: Re-generate.
1130
a0a1771e
JB		 11312019-07-01 Jan Beulich <jbeulich@suse.com>
1132
1133 * i386-opc.tbl (and, or): Add Optimize to forms allowing two
1134 register operands.
1135 * i386-tbl.h: Re-generate.
1136
cd546e7b
JB		 11372019-07-01 Jan Beulich <jbeulich@suse.com>
1138
1139 * i386-dis-evex-prefix.h: Use PCLMUL for vpclmulqdq.
1140 * i386-opc.tbl (vpclmullqlqdq, vpclmulhqlqdq, vpclmullqhqdq,
1141 vpclmulhqhqdq): Add CpuVPCLMULQDQ flavors.
1142 * i386-tbl.h: Re-generate.
1143
e3bba3fc
JB		 11442019-07-01 Jan Beulich <jbeulich@suse.com>
1145
1146 * i386-opc.tbl (vextractps, vpextrw, vpinsrw): Remove
1147 Disp8MemShift from register only templates.
1148 * i386-tbl.h: Re-generate.
1149
36cc073e
JB		 11502019-07-01 Jan Beulich <jbeulich@suse.com>
1151
1152 * i386-dis.c (EXdScalarS, MOD_EVEX_0F10_PREFIX_1,
1153 MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1,
1154 MOD_EVEX_0F11_PREFIX_3, EVEX_W_0F10_P_1_M_0,
1155 EVEX_W_0F10_P_1_M_1, EVEX_W_0F10_P_3_M_0, EVEX_W_0F10_P_3_M_1,
1156 EVEX_W_0F11_P_1_M_0, EVEX_W_0F11_P_1_M_1, EVEX_W_0F11_P_3_M_0,
1157 EVEX_W_0F11_P_3_M_1): Delete.
1158 (EVEX_W_0F10_P_1, EVEX_W_0F10_P_3, EVEX_W_0F11_P_1,
1159 EVEX_W_0F11_P_3): New.
1160 * i386-dis-evex-mod.h: Remove MOD_EVEX_0F10_PREFIX_1,
1161 MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1, and
1162 MOD_EVEX_0F11_PREFIX_3 table entries.
1163 * i386-dis-evex-prefix.h: Adjust PREFIX_EVEX_0F10 and
1164 PREFIX_EVEX_0F11 table entries.
1165 * i386-dis-evex-w.h: Replace EVEX_W_0F10_P_1_M_{0,1},
1166 EVEX_W_0F10_P_3_M_{0,1}, EVEX_W_0F11_P_1_M_{0,1}, and
1167 EVEX_W_0F11_P_3_M_{0,1} table entries.
1168
219920a7
JB		 11692019-07-01 Jan Beulich <jbeulich@suse.com>
1170
1171 * i386-dis.c (EXdVex, EXdVexS, EXqVex, EXqVexS, XMVex):
1172 Delete.
1173
e395f487
L		 11742019-06-27 H.J. Lu <hongjiu.lu@intel.com>
1175
1176 PR binutils/24719
1177 * i386-dis-evex-len.h: Add EVEX_LEN_0F38C6_REG_1_PREFIX_2,
1178 EVEX_LEN_0F38C6_REG_2_PREFIX_2, EVEX_LEN_0F38C6_REG_5_PREFIX_2,
1179 EVEX_LEN_0F38C6_REG_6_PREFIX_2, EVEX_LEN_0F38C7_R_1_P_2_W_0,
1180 EVEX_LEN_0F38C7_R_1_P_2_W_1, EVEX_LEN_0F38C7_R_2_P_2_W_0,
1181 EVEX_LEN_0F38C7_R_2_P_2_W_1, EVEX_LEN_0F38C7_R_5_P_2_W_0,
1182 EVEX_LEN_0F38C7_R_5_P_2_W_1, EVEX_LEN_0F38C7_R_6_P_2_W_0 and
1183 EVEX_LEN_0F38C7_R_6_P_2_W_1.
1184 * i386-dis-evex-prefix.h: Update PREFIX_EVEX_0F38C6_REG_1,
1185 PREFIX_EVEX_0F38C6_REG_2, PREFIX_EVEX_0F38C6_REG_5 and
1186 PREFIX_EVEX_0F38C6_REG_6 entries.
1187 * i386-dis-evex-w.h: Update EVEX_W_0F38C7_R_1_P_2,
1188 EVEX_W_0F38C7_R_2_P_2, EVEX_W_0F38C7_R_5_P_2 and
1189 EVEX_W_0F38C7_R_6_P_2 entries.
1190 * i386-dis.c: Add EVEX_LEN_0F38C6_REG_1_PREFIX_2,
1191 EVEX_LEN_0F38C6_REG_2_PREFIX_2, EVEX_LEN_0F38C6_REG_5_PREFIX_2,
1192 EVEX_LEN_0F38C6_REG_6_PREFIX_2, EVEX_LEN_0F38C7_R_1_P_2_W_0,
1193 EVEX_LEN_0F38C7_R_1_P_2_W_1, EVEX_LEN_0F38C7_R_2_P_2_W_0,
1194 EVEX_LEN_0F38C7_R_2_P_2_W_1, EVEX_LEN_0F38C7_R_5_P_2_W_0,
1195 EVEX_LEN_0F38C7_R_5_P_2_W_1, EVEX_LEN_0F38C7_R_6_P_2_W_0 and
1196 EVEX_LEN_0F38C7_R_6_P_2_W_1 enums.
1197
2b7bcc87
JB		 11982019-06-27 Jan Beulich <jbeulich@suse.com>
1199
1200 * i386-dis.c (VEX_LEN_0F2A_P_1, VEX_LEN_0F2A_P_3,
1201 VEX_LEN_0F2C_P_1, VEX_LEN_0F2C_P_3, VEX_LEN_0F2D_P_1,
1202 VEX_LEN_0F2D_P_3): Delete.
1203 (vex_len_table): Move vcvtsi2ss, vcvtsi2sd, vcvttss2si,
1204 vcvttsd2si, vcvtss2si, and vcvtsd2si leaf entries ...
1205 (prefix_table): ... here.
1206
c1dc7af5
JB		 12072019-06-27 Jan Beulich <jbeulich@suse.com>
1208
1209 * i386-dis.c (Iq): Delete.
1210 (Id): New.
1211 (reg_table): Use it for lwpins, lwpval, and bextr. Use Edq for
1212 TBM insns.
1213 (vex_len_table): Use Edq for vcvtsi2ss, vcvtsi2sd. Use Gdq for
1214 vcvttss2si, vcvttsd2si, vcvtss2si, and vcvtsd2si.
1215 (OP_E_memory): Also honor needindex when deciding whether an
1216 address size prefix needs printing.
1217 (OP_I): Remove handling of q_mode. Add handling of d_mode.
1218
d7560e2d
JW		 12192019-06-26 Jim Wilson <jimw@sifive.com>
1220
1221 PR binutils/24739
1222 * riscv-dis.c (riscv_disasemble_insn): Set info->endian_code.
1223 Set info->display_endian to info->endian_code.
1224
2c703856
JB		 12252019-06-25 Jan Beulich <jbeulich@suse.com>
1226
1227 * i386-gen.c (operand_type_init): Correct OPERAND_TYPE_DEBUG
1228 entry. Drop OPERAND_TYPE_ACC entry. Add OPERAND_TYPE_ACC8 and
1229 OPERAND_TYPE_ACC16 entries. Adjust OPERAND_TYPE_ACC32 and
1230 OPERAND_TYPE_ACC64 entries.
1231 * i386-init.h: Re-generate.
1232
54fbadc0
JB		 12332019-06-25 Jan Beulich <jbeulich@suse.com>
1234
1235 * i386-dis.c (Edqa, dqa_mode, EVEX_W_0F2A_P_1, EVEX_W_0F7B_P_1):
1236 Delete.
1237 (intel_operand_size, OP_E_register, OP_E_memory): Drop handling
1238 of dqa_mode.
1239 * i386-dis-evex-prefix.h: Move vcvtsi2ss and vcvtusi2ss leaf
1240 entries here.
1241 * i386-dis-evex-w.h: Drop EVEX_W_0F2A_P_1 and EVEX_W_0F7B_P_1
1242 entries. Use Edq for vcvtsi2sd and vcvtusi2sd.
1243
a280ab8e
JB		 12442019-06-25 Jan Beulich <jbeulich@suse.com>
1245
1246 * i386-dis.c (OP_I64): Forword more cases to OP_I(). Drop local
1247 variables.
1248
e1a1babd
JB		 12492019-06-25 Jan Beulich <jbeulich@suse.com>
1250
1251 * i386-dis.c (prefix_table): Use Edq for cvtsi2ss and cvtsi2sd.
1252 Use Gdq for cvttss2si, cvttsd2si, cvtss2si, and cvtsd2si, and
1253 movnti.
d7560e2d 1254 * i386-opc.tbl (movnti): Add IgnoreSize.
e1a1babd
JB		 1255 * i386-tbl.h: Re-generate.
1256
b8364fa7
JB		 12572019-06-25 Jan Beulich <jbeulich@suse.com>
1258
1259 * i386-opc.tbl (and): Mark Imm8S form for optimization.
1260 * i386-tbl.h: Re-generate.
1261
ad692897
L		 12622019-06-21 H.J. Lu <hongjiu.lu@intel.com>
1263
1264 * i386-dis-evex.h: Break into ...
1265 * i386-dis-evex-len.h: New file.
1266 * i386-dis-evex-mod.h: Likewise.
1267 * i386-dis-evex-prefix.h: Likewise.
1268 * i386-dis-evex-reg.h: Likewise.
1269 * i386-dis-evex-w.h: Likewise.
1270 * i386-dis.c: Include i386-dis-evex-reg.h, i386-dis-evex-prefix.h,
1271 i386-dis-evex.h, i386-dis-evex-len.h, i386-dis-evex-w.h and
1272 i386-dis-evex-mod.h.
1273
f0a6222e
L		 12742019-06-19 H.J. Lu <hongjiu.lu@intel.com>
1275
1276 PR binutils/24700
1277 * i386-dis-evex.h (evex_table): Update EVEX_W_0F3819_P_2,
1278 EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2, EVEX_W_0F385A_P_2 and
1279 EVEX_W_0F385B_P_2.
1280 (evex_len_table): Add EVEX_LEN_0F3819_P_2_W_0,
1281 EVEX_LEN_0F3819_P_2_W_1, EVEX_LEN_0F381A_P_2_W_0,
1282 EVEX_LEN_0F381A_P_2_W_1, EVEX_LEN_0F381B_P_2_W_0,
1283 EVEX_LEN_0F381B_P_2_W_1, EVEX_LEN_0F385A_P_2_W_0,
1284 EVEX_LEN_0F385A_P_2_W_1, EVEX_LEN_0F385B_P_2_W_0 and
1285 EVEX_LEN_0F385B_P_2_W_1.
1286 * i386-dis.c (EVEX_LEN_0F3819_P_2_W_0): New enum.
1287 (EVEX_LEN_0F3819_P_2_W_1): Likewise.
1288 (EVEX_LEN_0F381A_P_2_W_0): Likewise.
1289 (EVEX_LEN_0F381A_P_2_W_1): Likewise.
1290 (EVEX_LEN_0F381B_P_2_W_0): Likewise.
1291 (EVEX_LEN_0F381B_P_2_W_1): Likewise.
1292 (EVEX_LEN_0F385A_P_2_W_0): Likewise.
1293 (EVEX_LEN_0F385A_P_2_W_1): Likewise.
1294 (EVEX_LEN_0F385B_P_2_W_0): Likewise.
1295 (EVEX_LEN_0F385B_P_2_W_1): Likewise.
1296
6e1c90b7
L		 12972019-06-17 H.J. Lu <hongjiu.lu@intel.com>
1298
1299 PR binutils/24691
1300 * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A23_P_2,
1301 EVEX_W_0F3A38_P_2, EVEX_W_0F3A39_P_2, EVEX_W_0F3A3A_P_2,
1302 EVEX_W_0F3A3B_P_2 and EVEX_W_0F3A43_P_2.
1303 (evex_len_table): Add EVEX_LEN_0F3A23_P_2_W_0,
1304 EVEX_LEN_0F3A23_P_2_W_1, EVEX_LEN_0F3A38_P_2_W_0,
1305 EVEX_LEN_0F3A38_P_2_W_1, EVEX_LEN_0F3A39_P_2_W_0,
1306 EVEX_LEN_0F3A39_P_2_W_1, EVEX_LEN_0F3A3A_P_2_W_0,
1307 EVEX_LEN_0F3A3A_P_2_W_1, EVEX_LEN_0F3A3B_P_2_W_0,
1308 EVEX_LEN_0F3A3B_P_2_W_1, EVEX_LEN_0F3A43_P_2_W_0 and
1309 EVEX_LEN_0F3A43_P_2_W_1.
1310 * i386-dis.c (EVEX_LEN_0F3A23_P_2_W_0): New enum.
1311 (EVEX_LEN_0F3A23_P_2_W_1): Likewise.
1312 (EVEX_LEN_0F3A38_P_2_W_0): Likewise.
1313 (EVEX_LEN_0F3A38_P_2_W_1): Likewise.
1314 (EVEX_LEN_0F3A39_P_2_W_0): Likewise.
1315 (EVEX_LEN_0F3A39_P_2_W_1): Likewise.
1316 (EVEX_LEN_0F3A3A_P_2_W_0): Likewise.
1317 (EVEX_LEN_0F3A3A_P_2_W_1): Likewise.
1318 (EVEX_LEN_0F3A3B_P_2_W_0): Likewise.
1319 (EVEX_LEN_0F3A3B_P_2_W_1): Likewise.
1320 (EVEX_LEN_0F3A43_P_2_W_0): Likewise.
1321 (EVEX_LEN_0F3A43_P_2_W_1): Likewise.
1322
bcc5a6eb
NC		 13232019-06-14 Nick Clifton <nickc@redhat.com>
1324
1325 * po/fr.po; Updated French translation.
1326
e4c4ac46
SH		 13272019-06-13 Stafford Horne <shorne@gmail.com>
1328
1329 * or1k-asm.c: Regenerated.
1330 * or1k-desc.c: Regenerated.
1331 * or1k-desc.h: Regenerated.
1332 * or1k-dis.c: Regenerated.
1333 * or1k-ibld.c: Regenerated.
1334 * or1k-opc.c: Regenerated.
1335 * or1k-opc.h: Regenerated.
1336 * or1k-opinst.c: Regenerated.
1337
a0e44ef5
PB		 13382019-06-12 Peter Bergner <bergner@linux.ibm.com>
1339
1340 * ppc-opc.c (powerpc_opcodes) <ldmx>: Delete mnemonic.
1341
12efd68d
L		 13422019-06-05 H.J. Lu <hongjiu.lu@intel.com>
1343
1344 PR binutils/24633
1345 * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A18_P_2,
1346 EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2 and EVEX_W_0F3A1B_P_2.
1347 (evex_len_table): EVEX_LEN_0F3A18_P_2_W_0,
1348 EVEX_LEN_0F3A18_P_2_W_1, EVEX_LEN_0F3A19_P_2_W_0,
1349 EVEX_LEN_0F3A19_P_2_W_1, EVEX_LEN_0F3A1A_P_2_W_0,
1350 EVEX_LEN_0F3A1A_P_2_W_1, EVEX_LEN_0F3A1B_P_2_W_0,
1351 EVEX_LEN_0F3A1B_P_2_W_1.
1352 * i386-dis.c (EVEX_LEN_0F3A18_P_2_W_0): New enum.
1353 (EVEX_LEN_0F3A18_P_2_W_1): Likewise.
1354 (EVEX_LEN_0F3A19_P_2_W_0): Likewise.
1355 (EVEX_LEN_0F3A19_P_2_W_1): Likewise.
1356 (EVEX_LEN_0F3A1A_P_2_W_0): Likewise.
1357 (EVEX_LEN_0F3A1A_P_2_W_1): Likewise.
1358 (EVEX_LEN_0F3A1B_P_2_W_0): Likewise.
1359 (EVEX_LEN_0F3A1B_P_2_W_1): Likewise.
1360
63c6fc6c
L		 13612019-06-04 H.J. Lu <hongjiu.lu@intel.com>
1362
1363 PR binutils/24626
1364 * i386-dis.c (print_insn): Check for unused VEX.vvvv and
1365 EVEX.vvvv when disassembling VEX and EVEX instructions.
1366 (OP_VEX): Set vex.register_specifier to 0 after readding
1367 vex.register_specifier.
1368 (OP_Vex_2src_1): Likewise.
1369 (OP_Vex_2src_2): Likewise.
1370 (OP_LWP_E): Likewise.
1371 (OP_EX_Vex): Don't check vex.register_specifier.
1372 (OP_XMM_Vex): Likewise.
1373
9186c494
L		 13742019-06-04 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1375 Lili Cui <lili.cui@intel.com>
1376
1377 * i386-dis.c (enum): Add PREFIX_EVEX_0F3868, EVEX_W_0F3868_P_3.
1378 * i386-dis-evex.h (evex_table): Add AVX512_VP2INTERSECT
1379 instructions.
1380 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VP2INTERSECT_FLAGS,
1381 CPU_ANY_AVX512_VP2INTERSECT_FLAGS.
1382 (cpu_flags): Add CpuAVX512_VP2INTERSECT.
1383 * i386-opc.h (enum): Add CpuAVX512_VP2INTERSECT.
1384 (i386_cpu_flags): Add cpuavx512_vp2intersect.
1385 * i386-opc.tbl: Add AVX512_VP2INTERSECT insns.
1386 * i386-init.h: Regenerated.
1387 * i386-tbl.h: Likewise.
1388
5d79adc4
L		 13892019-06-04 Xuepeng Guo <xuepeng.guo@intel.com>
1390 Lili Cui <lili.cui@intel.com>
1391
1392 * doc/c-i386.texi: Document enqcmd.
1393 * testsuite/gas/i386/enqcmd-intel.d: New file.
1394 * testsuite/gas/i386/enqcmd-inval.l: Likewise.
1395 * testsuite/gas/i386/enqcmd-inval.s: Likewise.
1396 * testsuite/gas/i386/enqcmd.d: Likewise.
1397 * testsuite/gas/i386/enqcmd.s: Likewise.
1398 * testsuite/gas/i386/x86-64-enqcmd-intel.d: Likewise.
1399 * testsuite/gas/i386/x86-64-enqcmd-inval.l: Likewise.
1400 * testsuite/gas/i386/x86-64-enqcmd-inval.s: Likewise.
1401 * testsuite/gas/i386/x86-64-enqcmd.d: Likewise.
1402 * testsuite/gas/i386/x86-64-enqcmd.s: Likewise.
1403 * testsuite/gas/i386/i386.exp: Run enqcmd-intel, enqcmd-inval,
1404 enqcmd, x86-64-enqcmd-intel, x86-64-enqcmd-inval,
1405 and x86-64-enqcmd.
1406
a9d96ab9
AH		 14072019-06-04 Alan Hayward <alan.hayward@arm.com>
1408
1409 * arm-dis.c (is_mve_unpredictable): Remove spurious paranthesis.
1410
4f6d070a
AM		 14112019-06-03 Alan Modra <amodra@gmail.com>
1412
1413 * ppc-dis.c (prefix_opcd_indices): Correct size.
1414
a2f4b66c
L		 14152019-05-28 H.J. Lu <hongjiu.lu@intel.com>
1416
1417 PR gas/24625
1418 * i386-opc.tbl: Add CheckRegSize to AVX512_BF16 instructions with
1419 Disp8ShiftVL.
1420 * i386-tbl.h: Regenerated.
1421
405b5bd8
AM		 14222019-05-24 Alan Modra <amodra@gmail.com>
1423
1424 * po/POTFILES.in: Regenerate.
1425
8acf1435
PB		 14262019-05-24 Peter Bergner <bergner@linux.ibm.com>
1427 Alan Modra <amodra@gmail.com>
1428
1429 * ppc-opc.c (insert_d34, extract_d34, insert_nsi34, extract_nsi34),
1430 (insert_pcrel, extract_pcrel, extract_pcrel0): New functions.
1431 (extract_esync, extract_raq, extract_tbr, extract_sxl): Comment.
1432 (powerpc_operands <D34, SI34, NSI34, PRA0, PRAQ, PCREL, PCREL0,
1433 XTOP>): Define and add entries.
1434 (P8LS, PMLS, P_D_MASK, P_DRAPCREL_MASK): Define.
1435 (prefix_opcodes): Add pli, paddi, pla, psubi, plwz, plbz, pstw,
1436 pstb, plhz, plha, psth, plfs, plfd, pstfs, pstfd, plq, plxsd,
1437 plxssp, pld, plwa, pstxsd, pstxssp, pstxv, pstd, and pstq.
1438
dd7efa79
PB		 14392019-05-24 Peter Bergner <bergner@linux.ibm.com>
1440 Alan Modra <amodra@gmail.com>
1441
1442 * ppc-dis.c (ppc_opts): Add "future" entry.
1443 (PREFIX_OPCD_SEGS): Define.
1444 (prefix_opcd_indices): New array.
1445 (disassemble_init_powerpc): Initialize prefix_opcd_indices.
1446 (lookup_prefix): New function.
1447 (print_insn_powerpc): Handle 64-bit prefix instructions.
1448 * ppc-opc.c (PREFIX_OP, PREFIX_FORM, SUFFIX_MASK, PREFIX_MASK),
1449 (PMRR, POWERXX): Define.
1450 (prefix_opcodes): New instruction table.
1451 (prefix_num_opcodes): New constant.
1452
79472b45
JM		 14532019-05-23 Jose E. Marchesi <jose.marchesi@oracle.com>
1454
1455 * configure.ac (SHARED_DEPENDENCIES): Add case for bfd_bpf_arch.
1456 * configure: Regenerated.
1457 * Makefile.am: Add rules for the files generated from cpu/bpf.cpu
1458 and cpu/bpf.opc.
1459 (HFILES): Add bpf-desc.h and bpf-opc.h.
1460 (TARGET_LIBOPCODES_CFILES): Add bpf-asm.c, bpf-desc.c, bpf-dis.c,
1461 bpf-ibld.c and bpf-opc.c.
1462 (BPF_DEPS): Define.
1463 * Makefile.in: Regenerated.
1464 * disassemble.c (ARCH_bpf): Define.
1465 (disassembler): Add case for bfd_arch_bpf.
1466 (disassemble_init_for_target): Likewise.
1467 (enum epbf_isa_attr): Define.
1468 * disassemble.h: extern print_insn_bpf.
1469 * bpf-asm.c: Generated.
1470 * bpf-opc.h: Likewise.
1471 * bpf-opc.c: Likewise.
1472 * bpf-ibld.c: Likewise.
1473 * bpf-dis.c: Likewise.
1474 * bpf-desc.h: Likewise.
1475 * bpf-desc.c: Likewise.
1476
ba6cd17f
SD		 14772019-05-21 Sudakshina Das <sudi.das@arm.com>
1478
1479 * arm-dis.c (coprocessor_opcodes): New instructions for VMRS
1480 and VMSR with the new operands.
1481
e39c1607
SD		 14822019-05-21 Sudakshina Das <sudi.das@arm.com>
1483
1484 * arm-dis.c (enum mve_instructions): New enum
1485 for csinc, csinv, csneg, csel, cset, csetm, cinv, cinv
1486 and cneg.
1487 (mve_opcodes): New instructions as above.
1488 (is_mve_encoding_conflict): Add cases for csinc, csinv,
1489 csneg and csel.
1490 (print_insn_mve): Accept new %<bitfield>c and %<bitfield>C.
1491
23d00a41
SD		 14922019-05-21 Sudakshina Das <sudi.das@arm.com>
1493
1494 * arm-dis.c (emun mve_instructions): Updated for new instructions.
1495 (mve_opcodes): New instructions for asrl, lsll, lsrl, sqrshrl,
1496 sqrshr, sqshl, sqshll, srshr, srshrl, uqrshll, uqrshl, uqshll,
1497 uqshl, urshrl and urshr.
1498 (is_mve_okay_in_it): Add new instructions to TRUE list.
1499 (is_mve_unpredictable): Add cases for UNPRED_R13 and UNPRED_R15.
1500 (print_insn_mve): Updated to accept new %j,
1501 %<bitfield>m and %<bitfield>n patterns.
1502
cd4797ee
FS		 15032019-05-21 Faraz Shahbazker <fshahbazker@wavecomp.com>
1504
1505 * mips-opc.c (mips_builtin_opcodes): Change source register
1506 constraint for DAUI.
1507
999b073b
NC		 15082019-05-20 Nick Clifton <nickc@redhat.com>
1509
1510 * po/fr.po: Updated French translation.
1511
14b456f2
AV		 15122019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1513 Michael Collison <michael.collison@arm.com>
1514
1515 * arm-dis.c (thumb32_opcodes): Add new instructions.
1516 (enum mve_instructions): Likewise.
1517 (enum mve_undefined): Add new reasons.
1518 (is_mve_encoding_conflict): Handle new instructions.
1519 (is_mve_undefined): Likewise.
1520 (is_mve_unpredictable): Likewise.
1521 (print_mve_undefined): Likewise.
1522 (print_mve_size): Likewise.
1523
f49bb598
AV		 15242019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1525 Michael Collison <michael.collison@arm.com>
1526
1527 * arm-dis.c (thumb32_opcodes): Add new instructions.
1528 (enum mve_instructions): Likewise.
1529 (is_mve_encoding_conflict): Handle new instructions.
1530 (is_mve_undefined): Likewise.
1531 (is_mve_unpredictable): Likewise.
1532 (print_mve_size): Likewise.
1533
56858bea
AV		 15342019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1535 Michael Collison <michael.collison@arm.com>
1536
1537 * arm-dis.c (thumb32_opcodes): Add new instructions.
1538 (enum mve_instructions): Likewise.
1539 (is_mve_encoding_conflict): Likewise.
1540 (is_mve_unpredictable): Likewise.
1541 (print_mve_size): Likewise.
1542
e523f101
AV		 15432019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1544 Michael Collison <michael.collison@arm.com>
1545
1546 * arm-dis.c (thumb32_opcodes): Add new instructions.
1547 (enum mve_instructions): Likewise.
1548 (is_mve_encoding_conflict): Handle new instructions.
1549 (is_mve_undefined): Likewise.
1550 (is_mve_unpredictable): Likewise.
1551 (print_mve_size): Likewise.
1552
66dcaa5d
AV		 15532019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1554 Michael Collison <michael.collison@arm.com>
1555
1556 * arm-dis.c (thumb32_opcodes): Add new instructions.
1557 (enum mve_instructions): Likewise.
1558 (is_mve_encoding_conflict): Handle new instructions.
1559 (is_mve_undefined): Likewise.
1560 (is_mve_unpredictable): Likewise.
1561 (print_mve_size): Likewise.
1562 (print_insn_mve): Likewise.
1563
d052b9b7
AV		 15642019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1565 Michael Collison <michael.collison@arm.com>
1566
1567 * arm-dis.c (thumb32_opcodes): Add new instructions.
1568 (print_insn_thumb32): Handle new instructions.
1569
ed63aa17
AV		 15702019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1571 Michael Collison <michael.collison@arm.com>
1572
1573 * arm-dis.c (enum mve_instructions): Add new instructions.
1574 (enum mve_undefined): Add new reasons.
1575 (is_mve_encoding_conflict): Handle new instructions.
1576 (is_mve_undefined): Likewise.
1577 (is_mve_unpredictable): Likewise.
1578 (print_mve_undefined): Likewise.
1579 (print_mve_size): Likewise.
1580 (print_mve_shift_n): Likewise.
1581 (print_insn_mve): Likewise.
1582
897b9bbc
AV		 15832019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1584 Michael Collison <michael.collison@arm.com>
1585
1586 * arm-dis.c (enum mve_instructions): Add new instructions.
1587 (is_mve_encoding_conflict): Handle new instructions.
1588 (is_mve_unpredictable): Likewise.
1589 (print_mve_rotate): Likewise.
1590 (print_mve_size): Likewise.
1591 (print_insn_mve): Likewise.
1592
1c8f2df8
AV		 15932019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1594 Michael Collison <michael.collison@arm.com>
1595
1596 * arm-dis.c (enum mve_instructions): Add new instructions.
1597 (is_mve_encoding_conflict): Handle new instructions.
1598 (is_mve_unpredictable): Likewise.
1599 (print_mve_size): Likewise.
1600 (print_insn_mve): Likewise.
1601
d3b63143
AV		 16022019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1603 Michael Collison <michael.collison@arm.com>
1604
1605 * arm-dis.c (enum mve_instructions): Add new instructions.
1606 (enum mve_undefined): Add new reasons.
1607 (is_mve_encoding_conflict): Handle new instructions.
1608 (is_mve_undefined): Likewise.
1609 (is_mve_unpredictable): Likewise.
1610 (print_mve_undefined): Likewise.
1611 (print_mve_size): Likewise.
1612 (print_insn_mve): Likewise.
1613
14925797
AV		 16142019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1615 Michael Collison <michael.collison@arm.com>
1616
1617 * arm-dis.c (enum mve_instructions): Add new instructions.
1618 (is_mve_encoding_conflict): Handle new instructions.
1619 (is_mve_undefined): Likewise.
1620 (is_mve_unpredictable): Likewise.
1621 (print_mve_size): Likewise.
1622 (print_insn_mve): Likewise.
1623
c507f10b
AV		 16242019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1625 Michael Collison <michael.collison@arm.com>
1626
1627 * arm-dis.c (enum mve_instructions): Add new instructions.
1628 (enum mve_unpredictable): Add new reasons.
1629 (enum mve_undefined): Likewise.
1630 (is_mve_okay_in_it): Handle new isntructions.
1631 (is_mve_encoding_conflict): Likewise.
1632 (is_mve_undefined): Likewise.
1633 (is_mve_unpredictable): Likewise.
1634 (print_mve_vmov_index): Likewise.
1635 (print_simd_imm8): Likewise.
1636 (print_mve_undefined): Likewise.
1637 (print_mve_unpredictable): Likewise.
1638 (print_mve_size): Likewise.
1639 (print_insn_mve): Likewise.
1640
bf0b396d
AV		 16412019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1642 Michael Collison <michael.collison@arm.com>
1643
1644 * arm-dis.c (enum mve_instructions): Add new instructions.
1645 (enum mve_unpredictable): Add new reasons.
1646 (enum mve_undefined): Likewise.
1647 (is_mve_encoding_conflict): Handle new instructions.
1648 (is_mve_undefined): Likewise.
1649 (is_mve_unpredictable): Likewise.
1650 (print_mve_undefined): Likewise.
1651 (print_mve_unpredictable): Likewise.
1652 (print_mve_rounding_mode): Likewise.
1653 (print_mve_vcvt_size): Likewise.
1654 (print_mve_size): Likewise.
1655 (print_insn_mve): Likewise.
1656
ef1576a1
AV		 16572019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1658 Michael Collison <michael.collison@arm.com>
1659
1660 * arm-dis.c (enum mve_instructions): Add new instructions.
1661 (enum mve_unpredictable): Add new reasons.
1662 (enum mve_undefined): Likewise.
1663 (is_mve_undefined): Handle new instructions.
1664 (is_mve_unpredictable): Likewise.
1665 (print_mve_undefined): Likewise.
1666 (print_mve_unpredictable): Likewise.
1667 (print_mve_size): Likewise.
1668 (print_insn_mve): Likewise.
1669
aef6d006
AV		 16702019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1671 Michael Collison <michael.collison@arm.com>
1672
1673 * arm-dis.c (enum mve_instructions): Add new instructions.
1674 (enum mve_undefined): Add new reasons.
1675 (insns): Add new instructions.
1676 (is_mve_encoding_conflict):
1677 (print_mve_vld_str_addr): New print function.
1678 (is_mve_undefined): Handle new instructions.
1679 (is_mve_unpredictable): Likewise.
1680 (print_mve_undefined): Likewise.
1681 (print_mve_size): Likewise.
1682 (print_insn_coprocessor_1): Handle MVE VLDR, VSTR instructions.
1683 (print_insn_mve): Handle new operands.
1684
04d54ace
AV		 16852019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1686 Michael Collison <michael.collison@arm.com>
1687
1688 * arm-dis.c (enum mve_instructions): Add new instructions.
1689 (enum mve_unpredictable): Add new reasons.
1690 (is_mve_encoding_conflict): Handle new instructions.
1691 (is_mve_unpredictable): Likewise.
1692 (mve_opcodes): Add new instructions.
1693 (print_mve_unpredictable): Handle new reasons.
1694 (print_mve_register_blocks): New print function.
1695 (print_mve_size): Handle new instructions.
1696 (print_insn_mve): Likewise.
1697
9743db03
AV		 16982019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1699 Michael Collison <michael.collison@arm.com>
1700
1701 * arm-dis.c (enum mve_instructions): Add new instructions.
1702 (enum mve_unpredictable): Add new reasons.
1703 (enum mve_undefined): Likewise.
1704 (is_mve_encoding_conflict): Handle new instructions.
1705 (is_mve_undefined): Likewise.
1706 (is_mve_unpredictable): Likewise.
1707 (coprocessor_opcodes): Move NEON VDUP from here...
1708 (neon_opcodes): ... to here.
1709 (mve_opcodes): Add new instructions.
1710 (print_mve_undefined): Handle new reasons.
1711 (print_mve_unpredictable): Likewise.
1712 (print_mve_size): Handle new instructions.
1713 (print_insn_neon): Handle vdup.
1714 (print_insn_mve): Handle new operands.
1715
143275ea
AV		 17162019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1717 Michael Collison <michael.collison@arm.com>
1718
1719 * arm-dis.c (enum mve_instructions): Add new instructions.
1720 (enum mve_unpredictable): Add new values.
1721 (mve_opcodes): Add new instructions.
1722 (vec_condnames): New array with vector conditions.
1723 (mve_predicatenames): New array with predicate suffixes.
1724 (mve_vec_sizename): New array with vector sizes.
1725 (enum vpt_pred_state): New enum with vector predication states.
1726 (struct vpt_block): New struct type for vpt blocks.
1727 (vpt_block_state): Global struct to keep track of state.
1728 (mve_extract_pred_mask): New helper function.
1729 (num_instructions_vpt_block): Likewise.
1730 (mark_outside_vpt_block): Likewise.
1731 (mark_inside_vpt_block): Likewise.
1732 (invert_next_predicate_state): Likewise.
1733 (update_next_predicate_state): Likewise.
1734 (update_vpt_block_state): Likewise.
1735 (is_vpt_instruction): Likewise.
1736 (is_mve_encoding_conflict): Add entries for new instructions.
1737 (is_mve_unpredictable): Likewise.
1738 (print_mve_unpredictable): Handle new cases.
1739 (print_instruction_predicate): Likewise.
1740 (print_mve_size): New function.
1741 (print_vec_condition): New function.
1742 (print_insn_mve): Handle vpt blocks and new print operands.
1743
f08d8ce3
AV		 17442019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1745
1746 * arm-dis.c (print_insn_coprocessor_1): Disable the use of coprocessors
1747 8, 14 and 15 for Armv8.1-M Mainline.
1748
73cd51e5
AV		 17492019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1750 Michael Collison <michael.collison@arm.com>
1751
1752 * arm-dis.c (enum mve_instructions): New enum.
1753 (enum mve_unpredictable): Likewise.
1754 (enum mve_undefined): Likewise.
1755 (struct mopcode32): New struct.
1756 (is_mve_okay_in_it): New function.
1757 (is_mve_architecture): Likewise.
1758 (arm_decode_field): Likewise.
1759 (arm_decode_field_multiple): Likewise.
1760 (is_mve_encoding_conflict): Likewise.
1761 (is_mve_undefined): Likewise.
1762 (is_mve_unpredictable): Likewise.
1763 (print_mve_undefined): Likewise.
1764 (print_mve_unpredictable): Likewise.
1765 (print_insn_coprocessor_1): Use arm_decode_field_multiple.
1766 (print_insn_mve): New function.
1767 (print_insn_thumb32): Handle MVE architecture.
1768 (select_arm_features): Force thumb for Armv8.1-m Mainline.
1769
3076e594
NC		 17702019-05-10 Nick Clifton <nickc@redhat.com>
1771
1772 PR 24538
1773 * ia64-opc.c (ia64_find_matching_opcode): Check for reaching the
1774 end of the table prematurely.
1775
387e7624
FS		 17762019-05-10 Faraz Shahbazker <fshahbazker@wavecomp.com>
1777
1778 * mips-opc.c (mips_opcodes): Enable ADD, SUB, DADD and DSUB
1779 macros for R6.
1780
0067be51
AM		 17812019-05-11 Alan Modra <amodra@gmail.com>
1782
1783 * ppc-dis.c (print_insn_powerpc) Don't skip optional operands
1784 when -Mraw is in effect.
1785
42e6288f
MM		 17862019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1787
1788 * aarch64-dis-2.c: Regenerate.
1789 * aarch64-tbl.h (OP_SVE_BBU): New variant set.
1790 (OP_SVE_BBB): New variant set.
1791 (OP_SVE_DDDD): New variant set.
1792 (OP_SVE_HHH): New variant set.
1793 (OP_SVE_HHHU): New variant set.
1794 (OP_SVE_SSS): New variant set.
1795 (OP_SVE_SSSU): New variant set.
1796 (OP_SVE_SHH): New variant set.
1797 (OP_SVE_SBBU): New variant set.
1798 (OP_SVE_DSS): New variant set.
1799 (OP_SVE_DHHU): New variant set.
1800 (OP_SVE_VMV_HSD_BHS): New variant set.
1801 (OP_SVE_VVU_HSD_BHS): New variant set.
1802 (OP_SVE_VVVU_SD_BH): New variant set.
1803 (OP_SVE_VVVU_BHSD): New variant set.
1804 (OP_SVE_VVV_QHD_DBS): New variant set.
1805 (OP_SVE_VVV_HSD_BHS): New variant set.
1806 (OP_SVE_VVV_HSD_BHS2): New variant set.
1807 (OP_SVE_VVV_BHS_HSD): New variant set.
1808 (OP_SVE_VV_BHS_HSD): New variant set.
1809 (OP_SVE_VVV_SD): New variant set.
1810 (OP_SVE_VVU_BHS_HSD): New variant set.
1811 (OP_SVE_VZVV_SD): New variant set.
1812 (OP_SVE_VZVV_BH): New variant set.
1813 (OP_SVE_VZV_SD): New variant set.
1814 (aarch64_opcode_table): Add sve2 instructions.
1815
28ed815a
MM		 18162019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1817
1818 * aarch64-asm-2.c: Regenerated.
1819 * aarch64-dis-2.c: Regenerated.
1820 * aarch64-opc-2.c: Regenerated.
1821 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1822 for SVE_SHLIMM_UNPRED_22.
1823 (aarch64_print_operand): Add printing for SVE_SHLIMM_UNPRED_22.
1824 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHLIMM_UNPRED_22
1825 operand.
1826
fd1dc4a0
MM		 18272019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1828
1829 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1830 sve_size_tsz_bhs iclass encode.
1831 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1832 sve_size_tsz_bhs iclass decode.
1833
31e36ab3
MM		 18342019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1835
1836 * aarch64-asm-2.c: Regenerated.
1837 * aarch64-dis-2.c: Regenerated.
1838 * aarch64-opc-2.c: Regenerated.
1839 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1840 for SVE_Zm4_11_INDEX.
1841 (aarch64_print_operand): Add printing for SVE_Zm4_11_INDEX.
1842 (fields): Handle SVE_i2h field.
1843 * aarch64-opc.h (enum aarch64_field_kind): New SVE_i2h field.
1844 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm4_11_INDEX operand.
1845
1be5f94f
MM		 18462019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1847
1848 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1849 sve_shift_tsz_bhsd iclass encode.
1850 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1851 sve_shift_tsz_bhsd iclass decode.
1852
3c17238b
MM		 18532019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1854
1855 * aarch64-asm-2.c: Regenerated.
1856 * aarch64-dis-2.c: Regenerated.
1857 * aarch64-opc-2.c: Regenerated.
1858 * aarch64-asm.c (aarch64_ins_sve_shrimm):
1859 (aarch64_encode_variant_using_iclass): Handle
1860 sve_shift_tsz_hsd iclass encode.
1861 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1862 sve_shift_tsz_hsd iclass decode.
1863 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1864 for SVE_SHRIMM_UNPRED_22.
1865 (aarch64_print_operand): Add printing for SVE_SHRIMM_UNPRED_22.
1866 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHRIMM_UNPRED_22
1867 operand.
1868
cd50a87a
MM		 18692019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1870
1871 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1872 sve_size_013 iclass encode.
1873 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1874 sve_size_013 iclass decode.
1875
3c705960
MM		 18762019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1877
1878 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1879 sve_size_bh iclass encode.
1880 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1881 sve_size_bh iclass decode.
1882
0a57e14f
MM		 18832019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1884
1885 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1886 sve_size_sd2 iclass encode.
1887 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1888 sve_size_sd2 iclass decode.
1889 * aarch64-opc.c (fields): Handle SVE_sz2 field.
1890 * aarch64-opc.h (enum aarch64_field_kind): New SVE_sz2 field.
1891
c469c864
MM		 18922019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1893
1894 * aarch64-asm-2.c: Regenerated.
1895 * aarch64-dis-2.c: Regenerated.
1896 * aarch64-opc-2.c: Regenerated.
1897 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1898 for SVE_ADDR_ZX.
1899 (aarch64_print_operand): Add printing for SVE_ADDR_ZX.
1900 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_ADDR_ZX operand.
1901
116adc27
MM		 19022019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1903
1904 * aarch64-asm-2.c: Regenerated.
1905 * aarch64-dis-2.c: Regenerated.
1906 * aarch64-opc-2.c: Regenerated.
1907 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1908 for SVE_Zm3_11_INDEX.
1909 (aarch64_print_operand): Add printing for SVE_Zm3_11_INDEX.
1910 (fields): Handle SVE_i3l and SVE_i3h2 fields.
1911 * aarch64-opc.h (enum aarch64_field_kind): New SVE_i3l and SVE_i3h2
1912 fields.
1913 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm3_11_INDEX operand.
1914
3bd82c86
MM		 19152019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1916
1917 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1918 sve_size_hsd2 iclass encode.
1919 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1920 sve_size_hsd2 iclass decode.
1921 * aarch64-opc.c (fields): Handle SVE_size field.
1922 * aarch64-opc.h (enum aarch64_field_kind): New SVE_size field.
1923
adccc507
MM		 19242019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1925
1926 * aarch64-asm-2.c: Regenerated.
1927 * aarch64-dis-2.c: Regenerated.
1928 * aarch64-opc-2.c: Regenerated.
1929 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1930 for SVE_IMM_ROT3.
1931 (aarch64_print_operand): Add printing for SVE_IMM_ROT3.
1932 (fields): Handle SVE_rot3 field.
1933 * aarch64-opc.h (enum aarch64_field_kind): New SVE_rot3 field.
1934 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_IMM_ROT3 operand.
1935
5cd99750
MM		 19362019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1937
1938 * aarch64-opc.c (verify_constraints): Check for movprfx for sve2
1939 instructions.
1940
7ce2460a
MM		 19412019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1942
1943 * aarch64-tbl.h
1944 (aarch64_feature_sve2, aarch64_feature_sve2aes,
1945 aarch64_feature_sve2sha3, aarch64_feature_sve2sm4,
1946 aarch64_feature_sve2bitperm): New feature sets.
1947 (SVE2, SVE2_AES, SVE2_SHA3, SVE2_SM4, SVE2_BITPERM): New macros
1948 for feature set addresses.
1949 (SVE2_INSN, SVE2_INSNC, SVE2AES_INSN, SVE2SHA3_INSN,
1950 SVE2SM4_INSN, SVE2SM4_INSNC, SVE2BITPERM_INSN): New macros.
1951
41cee089
FS		 19522019-05-06 Andrew Bennett <andrew.bennett@imgtec.com>
1953 Faraz Shahbazker <fshahbazker@wavecomp.com>
1954
1955 * mips-dis.c (mips_calculate_combination_ases): Add ISA
1956 argument and set ASE_EVA_R6 appropriately.
1957 (set_default_mips_dis_options): Pass ISA to above.
1958 (parse_mips_dis_option): Likewise.
1959 * mips-opc.c (EVAR6): New macro.
1960 (mips_builtin_opcodes): Add llwpe, scwpe.
1961
b83b4b13
SD		 19622019-05-01 Sudakshina Das <sudi.das@arm.com>
1963
1964 * aarch64-asm-2.c: Regenerated.
1965 * aarch64-dis-2.c: Regenerated.
1966 * aarch64-opc-2.c: Regenerated.
1967 * aarch64-opc.c (operand_general_constraint_met_p): Add case for
1968 AARCH64_OPND_TME_UIMM16.
1969 (aarch64_print_operand): Likewise.
1970 * aarch64-tbl.h (QL_IMM_NIL): New.
1971 (TME): New.
1972 (_TME_INSN): New.
1973 (struct aarch64_opcode): Add tstart, tcommit, ttest and tcancel.
1974
4a90ce95
JD		 19752019-04-29 John Darrington <john@darrington.wattle.id.au>
1976
1977 * s12z-opc.c (shift_discrim): Return OP_INVALID when reading fails.
1978
a45328b9
AB		 19792019-04-26 Andrew Bennett <andrew.bennett@imgtec.com>
1980 Faraz Shahbazker <fshahbazker@wavecomp.com>
1981
1982 * mips-opc.c (mips_builtin_opcodes): Add llwp, lldp, scwp, scdp.
1983
d10be0cb
JD		 19842019-04-24 John Darrington <john@darrington.wattle.id.au>
1985
1986 * s12z-opc.h: Add extern "C" bracketing to help
1987 users who wish to use this interface in c++ code.
1988
a679f24e
JD		 19892019-04-24 John Darrington <john@darrington.wattle.id.au>
1990
1991 * s12z-opc.c (bm_decode): Handle bit map operations with the
1992 "reserved0" mode.
1993
32c36c3c
AV		 19942019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
1995
1996 * arm-dis.c (coprocessor_opcodes): Document new %J and %K format
1997 specifier. Add entries for VLDR and VSTR of system registers.
1998 (print_insn_coprocessor): Forbid coprocessor numbers 8, 14 and 15 in
1999 coprocessor instructions on Armv8.1-M Mainline targets. Add handling
2000 of %J and %K format specifier.
2001
efd6b359
AV		 20022019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
2003
2004 * arm-dis.c (coprocessor_opcodes): Document new %C format control code.
2005 Add new entries for VSCCLRM instruction.
2006 (print_insn_coprocessor): Handle new %C format control code.
2007
6b0dd094
AV		 20082019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
2009
2010 * arm-dis.c (enum isa): New enum.
2011 (struct sopcode32): New structure.
2012 (coprocessor_opcodes): change type of entries to struct sopcode32 and
2013 set isa field of all current entries to ANY.
2014 (print_insn_coprocessor): Change type of insn to struct sopcode32.
2015 Only match an entry if its isa field allows the current mode.
2016
4b5a202f
AV		 20172019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
2018
2019 * arm-dis.c (thumb_opcodes): Document %n control code. Add entry for
2020 CLRM.
2021 (print_insn_thumb32): Add logic to print %n CLRM register list.
2022
60f993ce
AV		 20232019-04-15 Sudakshina Das <sudi.das@arm.com>
2024
2025 * arm-dis.c (print_insn_thumb32): Updated to accept new %P
2026 and %Q patterns.
2027
f6b2b12d
AV		 20282019-04-15 Sudakshina Das <sudi.das@arm.com>
2029
2030 * arm-dis.c (thumb32_opcodes): New instruction bfcsel.
2031 (print_insn_thumb32): Edit the switch case for %Z.
2032
1889da70
AV		 20332019-04-15 Sudakshina Das <sudi.das@arm.com>
2034
2035 * arm-dis.c (print_insn_thumb32): Updated to accept new %Z pattern.
2036
65d1bc05
AV		 20372019-04-15 Sudakshina Das <sudi.das@arm.com>
2038
2039 * arm-dis.c (thumb32_opcodes): New instruction bfl.
2040
1caf72a5
AV		 20412019-04-15 Sudakshina Das <sudi.das@arm.com>
2042
2043 * arm-dis.c (print_insn_thumb32): Updated to accept new %Y pattern.
2044
f1c7f421
AV		 20452019-04-15 Sudakshina Das <sudi.das@arm.com>
2046
2047 * arm-dis.c (print_insn_thumb32): Add '%<bitfield>S' to print an
2048 Arm register with r13 and r15 unpredictable.
2049 (thumb32_opcodes): New instructions for bfx and bflx.
2050
4389b29a
AV		 20512019-04-15 Sudakshina Das <sudi.das@arm.com>
2052
2053 * arm-dis.c (thumb32_opcodes): New instructions for bf.
2054
e5d6e09e
AV		 20552019-04-15 Sudakshina Das <sudi.das@arm.com>
2056
2057 * arm-dis.c (print_insn_thumb32): Updated to accept new %W pattern.
2058
e12437dc
AV		 20592019-04-15 Sudakshina Das <sudi.das@arm.com>
2060
2061 * arm-dis.c (print_insn_thumb32): Updated to accept new %G pattern.
2062
031254f2
AV		 20632019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
2064
2065 * arm-dis.c (select_arm_features): Add logic for Armv8.1-M Mainline.
2066
e5a557ac
JD		 20672019-04-12 John Darrington <john@darrington.wattle.id.au>
2068
2069 s12z-dis.c, s12z-opc.c, s12z-opc.h: Replace "operator" with
2070 "optr". ("operator" is a reserved word in c++).
2071
bd7ceb8d
SD		 20722019-04-11 Sudakshina Das <sudi.das@arm.com>
2073
2074 * aarch64-opc.c (aarch64_print_operand): Add case for
2075 AARCH64_OPND_Rt_SP.
2076 (verify_constraints): Likewise.
2077 * aarch64-tbl.h (QL_LDST_AT): Update to add SP qualifier.
2078 (struct aarch64_opcode): Update stg, stzg, st2g, stz2g instructions
2079 to accept Rt|SP as first operand.
2080 (AARCH64_OPERANDS): Add new Rt_SP.
2081 * aarch64-asm-2.c: Regenerated.
2082 * aarch64-dis-2.c: Regenerated.
2083 * aarch64-opc-2.c: Regenerated.
2084
e54010f1
SD		 20852019-04-11 Sudakshina Das <sudi.das@arm.com>
2086
2087 * aarch64-asm-2.c: Regenerated.
2088 * aarch64-dis-2.c: Likewise.
2089 * aarch64-opc-2.c: Likewise.
2090 * aarch64-tbl.h (aarch64_opcode): Add new ldgm and stgm.
2091
7e96e219
RS		 20922019-04-09 Robert Suchanek <robert.suchanek@mips.com>
2093
2094 * mips-opc.c (mips_builtin_opcodes): Add RDHWR rt rd sel.
2095
6f2791d5
L		 20962019-04-08 H.J. Lu <hongjiu.lu@intel.com>
2097
2098 * i386-opc.tbl: Consolidate AVX512 BF16 entries.
2099 * i386-init.h: Regenerated.
2100
e392bad3
AM		 21012019-04-07 Alan Modra <amodra@gmail.com>
2102
2103 * ppc-dis.c (print_insn_powerpc): Use a tiny state machine
2104 op_separator to control printing of spaces, comma and parens
2105 rather than need_comma, need_paren and spaces vars.
2106
dffaa15c
AM		 21072019-04-07 Alan Modra <amodra@gmail.com>
2108
2109 PR 24421
2110 * arm-dis.c (print_insn_coprocessor): Correct bracket placement.
2111 (print_insn_neon, print_insn_arm): Likewise.
2112
d6aab7a1
XG		 21132019-04-05 Xuepeng Guo <xuepeng.guo@intel.com>
2114
2115 * i386-dis-evex.h (evex_table): Updated to support BF16
2116 instructions.
2117 * i386-dis.c (enum): Add EVEX_W_0F3852_P_1, EVEX_W_0F3872_P_1
2118 and EVEX_W_0F3872_P_3.
2119 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_BF16_FLAGS.
2120 (cpu_flags): Add bitfield for CpuAVX512_BF16.
2121 * i386-opc.h (enum): Add CpuAVX512_BF16.
2122 (i386_cpu_flags): Add bitfield for cpuavx512_bf16.
2123 * i386-opc.tbl: Add AVX512 BF16 instructions.
2124 * i386-init.h: Regenerated.
2125 * i386-tbl.h: Likewise.
2126
66e85460
AM		 21272019-04-05 Alan Modra <amodra@gmail.com>
2128
2129 * ppc-opc.c (XLBH_MASK): Subtract off BH field from BB_MASK.
2130 (powerpc_opcodes): Reorder bcctr and bclr extended mnemonics
2131 to favour printing of "-" branch hint when using the "y" bit.
2132 Allow BH field on bc{ctr,lr,tar}{,l}{-,+}.
2133
c2b1c275
AM		 21342019-04-05 Alan Modra <amodra@gmail.com>
2135
2136 * ppc-dis.c (print_insn_powerpc): Delay printing spaces after
2137 opcode until first operand is output.
2138
aae9718e
PB		 21392019-04-04 Peter Bergner <bergner@linux.ibm.com>
2140
2141 PR gas/24349
2142 * ppc-opc.c (valid_bo_pre_v2): Add comments.
2143 (valid_bo_post_v2): Add support for 'at' branch hints.
2144 (insert_bo): Only error on branch on ctr.
2145 (get_bo_hint_mask): New function.
2146 (insert_boe): Add new 'branch_taken' formal argument. Add support
2147 for inserting 'at' branch hints.
2148 (extract_boe): Add new 'branch_taken' formal argument. Add support
2149 for extracting 'at' branch hints.
2150 (insert_bom, extract_bom, insert_bop, extract_bop): New functions.
2151 (BOE): Delete operand.
2152 (BOM, BOP): New operands.
2153 (RM): Update value.
2154 (XLYLK, XLYLK_MASK, XLYBB_MASK): Delete.
2155 (powerpc_opcodes) <bc-, bcl-, bca-, bcla-, bclr-, bclrl-, bcctr-,
2156 bcctrl-, bctar-, bctarl->: Replace BOE with BOM.
2157 (powerpc_opcodes) <bc+, bcl+, bca+, bcla+, bclr+, bclrl+, bcctr+,
2158 bcctrl+, bctar+, bctarl+>: Replace BOE with BOP.
2159 <bdnztar, bdnztarl, bdztar, bdztarl, btar, btarl, bdnztar-, bdnztarl-,
2160 bdnztar+, bdnztarl+, bdztar-, bdztarl-, bdztar+, bdztarl+, bgetar,
2161 bnltar, bgetarl, bnltarl, bletar, bngtar, bletarl, bngtarl, bnetar,
2162 bnetarl, bnstar, bnutar, bnstarl, bnutarl, bgetar-, bnltar-, bgetarl-,
2163 bnltarl-, bletar-, bngtar-, bletarl-, bngtarl-, bnetar-, bnetarl-,
2164 bnstar-, bnutar-, bnstarl-, bnutarl-, bgetar+, bnltar+, bgetarl+,
2165 bnltarl+, bletar+, bngtar+, bletarl+, bngtarl+, bnetar+, bnetarl+,
2166 bnstar+, bnutar+, bnstarl+, bnutarl+, blttar, blttarl, bgttar, bgttarl,
2167 beqtar, beqtarl, bsotar, buntar, bsotarl, buntarl, blttar-, blttarl-,
2168 bgttar-, bgttarl-, beqtar-, beqtarl-, bsotar-, buntar-, bsotarl-,
2169 buntarl-, blttar+, blttarl+, bgttar+, bgttarl+, beqtar+, beqtarl+,
2170 bsotar+, buntar+, bsotarl+, buntarl+, bdnzftar, bdnzftarl, bdzftar,
2171 bdzftarl, bftar, bftarl, bftar-, bftarl-, bftar+, bftarl+, bdnzttar,
2172 bdnzttarl, bdzttar, bdzttarl, bttar, bttarl, bttar-, bttarl-, bttar+,
2173 bttarl+>: New extended mnemonics.
2174
96a86c01
AM		 21752019-03-28 Alan Modra <amodra@gmail.com>
2176
2177 PR 24390
2178 * ppc-opc.c (BTF): Define.
2179 (powerpc_opcodes): Use for mtfsb*.
2180 * ppc-dis.c (print_insn_powerpc): Print fields with both
2181 PPC_OPERAND_CR_REG and PPC_OPERAND_CR_BIT as a plain number.
2182
796d6298
TC		 21832019-03-25 Tamar Christina <tamar.christina@arm.com>
2184
2185 * arm-dis.c (struct arm_private_data): Remove has_mapping_symbols.
2186 (mapping_symbol_for_insn): Implement new algorithm.
2187 (print_insn): Remove duplicate code.
2188
60df3720
TC		 21892019-03-25 Tamar Christina <tamar.christina@arm.com>
2190
2191 * aarch64-dis.c (print_insn_aarch64):
2192 Implement override.
2193
51457761
TC		 21942019-03-25 Tamar Christina <tamar.christina@arm.com>
2195
2196 * aarch64-dis.c (print_insn_aarch64): Update the mapping symbol search
2197 order.
2198
53b2f36b
TC		 21992019-03-25 Tamar Christina <tamar.christina@arm.com>
2200
2201 * aarch64-dis.c (last_stop_offset): New.
2202 (print_insn_aarch64): Use stop_offset.
2203
89199bb5
L		 22042019-03-19 H.J. Lu <hongjiu.lu@intel.com>
2205
2206 PR gas/24359
2207 * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS to
2208 CPU_ANY_AVX2_FLAGS.
2209 * i386-init.h: Regenerated.
2210
97ed31ae
L		 22112019-03-18 H.J. Lu <hongjiu.lu@intel.com>
2212
2213 PR gas/24348
2214 * i386-opc.tbl: Add Optimize to vmovdqa32, vmovdqa64, vmovdqu8,
2215 vmovdqu16, vmovdqu32 and vmovdqu64.
2216 * i386-tbl.h: Regenerated.
2217
0919bfe9
AK		 22182019-03-12 Andreas Krebbel <krebbel@linux.ibm.com>
2219
2220 * s390-opc.txt: Rename selhhhr to selfhr. Remove optional operand
2221 from vstrszb, vstrszh, and vstrszf.
2222
22232019-03-12 Andreas Krebbel <krebbel@linux.ibm.com>
2224
2225 * s390-opc.txt: Add instruction descriptions.
2226
21820ebe
JW		 22272019-02-08 Jim Wilson <jimw@sifive.com>
2228
2229 * riscv-opc.c (riscv_opcodes) <beq>: Use Cz to compress 3 operand form.
2230 <bne>: Likewise.
2231
f7dd2fb2
TC		 22322019-02-07 Tamar Christina <tamar.christina@arm.com>
2233
2234 * arm-dis.c (arm_opcodes): Redefine hlt to armv1.
2235
6456d318
TC		 22362019-02-07 Tamar Christina <tamar.christina@arm.com>
2237
2238 PR binutils/23212
2239 * aarch64-opc.h (enum aarch64_field_kind): Add FLD_sz.
2240 * aarch64-opc.c (verify_elem_sd): New.
2241 (fields): Add FLD_sz entr.
2242 * aarch64-tbl.h (_SIMD_INSN): New.
2243 (aarch64_opcode_table): Add elem_sd verifier to fmla, fmls, fmul and
2244 fmulx scalar and vector by element isns.
2245
4a83b610
NC		 22462019-02-07 Nick Clifton <nickc@redhat.com>
2247
2248 * po/sv.po: Updated Swedish translation.
2249
fc60b8c8
AK		 22502019-01-31 Andreas Krebbel <krebbel@linux.ibm.com>
2251
2252 * s390-mkopc.c (main): Accept arch13 as cpu string.
2253 * s390-opc.c: Add new instruction formats and instruction opcode
2254 masks.
2255 * s390-opc.txt: Add new arch13 instructions.
2256
e10620d3
TC		 22572019-01-25 Sudakshina Das <sudi.das@arm.com>
2258
2259 * aarch64-tbl.h (QL_LDST_AT): Update macro.
2260 (aarch64_opcode): Change encoding for stg, stzg
2261 st2g and st2zg.
2262 * aarch64-asm-2.c: Regenerated.
2263 * aarch64-dis-2.c: Regenerated.
2264 * aarch64-opc-2.c: Regenerated.
2265
20a4ca55
SD		 22662019-01-25 Sudakshina Das <sudi.das@arm.com>
2267
2268 * aarch64-asm-2.c: Regenerated.
2269 * aarch64-dis-2.c: Likewise.
2270 * aarch64-opc-2.c: Likewise.
2271 * aarch64-tbl.h (aarch64_opcode): Add new stzgm.
2272
550fd7bf
SD		 22732019-01-25 Sudakshina Das <sudi.das@arm.com>
2274 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
2275
2276 * aarch64-asm.c (aarch64_ins_addr_simple_2): Remove.
2277 * aarch64-asm.h (ins_addr_simple_2): Likeiwse.
2278 * aarch64-dis.c (aarch64_ext_addr_simple_2): Likewise.
2279 * aarch64-dis.h (ext_addr_simple_2): Likewise.
2280 * aarch64-opc.c (operand_general_constraint_met_p): Remove
2281 case for ldstgv_indexed.
2282 (aarch64_print_operand): Remove case for AARCH64_OPND_ADDR_SIMPLE_2.
2283 * aarch64-tbl.h (struct aarch64_opcode): Remove ldgv and stgv.
2284 (AARCH64_OPERANDS): Remove ADDR_SIMPLE_2.
2285 * aarch64-asm-2.c: Regenerated.
2286 * aarch64-dis-2.c: Regenerated.
2287 * aarch64-opc-2.c: Regenerated.
2288
d9938630
NC		 22892019-01-23 Nick Clifton <nickc@redhat.com>
2290
2291 * po/pt_BR.po: Updated Brazilian Portuguese translation.
2292
375cd423
NC		 22932019-01-21 Nick Clifton <nickc@redhat.com>
2294
2295 * po/de.po: Updated German translation.
2296 * po/uk.po: Updated Ukranian translation.
2297
57299f48
CX		 22982019-01-20 Chenghua Xu <paul.hua.gm@gmail.com>
2299 * mips-dis.c (mips_arch_choices): Fix typo in
2300 gs464, gs464e and gs264e descriptors.
2301
f48dfe41
NC		 23022019-01-19 Nick Clifton <nickc@redhat.com>
2303
2304 * configure: Regenerate.
2305 * po/opcodes.pot: Regenerate.
2306
f974f26c
NC		 23072018-06-24 Nick Clifton <nickc@redhat.com>
2308
2309 2.32 branch created.
2310
39f286cd
JD		 23112019-01-09 John Darrington <john@darrington.wattle.id.au>
2312
448b8ca8
JD		 2313 * s12z-dis.c (print_insn_s12z): Do not dereference an operand
2314 if it is null.
2315 -dis.c (opr_emit_disassembly): Do not omit an index if it is
39f286cd
JD		 2316 zero.
2317
3107326d
AP		 23182019-01-09 Andrew Paprocki <andrew@ishiboo.com>
2319
2320 * configure: Regenerate.
2321
7e9ca91e
AM		 23222019-01-07 Alan Modra <amodra@gmail.com>
2323
2324 * configure: Regenerate.
2325 * po/POTFILES.in: Regenerate.
2326
ef1ad42b
JD		 23272019-01-03 John Darrington <john@darrington.wattle.id.au>
2328
2329 * s12z-opc.c: New file.
2330 * s12z-opc.h: New file.
2331 * s12z-dis.c: Removed all code not directly related to display
2332 of instructions. Used the interface provided by the new files
2333 instead.
2334 * Makefile.am (TARGET_LIBOPCODES_CFILES) Add s12z-opc.c.
7e9ca91e 2335 * Makefile.in: Regenerate.
ef1ad42b 2336 * configure.ac (bfd_s12z_arch): Correct the dependencies.
7e9ca91e 2337 * configure: Regenerate.
ef1ad42b 2338
82704155
AM		 23392019-01-01 Alan Modra <amodra@gmail.com>
2340
2341 Update year range in copyright notice of all files.
2342
d5c04e1b 2343For older changes see ChangeLog-2018
3499769a 2344\f
d5c04e1b 2345Copyright (C) 2019 Free Software Foundation, Inc.
3499769a
AM		 2346
2347Copying and distribution of this file, with or without modification,
2348are permitted in any medium without royalty provided the copyright
2349notice and this notice are preserved.
2350
2351Local Variables:
2352mode: change-log
2353left-margin: 8
2354fill-column: 74
2355version-control: never
2356End:
GDB Binutils - Deliverables
This page took 0.312664 seconds and 4 git commands to generate.