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Remove extraneous code.
[deliverable/binutils-gdb.git] / opcodes / arm-dis.c
CommitLineData
252b5132 1/* Instruction printing code for the ARM
01c7f630 2 Copyright (C) 1994, 95, 96, 97, 98, 99, 2000 Free Software Foundation, Inc.
252b5132
RH		 3 Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
4 Modification by James G. Smith (jsmith@cygnus.co.uk)
5
6This file is part of libopcodes.
7
8This program is free software; you can redistribute it and/or modify it under
9the terms of the GNU General Public License as published by the Free
10Software Foundation; either version 2 of the License, or (at your option)
11any later version.
12
13This program is distributed in the hope that it will be useful, but WITHOUT
14ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
15FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
16more details.
17
18You should have received a copy of the GNU General Public License
19along with this program; if not, write to the Free Software
20Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
21
cb6a5892 22#include "sysdep.h"
252b5132
RH		 23#include "dis-asm.h"
24#define DEFINE_TABLE
25#include "arm-opc.h"
26#include "coff/internal.h"
27#include "libcoff.h"
28#include "opintl.h"
29
30/* FIXME: This shouldn't be done here */
31#include "elf-bfd.h"
32#include "elf/internal.h"
33#include "elf/arm.h"
34
01c7f630 35#ifndef streq
58efb6c0 36#define streq(a,b) (strcmp ((a), (b)) == 0)
01c7f630 37#endif
58efb6c0 38
01c7f630 39#ifndef strneq
58efb6c0
NC		 40#define strneq(a,b,n) (strncmp ((a), (b), (n)) == 0)
41#endif
42
43#ifndef NUM_ELEM
44#define NUM_ELEM(a) (sizeof (a) / sizeof (a)[0])
01c7f630
NC		 45#endif
46
5876e06d 47static char * arm_conditional[] =
252b5132
RH		 48{"eq", "ne", "cs", "cc", "mi", "pl", "vs", "vc",
49 "hi", "ls", "ge", "lt", "gt", "le", "", "nv"};
50
58efb6c0
NC		 51typedef struct
52{
53 const char * name;
54 const char * description;
55 const char * reg_names[16];
56}
57arm_regname;
dd92f639 58
58efb6c0
NC		 59static arm_regname regnames[] =
60{
61 { "raw" , "Select raw register names",
62 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"}},
63 { "std", "Select register names used in ARM's ISA documentation",
64 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "sp", "lr", "pc" }},
65 { "apcs", "Select register names used in the APCS",
66 { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "v4", "v5", "v6", "sl", "fp", "ip", "sp", "lr", "pc" }},
67 { "atpcs", "Select register names used in the ATPCS",
68 { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "IP", "SP", "LR", "PC" }},
69 { "atpcs-special", "Select special register names used in the ATPCS",
70 { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "WR", "v5", "SB", "SL", "FP", "IP", "SP", "LR", "PC" }}
71};
72
73/* Default to standard register name set. */
74static unsigned int regname_selected = 1;
75
76#define NUM_ARM_REGNAMES NUM_ELEM (regnames)
77#define arm_regnames regnames[regname_selected].reg_names
252b5132 78
01c7f630
NC		 79static boolean force_thumb = false;
80
5876e06d 81static char * arm_fp_const[] =
252b5132
RH		 82{"0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0"};
83
5876e06d 84static char * arm_shift[] =
252b5132 85{"lsl", "lsr", "asr", "ror"};
01c7f630
NC		 86\f
87/* Forward declarations. */
88static void arm_decode_shift PARAMS ((long, fprintf_ftype, void *));
89static int print_insn_arm PARAMS ((bfd_vma, struct disassemble_info *, long));
90static int print_insn_thumb PARAMS ((bfd_vma, struct disassemble_info *, long));
01c7f630 91static void parse_disassembler_options PARAMS ((char *));
58efb6c0 92static int print_insn PARAMS ((bfd_vma, struct disassemble_info *, boolean));
01c7f630
NC		 93\f
94/* Functions. */
252b5132
RH		 95static void
96arm_decode_shift (given, func, stream)
97 long given;
98 fprintf_ftype func;
5876e06d 99 void * stream;
252b5132
RH		 100{
101 func (stream, "%s", arm_regnames[given & 0xf]);
5876e06d 102
252b5132
RH		 103 if ((given & 0xff0) != 0)
104 {
105 if ((given & 0x10) == 0)
106 {
107 int amount = (given & 0xf80) >> 7;
108 int shift = (given & 0x60) >> 5;
5876e06d 109
252b5132
RH		 110 if (amount == 0)
111 {
112 if (shift == 3)
113 {
114 func (stream, ", rrx");
115 return;
116 }
5876e06d 117
252b5132
RH		 118 amount = 32;
119 }
5876e06d 120
252b5132
RH		 121 func (stream, ", %s #%d", arm_shift[shift], amount);
122 }
123 else
124 func (stream, ", %s %s", arm_shift[(given & 0x60) >> 5],
125 arm_regnames[(given & 0xf00) >> 8]);
126 }
127}
128
129/* Print one instruction from PC on INFO->STREAM.
130 Return the size of the instruction (always 4 on ARM). */
252b5132
RH		 131static int
132print_insn_arm (pc, info, given)
5876e06d
NC		 133 bfd_vma pc;
134 struct disassemble_info * info;
135 long given;
252b5132
RH		 136{
137 struct arm_opcode * insn;
138 void * stream = info->stream;
139 fprintf_ftype func = info->fprintf_func;
140
141 for (insn = arm_opcodes; insn->assembler; insn++)
142 {
143 if ((given & insn->mask) == insn->value)
144 {
145 char * c;
146
147 for (c = insn->assembler; *c; c++)
148 {
149 if (*c == '%')
150 {
151 switch (*++c)
152 {
153 case '%':
154 func (stream, "%%");
155 break;
156
157 case 'a':
158 if (((given & 0x000f0000) == 0x000f0000)
159 && ((given & 0x02000000) == 0))
160 {
161 int offset = given & 0xfff;
162
163 func (stream, "[pc");
164
165 if (given & 0x01000000)
166 {
167 if ((given & 0x00800000) == 0)
168 offset = - offset;
169
170 /* pre-indexed */
171 func (stream, ", #%x]", offset);
172
173 offset += pc + 8;
174
58efb6c0
NC		 175 /* Cope with the possibility of write-back
176 being used. Probably a very dangerous thing
177 for the programmer to do, but who are we to
178 argue ? */
252b5132
RH		 179 if (given & 0x00200000)
180 func (stream, "!");
181 }
182 else
183 {
58efb6c0 184 /* Post indexed. */
252b5132
RH		 185 func (stream, "], #%x", offset);
186
58efb6c0 187 offset = pc + 8; /* ie ignore the offset. */
252b5132
RH		 188 }
189
190 func (stream, "\t; ");
191 info->print_address_func (offset, info);
192 }
193 else
194 {
195 func (stream, "[%s",
196 arm_regnames[(given >> 16) & 0xf]);
197 if ((given & 0x01000000) != 0)
198 {
199 if ((given & 0x02000000) == 0)
200 {
201 int offset = given & 0xfff;
202 if (offset)
203 func (stream, ", %s#%d",
204 (((given & 0x00800000) == 0)
205 ? "-" : ""), offset);
206 }
207 else
208 {
209 func (stream, ", %s",
210 (((given & 0x00800000) == 0)
211 ? "-" : ""));
212 arm_decode_shift (given, func, stream);
213 }
214
215 func (stream, "]%s",
216 ((given & 0x00200000) != 0) ? "!" : "");
217 }
218 else
219 {
220 if ((given & 0x02000000) == 0)
221 {
222 int offset = given & 0xfff;
223 if (offset)
224 func (stream, "], %s#%d",
225 (((given & 0x00800000) == 0)
226 ? "-" : ""), offset);
227 else
228 func (stream, "]");
229 }
230 else
231 {
232 func (stream, "], %s",
233 (((given & 0x00800000) == 0)
234 ? "-" : ""));
235 arm_decode_shift (given, func, stream);
236 }
237 }
238 }
239 break;
240
241 case 's':
242 if ((given & 0x004f0000) == 0x004f0000)
243 {
58efb6c0 244 /* PC relative with immediate offset. */
252b5132 245 int offset = ((given & 0xf00) >> 4) | (given & 0xf);
886796f9 246
252b5132
RH		 247 if ((given & 0x00800000) == 0)
248 offset = -offset;
886796f9
NC		 249
250 func (stream, "[pc, #%x]\t; ", offset);
251
252b5132
RH		 252 (*info->print_address_func)
253 (offset + pc + 8, info);
254 }
255 else
256 {
257 func (stream, "[%s",
258 arm_regnames[(given >> 16) & 0xf]);
259 if ((given & 0x01000000) != 0)
260 {
58efb6c0 261 /* Pre-indexed. */
252b5132
RH		 262 if ((given & 0x00400000) == 0x00400000)
263 {
58efb6c0 264 /* Immediate. */
252b5132
RH		 265 int offset = ((given & 0xf00) >> 4) | (given & 0xf);
266 if (offset)
267 func (stream, ", %s#%d",
268 (((given & 0x00800000) == 0)
269 ? "-" : ""), offset);
270 }
271 else
272 {
58efb6c0 273 /* Register. */
252b5132
RH		 274 func (stream, ", %s%s",
275 (((given & 0x00800000) == 0)
276 ? "-" : ""),
277 arm_regnames[given & 0xf]);
278 }
279
280 func (stream, "]%s",
281 ((given & 0x00200000) != 0) ? "!" : "");
282 }
283 else
284 {
58efb6c0 285 /* Post-indexed. */
252b5132
RH		 286 if ((given & 0x00400000) == 0x00400000)
287 {
58efb6c0 288 /* Immediate. */
252b5132
RH		 289 int offset = ((given & 0xf00) >> 4) | (given & 0xf);
290 if (offset)
291 func (stream, "], %s#%d",
292 (((given & 0x00800000) == 0)
293 ? "-" : ""), offset);
294 else
295 func (stream, "]");
296 }
297 else
298 {
58efb6c0 299 /* Register. */
252b5132
RH		 300 func (stream, "], %s%s",
301 (((given & 0x00800000) == 0)
302 ? "-" : ""),
303 arm_regnames[given & 0xf]);
304 }
305 }
306 }
307 break;
308
309 case 'b':
310 (*info->print_address_func)
311 (BDISP (given) * 4 + pc + 8, info);
312 break;
313
314 case 'c':
315 func (stream, "%s",
316 arm_conditional [(given >> 28) & 0xf]);
317 break;
318
319 case 'm':
320 {
321 int started = 0;
322 int reg;
323
324 func (stream, "{");
325 for (reg = 0; reg < 16; reg++)
326 if ((given & (1 << reg)) != 0)
327 {
328 if (started)
329 func (stream, ", ");
330 started = 1;
331 func (stream, "%s", arm_regnames[reg]);
332 }
333 func (stream, "}");
334 }
335 break;
336
337 case 'o':
338 if ((given & 0x02000000) != 0)
339 {
340 int rotate = (given & 0xf00) >> 7;
341 int immed = (given & 0xff);
9f20bbfd
NC		 342 immed = (((immed << (32 - rotate))
343 | (immed >> rotate)) & 0xffffffff);
344 func (stream, "#%d\t; 0x%x", immed, immed);
252b5132
RH		 345 }
346 else
347 arm_decode_shift (given, func, stream);
348 break;
349
350 case 'p':
351 if ((given & 0x0000f000) == 0x0000f000)
352 func (stream, "p");
353 break;
354
355 case 't':
356 if ((given & 0x01200000) == 0x00200000)
357 func (stream, "t");
358 break;
359
360 case 'h':
361 if ((given & 0x00000020) == 0x00000020)
362 func (stream, "h");
363 else
364 func (stream, "b");
365 break;
366
367 case 'A':
368 func (stream, "[%s", arm_regnames [(given >> 16) & 0xf]);
369 if ((given & 0x01000000) != 0)
370 {
371 int offset = given & 0xff;
372 if (offset)
373 func (stream, ", %s#%d]%s",
374 ((given & 0x00800000) == 0 ? "-" : ""),
375 offset * 4,
376 ((given & 0x00200000) != 0 ? "!" : ""));
377 else
378 func (stream, "]");
379 }
380 else
381 {
382 int offset = given & 0xff;
383 if (offset)
384 func (stream, "], %s#%d",
385 ((given & 0x00800000) == 0 ? "-" : ""),
386 offset * 4);
387 else
388 func (stream, "]");
389 }
390 break;
391
392 case 'C':
393 switch (given & 0x00090000)
394 {
395 default:
396 func (stream, "_???");
397 break;
398 case 0x90000:
399 func (stream, "_all");
400 break;
401 case 0x10000:
402 func (stream, "_ctl");
403 break;
404 case 0x80000:
405 func (stream, "_flg");
406 break;
407 }
408 break;
409
410 case 'F':
411 switch (given & 0x00408000)
412 {
413 case 0:
414 func (stream, "4");
415 break;
416 case 0x8000:
417 func (stream, "1");
418 break;
419 case 0x00400000:
420 func (stream, "2");
421 break;
422 default:
423 func (stream, "3");
424 }
425 break;
426
427 case 'P':
428 switch (given & 0x00080080)
429 {
430 case 0:
431 func (stream, "s");
432 break;
433 case 0x80:
434 func (stream, "d");
435 break;
436 case 0x00080000:
437 func (stream, "e");
438 break;
439 default:
440 func (stream, _("<illegal precision>"));
441 break;
442 }
443 break;
444 case 'Q':
445 switch (given & 0x00408000)
446 {
447 case 0:
448 func (stream, "s");
449 break;
450 case 0x8000:
451 func (stream, "d");
452 break;
453 case 0x00400000:
454 func (stream, "e");
455 break;
456 default:
457 func (stream, "p");
458 break;
459 }
460 break;
461 case 'R':
462 switch (given & 0x60)
463 {
464 case 0:
465 break;
466 case 0x20:
467 func (stream, "p");
468 break;
469 case 0x40:
470 func (stream, "m");
471 break;
472 default:
473 func (stream, "z");
474 break;
475 }
476 break;
477
478 case '0': case '1': case '2': case '3': case '4':
479 case '5': case '6': case '7': case '8': case '9':
480 {
481 int bitstart = *c++ - '0';
482 int bitend = 0;
483 while (*c >= '0' && *c <= '9')
484 bitstart = (bitstart * 10) + *c++ - '0';
485
486 switch (*c)
487 {
488 case '-':
489 c++;
58efb6c0 490
252b5132
RH		 491 while (*c >= '0' && *c <= '9')
492 bitend = (bitend * 10) + *c++ - '0';
58efb6c0 493
252b5132
RH		 494 if (!bitend)
495 abort ();
58efb6c0 496
252b5132
RH		 497 switch (*c)
498 {
499 case 'r':
500 {
501 long reg;
58efb6c0 502
252b5132
RH		 503 reg = given >> bitstart;
504 reg &= (2 << (bitend - bitstart)) - 1;
58efb6c0 505
252b5132
RH		 506 func (stream, "%s", arm_regnames[reg]);
507 }
508 break;
509 case 'd':
510 {
511 long reg;
58efb6c0 512
252b5132
RH		 513 reg = given >> bitstart;
514 reg &= (2 << (bitend - bitstart)) - 1;
58efb6c0 515
252b5132
RH		 516 func (stream, "%d", reg);
517 }
518 break;
519 case 'x':
520 {
521 long reg;
58efb6c0 522
252b5132
RH		 523 reg = given >> bitstart;
524 reg &= (2 << (bitend - bitstart)) - 1;
58efb6c0 525
252b5132 526 func (stream, "0x%08x", reg);
5876e06d 527
58efb6c0
NC		 528 /* Some SWI instructions have special
529 meanings. */
5876e06d
NC		 530 if ((given & 0x0fffffff) == 0x0FF00000)
531 func (stream, "\t; IMB");
532 else if ((given & 0x0fffffff) == 0x0FF00001)
533 func (stream, "\t; IMBRange");
252b5132
RH		 534 }
535 break;
cfbd315c
DL		 536 case 'X':
537 {
538 long reg;
58efb6c0 539
cfbd315c
DL		 540 reg = given >> bitstart;
541 reg &= (2 << (bitend - bitstart)) - 1;
58efb6c0 542
cfbd315c
DL		 543 func (stream, "%01x", reg & 0xf);
544 }
545 break;
252b5132
RH		 546 case 'f':
547 {
548 long reg;
58efb6c0 549
252b5132
RH		 550 reg = given >> bitstart;
551 reg &= (2 << (bitend - bitstart)) - 1;
58efb6c0 552
252b5132
RH		 553 if (reg > 7)
554 func (stream, "#%s",
555 arm_fp_const[reg & 7]);
556 else
557 func (stream, "f%d", reg);
558 }
559 break;
560 default:
561 abort ();
562 }
563 break;
58efb6c0 564
252b5132
RH		 565 case '`':
566 c++;
567 if ((given & (1 << bitstart)) == 0)
568 func (stream, "%c", *c);
569 break;
570 case '\'':
571 c++;
572 if ((given & (1 << bitstart)) != 0)
573 func (stream, "%c", *c);
574 break;
575 case '?':
576 ++c;
577 if ((given & (1 << bitstart)) != 0)
578 func (stream, "%c", *c++);
579 else
580 func (stream, "%c", *++c);
581 break;
582 default:
583 abort ();
584 }
585 break;
586
587 default:
588 abort ();
589 }
590 }
591 }
592 else
593 func (stream, "%c", *c);
594 }
595 return 4;
596 }
597 }
598 abort ();
599}
600
601/* Print one instruction from PC on INFO->STREAM.
602 Return the size of the instruction. */
252b5132
RH		 603static int
604print_insn_thumb (pc, info, given)
5876e06d
NC		 605 bfd_vma pc;
606 struct disassemble_info * info;
607 long given;
252b5132 608{
5876e06d
NC		 609 struct thumb_opcode * insn;
610 void * stream = info->stream;
611 fprintf_ftype func = info->fprintf_func;
252b5132
RH		 612
613 for (insn = thumb_opcodes; insn->assembler; insn++)
614 {
615 if ((given & insn->mask) == insn->value)
616 {
5876e06d 617 char * c = insn->assembler;
252b5132 618
58efb6c0
NC		 619 /* Special processing for Thumb 2 instruction BL sequence: */
620 if (!*c) /* Check for empty (not NULL) assembler string. */
252b5132
RH		 621 {
622 info->bytes_per_chunk = 4;
623 info->bytes_per_line = 4;
624
a3d9c82d
NC		 625 func (stream, "bl\t");
626
58efb6c0 627 info->print_address_func (BDISP23 (given) * 2 + pc + 4, info);
252b5132
RH		 628 return 4;
629 }
630 else
631 {
632 info->bytes_per_chunk = 2;
633 info->bytes_per_line = 4;
634
635 given &= 0xffff;
58efb6c0 636
252b5132
RH		 637 for (; *c; c++)
638 {
639 if (*c == '%')
640 {
641 int domaskpc = 0;
642 int domasklr = 0;
5876e06d 643
252b5132
RH		 644 switch (*++c)
645 {
646 case '%':
647 func (stream, "%%");
648 break;
649
650 case 'S':
651 {
652 long reg;
58efb6c0 653
252b5132
RH		 654 reg = (given >> 3) & 0x7;
655 if (given & (1 << 6))
656 reg += 8;
58efb6c0 657
252b5132
RH		 658 func (stream, "%s", arm_regnames[reg]);
659 }
660 break;
661
662 case 'D':
663 {
664 long reg;
5876e06d 665
252b5132
RH		 666 reg = given & 0x7;
667 if (given & (1 << 7))
668 reg += 8;
58efb6c0 669
252b5132
RH		 670 func (stream, "%s", arm_regnames[reg]);
671 }
672 break;
673
674 case 'T':
675 func (stream, "%s",
676 arm_conditional [(given >> 8) & 0xf]);
677 break;
678
679 case 'N':
680 if (given & (1 << 8))
681 domasklr = 1;
58efb6c0 682 /* Fall through. */
252b5132
RH		 683 case 'O':
684 if (*c == 'O' && (given & (1 << 8)))
685 domaskpc = 1;
58efb6c0 686 /* Fall through. */
252b5132
RH		 687 case 'M':
688 {
689 int started = 0;
690 int reg;
5876e06d 691
252b5132 692 func (stream, "{");
58efb6c0 693
252b5132
RH		 694 /* It would be nice if we could spot
695 ranges, and generate the rS-rE format: */
696 for (reg = 0; (reg < 8); reg++)
697 if ((given & (1 << reg)) != 0)
698 {
699 if (started)
700 func (stream, ", ");
701 started = 1;
702 func (stream, "%s", arm_regnames[reg]);
703 }
704
705 if (domasklr)
706 {
707 if (started)
708 func (stream, ", ");
709 started = 1;
710 func (stream, "lr");
711 }
712
713 if (domaskpc)
714 {
715 if (started)
716 func (stream, ", ");
717 func (stream, "pc");
718 }
719
720 func (stream, "}");
721 }
722 break;
723
724
725 case '0': case '1': case '2': case '3': case '4':
726 case '5': case '6': case '7': case '8': case '9':
727 {
728 int bitstart = *c++ - '0';
729 int bitend = 0;
5876e06d 730
252b5132
RH		 731 while (*c >= '0' && *c <= '9')
732 bitstart = (bitstart * 10) + *c++ - '0';
733
734 switch (*c)
735 {
736 case '-':
737 {
738 long reg;
5876e06d 739
252b5132
RH		 740 c++;
741 while (*c >= '0' && *c <= '9')
742 bitend = (bitend * 10) + *c++ - '0';
743 if (!bitend)
744 abort ();
745 reg = given >> bitstart;
746 reg &= (2 << (bitend - bitstart)) - 1;
747 switch (*c)
748 {
749 case 'r':
750 func (stream, "%s", arm_regnames[reg]);
751 break;
752
753 case 'd':
754 func (stream, "%d", reg);
755 break;
756
757 case 'H':
758 func (stream, "%d", reg << 1);
759 break;
760
761 case 'W':
762 func (stream, "%d", reg << 2);
763 break;
764
765 case 'a':
766 /* PC-relative address -- the bottom two
58efb6c0
NC		 767 bits of the address are dropped
768 before the calculation. */
252b5132
RH		 769 info->print_address_func
770 (((pc + 4) & ~3) + (reg << 2), info);
771 break;
772
773 case 'x':
774 func (stream, "0x%04x", reg);
775 break;
776
777 case 'I':
778 reg = ((reg ^ (1 << bitend)) - (1 << bitend));
779 func (stream, "%d", reg);
780 break;
781
782 case 'B':
783 reg = ((reg ^ (1 << bitend)) - (1 << bitend));
784 (*info->print_address_func)
785 (reg * 2 + pc + 4, info);
786 break;
787
788 default:
5876e06d 789 abort ();
252b5132
RH		 790 }
791 }
792 break;
793
794 case '\'':
795 c++;
796 if ((given & (1 << bitstart)) != 0)
797 func (stream, "%c", *c);
798 break;
799
800 case '?':
801 ++c;
802 if ((given & (1 << bitstart)) != 0)
803 func (stream, "%c", *c++);
804 else
805 func (stream, "%c", *++c);
806 break;
807
808 default:
5876e06d 809 abort ();
252b5132
RH		 810 }
811 }
812 break;
813
814 default:
815 abort ();
816 }
817 }
818 else
819 func (stream, "%c", *c);
820 }
821 }
822 return 2;
823 }
824 }
825
58efb6c0 826 /* No match. */
252b5132
RH		 827 abort ();
828}
829
58efb6c0 830/* Parse an individual disassembler option. */
a3d9c82d
NC		 831void
832parse_arm_disassembler_option (option)
01c7f630 833 char * option;
dd92f639 834{
01c7f630 835 if (option == NULL)
dd92f639
NC		 836 return;
837
01c7f630 838 if (strneq (option, "reg-names-", 10))
dd92f639 839 {
58efb6c0
NC		 840 int i;
841
01c7f630 842 option += 10;
58efb6c0
NC		 843
844 for (i = NUM_ARM_REGNAMES; i--;)
845 if (streq (option, regnames[i].name))
846 {
847 regname_selected = i;
848 break;
849 }
dd92f639 850
58efb6c0
NC		 851 if (i < 0)
852 fprintf (stderr, _("Unrecognised register name set: %s\n"), option);
dd92f639 853 }
01c7f630
NC		 854 else if (streq (option, "force-thumb"))
855 force_thumb = 1;
856 else if (streq (option, "no-force-thumb"))
857 force_thumb = 0;
dd92f639 858 else
58efb6c0 859 fprintf (stderr, _("Unrecognised disassembler option: %s\n"), option);
dd92f639
NC		 860
861 return;
862}
863
58efb6c0 864/* Parse the string of disassembler options, spliting it at whitespaces. */
01c7f630
NC		 865static void
866parse_disassembler_options (options)
867 char * options;
868{
869 char * space;
870
871 if (options == NULL)
872 return;
873
874 do
875 {
876 space = strchr (options, ' ');
877
878 if (space)
879 {
880 * space = '\0';
a3d9c82d 881 parse_arm_disassembler_option (options);
01c7f630
NC		 882 * space = ' ';
883 options = space + 1;
884 }
885 else
a3d9c82d 886 parse_arm_disassembler_option (options);
01c7f630
NC		 887 }
888 while (space);
889}
890
58efb6c0
NC		 891/* NOTE: There are no checks in these routines that
892 the relevant number of data bytes exist. */
893static int
894print_insn (pc, info, little)
252b5132 895 bfd_vma pc;
5876e06d 896 struct disassemble_info * info;
58efb6c0 897 boolean little;
252b5132
RH		 898{
899 unsigned char b[4];
900 long given;
901 int status;
252b5132 902 int is_thumb;
58efb6c0 903
dd92f639
NC		 904 if (info->disassembler_options)
905 {
906 parse_disassembler_options (info->disassembler_options);
907
58efb6c0 908 /* To avoid repeated parsing of these options, we remove them here. */
dd92f639
NC		 909 info->disassembler_options = NULL;
910 }
911
01c7f630
NC		 912 is_thumb = force_thumb;
913
914 if (!is_thumb && info->symbols != NULL)
252b5132 915 {
5876e06d
NC		 916 if (bfd_asymbol_flavour (*info->symbols) == bfd_target_coff_flavour)
917 {
2f0ca46a
NC		 918 coff_symbol_type * cs;
919
5876e06d
NC		 920 cs = coffsymbol (*info->symbols);
921 is_thumb = ( cs->native->u.syment.n_sclass == C_THUMBEXT
922 || cs->native->u.syment.n_sclass == C_THUMBSTAT
923 || cs->native->u.syment.n_sclass == C_THUMBLABEL
924 || cs->native->u.syment.n_sclass == C_THUMBEXTFUNC
925 || cs->native->u.syment.n_sclass == C_THUMBSTATFUNC);
926 }
927 else if (bfd_asymbol_flavour (*info->symbols) == bfd_target_elf_flavour)
928 {
2f0ca46a 929 elf_symbol_type * es;
58efb6c0 930 unsigned int type;
2f0ca46a 931
5876e06d 932 es = *(elf_symbol_type **)(info->symbols);
58efb6c0
NC		 933 type = ELF_ST_TYPE (es->internal_elf_sym.st_info);
934
935 is_thumb = (type == STT_ARM_TFUNC) || (type == STT_ARM_16BIT);
5876e06d
NC		 936 }
937 }
58efb6c0 938
252b5132 939 info->bytes_per_chunk = 4;
58efb6c0 940 info->display_endian = little ? BFD_ENDIAN_LITTLE : BFD_ENDIAN_BIG;
252b5132 941
58efb6c0 942 if (little)
252b5132 943 {
58efb6c0
NC		 944 status = info->read_memory_func (pc, (bfd_byte *) &b[0], 4, info);
945 if (status != 0 && is_thumb)
946 {
947 info->bytes_per_chunk = 2;
948
949 status = info->read_memory_func (pc, (bfd_byte *) b, 2, info);
950 b[3] = b[2] = 0;
951 }
952
953 if (status != 0)
954 {
955 info->memory_error_func (status, pc, info);
956 return -1;
957 }
958
959 given = (b[0]) | (b[1] << 8) | (b[2] << 16) | (b[3] << 24);
252b5132 960 }
58efb6c0 961 else
252b5132 962 {
58efb6c0
NC		 963 status = info->read_memory_func
964 (pc & ~ 0x3, (bfd_byte *) &b[0], 4, info);
965 if (status != 0)
252b5132 966 {
58efb6c0
NC		 967 info->memory_error_func (status, pc, info);
968 return -1;
969 }
970
971 if (is_thumb)
972 {
973 if (pc & 0x2)
252b5132 974 {
58efb6c0
NC		 975 given = (b[2] << 8) | b[3];
976
977 status = info->read_memory_func
978 ((pc + 4) & ~ 0x3, (bfd_byte *) b, 4, info);
979 if (status != 0)
980 {
981 info->memory_error_func (status, pc + 4, info);
982 return -1;
983 }
984
985 given |= (b[0] << 24) | (b[1] << 16);
252b5132 986 }
58efb6c0
NC		 987 else
988 given = (b[0] << 8) | b[1] | (b[2] << 24) | (b[3] << 16);
252b5132
RH		 989 }
990 else
58efb6c0 991 given = (b[0] << 24) | (b[1] << 16) | (b[2] << 8) | (b[3]);
252b5132 992 }
58efb6c0 993
252b5132 994 if (is_thumb)
5876e06d 995 status = print_insn_thumb (pc, info, given);
252b5132 996 else
5876e06d 997 status = print_insn_arm (pc, info, given);
252b5132
RH		 998
999 return status;
1000}
1001
1002int
58efb6c0 1003print_insn_big_arm (pc, info)
252b5132
RH		 1004 bfd_vma pc;
1005 struct disassemble_info * info;
1006{
58efb6c0
NC		 1007 return print_insn (pc, info, false);
1008}
01c7f630 1009
58efb6c0
NC		 1010int
1011print_insn_little_arm (pc, info)
1012 bfd_vma pc;
1013 struct disassemble_info * info;
1014{
1015 return print_insn (pc, info, true);
1016}
252b5132 1017
58efb6c0
NC		 1018void
1019print_arm_disassembler_options (FILE * stream)
1020{
1021 int i;
252b5132 1022
58efb6c0
NC		 1023 fprintf (stream, _("\n\
1024The following ARM specific disassembler options are supported for use with\n\
1025the -M switch:\n"));
01c7f630 1026
58efb6c0
NC		 1027 for (i = NUM_ARM_REGNAMES; i--;)
1028 fprintf (stream, " reg-names-%s %*c%s\n",
1029 regnames[i].name,
1030 14 - strlen (regnames[i].name), ' ',
1031 regnames[i].description);
1032
1033 fprintf (stream, " force-thumb Assume all insns are Thumb insns\n");
1034 fprintf (stream, " no-force-thumb Examine preceeding label to determine an insn's type\n\n");
252b5132 1035}
GDB Binutils - Deliverables
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