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Handle multiple target events before commit resume
[deliverable/binutils-gdb.git] / opcodes / bfin-dis.c
CommitLineData
4b7f6baa 1/* Disassemble ADI Blackfin Instructions.
82704155 2 Copyright (C) 2005-2019 Free Software Foundation, Inc.
4b7f6baa 3
9b201bb5
NC		 4 This file is part of libopcodes.
5
6 This library is free software; you can redistribute it and/or modify
4b7f6baa 7 it under the terms of the GNU General Public License as published by
9b201bb5
NC		 8 the Free Software Foundation; either version 3, or (at your option)
9 any later version.
4b7f6baa 10
9b201bb5
NC		 11 It is distributed in the hope that it will be useful, but WITHOUT
12 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
13 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
14 License for more details.
4b7f6baa
CM		 15
16 You should have received a copy of the GNU General Public License
17 along with this program; if not, write to the Free Software
18 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
19 MA 02110-1301, USA. */
20
5eb3690e 21#include "sysdep.h"
4b7f6baa 22#include <stdio.h>
4b7f6baa
CM		 23
24#include "opcode/bfin.h"
25
4b7f6baa
CM		 26#ifndef PRINTF
27#define PRINTF printf
28#endif
29
30#ifndef EXIT
31#define EXIT exit
32#endif
33
34typedef long TIword;
35
2fd2b153
AM		 36#define SIGNBIT(bits) (1ul << ((bits) - 1))
37#define MASKBITS(val, bits) ((val) & ((1ul << (bits)) - 1))
38#define SIGNEXTEND(v, n) ((MASKBITS (v, n) ^ SIGNBIT (n)) - SIGNBIT (n))
4b7f6baa 39
88c1242d 40#include "disassemble.h"
b7d48530 41
b21c9cb4
BS		 42typedef unsigned int bu32;
43
703ec4e8
MF		 44struct private
45{
a4e600b2 46 TIword iw0;
60ac5798 47 bfd_boolean comment, parallel;
703ec4e8 48};
528c6277 49
4b7f6baa
CM		 50typedef enum
51{
52 c_0, c_1, c_4, c_2, c_uimm2, c_uimm3, c_imm3, c_pcrel4,
086134ec
BS		 53 c_imm4, c_uimm4s4, c_uimm4s4d, c_uimm4, c_uimm4s2, c_negimm5s4, c_imm5, c_imm5d, c_uimm5, c_imm6,
54 c_imm7, c_imm7d, c_imm8, c_uimm8, c_pcrel8, c_uimm8s4, c_pcrel8s4, c_lppcrel10, c_pcrel10,
55 c_pcrel12, c_imm16s4, c_luimm16, c_imm16, c_imm16d, c_huimm16, c_rimm16, c_imm16s2, c_uimm16s4,
56 c_uimm16s4d, c_uimm16, c_pcrel24, c_uimm32, c_imm32, c_huimm32, c_huimm32e,
4b7f6baa
CM		 57} const_forms_t;
58
528c6277 59static const struct
4b7f6baa 60{
528c6277
MF		 61 const char *name;
62 const int nbits;
63 const char reloc;
64 const char issigned;
65 const char pcrel;
66 const char scale;
67 const char offset;
68 const char negative;
69 const char positive;
70 const char decimal;
71 const char leading;
72 const char exact;
4b7f6baa
CM		 73} constant_formats[] =
74{
086134ec
BS		 75 { "0", 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0},
76 { "1", 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0},
77 { "4", 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0},
78 { "2", 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0},
79 { "uimm2", 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
80 { "uimm3", 3, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
81 { "imm3", 3, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0},
82 { "pcrel4", 4, 1, 0, 1, 1, 0, 0, 0, 0, 0, 0},
83 { "imm4", 4, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0},
84 { "uimm4s4", 4, 0, 0, 0, 2, 0, 0, 1, 0, 0, 0},
85 { "uimm4s4d", 4, 0, 0, 0, 2, 0, 0, 1, 1, 0, 0},
86 { "uimm4", 4, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
87 { "uimm4s2", 4, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0},
88 { "negimm5s4", 5, 0, 1, 0, 2, 0, 1, 0, 0, 0, 0},
89 { "imm5", 5, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0},
90 { "imm5d", 5, 0, 1, 0, 0, 0, 0, 0, 1, 0, 0},
91 { "uimm5", 5, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
92 { "imm6", 6, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0},
93 { "imm7", 7, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0},
94 { "imm7d", 7, 0, 1, 0, 0, 0, 0, 0, 1, 3, 0},
95 { "imm8", 8, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0},
96 { "uimm8", 8, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
97 { "pcrel8", 8, 1, 0, 1, 1, 0, 0, 0, 0, 0, 0},
98 { "uimm8s4", 8, 0, 0, 0, 2, 0, 0, 0, 0, 0, 0},
99 { "pcrel8s4", 8, 1, 1, 1, 2, 0, 0, 0, 0, 0, 0},
100 { "lppcrel10", 10, 1, 0, 1, 1, 0, 0, 0, 0, 0, 0},
101 { "pcrel10", 10, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0},
102 { "pcrel12", 12, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0},
103 { "imm16s4", 16, 0, 1, 0, 2, 0, 0, 0, 0, 0, 0},
104 { "luimm16", 16, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0},
105 { "imm16", 16, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0},
106 { "imm16d", 16, 0, 1, 0, 0, 0, 0, 0, 1, 3, 0},
107 { "huimm16", 16, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0},
108 { "rimm16", 16, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0},
109 { "imm16s2", 16, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0},
110 { "uimm16s4", 16, 0, 0, 0, 2, 0, 0, 0, 0, 0, 0},
111 { "uimm16s4d", 16, 0, 0, 0, 2, 0, 0, 0, 1, 0, 0},
112 { "uimm16", 16, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
113 { "pcrel24", 24, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0},
114 { "uimm32", 32, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
115 { "imm32", 32, 0, 1, 0, 0, 0, 0, 0, 1, 3, 0},
116 { "huimm32", 32, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0},
117 { "huimm32e", 32, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1},
4b7f6baa
CM		 118};
119
528c6277
MF		 120static const char *
121fmtconst (const_forms_t cf, TIword x, bfd_vma pc, disassemble_info *outf)
4b7f6baa
CM		 122{
123 static char buf[60];
124
125 if (constant_formats[cf].reloc)
126 {
2fd2b153
AM		 127 bfd_vma ea;
128
129 if (constant_formats[cf].pcrel)
130 x = SIGNEXTEND (x, constant_formats[cf].nbits);
131 ea = (x + constant_formats[cf].offset) << constant_formats[cf].scale;
4b7f6baa
CM		 132 if (constant_formats[cf].pcrel)
133 ea += pc;
134
602427c4
MF		 135 /* truncate to 32-bits for proper symbol lookup/matching */
136 ea = (bu32)ea;
7a360e83 137
602427c4
MF		 138 if (outf->symbol_at_address_func (ea, outf) || !constant_formats[cf].exact)
139 {
086134ec
BS		 140 outf->print_address_func (ea, outf);
141 return "";
602427c4
MF		 142 }
143 else
144 {
0af1713e 145 sprintf (buf, "%lx", (unsigned long) x);
086134ec 146 return buf;
602427c4 147 }
4b7f6baa
CM		 148 }
149
150 /* Negative constants have an implied sign bit. */
151 if (constant_formats[cf].negative)
152 {
153 int nb = constant_formats[cf].nbits + 1;
b7d48530 154
4b7f6baa
CM		 155 x = x | (1 << constant_formats[cf].nbits);
156 x = SIGNEXTEND (x, nb);
157 }
2fd2b153
AM		 158 else if (constant_formats[cf].issigned)
159 x = SIGNEXTEND (x, constant_formats[cf].nbits);
4b7f6baa
CM		 160
161 if (constant_formats[cf].offset)
162 x += constant_formats[cf].offset;
163
164 if (constant_formats[cf].scale)
165 x <<= constant_formats[cf].scale;
166
086134ec 167 if (constant_formats[cf].decimal)
5de10af0 168 sprintf (buf, "%*li", constant_formats[cf].leading, x);
4b7f6baa 169 else
086134ec
BS		 170 {
171 if (constant_formats[cf].issigned && x < 0)
b6518b38 172 sprintf (buf, "-0x%lx", (unsigned long)(- x));
086134ec 173 else
0af1713e 174 sprintf (buf, "0x%lx", (unsigned long) x);
086134ec 175 }
4b7f6baa
CM		 176
177 return buf;
178}
179
b21c9cb4
BS		 180static bu32
181fmtconst_val (const_forms_t cf, unsigned int x, unsigned int pc)
182{
183 if (0 && constant_formats[cf].reloc)
184 {
2fd2b153
AM		 185 bu32 ea;
186
187 if (constant_formats[cf].pcrel)
188 x = SIGNEXTEND (x, constant_formats[cf].nbits);
189 ea = (x + constant_formats[cf].offset) << constant_formats[cf].scale;
b21c9cb4 190 if (constant_formats[cf].pcrel)
086134ec 191 ea += pc;
b21c9cb4
BS		 192
193 return ea;
194 }
195
196 /* Negative constants have an implied sign bit. */
197 if (constant_formats[cf].negative)
198 {
199 int nb = constant_formats[cf].nbits + 1;
2fd2b153 200 x = x | (1u << constant_formats[cf].nbits);
b21c9cb4
BS		 201 x = SIGNEXTEND (x, nb);
202 }
203 else if (constant_formats[cf].issigned)
204 x = SIGNEXTEND (x, constant_formats[cf].nbits);
205
206 x += constant_formats[cf].offset;
207 x <<= constant_formats[cf].scale;
208
209 return x;
210}
211
4b7f6baa
CM		 212enum machine_registers
213{
214 REG_RL0, REG_RL1, REG_RL2, REG_RL3, REG_RL4, REG_RL5, REG_RL6, REG_RL7,
215 REG_RH0, REG_RH1, REG_RH2, REG_RH3, REG_RH4, REG_RH5, REG_RH6, REG_RH7,
216 REG_R0, REG_R1, REG_R2, REG_R3, REG_R4, REG_R5, REG_R6, REG_R7,
217 REG_R1_0, REG_R3_2, REG_R5_4, REG_R7_6, REG_P0, REG_P1, REG_P2, REG_P3,
218 REG_P4, REG_P5, REG_SP, REG_FP, REG_A0x, REG_A1x, REG_A0w, REG_A1w,
219 REG_A0, REG_A1, REG_I0, REG_I1, REG_I2, REG_I3, REG_M0, REG_M1,
220 REG_M2, REG_M3, REG_B0, REG_B1, REG_B2, REG_B3, REG_L0, REG_L1,
221 REG_L2, REG_L3,
222 REG_AZ, REG_AN, REG_AC0, REG_AC1, REG_AV0, REG_AV1, REG_AV0S, REG_AV1S,
223 REG_AQ, REG_V, REG_VS,
224 REG_sftreset, REG_omode, REG_excause, REG_emucause, REG_idle_req, REG_hwerrcause, REG_CC, REG_LC0,
43a6aa65 225 REG_LC1, REG_ASTAT, REG_RETS, REG_LT0, REG_LB0, REG_LT1, REG_LB1,
4b7f6baa
CM		 226 REG_CYCLES, REG_CYCLES2, REG_USP, REG_SEQSTAT, REG_SYSCFG, REG_RETI, REG_RETX, REG_RETN,
227 REG_RETE, REG_EMUDAT, REG_BR0, REG_BR1, REG_BR2, REG_BR3, REG_BR4, REG_BR5, REG_BR6,
228 REG_BR7, REG_PL0, REG_PL1, REG_PL2, REG_PL3, REG_PL4, REG_PL5, REG_SLP, REG_FLP,
229 REG_PH0, REG_PH1, REG_PH2, REG_PH3, REG_PH4, REG_PH5, REG_SHP, REG_FHP,
230 REG_IL0, REG_IL1, REG_IL2, REG_IL3, REG_ML0, REG_ML1, REG_ML2, REG_ML3,
231 REG_BL0, REG_BL1, REG_BL2, REG_BL3, REG_LL0, REG_LL1, REG_LL2, REG_LL3,
232 REG_IH0, REG_IH1, REG_IH2, REG_IH3, REG_MH0, REG_MH1, REG_MH2, REG_MH3,
233 REG_BH0, REG_BH1, REG_BH2, REG_BH3, REG_LH0, REG_LH1, REG_LH2, REG_LH3,
22215ae0 234 REG_AC0_COPY, REG_V_COPY, REG_RND_MOD,
4b7f6baa
CM		 235 REG_LASTREG,
236};
237
238enum reg_class
239{
240 rc_dregs_lo, rc_dregs_hi, rc_dregs, rc_dregs_pair, rc_pregs, rc_spfp, rc_dregs_hilo, rc_accum_ext,
241 rc_accum_word, rc_accum, rc_iregs, rc_mregs, rc_bregs, rc_lregs, rc_dpregs, rc_gregs,
242 rc_regs, rc_statbits, rc_ignore_bits, rc_ccstat, rc_counters, rc_dregs2_sysregs1, rc_open, rc_sysregs2,
243 rc_sysregs3, rc_allregs,
244 LIM_REG_CLASSES
245};
246
69b8ea4a 247static const char * const reg_names[] =
4b7f6baa
CM		 248{
249 "R0.L", "R1.L", "R2.L", "R3.L", "R4.L", "R5.L", "R6.L", "R7.L",
250 "R0.H", "R1.H", "R2.H", "R3.H", "R4.H", "R5.H", "R6.H", "R7.H",
251 "R0", "R1", "R2", "R3", "R4", "R5", "R6", "R7",
252 "R1:0", "R3:2", "R5:4", "R7:6", "P0", "P1", "P2", "P3",
086134ec 253 "P4", "P5", "SP", "FP", "A0.X", "A1.X", "A0.W", "A1.W",
4b7f6baa
CM		 254 "A0", "A1", "I0", "I1", "I2", "I3", "M0", "M1",
255 "M2", "M3", "B0", "B1", "B2", "B3", "L0", "L1",
256 "L2", "L3",
257 "AZ", "AN", "AC0", "AC1", "AV0", "AV1", "AV0S", "AV1S",
258 "AQ", "V", "VS",
259 "sftreset", "omode", "excause", "emucause", "idle_req", "hwerrcause", "CC", "LC0",
43a6aa65 260 "LC1", "ASTAT", "RETS", "LT0", "LB0", "LT1", "LB1",
4b7f6baa
CM		 261 "CYCLES", "CYCLES2", "USP", "SEQSTAT", "SYSCFG", "RETI", "RETX", "RETN",
262 "RETE", "EMUDAT",
263 "R0.B", "R1.B", "R2.B", "R3.B", "R4.B", "R5.B", "R6.B", "R7.B",
264 "P0.L", "P1.L", "P2.L", "P3.L", "P4.L", "P5.L", "SP.L", "FP.L",
265 "P0.H", "P1.H", "P2.H", "P3.H", "P4.H", "P5.H", "SP.H", "FP.H",
266 "I0.L", "I1.L", "I2.L", "I3.L", "M0.L", "M1.L", "M2.L", "M3.L",
267 "B0.L", "B1.L", "B2.L", "B3.L", "L0.L", "L1.L", "L2.L", "L3.L",
268 "I0.H", "I1.H", "I2.H", "I3.H", "M0.H", "M1.H", "M2.H", "M3.H",
269 "B0.H", "B1.H", "B2.H", "B3.H", "L0.H", "L1.H", "L2.H", "L3.H",
22215ae0 270 "AC0_COPY", "V_COPY", "RND_MOD",
4b7f6baa
CM		 271 "LASTREG",
272 0
273};
274
275#define REGNAME(x) ((x) < REG_LASTREG ? (reg_names[x]) : "...... Illegal register .......")
276
277/* RL(0..7). */
69b8ea4a 278static const enum machine_registers decode_dregs_lo[] =
4b7f6baa
CM		 279{
280 REG_RL0, REG_RL1, REG_RL2, REG_RL3, REG_RL4, REG_RL5, REG_RL6, REG_RL7,
281};
282
b7d48530 283#define dregs_lo(x) REGNAME (decode_dregs_lo[(x) & 7])
4b7f6baa
CM		 284
285/* RH(0..7). */
69b8ea4a 286static const enum machine_registers decode_dregs_hi[] =
4b7f6baa
CM		 287{
288 REG_RH0, REG_RH1, REG_RH2, REG_RH3, REG_RH4, REG_RH5, REG_RH6, REG_RH7,
289};
290
b7d48530 291#define dregs_hi(x) REGNAME (decode_dregs_hi[(x) & 7])
4b7f6baa
CM		 292
293/* R(0..7). */
69b8ea4a 294static const enum machine_registers decode_dregs[] =
4b7f6baa
CM		 295{
296 REG_R0, REG_R1, REG_R2, REG_R3, REG_R4, REG_R5, REG_R6, REG_R7,
297};
298
b7d48530 299#define dregs(x) REGNAME (decode_dregs[(x) & 7])
4b7f6baa
CM		 300
301/* R BYTE(0..7). */
69b8ea4a 302static const enum machine_registers decode_dregs_byte[] =
4b7f6baa
CM		 303{
304 REG_BR0, REG_BR1, REG_BR2, REG_BR3, REG_BR4, REG_BR5, REG_BR6, REG_BR7,
305};
306
b7d48530 307#define dregs_byte(x) REGNAME (decode_dregs_byte[(x) & 7])
4b7f6baa
CM		 308
309/* P(0..5) SP FP. */
69b8ea4a 310static const enum machine_registers decode_pregs[] =
4b7f6baa
CM		 311{
312 REG_P0, REG_P1, REG_P2, REG_P3, REG_P4, REG_P5, REG_SP, REG_FP,
313};
314
b7d48530
NC		 315#define pregs(x) REGNAME (decode_pregs[(x) & 7])
316#define spfp(x) REGNAME (decode_spfp[(x) & 1])
602427c4 317#define dregs_hilo(x, i) REGNAME (decode_dregs_hilo[((i) << 3) | (x)])
b7d48530
NC		 318#define accum_ext(x) REGNAME (decode_accum_ext[(x) & 1])
319#define accum_word(x) REGNAME (decode_accum_word[(x) & 1])
320#define accum(x) REGNAME (decode_accum[(x) & 1])
4b7f6baa
CM		 321
322/* I(0..3). */
69b8ea4a 323static const enum machine_registers decode_iregs[] =
4b7f6baa
CM		 324{
325 REG_I0, REG_I1, REG_I2, REG_I3,
326};
327
b7d48530 328#define iregs(x) REGNAME (decode_iregs[(x) & 3])
4b7f6baa
CM		 329
330/* M(0..3). */
69b8ea4a 331static const enum machine_registers decode_mregs[] =
4b7f6baa
CM		 332{
333 REG_M0, REG_M1, REG_M2, REG_M3,
334};
335
b7d48530
NC		 336#define mregs(x) REGNAME (decode_mregs[(x) & 3])
337#define bregs(x) REGNAME (decode_bregs[(x) & 3])
338#define lregs(x) REGNAME (decode_lregs[(x) & 3])
4b7f6baa
CM		 339
340/* dregs pregs. */
69b8ea4a 341static const enum machine_registers decode_dpregs[] =
4b7f6baa
CM		 342{
343 REG_R0, REG_R1, REG_R2, REG_R3, REG_R4, REG_R5, REG_R6, REG_R7,
344 REG_P0, REG_P1, REG_P2, REG_P3, REG_P4, REG_P5, REG_SP, REG_FP,
345};
346
b7d48530 347#define dpregs(x) REGNAME (decode_dpregs[(x) & 15])
4b7f6baa
CM		 348
349/* [dregs pregs]. */
69b8ea4a 350static const enum machine_registers decode_gregs[] =
4b7f6baa
CM		 351{
352 REG_R0, REG_R1, REG_R2, REG_R3, REG_R4, REG_R5, REG_R6, REG_R7,
353 REG_P0, REG_P1, REG_P2, REG_P3, REG_P4, REG_P5, REG_SP, REG_FP,
354};
355
08c7881b 356#define gregs(x, i) REGNAME (decode_gregs[(((i) << 3) | (x)) & 15])
4b7f6baa
CM		 357
358/* [dregs pregs (iregs mregs) (bregs lregs)]. */
69b8ea4a 359static const enum machine_registers decode_regs[] =
4b7f6baa
CM		 360{
361 REG_R0, REG_R1, REG_R2, REG_R3, REG_R4, REG_R5, REG_R6, REG_R7,
362 REG_P0, REG_P1, REG_P2, REG_P3, REG_P4, REG_P5, REG_SP, REG_FP,
363 REG_I0, REG_I1, REG_I2, REG_I3, REG_M0, REG_M1, REG_M2, REG_M3,
364 REG_B0, REG_B1, REG_B2, REG_B3, REG_L0, REG_L1, REG_L2, REG_L3,
365};
366
08c7881b 367#define regs(x, i) REGNAME (decode_regs[(((i) << 3) | (x)) & 31])
4b7f6baa
CM		 368
369/* [dregs pregs (iregs mregs) (bregs lregs) Low Half]. */
69b8ea4a 370static const enum machine_registers decode_regs_lo[] =
4b7f6baa
CM		 371{
372 REG_RL0, REG_RL1, REG_RL2, REG_RL3, REG_RL4, REG_RL5, REG_RL6, REG_RL7,
373 REG_PL0, REG_PL1, REG_PL2, REG_PL3, REG_PL4, REG_PL5, REG_SLP, REG_FLP,
374 REG_IL0, REG_IL1, REG_IL2, REG_IL3, REG_ML0, REG_ML1, REG_ML2, REG_ML3,
375 REG_BL0, REG_BL1, REG_BL2, REG_BL3, REG_LL0, REG_LL1, REG_LL2, REG_LL3,
376};
377
08c7881b 378#define regs_lo(x, i) REGNAME (decode_regs_lo[(((i) << 3) | (x)) & 31])
602427c4 379
4b7f6baa 380/* [dregs pregs (iregs mregs) (bregs lregs) High Half]. */
69b8ea4a 381static const enum machine_registers decode_regs_hi[] =
4b7f6baa
CM		 382{
383 REG_RH0, REG_RH1, REG_RH2, REG_RH3, REG_RH4, REG_RH5, REG_RH6, REG_RH7,
384 REG_PH0, REG_PH1, REG_PH2, REG_PH3, REG_PH4, REG_PH5, REG_SHP, REG_FHP,
1985c81c 385 REG_IH0, REG_IH1, REG_IH2, REG_IH3, REG_MH0, REG_MH1, REG_MH2, REG_MH3,
4b7f6baa
CM		 386 REG_BH0, REG_BH1, REG_BH2, REG_BH3, REG_LH0, REG_LH1, REG_LH2, REG_LH3,
387};
388
08c7881b 389#define regs_hi(x, i) REGNAME (decode_regs_hi[(((i) << 3) | (x)) & 31])
4b7f6baa 390
69b8ea4a 391static const enum machine_registers decode_statbits[] =
4b7f6baa 392{
22215ae0
MF		 393 REG_AZ, REG_AN, REG_AC0_COPY, REG_V_COPY,
394 REG_LASTREG, REG_LASTREG, REG_AQ, REG_LASTREG,
395 REG_RND_MOD, REG_LASTREG, REG_LASTREG, REG_LASTREG,
396 REG_AC0, REG_AC1, REG_LASTREG, REG_LASTREG,
397 REG_AV0, REG_AV0S, REG_AV1, REG_AV1S,
398 REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG,
399 REG_V, REG_VS, REG_LASTREG, REG_LASTREG,
400 REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG,
4b7f6baa
CM		 401};
402
ad15c38e 403#define statbits(x) REGNAME (decode_statbits[(x) & 31])
4b7f6baa
CM		 404
405/* LC0 LC1. */
69b8ea4a 406static const enum machine_registers decode_counters[] =
4b7f6baa
CM		 407{
408 REG_LC0, REG_LC1,
409};
410
b7d48530
NC		 411#define counters(x) REGNAME (decode_counters[(x) & 1])
412#define dregs2_sysregs1(x) REGNAME (decode_dregs2_sysregs1[(x) & 7])
4b7f6baa
CM		 413
414/* [dregs pregs (iregs mregs) (bregs lregs)
415 dregs2_sysregs1 open sysregs2 sysregs3]. */
69b8ea4a 416static const enum machine_registers decode_allregs[] =
4b7f6baa
CM		 417{
418 REG_R0, REG_R1, REG_R2, REG_R3, REG_R4, REG_R5, REG_R6, REG_R7,
419 REG_P0, REG_P1, REG_P2, REG_P3, REG_P4, REG_P5, REG_SP, REG_FP,
420 REG_I0, REG_I1, REG_I2, REG_I3, REG_M0, REG_M1, REG_M2, REG_M3,
421 REG_B0, REG_B1, REG_B2, REG_B3, REG_L0, REG_L1, REG_L2, REG_L3,
43a6aa65 422 REG_A0x, REG_A0w, REG_A1x, REG_A1w, REG_LASTREG, REG_LASTREG, REG_ASTAT, REG_RETS,
4b7f6baa
CM		 423 REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG,
424 REG_LC0, REG_LT0, REG_LB0, REG_LC1, REG_LT1, REG_LB1, REG_CYCLES, REG_CYCLES2,
c958a8a8
JZ		 425 REG_USP, REG_SEQSTAT, REG_SYSCFG, REG_RETI, REG_RETX, REG_RETN, REG_RETE, REG_EMUDAT,
426 REG_LASTREG,
4b7f6baa
CM		 427};
428
50e2162a
MF		 429#define IS_DREG(g,r) ((g) == 0 && (r) < 8)
430#define IS_PREG(g,r) ((g) == 1 && (r) < 8)
c958a8a8 431#define IS_AREG(g,r) ((g) == 4 && (r) >= 0 && (r) < 4)
50e2162a
MF		 432#define IS_GENREG(g,r) ((((g) == 0 || (g) == 1) && (r) < 8) || IS_AREG (g, r))
433#define IS_DAGREG(g,r) (((g) == 2 || (g) == 3) && (r) < 8)
c958a8a8
JZ		 434#define IS_SYSREG(g,r) \
435 (((g) == 4 && ((r) == 6 || (r) == 7)) || (g) == 6 || (g) == 7)
50e2162a
MF		 436#define IS_RESERVEDREG(g,r) \
437 (((r) > 7) || ((g) == 4 && ((r) == 4 || (r) == 5)) || (g) == 5)
438
439#define allreg(r,g) (!IS_RESERVEDREG (g, r))
440#define mostreg(r,g) (!(IS_DREG (g, r) || IS_PREG (g, r) || IS_RESERVEDREG (g, r)))
c958a8a8 441
602427c4 442#define allregs(x, i) REGNAME (decode_allregs[((i) << 3) | (x)])
b7d48530 443#define uimm16s4(x) fmtconst (c_uimm16s4, x, 0, outf)
086134ec 444#define uimm16s4d(x) fmtconst (c_uimm16s4d, x, 0, outf)
b7d48530
NC		 445#define pcrel4(x) fmtconst (c_pcrel4, x, pc, outf)
446#define pcrel8(x) fmtconst (c_pcrel8, x, pc, outf)
447#define pcrel8s4(x) fmtconst (c_pcrel8s4, x, pc, outf)
448#define pcrel10(x) fmtconst (c_pcrel10, x, pc, outf)
449#define pcrel12(x) fmtconst (c_pcrel12, x, pc, outf)
450#define negimm5s4(x) fmtconst (c_negimm5s4, x, 0, outf)
451#define rimm16(x) fmtconst (c_rimm16, x, 0, outf)
452#define huimm16(x) fmtconst (c_huimm16, x, 0, outf)
453#define imm16(x) fmtconst (c_imm16, x, 0, outf)
086134ec 454#define imm16d(x) fmtconst (c_imm16d, x, 0, outf)
b7d48530
NC		 455#define uimm2(x) fmtconst (c_uimm2, x, 0, outf)
456#define uimm3(x) fmtconst (c_uimm3, x, 0, outf)
457#define luimm16(x) fmtconst (c_luimm16, x, 0, outf)
458#define uimm4(x) fmtconst (c_uimm4, x, 0, outf)
459#define uimm5(x) fmtconst (c_uimm5, x, 0, outf)
460#define imm16s2(x) fmtconst (c_imm16s2, x, 0, outf)
461#define uimm8(x) fmtconst (c_uimm8, x, 0, outf)
462#define imm16s4(x) fmtconst (c_imm16s4, x, 0, outf)
463#define uimm4s2(x) fmtconst (c_uimm4s2, x, 0, outf)
464#define uimm4s4(x) fmtconst (c_uimm4s4, x, 0, outf)
086134ec 465#define uimm4s4d(x) fmtconst (c_uimm4s4d, x, 0, outf)
b7d48530
NC		 466#define lppcrel10(x) fmtconst (c_lppcrel10, x, pc, outf)
467#define imm3(x) fmtconst (c_imm3, x, 0, outf)
468#define imm4(x) fmtconst (c_imm4, x, 0, outf)
469#define uimm8s4(x) fmtconst (c_uimm8s4, x, 0, outf)
470#define imm5(x) fmtconst (c_imm5, x, 0, outf)
086134ec 471#define imm5d(x) fmtconst (c_imm5d, x, 0, outf)
b7d48530
NC		 472#define imm6(x) fmtconst (c_imm6, x, 0, outf)
473#define imm7(x) fmtconst (c_imm7, x, 0, outf)
086134ec 474#define imm7d(x) fmtconst (c_imm7d, x, 0, outf)
b7d48530
NC		 475#define imm8(x) fmtconst (c_imm8, x, 0, outf)
476#define pcrel24(x) fmtconst (c_pcrel24, x, pc, outf)
477#define uimm16(x) fmtconst (c_uimm16, x, 0, outf)
b21c9cb4 478#define uimm32(x) fmtconst (c_uimm32, x, 0, outf)
086134ec 479#define imm32(x) fmtconst (c_imm32, x, 0, outf)
b21c9cb4 480#define huimm32(x) fmtconst (c_huimm32, x, 0, outf)
086134ec
BS		 481#define huimm32e(x) fmtconst (c_huimm32e, x, 0, outf)
482#define imm7_val(x) fmtconst_val (c_imm7, x, 0)
b21c9cb4
BS		 483#define imm16_val(x) fmtconst_val (c_uimm16, x, 0)
484#define luimm16_val(x) fmtconst_val (c_luimm16, x, 0)
4b7f6baa
CM		 485
486/* (arch.pm)arch_disassembler_functions. */
4b7f6baa 487#ifndef OUTS
500cccad 488#define OUTS(p, txt) (p)->fprintf_func ((p)->stream, "%s", txt)
4b7f6baa 489#endif
b3f3b4b0 490#define OUT(p, txt, ...) (p)->fprintf_func ((p)->stream, txt, ## __VA_ARGS__)
4b7f6baa 491
4b7f6baa
CM		 492static void
493amod0 (int s0, int x0, disassemble_info *outf)
494{
b7d48530 495 if (s0 == 1 && x0 == 0)
086134ec 496 OUTS (outf, " (S)");
4b7f6baa 497 else if (s0 == 0 && x0 == 1)
086134ec 498 OUTS (outf, " (CO)");
4b7f6baa 499 else if (s0 == 1 && x0 == 1)
086134ec 500 OUTS (outf, " (SCO)");
4b7f6baa
CM		 501}
502
503static void
504amod1 (int s0, int x0, disassemble_info *outf)
505{
506 if (s0 == 0 && x0 == 0)
086134ec 507 OUTS (outf, " (NS)");
4b7f6baa 508 else if (s0 == 1 && x0 == 0)
086134ec 509 OUTS (outf, " (S)");
4b7f6baa
CM		 510}
511
512static void
513amod0amod2 (int s0, int x0, int aop0, disassemble_info *outf)
514{
b7d48530 515 if (s0 == 1 && x0 == 0 && aop0 == 0)
086134ec 516 OUTS (outf, " (S)");
4b7f6baa 517 else if (s0 == 0 && x0 == 1 && aop0 == 0)
086134ec 518 OUTS (outf, " (CO)");
4b7f6baa 519 else if (s0 == 1 && x0 == 1 && aop0 == 0)
086134ec 520 OUTS (outf, " (SCO)");
4b7f6baa 521 else if (s0 == 0 && x0 == 0 && aop0 == 2)
086134ec 522 OUTS (outf, " (ASR)");
4b7f6baa 523 else if (s0 == 1 && x0 == 0 && aop0 == 2)
086134ec 524 OUTS (outf, " (S, ASR)");
4b7f6baa 525 else if (s0 == 0 && x0 == 1 && aop0 == 2)
086134ec 526 OUTS (outf, " (CO, ASR)");
4b7f6baa 527 else if (s0 == 1 && x0 == 1 && aop0 == 2)
086134ec 528 OUTS (outf, " (SCO, ASR)");
4b7f6baa 529 else if (s0 == 0 && x0 == 0 && aop0 == 3)
086134ec 530 OUTS (outf, " (ASL)");
4b7f6baa 531 else if (s0 == 1 && x0 == 0 && aop0 == 3)
086134ec 532 OUTS (outf, " (S, ASL)");
4b7f6baa 533 else if (s0 == 0 && x0 == 1 && aop0 == 3)
086134ec 534 OUTS (outf, " (CO, ASL)");
4b7f6baa 535 else if (s0 == 1 && x0 == 1 && aop0 == 3)
086134ec 536 OUTS (outf, " (SCO, ASL)");
4b7f6baa
CM		 537}
538
539static void
540searchmod (int r0, disassemble_info *outf)
541{
b7d48530
NC		 542 if (r0 == 0)
543 OUTS (outf, "GT");
544 else if (r0 == 1)
545 OUTS (outf, "GE");
546 else if (r0 == 2)
547 OUTS (outf, "LT");
548 else if (r0 == 3)
549 OUTS (outf, "LE");
4b7f6baa
CM		 550}
551
552static void
553aligndir (int r0, disassemble_info *outf)
554{
b7d48530 555 if (r0 == 1)
086134ec 556 OUTS (outf, " (R)");
4b7f6baa
CM		 557}
558
559static int
602427c4 560decode_multfunc (int h0, int h1, int src0, int src1, disassemble_info *outf)
4b7f6baa 561{
528c6277 562 const char *s0, *s1;
4b7f6baa
CM		 563
564 if (h0)
565 s0 = dregs_hi (src0);
566 else
567 s0 = dregs_lo (src0);
568
569 if (h1)
570 s1 = dregs_hi (src1);
571 else
572 s1 = dregs_lo (src1);
573
574 OUTS (outf, s0);
575 OUTS (outf, " * ");
576 OUTS (outf, s1);
577 return 0;
578}
579
580static int
602427c4 581decode_macfunc (int which, int op, int h0, int h1, int src0, int src1, disassemble_info *outf)
4b7f6baa 582{
528c6277
MF		 583 const char *a;
584 const char *sop = "<unknown op>";
4b7f6baa
CM		 585
586 if (which)
086134ec 587 a = "A1";
4b7f6baa 588 else
086134ec 589 a = "A0";
4b7f6baa
CM		 590
591 if (op == 3)
592 {
593 OUTS (outf, a);
594 return 0;
595 }
596
597 switch (op)
598 {
086134ec
BS		 599 case 0: sop = " = "; break;
600 case 1: sop = " += "; break;
601 case 2: sop = " -= "; break;
b7d48530 602 default: break;
4b7f6baa
CM		 603 }
604
605 OUTS (outf, a);
4b7f6baa 606 OUTS (outf, sop);
4b7f6baa
CM		 607 decode_multfunc (h0, h1, src0, src1, outf);
608
609 return 0;
610}
611
612static void
613decode_optmode (int mod, int MM, disassemble_info *outf)
614{
615 if (mod == 0 && MM == 0)
616 return;
617
618 OUTS (outf, " (");
619
620 if (MM && !mod)
621 {
622 OUTS (outf, "M)");
623 return;
624 }
625
626 if (MM)
627 OUTS (outf, "M, ");
b7d48530 628
4b7f6baa
CM		 629 if (mod == M_S2RND)
630 OUTS (outf, "S2RND");
631 else if (mod == M_T)
632 OUTS (outf, "T");
633 else if (mod == M_W32)
634 OUTS (outf, "W32");
635 else if (mod == M_FU)
636 OUTS (outf, "FU");
637 else if (mod == M_TFU)
638 OUTS (outf, "TFU");
639 else if (mod == M_IS)
640 OUTS (outf, "IS");
641 else if (mod == M_ISS2)
642 OUTS (outf, "ISS2");
643 else if (mod == M_IH)
644 OUTS (outf, "IH");
645 else if (mod == M_IU)
646 OUTS (outf, "IU");
647 else
648 abort ();
649
650 OUTS (outf, ")");
651}
b7d48530 652
e5bc4265 653static struct saved_state
b21c9cb4
BS		 654{
655 bu32 dpregs[16], iregs[4], mregs[4], bregs[4], lregs[4];
e5bc4265 656 bu32 ax[2], aw[2];
b21c9cb4 657 bu32 lt[2], lc[2], lb[2];
e5bc4265 658 bu32 rets;
602427c4 659} saved_state;
b21c9cb4
BS		 660
661#define DREG(x) (saved_state.dpregs[x])
602427c4 662#define GREG(x, i) DPREG ((x) | ((i) << 3))
b21c9cb4
BS		 663#define DPREG(x) (saved_state.dpregs[x])
664#define DREG(x) (saved_state.dpregs[x])
602427c4 665#define PREG(x) (saved_state.dpregs[(x) + 8])
b21c9cb4
BS		 666#define SPREG PREG (6)
667#define FPREG PREG (7)
668#define IREG(x) (saved_state.iregs[x])
669#define MREG(x) (saved_state.mregs[x])
670#define BREG(x) (saved_state.bregs[x])
671#define LREG(x) (saved_state.lregs[x])
e5bc4265
MF		 672#define AXREG(x) (saved_state.ax[x])
673#define AWREG(x) (saved_state.aw[x])
674#define LCREG(x) (saved_state.lc[x])
675#define LTREG(x) (saved_state.lt[x])
676#define LBREG(x) (saved_state.lb[x])
b21c9cb4 677#define RETSREG (saved_state.rets)
b21c9cb4
BS		 678
679static bu32 *
680get_allreg (int grp, int reg)
681{
682 int fullreg = (grp << 3) | reg;
683 /* REG_R0, REG_R1, REG_R2, REG_R3, REG_R4, REG_R5, REG_R6, REG_R7,
684 REG_P0, REG_P1, REG_P2, REG_P3, REG_P4, REG_P5, REG_SP, REG_FP,
685 REG_I0, REG_I1, REG_I2, REG_I3, REG_M0, REG_M1, REG_M2, REG_M3,
686 REG_B0, REG_B1, REG_B2, REG_B3, REG_L0, REG_L1, REG_L2, REG_L3,
687 REG_A0x, REG_A0w, REG_A1x, REG_A1w, , , REG_ASTAT, REG_RETS,
688 , , , , , , , ,
689 REG_LC0, REG_LT0, REG_LB0, REG_LC1, REG_LT1, REG_LB1, REG_CYCLES,
690 REG_CYCLES2,
691 REG_USP, REG_SEQSTAT, REG_SYSCFG, REG_RETI, REG_RETX, REG_RETN, REG_RETE,
692 REG_LASTREG */
693 switch (fullreg >> 2)
694 {
e5bc4265
MF		 695 case 0: case 1: return &DREG (reg);
696 case 2: case 3: return &PREG (reg);
697 case 4: return &IREG (reg & 3);
698 case 5: return &MREG (reg & 3);
699 case 6: return &BREG (reg & 3);
700 case 7: return &LREG (reg & 3);
b21c9cb4
BS		 701 default:
702 switch (fullreg)
086134ec 703 {
e5bc4265
MF		 704 case 32: return &AXREG (0);
705 case 33: return &AWREG (0);
706 case 34: return &AXREG (1);
707 case 35: return &AWREG (1);
708 case 39: return &RETSREG;
709 case 48: return &LCREG (0);
710 case 49: return &LTREG (0);
711 case 50: return &LBREG (0);
712 case 51: return &LCREG (1);
713 case 52: return &LTREG (1);
714 case 53: return &LBREG (1);
086134ec 715 }
b21c9cb4 716 }
e5bc4265 717 abort ();
b21c9cb4
BS		 718}
719
4b7f6baa
CM		 720static int
721decode_ProgCtrl_0 (TIword iw0, disassemble_info *outf)
722{
703ec4e8 723 struct private *priv = outf->private_data;
b7d48530
NC		 724 /* ProgCtrl
725 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
726 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |.prgfunc.......|.poprnd........|
727 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
4b7f6baa
CM		 728 int poprnd = ((iw0 >> ProgCtrl_poprnd_bits) & ProgCtrl_poprnd_mask);
729 int prgfunc = ((iw0 >> ProgCtrl_prgfunc_bits) & ProgCtrl_prgfunc_mask);
730
731 if (prgfunc == 0 && poprnd == 0)
b7d48530 732 OUTS (outf, "NOP");
703ec4e8 733 else if (priv->parallel)
219b747a 734 return 0;
4b7f6baa 735 else if (prgfunc == 1 && poprnd == 0)
b7d48530 736 OUTS (outf, "RTS");
4b7f6baa 737 else if (prgfunc == 1 && poprnd == 1)
b7d48530 738 OUTS (outf, "RTI");
4b7f6baa 739 else if (prgfunc == 1 && poprnd == 2)
b7d48530 740 OUTS (outf, "RTX");
4b7f6baa 741 else if (prgfunc == 1 && poprnd == 3)
b7d48530 742 OUTS (outf, "RTN");
4b7f6baa 743 else if (prgfunc == 1 && poprnd == 4)
b7d48530 744 OUTS (outf, "RTE");
4b7f6baa 745 else if (prgfunc == 2 && poprnd == 0)
b7d48530 746 OUTS (outf, "IDLE");
4b7f6baa 747 else if (prgfunc == 2 && poprnd == 3)
b7d48530 748 OUTS (outf, "CSYNC");
4b7f6baa 749 else if (prgfunc == 2 && poprnd == 4)
b7d48530 750 OUTS (outf, "SSYNC");
4b7f6baa 751 else if (prgfunc == 2 && poprnd == 5)
b7d48530 752 OUTS (outf, "EMUEXCPT");
50e2162a 753 else if (prgfunc == 3 && IS_DREG (0, poprnd))
4b7f6baa 754 {
086134ec 755 OUTS (outf, "CLI ");
4b7f6baa 756 OUTS (outf, dregs (poprnd));
4b7f6baa 757 }
50e2162a 758 else if (prgfunc == 4 && IS_DREG (0, poprnd))
4b7f6baa 759 {
086134ec 760 OUTS (outf, "STI ");
4b7f6baa 761 OUTS (outf, dregs (poprnd));
4b7f6baa 762 }
50e2162a 763 else if (prgfunc == 5 && IS_PREG (1, poprnd))
4b7f6baa 764 {
086134ec 765 OUTS (outf, "JUMP (");
4b7f6baa
CM		 766 OUTS (outf, pregs (poprnd));
767 OUTS (outf, ")");
4b7f6baa 768 }
50e2162a 769 else if (prgfunc == 6 && IS_PREG (1, poprnd))
4b7f6baa 770 {
086134ec 771 OUTS (outf, "CALL (");
4b7f6baa
CM		 772 OUTS (outf, pregs (poprnd));
773 OUTS (outf, ")");
4b7f6baa 774 }
50e2162a 775 else if (prgfunc == 7 && IS_PREG (1, poprnd))
4b7f6baa 776 {
086134ec 777 OUTS (outf, "CALL (PC + ");
4b7f6baa
CM		 778 OUTS (outf, pregs (poprnd));
779 OUTS (outf, ")");
4b7f6baa 780 }
50e2162a 781 else if (prgfunc == 8 && IS_PREG (1, poprnd))
4b7f6baa 782 {
086134ec 783 OUTS (outf, "JUMP (PC + ");
4b7f6baa
CM		 784 OUTS (outf, pregs (poprnd));
785 OUTS (outf, ")");
4b7f6baa
CM		 786 }
787 else if (prgfunc == 9)
788 {
086134ec 789 OUTS (outf, "RAISE ");
4b7f6baa 790 OUTS (outf, uimm4 (poprnd));
4b7f6baa
CM		 791 }
792 else if (prgfunc == 10)
793 {
086134ec 794 OUTS (outf, "EXCPT ");
4b7f6baa 795 OUTS (outf, uimm4 (poprnd));
4b7f6baa 796 }
219b747a 797 else if (prgfunc == 11 && IS_PREG (1, poprnd) && poprnd <= 5)
4b7f6baa 798 {
086134ec 799 OUTS (outf, "TESTSET (");
4b7f6baa
CM		 800 OUTS (outf, pregs (poprnd));
801 OUTS (outf, ")");
4b7f6baa
CM		 802 }
803 else
b7d48530
NC		 804 return 0;
805 return 2;
4b7f6baa
CM		 806}
807
808static int
809decode_CaCTRL_0 (TIword iw0, disassemble_info *outf)
810{
703ec4e8 811 struct private *priv = outf->private_data;
b7d48530
NC		 812 /* CaCTRL
813 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
814 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 |.a.|.op....|.reg.......|
815 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
4b7f6baa
CM		 816 int a = ((iw0 >> CaCTRL_a_bits) & CaCTRL_a_mask);
817 int op = ((iw0 >> CaCTRL_op_bits) & CaCTRL_op_mask);
818 int reg = ((iw0 >> CaCTRL_reg_bits) & CaCTRL_reg_mask);
819
703ec4e8 820 if (priv->parallel)
219b747a
MF		 821 return 0;
822
4b7f6baa
CM		 823 if (a == 0 && op == 0)
824 {
4b7f6baa
CM		 825 OUTS (outf, "PREFETCH[");
826 OUTS (outf, pregs (reg));
827 OUTS (outf, "]");
4b7f6baa
CM		 828 }
829 else if (a == 0 && op == 1)
830 {
4b7f6baa
CM		 831 OUTS (outf, "FLUSHINV[");
832 OUTS (outf, pregs (reg));
833 OUTS (outf, "]");
4b7f6baa
CM		 834 }
835 else if (a == 0 && op == 2)
836 {
4b7f6baa
CM		 837 OUTS (outf, "FLUSH[");
838 OUTS (outf, pregs (reg));
839 OUTS (outf, "]");
4b7f6baa
CM		 840 }
841 else if (a == 0 && op == 3)
842 {
4b7f6baa
CM		 843 OUTS (outf, "IFLUSH[");
844 OUTS (outf, pregs (reg));
845 OUTS (outf, "]");
4b7f6baa
CM		 846 }
847 else if (a == 1 && op == 0)
848 {
4b7f6baa
CM		 849 OUTS (outf, "PREFETCH[");
850 OUTS (outf, pregs (reg));
851 OUTS (outf, "++]");
4b7f6baa
CM		 852 }
853 else if (a == 1 && op == 1)
854 {
4b7f6baa
CM		 855 OUTS (outf, "FLUSHINV[");
856 OUTS (outf, pregs (reg));
857 OUTS (outf, "++]");
4b7f6baa
CM		 858 }
859 else if (a == 1 && op == 2)
860 {
4b7f6baa
CM		 861 OUTS (outf, "FLUSH[");
862 OUTS (outf, pregs (reg));
863 OUTS (outf, "++]");
4b7f6baa
CM		 864 }
865 else if (a == 1 && op == 3)
866 {
4b7f6baa
CM		 867 OUTS (outf, "IFLUSH[");
868 OUTS (outf, pregs (reg));
869 OUTS (outf, "++]");
4b7f6baa
CM		 870 }
871 else
b7d48530
NC		 872 return 0;
873 return 2;
4b7f6baa
CM		 874}
875
876static int
877decode_PushPopReg_0 (TIword iw0, disassemble_info *outf)
878{
703ec4e8 879 struct private *priv = outf->private_data;
b7d48530
NC		 880 /* PushPopReg
881 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
882 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 |.W.|.grp.......|.reg.......|
883 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
4b7f6baa
CM		 884 int W = ((iw0 >> PushPopReg_W_bits) & PushPopReg_W_mask);
885 int grp = ((iw0 >> PushPopReg_grp_bits) & PushPopReg_grp_mask);
886 int reg = ((iw0 >> PushPopReg_reg_bits) & PushPopReg_reg_mask);
887
703ec4e8 888 if (priv->parallel)
219b747a
MF		 889 return 0;
890
50e2162a 891 if (W == 0 && mostreg (reg, grp))
4b7f6baa 892 {
4b7f6baa
CM		 893 OUTS (outf, allregs (reg, grp));
894 OUTS (outf, " = [SP++]");
4b7f6baa 895 }
219b747a 896 else if (W == 1 && allreg (reg, grp) && !(grp == 1 && reg == 6))
4b7f6baa 897 {
4b7f6baa
CM		 898 OUTS (outf, "[--SP] = ");
899 OUTS (outf, allregs (reg, grp));
4b7f6baa
CM		 900 }
901 else
b7d48530
NC		 902 return 0;
903 return 2;
4b7f6baa
CM		 904}
905
906static int
907decode_PushPopMultiple_0 (TIword iw0, disassemble_info *outf)
908{
703ec4e8 909 struct private *priv = outf->private_data;
b7d48530
NC		 910 /* PushPopMultiple
911 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
912 | 0 | 0 | 0 | 0 | 0 | 1 | 0 |.d.|.p.|.W.|.dr........|.pr........|
913 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
4b7f6baa
CM		 914 int p = ((iw0 >> PushPopMultiple_p_bits) & PushPopMultiple_p_mask);
915 int d = ((iw0 >> PushPopMultiple_d_bits) & PushPopMultiple_d_mask);
916 int W = ((iw0 >> PushPopMultiple_W_bits) & PushPopMultiple_W_mask);
917 int dr = ((iw0 >> PushPopMultiple_dr_bits) & PushPopMultiple_dr_mask);
918 int pr = ((iw0 >> PushPopMultiple_pr_bits) & PushPopMultiple_pr_mask);
4b7f6baa 919
703ec4e8 920 if (priv->parallel)
219b747a
MF		 921 return 0;
922
775f1cf0
MF		 923 if (pr > 5)
924 return 0;
925
4b7f6baa
CM		 926 if (W == 1 && d == 1 && p == 1)
927 {
4b7f6baa 928 OUTS (outf, "[--SP] = (R7:");
086134ec 929 OUTS (outf, imm5d (dr));
4b7f6baa 930 OUTS (outf, ", P5:");
086134ec 931 OUTS (outf, imm5d (pr));
4b7f6baa 932 OUTS (outf, ")");
4b7f6baa 933 }
219b747a 934 else if (W == 1 && d == 1 && p == 0 && pr == 0)
4b7f6baa 935 {
4b7f6baa 936 OUTS (outf, "[--SP] = (R7:");
086134ec 937 OUTS (outf, imm5d (dr));
4b7f6baa 938 OUTS (outf, ")");
4b7f6baa 939 }
219b747a 940 else if (W == 1 && d == 0 && p == 1 && dr == 0)
4b7f6baa 941 {
4b7f6baa 942 OUTS (outf, "[--SP] = (P5:");
086134ec 943 OUTS (outf, imm5d (pr));
4b7f6baa 944 OUTS (outf, ")");
4b7f6baa
CM		 945 }
946 else if (W == 0 && d == 1 && p == 1)
947 {
4b7f6baa 948 OUTS (outf, "(R7:");
086134ec 949 OUTS (outf, imm5d (dr));
4b7f6baa 950 OUTS (outf, ", P5:");
086134ec 951 OUTS (outf, imm5d (pr));
4b7f6baa 952 OUTS (outf, ") = [SP++]");
4b7f6baa 953 }
219b747a 954 else if (W == 0 && d == 1 && p == 0 && pr == 0)
4b7f6baa 955 {
4b7f6baa 956 OUTS (outf, "(R7:");
086134ec 957 OUTS (outf, imm5d (dr));
4b7f6baa 958 OUTS (outf, ") = [SP++]");
4b7f6baa 959 }
219b747a 960 else if (W == 0 && d == 0 && p == 1 && dr == 0)
4b7f6baa 961 {
4b7f6baa 962 OUTS (outf, "(P5:");
086134ec 963 OUTS (outf, imm5d (pr));
4b7f6baa 964 OUTS (outf, ") = [SP++]");
4b7f6baa
CM		 965 }
966 else
b7d48530
NC		 967 return 0;
968 return 2;
4b7f6baa
CM		 969}
970
971static int
972decode_ccMV_0 (TIword iw0, disassemble_info *outf)
973{
703ec4e8 974 struct private *priv = outf->private_data;
b7d48530
NC		 975 /* ccMV
976 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
977 | 0 | 0 | 0 | 0 | 0 | 1 | 1 |.T.|.d.|.s.|.dst.......|.src.......|
978 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
4b7f6baa
CM		 979 int s = ((iw0 >> CCmv_s_bits) & CCmv_s_mask);
980 int d = ((iw0 >> CCmv_d_bits) & CCmv_d_mask);
981 int T = ((iw0 >> CCmv_T_bits) & CCmv_T_mask);
982 int src = ((iw0 >> CCmv_src_bits) & CCmv_src_mask);
983 int dst = ((iw0 >> CCmv_dst_bits) & CCmv_dst_mask);
984
703ec4e8 985 if (priv->parallel)
219b747a
MF		 986 return 0;
987
4b7f6baa
CM		 988 if (T == 1)
989 {
4b7f6baa
CM		 990 OUTS (outf, "IF CC ");
991 OUTS (outf, gregs (dst, d));
992 OUTS (outf, " = ");
993 OUTS (outf, gregs (src, s));
4b7f6baa
CM		 994 }
995 else if (T == 0)
996 {
086134ec 997 OUTS (outf, "IF !CC ");
4b7f6baa
CM		 998 OUTS (outf, gregs (dst, d));
999 OUTS (outf, " = ");
1000 OUTS (outf, gregs (src, s));
4b7f6baa
CM		 1001 }
1002 else
b7d48530
NC		 1003 return 0;
1004 return 2;
4b7f6baa
CM		 1005}
1006
1007static int
1008decode_CCflag_0 (TIword iw0, disassemble_info *outf)
1009{
703ec4e8 1010 struct private *priv = outf->private_data;
b7d48530
NC		 1011 /* CCflag
1012 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1013 | 0 | 0 | 0 | 0 | 1 |.I.|.opc.......|.G.|.y.........|.x.........|
1014 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
4b7f6baa
CM		 1015 int x = ((iw0 >> CCflag_x_bits) & CCflag_x_mask);
1016 int y = ((iw0 >> CCflag_y_bits) & CCflag_y_mask);
1017 int I = ((iw0 >> CCflag_I_bits) & CCflag_I_mask);
1018 int G = ((iw0 >> CCflag_G_bits) & CCflag_G_mask);
1019 int opc = ((iw0 >> CCflag_opc_bits) & CCflag_opc_mask);
1020
703ec4e8 1021 if (priv->parallel)
219b747a
MF		 1022 return 0;
1023
4b7f6baa
CM		 1024 if (opc == 0 && I == 0 && G == 0)
1025 {
086134ec 1026 OUTS (outf, "CC = ");
4b7f6baa 1027 OUTS (outf, dregs (x));
086134ec 1028 OUTS (outf, " == ");
4b7f6baa 1029 OUTS (outf, dregs (y));
4b7f6baa
CM		 1030 }
1031 else if (opc == 1 && I == 0 && G == 0)
1032 {
086134ec 1033 OUTS (outf, "CC = ");
4b7f6baa 1034 OUTS (outf, dregs (x));
086134ec 1035 OUTS (outf, " < ");
4b7f6baa 1036 OUTS (outf, dregs (y));
4b7f6baa
CM		 1037 }
1038 else if (opc == 2 && I == 0 && G == 0)
1039 {
086134ec 1040 OUTS (outf, "CC = ");
4b7f6baa 1041 OUTS (outf, dregs (x));
086134ec 1042 OUTS (outf, " <= ");
4b7f6baa 1043 OUTS (outf, dregs (y));
4b7f6baa
CM		 1044 }
1045 else if (opc == 3 && I == 0 && G == 0)
1046 {
086134ec 1047 OUTS (outf, "CC = ");
4b7f6baa 1048 OUTS (outf, dregs (x));
086134ec 1049 OUTS (outf, " < ");
4b7f6baa 1050 OUTS (outf, dregs (y));
086134ec 1051 OUTS (outf, " (IU)");
4b7f6baa
CM		 1052 }
1053 else if (opc == 4 && I == 0 && G == 0)
1054 {
086134ec 1055 OUTS (outf, "CC = ");
4b7f6baa 1056 OUTS (outf, dregs (x));
086134ec 1057 OUTS (outf, " <= ");
4b7f6baa 1058 OUTS (outf, dregs (y));
086134ec 1059 OUTS (outf, " (IU)");
4b7f6baa
CM		 1060 }
1061 else if (opc == 0 && I == 1 && G == 0)
1062 {
086134ec 1063 OUTS (outf, "CC = ");
4b7f6baa 1064 OUTS (outf, dregs (x));
086134ec 1065 OUTS (outf, " == ");
4b7f6baa 1066 OUTS (outf, imm3 (y));
4b7f6baa
CM		 1067 }
1068 else if (opc == 1 && I == 1 && G == 0)
1069 {
086134ec 1070 OUTS (outf, "CC = ");
4b7f6baa 1071 OUTS (outf, dregs (x));
086134ec 1072 OUTS (outf, " < ");
4b7f6baa 1073 OUTS (outf, imm3 (y));
4b7f6baa
CM		 1074 }
1075 else if (opc == 2 && I == 1 && G == 0)
1076 {
086134ec 1077 OUTS (outf, "CC = ");
4b7f6baa 1078 OUTS (outf, dregs (x));
086134ec 1079 OUTS (outf, " <= ");
4b7f6baa 1080 OUTS (outf, imm3 (y));
4b7f6baa
CM		 1081 }
1082 else if (opc == 3 && I == 1 && G == 0)
1083 {
086134ec 1084 OUTS (outf, "CC = ");
4b7f6baa 1085 OUTS (outf, dregs (x));
086134ec 1086 OUTS (outf, " < ");
4b7f6baa 1087 OUTS (outf, uimm3 (y));
086134ec 1088 OUTS (outf, " (IU)");
4b7f6baa
CM		 1089 }
1090 else if (opc == 4 && I == 1 && G == 0)
1091 {
086134ec 1092 OUTS (outf, "CC = ");
4b7f6baa 1093 OUTS (outf, dregs (x));
086134ec 1094 OUTS (outf, " <= ");
4b7f6baa 1095 OUTS (outf, uimm3 (y));
086134ec 1096 OUTS (outf, " (IU)");
4b7f6baa
CM		 1097 }
1098 else if (opc == 0 && I == 0 && G == 1)
1099 {
086134ec 1100 OUTS (outf, "CC = ");
4b7f6baa 1101 OUTS (outf, pregs (x));
086134ec 1102 OUTS (outf, " == ");
4b7f6baa 1103 OUTS (outf, pregs (y));
4b7f6baa
CM		 1104 }
1105 else if (opc == 1 && I == 0 && G == 1)
1106 {
086134ec 1107 OUTS (outf, "CC = ");
4b7f6baa 1108 OUTS (outf, pregs (x));
086134ec 1109 OUTS (outf, " < ");
4b7f6baa 1110 OUTS (outf, pregs (y));
4b7f6baa
CM		 1111 }
1112 else if (opc == 2 && I == 0 && G == 1)
1113 {
086134ec 1114 OUTS (outf, "CC = ");
4b7f6baa 1115 OUTS (outf, pregs (x));
086134ec 1116 OUTS (outf, " <= ");
4b7f6baa 1117 OUTS (outf, pregs (y));
4b7f6baa
CM		 1118 }
1119 else if (opc == 3 && I == 0 && G == 1)
1120 {
086134ec 1121 OUTS (outf, "CC = ");
4b7f6baa 1122 OUTS (outf, pregs (x));
086134ec 1123 OUTS (outf, " < ");
4b7f6baa 1124 OUTS (outf, pregs (y));
086134ec 1125 OUTS (outf, " (IU)");
4b7f6baa
CM		 1126 }
1127 else if (opc == 4 && I == 0 && G == 1)
1128 {
086134ec 1129 OUTS (outf, "CC = ");
4b7f6baa 1130 OUTS (outf, pregs (x));
086134ec 1131 OUTS (outf, " <= ");
4b7f6baa 1132 OUTS (outf, pregs (y));
086134ec 1133 OUTS (outf, " (IU)");
4b7f6baa
CM		 1134 }
1135 else if (opc == 0 && I == 1 && G == 1)
1136 {
086134ec 1137 OUTS (outf, "CC = ");
4b7f6baa 1138 OUTS (outf, pregs (x));
086134ec 1139 OUTS (outf, " == ");
4b7f6baa 1140 OUTS (outf, imm3 (y));
4b7f6baa
CM		 1141 }
1142 else if (opc == 1 && I == 1 && G == 1)
1143 {
086134ec 1144 OUTS (outf, "CC = ");
4b7f6baa 1145 OUTS (outf, pregs (x));
086134ec 1146 OUTS (outf, " < ");
4b7f6baa 1147 OUTS (outf, imm3 (y));
4b7f6baa
CM		 1148 }
1149 else if (opc == 2 && I == 1 && G == 1)
1150 {
086134ec 1151 OUTS (outf, "CC = ");
4b7f6baa 1152 OUTS (outf, pregs (x));
086134ec 1153 OUTS (outf, " <= ");
4b7f6baa 1154 OUTS (outf, imm3 (y));
4b7f6baa
CM		 1155 }
1156 else if (opc == 3 && I == 1 && G == 1)
1157 {
086134ec 1158 OUTS (outf, "CC = ");
4b7f6baa 1159 OUTS (outf, pregs (x));
086134ec 1160 OUTS (outf, " < ");
4b7f6baa 1161 OUTS (outf, uimm3 (y));
086134ec 1162 OUTS (outf, " (IU)");
4b7f6baa
CM		 1163 }
1164 else if (opc == 4 && I == 1 && G == 1)
1165 {
086134ec 1166 OUTS (outf, "CC = ");
4b7f6baa 1167 OUTS (outf, pregs (x));
086134ec 1168 OUTS (outf, " <= ");
4b7f6baa 1169 OUTS (outf, uimm3 (y));
086134ec 1170 OUTS (outf, " (IU)");
4b7f6baa 1171 }
219b747a 1172 else if (opc == 5 && I == 0 && G == 0 && x == 0 && y == 0)
086134ec 1173 OUTS (outf, "CC = A0 == A1");
b7d48530 1174
219b747a 1175 else if (opc == 6 && I == 0 && G == 0 && x == 0 && y == 0)
086134ec 1176 OUTS (outf, "CC = A0 < A1");
b7d48530 1177
219b747a 1178 else if (opc == 7 && I == 0 && G == 0 && x == 0 && y == 0)
086134ec 1179 OUTS (outf, "CC = A0 <= A1");
b7d48530 1180
4b7f6baa 1181 else
b7d48530
NC		 1182 return 0;
1183 return 2;
4b7f6baa
CM		 1184}
1185
1186static int
1187decode_CC2dreg_0 (TIword iw0, disassemble_info *outf)
1188{
703ec4e8 1189 struct private *priv = outf->private_data;
b7d48530
NC		 1190 /* CC2dreg
1191 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1192 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 |.op....|.reg.......|
1193 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
4b7f6baa
CM		 1194 int op = ((iw0 >> CC2dreg_op_bits) & CC2dreg_op_mask);
1195 int reg = ((iw0 >> CC2dreg_reg_bits) & CC2dreg_reg_mask);
1196
703ec4e8 1197 if (priv->parallel)
219b747a
MF		 1198 return 0;
1199
4b7f6baa
CM		 1200 if (op == 0)
1201 {
4b7f6baa 1202 OUTS (outf, dregs (reg));
086134ec 1203 OUTS (outf, " = CC");
4b7f6baa
CM		 1204 }
1205 else if (op == 1)
1206 {
086134ec 1207 OUTS (outf, "CC = ");
4b7f6baa 1208 OUTS (outf, dregs (reg));
4b7f6baa 1209 }
50e2162a 1210 else if (op == 3 && reg == 0)
086134ec 1211 OUTS (outf, "CC = !CC");
4b7f6baa 1212 else
b7d48530
NC		 1213 return 0;
1214
1215 return 2;
4b7f6baa
CM		 1216}
1217
1218static int
1219decode_CC2stat_0 (TIword iw0, disassemble_info *outf)
1220{
703ec4e8 1221 struct private *priv = outf->private_data;
b7d48530
NC		 1222 /* CC2stat
1223 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1224 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 |.D.|.op....|.cbit..............|
1225 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
4b7f6baa
CM		 1226 int D = ((iw0 >> CC2stat_D_bits) & CC2stat_D_mask);
1227 int op = ((iw0 >> CC2stat_op_bits) & CC2stat_op_mask);
1228 int cbit = ((iw0 >> CC2stat_cbit_bits) & CC2stat_cbit_mask);
1229
b2459327 1230 const char *bitname = statbits (cbit);
b3f3b4b0 1231 const char * const op_names[] = { "", "|", "&", "^" } ;
219b747a 1232
703ec4e8 1233 if (priv->parallel)
219b747a
MF		 1234 return 0;
1235
b2459327
MF		 1236 if (decode_statbits[cbit] == REG_LASTREG)
1237 {
1238 /* All ASTAT bits except CC may be operated on in hardware, but may
1239 not have a dedicated insn, so still decode "valid" insns. */
1240 static char bitnames[64];
1241 if (cbit != 5)
1242 sprintf (bitnames, "ASTAT[%i /* unused bit */]", cbit);
1243 else
219b747a
MF		 1244 return 0;
1245
b2459327
MF		 1246 bitname = bitnames;
1247 }
1248
b3f3b4b0
MF		 1249 if (D == 0)
1250 OUT (outf, "CC %s= %s", op_names[op], bitname);
4b7f6baa 1251 else
b3f3b4b0 1252 OUT (outf, "%s %s= CC", bitname, op_names[op]);
b7d48530
NC		 1253
1254 return 2;
4b7f6baa
CM		 1255}
1256
1257static int
1258decode_BRCC_0 (TIword iw0, bfd_vma pc, disassemble_info *outf)
1259{
703ec4e8 1260 struct private *priv = outf->private_data;
b7d48530
NC		 1261 /* BRCC
1262 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1263 | 0 | 0 | 0 | 1 |.T.|.B.|.offset................................|
1264 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
4b7f6baa
CM		 1265 int B = ((iw0 >> BRCC_B_bits) & BRCC_B_mask);
1266 int T = ((iw0 >> BRCC_T_bits) & BRCC_T_mask);
1267 int offset = ((iw0 >> BRCC_offset_bits) & BRCC_offset_mask);
1268
703ec4e8 1269 if (priv->parallel)
219b747a
MF		 1270 return 0;
1271
4b7f6baa
CM		 1272 if (T == 1 && B == 1)
1273 {
086134ec 1274 OUTS (outf, "IF CC JUMP 0x");
4b7f6baa 1275 OUTS (outf, pcrel10 (offset));
086134ec 1276 OUTS (outf, " (BP)");
4b7f6baa
CM		 1277 }
1278 else if (T == 0 && B == 1)
1279 {
086134ec 1280 OUTS (outf, "IF !CC JUMP 0x");
4b7f6baa 1281 OUTS (outf, pcrel10 (offset));
086134ec 1282 OUTS (outf, " (BP)");
4b7f6baa
CM		 1283 }
1284 else if (T == 1)
1285 {
086134ec 1286 OUTS (outf, "IF CC JUMP 0x");
4b7f6baa 1287 OUTS (outf, pcrel10 (offset));
4b7f6baa
CM		 1288 }
1289 else if (T == 0)
1290 {
086134ec 1291 OUTS (outf, "IF !CC JUMP 0x");
4b7f6baa 1292 OUTS (outf, pcrel10 (offset));
4b7f6baa
CM		 1293 }
1294 else
b7d48530
NC		 1295 return 0;
1296
1297 return 2;
4b7f6baa
CM		 1298}
1299
1300static int
1301decode_UJUMP_0 (TIword iw0, bfd_vma pc, disassemble_info *outf)
1302{
703ec4e8 1303 struct private *priv = outf->private_data;
b7d48530
NC		 1304 /* UJUMP
1305 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1306 | 0 | 0 | 1 | 0 |.offset........................................|
1307 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
4b7f6baa
CM		 1308 int offset = ((iw0 >> UJump_offset_bits) & UJump_offset_mask);
1309
703ec4e8 1310 if (priv->parallel)
219b747a
MF		 1311 return 0;
1312
086134ec 1313 OUTS (outf, "JUMP.S 0x");
4b7f6baa 1314 OUTS (outf, pcrel12 (offset));
b7d48530 1315 return 2;
4b7f6baa
CM		 1316}
1317
1318static int
1319decode_REGMV_0 (TIword iw0, disassemble_info *outf)
1320{
b7d48530
NC		 1321 /* REGMV
1322 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1323 | 0 | 0 | 1 | 1 |.gd........|.gs........|.dst.......|.src.......|
1324 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
4b7f6baa
CM		 1325 int gs = ((iw0 >> RegMv_gs_bits) & RegMv_gs_mask);
1326 int gd = ((iw0 >> RegMv_gd_bits) & RegMv_gd_mask);
1327 int src = ((iw0 >> RegMv_src_bits) & RegMv_src_mask);
1328 int dst = ((iw0 >> RegMv_dst_bits) & RegMv_dst_mask);
1329
602427c4 1330 /* Reserved slots cannot be a src/dst. */
35fc57f3
MF		 1331 if (IS_RESERVEDREG (gs, src) || IS_RESERVEDREG (gd, dst))
1332 goto invalid_move;
1333
1334 /* Standard register moves */
1335 if ((gs < 2) || /* Dregs/Pregs as source */
1336 (gd < 2) || /* Dregs/Pregs as dest */
1337 (gs == 4 && src < 4) || /* Accumulators as source */
1338 (gd == 4 && dst < 4 && (gs < 4)) || /* Accumulators as dest */
1339 (gs == 7 && src == 7 && !(gd == 4 && dst < 4)) || /* EMUDAT as src */
1340 (gd == 7 && dst == 7)) /* EMUDAT as dest */
1341 goto valid_move;
1342
1343 /* dareg = dareg (IMBL) */
1344 if (gs < 4 && gd < 4)
1345 goto valid_move;
1346
1347 /* USP can be src to sysregs, but not dagregs. */
1348 if ((gs == 7 && src == 0) && (gd >= 4))
1349 goto valid_move;
1350
1351 /* USP can move between genregs (only check Accumulators). */
1352 if (((gs == 7 && src == 0) && (gd == 4 && dst < 4)) ||
1353 ((gd == 7 && dst == 0) && (gs == 4 && src < 4)))
1354 goto valid_move;
1355
1356 /* Still here ? Invalid reg pair. */
1357 invalid_move:
1358 return 0;
c958a8a8 1359
35fc57f3 1360 valid_move:
4b7f6baa 1361 OUTS (outf, allregs (dst, gd));
086134ec 1362 OUTS (outf, " = ");
4b7f6baa 1363 OUTS (outf, allregs (src, gs));
b7d48530 1364 return 2;
4b7f6baa
CM		 1365}
1366
1367static int
1368decode_ALU2op_0 (TIword iw0, disassemble_info *outf)
1369{
b7d48530
NC		 1370 /* ALU2op
1371 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1372 | 0 | 1 | 0 | 0 | 0 | 0 |.opc...........|.src.......|.dst.......|
1373 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
4b7f6baa
CM		 1374 int src = ((iw0 >> ALU2op_src_bits) & ALU2op_src_mask);
1375 int opc = ((iw0 >> ALU2op_opc_bits) & ALU2op_opc_mask);
1376 int dst = ((iw0 >> ALU2op_dst_bits) & ALU2op_dst_mask);
1377
1378 if (opc == 0)
1379 {
4b7f6baa 1380 OUTS (outf, dregs (dst));
086134ec 1381 OUTS (outf, " >>>= ");
4b7f6baa 1382 OUTS (outf, dregs (src));
4b7f6baa
CM		 1383 }
1384 else if (opc == 1)
1385 {
4b7f6baa 1386 OUTS (outf, dregs (dst));
086134ec 1387 OUTS (outf, " >>= ");
4b7f6baa 1388 OUTS (outf, dregs (src));
4b7f6baa
CM		 1389 }
1390 else if (opc == 2)
1391 {
4b7f6baa 1392 OUTS (outf, dregs (dst));
086134ec 1393 OUTS (outf, " <<= ");
4b7f6baa 1394 OUTS (outf, dregs (src));
4b7f6baa
CM		 1395 }
1396 else if (opc == 3)
1397 {
4b7f6baa 1398 OUTS (outf, dregs (dst));
086134ec 1399 OUTS (outf, " *= ");
4b7f6baa 1400 OUTS (outf, dregs (src));
4b7f6baa
CM		 1401 }
1402 else if (opc == 4)
1403 {
4b7f6baa 1404 OUTS (outf, dregs (dst));
086134ec 1405 OUTS (outf, " = (");
4b7f6baa 1406 OUTS (outf, dregs (dst));
086134ec 1407 OUTS (outf, " + ");
4b7f6baa 1408 OUTS (outf, dregs (src));
086134ec 1409 OUTS (outf, ") << 0x1");
4b7f6baa
CM		 1410 }
1411 else if (opc == 5)
1412 {
4b7f6baa 1413 OUTS (outf, dregs (dst));
086134ec 1414 OUTS (outf, " = (");
4b7f6baa 1415 OUTS (outf, dregs (dst));
086134ec 1416 OUTS (outf, " + ");
4b7f6baa 1417 OUTS (outf, dregs (src));
086134ec 1418 OUTS (outf, ") << 0x2");
4b7f6baa
CM		 1419 }
1420 else if (opc == 8)
1421 {
086134ec 1422 OUTS (outf, "DIVQ (");
4b7f6baa 1423 OUTS (outf, dregs (dst));
086134ec 1424 OUTS (outf, ", ");
4b7f6baa
CM		 1425 OUTS (outf, dregs (src));
1426 OUTS (outf, ")");
4b7f6baa
CM		 1427 }
1428 else if (opc == 9)
1429 {
086134ec 1430 OUTS (outf, "DIVS (");
4b7f6baa 1431 OUTS (outf, dregs (dst));
086134ec 1432 OUTS (outf, ", ");
4b7f6baa
CM		 1433 OUTS (outf, dregs (src));
1434 OUTS (outf, ")");
4b7f6baa
CM		 1435 }
1436 else if (opc == 10)
1437 {
4b7f6baa 1438 OUTS (outf, dregs (dst));
086134ec 1439 OUTS (outf, " = ");
4b7f6baa 1440 OUTS (outf, dregs_lo (src));
086134ec 1441 OUTS (outf, " (X)");
4b7f6baa
CM		 1442 }
1443 else if (opc == 11)
1444 {
4b7f6baa 1445 OUTS (outf, dregs (dst));
086134ec 1446 OUTS (outf, " = ");
4b7f6baa 1447 OUTS (outf, dregs_lo (src));
086134ec 1448 OUTS (outf, " (Z)");
4b7f6baa
CM		 1449 }
1450 else if (opc == 12)
1451 {
4b7f6baa 1452 OUTS (outf, dregs (dst));
086134ec 1453 OUTS (outf, " = ");
4b7f6baa 1454 OUTS (outf, dregs_byte (src));
086134ec 1455 OUTS (outf, " (X)");
4b7f6baa
CM		 1456 }
1457 else if (opc == 13)
1458 {
4b7f6baa 1459 OUTS (outf, dregs (dst));
086134ec 1460 OUTS (outf, " = ");
4b7f6baa 1461 OUTS (outf, dregs_byte (src));
086134ec 1462 OUTS (outf, " (Z)");
4b7f6baa
CM		 1463 }
1464 else if (opc == 14)
1465 {
4b7f6baa 1466 OUTS (outf, dregs (dst));
086134ec 1467 OUTS (outf, " = -");
4b7f6baa 1468 OUTS (outf, dregs (src));
4b7f6baa
CM		 1469 }
1470 else if (opc == 15)
1471 {
4b7f6baa 1472 OUTS (outf, dregs (dst));
086134ec 1473 OUTS (outf, " =~ ");
4b7f6baa 1474 OUTS (outf, dregs (src));
4b7f6baa
CM		 1475 }
1476 else
b7d48530
NC		 1477 return 0;
1478
1479 return 2;
4b7f6baa
CM		 1480}
1481
1482static int
1483decode_PTR2op_0 (TIword iw0, disassemble_info *outf)
1484{
b7d48530
NC		 1485 /* PTR2op
1486 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1487 | 0 | 1 | 0 | 0 | 0 | 1 | 0 |.opc.......|.src.......|.dst.......|
1488 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
4b7f6baa
CM		 1489 int src = ((iw0 >> PTR2op_src_bits) & PTR2op_dst_mask);
1490 int opc = ((iw0 >> PTR2op_opc_bits) & PTR2op_opc_mask);
1491 int dst = ((iw0 >> PTR2op_dst_bits) & PTR2op_dst_mask);
1492
1493 if (opc == 0)
1494 {
4b7f6baa 1495 OUTS (outf, pregs (dst));
086134ec 1496 OUTS (outf, " -= ");
4b7f6baa 1497 OUTS (outf, pregs (src));
4b7f6baa
CM		 1498 }
1499 else if (opc == 1)
1500 {
4b7f6baa 1501 OUTS (outf, pregs (dst));
086134ec 1502 OUTS (outf, " = ");
4b7f6baa 1503 OUTS (outf, pregs (src));
086134ec 1504 OUTS (outf, " << 0x2");
4b7f6baa
CM		 1505 }
1506 else if (opc == 3)
1507 {
4b7f6baa 1508 OUTS (outf, pregs (dst));
086134ec 1509 OUTS (outf, " = ");
4b7f6baa 1510 OUTS (outf, pregs (src));
086134ec 1511 OUTS (outf, " >> 0x2");
4b7f6baa
CM		 1512 }
1513 else if (opc == 4)
1514 {
4b7f6baa 1515 OUTS (outf, pregs (dst));
086134ec 1516 OUTS (outf, " = ");
4b7f6baa 1517 OUTS (outf, pregs (src));
086134ec 1518 OUTS (outf, " >> 0x1");
4b7f6baa
CM		 1519 }
1520 else if (opc == 5)
1521 {
4b7f6baa 1522 OUTS (outf, pregs (dst));
086134ec 1523 OUTS (outf, " += ");
4b7f6baa 1524 OUTS (outf, pregs (src));
086134ec 1525 OUTS (outf, " (BREV)");
4b7f6baa
CM		 1526 }
1527 else if (opc == 6)
1528 {
4b7f6baa 1529 OUTS (outf, pregs (dst));
086134ec 1530 OUTS (outf, " = (");
4b7f6baa 1531 OUTS (outf, pregs (dst));
086134ec 1532 OUTS (outf, " + ");
4b7f6baa 1533 OUTS (outf, pregs (src));
086134ec 1534 OUTS (outf, ") << 0x1");
4b7f6baa
CM		 1535 }
1536 else if (opc == 7)
1537 {
4b7f6baa 1538 OUTS (outf, pregs (dst));
086134ec 1539 OUTS (outf, " = (");
4b7f6baa 1540 OUTS (outf, pregs (dst));
086134ec 1541 OUTS (outf, " + ");
4b7f6baa 1542 OUTS (outf, pregs (src));
086134ec 1543 OUTS (outf, ") << 0x2");
4b7f6baa
CM		 1544 }
1545 else
b7d48530
NC		 1546 return 0;
1547
1548 return 2;
4b7f6baa
CM		 1549}
1550
1551static int
1552decode_LOGI2op_0 (TIword iw0, disassemble_info *outf)
1553{
703ec4e8 1554 struct private *priv = outf->private_data;
b7d48530
NC		 1555 /* LOGI2op
1556 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1557 | 0 | 1 | 0 | 0 | 1 |.opc.......|.src...............|.dst.......|
1558 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
4b7f6baa
CM		 1559 int src = ((iw0 >> LOGI2op_src_bits) & LOGI2op_src_mask);
1560 int opc = ((iw0 >> LOGI2op_opc_bits) & LOGI2op_opc_mask);
1561 int dst = ((iw0 >> LOGI2op_dst_bits) & LOGI2op_dst_mask);
1562
703ec4e8 1563 if (priv->parallel)
219b747a
MF		 1564 return 0;
1565
4b7f6baa
CM		 1566 if (opc == 0)
1567 {
086134ec 1568 OUTS (outf, "CC = !BITTST (");
4b7f6baa 1569 OUTS (outf, dregs (dst));
086134ec 1570 OUTS (outf, ", ");
4b7f6baa 1571 OUTS (outf, uimm5 (src));
086134ec
BS		 1572 OUTS (outf, ");\t\t/* bit");
1573 OUTS (outf, imm7d (src));
1574 OUTS (outf, " */");
60ac5798 1575 priv->comment = TRUE;
4b7f6baa
CM		 1576 }
1577 else if (opc == 1)
1578 {
4b7f6baa
CM		 1579 OUTS (outf, "CC = BITTST (");
1580 OUTS (outf, dregs (dst));
086134ec 1581 OUTS (outf, ", ");
4b7f6baa 1582 OUTS (outf, uimm5 (src));
086134ec
BS		 1583 OUTS (outf, ");\t\t/* bit");
1584 OUTS (outf, imm7d (src));
1585 OUTS (outf, " */");
60ac5798 1586 priv->comment = TRUE;
4b7f6baa
CM		 1587 }
1588 else if (opc == 2)
1589 {
4b7f6baa
CM		 1590 OUTS (outf, "BITSET (");
1591 OUTS (outf, dregs (dst));
086134ec 1592 OUTS (outf, ", ");
4b7f6baa 1593 OUTS (outf, uimm5 (src));
086134ec
BS		 1594 OUTS (outf, ");\t\t/* bit");
1595 OUTS (outf, imm7d (src));
1596 OUTS (outf, " */");
60ac5798 1597 priv->comment = TRUE;
4b7f6baa
CM		 1598 }
1599 else if (opc == 3)
1600 {
4b7f6baa
CM		 1601 OUTS (outf, "BITTGL (");
1602 OUTS (outf, dregs (dst));
086134ec 1603 OUTS (outf, ", ");
4b7f6baa 1604 OUTS (outf, uimm5 (src));
086134ec
BS		 1605 OUTS (outf, ");\t\t/* bit");
1606 OUTS (outf, imm7d (src));
1607 OUTS (outf, " */");
60ac5798 1608 priv->comment = TRUE;
4b7f6baa
CM		 1609 }
1610 else if (opc == 4)
1611 {
4b7f6baa
CM		 1612 OUTS (outf, "BITCLR (");
1613 OUTS (outf, dregs (dst));
086134ec 1614 OUTS (outf, ", ");
4b7f6baa 1615 OUTS (outf, uimm5 (src));
086134ec
BS		 1616 OUTS (outf, ");\t\t/* bit");
1617 OUTS (outf, imm7d (src));
1618 OUTS (outf, " */");
60ac5798 1619 priv->comment = TRUE;
4b7f6baa
CM		 1620 }
1621 else if (opc == 5)
1622 {
4b7f6baa 1623 OUTS (outf, dregs (dst));
086134ec 1624 OUTS (outf, " >>>= ");
4b7f6baa 1625 OUTS (outf, uimm5 (src));
4b7f6baa
CM		 1626 }
1627 else if (opc == 6)
1628 {
4b7f6baa 1629 OUTS (outf, dregs (dst));
086134ec 1630 OUTS (outf, " >>= ");
4b7f6baa 1631 OUTS (outf, uimm5 (src));
4b7f6baa
CM		 1632 }
1633 else if (opc == 7)
1634 {
4b7f6baa 1635 OUTS (outf, dregs (dst));
086134ec 1636 OUTS (outf, " <<= ");
4b7f6baa 1637 OUTS (outf, uimm5 (src));
4b7f6baa
CM		 1638 }
1639 else
b7d48530
NC		 1640 return 0;
1641
1642 return 2;
4b7f6baa
CM		 1643}
1644
1645static int
1646decode_COMP3op_0 (TIword iw0, disassemble_info *outf)
1647{
b7d48530
NC		 1648 /* COMP3op
1649 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1650 | 0 | 1 | 0 | 1 |.opc.......|.dst.......|.src1......|.src0......|
1651 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
4b7f6baa
CM		 1652 int opc = ((iw0 >> COMP3op_opc_bits) & COMP3op_opc_mask);
1653 int dst = ((iw0 >> COMP3op_dst_bits) & COMP3op_dst_mask);
1654 int src0 = ((iw0 >> COMP3op_src0_bits) & COMP3op_src0_mask);
1655 int src1 = ((iw0 >> COMP3op_src1_bits) & COMP3op_src1_mask);
1656
1657 if (opc == 5 && src1 == src0)
1658 {
4b7f6baa 1659 OUTS (outf, pregs (dst));
086134ec 1660 OUTS (outf, " = ");
4b7f6baa 1661 OUTS (outf, pregs (src0));
086134ec 1662 OUTS (outf, " << 0x1");
4b7f6baa
CM		 1663 }
1664 else if (opc == 1)
1665 {
4b7f6baa 1666 OUTS (outf, dregs (dst));
086134ec 1667 OUTS (outf, " = ");
4b7f6baa 1668 OUTS (outf, dregs (src0));
086134ec 1669 OUTS (outf, " - ");
4b7f6baa 1670 OUTS (outf, dregs (src1));
4b7f6baa
CM		 1671 }
1672 else if (opc == 2)
1673 {
4b7f6baa 1674 OUTS (outf, dregs (dst));
086134ec 1675 OUTS (outf, " = ");
4b7f6baa 1676 OUTS (outf, dregs (src0));
086134ec 1677 OUTS (outf, " & ");
4b7f6baa 1678 OUTS (outf, dregs (src1));
4b7f6baa
CM		 1679 }
1680 else if (opc == 3)
1681 {
4b7f6baa 1682 OUTS (outf, dregs (dst));
086134ec 1683 OUTS (outf, " = ");
4b7f6baa 1684 OUTS (outf, dregs (src0));
086134ec 1685 OUTS (outf, " | ");
4b7f6baa 1686 OUTS (outf, dregs (src1));
4b7f6baa
CM		 1687 }
1688 else if (opc == 4)
1689 {
4b7f6baa 1690 OUTS (outf, dregs (dst));
086134ec 1691 OUTS (outf, " = ");
4b7f6baa 1692 OUTS (outf, dregs (src0));
086134ec 1693 OUTS (outf, " ^ ");
4b7f6baa 1694 OUTS (outf, dregs (src1));
4b7f6baa
CM		 1695 }
1696 else if (opc == 5)
1697 {
4b7f6baa 1698 OUTS (outf, pregs (dst));
086134ec 1699 OUTS (outf, " = ");
4b7f6baa 1700 OUTS (outf, pregs (src0));
086134ec 1701 OUTS (outf, " + ");
4b7f6baa 1702 OUTS (outf, pregs (src1));
4b7f6baa
CM		 1703 }
1704 else if (opc == 6)
1705 {
4b7f6baa 1706 OUTS (outf, pregs (dst));
086134ec 1707 OUTS (outf, " = ");
4b7f6baa 1708 OUTS (outf, pregs (src0));
086134ec 1709 OUTS (outf, " + (");
4b7f6baa 1710 OUTS (outf, pregs (src1));
086134ec 1711 OUTS (outf, " << 0x1)");
4b7f6baa
CM		 1712 }
1713 else if (opc == 7)
1714 {
4b7f6baa 1715 OUTS (outf, pregs (dst));
086134ec 1716 OUTS (outf, " = ");
4b7f6baa 1717 OUTS (outf, pregs (src0));
086134ec 1718 OUTS (outf, " + (");
4b7f6baa 1719 OUTS (outf, pregs (src1));
086134ec 1720 OUTS (outf, " << 0x2)");
4b7f6baa
CM		 1721 }
1722 else if (opc == 0)
1723 {
4b7f6baa 1724 OUTS (outf, dregs (dst));
086134ec 1725 OUTS (outf, " = ");
4b7f6baa 1726 OUTS (outf, dregs (src0));
086134ec 1727 OUTS (outf, " + ");
4b7f6baa 1728 OUTS (outf, dregs (src1));
4b7f6baa
CM		 1729 }
1730 else
b7d48530
NC		 1731 return 0;
1732
1733 return 2;
4b7f6baa
CM		 1734}
1735
1736static int
1737decode_COMPI2opD_0 (TIword iw0, disassemble_info *outf)
1738{
703ec4e8 1739 struct private *priv = outf->private_data;
b7d48530
NC		 1740 /* COMPI2opD
1741 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1742 | 0 | 1 | 1 | 0 | 0 |.op|..src......................|.dst.......|
1743 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
4b7f6baa
CM		 1744 int op = ((iw0 >> COMPI2opD_op_bits) & COMPI2opD_op_mask);
1745 int dst = ((iw0 >> COMPI2opD_dst_bits) & COMPI2opD_dst_mask);
1746 int src = ((iw0 >> COMPI2opD_src_bits) & COMPI2opD_src_mask);
1747
086134ec
BS		 1748 bu32 *pval = get_allreg (0, dst);
1749
703ec4e8 1750 if (priv->parallel)
219b747a
MF		 1751 return 0;
1752
086134ec
BS		 1753 /* Since we don't have 32-bit immediate loads, we allow the disassembler
1754 to combine them, so it prints out the right values.
1755 Here we keep track of the registers. */
1756 if (op == 0)
1757 {
1758 *pval = imm7_val (src);
1759 if (src & 0x40)
1760 *pval |= 0xFFFFFF80;
1761 else
1762 *pval &= 0x7F;
1763 }
1764
4b7f6baa
CM		 1765 if (op == 0)
1766 {
4b7f6baa 1767 OUTS (outf, dregs (dst));
086134ec 1768 OUTS (outf, " = ");
4b7f6baa 1769 OUTS (outf, imm7 (src));
086134ec
BS		 1770 OUTS (outf, " (X);\t\t/*\t\t");
1771 OUTS (outf, dregs (dst));
1772 OUTS (outf, "=");
1773 OUTS (outf, uimm32 (*pval));
1774 OUTS (outf, "(");
1775 OUTS (outf, imm32 (*pval));
1776 OUTS (outf, ") */");
60ac5798 1777 priv->comment = TRUE;
4b7f6baa
CM		 1778 }
1779 else if (op == 1)
1780 {
4b7f6baa 1781 OUTS (outf, dregs (dst));
086134ec 1782 OUTS (outf, " += ");
4b7f6baa 1783 OUTS (outf, imm7 (src));
086134ec
BS		 1784 OUTS (outf, ";\t\t/* (");
1785 OUTS (outf, imm7d (src));
1786 OUTS (outf, ") */");
60ac5798 1787 priv->comment = TRUE;
4b7f6baa
CM		 1788 }
1789 else
b7d48530
NC		 1790 return 0;
1791
1792 return 2;
4b7f6baa
CM		 1793}
1794
1795static int
1796decode_COMPI2opP_0 (TIword iw0, disassemble_info *outf)
1797{
703ec4e8 1798 struct private *priv = outf->private_data;
b7d48530
NC		 1799 /* COMPI2opP
1800 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1801 | 0 | 1 | 1 | 0 | 1 |.op|.src.......................|.dst.......|
1802 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
4b7f6baa
CM		 1803 int op = ((iw0 >> COMPI2opP_op_bits) & COMPI2opP_op_mask);
1804 int src = ((iw0 >> COMPI2opP_src_bits) & COMPI2opP_src_mask);
1805 int dst = ((iw0 >> COMPI2opP_dst_bits) & COMPI2opP_dst_mask);
1806
086134ec
BS		 1807 bu32 *pval = get_allreg (1, dst);
1808
703ec4e8 1809 if (priv->parallel)
219b747a
MF		 1810 return 0;
1811
086134ec
BS		 1812 if (op == 0)
1813 {
1814 *pval = imm7_val (src);
1815 if (src & 0x40)
1816 *pval |= 0xFFFFFF80;
1817 else
1818 *pval &= 0x7F;
1819 }
1820
4b7f6baa
CM		 1821 if (op == 0)
1822 {
4b7f6baa 1823 OUTS (outf, pregs (dst));
086134ec 1824 OUTS (outf, " = ");
4b7f6baa 1825 OUTS (outf, imm7 (src));
086134ec
BS		 1826 OUTS (outf, " (X);\t\t/*\t\t");
1827 OUTS (outf, pregs (dst));
1828 OUTS (outf, "=");
1829 OUTS (outf, uimm32 (*pval));
1830 OUTS (outf, "(");
1831 OUTS (outf, imm32 (*pval));
1832 OUTS (outf, ") */");
60ac5798 1833 priv->comment = TRUE;
4b7f6baa
CM		 1834 }
1835 else if (op == 1)
1836 {
4b7f6baa 1837 OUTS (outf, pregs (dst));
086134ec 1838 OUTS (outf, " += ");
4b7f6baa 1839 OUTS (outf, imm7 (src));
086134ec
BS		 1840 OUTS (outf, ";\t\t/* (");
1841 OUTS (outf, imm7d (src));
1842 OUTS (outf, ") */");
60ac5798 1843 priv->comment = TRUE;
4b7f6baa
CM		 1844 }
1845 else
b7d48530
NC		 1846 return 0;
1847
1848 return 2;
4b7f6baa
CM		 1849}
1850
1851static int
1852decode_LDSTpmod_0 (TIword iw0, disassemble_info *outf)
1853{
b7d48530
NC		 1854 /* LDSTpmod
1855 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1856 | 1 | 0 | 0 | 0 |.W.|.aop...|.reg.......|.idx.......|.ptr.......|
1857 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
4b7f6baa
CM		 1858 int W = ((iw0 >> LDSTpmod_W_bits) & LDSTpmod_W_mask);
1859 int aop = ((iw0 >> LDSTpmod_aop_bits) & LDSTpmod_aop_mask);
1860 int idx = ((iw0 >> LDSTpmod_idx_bits) & LDSTpmod_idx_mask);
1861 int ptr = ((iw0 >> LDSTpmod_ptr_bits) & LDSTpmod_ptr_mask);
1862 int reg = ((iw0 >> LDSTpmod_reg_bits) & LDSTpmod_reg_mask);
1863
1864 if (aop == 1 && W == 0 && idx == ptr)
1865 {
4b7f6baa 1866 OUTS (outf, dregs_lo (reg));
086134ec 1867 OUTS (outf, " = W[");
4b7f6baa
CM		 1868 OUTS (outf, pregs (ptr));
1869 OUTS (outf, "]");
4b7f6baa
CM		 1870 }
1871 else if (aop == 2 && W == 0 && idx == ptr)
1872 {
4b7f6baa 1873 OUTS (outf, dregs_hi (reg));
086134ec 1874 OUTS (outf, " = W[");
4b7f6baa
CM		 1875 OUTS (outf, pregs (ptr));
1876 OUTS (outf, "]");
4b7f6baa
CM		 1877 }
1878 else if (aop == 1 && W == 1 && idx == ptr)
1879 {
4b7f6baa
CM		 1880 OUTS (outf, "W[");
1881 OUTS (outf, pregs (ptr));
086134ec 1882 OUTS (outf, "] = ");
4b7f6baa 1883 OUTS (outf, dregs_lo (reg));
4b7f6baa
CM		 1884 }
1885 else if (aop == 2 && W == 1 && idx == ptr)
1886 {
4b7f6baa
CM		 1887 OUTS (outf, "W[");
1888 OUTS (outf, pregs (ptr));
086134ec 1889 OUTS (outf, "] = ");
4b7f6baa 1890 OUTS (outf, dregs_hi (reg));
4b7f6baa
CM		 1891 }
1892 else if (aop == 0 && W == 0)
1893 {
4b7f6baa 1894 OUTS (outf, dregs (reg));
086134ec 1895 OUTS (outf, " = [");
4b7f6baa 1896 OUTS (outf, pregs (ptr));
086134ec 1897 OUTS (outf, " ++ ");
4b7f6baa
CM		 1898 OUTS (outf, pregs (idx));
1899 OUTS (outf, "]");
4b7f6baa
CM		 1900 }
1901 else if (aop == 1 && W == 0)
1902 {
4b7f6baa 1903 OUTS (outf, dregs_lo (reg));
086134ec 1904 OUTS (outf, " = W[");
4b7f6baa 1905 OUTS (outf, pregs (ptr));
086134ec 1906 OUTS (outf, " ++ ");
4b7f6baa
CM		 1907 OUTS (outf, pregs (idx));
1908 OUTS (outf, "]");
4b7f6baa
CM		 1909 }
1910 else if (aop == 2 && W == 0)
1911 {
4b7f6baa 1912 OUTS (outf, dregs_hi (reg));
086134ec 1913 OUTS (outf, " = W[");
4b7f6baa 1914 OUTS (outf, pregs (ptr));
086134ec 1915 OUTS (outf, " ++ ");
4b7f6baa
CM		 1916 OUTS (outf, pregs (idx));
1917 OUTS (outf, "]");
4b7f6baa
CM		 1918 }
1919 else if (aop == 3 && W == 0)
1920 {
4b7f6baa 1921 OUTS (outf, dregs (reg));
086134ec 1922 OUTS (outf, " = W[");
4b7f6baa 1923 OUTS (outf, pregs (ptr));
086134ec 1924 OUTS (outf, " ++ ");
4b7f6baa
CM		 1925 OUTS (outf, pregs (idx));
1926 OUTS (outf, "] (Z)");
4b7f6baa
CM		 1927 }
1928 else if (aop == 3 && W == 1)
1929 {
4b7f6baa 1930 OUTS (outf, dregs (reg));
086134ec 1931 OUTS (outf, " = W[");
4b7f6baa 1932 OUTS (outf, pregs (ptr));
086134ec 1933 OUTS (outf, " ++ ");
4b7f6baa 1934 OUTS (outf, pregs (idx));
086134ec 1935 OUTS (outf, "] (X)");
4b7f6baa
CM		 1936 }
1937 else if (aop == 0 && W == 1)
1938 {
4b7f6baa
CM		 1939 OUTS (outf, "[");
1940 OUTS (outf, pregs (ptr));
086134ec 1941 OUTS (outf, " ++ ");
4b7f6baa 1942 OUTS (outf, pregs (idx));
086134ec 1943 OUTS (outf, "] = ");
4b7f6baa 1944 OUTS (outf, dregs (reg));
4b7f6baa
CM		 1945 }
1946 else if (aop == 1 && W == 1)
1947 {
4b7f6baa
CM		 1948 OUTS (outf, "W[");
1949 OUTS (outf, pregs (ptr));
086134ec 1950 OUTS (outf, " ++ ");
4b7f6baa 1951 OUTS (outf, pregs (idx));
086134ec 1952 OUTS (outf, "] = ");
4b7f6baa 1953 OUTS (outf, dregs_lo (reg));
4b7f6baa
CM		 1954 }
1955 else if (aop == 2 && W == 1)
1956 {
4b7f6baa
CM		 1957 OUTS (outf, "W[");
1958 OUTS (outf, pregs (ptr));
086134ec 1959 OUTS (outf, " ++ ");
4b7f6baa 1960 OUTS (outf, pregs (idx));
086134ec 1961 OUTS (outf, "] = ");
4b7f6baa 1962 OUTS (outf, dregs_hi (reg));
4b7f6baa
CM		 1963 }
1964 else
b7d48530
NC		 1965 return 0;
1966
1967 return 2;
4b7f6baa
CM		 1968}
1969
1970static int
1971decode_dagMODim_0 (TIword iw0, disassemble_info *outf)
1972{
b7d48530
NC		 1973 /* dagMODim
1974 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1975 | 1 | 0 | 0 | 1 | 1 | 1 | 1 | 0 |.br| 1 | 1 |.op|.m.....|.i.....|
1976 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
4b7f6baa
CM		 1977 int i = ((iw0 >> DagMODim_i_bits) & DagMODim_i_mask);
1978 int m = ((iw0 >> DagMODim_m_bits) & DagMODim_m_mask);
1979 int br = ((iw0 >> DagMODim_br_bits) & DagMODim_br_mask);
1980 int op = ((iw0 >> DagMODim_op_bits) & DagMODim_op_mask);
1981
1982 if (op == 0 && br == 1)
1983 {
4b7f6baa 1984 OUTS (outf, iregs (i));
086134ec 1985 OUTS (outf, " += ");
4b7f6baa 1986 OUTS (outf, mregs (m));
086134ec 1987 OUTS (outf, " (BREV)");
4b7f6baa
CM		 1988 }
1989 else if (op == 0)
1990 {
4b7f6baa 1991 OUTS (outf, iregs (i));
086134ec 1992 OUTS (outf, " += ");
4b7f6baa 1993 OUTS (outf, mregs (m));
4b7f6baa 1994 }
219b747a 1995 else if (op == 1 && br == 0)
4b7f6baa 1996 {
4b7f6baa 1997 OUTS (outf, iregs (i));
086134ec 1998 OUTS (outf, " -= ");
4b7f6baa 1999 OUTS (outf, mregs (m));
4b7f6baa
CM		 2000 }
2001 else
b7d48530
NC		 2002 return 0;
2003
2004 return 2;
4b7f6baa
CM		 2005}
2006
2007static int
2008decode_dagMODik_0 (TIword iw0, disassemble_info *outf)
2009{
703ec4e8 2010 struct private *priv = outf->private_data;
b7d48530
NC		 2011 /* dagMODik
2012 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2013 | 1 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | 1 | 0 |.op....|.i.....|
2014 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
4b7f6baa
CM		 2015 int i = ((iw0 >> DagMODik_i_bits) & DagMODik_i_mask);
2016 int op = ((iw0 >> DagMODik_op_bits) & DagMODik_op_mask);
2017
2018 if (op == 0)
2019 {
4b7f6baa 2020 OUTS (outf, iregs (i));
086134ec 2021 OUTS (outf, " += 0x2");
4b7f6baa
CM		 2022 }
2023 else if (op == 1)
2024 {
4b7f6baa 2025 OUTS (outf, iregs (i));
086134ec 2026 OUTS (outf, " -= 0x2");
4b7f6baa
CM		 2027 }
2028 else if (op == 2)
2029 {
4b7f6baa 2030 OUTS (outf, iregs (i));
086134ec 2031 OUTS (outf, " += 0x4");
4b7f6baa
CM		 2032 }
2033 else if (op == 3)
2034 {
4b7f6baa 2035 OUTS (outf, iregs (i));
086134ec 2036 OUTS (outf, " -= 0x4");
4b7f6baa
CM		 2037 }
2038 else
b7d48530
NC		 2039 return 0;
2040
703ec4e8 2041 if (!priv->parallel)
602427c4
MF		 2042 {
2043 OUTS (outf, ";\t\t/* ( ");
2044 if (op == 0 || op == 1)
2045 OUTS (outf, "2");
2046 else if (op == 2 || op == 3)
086134ec 2047 OUTS (outf, "4");
602427c4 2048 OUTS (outf, ") */");
60ac5798 2049 priv->comment = TRUE;
602427c4 2050 }
086134ec 2051
b7d48530 2052 return 2;
4b7f6baa
CM		 2053}
2054
2055static int
2056decode_dspLDST_0 (TIword iw0, disassemble_info *outf)
2057{
b7d48530
NC		 2058 /* dspLDST
2059 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2060 | 1 | 0 | 0 | 1 | 1 | 1 |.W.|.aop...|.m.....|.i.....|.reg.......|
2061 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
4b7f6baa
CM		 2062 int i = ((iw0 >> DspLDST_i_bits) & DspLDST_i_mask);
2063 int m = ((iw0 >> DspLDST_m_bits) & DspLDST_m_mask);
2064 int W = ((iw0 >> DspLDST_W_bits) & DspLDST_W_mask);
2065 int aop = ((iw0 >> DspLDST_aop_bits) & DspLDST_aop_mask);
2066 int reg = ((iw0 >> DspLDST_reg_bits) & DspLDST_reg_mask);
2067
2068 if (aop == 0 && W == 0 && m == 0)
2069 {
4b7f6baa 2070 OUTS (outf, dregs (reg));
086134ec 2071 OUTS (outf, " = [");
4b7f6baa
CM		 2072 OUTS (outf, iregs (i));
2073 OUTS (outf, "++]");
4b7f6baa
CM		 2074 }
2075 else if (aop == 0 && W == 0 && m == 1)
2076 {
4b7f6baa 2077 OUTS (outf, dregs_lo (reg));
086134ec 2078 OUTS (outf, " = W[");
4b7f6baa
CM		 2079 OUTS (outf, iregs (i));
2080 OUTS (outf, "++]");
4b7f6baa
CM		 2081 }
2082 else if (aop == 0 && W == 0 && m == 2)
2083 {
4b7f6baa 2084 OUTS (outf, dregs_hi (reg));
086134ec 2085 OUTS (outf, " = W[");
4b7f6baa
CM		 2086 OUTS (outf, iregs (i));
2087 OUTS (outf, "++]");
4b7f6baa
CM		 2088 }
2089 else if (aop == 1 && W == 0 && m == 0)
2090 {
4b7f6baa 2091 OUTS (outf, dregs (reg));
086134ec 2092 OUTS (outf, " = [");
4b7f6baa
CM		 2093 OUTS (outf, iregs (i));
2094 OUTS (outf, "--]");
4b7f6baa
CM		 2095 }
2096 else if (aop == 1 && W == 0 && m == 1)
2097 {
4b7f6baa 2098 OUTS (outf, dregs_lo (reg));
086134ec 2099 OUTS (outf, " = W[");
4b7f6baa
CM		 2100 OUTS (outf, iregs (i));
2101 OUTS (outf, "--]");
4b7f6baa
CM		 2102 }
2103 else if (aop == 1 && W == 0 && m == 2)
2104 {
4b7f6baa 2105 OUTS (outf, dregs_hi (reg));
086134ec 2106 OUTS (outf, " = W[");
4b7f6baa
CM		 2107 OUTS (outf, iregs (i));
2108 OUTS (outf, "--]");
4b7f6baa
CM		 2109 }
2110 else if (aop == 2 && W == 0 && m == 0)
2111 {
4b7f6baa 2112 OUTS (outf, dregs (reg));
086134ec 2113 OUTS (outf, " = [");
4b7f6baa
CM		 2114 OUTS (outf, iregs (i));
2115 OUTS (outf, "]");
4b7f6baa
CM		 2116 }
2117 else if (aop == 2 && W == 0 && m == 1)
2118 {
4b7f6baa 2119 OUTS (outf, dregs_lo (reg));
086134ec 2120 OUTS (outf, " = W[");
4b7f6baa
CM		 2121 OUTS (outf, iregs (i));
2122 OUTS (outf, "]");
4b7f6baa
CM		 2123 }
2124 else if (aop == 2 && W == 0 && m == 2)
2125 {
4b7f6baa 2126 OUTS (outf, dregs_hi (reg));
086134ec 2127 OUTS (outf, " = W[");
4b7f6baa
CM		 2128 OUTS (outf, iregs (i));
2129 OUTS (outf, "]");
4b7f6baa
CM		 2130 }
2131 else if (aop == 0 && W == 1 && m == 0)
2132 {
4b7f6baa
CM		 2133 OUTS (outf, "[");
2134 OUTS (outf, iregs (i));
086134ec 2135 OUTS (outf, "++] = ");
4b7f6baa 2136 OUTS (outf, dregs (reg));
4b7f6baa
CM		 2137 }
2138 else if (aop == 0 && W == 1 && m == 1)
2139 {
4b7f6baa
CM		 2140 OUTS (outf, "W[");
2141 OUTS (outf, iregs (i));
086134ec 2142 OUTS (outf, "++] = ");
4b7f6baa 2143 OUTS (outf, dregs_lo (reg));
4b7f6baa
CM		 2144 }
2145 else if (aop == 0 && W == 1 && m == 2)
2146 {
4b7f6baa
CM		 2147 OUTS (outf, "W[");
2148 OUTS (outf, iregs (i));
086134ec 2149 OUTS (outf, "++] = ");
4b7f6baa 2150 OUTS (outf, dregs_hi (reg));
4b7f6baa
CM		 2151 }
2152 else if (aop == 1 && W == 1 && m == 0)
2153 {
4b7f6baa
CM		 2154 OUTS (outf, "[");
2155 OUTS (outf, iregs (i));
086134ec 2156 OUTS (outf, "--] = ");
4b7f6baa 2157 OUTS (outf, dregs (reg));
4b7f6baa
CM		 2158 }
2159 else if (aop == 1 && W == 1 && m == 1)
2160 {
4b7f6baa
CM		 2161 OUTS (outf, "W[");
2162 OUTS (outf, iregs (i));
086134ec 2163 OUTS (outf, "--] = ");
4b7f6baa 2164 OUTS (outf, dregs_lo (reg));
4b7f6baa
CM		 2165 }
2166 else if (aop == 1 && W == 1 && m == 2)
2167 {
4b7f6baa
CM		 2168 OUTS (outf, "W[");
2169 OUTS (outf, iregs (i));
086134ec 2170 OUTS (outf, "--] = ");
4b7f6baa 2171 OUTS (outf, dregs_hi (reg));
4b7f6baa
CM		 2172 }
2173 else if (aop == 2 && W == 1 && m == 0)
2174 {
4b7f6baa
CM		 2175 OUTS (outf, "[");
2176 OUTS (outf, iregs (i));
086134ec 2177 OUTS (outf, "] = ");
4b7f6baa 2178 OUTS (outf, dregs (reg));
4b7f6baa
CM		 2179 }
2180 else if (aop == 2 && W == 1 && m == 1)
2181 {
4b7f6baa
CM		 2182 OUTS (outf, "W[");
2183 OUTS (outf, iregs (i));
086134ec 2184 OUTS (outf, "] = ");
4b7f6baa 2185 OUTS (outf, dregs_lo (reg));
4b7f6baa
CM		 2186 }
2187 else if (aop == 2 && W == 1 && m == 2)
2188 {
4b7f6baa
CM		 2189 OUTS (outf, "W[");
2190 OUTS (outf, iregs (i));
086134ec 2191 OUTS (outf, "] = ");
4b7f6baa 2192 OUTS (outf, dregs_hi (reg));
4b7f6baa
CM		 2193 }
2194 else if (aop == 3 && W == 0)
2195 {
4b7f6baa 2196 OUTS (outf, dregs (reg));
086134ec 2197 OUTS (outf, " = [");
4b7f6baa 2198 OUTS (outf, iregs (i));
086134ec 2199 OUTS (outf, " ++ ");
4b7f6baa
CM		 2200 OUTS (outf, mregs (m));
2201 OUTS (outf, "]");
4b7f6baa
CM		 2202 }
2203 else if (aop == 3 && W == 1)
2204 {
4b7f6baa
CM		 2205 OUTS (outf, "[");
2206 OUTS (outf, iregs (i));
086134ec 2207 OUTS (outf, " ++ ");
4b7f6baa 2208 OUTS (outf, mregs (m));
086134ec 2209 OUTS (outf, "] = ");
4b7f6baa 2210 OUTS (outf, dregs (reg));
4b7f6baa
CM		 2211 }
2212 else
b7d48530
NC		 2213 return 0;
2214
2215 return 2;
4b7f6baa
CM		 2216}
2217
2218static int
2219decode_LDST_0 (TIword iw0, disassemble_info *outf)
2220{
b7d48530
NC		 2221 /* LDST
2222 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2223 | 1 | 0 | 0 | 1 |.sz....|.W.|.aop...|.Z.|.ptr.......|.reg.......|
2224 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
4b7f6baa
CM		 2225 int Z = ((iw0 >> LDST_Z_bits) & LDST_Z_mask);
2226 int W = ((iw0 >> LDST_W_bits) & LDST_W_mask);
2227 int sz = ((iw0 >> LDST_sz_bits) & LDST_sz_mask);
2228 int aop = ((iw0 >> LDST_aop_bits) & LDST_aop_mask);
2229 int reg = ((iw0 >> LDST_reg_bits) & LDST_reg_mask);
2230 int ptr = ((iw0 >> LDST_ptr_bits) & LDST_ptr_mask);
2231
2232 if (aop == 0 && sz == 0 && Z == 0 && W == 0)
2233 {
4b7f6baa 2234 OUTS (outf, dregs (reg));
086134ec 2235 OUTS (outf, " = [");
4b7f6baa
CM		 2236 OUTS (outf, pregs (ptr));
2237 OUTS (outf, "++]");
4b7f6baa 2238 }
219b747a 2239 else if (aop == 0 && sz == 0 && Z == 1 && W == 0 && reg != ptr)
4b7f6baa 2240 {
4b7f6baa 2241 OUTS (outf, pregs (reg));
086134ec 2242 OUTS (outf, " = [");
4b7f6baa
CM		 2243 OUTS (outf, pregs (ptr));
2244 OUTS (outf, "++]");
4b7f6baa
CM		 2245 }
2246 else if (aop == 0 && sz == 1 && Z == 0 && W == 0)
2247 {
4b7f6baa 2248 OUTS (outf, dregs (reg));
086134ec 2249 OUTS (outf, " = W[");
4b7f6baa
CM		 2250 OUTS (outf, pregs (ptr));
2251 OUTS (outf, "++] (Z)");
4b7f6baa
CM		 2252 }
2253 else if (aop == 0 && sz == 1 && Z == 1 && W == 0)
2254 {
4b7f6baa 2255 OUTS (outf, dregs (reg));
086134ec 2256 OUTS (outf, " = W[");
4b7f6baa 2257 OUTS (outf, pregs (ptr));
086134ec 2258 OUTS (outf, "++] (X)");
4b7f6baa
CM		 2259 }
2260 else if (aop == 0 && sz == 2 && Z == 0 && W == 0)
2261 {
4b7f6baa 2262 OUTS (outf, dregs (reg));
086134ec 2263 OUTS (outf, " = B[");
4b7f6baa
CM		 2264 OUTS (outf, pregs (ptr));
2265 OUTS (outf, "++] (Z)");
4b7f6baa
CM		 2266 }
2267 else if (aop == 0 && sz == 2 && Z == 1 && W == 0)
2268 {
4b7f6baa 2269 OUTS (outf, dregs (reg));
086134ec 2270 OUTS (outf, " = B[");
4b7f6baa 2271 OUTS (outf, pregs (ptr));
086134ec 2272 OUTS (outf, "++] (X)");
4b7f6baa
CM		 2273 }
2274 else if (aop == 1 && sz == 0 && Z == 0 && W == 0)
2275 {
4b7f6baa 2276 OUTS (outf, dregs (reg));
086134ec 2277 OUTS (outf, " = [");
4b7f6baa
CM		 2278 OUTS (outf, pregs (ptr));
2279 OUTS (outf, "--]");
4b7f6baa 2280 }
219b747a 2281 else if (aop == 1 && sz == 0 && Z == 1 && W == 0 && reg != ptr)
4b7f6baa 2282 {
4b7f6baa 2283 OUTS (outf, pregs (reg));
086134ec 2284 OUTS (outf, " = [");
4b7f6baa
CM		 2285 OUTS (outf, pregs (ptr));
2286 OUTS (outf, "--]");
4b7f6baa
CM		 2287 }
2288 else if (aop == 1 && sz == 1 && Z == 0 && W == 0)
2289 {
4b7f6baa 2290 OUTS (outf, dregs (reg));
086134ec 2291 OUTS (outf, " = W[");
4b7f6baa
CM		 2292 OUTS (outf, pregs (ptr));
2293 OUTS (outf, "--] (Z)");
4b7f6baa
CM		 2294 }
2295 else if (aop == 1 && sz == 1 && Z == 1 && W == 0)
2296 {
4b7f6baa 2297 OUTS (outf, dregs (reg));
086134ec 2298 OUTS (outf, " = W[");
4b7f6baa 2299 OUTS (outf, pregs (ptr));
086134ec 2300 OUTS (outf, "--] (X)");
4b7f6baa
CM		 2301 }
2302 else if (aop == 1 && sz == 2 && Z == 0 && W == 0)
2303 {
4b7f6baa 2304 OUTS (outf, dregs (reg));
086134ec 2305 OUTS (outf, " = B[");
4b7f6baa
CM		 2306 OUTS (outf, pregs (ptr));
2307 OUTS (outf, "--] (Z)");
4b7f6baa
CM		 2308 }
2309 else if (aop == 1 && sz == 2 && Z == 1 && W == 0)
2310 {
4b7f6baa 2311 OUTS (outf, dregs (reg));
086134ec 2312 OUTS (outf, " = B[");
4b7f6baa 2313 OUTS (outf, pregs (ptr));
086134ec 2314 OUTS (outf, "--] (X)");
4b7f6baa
CM		 2315 }
2316 else if (aop == 2 && sz == 0 && Z == 0 && W == 0)
2317 {
4b7f6baa 2318 OUTS (outf, dregs (reg));
086134ec 2319 OUTS (outf, " = [");
4b7f6baa
CM		 2320 OUTS (outf, pregs (ptr));
2321 OUTS (outf, "]");
4b7f6baa
CM		 2322 }
2323 else if (aop == 2 && sz == 0 && Z == 1 && W == 0)
2324 {
4b7f6baa 2325 OUTS (outf, pregs (reg));
086134ec 2326 OUTS (outf, " = [");
4b7f6baa
CM		 2327 OUTS (outf, pregs (ptr));
2328 OUTS (outf, "]");
4b7f6baa
CM		 2329 }
2330 else if (aop == 2 && sz == 1 && Z == 0 && W == 0)
2331 {
4b7f6baa 2332 OUTS (outf, dregs (reg));
086134ec 2333 OUTS (outf, " = W[");
4b7f6baa
CM		 2334 OUTS (outf, pregs (ptr));
2335 OUTS (outf, "] (Z)");
4b7f6baa
CM		 2336 }
2337 else if (aop == 2 && sz == 1 && Z == 1 && W == 0)
2338 {
4b7f6baa 2339 OUTS (outf, dregs (reg));
086134ec 2340 OUTS (outf, " = W[");
4b7f6baa 2341 OUTS (outf, pregs (ptr));
086134ec 2342 OUTS (outf, "] (X)");
4b7f6baa
CM		 2343 }
2344 else if (aop == 2 && sz == 2 && Z == 0 && W == 0)
2345 {
4b7f6baa 2346 OUTS (outf, dregs (reg));
086134ec 2347 OUTS (outf, " = B[");
4b7f6baa
CM		 2348 OUTS (outf, pregs (ptr));
2349 OUTS (outf, "] (Z)");
4b7f6baa
CM		 2350 }
2351 else if (aop == 2 && sz == 2 && Z == 1 && W == 0)
2352 {
4b7f6baa 2353 OUTS (outf, dregs (reg));
086134ec 2354 OUTS (outf, " = B[");
4b7f6baa 2355 OUTS (outf, pregs (ptr));
086134ec 2356 OUTS (outf, "] (X)");
4b7f6baa
CM		 2357 }
2358 else if (aop == 0 && sz == 0 && Z == 0 && W == 1)
2359 {
4b7f6baa
CM		 2360 OUTS (outf, "[");
2361 OUTS (outf, pregs (ptr));
086134ec 2362 OUTS (outf, "++] = ");
4b7f6baa 2363 OUTS (outf, dregs (reg));
4b7f6baa
CM		 2364 }
2365 else if (aop == 0 && sz == 0 && Z == 1 && W == 1)
2366 {
4b7f6baa
CM		 2367 OUTS (outf, "[");
2368 OUTS (outf, pregs (ptr));
086134ec 2369 OUTS (outf, "++] = ");
4b7f6baa 2370 OUTS (outf, pregs (reg));
4b7f6baa
CM		 2371 }
2372 else if (aop == 0 && sz == 1 && Z == 0 && W == 1)
2373 {
4b7f6baa
CM		 2374 OUTS (outf, "W[");
2375 OUTS (outf, pregs (ptr));
086134ec 2376 OUTS (outf, "++] = ");
4b7f6baa 2377 OUTS (outf, dregs (reg));
4b7f6baa
CM		 2378 }
2379 else if (aop == 0 && sz == 2 && Z == 0 && W == 1)
2380 {
4b7f6baa
CM		 2381 OUTS (outf, "B[");
2382 OUTS (outf, pregs (ptr));
086134ec 2383 OUTS (outf, "++] = ");
4b7f6baa 2384 OUTS (outf, dregs (reg));
4b7f6baa
CM		 2385 }
2386 else if (aop == 1 && sz == 0 && Z == 0 && W == 1)
2387 {
4b7f6baa
CM		 2388 OUTS (outf, "[");
2389 OUTS (outf, pregs (ptr));
086134ec 2390 OUTS (outf, "--] = ");
4b7f6baa 2391 OUTS (outf, dregs (reg));
4b7f6baa
CM		 2392 }
2393 else if (aop == 1 && sz == 0 && Z == 1 && W == 1)
2394 {
4b7f6baa
CM		 2395 OUTS (outf, "[");
2396 OUTS (outf, pregs (ptr));
086134ec 2397 OUTS (outf, "--] = ");
4b7f6baa 2398 OUTS (outf, pregs (reg));
4b7f6baa
CM		 2399 }
2400 else if (aop == 1 && sz == 1 && Z == 0 && W == 1)
2401 {
4b7f6baa
CM		 2402 OUTS (outf, "W[");
2403 OUTS (outf, pregs (ptr));
086134ec 2404 OUTS (outf, "--] = ");
4b7f6baa 2405 OUTS (outf, dregs (reg));
4b7f6baa
CM		 2406 }
2407 else if (aop == 1 && sz == 2 && Z == 0 && W == 1)
2408 {
4b7f6baa
CM		 2409 OUTS (outf, "B[");
2410 OUTS (outf, pregs (ptr));
086134ec 2411 OUTS (outf, "--] = ");
4b7f6baa 2412 OUTS (outf, dregs (reg));
4b7f6baa
CM		 2413 }
2414 else if (aop == 2 && sz == 0 && Z == 0 && W == 1)
2415 {
4b7f6baa
CM		 2416 OUTS (outf, "[");
2417 OUTS (outf, pregs (ptr));
086134ec 2418 OUTS (outf, "] = ");
4b7f6baa 2419 OUTS (outf, dregs (reg));
4b7f6baa
CM		 2420 }
2421 else if (aop == 2 && sz == 0 && Z == 1 && W == 1)
2422 {
4b7f6baa
CM		 2423 OUTS (outf, "[");
2424 OUTS (outf, pregs (ptr));
086134ec 2425 OUTS (outf, "] = ");
4b7f6baa 2426 OUTS (outf, pregs (reg));
4b7f6baa
CM		 2427 }
2428 else if (aop == 2 && sz == 1 && Z == 0 && W == 1)
2429 {
4b7f6baa
CM		 2430 OUTS (outf, "W[");
2431 OUTS (outf, pregs (ptr));
086134ec 2432 OUTS (outf, "] = ");
4b7f6baa 2433 OUTS (outf, dregs (reg));
4b7f6baa
CM		 2434 }
2435 else if (aop == 2 && sz == 2 && Z == 0 && W == 1)
2436 {
4b7f6baa
CM		 2437 OUTS (outf, "B[");
2438 OUTS (outf, pregs (ptr));
086134ec 2439 OUTS (outf, "] = ");
4b7f6baa 2440 OUTS (outf, dregs (reg));
4b7f6baa
CM		 2441 }
2442 else
b7d48530
NC		 2443 return 0;
2444
2445 return 2;
4b7f6baa
CM		 2446}
2447
2448static int
2449decode_LDSTiiFP_0 (TIword iw0, disassemble_info *outf)
2450{
b7d48530
NC		 2451 /* LDSTiiFP
2452 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2453 | 1 | 0 | 1 | 1 | 1 | 0 |.W.|.offset............|.reg...........|
2454 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
4b7f6baa
CM		 2455 int reg = ((iw0 >> LDSTiiFP_reg_bits) & LDSTiiFP_reg_mask);
2456 int offset = ((iw0 >> LDSTiiFP_offset_bits) & LDSTiiFP_offset_mask);
2457 int W = ((iw0 >> LDSTiiFP_W_bits) & LDSTiiFP_W_mask);
2458
2459 if (W == 0)
2460 {
4b7f6baa 2461 OUTS (outf, dpregs (reg));
086134ec 2462 OUTS (outf, " = [FP ");
4b7f6baa
CM		 2463 OUTS (outf, negimm5s4 (offset));
2464 OUTS (outf, "]");
4b7f6baa
CM		 2465 }
2466 else if (W == 1)
2467 {
086134ec 2468 OUTS (outf, "[FP ");
4b7f6baa 2469 OUTS (outf, negimm5s4 (offset));
086134ec 2470 OUTS (outf, "] = ");
4b7f6baa 2471 OUTS (outf, dpregs (reg));
4b7f6baa
CM		 2472 }
2473 else
b7d48530
NC		 2474 return 0;
2475
2476 return 2;
4b7f6baa
CM		 2477}
2478
2479static int
2480decode_LDSTii_0 (TIword iw0, disassemble_info *outf)
2481{
b7d48530
NC		 2482 /* LDSTii
2483 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2484 | 1 | 0 | 1 |.W.|.op....|.offset........|.ptr.......|.reg.......|
2485 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
4b7f6baa
CM		 2486 int reg = ((iw0 >> LDSTii_reg_bit) & LDSTii_reg_mask);
2487 int ptr = ((iw0 >> LDSTii_ptr_bit) & LDSTii_ptr_mask);
2488 int offset = ((iw0 >> LDSTii_offset_bit) & LDSTii_offset_mask);
2489 int op = ((iw0 >> LDSTii_op_bit) & LDSTii_op_mask);
2490 int W = ((iw0 >> LDSTii_W_bit) & LDSTii_W_mask);
2491
2492 if (W == 0 && op == 0)
2493 {
4b7f6baa 2494 OUTS (outf, dregs (reg));
086134ec 2495 OUTS (outf, " = [");
4b7f6baa 2496 OUTS (outf, pregs (ptr));
086134ec 2497 OUTS (outf, " + ");
4b7f6baa
CM		 2498 OUTS (outf, uimm4s4 (offset));
2499 OUTS (outf, "]");
4b7f6baa
CM		 2500 }
2501 else if (W == 0 && op == 1)
2502 {
4b7f6baa 2503 OUTS (outf, dregs (reg));
086134ec 2504 OUTS (outf, " = W[");
4b7f6baa 2505 OUTS (outf, pregs (ptr));
086134ec 2506 OUTS (outf, " + ");
4b7f6baa
CM		 2507 OUTS (outf, uimm4s2 (offset));
2508 OUTS (outf, "] (Z)");
4b7f6baa
CM		 2509 }
2510 else if (W == 0 && op == 2)
2511 {
4b7f6baa 2512 OUTS (outf, dregs (reg));
086134ec 2513 OUTS (outf, " = W[");
4b7f6baa 2514 OUTS (outf, pregs (ptr));
086134ec 2515 OUTS (outf, " + ");
4b7f6baa 2516 OUTS (outf, uimm4s2 (offset));
086134ec 2517 OUTS (outf, "] (X)");
4b7f6baa
CM		 2518 }
2519 else if (W == 0 && op == 3)
2520 {
4b7f6baa 2521 OUTS (outf, pregs (reg));
086134ec 2522 OUTS (outf, " = [");
4b7f6baa 2523 OUTS (outf, pregs (ptr));
086134ec 2524 OUTS (outf, " + ");
4b7f6baa
CM		 2525 OUTS (outf, uimm4s4 (offset));
2526 OUTS (outf, "]");
4b7f6baa
CM		 2527 }
2528 else if (W == 1 && op == 0)
2529 {
4b7f6baa
CM		 2530 OUTS (outf, "[");
2531 OUTS (outf, pregs (ptr));
086134ec 2532 OUTS (outf, " + ");
4b7f6baa 2533 OUTS (outf, uimm4s4 (offset));
086134ec 2534 OUTS (outf, "] = ");
4b7f6baa 2535 OUTS (outf, dregs (reg));
4b7f6baa
CM		 2536 }
2537 else if (W == 1 && op == 1)
2538 {
086134ec 2539 OUTS (outf, "W[");
4b7f6baa 2540 OUTS (outf, pregs (ptr));
086134ec 2541 OUTS (outf, " + ");
4b7f6baa 2542 OUTS (outf, uimm4s2 (offset));
086134ec 2543 OUTS (outf, "] = ");
4b7f6baa 2544 OUTS (outf, dregs (reg));
4b7f6baa
CM		 2545 }
2546 else if (W == 1 && op == 3)
2547 {
4b7f6baa
CM		 2548 OUTS (outf, "[");
2549 OUTS (outf, pregs (ptr));
086134ec 2550 OUTS (outf, " + ");
4b7f6baa 2551 OUTS (outf, uimm4s4 (offset));
086134ec 2552 OUTS (outf, "] = ");
4b7f6baa 2553 OUTS (outf, pregs (reg));
4b7f6baa
CM		 2554 }
2555 else
b7d48530
NC		 2556 return 0;
2557
2558 return 2;
4b7f6baa
CM		 2559}
2560
2561static int
2562decode_LoopSetup_0 (TIword iw0, TIword iw1, bfd_vma pc, disassemble_info *outf)
2563{
703ec4e8 2564 struct private *priv = outf->private_data;
b7d48530
NC		 2565 /* LoopSetup
2566 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2567 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 1 |.rop...|.c.|.soffset.......|
2568 |.reg...........| - | - |.eoffset...............................|
2569 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
4b7f6baa
CM		 2570 int c = ((iw0 >> (LoopSetup_c_bits - 16)) & LoopSetup_c_mask);
2571 int reg = ((iw1 >> LoopSetup_reg_bits) & LoopSetup_reg_mask);
2572 int rop = ((iw0 >> (LoopSetup_rop_bits - 16)) & LoopSetup_rop_mask);
2573 int soffset = ((iw0 >> (LoopSetup_soffset_bits - 16)) & LoopSetup_soffset_mask);
2574 int eoffset = ((iw1 >> LoopSetup_eoffset_bits) & LoopSetup_eoffset_mask);
2575
703ec4e8 2576 if (priv->parallel)
219b747a
MF		 2577 return 0;
2578
298c1ec2
MF		 2579 if (reg > 7)
2580 return 0;
2581
4b7f6baa
CM		 2582 if (rop == 0)
2583 {
4b7f6baa 2584 OUTS (outf, "LSETUP");
086134ec 2585 OUTS (outf, "(0x");
4b7f6baa 2586 OUTS (outf, pcrel4 (soffset));
086134ec 2587 OUTS (outf, ", 0x");
4b7f6baa 2588 OUTS (outf, lppcrel10 (eoffset));
086134ec 2589 OUTS (outf, ") ");
4b7f6baa 2590 OUTS (outf, counters (c));
4b7f6baa
CM		 2591 }
2592 else if (rop == 1)
2593 {
4b7f6baa 2594 OUTS (outf, "LSETUP");
086134ec 2595 OUTS (outf, "(0x");
4b7f6baa 2596 OUTS (outf, pcrel4 (soffset));
086134ec 2597 OUTS (outf, ", 0x");
4b7f6baa 2598 OUTS (outf, lppcrel10 (eoffset));
086134ec 2599 OUTS (outf, ") ");
4b7f6baa 2600 OUTS (outf, counters (c));
086134ec 2601 OUTS (outf, " = ");
4b7f6baa 2602 OUTS (outf, pregs (reg));
4b7f6baa
CM		 2603 }
2604 else if (rop == 3)
2605 {
4b7f6baa 2606 OUTS (outf, "LSETUP");
086134ec 2607 OUTS (outf, "(0x");
4b7f6baa 2608 OUTS (outf, pcrel4 (soffset));
086134ec 2609 OUTS (outf, ", 0x");
4b7f6baa 2610 OUTS (outf, lppcrel10 (eoffset));
086134ec 2611 OUTS (outf, ") ");
4b7f6baa 2612 OUTS (outf, counters (c));
086134ec 2613 OUTS (outf, " = ");
4b7f6baa 2614 OUTS (outf, pregs (reg));
086134ec 2615 OUTS (outf, " >> 0x1");
4b7f6baa
CM		 2616 }
2617 else
b7d48530
NC		 2618 return 0;
2619
2620 return 4;
4b7f6baa
CM		 2621}
2622
2623static int
2624decode_LDIMMhalf_0 (TIword iw0, TIword iw1, disassemble_info *outf)
2625{
703ec4e8 2626 struct private *priv = outf->private_data;
b7d48530
NC		 2627 /* LDIMMhalf
2628 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2629 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 1 |.Z.|.H.|.S.|.grp...|.reg.......|
2630 |.hword.........................................................|
2631 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
4b7f6baa
CM		 2632 int H = ((iw0 >> (LDIMMhalf_H_bits - 16)) & LDIMMhalf_H_mask);
2633 int Z = ((iw0 >> (LDIMMhalf_Z_bits - 16)) & LDIMMhalf_Z_mask);
2634 int S = ((iw0 >> (LDIMMhalf_S_bits - 16)) & LDIMMhalf_S_mask);
2635 int reg = ((iw0 >> (LDIMMhalf_reg_bits - 16)) & LDIMMhalf_reg_mask);
2636 int grp = ((iw0 >> (LDIMMhalf_grp_bits - 16)) & LDIMMhalf_grp_mask);
2637 int hword = ((iw1 >> LDIMMhalf_hword_bits) & LDIMMhalf_hword_mask);
2638
b21c9cb4
BS		 2639 bu32 *pval = get_allreg (grp, reg);
2640
703ec4e8 2641 if (priv->parallel)
219b747a
MF		 2642 return 0;
2643
b21c9cb4
BS		 2644 /* Since we don't have 32-bit immediate loads, we allow the disassembler
2645 to combine them, so it prints out the right values.
2646 Here we keep track of the registers. */
2647 if (H == 0 && S == 1 && Z == 0)
2648 {
2649 /* regs = imm16 (x) */
2650 *pval = imm16_val (hword);
086134ec
BS		 2651 if (hword & 0x8000)
2652 *pval |= 0xFFFF0000;
2653 else
2654 *pval &= 0xFFFF;
b21c9cb4
BS		 2655 }
2656 else if (H == 0 && S == 0 && Z == 1)
2657 {
2658 /* regs = luimm16 (Z) */
2659 *pval = luimm16_val (hword);
086134ec 2660 *pval &= 0xFFFF;
b21c9cb4
BS		 2661 }
2662 else if (H == 0 && S == 0 && Z == 0)
2663 {
2664 /* regs_lo = luimm16 */
2665 *pval &= 0xFFFF0000;
2666 *pval |= luimm16_val (hword);
2667 }
2668 else if (H == 1 && S == 0 && Z == 0)
2669 {
2670 /* regs_hi = huimm16 */
2671 *pval &= 0xFFFF;
2672 *pval |= luimm16_val (hword) << 16;
2673 }
2674
2675 /* Here we do the disassembly */
4b7f6baa
CM		 2676 if (grp == 0 && H == 0 && S == 0 && Z == 0)
2677 {
4b7f6baa 2678 OUTS (outf, dregs_lo (reg));
086134ec
BS		 2679 OUTS (outf, " = ");
2680 OUTS (outf, uimm16 (hword));
4b7f6baa
CM		 2681 }
2682 else if (grp == 0 && H == 1 && S == 0 && Z == 0)
2683 {
4b7f6baa 2684 OUTS (outf, dregs_hi (reg));
086134ec
BS		 2685 OUTS (outf, " = ");
2686 OUTS (outf, uimm16 (hword));
4b7f6baa
CM		 2687 }
2688 else if (grp == 0 && H == 0 && S == 1 && Z == 0)
2689 {
4b7f6baa 2690 OUTS (outf, dregs (reg));
086134ec 2691 OUTS (outf, " = ");
4b7f6baa
CM		 2692 OUTS (outf, imm16 (hword));
2693 OUTS (outf, " (X)");
4b7f6baa
CM		 2694 }
2695 else if (H == 0 && S == 1 && Z == 0)
602427c4 2696 {
4b7f6baa 2697 OUTS (outf, regs (reg, grp));
086134ec 2698 OUTS (outf, " = ");
4b7f6baa
CM		 2699 OUTS (outf, imm16 (hword));
2700 OUTS (outf, " (X)");
4b7f6baa
CM		 2701 }
2702 else if (H == 0 && S == 0 && Z == 1)
2703 {
4b7f6baa 2704 OUTS (outf, regs (reg, grp));
086134ec
BS		 2705 OUTS (outf, " = ");
2706 OUTS (outf, uimm16 (hword));
2707 OUTS (outf, " (Z)");
4b7f6baa
CM		 2708 }
2709 else if (H == 0 && S == 0 && Z == 0)
2710 {
4b7f6baa 2711 OUTS (outf, regs_lo (reg, grp));
086134ec 2712 OUTS (outf, " = ");
b21c9cb4 2713 OUTS (outf, uimm16 (hword));
4b7f6baa
CM		 2714 }
2715 else if (H == 1 && S == 0 && Z == 0)
2716 {
4b7f6baa 2717 OUTS (outf, regs_hi (reg, grp));
086134ec 2718 OUTS (outf, " = ");
b21c9cb4 2719 OUTS (outf, uimm16 (hword));
4b7f6baa
CM		 2720 }
2721 else
b7d48530
NC		 2722 return 0;
2723
b21c9cb4 2724 /* And we print out the 32-bit value if it is a pointer. */
086134ec 2725 if (S == 0 && Z == 0)
b21c9cb4 2726 {
086134ec
BS		 2727 OUTS (outf, ";\t\t/* (");
2728 OUTS (outf, imm16d (hword));
2729 OUTS (outf, ")\t");
2730
b21c9cb4 2731 /* If it is an MMR, don't print the symbol. */
086134ec
BS		 2732 if (*pval < 0xFFC00000 && grp == 1)
2733 {
2734 OUTS (outf, regs (reg, grp));
2735 OUTS (outf, "=0x");
2736 OUTS (outf, huimm32e (*pval));
2737 }
b21c9cb4 2738 else
086134ec
BS		 2739 {
2740 OUTS (outf, regs (reg, grp));
2741 OUTS (outf, "=0x");
2742 OUTS (outf, huimm32e (*pval));
2743 OUTS (outf, "(");
2744 OUTS (outf, imm32 (*pval));
2745 OUTS (outf, ")");
2746 }
b21c9cb4
BS		 2747
2748 OUTS (outf, " */");
60ac5798 2749 priv->comment = TRUE;
086134ec
BS		 2750 }
2751 if (S == 1 || Z == 1)
2752 {
602427c4
MF		 2753 OUTS (outf, ";\t\t/*\t\t");
2754 OUTS (outf, regs (reg, grp));
2755 OUTS (outf, "=0x");
2756 OUTS (outf, huimm32e (*pval));
2757 OUTS (outf, "(");
2758 OUTS (outf, imm32 (*pval));
2759 OUTS (outf, ") */");
60ac5798 2760 priv->comment = TRUE;
b21c9cb4 2761 }
b7d48530 2762 return 4;
4b7f6baa
CM		 2763}
2764
2765static int
2766decode_CALLa_0 (TIword iw0, TIword iw1, bfd_vma pc, disassemble_info *outf)
2767{
703ec4e8 2768 struct private *priv = outf->private_data;
b7d48530
NC		 2769 /* CALLa
2770 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2771 | 1 | 1 | 1 | 0 | 0 | 0 | 1 |.S.|.msw...........................|
2772 |.lsw...........................................................|
2773 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
4b7f6baa
CM		 2774 int S = ((iw0 >> (CALLa_S_bits - 16)) & CALLa_S_mask);
2775 int lsw = ((iw1 >> 0) & 0xffff);
2776 int msw = ((iw0 >> 0) & 0xff);
2777
703ec4e8 2778 if (priv->parallel)
219b747a
MF		 2779 return 0;
2780
4b7f6baa 2781 if (S == 1)
086134ec 2782 OUTS (outf, "CALL 0x");
4b7f6baa 2783 else if (S == 0)
086134ec 2784 OUTS (outf, "JUMP.L 0x");
4b7f6baa 2785 else
b7d48530
NC		 2786 return 0;
2787
2788 OUTS (outf, pcrel24 (((msw) << 16) | (lsw)));
2789 return 4;
4b7f6baa
CM		 2790}
2791
2792static int
2793decode_LDSTidxI_0 (TIword iw0, TIword iw1, disassemble_info *outf)
2794{
b7d48530
NC		 2795 /* LDSTidxI
2796 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2797 | 1 | 1 | 1 | 0 | 0 | 1 |.W.|.Z.|.sz....|.ptr.......|.reg.......|
2798 |.offset........................................................|
2799 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
4b7f6baa
CM		 2800 int Z = ((iw0 >> (LDSTidxI_Z_bits - 16)) & LDSTidxI_Z_mask);
2801 int W = ((iw0 >> (LDSTidxI_W_bits - 16)) & LDSTidxI_W_mask);
2802 int sz = ((iw0 >> (LDSTidxI_sz_bits - 16)) & LDSTidxI_sz_mask);
2803 int reg = ((iw0 >> (LDSTidxI_reg_bits - 16)) & LDSTidxI_reg_mask);
2804 int ptr = ((iw0 >> (LDSTidxI_ptr_bits - 16)) & LDSTidxI_ptr_mask);
2805 int offset = ((iw1 >> LDSTidxI_offset_bits) & LDSTidxI_offset_mask);
2806
2807 if (W == 0 && sz == 0 && Z == 0)
2808 {
4b7f6baa 2809 OUTS (outf, dregs (reg));
086134ec 2810 OUTS (outf, " = [");
4b7f6baa 2811 OUTS (outf, pregs (ptr));
086134ec 2812 OUTS (outf, " + ");
4b7f6baa
CM		 2813 OUTS (outf, imm16s4 (offset));
2814 OUTS (outf, "]");
4b7f6baa
CM		 2815 }
2816 else if (W == 0 && sz == 0 && Z == 1)
2817 {
4b7f6baa 2818 OUTS (outf, pregs (reg));
086134ec 2819 OUTS (outf, " = [");
4b7f6baa 2820 OUTS (outf, pregs (ptr));
086134ec 2821 OUTS (outf, " + ");
4b7f6baa
CM		 2822 OUTS (outf, imm16s4 (offset));
2823 OUTS (outf, "]");
4b7f6baa
CM		 2824 }
2825 else if (W == 0 && sz == 1 && Z == 0)
2826 {
4b7f6baa 2827 OUTS (outf, dregs (reg));
086134ec 2828 OUTS (outf, " = W[");
4b7f6baa 2829 OUTS (outf, pregs (ptr));
086134ec 2830 OUTS (outf, " + ");
4b7f6baa
CM		 2831 OUTS (outf, imm16s2 (offset));
2832 OUTS (outf, "] (Z)");
4b7f6baa
CM		 2833 }
2834 else if (W == 0 && sz == 1 && Z == 1)
2835 {
4b7f6baa 2836 OUTS (outf, dregs (reg));
086134ec 2837 OUTS (outf, " = W[");
4b7f6baa 2838 OUTS (outf, pregs (ptr));
086134ec 2839 OUTS (outf, " + ");
4b7f6baa 2840 OUTS (outf, imm16s2 (offset));
086134ec 2841 OUTS (outf, "] (X)");
4b7f6baa
CM		 2842 }
2843 else if (W == 0 && sz == 2 && Z == 0)
2844 {
4b7f6baa 2845 OUTS (outf, dregs (reg));
086134ec 2846 OUTS (outf, " = B[");
4b7f6baa 2847 OUTS (outf, pregs (ptr));
086134ec 2848 OUTS (outf, " + ");
4b7f6baa
CM		 2849 OUTS (outf, imm16 (offset));
2850 OUTS (outf, "] (Z)");
4b7f6baa
CM		 2851 }
2852 else if (W == 0 && sz == 2 && Z == 1)
2853 {
4b7f6baa 2854 OUTS (outf, dregs (reg));
086134ec 2855 OUTS (outf, " = B[");
4b7f6baa 2856 OUTS (outf, pregs (ptr));
086134ec 2857 OUTS (outf, " + ");
4b7f6baa 2858 OUTS (outf, imm16 (offset));
086134ec 2859 OUTS (outf, "] (X)");
4b7f6baa
CM		 2860 }
2861 else if (W == 1 && sz == 0 && Z == 0)
2862 {
4b7f6baa
CM		 2863 OUTS (outf, "[");
2864 OUTS (outf, pregs (ptr));
086134ec 2865 OUTS (outf, " + ");
4b7f6baa 2866 OUTS (outf, imm16s4 (offset));
086134ec 2867 OUTS (outf, "] = ");
4b7f6baa 2868 OUTS (outf, dregs (reg));
4b7f6baa
CM		 2869 }
2870 else if (W == 1 && sz == 0 && Z == 1)
2871 {
4b7f6baa
CM		 2872 OUTS (outf, "[");
2873 OUTS (outf, pregs (ptr));
086134ec 2874 OUTS (outf, " + ");
4b7f6baa 2875 OUTS (outf, imm16s4 (offset));
086134ec 2876 OUTS (outf, "] = ");
4b7f6baa 2877 OUTS (outf, pregs (reg));
4b7f6baa
CM		 2878 }
2879 else if (W == 1 && sz == 1 && Z == 0)
2880 {
4b7f6baa
CM		 2881 OUTS (outf, "W[");
2882 OUTS (outf, pregs (ptr));
086134ec 2883 OUTS (outf, " + ");
4b7f6baa 2884 OUTS (outf, imm16s2 (offset));
086134ec 2885 OUTS (outf, "] = ");
4b7f6baa 2886 OUTS (outf, dregs (reg));
4b7f6baa
CM		 2887 }
2888 else if (W == 1 && sz == 2 && Z == 0)
2889 {
4b7f6baa
CM		 2890 OUTS (outf, "B[");
2891 OUTS (outf, pregs (ptr));
086134ec 2892 OUTS (outf, " + ");
4b7f6baa 2893 OUTS (outf, imm16 (offset));
086134ec 2894 OUTS (outf, "] = ");
4b7f6baa 2895 OUTS (outf, dregs (reg));
4b7f6baa
CM		 2896 }
2897 else
b7d48530
NC		 2898 return 0;
2899
2900 return 4;
4b7f6baa
CM		 2901}
2902
2903static int
2904decode_linkage_0 (TIword iw0, TIword iw1, disassemble_info *outf)
2905{
703ec4e8 2906 struct private *priv = outf->private_data;
b7d48530
NC		 2907 /* linkage
2908 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2909 | 1 | 1 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |.R.|
2910 |.framesize.....................................................|
2911 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
4b7f6baa
CM		 2912 int R = ((iw0 >> (Linkage_R_bits - 16)) & Linkage_R_mask);
2913 int framesize = ((iw1 >> Linkage_framesize_bits) & Linkage_framesize_mask);
2914
703ec4e8 2915 if (priv->parallel)
219b747a
MF		 2916 return 0;
2917
4b7f6baa
CM		 2918 if (R == 0)
2919 {
4b7f6baa
CM		 2920 OUTS (outf, "LINK ");
2921 OUTS (outf, uimm16s4 (framesize));
086134ec
BS		 2922 OUTS (outf, ";\t\t/* (");
2923 OUTS (outf, uimm16s4d (framesize));
2924 OUTS (outf, ") */");
60ac5798 2925 priv->comment = TRUE;
4b7f6baa
CM		 2926 }
2927 else if (R == 1)
b7d48530 2928 OUTS (outf, "UNLINK");
4b7f6baa 2929 else
b7d48530
NC		 2930 return 0;
2931
2932 return 4;
4b7f6baa
CM		 2933}
2934
2935static int
2936decode_dsp32mac_0 (TIword iw0, TIword iw1, disassemble_info *outf)
2937{
b7d48530
NC		 2938 /* dsp32mac
2939 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2940 | 1 | 1 | 0 | 0 |.M.| 0 | 0 |.mmod..........|.MM|.P.|.w1|.op1...|
2941 |.h01|.h11|.w0|.op0...|.h00|.h10|.dst.......|.src0......|.src1..|
2942 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
2943 int op1 = ((iw0 >> (DSP32Mac_op1_bits - 16)) & DSP32Mac_op1_mask);
2944 int w1 = ((iw0 >> (DSP32Mac_w1_bits - 16)) & DSP32Mac_w1_mask);
2945 int P = ((iw0 >> (DSP32Mac_p_bits - 16)) & DSP32Mac_p_mask);
2946 int MM = ((iw0 >> (DSP32Mac_MM_bits - 16)) & DSP32Mac_MM_mask);
4b7f6baa 2947 int mmod = ((iw0 >> (DSP32Mac_mmod_bits - 16)) & DSP32Mac_mmod_mask);
b7d48530 2948 int w0 = ((iw1 >> DSP32Mac_w0_bits) & DSP32Mac_w0_mask);
4b7f6baa
CM		 2949 int src0 = ((iw1 >> DSP32Mac_src0_bits) & DSP32Mac_src0_mask);
2950 int src1 = ((iw1 >> DSP32Mac_src1_bits) & DSP32Mac_src1_mask);
b7d48530
NC		 2951 int dst = ((iw1 >> DSP32Mac_dst_bits) & DSP32Mac_dst_mask);
2952 int h10 = ((iw1 >> DSP32Mac_h10_bits) & DSP32Mac_h10_mask);
2953 int h00 = ((iw1 >> DSP32Mac_h00_bits) & DSP32Mac_h00_mask);
2954 int op0 = ((iw1 >> DSP32Mac_op0_bits) & DSP32Mac_op0_mask);
2955 int h11 = ((iw1 >> DSP32Mac_h11_bits) & DSP32Mac_h11_mask);
2956 int h01 = ((iw1 >> DSP32Mac_h01_bits) & DSP32Mac_h01_mask);
4b7f6baa
CM		 2957
2958 if (w0 == 0 && w1 == 0 && op1 == 3 && op0 == 3)
2959 return 0;
2960
2961 if (op1 == 3 && MM)
2962 return 0;
2963
2964 if ((w1 || w0) && mmod == M_W32)
2965 return 0;
2966
ee171c8f 2967 if (((1 << mmod) & (P ? 0x131b : 0x1b5f)) == 0)
4b7f6baa
CM		 2968 return 0;
2969
2970 if (w1 == 1 || op1 != 3)
2971 {
2972 if (w1)
2973 OUTS (outf, P ? dregs (dst + 1) : dregs_hi (dst));
2974
2975 if (op1 == 3)
2976 OUTS (outf, " = A1");
2977 else
2978 {
2979 if (w1)
2980 OUTS (outf, " = (");
2981 decode_macfunc (1, op1, h01, h11, src0, src1, outf);
2982 if (w1)
2983 OUTS (outf, ")");
2984 }
2985
2986 if (w0 == 1 || op0 != 3)
2987 {
2988 if (MM)
2989 OUTS (outf, " (M)");
4b7f6baa
CM		 2990 OUTS (outf, ", ");
2991 }
2992 }
2993
2994 if (w0 == 1 || op0 != 3)
2995 {
67171547
MF		 2996 /* Clear MM option since it only matters for MAC1, and if we made
2997 it this far, we've already shown it or we want to ignore it. */
2998 MM = 0;
2999
4b7f6baa
CM		 3000 if (w0)
3001 OUTS (outf, P ? dregs (dst) : dregs_lo (dst));
3002
3003 if (op0 == 3)
3004 OUTS (outf, " = A0");
3005 else
3006 {
3007 if (w0)
3008 OUTS (outf, " = (");
3009 decode_macfunc (0, op0, h00, h10, src0, src1, outf);
3010 if (w0)
3011 OUTS (outf, ")");
3012 }
3013 }
3014
3015 decode_optmode (mmod, MM, outf);
3016
3017 return 4;
3018}
3019
3020static int
3021decode_dsp32mult_0 (TIword iw0, TIword iw1, disassemble_info *outf)
3022{
b7d48530
NC		 3023 /* dsp32mult
3024 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
3025 | 1 | 1 | 0 | 0 |.M.| 0 | 1 |.mmod..........|.MM|.P.|.w1|.op1...|
3026 |.h01|.h11|.w0|.op0...|.h00|.h10|.dst.......|.src0......|.src1..|
3027 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
3028 int w1 = ((iw0 >> (DSP32Mac_w1_bits - 16)) & DSP32Mac_w1_mask);
3029 int P = ((iw0 >> (DSP32Mac_p_bits - 16)) & DSP32Mac_p_mask);
3030 int MM = ((iw0 >> (DSP32Mac_MM_bits - 16)) & DSP32Mac_MM_mask);
4b7f6baa 3031 int mmod = ((iw0 >> (DSP32Mac_mmod_bits - 16)) & DSP32Mac_mmod_mask);
b7d48530 3032 int w0 = ((iw1 >> DSP32Mac_w0_bits) & DSP32Mac_w0_mask);
4b7f6baa
CM		 3033 int src0 = ((iw1 >> DSP32Mac_src0_bits) & DSP32Mac_src0_mask);
3034 int src1 = ((iw1 >> DSP32Mac_src1_bits) & DSP32Mac_src1_mask);
b7d48530
NC		 3035 int dst = ((iw1 >> DSP32Mac_dst_bits) & DSP32Mac_dst_mask);
3036 int h10 = ((iw1 >> DSP32Mac_h10_bits) & DSP32Mac_h10_mask);
3037 int h00 = ((iw1 >> DSP32Mac_h00_bits) & DSP32Mac_h00_mask);
3038 int h11 = ((iw1 >> DSP32Mac_h11_bits) & DSP32Mac_h11_mask);
3039 int h01 = ((iw1 >> DSP32Mac_h01_bits) & DSP32Mac_h01_mask);
4b7f6baa
CM		 3040
3041 if (w1 == 0 && w0 == 0)
3042 return 0;
b7d48530 3043
4b7f6baa
CM		 3044 if (((1 << mmod) & (P ? 0x313 : 0x1b57)) == 0)
3045 return 0;
b7d48530 3046
4b7f6baa
CM		 3047 if (w1)
3048 {
4db66394 3049 OUTS (outf, P ? dregs (dst + 1) : dregs_hi (dst));
4b7f6baa
CM		 3050 OUTS (outf, " = ");
3051 decode_multfunc (h01, h11, src0, src1, outf);
3052
3053 if (w0)
3054 {
3055 if (MM)
3056 OUTS (outf, " (M)");
3057 MM = 0;
3058 OUTS (outf, ", ");
3059 }
3060 }
3061
3062 if (w0)
3063 {
4db66394 3064 OUTS (outf, P ? dregs (dst) : dregs_lo (dst));
4b7f6baa
CM		 3065 OUTS (outf, " = ");
3066 decode_multfunc (h00, h10, src0, src1, outf);
3067 }
3068
3069 decode_optmode (mmod, MM, outf);
3070 return 4;
3071}
3072
3073static int
3074decode_dsp32alu_0 (TIword iw0, TIword iw1, disassemble_info *outf)
3075{
b7d48530
NC		 3076 /* dsp32alu
3077 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
3078 | 1 | 1 | 0 | 0 |.M.| 1 | 0 | - | - | - |.HL|.aopcde............|
3079 |.aop...|.s.|.x.|.dst0......|.dst1......|.src0......|.src1......|
3080 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
4b7f6baa
CM		 3081 int s = ((iw1 >> DSP32Alu_s_bits) & DSP32Alu_s_mask);
3082 int x = ((iw1 >> DSP32Alu_x_bits) & DSP32Alu_x_mask);
3083 int aop = ((iw1 >> DSP32Alu_aop_bits) & DSP32Alu_aop_mask);
3084 int src0 = ((iw1 >> DSP32Alu_src0_bits) & DSP32Alu_src0_mask);
3085 int src1 = ((iw1 >> DSP32Alu_src1_bits) & DSP32Alu_src1_mask);
3086 int dst0 = ((iw1 >> DSP32Alu_dst0_bits) & DSP32Alu_dst0_mask);
3087 int dst1 = ((iw1 >> DSP32Alu_dst1_bits) & DSP32Alu_dst1_mask);
3088 int HL = ((iw0 >> (DSP32Alu_HL_bits - 16)) & DSP32Alu_HL_mask);
3089 int aopcde = ((iw0 >> (DSP32Alu_aopcde_bits - 16)) & DSP32Alu_aopcde_mask);
3090
3091 if (aop == 0 && aopcde == 9 && HL == 0 && s == 0)
3092 {
086134ec 3093 OUTS (outf, "A0.L = ");
4b7f6baa 3094 OUTS (outf, dregs_lo (src0));
4b7f6baa
CM		 3095 }
3096 else if (aop == 2 && aopcde == 9 && HL == 1 && s == 0)
3097 {
086134ec 3098 OUTS (outf, "A1.H = ");
4b7f6baa 3099 OUTS (outf, dregs_hi (src0));
4b7f6baa
CM		 3100 }
3101 else if (aop == 2 && aopcde == 9 && HL == 0 && s == 0)
3102 {
086134ec 3103 OUTS (outf, "A1.L = ");
4b7f6baa 3104 OUTS (outf, dregs_lo (src0));
4b7f6baa
CM		 3105 }
3106 else if (aop == 0 && aopcde == 9 && HL == 1 && s == 0)
3107 {
086134ec 3108 OUTS (outf, "A0.H = ");
4b7f6baa 3109 OUTS (outf, dregs_hi (src0));
4b7f6baa
CM		 3110 }
3111 else if (x == 1 && HL == 1 && aop == 3 && aopcde == 5)
3112 {
4b7f6baa 3113 OUTS (outf, dregs_hi (dst0));
086134ec 3114 OUTS (outf, " = ");
4b7f6baa 3115 OUTS (outf, dregs (src0));
086134ec 3116 OUTS (outf, " - ");
4b7f6baa 3117 OUTS (outf, dregs (src1));
086134ec 3118 OUTS (outf, " (RND20)");
4b7f6baa
CM		 3119 }
3120 else if (x == 1 && HL == 1 && aop == 2 && aopcde == 5)
3121 {
4b7f6baa 3122 OUTS (outf, dregs_hi (dst0));
086134ec 3123 OUTS (outf, " = ");
4b7f6baa 3124 OUTS (outf, dregs (src0));
086134ec 3125 OUTS (outf, " + ");
4b7f6baa 3126 OUTS (outf, dregs (src1));
086134ec 3127 OUTS (outf, " (RND20)");
4b7f6baa
CM		 3128 }
3129 else if (x == 0 && HL == 0 && aop == 1 && aopcde == 5)
3130 {
4b7f6baa 3131 OUTS (outf, dregs_lo (dst0));
086134ec 3132 OUTS (outf, " = ");
4b7f6baa 3133 OUTS (outf, dregs (src0));
086134ec 3134 OUTS (outf, " - ");
4b7f6baa 3135 OUTS (outf, dregs (src1));
086134ec 3136 OUTS (outf, " (RND12)");
4b7f6baa
CM		 3137 }
3138 else if (x == 0 && HL == 0 && aop == 0 && aopcde == 5)
3139 {
4b7f6baa 3140 OUTS (outf, dregs_lo (dst0));
086134ec 3141 OUTS (outf, " = ");
4b7f6baa 3142 OUTS (outf, dregs (src0));
086134ec 3143 OUTS (outf, " + ");
4b7f6baa 3144 OUTS (outf, dregs (src1));
086134ec 3145 OUTS (outf, " (RND12)");
4b7f6baa
CM		 3146 }
3147 else if (x == 1 && HL == 0 && aop == 3 && aopcde == 5)
3148 {
4b7f6baa 3149 OUTS (outf, dregs_lo (dst0));
086134ec 3150 OUTS (outf, " = ");
4b7f6baa 3151 OUTS (outf, dregs (src0));
086134ec 3152 OUTS (outf, " - ");
4b7f6baa 3153 OUTS (outf, dregs (src1));
086134ec 3154 OUTS (outf, " (RND20)");
4b7f6baa
CM		 3155 }
3156 else if (x == 0 && HL == 1 && aop == 0 && aopcde == 5)
3157 {
4b7f6baa 3158 OUTS (outf, dregs_hi (dst0));
086134ec 3159 OUTS (outf, " = ");
4b7f6baa 3160 OUTS (outf, dregs (src0));
086134ec 3161 OUTS (outf, " + ");
4b7f6baa 3162 OUTS (outf, dregs (src1));
086134ec 3163 OUTS (outf, " (RND12)");
4b7f6baa
CM		 3164 }
3165 else if (x == 1 && HL == 0 && aop == 2 && aopcde == 5)
3166 {
4b7f6baa 3167 OUTS (outf, dregs_lo (dst0));
086134ec 3168 OUTS (outf, " = ");
4b7f6baa 3169 OUTS (outf, dregs (src0));
086134ec 3170 OUTS (outf, " + ");
4b7f6baa 3171 OUTS (outf, dregs (src1));
086134ec 3172 OUTS (outf, " (RND20)");
4b7f6baa
CM		 3173 }
3174 else if (x == 0 && HL == 1 && aop == 1 && aopcde == 5)
3175 {
4b7f6baa 3176 OUTS (outf, dregs_hi (dst0));
086134ec 3177 OUTS (outf, " = ");
4b7f6baa 3178 OUTS (outf, dregs (src0));
086134ec 3179 OUTS (outf, " - ");
4b7f6baa 3180 OUTS (outf, dregs (src1));
086134ec 3181 OUTS (outf, " (RND12)");
4b7f6baa
CM		 3182 }
3183 else if (HL == 1 && aop == 0 && aopcde == 2)
3184 {
4b7f6baa 3185 OUTS (outf, dregs_hi (dst0));
086134ec 3186 OUTS (outf, " = ");
4b7f6baa 3187 OUTS (outf, dregs_lo (src0));
086134ec 3188 OUTS (outf, " + ");
4b7f6baa 3189 OUTS (outf, dregs_lo (src1));
4b7f6baa 3190 amod1 (s, x, outf);
4b7f6baa
CM		 3191 }
3192 else if (HL == 1 && aop == 1 && aopcde == 2)
3193 {
4b7f6baa 3194 OUTS (outf, dregs_hi (dst0));
086134ec 3195 OUTS (outf, " = ");
4b7f6baa 3196 OUTS (outf, dregs_lo (src0));
086134ec 3197 OUTS (outf, " + ");
4b7f6baa 3198 OUTS (outf, dregs_hi (src1));
4b7f6baa 3199 amod1 (s, x, outf);
4b7f6baa
CM		 3200 }
3201 else if (HL == 1 && aop == 2 && aopcde == 2)
3202 {
4b7f6baa 3203 OUTS (outf, dregs_hi (dst0));
086134ec 3204 OUTS (outf, " = ");
4b7f6baa 3205 OUTS (outf, dregs_hi (src0));
086134ec 3206 OUTS (outf, " + ");
4b7f6baa 3207 OUTS (outf, dregs_lo (src1));
4b7f6baa 3208 amod1 (s, x, outf);
4b7f6baa
CM		 3209 }
3210 else if (HL == 1 && aop == 3 && aopcde == 2)
3211 {
4b7f6baa 3212 OUTS (outf, dregs_hi (dst0));
086134ec 3213 OUTS (outf, " = ");
4b7f6baa 3214 OUTS (outf, dregs_hi (src0));
086134ec 3215 OUTS (outf, " + ");
4b7f6baa 3216 OUTS (outf, dregs_hi (src1));
4b7f6baa 3217 amod1 (s, x, outf);
4b7f6baa
CM		 3218 }
3219 else if (HL == 0 && aop == 0 && aopcde == 3)
3220 {
4b7f6baa 3221 OUTS (outf, dregs_lo (dst0));
086134ec 3222 OUTS (outf, " = ");
4b7f6baa 3223 OUTS (outf, dregs_lo (src0));
086134ec 3224 OUTS (outf, " - ");
4b7f6baa 3225 OUTS (outf, dregs_lo (src1));
4b7f6baa 3226 amod1 (s, x, outf);
4b7f6baa
CM		 3227 }
3228 else if (HL == 0 && aop == 1 && aopcde == 3)
3229 {
4b7f6baa 3230 OUTS (outf, dregs_lo (dst0));
086134ec 3231 OUTS (outf, " = ");
4b7f6baa 3232 OUTS (outf, dregs_lo (src0));
086134ec 3233 OUTS (outf, " - ");
4b7f6baa 3234 OUTS (outf, dregs_hi (src1));
4b7f6baa 3235 amod1 (s, x, outf);
4b7f6baa
CM		 3236 }
3237 else if (HL == 0 && aop == 3 && aopcde == 2)
3238 {
4b7f6baa 3239 OUTS (outf, dregs_lo (dst0));
086134ec 3240 OUTS (outf, " = ");
4b7f6baa 3241 OUTS (outf, dregs_hi (src0));
086134ec 3242 OUTS (outf, " + ");
4b7f6baa 3243 OUTS (outf, dregs_hi (src1));
4b7f6baa 3244 amod1 (s, x, outf);
4b7f6baa
CM		 3245 }
3246 else if (HL == 1 && aop == 0 && aopcde == 3)
3247 {
4b7f6baa 3248 OUTS (outf, dregs_hi (dst0));
086134ec 3249 OUTS (outf, " = ");
4b7f6baa 3250 OUTS (outf, dregs_lo (src0));
086134ec 3251 OUTS (outf, " - ");
4b7f6baa 3252 OUTS (outf, dregs_lo (src1));
4b7f6baa 3253 amod1 (s, x, outf);
4b7f6baa
CM		 3254 }
3255 else if (HL == 1 && aop == 1 && aopcde == 3)
3256 {
4b7f6baa 3257 OUTS (outf, dregs_hi (dst0));
086134ec 3258 OUTS (outf, " = ");
4b7f6baa 3259 OUTS (outf, dregs_lo (src0));
086134ec 3260 OUTS (outf, " - ");
4b7f6baa 3261 OUTS (outf, dregs_hi (src1));
4b7f6baa 3262 amod1 (s, x, outf);
4b7f6baa
CM		 3263 }
3264 else if (HL == 1 && aop == 2 && aopcde == 3)
3265 {
4b7f6baa 3266 OUTS (outf, dregs_hi (dst0));
086134ec 3267 OUTS (outf, " = ");
4b7f6baa 3268 OUTS (outf, dregs_hi (src0));
086134ec 3269 OUTS (outf, " - ");
4b7f6baa 3270 OUTS (outf, dregs_lo (src1));
4b7f6baa 3271 amod1 (s, x, outf);
4b7f6baa
CM		 3272 }
3273 else if (HL == 1 && aop == 3 && aopcde == 3)
3274 {
4b7f6baa 3275 OUTS (outf, dregs_hi (dst0));
086134ec 3276 OUTS (outf, " = ");
4b7f6baa 3277 OUTS (outf, dregs_hi (src0));
086134ec 3278 OUTS (outf, " - ");
4b7f6baa 3279 OUTS (outf, dregs_hi (src1));
4b7f6baa 3280 amod1 (s, x, outf);
4b7f6baa
CM		 3281 }
3282 else if (HL == 0 && aop == 2 && aopcde == 2)
3283 {
4b7f6baa 3284 OUTS (outf, dregs_lo (dst0));
086134ec 3285 OUTS (outf, " = ");
4b7f6baa 3286 OUTS (outf, dregs_hi (src0));
086134ec 3287 OUTS (outf, " + ");
4b7f6baa 3288 OUTS (outf, dregs_lo (src1));
4b7f6baa 3289 amod1 (s, x, outf);
4b7f6baa
CM		 3290 }
3291 else if (HL == 0 && aop == 1 && aopcde == 2)
3292 {
4b7f6baa 3293 OUTS (outf, dregs_lo (dst0));
086134ec 3294 OUTS (outf, " = ");
4b7f6baa 3295 OUTS (outf, dregs_lo (src0));
086134ec 3296 OUTS (outf, " + ");
4b7f6baa 3297 OUTS (outf, dregs_hi (src1));
4b7f6baa 3298 amod1 (s, x, outf);
4b7f6baa
CM		 3299 }
3300 else if (HL == 0 && aop == 2 && aopcde == 3)
3301 {
4b7f6baa 3302 OUTS (outf, dregs_lo (dst0));
086134ec 3303 OUTS (outf, " = ");
4b7f6baa 3304 OUTS (outf, dregs_hi (src0));
086134ec 3305 OUTS (outf, " - ");
4b7f6baa 3306 OUTS (outf, dregs_lo (src1));
4b7f6baa 3307 amod1 (s, x, outf);
4b7f6baa
CM		 3308 }
3309 else if (HL == 0 && aop == 3 && aopcde == 3)
3310 {
4b7f6baa 3311 OUTS (outf, dregs_lo (dst0));
086134ec 3312 OUTS (outf, " = ");
4b7f6baa 3313 OUTS (outf, dregs_hi (src0));
086134ec 3314 OUTS (outf, " - ");
4b7f6baa 3315 OUTS (outf, dregs_hi (src1));
4b7f6baa 3316 amod1 (s, x, outf);
4b7f6baa
CM		 3317 }
3318 else if (HL == 0 && aop == 0 && aopcde == 2)
3319 {
4b7f6baa 3320 OUTS (outf, dregs_lo (dst0));
086134ec 3321 OUTS (outf, " = ");
4b7f6baa 3322 OUTS (outf, dregs_lo (src0));
086134ec 3323 OUTS (outf, " + ");
4b7f6baa 3324 OUTS (outf, dregs_lo (src1));
4b7f6baa 3325 amod1 (s, x, outf);
4b7f6baa
CM		 3326 }
3327 else if (aop == 0 && aopcde == 9 && s == 1)
3328 {
086134ec 3329 OUTS (outf, "A0 = ");
4b7f6baa 3330 OUTS (outf, dregs (src0));
4b7f6baa
CM		 3331 }
3332 else if (aop == 3 && aopcde == 11 && s == 0)
086134ec 3333 OUTS (outf, "A0 -= A1");
b7d48530 3334
4b7f6baa 3335 else if (aop == 3 && aopcde == 11 && s == 1)
086134ec 3336 OUTS (outf, "A0 -= A1 (W32)");
b7d48530 3337
4b7f6baa
CM		 3338 else if (aop == 1 && aopcde == 22 && HL == 1)
3339 {
4b7f6baa 3340 OUTS (outf, dregs (dst0));
086134ec 3341 OUTS (outf, " = BYTEOP2P (");
4b7f6baa
CM		 3342 OUTS (outf, dregs (src0 + 1));
3343 OUTS (outf, ":");
086134ec
BS		 3344 OUTS (outf, imm5d (src0));
3345 OUTS (outf, ", ");
4b7f6baa
CM		 3346 OUTS (outf, dregs (src1 + 1));
3347 OUTS (outf, ":");
086134ec
BS		 3348 OUTS (outf, imm5d (src1));
3349 OUTS (outf, ") (TH");
4b7f6baa
CM		 3350 if (s == 1)
3351 OUTS (outf, ", R)");
3352 else
3353 OUTS (outf, ")");
4b7f6baa
CM		 3354 }
3355 else if (aop == 1 && aopcde == 22 && HL == 0)
3356 {
4b7f6baa 3357 OUTS (outf, dregs (dst0));
086134ec 3358 OUTS (outf, " = BYTEOP2P (");
4b7f6baa
CM		 3359 OUTS (outf, dregs (src0 + 1));
3360 OUTS (outf, ":");
086134ec
BS		 3361 OUTS (outf, imm5d (src0));
3362 OUTS (outf, ", ");
4b7f6baa
CM		 3363 OUTS (outf, dregs (src1 + 1));
3364 OUTS (outf, ":");
086134ec
BS		 3365 OUTS (outf, imm5d (src1));
3366 OUTS (outf, ") (TL");
4b7f6baa
CM		 3367 if (s == 1)
3368 OUTS (outf, ", R)");
3369 else
3370 OUTS (outf, ")");
4b7f6baa
CM		 3371 }
3372 else if (aop == 0 && aopcde == 22 && HL == 1)
3373 {
4b7f6baa 3374 OUTS (outf, dregs (dst0));
086134ec 3375 OUTS (outf, " = BYTEOP2P (");
4b7f6baa
CM		 3376 OUTS (outf, dregs (src0 + 1));
3377 OUTS (outf, ":");
086134ec
BS		 3378 OUTS (outf, imm5d (src0));
3379 OUTS (outf, ", ");
4b7f6baa
CM		 3380 OUTS (outf, dregs (src1 + 1));
3381 OUTS (outf, ":");
086134ec
BS		 3382 OUTS (outf, imm5d (src1));
3383 OUTS (outf, ") (RNDH");
4b7f6baa
CM		 3384 if (s == 1)
3385 OUTS (outf, ", R)");
3386 else
3387 OUTS (outf, ")");
4b7f6baa
CM		 3388 }
3389 else if (aop == 0 && aopcde == 22 && HL == 0)
3390 {
4b7f6baa 3391 OUTS (outf, dregs (dst0));
086134ec 3392 OUTS (outf, " = BYTEOP2P (");
4b7f6baa
CM		 3393 OUTS (outf, dregs (src0 + 1));
3394 OUTS (outf, ":");
086134ec
BS		 3395 OUTS (outf, imm5d (src0));
3396 OUTS (outf, ", ");
4b7f6baa
CM		 3397 OUTS (outf, dregs (src1 + 1));
3398 OUTS (outf, ":");
086134ec
BS		 3399 OUTS (outf, imm5d (src1));
3400 OUTS (outf, ") (RNDL");
4b7f6baa
CM		 3401 if (s == 1)
3402 OUTS (outf, ", R)");
3403 else
3404 OUTS (outf, ")");
4b7f6baa
CM		 3405 }
3406 else if (aop == 0 && s == 0 && aopcde == 8)
086134ec 3407 OUTS (outf, "A0 = 0");
b7d48530 3408
4b7f6baa 3409 else if (aop == 0 && s == 1 && aopcde == 8)
086134ec 3410 OUTS (outf, "A0 = A0 (S)");
b7d48530 3411
4b7f6baa 3412 else if (aop == 1 && s == 0 && aopcde == 8)
086134ec 3413 OUTS (outf, "A1 = 0");
b7d48530 3414
4b7f6baa 3415 else if (aop == 1 && s == 1 && aopcde == 8)
086134ec 3416 OUTS (outf, "A1 = A1 (S)");
b7d48530 3417
4b7f6baa 3418 else if (aop == 2 && s == 0 && aopcde == 8)
086134ec 3419 OUTS (outf, "A1 = A0 = 0");
b7d48530 3420
4b7f6baa 3421 else if (aop == 2 && s == 1 && aopcde == 8)
086134ec 3422 OUTS (outf, "A1 = A1 (S), A0 = A0 (S)");
b7d48530 3423
4b7f6baa 3424 else if (aop == 3 && s == 0 && aopcde == 8)
086134ec 3425 OUTS (outf, "A0 = A1");
b7d48530 3426
4b7f6baa 3427 else if (aop == 3 && s == 1 && aopcde == 8)
086134ec 3428 OUTS (outf, "A1 = A0");
b7d48530 3429
4b7f6baa
CM		 3430 else if (aop == 1 && aopcde == 9 && s == 0)
3431 {
086134ec 3432 OUTS (outf, "A0.X = ");
4b7f6baa 3433 OUTS (outf, dregs_lo (src0));
4b7f6baa
CM		 3434 }
3435 else if (aop == 1 && HL == 0 && aopcde == 11)
3436 {
4b7f6baa 3437 OUTS (outf, dregs_lo (dst0));
086134ec 3438 OUTS (outf, " = (A0 += A1)");
4b7f6baa
CM		 3439 }
3440 else if (aop == 3 && HL == 0 && aopcde == 16)
13c02f06 3441 OUTS (outf, "A1 = ABS A1, A0 = ABS A0");
b7d48530 3442
4b7f6baa
CM		 3443 else if (aop == 0 && aopcde == 23 && HL == 1)
3444 {
4b7f6baa 3445 OUTS (outf, dregs (dst0));
086134ec 3446 OUTS (outf, " = BYTEOP3P (");
4b7f6baa
CM		 3447 OUTS (outf, dregs (src0 + 1));
3448 OUTS (outf, ":");
086134ec
BS		 3449 OUTS (outf, imm5d (src0));
3450 OUTS (outf, ", ");
4b7f6baa
CM		 3451 OUTS (outf, dregs (src1 + 1));
3452 OUTS (outf, ":");
086134ec
BS		 3453 OUTS (outf, imm5d (src1));
3454 OUTS (outf, ") (HI");
4b7f6baa
CM		 3455 if (s == 1)
3456 OUTS (outf, ", R)");
3457 else
3458 OUTS (outf, ")");
4b7f6baa
CM		 3459 }
3460 else if (aop == 3 && aopcde == 9 && s == 0)
3461 {
086134ec 3462 OUTS (outf, "A1.X = ");
4b7f6baa 3463 OUTS (outf, dregs_lo (src0));
4b7f6baa
CM		 3464 }
3465 else if (aop == 1 && HL == 1 && aopcde == 16)
086134ec 3466 OUTS (outf, "A1 = ABS A1");
b7d48530 3467
4b7f6baa 3468 else if (aop == 0 && HL == 1 && aopcde == 16)
086134ec 3469 OUTS (outf, "A1 = ABS A0");
b7d48530 3470
4b7f6baa
CM		 3471 else if (aop == 2 && aopcde == 9 && s == 1)
3472 {
086134ec 3473 OUTS (outf, "A1 = ");
4b7f6baa 3474 OUTS (outf, dregs (src0));
4b7f6baa
CM		 3475 }
3476 else if (HL == 0 && aop == 3 && aopcde == 12)
3477 {
4b7f6baa 3478 OUTS (outf, dregs_lo (dst0));
086134ec 3479 OUTS (outf, " = ");
4b7f6baa 3480 OUTS (outf, dregs (src0));
086134ec 3481 OUTS (outf, " (RND)");
4b7f6baa
CM		 3482 }
3483 else if (aop == 1 && HL == 0 && aopcde == 16)
086134ec 3484 OUTS (outf, "A0 = ABS A1");
b7d48530 3485
4b7f6baa 3486 else if (aop == 0 && HL == 0 && aopcde == 16)
086134ec 3487 OUTS (outf, "A0 = ABS A0");
b7d48530 3488
4b7f6baa
CM		 3489 else if (aop == 3 && HL == 0 && aopcde == 15)
3490 {
4b7f6baa 3491 OUTS (outf, dregs (dst0));
086134ec 3492 OUTS (outf, " = -");
4b7f6baa 3493 OUTS (outf, dregs (src0));
086134ec 3494 OUTS (outf, " (V)");
4b7f6baa
CM		 3495 }
3496 else if (aop == 3 && s == 1 && HL == 0 && aopcde == 7)
3497 {
4b7f6baa 3498 OUTS (outf, dregs (dst0));
086134ec 3499 OUTS (outf, " = -");
4b7f6baa 3500 OUTS (outf, dregs (src0));
086134ec 3501 OUTS (outf, " (S)");
4b7f6baa
CM		 3502 }
3503 else if (aop == 3 && s == 0 && HL == 0 && aopcde == 7)
3504 {
4b7f6baa 3505 OUTS (outf, dregs (dst0));
086134ec 3506 OUTS (outf, " = -");
4b7f6baa 3507 OUTS (outf, dregs (src0));
086134ec 3508 OUTS (outf, " (NS)");
4b7f6baa
CM		 3509 }
3510 else if (aop == 1 && HL == 1 && aopcde == 11)
3511 {
4b7f6baa 3512 OUTS (outf, dregs_hi (dst0));
086134ec 3513 OUTS (outf, " = (A0 += A1)");
4b7f6baa
CM		 3514 }
3515 else if (aop == 2 && aopcde == 11 && s == 0)
086134ec 3516 OUTS (outf, "A0 += A1");
b7d48530 3517
4b7f6baa 3518 else if (aop == 2 && aopcde == 11 && s == 1)
086134ec 3519 OUTS (outf, "A0 += A1 (W32)");
b7d48530 3520
4b7f6baa 3521 else if (aop == 3 && HL == 0 && aopcde == 14)
086134ec 3522 OUTS (outf, "A1 = -A1, A0 = -A0");
b7d48530 3523
4b7f6baa
CM		 3524 else if (HL == 1 && aop == 3 && aopcde == 12)
3525 {
4b7f6baa 3526 OUTS (outf, dregs_hi (dst0));
086134ec 3527 OUTS (outf, " = ");
4b7f6baa 3528 OUTS (outf, dregs (src0));
086134ec 3529 OUTS (outf, " (RND)");
4b7f6baa
CM		 3530 }
3531 else if (aop == 0 && aopcde == 23 && HL == 0)
3532 {
4b7f6baa 3533 OUTS (outf, dregs (dst0));
086134ec 3534 OUTS (outf, " = BYTEOP3P (");
4b7f6baa
CM		 3535 OUTS (outf, dregs (src0 + 1));
3536 OUTS (outf, ":");
086134ec
BS		 3537 OUTS (outf, imm5d (src0));
3538 OUTS (outf, ", ");
4b7f6baa
CM		 3539 OUTS (outf, dregs (src1 + 1));
3540 OUTS (outf, ":");
086134ec
BS		 3541 OUTS (outf, imm5d (src1));
3542 OUTS (outf, ") (LO");
4b7f6baa
CM		 3543 if (s == 1)
3544 OUTS (outf, ", R)");
3545 else
3546 OUTS (outf, ")");
4b7f6baa
CM		 3547 }
3548 else if (aop == 0 && HL == 0 && aopcde == 14)
086134ec 3549 OUTS (outf, "A0 = -A0");
b7d48530 3550
4b7f6baa 3551 else if (aop == 1 && HL == 0 && aopcde == 14)
086134ec 3552 OUTS (outf, "A0 = -A1");
b7d48530 3553
4b7f6baa 3554 else if (aop == 0 && HL == 1 && aopcde == 14)
086134ec 3555 OUTS (outf, "A1 = -A0");
b7d48530 3556
4b7f6baa 3557 else if (aop == 1 && HL == 1 && aopcde == 14)
086134ec 3558 OUTS (outf, "A1 = -A1");
b7d48530 3559
4b7f6baa
CM		 3560 else if (aop == 0 && aopcde == 12)
3561 {
4b7f6baa 3562 OUTS (outf, dregs_hi (dst0));
086134ec 3563 OUTS (outf, " = ");
4b7f6baa 3564 OUTS (outf, dregs_lo (dst0));
086134ec 3565 OUTS (outf, " = SIGN (");
4b7f6baa 3566 OUTS (outf, dregs_hi (src0));
086134ec 3567 OUTS (outf, ") * ");
4b7f6baa 3568 OUTS (outf, dregs_hi (src1));
086134ec 3569 OUTS (outf, " + SIGN (");
4b7f6baa 3570 OUTS (outf, dregs_lo (src0));
086134ec 3571 OUTS (outf, ") * ");
4b7f6baa 3572 OUTS (outf, dregs_lo (src1));
4b7f6baa
CM		 3573 }
3574 else if (aop == 2 && aopcde == 0)
3575 {
4b7f6baa 3576 OUTS (outf, dregs (dst0));
086134ec 3577 OUTS (outf, " = ");
4b7f6baa 3578 OUTS (outf, dregs (src0));
086134ec 3579 OUTS (outf, " -|+ ");
4b7f6baa 3580 OUTS (outf, dregs (src1));
4b7f6baa 3581 amod0 (s, x, outf);
4b7f6baa
CM		 3582 }
3583 else if (aop == 1 && aopcde == 12)
3584 {
4b7f6baa 3585 OUTS (outf, dregs (dst1));
086134ec 3586 OUTS (outf, " = A1.L + A1.H, ");
4b7f6baa 3587 OUTS (outf, dregs (dst0));
086134ec 3588 OUTS (outf, " = A0.L + A0.H");
4b7f6baa
CM		 3589 }
3590 else if (aop == 2 && aopcde == 4)
3591 {
4b7f6baa 3592 OUTS (outf, dregs (dst1));
086134ec 3593 OUTS (outf, " = ");
4b7f6baa 3594 OUTS (outf, dregs (src0));
086134ec 3595 OUTS (outf, " + ");
4b7f6baa 3596 OUTS (outf, dregs (src1));
086134ec 3597 OUTS (outf, ", ");
4b7f6baa 3598 OUTS (outf, dregs (dst0));
086134ec 3599 OUTS (outf, " = ");
4b7f6baa 3600 OUTS (outf, dregs (src0));
086134ec 3601 OUTS (outf, " - ");
4b7f6baa 3602 OUTS (outf, dregs (src1));
4b7f6baa 3603 amod1 (s, x, outf);
4b7f6baa
CM		 3604 }
3605 else if (HL == 0 && aopcde == 1)
3606 {
4b7f6baa 3607 OUTS (outf, dregs (dst1));
086134ec 3608 OUTS (outf, " = ");
4b7f6baa 3609 OUTS (outf, dregs (src0));
086134ec 3610 OUTS (outf, " +|+ ");
4b7f6baa 3611 OUTS (outf, dregs (src1));
086134ec 3612 OUTS (outf, ", ");
4b7f6baa 3613 OUTS (outf, dregs (dst0));
086134ec 3614 OUTS (outf, " = ");
4b7f6baa 3615 OUTS (outf, dregs (src0));
086134ec 3616 OUTS (outf, " -|- ");
4b7f6baa
CM		 3617 OUTS (outf, dregs (src1));
3618 amod0amod2 (s, x, aop, outf);
4b7f6baa
CM		 3619 }
3620 else if (aop == 0 && aopcde == 11)
3621 {
4b7f6baa 3622 OUTS (outf, dregs (dst0));
086134ec 3623 OUTS (outf, " = (A0 += A1)");
4b7f6baa
CM		 3624 }
3625 else if (aop == 0 && aopcde == 10)
3626 {
4b7f6baa 3627 OUTS (outf, dregs_lo (dst0));
086134ec 3628 OUTS (outf, " = A0.X");
4b7f6baa
CM		 3629 }
3630 else if (aop == 1 && aopcde == 10)
3631 {
4b7f6baa 3632 OUTS (outf, dregs_lo (dst0));
086134ec 3633 OUTS (outf, " = A1.X");
4b7f6baa
CM		 3634 }
3635 else if (aop == 1 && aopcde == 0)
3636 {
4b7f6baa 3637 OUTS (outf, dregs (dst0));
086134ec 3638 OUTS (outf, " = ");
4b7f6baa 3639 OUTS (outf, dregs (src0));
086134ec 3640 OUTS (outf, " +|- ");
4b7f6baa 3641 OUTS (outf, dregs (src1));
4b7f6baa 3642 amod0 (s, x, outf);
4b7f6baa
CM		 3643 }
3644 else if (aop == 3 && aopcde == 0)
3645 {
4b7f6baa 3646 OUTS (outf, dregs (dst0));
086134ec 3647 OUTS (outf, " = ");
4b7f6baa 3648 OUTS (outf, dregs (src0));
086134ec 3649 OUTS (outf, " -|- ");
4b7f6baa 3650 OUTS (outf, dregs (src1));
4b7f6baa 3651 amod0 (s, x, outf);
4b7f6baa
CM		 3652 }
3653 else if (aop == 1 && aopcde == 4)
3654 {
4b7f6baa 3655 OUTS (outf, dregs (dst0));
086134ec 3656 OUTS (outf, " = ");
4b7f6baa 3657 OUTS (outf, dregs (src0));
086134ec 3658 OUTS (outf, " - ");
4b7f6baa 3659 OUTS (outf, dregs (src1));
4b7f6baa 3660 amod1 (s, x, outf);
4b7f6baa
CM		 3661 }
3662 else if (aop == 0 && aopcde == 17)
3663 {
4b7f6baa 3664 OUTS (outf, dregs (dst1));
086134ec 3665 OUTS (outf, " = A1 + A0, ");
4b7f6baa 3666 OUTS (outf, dregs (dst0));
086134ec 3667 OUTS (outf, " = A1 - A0");
4b7f6baa 3668 amod1 (s, x, outf);
4b7f6baa
CM		 3669 }
3670 else if (aop == 1 && aopcde == 17)
3671 {
4b7f6baa 3672 OUTS (outf, dregs (dst1));
086134ec 3673 OUTS (outf, " = A0 + A1, ");
4b7f6baa 3674 OUTS (outf, dregs (dst0));
086134ec 3675 OUTS (outf, " = A0 - A1");
4b7f6baa 3676 amod1 (s, x, outf);
4b7f6baa
CM		 3677 }
3678 else if (aop == 0 && aopcde == 18)
3679 {
086134ec 3680 OUTS (outf, "SAA (");
4b7f6baa
CM		 3681 OUTS (outf, dregs (src0 + 1));
3682 OUTS (outf, ":");
086134ec
BS		 3683 OUTS (outf, imm5d (src0));
3684 OUTS (outf, ", ");
4b7f6baa
CM		 3685 OUTS (outf, dregs (src1 + 1));
3686 OUTS (outf, ":");
086134ec
BS		 3687 OUTS (outf, imm5d (src1));
3688 OUTS (outf, ")");
4b7f6baa 3689 aligndir (s, outf);
4b7f6baa
CM		 3690 }
3691 else if (aop == 3 && aopcde == 18)
b7d48530
NC		 3692 OUTS (outf, "DISALGNEXCPT");
3693
4b7f6baa
CM		 3694 else if (aop == 0 && aopcde == 20)
3695 {
4b7f6baa 3696 OUTS (outf, dregs (dst0));
086134ec 3697 OUTS (outf, " = BYTEOP1P (");
4b7f6baa
CM		 3698 OUTS (outf, dregs (src0 + 1));
3699 OUTS (outf, ":");
086134ec
BS		 3700 OUTS (outf, imm5d (src0));
3701 OUTS (outf, ", ");
4b7f6baa
CM		 3702 OUTS (outf, dregs (src1 + 1));
3703 OUTS (outf, ":");
086134ec 3704 OUTS (outf, imm5d (src1));
4b7f6baa
CM		 3705 OUTS (outf, ")");
3706 aligndir (s, outf);
4b7f6baa
CM		 3707 }
3708 else if (aop == 1 && aopcde == 20)
3709 {
4b7f6baa 3710 OUTS (outf, dregs (dst0));
086134ec 3711 OUTS (outf, " = BYTEOP1P (");
4b7f6baa
CM		 3712 OUTS (outf, dregs (src0 + 1));
3713 OUTS (outf, ":");
086134ec
BS		 3714 OUTS (outf, imm5d (src0));
3715 OUTS (outf, ", ");
4b7f6baa
CM		 3716 OUTS (outf, dregs (src1 + 1));
3717 OUTS (outf, ":");
086134ec
BS		 3718 OUTS (outf, imm5d (src1));
3719 OUTS (outf, ") (T");
4b7f6baa
CM		 3720 if (s == 1)
3721 OUTS (outf, ", R)");
3722 else
3723 OUTS (outf, ")");
4b7f6baa
CM		 3724 }
3725 else if (aop == 0 && aopcde == 21)
3726 {
4b7f6baa
CM		 3727 OUTS (outf, "(");
3728 OUTS (outf, dregs (dst1));
086134ec 3729 OUTS (outf, ", ");
4b7f6baa 3730 OUTS (outf, dregs (dst0));
086134ec 3731 OUTS (outf, ") = BYTEOP16P (");
4b7f6baa
CM		 3732 OUTS (outf, dregs (src0 + 1));
3733 OUTS (outf, ":");
086134ec
BS		 3734 OUTS (outf, imm5d (src0));
3735 OUTS (outf, ", ");
4b7f6baa
CM		 3736 OUTS (outf, dregs (src1 + 1));
3737 OUTS (outf, ":");
086134ec
BS		 3738 OUTS (outf, imm5d (src1));
3739 OUTS (outf, ")");
4b7f6baa 3740 aligndir (s, outf);
4b7f6baa
CM		 3741 }
3742 else if (aop == 1 && aopcde == 21)
3743 {
4b7f6baa
CM		 3744 OUTS (outf, "(");
3745 OUTS (outf, dregs (dst1));
086134ec 3746 OUTS (outf, ", ");
4b7f6baa 3747 OUTS (outf, dregs (dst0));
086134ec 3748 OUTS (outf, ") = BYTEOP16M (");
4b7f6baa
CM		 3749 OUTS (outf, dregs (src0 + 1));
3750 OUTS (outf, ":");
086134ec
BS		 3751 OUTS (outf, imm5d (src0));
3752 OUTS (outf, ", ");
4b7f6baa
CM		 3753 OUTS (outf, dregs (src1 + 1));
3754 OUTS (outf, ":");
086134ec
BS		 3755 OUTS (outf, imm5d (src1));
3756 OUTS (outf, ")");
4b7f6baa 3757 aligndir (s, outf);
4b7f6baa
CM		 3758 }
3759 else if (aop == 2 && aopcde == 7)
3760 {
4b7f6baa 3761 OUTS (outf, dregs (dst0));
086134ec 3762 OUTS (outf, " = ABS ");
4b7f6baa 3763 OUTS (outf, dregs (src0));
4b7f6baa
CM		 3764 }
3765 else if (aop == 1 && aopcde == 7)
3766 {
4b7f6baa 3767 OUTS (outf, dregs (dst0));
086134ec 3768 OUTS (outf, " = MIN (");
4b7f6baa 3769 OUTS (outf, dregs (src0));
086134ec 3770 OUTS (outf, ", ");
4b7f6baa
CM		 3771 OUTS (outf, dregs (src1));
3772 OUTS (outf, ")");
4b7f6baa
CM		 3773 }
3774 else if (aop == 0 && aopcde == 7)
3775 {
4b7f6baa 3776 OUTS (outf, dregs (dst0));
086134ec 3777 OUTS (outf, " = MAX (");
4b7f6baa 3778 OUTS (outf, dregs (src0));
086134ec 3779 OUTS (outf, ", ");
4b7f6baa
CM		 3780 OUTS (outf, dregs (src1));
3781 OUTS (outf, ")");
4b7f6baa
CM		 3782 }
3783 else if (aop == 2 && aopcde == 6)
3784 {
4b7f6baa 3785 OUTS (outf, dregs (dst0));
086134ec 3786 OUTS (outf, " = ABS ");
4b7f6baa 3787 OUTS (outf, dregs (src0));
086134ec 3788 OUTS (outf, " (V)");
4b7f6baa
CM		 3789 }
3790 else if (aop == 1 && aopcde == 6)
3791 {
4b7f6baa 3792 OUTS (outf, dregs (dst0));
086134ec 3793 OUTS (outf, " = MIN (");
4b7f6baa 3794 OUTS (outf, dregs (src0));
086134ec 3795 OUTS (outf, ", ");
4b7f6baa 3796 OUTS (outf, dregs (src1));
086134ec 3797 OUTS (outf, ") (V)");
4b7f6baa
CM		 3798 }
3799 else if (aop == 0 && aopcde == 6)
3800 {
4b7f6baa 3801 OUTS (outf, dregs (dst0));
086134ec 3802 OUTS (outf, " = MAX (");
4b7f6baa 3803 OUTS (outf, dregs (src0));
086134ec 3804 OUTS (outf, ", ");
4b7f6baa 3805 OUTS (outf, dregs (src1));
086134ec 3806 OUTS (outf, ") (V)");
4b7f6baa
CM		 3807 }
3808 else if (HL == 1 && aopcde == 1)
3809 {
4b7f6baa 3810 OUTS (outf, dregs (dst1));
086134ec 3811 OUTS (outf, " = ");
4b7f6baa 3812 OUTS (outf, dregs (src0));
086134ec 3813 OUTS (outf, " +|- ");
4b7f6baa 3814 OUTS (outf, dregs (src1));
086134ec 3815 OUTS (outf, ", ");
4b7f6baa 3816 OUTS (outf, dregs (dst0));
086134ec 3817 OUTS (outf, " = ");
4b7f6baa 3818 OUTS (outf, dregs (src0));
086134ec 3819 OUTS (outf, " -|+ ");
4b7f6baa
CM		 3820 OUTS (outf, dregs (src1));
3821 amod0amod2 (s, x, aop, outf);
4b7f6baa
CM		 3822 }
3823 else if (aop == 0 && aopcde == 4)
3824 {
4b7f6baa 3825 OUTS (outf, dregs (dst0));
086134ec 3826 OUTS (outf, " = ");
4b7f6baa 3827 OUTS (outf, dregs (src0));
086134ec 3828 OUTS (outf, " + ");
4b7f6baa 3829 OUTS (outf, dregs (src1));
4b7f6baa 3830 amod1 (s, x, outf);
4b7f6baa
CM		 3831 }
3832 else if (aop == 0 && aopcde == 0)
3833 {
4b7f6baa 3834 OUTS (outf, dregs (dst0));
086134ec 3835 OUTS (outf, " = ");
4b7f6baa 3836 OUTS (outf, dregs (src0));
086134ec 3837 OUTS (outf, " +|+ ");
4b7f6baa 3838 OUTS (outf, dregs (src1));
4b7f6baa 3839 amod0 (s, x, outf);
4b7f6baa
CM		 3840 }
3841 else if (aop == 0 && aopcde == 24)
3842 {
4b7f6baa 3843 OUTS (outf, dregs (dst0));
086134ec 3844 OUTS (outf, " = BYTEPACK (");
4b7f6baa 3845 OUTS (outf, dregs (src0));
086134ec 3846 OUTS (outf, ", ");
4b7f6baa
CM		 3847 OUTS (outf, dregs (src1));
3848 OUTS (outf, ")");
4b7f6baa
CM		 3849 }
3850 else if (aop == 1 && aopcde == 24)
3851 {
4b7f6baa
CM		 3852 OUTS (outf, "(");
3853 OUTS (outf, dregs (dst1));
086134ec 3854 OUTS (outf, ", ");
4b7f6baa
CM		 3855 OUTS (outf, dregs (dst0));
3856 OUTS (outf, ") = BYTEUNPACK ");
3857 OUTS (outf, dregs (src0 + 1));
3858 OUTS (outf, ":");
086134ec 3859 OUTS (outf, imm5d (src0));
4b7f6baa 3860 aligndir (s, outf);
4b7f6baa
CM		 3861 }
3862 else if (aopcde == 13)
3863 {
4b7f6baa
CM		 3864 OUTS (outf, "(");
3865 OUTS (outf, dregs (dst1));
086134ec 3866 OUTS (outf, ", ");
4b7f6baa
CM		 3867 OUTS (outf, dregs (dst0));
3868 OUTS (outf, ") = SEARCH ");
3869 OUTS (outf, dregs (src0));
086134ec 3870 OUTS (outf, " (");
4b7f6baa
CM		 3871 searchmod (aop, outf);
3872 OUTS (outf, ")");
4b7f6baa
CM		 3873 }
3874 else
b7d48530
NC		 3875 return 0;
3876
3877 return 4;
4b7f6baa
CM		 3878}
3879
3880static int
3881decode_dsp32shift_0 (TIword iw0, TIword iw1, disassemble_info *outf)
3882{
b7d48530
NC		 3883 /* dsp32shift
3884 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
3885 | 1 | 1 | 0 | 0 |.M.| 1 | 1 | 0 | 0 | - | - |.sopcde............|
3886 |.sop...|.HLs...|.dst0......| - | - | - |.src0......|.src1......|
3887 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
4b7f6baa
CM		 3888 int HLs = ((iw1 >> DSP32Shift_HLs_bits) & DSP32Shift_HLs_mask);
3889 int sop = ((iw1 >> DSP32Shift_sop_bits) & DSP32Shift_sop_mask);
3890 int src0 = ((iw1 >> DSP32Shift_src0_bits) & DSP32Shift_src0_mask);
3891 int src1 = ((iw1 >> DSP32Shift_src1_bits) & DSP32Shift_src1_mask);
3892 int dst0 = ((iw1 >> DSP32Shift_dst0_bits) & DSP32Shift_dst0_mask);
3893 int sopcde = ((iw0 >> (DSP32Shift_sopcde_bits - 16)) & DSP32Shift_sopcde_mask);
3894 const char *acc01 = (HLs & 1) == 0 ? "A0" : "A1";
3895
4b7f6baa
CM		 3896 if (HLs == 0 && sop == 0 && sopcde == 0)
3897 {
4b7f6baa 3898 OUTS (outf, dregs_lo (dst0));
086134ec 3899 OUTS (outf, " = ASHIFT ");
4b7f6baa
CM		 3900 OUTS (outf, dregs_lo (src1));
3901 OUTS (outf, " BY ");
3902 OUTS (outf, dregs_lo (src0));
4b7f6baa
CM		 3903 }
3904 else if (HLs == 1 && sop == 0 && sopcde == 0)
3905 {
4b7f6baa 3906 OUTS (outf, dregs_lo (dst0));
086134ec 3907 OUTS (outf, " = ASHIFT ");
4b7f6baa
CM		 3908 OUTS (outf, dregs_hi (src1));
3909 OUTS (outf, " BY ");
3910 OUTS (outf, dregs_lo (src0));
4b7f6baa
CM		 3911 }
3912 else if (HLs == 2 && sop == 0 && sopcde == 0)
3913 {
4b7f6baa 3914 OUTS (outf, dregs_hi (dst0));
086134ec 3915 OUTS (outf, " = ASHIFT ");
4b7f6baa
CM		 3916 OUTS (outf, dregs_lo (src1));
3917 OUTS (outf, " BY ");
3918 OUTS (outf, dregs_lo (src0));
4b7f6baa
CM		 3919 }
3920 else if (HLs == 3 && sop == 0 && sopcde == 0)
3921 {
4b7f6baa 3922 OUTS (outf, dregs_hi (dst0));
086134ec 3923 OUTS (outf, " = ASHIFT ");
4b7f6baa
CM		 3924 OUTS (outf, dregs_hi (src1));
3925 OUTS (outf, " BY ");
3926 OUTS (outf, dregs_lo (src0));
4b7f6baa
CM		 3927 }
3928 else if (HLs == 0 && sop == 1 && sopcde == 0)
3929 {
4b7f6baa 3930 OUTS (outf, dregs_lo (dst0));
086134ec 3931 OUTS (outf, " = ASHIFT ");
4b7f6baa
CM		 3932 OUTS (outf, dregs_lo (src1));
3933 OUTS (outf, " BY ");
3934 OUTS (outf, dregs_lo (src0));
086134ec 3935 OUTS (outf, " (S)");
4b7f6baa
CM		 3936 }
3937 else if (HLs == 1 && sop == 1 && sopcde == 0)
3938 {
4b7f6baa 3939 OUTS (outf, dregs_lo (dst0));
086134ec 3940 OUTS (outf, " = ASHIFT ");
4b7f6baa
CM		 3941 OUTS (outf, dregs_hi (src1));
3942 OUTS (outf, " BY ");
3943 OUTS (outf, dregs_lo (src0));
086134ec 3944 OUTS (outf, " (S)");
4b7f6baa
CM		 3945 }
3946 else if (HLs == 2 && sop == 1 && sopcde == 0)
3947 {
4b7f6baa 3948 OUTS (outf, dregs_hi (dst0));
086134ec 3949 OUTS (outf, " = ASHIFT ");
4b7f6baa
CM		 3950 OUTS (outf, dregs_lo (src1));
3951 OUTS (outf, " BY ");
3952 OUTS (outf, dregs_lo (src0));
086134ec 3953 OUTS (outf, " (S)");
4b7f6baa
CM		 3954 }
3955 else if (HLs == 3 && sop == 1 && sopcde == 0)
3956 {
4b7f6baa 3957 OUTS (outf, dregs_hi (dst0));
086134ec 3958 OUTS (outf, " = ASHIFT ");
4b7f6baa
CM		 3959 OUTS (outf, dregs_hi (src1));
3960 OUTS (outf, " BY ");
3961 OUTS (outf, dregs_lo (src0));
086134ec 3962 OUTS (outf, " (S)");
4b7f6baa
CM		 3963 }
3964 else if (sop == 2 && sopcde == 0)
3965 {
4b7f6baa 3966 OUTS (outf, (HLs & 2) == 0 ? dregs_lo (dst0) : dregs_hi (dst0));
086134ec 3967 OUTS (outf, " = LSHIFT ");
4b7f6baa
CM		 3968 OUTS (outf, (HLs & 1) == 0 ? dregs_lo (src1) : dregs_hi (src1));
3969 OUTS (outf, " BY ");
3970 OUTS (outf, dregs_lo (src0));
4b7f6baa
CM		 3971 }
3972 else if (sop == 0 && sopcde == 3)
3973 {
4b7f6baa 3974 OUTS (outf, acc01);
086134ec 3975 OUTS (outf, " = ASHIFT ");
4b7f6baa
CM		 3976 OUTS (outf, acc01);
3977 OUTS (outf, " BY ");
3978 OUTS (outf, dregs_lo (src0));
4b7f6baa
CM		 3979 }
3980 else if (sop == 1 && sopcde == 3)
3981 {
4b7f6baa 3982 OUTS (outf, acc01);
086134ec 3983 OUTS (outf, " = LSHIFT ");
4b7f6baa
CM		 3984 OUTS (outf, acc01);
3985 OUTS (outf, " BY ");
3986 OUTS (outf, dregs_lo (src0));
4b7f6baa
CM		 3987 }
3988 else if (sop == 2 && sopcde == 3)
3989 {
4b7f6baa 3990 OUTS (outf, acc01);
086134ec 3991 OUTS (outf, " = ROT ");
4b7f6baa
CM		 3992 OUTS (outf, acc01);
3993 OUTS (outf, " BY ");
3994 OUTS (outf, dregs_lo (src0));
4b7f6baa
CM		 3995 }
3996 else if (sop == 3 && sopcde == 3)
3997 {
4b7f6baa 3998 OUTS (outf, dregs (dst0));
086134ec 3999 OUTS (outf, " = ROT ");
4b7f6baa
CM		 4000 OUTS (outf, dregs (src1));
4001 OUTS (outf, " BY ");
4002 OUTS (outf, dregs_lo (src0));
4b7f6baa
CM		 4003 }
4004 else if (sop == 1 && sopcde == 1)
4005 {
4b7f6baa 4006 OUTS (outf, dregs (dst0));
086134ec 4007 OUTS (outf, " = ASHIFT ");
4b7f6baa
CM		 4008 OUTS (outf, dregs (src1));
4009 OUTS (outf, " BY ");
4010 OUTS (outf, dregs_lo (src0));
086134ec 4011 OUTS (outf, " (V, S)");
4b7f6baa
CM		 4012 }
4013 else if (sop == 0 && sopcde == 1)
4014 {
4b7f6baa 4015 OUTS (outf, dregs (dst0));
086134ec 4016 OUTS (outf, " = ASHIFT ");
4b7f6baa
CM		 4017 OUTS (outf, dregs (src1));
4018 OUTS (outf, " BY ");
4019 OUTS (outf, dregs_lo (src0));
086134ec 4020 OUTS (outf, " (V)");
4b7f6baa
CM		 4021 }
4022 else if (sop == 0 && sopcde == 2)
4023 {
4b7f6baa 4024 OUTS (outf, dregs (dst0));
086134ec 4025 OUTS (outf, " = ASHIFT ");
4b7f6baa
CM		 4026 OUTS (outf, dregs (src1));
4027 OUTS (outf, " BY ");
4028 OUTS (outf, dregs_lo (src0));
4b7f6baa
CM		 4029 }
4030 else if (sop == 1 && sopcde == 2)
4031 {
4b7f6baa 4032 OUTS (outf, dregs (dst0));
086134ec 4033 OUTS (outf, " = ASHIFT ");
4b7f6baa
CM		 4034 OUTS (outf, dregs (src1));
4035 OUTS (outf, " BY ");
4036 OUTS (outf, dregs_lo (src0));
086134ec 4037 OUTS (outf, " (S)");
4b7f6baa
CM		 4038 }
4039 else if (sop == 2 && sopcde == 2)
4040 {
4b7f6baa 4041 OUTS (outf, dregs (dst0));
59a82d23 4042 OUTS (outf, " = LSHIFT ");
4b7f6baa
CM		 4043 OUTS (outf, dregs (src1));
4044 OUTS (outf, " BY ");
4045 OUTS (outf, dregs_lo (src0));
4b7f6baa
CM		 4046 }
4047 else if (sop == 3 && sopcde == 2)
4048 {
4b7f6baa 4049 OUTS (outf, dregs (dst0));
086134ec 4050 OUTS (outf, " = ROT ");
4b7f6baa
CM		 4051 OUTS (outf, dregs (src1));
4052 OUTS (outf, " BY ");
4053 OUTS (outf, dregs_lo (src0));
4b7f6baa
CM		 4054 }
4055 else if (sop == 2 && sopcde == 1)
4056 {
4b7f6baa 4057 OUTS (outf, dregs (dst0));
59a82d23 4058 OUTS (outf, " = LSHIFT ");
4b7f6baa
CM		 4059 OUTS (outf, dregs (src1));
4060 OUTS (outf, " BY ");
4061 OUTS (outf, dregs_lo (src0));
086134ec 4062 OUTS (outf, " (V)");
4b7f6baa
CM		 4063 }
4064 else if (sop == 0 && sopcde == 4)
4065 {
4b7f6baa 4066 OUTS (outf, dregs (dst0));
086134ec 4067 OUTS (outf, " = PACK (");
4b7f6baa 4068 OUTS (outf, dregs_lo (src1));
086134ec 4069 OUTS (outf, ", ");
4b7f6baa
CM		 4070 OUTS (outf, dregs_lo (src0));
4071 OUTS (outf, ")");
4b7f6baa
CM		 4072 }
4073 else if (sop == 1 && sopcde == 4)
4074 {
4b7f6baa 4075 OUTS (outf, dregs (dst0));
086134ec 4076 OUTS (outf, " = PACK (");
4b7f6baa 4077 OUTS (outf, dregs_lo (src1));
086134ec 4078 OUTS (outf, ", ");
4b7f6baa
CM		 4079 OUTS (outf, dregs_hi (src0));
4080 OUTS (outf, ")");
4b7f6baa
CM		 4081 }
4082 else if (sop == 2 && sopcde == 4)
4083 {
4b7f6baa 4084 OUTS (outf, dregs (dst0));
086134ec 4085 OUTS (outf, " = PACK (");
4b7f6baa 4086 OUTS (outf, dregs_hi (src1));
086134ec 4087 OUTS (outf, ", ");
4b7f6baa
CM		 4088 OUTS (outf, dregs_lo (src0));
4089 OUTS (outf, ")");
4b7f6baa
CM		 4090 }
4091 else if (sop == 3 && sopcde == 4)
4092 {
4b7f6baa 4093 OUTS (outf, dregs (dst0));
086134ec 4094 OUTS (outf, " = PACK (");
4b7f6baa 4095 OUTS (outf, dregs_hi (src1));
086134ec 4096 OUTS (outf, ", ");
4b7f6baa
CM		 4097 OUTS (outf, dregs_hi (src0));
4098 OUTS (outf, ")");
4b7f6baa
CM		 4099 }
4100 else if (sop == 0 && sopcde == 5)
4101 {
4b7f6baa 4102 OUTS (outf, dregs_lo (dst0));
086134ec 4103 OUTS (outf, " = SIGNBITS ");
4b7f6baa 4104 OUTS (outf, dregs (src1));
4b7f6baa
CM		 4105 }
4106 else if (sop == 1 && sopcde == 5)
4107 {
4b7f6baa 4108 OUTS (outf, dregs_lo (dst0));
086134ec 4109 OUTS (outf, " = SIGNBITS ");
4b7f6baa 4110 OUTS (outf, dregs_lo (src1));
4b7f6baa
CM		 4111 }
4112 else if (sop == 2 && sopcde == 5)
4113 {
4b7f6baa 4114 OUTS (outf, dregs_lo (dst0));
086134ec 4115 OUTS (outf, " = SIGNBITS ");
4b7f6baa 4116 OUTS (outf, dregs_hi (src1));
4b7f6baa
CM		 4117 }
4118 else if (sop == 0 && sopcde == 6)
4119 {
4b7f6baa 4120 OUTS (outf, dregs_lo (dst0));
086134ec 4121 OUTS (outf, " = SIGNBITS A0");
4b7f6baa
CM		 4122 }
4123 else if (sop == 1 && sopcde == 6)
4124 {
4b7f6baa 4125 OUTS (outf, dregs_lo (dst0));
086134ec 4126 OUTS (outf, " = SIGNBITS A1");
4b7f6baa
CM		 4127 }
4128 else if (sop == 3 && sopcde == 6)
4129 {
4b7f6baa 4130 OUTS (outf, dregs_lo (dst0));
086134ec 4131 OUTS (outf, " = ONES ");
4b7f6baa 4132 OUTS (outf, dregs (src1));
4b7f6baa
CM		 4133 }
4134 else if (sop == 0 && sopcde == 7)
4135 {
4b7f6baa 4136 OUTS (outf, dregs_lo (dst0));
086134ec 4137 OUTS (outf, " = EXPADJ (");
4b7f6baa 4138 OUTS (outf, dregs (src1));
086134ec 4139 OUTS (outf, ", ");
4b7f6baa
CM		 4140 OUTS (outf, dregs_lo (src0));
4141 OUTS (outf, ")");
4b7f6baa
CM		 4142 }
4143 else if (sop == 1 && sopcde == 7)
4144 {
4b7f6baa 4145 OUTS (outf, dregs_lo (dst0));
086134ec 4146 OUTS (outf, " = EXPADJ (");
4b7f6baa 4147 OUTS (outf, dregs (src1));
086134ec 4148 OUTS (outf, ", ");
4b7f6baa
CM		 4149 OUTS (outf, dregs_lo (src0));
4150 OUTS (outf, ") (V)");
4b7f6baa
CM		 4151 }
4152 else if (sop == 2 && sopcde == 7)
4153 {
4b7f6baa 4154 OUTS (outf, dregs_lo (dst0));
086134ec 4155 OUTS (outf, " = EXPADJ (");
4b7f6baa 4156 OUTS (outf, dregs_lo (src1));
086134ec 4157 OUTS (outf, ", ");
4b7f6baa
CM		 4158 OUTS (outf, dregs_lo (src0));
4159 OUTS (outf, ")");
4b7f6baa
CM		 4160 }
4161 else if (sop == 3 && sopcde == 7)
4162 {
4b7f6baa 4163 OUTS (outf, dregs_lo (dst0));
086134ec 4164 OUTS (outf, " = EXPADJ (");
4b7f6baa 4165 OUTS (outf, dregs_hi (src1));
086134ec 4166 OUTS (outf, ", ");
4b7f6baa
CM		 4167 OUTS (outf, dregs_lo (src0));
4168 OUTS (outf, ")");
4b7f6baa
CM		 4169 }
4170 else if (sop == 0 && sopcde == 8)
4171 {
4b7f6baa
CM		 4172 OUTS (outf, "BITMUX (");
4173 OUTS (outf, dregs (src0));
086134ec 4174 OUTS (outf, ", ");
4b7f6baa 4175 OUTS (outf, dregs (src1));
086134ec 4176 OUTS (outf, ", A0) (ASR)");
4b7f6baa
CM		 4177 }
4178 else if (sop == 1 && sopcde == 8)
4179 {
4b7f6baa
CM		 4180 OUTS (outf, "BITMUX (");
4181 OUTS (outf, dregs (src0));
086134ec 4182 OUTS (outf, ", ");
4b7f6baa 4183 OUTS (outf, dregs (src1));
086134ec 4184 OUTS (outf, ", A0) (ASL)");
4b7f6baa
CM		 4185 }
4186 else if (sop == 0 && sopcde == 9)
4187 {
4b7f6baa 4188 OUTS (outf, dregs_lo (dst0));
086134ec 4189 OUTS (outf, " = VIT_MAX (");
4b7f6baa
CM		 4190 OUTS (outf, dregs (src1));
4191 OUTS (outf, ") (ASL)");
4b7f6baa
CM		 4192 }
4193 else if (sop == 1 && sopcde == 9)
4194 {
4b7f6baa 4195 OUTS (outf, dregs_lo (dst0));
086134ec 4196 OUTS (outf, " = VIT_MAX (");
4b7f6baa
CM		 4197 OUTS (outf, dregs (src1));
4198 OUTS (outf, ") (ASR)");
4b7f6baa
CM		 4199 }
4200 else if (sop == 2 && sopcde == 9)
4201 {
4b7f6baa 4202 OUTS (outf, dregs (dst0));
086134ec 4203 OUTS (outf, " = VIT_MAX (");
4b7f6baa 4204 OUTS (outf, dregs (src1));
086134ec 4205 OUTS (outf, ", ");
4b7f6baa 4206 OUTS (outf, dregs (src0));
086134ec 4207 OUTS (outf, ") (ASL)");
4b7f6baa
CM		 4208 }
4209 else if (sop == 3 && sopcde == 9)
4210 {
4b7f6baa 4211 OUTS (outf, dregs (dst0));
086134ec 4212 OUTS (outf, " = VIT_MAX (");
4b7f6baa 4213 OUTS (outf, dregs (src1));
086134ec 4214 OUTS (outf, ", ");
4b7f6baa 4215 OUTS (outf, dregs (src0));
086134ec 4216 OUTS (outf, ") (ASR)");
4b7f6baa
CM		 4217 }
4218 else if (sop == 0 && sopcde == 10)
4219 {
4b7f6baa 4220 OUTS (outf, dregs (dst0));
086134ec 4221 OUTS (outf, " = EXTRACT (");
4b7f6baa 4222 OUTS (outf, dregs (src1));
086134ec 4223 OUTS (outf, ", ");
4b7f6baa
CM		 4224 OUTS (outf, dregs_lo (src0));
4225 OUTS (outf, ") (Z)");
4b7f6baa
CM		 4226 }
4227 else if (sop == 1 && sopcde == 10)
4228 {
4b7f6baa 4229 OUTS (outf, dregs (dst0));
086134ec 4230 OUTS (outf, " = EXTRACT (");
4b7f6baa 4231 OUTS (outf, dregs (src1));
086134ec 4232 OUTS (outf, ", ");
4b7f6baa 4233 OUTS (outf, dregs_lo (src0));
086134ec 4234 OUTS (outf, ") (X)");
4b7f6baa
CM		 4235 }
4236 else if (sop == 2 && sopcde == 10)
4237 {
4b7f6baa 4238 OUTS (outf, dregs (dst0));
086134ec 4239 OUTS (outf, " = DEPOSIT (");
4b7f6baa 4240 OUTS (outf, dregs (src1));
086134ec 4241 OUTS (outf, ", ");
4b7f6baa
CM		 4242 OUTS (outf, dregs (src0));
4243 OUTS (outf, ")");
4b7f6baa
CM		 4244 }
4245 else if (sop == 3 && sopcde == 10)
4246 {
4b7f6baa 4247 OUTS (outf, dregs (dst0));
086134ec 4248 OUTS (outf, " = DEPOSIT (");
4b7f6baa 4249 OUTS (outf, dregs (src1));
086134ec 4250 OUTS (outf, ", ");
4b7f6baa 4251 OUTS (outf, dregs (src0));
086134ec 4252 OUTS (outf, ") (X)");
4b7f6baa
CM		 4253 }
4254 else if (sop == 0 && sopcde == 11)
4255 {
4b7f6baa 4256 OUTS (outf, dregs_lo (dst0));
086134ec 4257 OUTS (outf, " = CC = BXORSHIFT (A0, ");
4b7f6baa
CM		 4258 OUTS (outf, dregs (src0));
4259 OUTS (outf, ")");
4b7f6baa
CM		 4260 }
4261 else if (sop == 1 && sopcde == 11)
4262 {
4b7f6baa 4263 OUTS (outf, dregs_lo (dst0));
086134ec 4264 OUTS (outf, " = CC = BXOR (A0, ");
4b7f6baa
CM		 4265 OUTS (outf, dregs (src0));
4266 OUTS (outf, ")");
4b7f6baa
CM		 4267 }
4268 else if (sop == 0 && sopcde == 12)
086134ec 4269 OUTS (outf, "A0 = BXORSHIFT (A0, A1, CC)");
b7d48530 4270
4b7f6baa
CM		 4271 else if (sop == 1 && sopcde == 12)
4272 {
4b7f6baa 4273 OUTS (outf, dregs_lo (dst0));
086134ec 4274 OUTS (outf, " = CC = BXOR (A0, A1, CC)");
4b7f6baa
CM		 4275 }
4276 else if (sop == 0 && sopcde == 13)
4277 {
4b7f6baa 4278 OUTS (outf, dregs (dst0));
086134ec 4279 OUTS (outf, " = ALIGN8 (");
4b7f6baa 4280 OUTS (outf, dregs (src1));
086134ec 4281 OUTS (outf, ", ");
4b7f6baa
CM		 4282 OUTS (outf, dregs (src0));
4283 OUTS (outf, ")");
4b7f6baa
CM		 4284 }
4285 else if (sop == 1 && sopcde == 13)
4286 {
4b7f6baa 4287 OUTS (outf, dregs (dst0));
086134ec 4288 OUTS (outf, " = ALIGN16 (");
4b7f6baa 4289 OUTS (outf, dregs (src1));
086134ec 4290 OUTS (outf, ", ");
4b7f6baa
CM		 4291 OUTS (outf, dregs (src0));
4292 OUTS (outf, ")");
4b7f6baa
CM		 4293 }
4294 else if (sop == 2 && sopcde == 13)
4295 {
4b7f6baa 4296 OUTS (outf, dregs (dst0));
086134ec 4297 OUTS (outf, " = ALIGN24 (");
4b7f6baa 4298 OUTS (outf, dregs (src1));
086134ec 4299 OUTS (outf, ", ");
4b7f6baa
CM		 4300 OUTS (outf, dregs (src0));
4301 OUTS (outf, ")");
4b7f6baa
CM		 4302 }
4303 else
b7d48530
NC		 4304 return 0;
4305
4306 return 4;
4b7f6baa
CM		 4307}
4308
4309static int
4310decode_dsp32shiftimm_0 (TIword iw0, TIword iw1, disassemble_info *outf)
4311{
b7d48530
NC		 4312 /* dsp32shiftimm
4313 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
4314 | 1 | 1 | 0 | 0 |.M.| 1 | 1 | 0 | 1 | - | - |.sopcde............|
4315 |.sop...|.HLs...|.dst0......|.immag.................|.src1......|
4316 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
4317 int src1 = ((iw1 >> DSP32ShiftImm_src1_bits) & DSP32ShiftImm_src1_mask);
4318 int sop = ((iw1 >> DSP32ShiftImm_sop_bits) & DSP32ShiftImm_sop_mask);
4319 int bit8 = ((iw1 >> 8) & 0x1);
4320 int immag = ((iw1 >> DSP32ShiftImm_immag_bits) & DSP32ShiftImm_immag_mask);
4b7f6baa 4321 int newimmag = (-(iw1 >> DSP32ShiftImm_immag_bits) & DSP32ShiftImm_immag_mask);
b7d48530
NC		 4322 int dst0 = ((iw1 >> DSP32ShiftImm_dst0_bits) & DSP32ShiftImm_dst0_mask);
4323 int sopcde = ((iw0 >> (DSP32ShiftImm_sopcde_bits - 16)) & DSP32ShiftImm_sopcde_mask);
4324 int HLs = ((iw1 >> DSP32ShiftImm_HLs_bits) & DSP32ShiftImm_HLs_mask);
4b7f6baa 4325
331f1cbe 4326 if (sop == 0 && sopcde == 0)
4b7f6baa 4327 {
331f1cbe
BS		 4328 OUTS (outf, (HLs & 2) ? dregs_hi (dst0) : dregs_lo (dst0));
4329 OUTS (outf, " = ");
4330 OUTS (outf, (HLs & 1) ? dregs_hi (src1) : dregs_lo (src1));
4331 OUTS (outf, " >>> ");
4b7f6baa 4332 OUTS (outf, uimm4 (newimmag));
4b7f6baa 4333 }
331f1cbe 4334 else if (sop == 1 && sopcde == 0 && bit8 == 0)
4b7f6baa 4335 {
331f1cbe
BS		 4336 OUTS (outf, (HLs & 2) ? dregs_hi (dst0) : dregs_lo (dst0));
4337 OUTS (outf, " = ");
4338 OUTS (outf, (HLs & 1) ? dregs_hi (src1) : dregs_lo (src1));
4339 OUTS (outf, " << ");
4b7f6baa 4340 OUTS (outf, uimm4 (immag));
331f1cbe 4341 OUTS (outf, " (S)");
4b7f6baa 4342 }
331f1cbe 4343 else if (sop == 1 && sopcde == 0 && bit8 == 1)
4b7f6baa 4344 {
331f1cbe
BS		 4345 OUTS (outf, (HLs & 2) ? dregs_hi (dst0) : dregs_lo (dst0));
4346 OUTS (outf, " = ");
4347 OUTS (outf, (HLs & 1) ? dregs_hi (src1) : dregs_lo (src1));
4348 OUTS (outf, " >>> ");
4b7f6baa 4349 OUTS (outf, uimm4 (newimmag));
331f1cbe 4350 OUTS (outf, " (S)");
4b7f6baa 4351 }
331f1cbe 4352 else if (sop == 2 && sopcde == 0 && bit8 == 0)
4b7f6baa 4353 {
331f1cbe
BS		 4354 OUTS (outf, (HLs & 2) ? dregs_hi (dst0) : dregs_lo (dst0));
4355 OUTS (outf, " = ");
4356 OUTS (outf, (HLs & 1) ? dregs_hi (src1) : dregs_lo (src1));
4357 OUTS (outf, " << ");
4b7f6baa 4358 OUTS (outf, uimm4 (immag));
4b7f6baa 4359 }
331f1cbe 4360 else if (sop == 2 && sopcde == 0 && bit8 == 1)
4b7f6baa 4361 {
331f1cbe
BS		 4362 OUTS (outf, (HLs & 2) ? dregs_hi (dst0) : dregs_lo (dst0));
4363 OUTS (outf, " = ");
4364 OUTS (outf, (HLs & 1) ? dregs_hi (src1) : dregs_lo (src1));
4365 OUTS (outf, " >> ");
4b7f6baa 4366 OUTS (outf, uimm4 (newimmag));
4b7f6baa 4367 }
4b7f6baa
CM		 4368 else if (sop == 2 && sopcde == 3 && HLs == 1)
4369 {
086134ec 4370 OUTS (outf, "A1 = ROT A1 BY ");
4b7f6baa 4371 OUTS (outf, imm6 (immag));
4b7f6baa
CM		 4372 }
4373 else if (sop == 0 && sopcde == 3 && HLs == 0 && bit8 == 0)
4374 {
086134ec 4375 OUTS (outf, "A0 = A0 << ");
4b7f6baa 4376 OUTS (outf, uimm5 (immag));
4b7f6baa
CM		 4377 }
4378 else if (sop == 0 && sopcde == 3 && HLs == 0 && bit8 == 1)
4379 {
086134ec 4380 OUTS (outf, "A0 = A0 >>> ");
4b7f6baa 4381 OUTS (outf, uimm5 (newimmag));
4b7f6baa
CM		 4382 }
4383 else if (sop == 0 && sopcde == 3 && HLs == 1 && bit8 == 0)
4384 {
086134ec 4385 OUTS (outf, "A1 = A1 << ");
4b7f6baa 4386 OUTS (outf, uimm5 (immag));
4b7f6baa
CM		 4387 }
4388 else if (sop == 0 && sopcde == 3 && HLs == 1 && bit8 == 1)
4389 {
086134ec 4390 OUTS (outf, "A1 = A1 >>> ");
4b7f6baa 4391 OUTS (outf, uimm5 (newimmag));
4b7f6baa
CM		 4392 }
4393 else if (sop == 1 && sopcde == 3 && HLs == 0)
4394 {
086134ec 4395 OUTS (outf, "A0 = A0 >> ");
4b7f6baa 4396 OUTS (outf, uimm5 (newimmag));
4b7f6baa
CM		 4397 }
4398 else if (sop == 1 && sopcde == 3 && HLs == 1)
4399 {
086134ec 4400 OUTS (outf, "A1 = A1 >> ");
4b7f6baa 4401 OUTS (outf, uimm5 (newimmag));
4b7f6baa
CM		 4402 }
4403 else if (sop == 2 && sopcde == 3 && HLs == 0)
4404 {
086134ec 4405 OUTS (outf, "A0 = ROT A0 BY ");
4b7f6baa 4406 OUTS (outf, imm6 (immag));
4b7f6baa
CM		 4407 }
4408 else if (sop == 1 && sopcde == 1 && bit8 == 0)
4409 {
4b7f6baa 4410 OUTS (outf, dregs (dst0));
086134ec 4411 OUTS (outf, " = ");
4b7f6baa 4412 OUTS (outf, dregs (src1));
086134ec 4413 OUTS (outf, " << ");
4b7f6baa
CM		 4414 OUTS (outf, uimm5 (immag));
4415 OUTS (outf, " (V, S)");
4b7f6baa
CM		 4416 }
4417 else if (sop == 1 && sopcde == 1 && bit8 == 1)
4418 {
4b7f6baa 4419 OUTS (outf, dregs (dst0));
086134ec 4420 OUTS (outf, " = ");
4b7f6baa 4421 OUTS (outf, dregs (src1));
086134ec 4422 OUTS (outf, " >>> ");
4b7f6baa 4423 OUTS (outf, imm5 (-immag));
0b7691fd 4424 OUTS (outf, " (V, S)");
4b7f6baa
CM		 4425 }
4426 else if (sop == 2 && sopcde == 1 && bit8 == 1)
4427 {
4b7f6baa 4428 OUTS (outf, dregs (dst0));
086134ec 4429 OUTS (outf, " = ");
4b7f6baa
CM		 4430 OUTS (outf, dregs (src1));
4431 OUTS (outf, " >> ");
4432 OUTS (outf, uimm5 (newimmag));
4433 OUTS (outf, " (V)");
4b7f6baa
CM		 4434 }
4435 else if (sop == 2 && sopcde == 1 && bit8 == 0)
4436 {
4b7f6baa 4437 OUTS (outf, dregs (dst0));
086134ec 4438 OUTS (outf, " = ");
4b7f6baa 4439 OUTS (outf, dregs (src1));
086134ec 4440 OUTS (outf, " << ");
4b7f6baa
CM		 4441 OUTS (outf, imm5 (immag));
4442 OUTS (outf, " (V)");
4b7f6baa
CM		 4443 }
4444 else if (sop == 0 && sopcde == 1)
4445 {
4b7f6baa 4446 OUTS (outf, dregs (dst0));
086134ec 4447 OUTS (outf, " = ");
4b7f6baa 4448 OUTS (outf, dregs (src1));
086134ec 4449 OUTS (outf, " >>> ");
4b7f6baa
CM		 4450 OUTS (outf, uimm5 (newimmag));
4451 OUTS (outf, " (V)");
4b7f6baa
CM		 4452 }
4453 else if (sop == 1 && sopcde == 2)
4454 {
4b7f6baa 4455 OUTS (outf, dregs (dst0));
086134ec 4456 OUTS (outf, " = ");
4b7f6baa 4457 OUTS (outf, dregs (src1));
086134ec 4458 OUTS (outf, " << ");
4b7f6baa 4459 OUTS (outf, uimm5 (immag));
086134ec 4460 OUTS (outf, " (S)");
4b7f6baa
CM		 4461 }
4462 else if (sop == 2 && sopcde == 2 && bit8 == 1)
4463 {
4b7f6baa 4464 OUTS (outf, dregs (dst0));
086134ec 4465 OUTS (outf, " = ");
4b7f6baa 4466 OUTS (outf, dregs (src1));
086134ec 4467 OUTS (outf, " >> ");
4b7f6baa 4468 OUTS (outf, uimm5 (newimmag));
4b7f6baa
CM		 4469 }
4470 else if (sop == 2 && sopcde == 2 && bit8 == 0)
4471 {
4b7f6baa 4472 OUTS (outf, dregs (dst0));
086134ec 4473 OUTS (outf, " = ");
4b7f6baa 4474 OUTS (outf, dregs (src1));
086134ec 4475 OUTS (outf, " << ");
4b7f6baa 4476 OUTS (outf, uimm5 (immag));
4b7f6baa
CM		 4477 }
4478 else if (sop == 3 && sopcde == 2)
4479 {
4b7f6baa 4480 OUTS (outf, dregs (dst0));
086134ec 4481 OUTS (outf, " = ROT ");
4b7f6baa
CM		 4482 OUTS (outf, dregs (src1));
4483 OUTS (outf, " BY ");
4484 OUTS (outf, imm6 (immag));
4b7f6baa
CM		 4485 }
4486 else if (sop == 0 && sopcde == 2)
4487 {
4b7f6baa 4488 OUTS (outf, dregs (dst0));
086134ec 4489 OUTS (outf, " = ");
4b7f6baa 4490 OUTS (outf, dregs (src1));
086134ec 4491 OUTS (outf, " >>> ");
4b7f6baa 4492 OUTS (outf, uimm5 (newimmag));
4b7f6baa
CM		 4493 }
4494 else
b7d48530
NC		 4495 return 0;
4496
4497 return 4;
4b7f6baa
CM		 4498}
4499
4500static int
4501decode_pseudoDEBUG_0 (TIword iw0, disassemble_info *outf)
4502{
703ec4e8 4503 struct private *priv = outf->private_data;
b7d48530
NC		 4504 /* pseudoDEBUG
4505 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
4506 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 |.fn....|.grp.......|.reg.......|
4507 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
4b7f6baa
CM		 4508 int fn = ((iw0 >> PseudoDbg_fn_bits) & PseudoDbg_fn_mask);
4509 int grp = ((iw0 >> PseudoDbg_grp_bits) & PseudoDbg_grp_mask);
4510 int reg = ((iw0 >> PseudoDbg_reg_bits) & PseudoDbg_reg_mask);
4511
703ec4e8 4512 if (priv->parallel)
219b747a
MF		 4513 return 0;
4514
4b7f6baa 4515 if (reg == 0 && fn == 3)
b7d48530
NC		 4516 OUTS (outf, "DBG A0");
4517
4b7f6baa 4518 else if (reg == 1 && fn == 3)
b7d48530
NC		 4519 OUTS (outf, "DBG A1");
4520
4b7f6baa 4521 else if (reg == 3 && fn == 3)
b7d48530
NC		 4522 OUTS (outf, "ABORT");
4523
4b7f6baa 4524 else if (reg == 4 && fn == 3)
b7d48530
NC		 4525 OUTS (outf, "HLT");
4526
4b7f6baa 4527 else if (reg == 5 && fn == 3)
b7d48530
NC		 4528 OUTS (outf, "DBGHALT");
4529
4b7f6baa
CM		 4530 else if (reg == 6 && fn == 3)
4531 {
086134ec 4532 OUTS (outf, "DBGCMPLX (");
4b7f6baa
CM		 4533 OUTS (outf, dregs (grp));
4534 OUTS (outf, ")");
4b7f6baa
CM		 4535 }
4536 else if (reg == 7 && fn == 3)
b7d48530
NC		 4537 OUTS (outf, "DBG");
4538
4b7f6baa
CM		 4539 else if (grp == 0 && fn == 2)
4540 {
73a63ccf 4541 OUTS (outf, "OUTC ");
4b7f6baa 4542 OUTS (outf, dregs (reg));
4b7f6baa
CM		 4543 }
4544 else if (fn == 0)
4545 {
a01eda85 4546 OUTS (outf, "DBG ");
4b7f6baa 4547 OUTS (outf, allregs (reg, grp));
4b7f6baa
CM		 4548 }
4549 else if (fn == 1)
4550 {
9805c0a5 4551 OUTS (outf, "PRNT ");
4b7f6baa 4552 OUTS (outf, allregs (reg, grp));
4b7f6baa
CM		 4553 }
4554 else
b7d48530
NC		 4555 return 0;
4556
4557 return 2;
4b7f6baa
CM		 4558}
4559
73a63ccf
MF		 4560static int
4561decode_pseudoOChar_0 (TIword iw0, disassemble_info *outf)
4562{
703ec4e8 4563 struct private *priv = outf->private_data;
73a63ccf
MF		 4564 /* psedoOChar
4565 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
4566 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 1 |.ch............................|
4567 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
4568 int ch = ((iw0 >> PseudoChr_ch_bits) & PseudoChr_ch_mask);
4569
703ec4e8 4570 if (priv->parallel)
219b747a
MF		 4571 return 0;
4572
73a63ccf
MF		 4573 OUTS (outf, "OUTC ");
4574 OUTS (outf, uimm8 (ch));
4575
4576 return 2;
4577}
4578
4b7f6baa
CM		 4579static int
4580decode_pseudodbg_assert_0 (TIword iw0, TIword iw1, disassemble_info *outf)
4581{
703ec4e8 4582 struct private *priv = outf->private_data;
b7d48530
NC		 4583 /* pseudodbg_assert
4584 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
66a6900a 4585 | 1 | 1 | 1 | 1 | 0 | - | - | - | dbgop |.grp.......|.regtest...|
b7d48530
NC		 4586 |.expected......................................................|
4587 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
4b7f6baa 4588 int expected = ((iw1 >> PseudoDbg_Assert_expected_bits) & PseudoDbg_Assert_expected_mask);
b7d48530 4589 int dbgop = ((iw0 >> (PseudoDbg_Assert_dbgop_bits - 16)) & PseudoDbg_Assert_dbgop_mask);
66a6900a 4590 int grp = ((iw0 >> (PseudoDbg_Assert_grp_bits - 16)) & PseudoDbg_Assert_grp_mask);
b7d48530 4591 int regtest = ((iw0 >> (PseudoDbg_Assert_regtest_bits - 16)) & PseudoDbg_Assert_regtest_mask);
4b7f6baa 4592
703ec4e8 4593 if (priv->parallel)
219b747a
MF		 4594 return 0;
4595
4b7f6baa
CM		 4596 if (dbgop == 0)
4597 {
086134ec 4598 OUTS (outf, "DBGA (");
66a6900a 4599 OUTS (outf, regs_lo (regtest, grp));
086134ec 4600 OUTS (outf, ", ");
4b7f6baa
CM		 4601 OUTS (outf, uimm16 (expected));
4602 OUTS (outf, ")");
4b7f6baa
CM		 4603 }
4604 else if (dbgop == 1)
4605 {
086134ec 4606 OUTS (outf, "DBGA (");
66a6900a 4607 OUTS (outf, regs_hi (regtest, grp));
086134ec 4608 OUTS (outf, ", ");
4b7f6baa
CM		 4609 OUTS (outf, uimm16 (expected));
4610 OUTS (outf, ")");
4b7f6baa
CM		 4611 }
4612 else if (dbgop == 2)
4613 {
086134ec 4614 OUTS (outf, "DBGAL (");
66a6900a 4615 OUTS (outf, allregs (regtest, grp));
086134ec 4616 OUTS (outf, ", ");
4b7f6baa
CM		 4617 OUTS (outf, uimm16 (expected));
4618 OUTS (outf, ")");
4b7f6baa
CM		 4619 }
4620 else if (dbgop == 3)
4621 {
086134ec 4622 OUTS (outf, "DBGAH (");
66a6900a 4623 OUTS (outf, allregs (regtest, grp));
086134ec 4624 OUTS (outf, ", ");
4b7f6baa
CM		 4625 OUTS (outf, uimm16 (expected));
4626 OUTS (outf, ")");
4b7f6baa
CM		 4627 }
4628 else
b7d48530
NC		 4629 return 0;
4630 return 4;
4b7f6baa
CM		 4631}
4632
ba329817
MF		 4633static int
4634ifetch (bfd_vma pc, disassemble_info *outf, TIword *iw)
4635{
4636 bfd_byte buf[2];
4637 int status;
4638
ed2c4879 4639 status = (*outf->read_memory_func) (pc, buf, 2, outf);
ba329817
MF		 4640 if (status != 0)
4641 {
4642 (*outf->memory_error_func) (status, pc, outf);
4643 return -1;
4644 }
4645
4646 *iw = bfd_getl16 (buf);
4647 return 0;
4648}
4649
ad15c38e 4650static int
4b7f6baa
CM		 4651_print_insn_bfin (bfd_vma pc, disassemble_info *outf)
4652{
703ec4e8 4653 struct private *priv = outf->private_data;
4b7f6baa
CM		 4654 TIword iw0;
4655 TIword iw1;
b7d48530
NC		 4656 int rv = 0;
4657
ed2c4879
MF		 4658 /* The PC must be 16-bit aligned. */
4659 if (pc & 1)
4660 {
4661 OUTS (outf, "ILLEGAL (UNALIGNED)");
4662 /* For people dumping data, just re-align the return value. */
4663 return 1;
4664 }
4665
ba329817
MF		 4666 if (ifetch (pc, outf, &iw0))
4667 return -1;
a4e600b2 4668 priv->iw0 = iw0;
4b7f6baa 4669
bdc4de1b 4670 if (((iw0 & 0xc000) == 0xc000) && ((iw0 & 0xff00) != 0xf800))
ba329817
MF		 4671 {
4672 /* 32-bit insn. */
4673 if (ifetch (pc + 2, outf, &iw1))
4674 return -1;
4675 }
4676 else
4677 /* 16-bit insn. */
4678 iw1 = 0;
4b7f6baa
CM		 4679
4680 if ((iw0 & 0xf7ff) == 0xc003 && iw1 == 0x1800)
4681 {
703ec4e8 4682 if (priv->parallel)
219b747a 4683 {
602427c4
MF		 4684 OUTS (outf, "ILLEGAL");
4685 return 0;
219b747a 4686 }
086134ec 4687 OUTS (outf, "MNOP");
4b7f6baa
CM		 4688 return 4;
4689 }
4690 else if ((iw0 & 0xff00) == 0x0000)
b7d48530 4691 rv = decode_ProgCtrl_0 (iw0, outf);
4b7f6baa 4692 else if ((iw0 & 0xffc0) == 0x0240)
b7d48530 4693 rv = decode_CaCTRL_0 (iw0, outf);
4b7f6baa 4694 else if ((iw0 & 0xff80) == 0x0100)
b7d48530 4695 rv = decode_PushPopReg_0 (iw0, outf);
4b7f6baa 4696 else if ((iw0 & 0xfe00) == 0x0400)
b7d48530 4697 rv = decode_PushPopMultiple_0 (iw0, outf);
4b7f6baa 4698 else if ((iw0 & 0xfe00) == 0x0600)
b7d48530 4699 rv = decode_ccMV_0 (iw0, outf);
4b7f6baa 4700 else if ((iw0 & 0xf800) == 0x0800)
b7d48530 4701 rv = decode_CCflag_0 (iw0, outf);
4b7f6baa 4702 else if ((iw0 & 0xffe0) == 0x0200)
b7d48530 4703 rv = decode_CC2dreg_0 (iw0, outf);
4b7f6baa 4704 else if ((iw0 & 0xff00) == 0x0300)
b7d48530 4705 rv = decode_CC2stat_0 (iw0, outf);
4b7f6baa 4706 else if ((iw0 & 0xf000) == 0x1000)
b7d48530 4707 rv = decode_BRCC_0 (iw0, pc, outf);
4b7f6baa 4708 else if ((iw0 & 0xf000) == 0x2000)
b7d48530 4709 rv = decode_UJUMP_0 (iw0, pc, outf);
4b7f6baa 4710 else if ((iw0 & 0xf000) == 0x3000)
b7d48530 4711 rv = decode_REGMV_0 (iw0, outf);
4b7f6baa 4712 else if ((iw0 & 0xfc00) == 0x4000)
b7d48530 4713 rv = decode_ALU2op_0 (iw0, outf);
4b7f6baa 4714 else if ((iw0 & 0xfe00) == 0x4400)
b7d48530 4715 rv = decode_PTR2op_0 (iw0, outf);
4b7f6baa 4716 else if ((iw0 & 0xf800) == 0x4800)
b7d48530 4717 rv = decode_LOGI2op_0 (iw0, outf);
4b7f6baa 4718 else if ((iw0 & 0xf000) == 0x5000)
b7d48530 4719 rv = decode_COMP3op_0 (iw0, outf);
4b7f6baa 4720 else if ((iw0 & 0xf800) == 0x6000)
b7d48530 4721 rv = decode_COMPI2opD_0 (iw0, outf);
4b7f6baa 4722 else if ((iw0 & 0xf800) == 0x6800)
b7d48530 4723 rv = decode_COMPI2opP_0 (iw0, outf);
4b7f6baa 4724 else if ((iw0 & 0xf000) == 0x8000)
b7d48530 4725 rv = decode_LDSTpmod_0 (iw0, outf);
4b7f6baa 4726 else if ((iw0 & 0xff60) == 0x9e60)
b7d48530 4727 rv = decode_dagMODim_0 (iw0, outf);
4b7f6baa 4728 else if ((iw0 & 0xfff0) == 0x9f60)
b7d48530 4729 rv = decode_dagMODik_0 (iw0, outf);
4b7f6baa 4730 else if ((iw0 & 0xfc00) == 0x9c00)
b7d48530 4731 rv = decode_dspLDST_0 (iw0, outf);
4b7f6baa 4732 else if ((iw0 & 0xf000) == 0x9000)
b7d48530 4733 rv = decode_LDST_0 (iw0, outf);
4b7f6baa 4734 else if ((iw0 & 0xfc00) == 0xb800)
b7d48530 4735 rv = decode_LDSTiiFP_0 (iw0, outf);
4b7f6baa 4736 else if ((iw0 & 0xe000) == 0xA000)
b7d48530 4737 rv = decode_LDSTii_0 (iw0, outf);
4b7f6baa 4738 else if ((iw0 & 0xff80) == 0xe080 && (iw1 & 0x0C00) == 0x0000)
b7d48530 4739 rv = decode_LoopSetup_0 (iw0, iw1, pc, outf);
4b7f6baa 4740 else if ((iw0 & 0xff00) == 0xe100 && (iw1 & 0x0000) == 0x0000)
b7d48530 4741 rv = decode_LDIMMhalf_0 (iw0, iw1, outf);
4b7f6baa 4742 else if ((iw0 & 0xfe00) == 0xe200 && (iw1 & 0x0000) == 0x0000)
b7d48530 4743 rv = decode_CALLa_0 (iw0, iw1, pc, outf);
4b7f6baa 4744 else if ((iw0 & 0xfc00) == 0xe400 && (iw1 & 0x0000) == 0x0000)
b7d48530 4745 rv = decode_LDSTidxI_0 (iw0, iw1, outf);
4b7f6baa 4746 else if ((iw0 & 0xfffe) == 0xe800 && (iw1 & 0x0000) == 0x0000)
b7d48530 4747 rv = decode_linkage_0 (iw0, iw1, outf);
4b7f6baa 4748 else if ((iw0 & 0xf600) == 0xc000 && (iw1 & 0x0000) == 0x0000)
b7d48530 4749 rv = decode_dsp32mac_0 (iw0, iw1, outf);
4b7f6baa 4750 else if ((iw0 & 0xf600) == 0xc200 && (iw1 & 0x0000) == 0x0000)
b7d48530 4751 rv = decode_dsp32mult_0 (iw0, iw1, outf);
4b7f6baa 4752 else if ((iw0 & 0xf7c0) == 0xc400 && (iw1 & 0x0000) == 0x0000)
b7d48530 4753 rv = decode_dsp32alu_0 (iw0, iw1, outf);
4b7f6baa 4754 else if ((iw0 & 0xf780) == 0xc600 && (iw1 & 0x01c0) == 0x0000)
b7d48530 4755 rv = decode_dsp32shift_0 (iw0, iw1, outf);
4b7f6baa 4756 else if ((iw0 & 0xf780) == 0xc680 && (iw1 & 0x0000) == 0x0000)
b7d48530 4757 rv = decode_dsp32shiftimm_0 (iw0, iw1, outf);
4b7f6baa 4758 else if ((iw0 & 0xff00) == 0xf800)
b7d48530 4759 rv = decode_pseudoDEBUG_0 (iw0, outf);
4b7f6baa 4760 else if ((iw0 & 0xFF00) == 0xF900)
73a63ccf 4761 rv = decode_pseudoOChar_0 (iw0, outf);
66a6900a 4762 else if ((iw0 & 0xFF00) == 0xf000 && (iw1 & 0x0000) == 0x0000)
b7d48530 4763 rv = decode_pseudodbg_assert_0 (iw0, iw1, outf);
4b7f6baa 4764
219b747a
MF		 4765 if (rv == 0)
4766 OUTS (outf, "ILLEGAL");
4767
b7d48530 4768 return rv;
4b7f6baa
CM		 4769}
4770
4b7f6baa
CM		 4771int
4772print_insn_bfin (bfd_vma pc, disassemble_info *outf)
4773{
703ec4e8 4774 struct private priv;
ba329817 4775 int count;
471e4e36 4776
60ac5798
MF		 4777 priv.parallel = FALSE;
4778 priv.comment = FALSE;
703ec4e8
MF		 4779 outf->private_data = &priv;
4780
ba329817
MF		 4781 count = _print_insn_bfin (pc, outf);
4782 if (count == -1)
4783 return -1;
471e4e36 4784
4b7f6baa 4785 /* Proper display of multiple issue instructions. */
471e4e36 4786
a4e600b2
MF		 4787 if (count == 4 && (priv.iw0 & 0xc000) == 0xc000 && (priv.iw0 & BIT_MULTI_INS)
4788 && ((priv.iw0 & 0xe800) != 0xe800 /* Not Linkage. */ ))
4b7f6baa 4789 {
60ac5798 4790 bfd_boolean legal = TRUE;
219b747a
MF		 4791 int len;
4792
60ac5798 4793 priv.parallel = TRUE;
f5caf9f4 4794 OUTS (outf, " || ");
219b747a 4795 len = _print_insn_bfin (pc + 4, outf);
ba329817
MF		 4796 if (len == -1)
4797 return -1;
f5caf9f4 4798 OUTS (outf, " || ");
219b747a 4799 if (len != 2)
60ac5798 4800 legal = FALSE;
219b747a 4801 len = _print_insn_bfin (pc + 6, outf);
ba329817
MF		 4802 if (len == -1)
4803 return -1;
219b747a 4804 if (len != 2)
60ac5798 4805 legal = FALSE;
219b747a
MF		 4806
4807 if (legal)
4808 count = 8;
4809 else
4810 {
f5caf9f4 4811 OUTS (outf, ";\t\t/* ILLEGAL PARALLEL INSTRUCTION */");
60ac5798 4812 priv.comment = TRUE;
219b747a
MF		 4813 count = 0;
4814 }
4b7f6baa 4815 }
219b747a 4816
703ec4e8 4817 if (!priv.comment)
f5caf9f4 4818 OUTS (outf, ";");
086134ec 4819
219b747a
MF		 4820 if (count == 0)
4821 return 2;
4822
4b7f6baa
CM		 4823 return count;
4824}
GDB Binutils - Deliverables
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