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gas: make .lcomm to accept an optional aligmnet in eBPF targets
[deliverable/binutils-gdb.git] / opcodes / bpf-desc.c
CommitLineData
79472b45
JM		 1/* DO NOT EDIT! -*- buffer-read-only: t -*- vi:set ro: */
2/* CPU data for bpf.
3
4THIS FILE IS MACHINE GENERATED WITH CGEN.
5
6Copyright (C) 1996-2019 Free Software Foundation, Inc.
7
8This file is part of the GNU Binutils and/or GDB, the GNU debugger.
9
10 This file is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 3, or (at your option)
13 any later version.
14
15 It is distributed in the hope that it will be useful, but WITHOUT
16 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
17 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
18 License for more details.
19
20 You should have received a copy of the GNU General Public License along
21 with this program; if not, write to the Free Software Foundation, Inc.,
22 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
23
24*/
25
26#include "sysdep.h"
27#include <stdio.h>
28#include <stdarg.h>
29#include "ansidecl.h"
30#include "bfd.h"
31#include "symcat.h"
32#include "bpf-desc.h"
33#include "bpf-opc.h"
34#include "opintl.h"
35#include "libiberty.h"
36#include "xregex.h"
37
38/* Attributes. */
39
40static const CGEN_ATTR_ENTRY bool_attr[] =
41{
42 { "#f", 0 },
43 { "#t", 1 },
44 { 0, 0 }
45};
46
47static const CGEN_ATTR_ENTRY MACH_attr[] ATTRIBUTE_UNUSED =
48{
49 { "base", MACH_BASE },
50 { "bpf", MACH_BPF },
51 { "max", MACH_MAX },
52 { 0, 0 }
53};
54
55static const CGEN_ATTR_ENTRY ISA_attr[] ATTRIBUTE_UNUSED =
56{
57 { "ebpfle", ISA_EBPFLE },
58 { "ebpfbe", ISA_EBPFBE },
59 { "max", ISA_MAX },
60 { 0, 0 }
61};
62
63const CGEN_ATTR_TABLE bpf_cgen_ifield_attr_table[] =
64{
65 { "MACH", & MACH_attr[0], & MACH_attr[0] },
66 { "ISA", & ISA_attr[0], & ISA_attr[0] },
67 { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
68 { "PCREL-ADDR", &bool_attr[0], &bool_attr[0] },
69 { "ABS-ADDR", &bool_attr[0], &bool_attr[0] },
70 { "RESERVED", &bool_attr[0], &bool_attr[0] },
71 { "SIGN-OPT", &bool_attr[0], &bool_attr[0] },
72 { "SIGNED", &bool_attr[0], &bool_attr[0] },
73 { 0, 0, 0 }
74};
75
76const CGEN_ATTR_TABLE bpf_cgen_hardware_attr_table[] =
77{
78 { "MACH", & MACH_attr[0], & MACH_attr[0] },
79 { "ISA", & ISA_attr[0], & ISA_attr[0] },
80 { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
81 { "CACHE-ADDR", &bool_attr[0], &bool_attr[0] },
82 { "PC", &bool_attr[0], &bool_attr[0] },
83 { "PROFILE", &bool_attr[0], &bool_attr[0] },
84 { 0, 0, 0 }
85};
86
87const CGEN_ATTR_TABLE bpf_cgen_operand_attr_table[] =
88{
89 { "MACH", & MACH_attr[0], & MACH_attr[0] },
90 { "ISA", & ISA_attr[0], & ISA_attr[0] },
91 { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
92 { "PCREL-ADDR", &bool_attr[0], &bool_attr[0] },
93 { "ABS-ADDR", &bool_attr[0], &bool_attr[0] },
94 { "SIGN-OPT", &bool_attr[0], &bool_attr[0] },
95 { "SIGNED", &bool_attr[0], &bool_attr[0] },
96 { "NEGATIVE", &bool_attr[0], &bool_attr[0] },
97 { "RELAX", &bool_attr[0], &bool_attr[0] },
98 { "SEM-ONLY", &bool_attr[0], &bool_attr[0] },
99 { 0, 0, 0 }
100};
101
102const CGEN_ATTR_TABLE bpf_cgen_insn_attr_table[] =
103{
104 { "MACH", & MACH_attr[0], & MACH_attr[0] },
105 { "ISA", & ISA_attr[0], & ISA_attr[0] },
106 { "ALIAS", &bool_attr[0], &bool_attr[0] },
107 { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
108 { "UNCOND-CTI", &bool_attr[0], &bool_attr[0] },
109 { "COND-CTI", &bool_attr[0], &bool_attr[0] },
110 { "SKIP-CTI", &bool_attr[0], &bool_attr[0] },
111 { "DELAY-SLOT", &bool_attr[0], &bool_attr[0] },
112 { "RELAXABLE", &bool_attr[0], &bool_attr[0] },
113 { "RELAXED", &bool_attr[0], &bool_attr[0] },
114 { "NO-DIS", &bool_attr[0], &bool_attr[0] },
115 { "PBB", &bool_attr[0], &bool_attr[0] },
116 { 0, 0, 0 }
117};
118
119/* Instruction set variants. */
120
121static const CGEN_ISA bpf_cgen_isa_table[] = {
122 { "ebpfle", 64, 8, 64, 128 },
123 { "ebpfbe", 64, 8, 64, 128 },
124 { 0, 0, 0, 0, 0 }
125};
126
127/* Machine variants. */
128
129static const CGEN_MACH bpf_cgen_mach_table[] = {
130 { "bpf", "bpf", MACH_BPF, 0 },
131 { 0, 0, 0, 0 }
132};
133
134static CGEN_KEYWORD_ENTRY bpf_cgen_opval_h_gpr_entries[] =
135{
136 { "%a", 0, {0, {{{0, 0}}}}, 0, 0 },
137 { "%r1", 1, {0, {{{0, 0}}}}, 0, 0 },
138 { "%r2", 2, {0, {{{0, 0}}}}, 0, 0 },
139 { "%r3", 3, {0, {{{0, 0}}}}, 0, 0 },
140 { "%r4", 4, {0, {{{0, 0}}}}, 0, 0 },
141 { "%r5", 5, {0, {{{0, 0}}}}, 0, 0 },
142 { "%ctx", 6, {0, {{{0, 0}}}}, 0, 0 },
143 { "%r7", 7, {0, {{{0, 0}}}}, 0, 0 },
144 { "%r8", 8, {0, {{{0, 0}}}}, 0, 0 },
145 { "%r9", 9, {0, {{{0, 0}}}}, 0, 0 },
146 { "%fp", 10, {0, {{{0, 0}}}}, 0, 0 },
147 { "%r0", 0, {0, {{{0, 0}}}}, 0, 0 },
148 { "%r6", 6, {0, {{{0, 0}}}}, 0, 0 },
149 { "%r10", 10, {0, {{{0, 0}}}}, 0, 0 }
150};
151
152CGEN_KEYWORD bpf_cgen_opval_h_gpr =
153{
154 & bpf_cgen_opval_h_gpr_entries[0],
155 14,
156 0, 0, 0, 0, ""
157};
158
159
160/* The hardware table. */
161
162#define A(a) (1 << CGEN_HW_##a)
163
164const CGEN_HW_ENTRY bpf_cgen_hw_table[] =
165{
166 { "h-memory", HW_H_MEMORY, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
167 { "h-sint", HW_H_SINT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
168 { "h-uint", HW_H_UINT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
169 { "h-addr", HW_H_ADDR, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
170 { "h-iaddr", HW_H_IADDR, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
171 { "h-gpr", HW_H_GPR, CGEN_ASM_KEYWORD, (PTR) & bpf_cgen_opval_h_gpr, { 0, { { { (1<<MACH_BPF), 0 } }, { { 1, "\xc0" } } } } },
172 { "h-pc", HW_H_PC, CGEN_ASM_NONE, 0, { 0|A(PROFILE)|A(PC), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } },
173 { "h-sint64", HW_H_SINT64, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
174 { 0, 0, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }
175};
176
177#undef A
178
179
180/* The instruction field table. */
181
182#define A(a) (1 << CGEN_IFLD_##a)
183
184const CGEN_IFLD bpf_cgen_ifld_table[] =
185{
186 { BPF_F_NIL, "f-nil", 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
187 { BPF_F_ANYOF, "f-anyof", 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
188 { BPF_F_OP_CODE, "f-op-code", 0, 8, 7, 4, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
189 { BPF_F_OP_SRC, "f-op-src", 0, 8, 3, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
190 { BPF_F_OP_CLASS, "f-op-class", 0, 8, 2, 3, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
191 { BPF_F_OP_MODE, "f-op-mode", 0, 8, 7, 3, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
192 { BPF_F_OP_SIZE, "f-op-size", 0, 8, 4, 2, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
193 { BPF_F_DSTLE, "f-dstle", 8, 8, 3, 4, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } },
194 { BPF_F_SRCLE, "f-srcle", 8, 8, 7, 4, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } },
195 { BPF_F_DSTBE, "f-dstbe", 8, 8, 7, 4, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } },
196 { BPF_F_SRCBE, "f-srcbe", 8, 8, 3, 4, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } },
197 { BPF_F_REGS, "f-regs", 8, 8, 7, 8, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
198 { BPF_F_OFFSET16, "f-offset16", 16, 16, 15, 16, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
199 { BPF_F_IMM32, "f-imm32", 32, 32, 31, 32, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
200 { BPF_F_IMM64_A, "f-imm64-a", 32, 32, 31, 32, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
201 { BPF_F_IMM64_B, "f-imm64-b", 64, 32, 31, 32, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
202 { BPF_F_IMM64_C, "f-imm64-c", 96, 32, 31, 32, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
203 { BPF_F_IMM64, "f-imm64", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
204 { 0, 0, 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }
205};
206
207#undef A
208
209
210
211/* multi ifield declarations */
212
213const CGEN_MAYBE_MULTI_IFLD BPF_F_IMM64_MULTI_IFIELD [];
214
215
216/* multi ifield definitions */
217
218const CGEN_MAYBE_MULTI_IFLD BPF_F_IMM64_MULTI_IFIELD [] =
219{
220 { 0, { (const PTR) &bpf_cgen_ifld_table[BPF_F_IMM64_A] } },
221 { 0, { (const PTR) &bpf_cgen_ifld_table[BPF_F_IMM64_B] } },
222 { 0, { (const PTR) &bpf_cgen_ifld_table[BPF_F_IMM64_C] } },
223 { 0, { (const PTR) 0 } }
224};
225
226/* The operand table. */
227
228#define A(a) (1 << CGEN_OPERAND_##a)
229#define OPERAND(op) BPF_OPERAND_##op
230
231const CGEN_OPERAND bpf_cgen_operand_table[] =
232{
233/* pc: program counter */
234 { "pc", BPF_OPERAND_PC, HW_H_PC, 0, 0,
235 { 0, { (const PTR) &bpf_cgen_ifld_table[BPF_F_NIL] } },
236 { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
237/* dstle: destination register */
238 { "dstle", BPF_OPERAND_DSTLE, HW_H_GPR, 3, 4,
239 { 0, { (const PTR) &bpf_cgen_ifld_table[BPF_F_DSTLE] } },
240 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } },
241/* srcle: source register */
242 { "srcle", BPF_OPERAND_SRCLE, HW_H_GPR, 7, 4,
243 { 0, { (const PTR) &bpf_cgen_ifld_table[BPF_F_SRCLE] } },
244 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } },
245/* dstbe: destination register */
246 { "dstbe", BPF_OPERAND_DSTBE, HW_H_GPR, 7, 4,
247 { 0, { (const PTR) &bpf_cgen_ifld_table[BPF_F_DSTBE] } },
248 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } },
249/* srcbe: source register */
250 { "srcbe", BPF_OPERAND_SRCBE, HW_H_GPR, 3, 4,
251 { 0, { (const PTR) &bpf_cgen_ifld_table[BPF_F_SRCBE] } },
252 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } },
253/* disp16: 16-bit PC-relative address */
254 { "disp16", BPF_OPERAND_DISP16, HW_H_SINT, 15, 16,
255 { 0, { (const PTR) &bpf_cgen_ifld_table[BPF_F_OFFSET16] } },
256 { 0|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
257/* disp32: 32-bit PC-relative address */
258 { "disp32", BPF_OPERAND_DISP32, HW_H_SINT, 31, 32,
259 { 0, { (const PTR) &bpf_cgen_ifld_table[BPF_F_IMM32] } },
260 { 0|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
261/* imm32: 32-bit immediate */
262 { "imm32", BPF_OPERAND_IMM32, HW_H_SINT, 31, 32,
263 { 0, { (const PTR) &bpf_cgen_ifld_table[BPF_F_IMM32] } },
264 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
265/* offset16: 16-bit offset */
266 { "offset16", BPF_OPERAND_OFFSET16, HW_H_SINT, 15, 16,
267 { 0, { (const PTR) &bpf_cgen_ifld_table[BPF_F_OFFSET16] } },
268 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
269/* imm64: 64-bit immediate */
270 { "imm64", BPF_OPERAND_IMM64, HW_H_SINT64, 31, 96,
271 { 3, { (const PTR) &BPF_F_IMM64_MULTI_IFIELD[0] } },
272 { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
273/* endsize: endianness size immediate: 16, 32 or 64 */
274 { "endsize", BPF_OPERAND_ENDSIZE, HW_H_UINT, 31, 32,
275 { 0, { (const PTR) &bpf_cgen_ifld_table[BPF_F_IMM32] } },
276 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
277/* sentinel */
278 { 0, 0, 0, 0, 0,
279 { 0, { (const PTR) 0 } },
280 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }
281};
282
283#undef A
284
285
286/* The instruction table. */
287
288#define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field))
289#define A(a) (1 << CGEN_INSN_##a)
290
291static const CGEN_IBASE bpf_cgen_insn_table[MAX_INSNS] =
292{
293 /* Special null first entry.
294 A `num' value of zero is thus invalid.
295 Also, the special `invalid' insn resides here. */
296 { 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } },
297/* add $dstle,$imm32 */
298 {
299 BPF_INSN_ADDILE, "addile", "add", 64,
300 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
301 },
302/* add $dstle,$srcle */
303 {
304 BPF_INSN_ADDRLE, "addrle", "add", 64,
305 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
306 },
307/* add32 $dstle,$imm32 */
308 {
309 BPF_INSN_ADD32ILE, "add32ile", "add32", 64,
310 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
311 },
312/* add32 $dstle,$srcle */
313 {
314 BPF_INSN_ADD32RLE, "add32rle", "add32", 64,
315 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
316 },
317/* sub $dstle,$imm32 */
318 {
319 BPF_INSN_SUBILE, "subile", "sub", 64,
320 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
321 },
322/* sub $dstle,$srcle */
323 {
324 BPF_INSN_SUBRLE, "subrle", "sub", 64,
325 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
326 },
327/* sub32 $dstle,$imm32 */
328 {
329 BPF_INSN_SUB32ILE, "sub32ile", "sub32", 64,
330 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
331 },
332/* sub32 $dstle,$srcle */
333 {
334 BPF_INSN_SUB32RLE, "sub32rle", "sub32", 64,
335 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
336 },
337/* mul $dstle,$imm32 */
338 {
339 BPF_INSN_MULILE, "mulile", "mul", 64,
340 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
341 },
342/* mul $dstle,$srcle */
343 {
344 BPF_INSN_MULRLE, "mulrle", "mul", 64,
345 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
346 },
347/* mul32 $dstle,$imm32 */
348 {
349 BPF_INSN_MUL32ILE, "mul32ile", "mul32", 64,
350 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
351 },
352/* mul32 $dstle,$srcle */
353 {
354 BPF_INSN_MUL32RLE, "mul32rle", "mul32", 64,
355 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
356 },
357/* div $dstle,$imm32 */
358 {
359 BPF_INSN_DIVILE, "divile", "div", 64,
360 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
361 },
362/* div $dstle,$srcle */
363 {
364 BPF_INSN_DIVRLE, "divrle", "div", 64,
365 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
366 },
367/* div32 $dstle,$imm32 */
368 {
369 BPF_INSN_DIV32ILE, "div32ile", "div32", 64,
370 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
371 },
372/* div32 $dstle,$srcle */
373 {
374 BPF_INSN_DIV32RLE, "div32rle", "div32", 64,
375 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
376 },
377/* or $dstle,$imm32 */
378 {
379 BPF_INSN_ORILE, "orile", "or", 64,
380 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
381 },
382/* or $dstle,$srcle */
383 {
384 BPF_INSN_ORRLE, "orrle", "or", 64,
385 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
386 },
387/* or32 $dstle,$imm32 */
388 {
389 BPF_INSN_OR32ILE, "or32ile", "or32", 64,
390 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
391 },
392/* or32 $dstle,$srcle */
393 {
394 BPF_INSN_OR32RLE, "or32rle", "or32", 64,
395 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
396 },
397/* and $dstle,$imm32 */
398 {
399 BPF_INSN_ANDILE, "andile", "and", 64,
400 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
401 },
402/* and $dstle,$srcle */
403 {
404 BPF_INSN_ANDRLE, "andrle", "and", 64,
405 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
406 },
407/* and32 $dstle,$imm32 */
408 {
409 BPF_INSN_AND32ILE, "and32ile", "and32", 64,
410 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
411 },
412/* and32 $dstle,$srcle */
413 {
414 BPF_INSN_AND32RLE, "and32rle", "and32", 64,
415 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
416 },
417/* lsh $dstle,$imm32 */
418 {
419 BPF_INSN_LSHILE, "lshile", "lsh", 64,
420 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
421 },
422/* lsh $dstle,$srcle */
423 {
424 BPF_INSN_LSHRLE, "lshrle", "lsh", 64,
425 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
426 },
427/* lsh32 $dstle,$imm32 */
428 {
429 BPF_INSN_LSH32ILE, "lsh32ile", "lsh32", 64,
430 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
431 },
432/* lsh32 $dstle,$srcle */
433 {
434 BPF_INSN_LSH32RLE, "lsh32rle", "lsh32", 64,
435 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
436 },
437/* rsh $dstle,$imm32 */
438 {
439 BPF_INSN_RSHILE, "rshile", "rsh", 64,
440 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
441 },
442/* rsh $dstle,$srcle */
443 {
444 BPF_INSN_RSHRLE, "rshrle", "rsh", 64,
445 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
446 },
447/* rsh32 $dstle,$imm32 */
448 {
449 BPF_INSN_RSH32ILE, "rsh32ile", "rsh32", 64,
450 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
451 },
452/* rsh32 $dstle,$srcle */
453 {
454 BPF_INSN_RSH32RLE, "rsh32rle", "rsh32", 64,
455 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
456 },
457/* mod $dstle,$imm32 */
458 {
459 BPF_INSN_MODILE, "modile", "mod", 64,
460 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
461 },
462/* mod $dstle,$srcle */
463 {
464 BPF_INSN_MODRLE, "modrle", "mod", 64,
465 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
466 },
467/* mod32 $dstle,$imm32 */
468 {
469 BPF_INSN_MOD32ILE, "mod32ile", "mod32", 64,
470 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
471 },
472/* mod32 $dstle,$srcle */
473 {
474 BPF_INSN_MOD32RLE, "mod32rle", "mod32", 64,
475 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
476 },
477/* xor $dstle,$imm32 */
478 {
479 BPF_INSN_XORILE, "xorile", "xor", 64,
480 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
481 },
482/* xor $dstle,$srcle */
483 {
484 BPF_INSN_XORRLE, "xorrle", "xor", 64,
485 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
486 },
487/* xor32 $dstle,$imm32 */
488 {
489 BPF_INSN_XOR32ILE, "xor32ile", "xor32", 64,
490 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
491 },
492/* xor32 $dstle,$srcle */
493 {
494 BPF_INSN_XOR32RLE, "xor32rle", "xor32", 64,
495 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
496 },
497/* mov $dstle,$imm32 */
498 {
499 BPF_INSN_MOVILE, "movile", "mov", 64,
500 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
501 },
502/* mov $dstle,$srcle */
503 {
504 BPF_INSN_MOVRLE, "movrle", "mov", 64,
505 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
506 },
507/* mov32 $dstle,$imm32 */
508 {
509 BPF_INSN_MOV32ILE, "mov32ile", "mov32", 64,
510 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
511 },
512/* mov32 $dstle,$srcle */
513 {
514 BPF_INSN_MOV32RLE, "mov32rle", "mov32", 64,
515 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
516 },
517/* arsh $dstle,$imm32 */
518 {
519 BPF_INSN_ARSHILE, "arshile", "arsh", 64,
520 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
521 },
522/* arsh $dstle,$srcle */
523 {
524 BPF_INSN_ARSHRLE, "arshrle", "arsh", 64,
525 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
526 },
527/* arsh32 $dstle,$imm32 */
528 {
529 BPF_INSN_ARSH32ILE, "arsh32ile", "arsh32", 64,
530 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
531 },
532/* arsh32 $dstle,$srcle */
533 {
534 BPF_INSN_ARSH32RLE, "arsh32rle", "arsh32", 64,
535 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
536 },
537/* neg $dstle */
538 {
539 BPF_INSN_NEGLE, "negle", "neg", 64,
540 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
541 },
542/* neg32 $dstle */
543 {
544 BPF_INSN_NEG32LE, "neg32le", "neg32", 64,
545 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
546 },
547/* add $dstbe,$imm32 */
548 {
549 BPF_INSN_ADDIBE, "addibe", "add", 64,
550 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
551 },
552/* add $dstbe,$srcbe */
553 {
554 BPF_INSN_ADDRBE, "addrbe", "add", 64,
555 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
556 },
557/* add32 $dstbe,$imm32 */
558 {
559 BPF_INSN_ADD32IBE, "add32ibe", "add32", 64,
560 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
561 },
562/* add32 $dstbe,$srcbe */
563 {
564 BPF_INSN_ADD32RBE, "add32rbe", "add32", 64,
565 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
566 },
567/* sub $dstbe,$imm32 */
568 {
569 BPF_INSN_SUBIBE, "subibe", "sub", 64,
570 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
571 },
572/* sub $dstbe,$srcbe */
573 {
574 BPF_INSN_SUBRBE, "subrbe", "sub", 64,
575 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
576 },
577/* sub32 $dstbe,$imm32 */
578 {
579 BPF_INSN_SUB32IBE, "sub32ibe", "sub32", 64,
580 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
581 },
582/* sub32 $dstbe,$srcbe */
583 {
584 BPF_INSN_SUB32RBE, "sub32rbe", "sub32", 64,
585 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
586 },
587/* mul $dstbe,$imm32 */
588 {
589 BPF_INSN_MULIBE, "mulibe", "mul", 64,
590 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
591 },
592/* mul $dstbe,$srcbe */
593 {
594 BPF_INSN_MULRBE, "mulrbe", "mul", 64,
595 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
596 },
597/* mul32 $dstbe,$imm32 */
598 {
599 BPF_INSN_MUL32IBE, "mul32ibe", "mul32", 64,
600 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
601 },
602/* mul32 $dstbe,$srcbe */
603 {
604 BPF_INSN_MUL32RBE, "mul32rbe", "mul32", 64,
605 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
606 },
607/* div $dstbe,$imm32 */
608 {
609 BPF_INSN_DIVIBE, "divibe", "div", 64,
610 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
611 },
612/* div $dstbe,$srcbe */
613 {
614 BPF_INSN_DIVRBE, "divrbe", "div", 64,
615 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
616 },
617/* div32 $dstbe,$imm32 */
618 {
619 BPF_INSN_DIV32IBE, "div32ibe", "div32", 64,
620 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
621 },
622/* div32 $dstbe,$srcbe */
623 {
624 BPF_INSN_DIV32RBE, "div32rbe", "div32", 64,
625 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
626 },
627/* or $dstbe,$imm32 */
628 {
629 BPF_INSN_ORIBE, "oribe", "or", 64,
630 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
631 },
632/* or $dstbe,$srcbe */
633 {
634 BPF_INSN_ORRBE, "orrbe", "or", 64,
635 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
636 },
637/* or32 $dstbe,$imm32 */
638 {
639 BPF_INSN_OR32IBE, "or32ibe", "or32", 64,
640 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
641 },
642/* or32 $dstbe,$srcbe */
643 {
644 BPF_INSN_OR32RBE, "or32rbe", "or32", 64,
645 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
646 },
647/* and $dstbe,$imm32 */
648 {
649 BPF_INSN_ANDIBE, "andibe", "and", 64,
650 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
651 },
652/* and $dstbe,$srcbe */
653 {
654 BPF_INSN_ANDRBE, "andrbe", "and", 64,
655 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
656 },
657/* and32 $dstbe,$imm32 */
658 {
659 BPF_INSN_AND32IBE, "and32ibe", "and32", 64,
660 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
661 },
662/* and32 $dstbe,$srcbe */
663 {
664 BPF_INSN_AND32RBE, "and32rbe", "and32", 64,
665 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
666 },
667/* lsh $dstbe,$imm32 */
668 {
669 BPF_INSN_LSHIBE, "lshibe", "lsh", 64,
670 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
671 },
672/* lsh $dstbe,$srcbe */
673 {
674 BPF_INSN_LSHRBE, "lshrbe", "lsh", 64,
675 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
676 },
677/* lsh32 $dstbe,$imm32 */
678 {
679 BPF_INSN_LSH32IBE, "lsh32ibe", "lsh32", 64,
680 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
681 },
682/* lsh32 $dstbe,$srcbe */
683 {
684 BPF_INSN_LSH32RBE, "lsh32rbe", "lsh32", 64,
685 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
686 },
687/* rsh $dstbe,$imm32 */
688 {
689 BPF_INSN_RSHIBE, "rshibe", "rsh", 64,
690 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
691 },
692/* rsh $dstbe,$srcbe */
693 {
694 BPF_INSN_RSHRBE, "rshrbe", "rsh", 64,
695 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
696 },
697/* rsh32 $dstbe,$imm32 */
698 {
699 BPF_INSN_RSH32IBE, "rsh32ibe", "rsh32", 64,
700 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
701 },
702/* rsh32 $dstbe,$srcbe */
703 {
704 BPF_INSN_RSH32RBE, "rsh32rbe", "rsh32", 64,
705 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
706 },
707/* mod $dstbe,$imm32 */
708 {
709 BPF_INSN_MODIBE, "modibe", "mod", 64,
710 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
711 },
712/* mod $dstbe,$srcbe */
713 {
714 BPF_INSN_MODRBE, "modrbe", "mod", 64,
715 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
716 },
717/* mod32 $dstbe,$imm32 */
718 {
719 BPF_INSN_MOD32IBE, "mod32ibe", "mod32", 64,
720 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
721 },
722/* mod32 $dstbe,$srcbe */
723 {
724 BPF_INSN_MOD32RBE, "mod32rbe", "mod32", 64,
725 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
726 },
727/* xor $dstbe,$imm32 */
728 {
729 BPF_INSN_XORIBE, "xoribe", "xor", 64,
730 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
731 },
732/* xor $dstbe,$srcbe */
733 {
734 BPF_INSN_XORRBE, "xorrbe", "xor", 64,
735 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
736 },
737/* xor32 $dstbe,$imm32 */
738 {
739 BPF_INSN_XOR32IBE, "xor32ibe", "xor32", 64,
740 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
741 },
742/* xor32 $dstbe,$srcbe */
743 {
744 BPF_INSN_XOR32RBE, "xor32rbe", "xor32", 64,
745 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
746 },
747/* mov $dstbe,$imm32 */
748 {
749 BPF_INSN_MOVIBE, "movibe", "mov", 64,
750 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
751 },
752/* mov $dstbe,$srcbe */
753 {
754 BPF_INSN_MOVRBE, "movrbe", "mov", 64,
755 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
756 },
757/* mov32 $dstbe,$imm32 */
758 {
759 BPF_INSN_MOV32IBE, "mov32ibe", "mov32", 64,
760 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
761 },
762/* mov32 $dstbe,$srcbe */
763 {
764 BPF_INSN_MOV32RBE, "mov32rbe", "mov32", 64,
765 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
766 },
767/* arsh $dstbe,$imm32 */
768 {
769 BPF_INSN_ARSHIBE, "arshibe", "arsh", 64,
770 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
771 },
772/* arsh $dstbe,$srcbe */
773 {
774 BPF_INSN_ARSHRBE, "arshrbe", "arsh", 64,
775 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
776 },
777/* arsh32 $dstbe,$imm32 */
778 {
779 BPF_INSN_ARSH32IBE, "arsh32ibe", "arsh32", 64,
780 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
781 },
782/* arsh32 $dstbe,$srcbe */
783 {
784 BPF_INSN_ARSH32RBE, "arsh32rbe", "arsh32", 64,
785 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
786 },
787/* neg $dstbe */
788 {
789 BPF_INSN_NEGBE, "negbe", "neg", 64,
790 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
791 },
792/* neg32 $dstbe */
793 {
794 BPF_INSN_NEG32BE, "neg32be", "neg32", 64,
795 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
796 },
797/* endle $dstle,$endsize */
798 {
799 BPF_INSN_ENDLELE, "endlele", "endle", 64,
800 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
801 },
802/* endbe $dstle,$endsize */
803 {
804 BPF_INSN_ENDBELE, "endbele", "endbe", 64,
805 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
806 },
807/* endle $dstbe,$endsize */
808 {
809 BPF_INSN_ENDLEBE, "endlebe", "endle", 64,
810 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
811 },
812/* endbe $dstbe,$endsize */
813 {
814 BPF_INSN_ENDBEBE, "endbebe", "endbe", 64,
815 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
816 },
817/* lddw $dstle,$imm64 */
818 {
819 BPF_INSN_LDDWLE, "lddwle", "lddw", 128,
820 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
821 },
822/* lddw $dstbe,$imm64 */
823 {
824 BPF_INSN_LDDWBE, "lddwbe", "lddw", 128,
825 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
826 },
3719fd55 827/* ldabsw $imm32 */
79472b45 828 {
3719fd55
JM		 829 BPF_INSN_LDABSW, "ldabsw", "ldabsw", 64,
830 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }
79472b45 831 },
3719fd55 832/* ldabsh $imm32 */
79472b45 833 {
3719fd55
JM		 834 BPF_INSN_LDABSH, "ldabsh", "ldabsh", 64,
835 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }
79472b45 836 },
3719fd55 837/* ldabsb $imm32 */
79472b45 838 {
3719fd55
JM		 839 BPF_INSN_LDABSB, "ldabsb", "ldabsb", 64,
840 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }
79472b45 841 },
3719fd55 842/* ldabsdw $imm32 */
79472b45 843 {
3719fd55
JM		 844 BPF_INSN_LDABSDW, "ldabsdw", "ldabsdw", 64,
845 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }
79472b45 846 },
92434a14 847/* ldindw $srcle,$imm32 */
79472b45
JM		 848 {
849 BPF_INSN_LDINDWLE, "ldindwle", "ldindw", 64,
850 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
851 },
92434a14 852/* ldindh $srcle,$imm32 */
79472b45
JM		 853 {
854 BPF_INSN_LDINDHLE, "ldindhle", "ldindh", 64,
855 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
856 },
92434a14 857/* ldindb $srcle,$imm32 */
79472b45
JM		 858 {
859 BPF_INSN_LDINDBLE, "ldindble", "ldindb", 64,
860 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
861 },
92434a14 862/* ldinddw $srcle,$imm32 */
79472b45
JM		 863 {
864 BPF_INSN_LDINDDWLE, "ldinddwle", "ldinddw", 64,
865 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
866 },
92434a14 867/* ldindw $srcbe,$imm32 */
79472b45
JM		 868 {
869 BPF_INSN_LDINDWBE, "ldindwbe", "ldindw", 64,
870 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
871 },
92434a14 872/* ldindh $srcbe,$imm32 */
79472b45
JM		 873 {
874 BPF_INSN_LDINDHBE, "ldindhbe", "ldindh", 64,
875 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
876 },
92434a14 877/* ldindb $srcbe,$imm32 */
79472b45
JM		 878 {
879 BPF_INSN_LDINDBBE, "ldindbbe", "ldindb", 64,
880 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
881 },
92434a14 882/* ldinddw $srcbe,$imm32 */
79472b45
JM		 883 {
884 BPF_INSN_LDINDDWBE, "ldinddwbe", "ldinddw", 64,
885 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
886 },
887/* ldxw $dstle,[$srcle+$offset16] */
888 {
889 BPF_INSN_LDXWLE, "ldxwle", "ldxw", 64,
890 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
891 },
892/* ldxh $dstle,[$srcle+$offset16] */
893 {
894 BPF_INSN_LDXHLE, "ldxhle", "ldxh", 64,
895 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
896 },
897/* ldxb $dstle,[$srcle+$offset16] */
898 {
899 BPF_INSN_LDXBLE, "ldxble", "ldxb", 64,
900 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
901 },
902/* ldxdw $dstle,[$srcle+$offset16] */
903 {
904 BPF_INSN_LDXDWLE, "ldxdwle", "ldxdw", 64,
905 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
906 },
907/* stxw [$dstle+$offset16],$srcle */
908 {
909 BPF_INSN_STXWLE, "stxwle", "stxw", 64,
910 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
911 },
912/* stxh [$dstle+$offset16],$srcle */
913 {
914 BPF_INSN_STXHLE, "stxhle", "stxh", 64,
915 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
916 },
917/* stxb [$dstle+$offset16],$srcle */
918 {
919 BPF_INSN_STXBLE, "stxble", "stxb", 64,
920 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
921 },
922/* stxdw [$dstle+$offset16],$srcle */
923 {
924 BPF_INSN_STXDWLE, "stxdwle", "stxdw", 64,
925 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
926 },
927/* ldxw $dstbe,[$srcbe+$offset16] */
928 {
929 BPF_INSN_LDXWBE, "ldxwbe", "ldxw", 64,
930 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
931 },
932/* ldxh $dstbe,[$srcbe+$offset16] */
933 {
934 BPF_INSN_LDXHBE, "ldxhbe", "ldxh", 64,
935 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
936 },
937/* ldxb $dstbe,[$srcbe+$offset16] */
938 {
939 BPF_INSN_LDXBBE, "ldxbbe", "ldxb", 64,
940 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
941 },
942/* ldxdw $dstbe,[$srcbe+$offset16] */
943 {
944 BPF_INSN_LDXDWBE, "ldxdwbe", "ldxdw", 64,
945 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
946 },
947/* stxw [$dstbe+$offset16],$srcbe */
948 {
949 BPF_INSN_STXWBE, "stxwbe", "stxw", 64,
950 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
951 },
952/* stxh [$dstbe+$offset16],$srcbe */
953 {
954 BPF_INSN_STXHBE, "stxhbe", "stxh", 64,
955 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
956 },
957/* stxb [$dstbe+$offset16],$srcbe */
958 {
959 BPF_INSN_STXBBE, "stxbbe", "stxb", 64,
960 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
961 },
962/* stxdw [$dstbe+$offset16],$srcbe */
963 {
964 BPF_INSN_STXDWBE, "stxdwbe", "stxdw", 64,
965 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
966 },
967/* stb [$dstle+$offset16],$imm32 */
968 {
969 BPF_INSN_STBLE, "stble", "stb", 64,
970 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
971 },
972/* sth [$dstle+$offset16],$imm32 */
973 {
974 BPF_INSN_STHLE, "sthle", "sth", 64,
975 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
976 },
977/* stw [$dstle+$offset16],$imm32 */
978 {
979 BPF_INSN_STWLE, "stwle", "stw", 64,
980 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
981 },
982/* stdw [$dstle+$offset16],$imm32 */
983 {
984 BPF_INSN_STDWLE, "stdwle", "stdw", 64,
985 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
986 },
987/* stb [$dstbe+$offset16],$imm32 */
988 {
989 BPF_INSN_STBBE, "stbbe", "stb", 64,
990 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
991 },
992/* sth [$dstbe+$offset16],$imm32 */
993 {
994 BPF_INSN_STHBE, "sthbe", "sth", 64,
995 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
996 },
997/* stw [$dstbe+$offset16],$imm32 */
998 {
999 BPF_INSN_STWBE, "stwbe", "stw", 64,
1000 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
1001 },
1002/* stdw [$dstbe+$offset16],$imm32 */
1003 {
1004 BPF_INSN_STDWBE, "stdwbe", "stdw", 64,
1005 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
1006 },
1007/* jeq $dstle,$imm32,$disp16 */
1008 {
1009 BPF_INSN_JEQILE, "jeqile", "jeq", 64,
1010 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
1011 },
1012/* jeq $dstle,$srcle,$disp16 */
1013 {
1014 BPF_INSN_JEQRLE, "jeqrle", "jeq", 64,
1015 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
1016 },
1017/* jgt $dstle,$imm32,$disp16 */
1018 {
1019 BPF_INSN_JGTILE, "jgtile", "jgt", 64,
1020 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
1021 },
1022/* jgt $dstle,$srcle,$disp16 */
1023 {
1024 BPF_INSN_JGTRLE, "jgtrle", "jgt", 64,
1025 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
1026 },
1027/* jge $dstle,$imm32,$disp16 */
1028 {
1029 BPF_INSN_JGEILE, "jgeile", "jge", 64,
1030 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
1031 },
1032/* jge $dstle,$srcle,$disp16 */
1033 {
1034 BPF_INSN_JGERLE, "jgerle", "jge", 64,
1035 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
1036 },
1037/* jlt $dstle,$imm32,$disp16 */
1038 {
1039 BPF_INSN_JLTILE, "jltile", "jlt", 64,
1040 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
1041 },
1042/* jlt $dstle,$srcle,$disp16 */
1043 {
1044 BPF_INSN_JLTRLE, "jltrle", "jlt", 64,
1045 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
1046 },
1047/* jle $dstle,$imm32,$disp16 */
1048 {
1049 BPF_INSN_JLEILE, "jleile", "jle", 64,
1050 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
1051 },
1052/* jle $dstle,$srcle,$disp16 */
1053 {
1054 BPF_INSN_JLERLE, "jlerle", "jle", 64,
1055 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
1056 },
1057/* jset $dstle,$imm32,$disp16 */
1058 {
1059 BPF_INSN_JSETILE, "jsetile", "jset", 64,
1060 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
1061 },
1062/* jset $dstle,$srcle,$disp16 */
1063 {
1064 BPF_INSN_JSETRLE, "jsetrle", "jset", 64,
1065 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
1066 },
1067/* jne $dstle,$imm32,$disp16 */
1068 {
1069 BPF_INSN_JNEILE, "jneile", "jne", 64,
1070 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
1071 },
1072/* jne $dstle,$srcle,$disp16 */
1073 {
1074 BPF_INSN_JNERLE, "jnerle", "jne", 64,
1075 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
1076 },
1077/* jsgt $dstle,$imm32,$disp16 */
1078 {
1079 BPF_INSN_JSGTILE, "jsgtile", "jsgt", 64,
1080 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
1081 },
1082/* jsgt $dstle,$srcle,$disp16 */
1083 {
1084 BPF_INSN_JSGTRLE, "jsgtrle", "jsgt", 64,
1085 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
1086 },
1087/* jsge $dstle,$imm32,$disp16 */
1088 {
1089 BPF_INSN_JSGEILE, "jsgeile", "jsge", 64,
1090 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
1091 },
1092/* jsge $dstle,$srcle,$disp16 */
1093 {
1094 BPF_INSN_JSGERLE, "jsgerle", "jsge", 64,
1095 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
1096 },
1097/* jslt $dstle,$imm32,$disp16 */
1098 {
1099 BPF_INSN_JSLTILE, "jsltile", "jslt", 64,
1100 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
1101 },
1102/* jslt $dstle,$srcle,$disp16 */
1103 {
1104 BPF_INSN_JSLTRLE, "jsltrle", "jslt", 64,
1105 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
1106 },
1107/* jsle $dstle,$imm32,$disp16 */
1108 {
1109 BPF_INSN_JSLEILE, "jsleile", "jsle", 64,
1110 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
1111 },
1112/* jsle $dstle,$srcle,$disp16 */
1113 {
1114 BPF_INSN_JSLERLE, "jslerle", "jsle", 64,
1115 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
1116 },
1117/* jeq $dstbe,$imm32,$disp16 */
1118 {
1119 BPF_INSN_JEQIBE, "jeqibe", "jeq", 64,
1120 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
1121 },
1122/* jeq $dstbe,$srcbe,$disp16 */
1123 {
1124 BPF_INSN_JEQRBE, "jeqrbe", "jeq", 64,
1125 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
1126 },
1127/* jgt $dstbe,$imm32,$disp16 */
1128 {
1129 BPF_INSN_JGTIBE, "jgtibe", "jgt", 64,
1130 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
1131 },
1132/* jgt $dstbe,$srcbe,$disp16 */
1133 {
1134 BPF_INSN_JGTRBE, "jgtrbe", "jgt", 64,
1135 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
1136 },
1137/* jge $dstbe,$imm32,$disp16 */
1138 {
1139 BPF_INSN_JGEIBE, "jgeibe", "jge", 64,
1140 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
1141 },
1142/* jge $dstbe,$srcbe,$disp16 */
1143 {
1144 BPF_INSN_JGERBE, "jgerbe", "jge", 64,
1145 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
1146 },
1147/* jlt $dstbe,$imm32,$disp16 */
1148 {
1149 BPF_INSN_JLTIBE, "jltibe", "jlt", 64,
1150 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
1151 },
1152/* jlt $dstbe,$srcbe,$disp16 */
1153 {
1154 BPF_INSN_JLTRBE, "jltrbe", "jlt", 64,
1155 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
1156 },
1157/* jle $dstbe,$imm32,$disp16 */
1158 {
1159 BPF_INSN_JLEIBE, "jleibe", "jle", 64,
1160 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
1161 },
1162/* jle $dstbe,$srcbe,$disp16 */
1163 {
1164 BPF_INSN_JLERBE, "jlerbe", "jle", 64,
1165 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
1166 },
1167/* jset $dstbe,$imm32,$disp16 */
1168 {
1169 BPF_INSN_JSETIBE, "jsetibe", "jset", 64,
1170 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
1171 },
1172/* jset $dstbe,$srcbe,$disp16 */
1173 {
1174 BPF_INSN_JSETRBE, "jsetrbe", "jset", 64,
1175 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
1176 },
1177/* jne $dstbe,$imm32,$disp16 */
1178 {
1179 BPF_INSN_JNEIBE, "jneibe", "jne", 64,
1180 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
1181 },
1182/* jne $dstbe,$srcbe,$disp16 */
1183 {
1184 BPF_INSN_JNERBE, "jnerbe", "jne", 64,
1185 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
1186 },
1187/* jsgt $dstbe,$imm32,$disp16 */
1188 {
1189 BPF_INSN_JSGTIBE, "jsgtibe", "jsgt", 64,
1190 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
1191 },
1192/* jsgt $dstbe,$srcbe,$disp16 */
1193 {
1194 BPF_INSN_JSGTRBE, "jsgtrbe", "jsgt", 64,
1195 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
1196 },
1197/* jsge $dstbe,$imm32,$disp16 */
1198 {
1199 BPF_INSN_JSGEIBE, "jsgeibe", "jsge", 64,
1200 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
1201 },
1202/* jsge $dstbe,$srcbe,$disp16 */
1203 {
1204 BPF_INSN_JSGERBE, "jsgerbe", "jsge", 64,
1205 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
1206 },
1207/* jslt $dstbe,$imm32,$disp16 */
1208 {
1209 BPF_INSN_JSLTIBE, "jsltibe", "jslt", 64,
1210 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
1211 },
1212/* jslt $dstbe,$srcbe,$disp16 */
1213 {
1214 BPF_INSN_JSLTRBE, "jsltrbe", "jslt", 64,
1215 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
1216 },
1217/* jsle $dstbe,$imm32,$disp16 */
1218 {
1219 BPF_INSN_JSLEIBE, "jsleibe", "jsle", 64,
1220 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
1221 },
1222/* jsle $dstbe,$srcbe,$disp16 */
1223 {
1224 BPF_INSN_JSLERBE, "jslerbe", "jsle", 64,
1225 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
1226 },
1227/* ja $disp16 */
1228 {
1229 BPF_INSN_JA, "ja", "ja", 64,
1230 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }
1231 },
1232/* call $disp32 */
1233 {
1234 BPF_INSN_CALL, "call", "call", 64,
1235 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }
1236 },
1237/* exit */
1238 {
1239 BPF_INSN_EXIT, "exit", "exit", 64,
1240 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }
1241 },
1242/* xadddw [$dstle+$offset16],$srcle */
1243 {
1244 BPF_INSN_XADDDWLE, "xadddwle", "xadddw", 64,
1245 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
1246 },
1247/* xaddw [$dstle+$offset16],$srcle */
1248 {
1249 BPF_INSN_XADDWLE, "xaddwle", "xaddw", 64,
1250 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
1251 },
1252/* xadddw [$dstbe+$offset16],$srcbe */
1253 {
1254 BPF_INSN_XADDDWBE, "xadddwbe", "xadddw", 64,
1255 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
1256 },
1257/* xaddw [$dstbe+$offset16],$srcbe */
1258 {
1259 BPF_INSN_XADDWBE, "xaddwbe", "xaddw", 64,
1260 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
1261 },
1262};
1263
1264#undef OP
1265#undef A
1266
1267/* Initialize anything needed to be done once, before any cpu_open call. */
1268
1269static void
1270init_tables (void)
1271{
1272}
1273
1274#ifndef opcodes_error_handler
1275#define opcodes_error_handler(...) \
1276 fprintf (stderr, __VA_ARGS__); fputc ('\n', stderr)
1277#endif
1278
1279static const CGEN_MACH * lookup_mach_via_bfd_name (const CGEN_MACH *, const char *);
1280static void build_hw_table (CGEN_CPU_TABLE *);
1281static void build_ifield_table (CGEN_CPU_TABLE *);
1282static void build_operand_table (CGEN_CPU_TABLE *);
1283static void build_insn_table (CGEN_CPU_TABLE *);
1284static void bpf_cgen_rebuild_tables (CGEN_CPU_TABLE *);
1285
1286/* Subroutine of bpf_cgen_cpu_open to look up a mach via its bfd name. */
1287
1288static const CGEN_MACH *
1289lookup_mach_via_bfd_name (const CGEN_MACH *table, const char *name)
1290{
1291 while (table->name)
1292 {
1293 if (strcmp (name, table->bfd_name) == 0)
1294 return table;
1295 ++table;
1296 }
1297 return NULL;
1298}
1299
1300/* Subroutine of bpf_cgen_cpu_open to build the hardware table. */
1301
1302static void
1303build_hw_table (CGEN_CPU_TABLE *cd)
1304{
1305 int i;
1306 int machs = cd->machs;
1307 const CGEN_HW_ENTRY *init = & bpf_cgen_hw_table[0];
1308 /* MAX_HW is only an upper bound on the number of selected entries.
1309 However each entry is indexed by it's enum so there can be holes in
1310 the table. */
1311 const CGEN_HW_ENTRY **selected =
1312 (const CGEN_HW_ENTRY **) xmalloc (MAX_HW * sizeof (CGEN_HW_ENTRY *));
1313
1314 cd->hw_table.init_entries = init;
1315 cd->hw_table.entry_size = sizeof (CGEN_HW_ENTRY);
1316 memset (selected, 0, MAX_HW * sizeof (CGEN_HW_ENTRY *));
1317 /* ??? For now we just use machs to determine which ones we want. */
1318 for (i = 0; init[i].name != NULL; ++i)
1319 if (CGEN_HW_ATTR_VALUE (&init[i], CGEN_HW_MACH)
1320 & machs)
1321 selected[init[i].type] = &init[i];
1322 cd->hw_table.entries = selected;
1323 cd->hw_table.num_entries = MAX_HW;
1324}
1325
1326/* Subroutine of bpf_cgen_cpu_open to build the hardware table. */
1327
1328static void
1329build_ifield_table (CGEN_CPU_TABLE *cd)
1330{
1331 cd->ifld_table = & bpf_cgen_ifld_table[0];
1332}
1333
1334/* Subroutine of bpf_cgen_cpu_open to build the hardware table. */
1335
1336static void
1337build_operand_table (CGEN_CPU_TABLE *cd)
1338{
1339 int i;
1340 int machs = cd->machs;
1341 const CGEN_OPERAND *init = & bpf_cgen_operand_table[0];
1342 /* MAX_OPERANDS is only an upper bound on the number of selected entries.
1343 However each entry is indexed by it's enum so there can be holes in
1344 the table. */
1345 const CGEN_OPERAND **selected = xmalloc (MAX_OPERANDS * sizeof (* selected));
1346
1347 cd->operand_table.init_entries = init;
1348 cd->operand_table.entry_size = sizeof (CGEN_OPERAND);
1349 memset (selected, 0, MAX_OPERANDS * sizeof (CGEN_OPERAND *));
1350 /* ??? For now we just use mach to determine which ones we want. */
1351 for (i = 0; init[i].name != NULL; ++i)
1352 if (CGEN_OPERAND_ATTR_VALUE (&init[i], CGEN_OPERAND_MACH)
1353 & machs)
1354 selected[init[i].type] = &init[i];
1355 cd->operand_table.entries = selected;
1356 cd->operand_table.num_entries = MAX_OPERANDS;
1357}
1358
1359/* Subroutine of bpf_cgen_cpu_open to build the hardware table.
1360 ??? This could leave out insns not supported by the specified mach/isa,
1361 but that would cause errors like "foo only supported by bar" to become
1362 "unknown insn", so for now we include all insns and require the app to
1363 do the checking later.
1364 ??? On the other hand, parsing of such insns may require their hardware or
1365 operand elements to be in the table [which they mightn't be]. */
1366
1367static void
1368build_insn_table (CGEN_CPU_TABLE *cd)
1369{
1370 int i;
1371 const CGEN_IBASE *ib = & bpf_cgen_insn_table[0];
1372 CGEN_INSN *insns = xmalloc (MAX_INSNS * sizeof (CGEN_INSN));
1373
1374 memset (insns, 0, MAX_INSNS * sizeof (CGEN_INSN));
1375 for (i = 0; i < MAX_INSNS; ++i)
1376 insns[i].base = &ib[i];
1377 cd->insn_table.init_entries = insns;
1378 cd->insn_table.entry_size = sizeof (CGEN_IBASE);
1379 cd->insn_table.num_init_entries = MAX_INSNS;
1380}
1381
1382/* Subroutine of bpf_cgen_cpu_open to rebuild the tables. */
1383
1384static void
1385bpf_cgen_rebuild_tables (CGEN_CPU_TABLE *cd)
1386{
1387 int i;
1388 CGEN_BITSET *isas = cd->isas;
1389 unsigned int machs = cd->machs;
1390
1391 cd->int_insn_p = CGEN_INT_INSN_P;
1392
1393 /* Data derived from the isa spec. */
1394#define UNSET (CGEN_SIZE_UNKNOWN + 1)
1395 cd->default_insn_bitsize = UNSET;
1396 cd->base_insn_bitsize = UNSET;
1397 cd->min_insn_bitsize = 65535; /* Some ridiculously big number. */
1398 cd->max_insn_bitsize = 0;
1399 for (i = 0; i < MAX_ISAS; ++i)
1400 if (cgen_bitset_contains (isas, i))
1401 {
1402 const CGEN_ISA *isa = & bpf_cgen_isa_table[i];
1403
1404 /* Default insn sizes of all selected isas must be
1405 equal or we set the result to 0, meaning "unknown". */
1406 if (cd->default_insn_bitsize == UNSET)
1407 cd->default_insn_bitsize = isa->default_insn_bitsize;
1408 else if (isa->default_insn_bitsize == cd->default_insn_bitsize)
1409 ; /* This is ok. */
1410 else
1411 cd->default_insn_bitsize = CGEN_SIZE_UNKNOWN;
1412
1413 /* Base insn sizes of all selected isas must be equal
1414 or we set the result to 0, meaning "unknown". */
1415 if (cd->base_insn_bitsize == UNSET)
1416 cd->base_insn_bitsize = isa->base_insn_bitsize;
1417 else if (isa->base_insn_bitsize == cd->base_insn_bitsize)
1418 ; /* This is ok. */
1419 else
1420 cd->base_insn_bitsize = CGEN_SIZE_UNKNOWN;
1421
1422 /* Set min,max insn sizes. */
1423 if (isa->min_insn_bitsize < cd->min_insn_bitsize)
1424 cd->min_insn_bitsize = isa->min_insn_bitsize;
1425 if (isa->max_insn_bitsize > cd->max_insn_bitsize)
1426 cd->max_insn_bitsize = isa->max_insn_bitsize;
1427 }
1428
1429 /* Data derived from the mach spec. */
1430 for (i = 0; i < MAX_MACHS; ++i)
1431 if (((1 << i) & machs) != 0)
1432 {
1433 const CGEN_MACH *mach = & bpf_cgen_mach_table[i];
1434
1435 if (mach->insn_chunk_bitsize != 0)
1436 {
1437 if (cd->insn_chunk_bitsize != 0 && cd->insn_chunk_bitsize != mach->insn_chunk_bitsize)
1438 {
1439 opcodes_error_handler
1440 (/* xgettext:c-format */
1441 _("internal error: bpf_cgen_rebuild_tables: "
1442 "conflicting insn-chunk-bitsize values: `%d' vs. `%d'"),
1443 cd->insn_chunk_bitsize, mach->insn_chunk_bitsize);
1444 abort ();
1445 }
1446
1447 cd->insn_chunk_bitsize = mach->insn_chunk_bitsize;
1448 }
1449 }
1450
1451 /* Determine which hw elements are used by MACH. */
1452 build_hw_table (cd);
1453
1454 /* Build the ifield table. */
1455 build_ifield_table (cd);
1456
1457 /* Determine which operands are used by MACH/ISA. */
1458 build_operand_table (cd);
1459
1460 /* Build the instruction table. */
1461 build_insn_table (cd);
1462}
1463
1464/* Initialize a cpu table and return a descriptor.
1465 It's much like opening a file, and must be the first function called.
1466 The arguments are a set of (type/value) pairs, terminated with
1467 CGEN_CPU_OPEN_END.
1468
1469 Currently supported values:
1470 CGEN_CPU_OPEN_ISAS: bitmap of values in enum isa_attr
1471 CGEN_CPU_OPEN_MACHS: bitmap of values in enum mach_attr
1472 CGEN_CPU_OPEN_BFDMACH: specify 1 mach using bfd name
1473 CGEN_CPU_OPEN_ENDIAN: specify endian choice
1474 CGEN_CPU_OPEN_END: terminates arguments
1475
1476 ??? Simultaneous multiple isas might not make sense, but it's not (yet)
1477 precluded. */
1478
1479CGEN_CPU_DESC
1480bpf_cgen_cpu_open (enum cgen_cpu_open_arg arg_type, ...)
1481{
1482 CGEN_CPU_TABLE *cd = (CGEN_CPU_TABLE *) xmalloc (sizeof (CGEN_CPU_TABLE));
1483 static int init_p;
1484 CGEN_BITSET *isas = 0; /* 0 = "unspecified" */
1485 unsigned int machs = 0; /* 0 = "unspecified" */
1486 enum cgen_endian endian = CGEN_ENDIAN_UNKNOWN;
1487 va_list ap;
1488
1489 if (! init_p)
1490 {
1491 init_tables ();
1492 init_p = 1;
1493 }
1494
1495 memset (cd, 0, sizeof (*cd));
1496
1497 va_start (ap, arg_type);
1498 while (arg_type != CGEN_CPU_OPEN_END)
1499 {
1500 switch (arg_type)
1501 {
1502 case CGEN_CPU_OPEN_ISAS :
1503 isas = va_arg (ap, CGEN_BITSET *);
1504 break;
1505 case CGEN_CPU_OPEN_MACHS :
1506 machs = va_arg (ap, unsigned int);
1507 break;
1508 case CGEN_CPU_OPEN_BFDMACH :
1509 {
1510 const char *name = va_arg (ap, const char *);
1511 const CGEN_MACH *mach =
1512 lookup_mach_via_bfd_name (bpf_cgen_mach_table, name);
1513
1514 if (mach != NULL)
1515 machs |= 1 << mach->num;
1516 break;
1517 }
1518 case CGEN_CPU_OPEN_ENDIAN :
1519 endian = va_arg (ap, enum cgen_endian);
1520 break;
1521 default :
1522 opcodes_error_handler
1523 (/* xgettext:c-format */
1524 _("internal error: bpf_cgen_cpu_open: "
1525 "unsupported argument `%d'"),
1526 arg_type);
1527 abort (); /* ??? return NULL? */
1528 }
1529 arg_type = va_arg (ap, enum cgen_cpu_open_arg);
1530 }
1531 va_end (ap);
1532
1533 /* Mach unspecified means "all". */
1534 if (machs == 0)
1535 machs = (1 << MAX_MACHS) - 1;
1536 /* Base mach is always selected. */
1537 machs |= 1;
1538 if (endian == CGEN_ENDIAN_UNKNOWN)
1539 {
1540 /* ??? If target has only one, could have a default. */
1541 opcodes_error_handler
1542 (/* xgettext:c-format */
1543 _("internal error: bpf_cgen_cpu_open: no endianness specified"));
1544 abort ();
1545 }
1546
1547 cd->isas = cgen_bitset_copy (isas);
1548 cd->machs = machs;
1549 cd->endian = endian;
1550 /* FIXME: for the sparc case we can determine insn-endianness statically.
1551 The worry here is where both data and insn endian can be independently
1552 chosen, in which case this function will need another argument.
1553 Actually, will want to allow for more arguments in the future anyway. */
1554 cd->insn_endian = endian;
1555
1556 /* Table (re)builder. */
1557 cd->rebuild_tables = bpf_cgen_rebuild_tables;
1558 bpf_cgen_rebuild_tables (cd);
1559
1560 /* Default to not allowing signed overflow. */
1561 cd->signed_overflow_ok_p = 0;
1562
1563 return (CGEN_CPU_DESC) cd;
1564}
1565
1566/* Cover fn to bpf_cgen_cpu_open to handle the simple case of 1 isa, 1 mach.
1567 MACH_NAME is the bfd name of the mach. */
1568
1569CGEN_CPU_DESC
1570bpf_cgen_cpu_open_1 (const char *mach_name, enum cgen_endian endian)
1571{
1572 return bpf_cgen_cpu_open (CGEN_CPU_OPEN_BFDMACH, mach_name,
1573 CGEN_CPU_OPEN_ENDIAN, endian,
1574 CGEN_CPU_OPEN_END);
1575}
1576
1577/* Close a cpu table.
1578 ??? This can live in a machine independent file, but there's currently
1579 no place to put this file (there's no libcgen). libopcodes is the wrong
1580 place as some simulator ports use this but they don't use libopcodes. */
1581
1582void
1583bpf_cgen_cpu_close (CGEN_CPU_DESC cd)
1584{
1585 unsigned int i;
1586 const CGEN_INSN *insns;
1587
1588 if (cd->macro_insn_table.init_entries)
1589 {
1590 insns = cd->macro_insn_table.init_entries;
1591 for (i = 0; i < cd->macro_insn_table.num_init_entries; ++i, ++insns)
1592 if (CGEN_INSN_RX ((insns)))
1593 regfree (CGEN_INSN_RX (insns));
1594 }
1595
1596 if (cd->insn_table.init_entries)
1597 {
1598 insns = cd->insn_table.init_entries;
1599 for (i = 0; i < cd->insn_table.num_init_entries; ++i, ++insns)
1600 if (CGEN_INSN_RX (insns))
1601 regfree (CGEN_INSN_RX (insns));
1602 }
1603
1604 if (cd->macro_insn_table.init_entries)
1605 free ((CGEN_INSN *) cd->macro_insn_table.init_entries);
1606
1607 if (cd->insn_table.init_entries)
1608 free ((CGEN_INSN *) cd->insn_table.init_entries);
1609
1610 if (cd->hw_table.entries)
1611 free ((CGEN_HW_ENTRY *) cd->hw_table.entries);
1612
1613 if (cd->operand_table.entries)
1614 free ((CGEN_HW_ENTRY *) cd->operand_table.entries);
1615
1616 free (cd);
1617}
1618
GDB Binutils - Deliverables
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