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2005-02-23 Andrew Cagney <cagney@gnu.org>
[deliverable/binutils-gdb.git] / opcodes / fr30-dis.c
CommitLineData
252b5132
RH		 1/* Disassembler interface for targets using CGEN. -*- C -*-
2 CGEN: Cpu tools GENerator
3
4THIS FILE IS MACHINE GENERATED WITH CGEN.
5- the resultant file is machine generated, cgen-dis.in isn't
6
bf143b25 7Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2005
98f70fc4 8Free Software Foundation, Inc.
252b5132
RH		 9
10This file is part of the GNU Binutils and GDB, the GNU debugger.
11
12This program is free software; you can redistribute it and/or modify
13it under the terms of the GNU General Public License as published by
14the Free Software Foundation; either version 2, or (at your option)
15any later version.
16
17This program is distributed in the hope that it will be useful,
18but WITHOUT ANY WARRANTY; without even the implied warranty of
19MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20GNU General Public License for more details.
21
22You should have received a copy of the GNU General Public License
23along with this program; if not, write to the Free Software Foundation, Inc.,
2459 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
25
26/* ??? Eventually more and more of this stuff can go to cpu-independent files.
27 Keep that in mind. */
28
29#include "sysdep.h"
30#include <stdio.h>
31#include "ansidecl.h"
32#include "dis-asm.h"
33#include "bfd.h"
34#include "symcat.h"
98f70fc4 35#include "libiberty.h"
252b5132
RH		 36#include "fr30-desc.h"
37#include "fr30-opc.h"
38#include "opintl.h"
39
40/* Default text to print if an instruction isn't recognized. */
41#define UNKNOWN_INSN_MSG _("*unknown*")
42
0e2ee3ca 43static void print_normal
ffead7ae 44 (CGEN_CPU_DESC, void *, long, unsigned int, bfd_vma, int);
0e2ee3ca 45static void print_address
bf143b25 46 (CGEN_CPU_DESC, void *, bfd_vma, unsigned int, bfd_vma, int) ATTRIBUTE_UNUSED;
0e2ee3ca 47static void print_keyword
bf143b25 48 (CGEN_CPU_DESC, void *, CGEN_KEYWORD *, long, unsigned int) ATTRIBUTE_UNUSED;
0e2ee3ca 49static void print_insn_normal
ffead7ae 50 (CGEN_CPU_DESC, void *, const CGEN_INSN *, CGEN_FIELDS *, bfd_vma, int);
0e2ee3ca 51static int print_insn
ffead7ae 52 (CGEN_CPU_DESC, bfd_vma, disassemble_info *, char *, unsigned);
0e2ee3ca 53static int default_print_insn
bf143b25 54 (CGEN_CPU_DESC, bfd_vma, disassemble_info *) ATTRIBUTE_UNUSED;
0e2ee3ca 55static int read_insn
ffead7ae
MM		 56 (CGEN_CPU_DESC, bfd_vma, disassemble_info *, char *, int, CGEN_EXTRACT_INFO *,
57 unsigned long *);
252b5132
RH		 58\f
59/* -- disassembler routines inserted here */
60
61/* -- dis.c */
0e2ee3ca
NC		 62static void print_register_list
63 PARAMS ((PTR, long, long, int));
64static void print_hi_register_list_ld
65 PARAMS ((CGEN_CPU_DESC, PTR, long, unsigned, bfd_vma, int));
66static void print_low_register_list_ld
67 PARAMS ((CGEN_CPU_DESC, PTR, long, unsigned, bfd_vma, int));
68static void print_hi_register_list_st
69 PARAMS ((CGEN_CPU_DESC, PTR, long, unsigned, bfd_vma, int));
70static void print_low_register_list_st
71 PARAMS ((CGEN_CPU_DESC, PTR, long, unsigned, bfd_vma, int));
72static void print_m4
73 PARAMS ((CGEN_CPU_DESC, PTR, long, unsigned, bfd_vma, int));
252b5132
RH		 74
75static void
76print_register_list (dis_info, value, offset, load_store)
77 PTR dis_info;
78 long value;
79 long offset;
80 int load_store; /* 0 == load, 1 == store */
81{
82 disassemble_info *info = dis_info;
83 int mask;
84 int index = 0;
85 char* comma = "";
86
87 if (load_store)
88 mask = 0x80;
89 else
90 mask = 1;
91
92 if (value & mask)
93 {
94 (*info->fprintf_func) (info->stream, "r%i", index + offset);
95 comma = ",";
96 }
97
98 for (index = 1; index <= 7; ++index)
99 {
100 if (load_store)
101 mask >>= 1;
102 else
103 mask <<= 1;
104
105 if (value & mask)
106 {
107 (*info->fprintf_func) (info->stream, "%sr%i", comma, index + offset);
108 comma = ",";
109 }
110 }
111}
112
113static void
114print_hi_register_list_ld (cd, dis_info, value, attrs, pc, length)
9a2e995d 115 CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
252b5132
RH		 116 PTR dis_info;
117 long value;
9a2e995d
GH		 118 unsigned int attrs ATTRIBUTE_UNUSED;
119 bfd_vma pc ATTRIBUTE_UNUSED;
120 int length ATTRIBUTE_UNUSED;
252b5132
RH		 121{
122 print_register_list (dis_info, value, 8, 0/*load*/);
123}
124
125static void
126print_low_register_list_ld (cd, dis_info, value, attrs, pc, length)
9a2e995d 127 CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
252b5132
RH		 128 PTR dis_info;
129 long value;
9a2e995d
GH		 130 unsigned int attrs ATTRIBUTE_UNUSED;
131 bfd_vma pc ATTRIBUTE_UNUSED;
132 int length ATTRIBUTE_UNUSED;
252b5132
RH		 133{
134 print_register_list (dis_info, value, 0, 0/*load*/);
135}
136
137static void
138print_hi_register_list_st (cd, dis_info, value, attrs, pc, length)
9a2e995d 139 CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
252b5132
RH		 140 PTR dis_info;
141 long value;
9a2e995d
GH		 142 unsigned int attrs ATTRIBUTE_UNUSED;
143 bfd_vma pc ATTRIBUTE_UNUSED;
144 int length ATTRIBUTE_UNUSED;
252b5132
RH		 145{
146 print_register_list (dis_info, value, 8, 1/*store*/);
147}
148
149static void
150print_low_register_list_st (cd, dis_info, value, attrs, pc, length)
9a2e995d 151 CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
252b5132
RH		 152 PTR dis_info;
153 long value;
9a2e995d
GH		 154 unsigned int attrs ATTRIBUTE_UNUSED;
155 bfd_vma pc ATTRIBUTE_UNUSED;
156 int length ATTRIBUTE_UNUSED;
252b5132
RH		 157{
158 print_register_list (dis_info, value, 0, 1/*store*/);
159}
160
161static void
162print_m4 (cd, dis_info, value, attrs, pc, length)
9a2e995d 163 CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
252b5132
RH		 164 PTR dis_info;
165 long value;
9a2e995d
GH		 166 unsigned int attrs ATTRIBUTE_UNUSED;
167 bfd_vma pc ATTRIBUTE_UNUSED;
168 int length ATTRIBUTE_UNUSED;
252b5132
RH		 169{
170 disassemble_info *info = (disassemble_info *) dis_info;
171 (*info->fprintf_func) (info->stream, "%ld", value);
172}
173/* -- */
174
0e2ee3ca
NC		 175void fr30_cgen_print_operand
176 PARAMS ((CGEN_CPU_DESC, int, PTR, CGEN_FIELDS *,
177 void const *, bfd_vma, int));
178
252b5132
RH		 179/* Main entry point for printing operands.
180 XINFO is a `void *' and not a `disassemble_info *' to not put a requirement
181 of dis-asm.h on cgen.h.
182
183 This function is basically just a big switch statement. Earlier versions
184 used tables to look up the function to use, but
185 - if the table contains both assembler and disassembler functions then
186 the disassembler contains much of the assembler and vice-versa,
187 - there's a lot of inlining possibilities as things grow,
188 - using a switch statement avoids the function call overhead.
189
190 This function could be moved into `print_insn_normal', but keeping it
191 separate makes clear the interface between `print_insn_normal' and each of
9a2e995d 192 the handlers. */
252b5132
RH		 193
194void
195fr30_cgen_print_operand (cd, opindex, xinfo, fields, attrs, pc, length)
196 CGEN_CPU_DESC cd;
197 int opindex;
198 PTR xinfo;
199 CGEN_FIELDS *fields;
d5b2f4d6 200 void const *attrs ATTRIBUTE_UNUSED;
252b5132
RH		 201 bfd_vma pc;
202 int length;
203{
204 disassemble_info *info = (disassemble_info *) xinfo;
205
206 switch (opindex)
207 {
208 case FR30_OPERAND_CRI :
209 print_keyword (cd, info, & fr30_cgen_opval_cr_names, fields->f_CRi, 0);
210 break;
211 case FR30_OPERAND_CRJ :
212 print_keyword (cd, info, & fr30_cgen_opval_cr_names, fields->f_CRj, 0);
213 break;
214 case FR30_OPERAND_R13 :
eb1b03df 215 print_keyword (cd, info, & fr30_cgen_opval_h_r13, 0, 0);
252b5132
RH		 216 break;
217 case FR30_OPERAND_R14 :
eb1b03df 218 print_keyword (cd, info, & fr30_cgen_opval_h_r14, 0, 0);
252b5132
RH		 219 break;
220 case FR30_OPERAND_R15 :
eb1b03df 221 print_keyword (cd, info, & fr30_cgen_opval_h_r15, 0, 0);
252b5132
RH		 222 break;
223 case FR30_OPERAND_RI :
224 print_keyword (cd, info, & fr30_cgen_opval_gr_names, fields->f_Ri, 0);
225 break;
226 case FR30_OPERAND_RIC :
227 print_keyword (cd, info, & fr30_cgen_opval_gr_names, fields->f_Ric, 0);
228 break;
229 case FR30_OPERAND_RJ :
230 print_keyword (cd, info, & fr30_cgen_opval_gr_names, fields->f_Rj, 0);
231 break;
232 case FR30_OPERAND_RJC :
233 print_keyword (cd, info, & fr30_cgen_opval_gr_names, fields->f_Rjc, 0);
234 break;
235 case FR30_OPERAND_RS1 :
236 print_keyword (cd, info, & fr30_cgen_opval_dr_names, fields->f_Rs1, 0);
237 break;
238 case FR30_OPERAND_RS2 :
239 print_keyword (cd, info, & fr30_cgen_opval_dr_names, fields->f_Rs2, 0);
240 break;
241 case FR30_OPERAND_CC :
242 print_normal (cd, info, fields->f_cc, 0, pc, length);
243 break;
244 case FR30_OPERAND_CCC :
245 print_normal (cd, info, fields->f_ccc, 0|(1<<CGEN_OPERAND_HASH_PREFIX), pc, length);
246 break;
247 case FR30_OPERAND_DIR10 :
248 print_normal (cd, info, fields->f_dir10, 0, pc, length);
249 break;
250 case FR30_OPERAND_DIR8 :
251 print_normal (cd, info, fields->f_dir8, 0, pc, length);
252 break;
253 case FR30_OPERAND_DIR9 :
254 print_normal (cd, info, fields->f_dir9, 0, pc, length);
255 break;
256 case FR30_OPERAND_DISP10 :
257 print_normal (cd, info, fields->f_disp10, 0|(1<<CGEN_OPERAND_SIGNED)|(1<<CGEN_OPERAND_HASH_PREFIX), pc, length);
258 break;
259 case FR30_OPERAND_DISP8 :
260 print_normal (cd, info, fields->f_disp8, 0|(1<<CGEN_OPERAND_SIGNED)|(1<<CGEN_OPERAND_HASH_PREFIX), pc, length);
261 break;
262 case FR30_OPERAND_DISP9 :
263 print_normal (cd, info, fields->f_disp9, 0|(1<<CGEN_OPERAND_SIGNED)|(1<<CGEN_OPERAND_HASH_PREFIX), pc, length);
264 break;
265 case FR30_OPERAND_I20 :
266 print_normal (cd, info, fields->f_i20, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_VIRTUAL), pc, length);
267 break;
268 case FR30_OPERAND_I32 :
269 print_normal (cd, info, fields->f_i32, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_SIGN_OPT), pc, length);
270 break;
271 case FR30_OPERAND_I8 :
272 print_normal (cd, info, fields->f_i8, 0|(1<<CGEN_OPERAND_HASH_PREFIX), pc, length);
273 break;
274 case FR30_OPERAND_LABEL12 :
275 print_address (cd, info, fields->f_rel12, 0|(1<<CGEN_OPERAND_PCREL_ADDR), pc, length);
276 break;
277 case FR30_OPERAND_LABEL9 :
278 print_address (cd, info, fields->f_rel9, 0|(1<<CGEN_OPERAND_PCREL_ADDR), pc, length);
279 break;
280 case FR30_OPERAND_M4 :
281 print_m4 (cd, info, fields->f_m4, 0|(1<<CGEN_OPERAND_SIGNED)|(1<<CGEN_OPERAND_HASH_PREFIX), pc, length);
282 break;
283 case FR30_OPERAND_PS :
eb1b03df 284 print_keyword (cd, info, & fr30_cgen_opval_h_ps, 0, 0);
252b5132
RH		 285 break;
286 case FR30_OPERAND_REGLIST_HI_LD :
287 print_hi_register_list_ld (cd, info, fields->f_reglist_hi_ld, 0, pc, length);
288 break;
289 case FR30_OPERAND_REGLIST_HI_ST :
290 print_hi_register_list_st (cd, info, fields->f_reglist_hi_st, 0, pc, length);
291 break;
292 case FR30_OPERAND_REGLIST_LOW_LD :
293 print_low_register_list_ld (cd, info, fields->f_reglist_low_ld, 0, pc, length);
294 break;
295 case FR30_OPERAND_REGLIST_LOW_ST :
296 print_low_register_list_st (cd, info, fields->f_reglist_low_st, 0, pc, length);
297 break;
298 case FR30_OPERAND_S10 :
299 print_normal (cd, info, fields->f_s10, 0|(1<<CGEN_OPERAND_SIGNED)|(1<<CGEN_OPERAND_HASH_PREFIX), pc, length);
300 break;
301 case FR30_OPERAND_U10 :
302 print_normal (cd, info, fields->f_u10, 0|(1<<CGEN_OPERAND_HASH_PREFIX), pc, length);
303 break;
304 case FR30_OPERAND_U4 :
305 print_normal (cd, info, fields->f_u4, 0|(1<<CGEN_OPERAND_HASH_PREFIX), pc, length);
306 break;
307 case FR30_OPERAND_U4C :
308 print_normal (cd, info, fields->f_u4c, 0|(1<<CGEN_OPERAND_HASH_PREFIX), pc, length);
309 break;
310 case FR30_OPERAND_U8 :
311 print_normal (cd, info, fields->f_u8, 0|(1<<CGEN_OPERAND_HASH_PREFIX), pc, length);
312 break;
313 case FR30_OPERAND_UDISP6 :
314 print_normal (cd, info, fields->f_udisp6, 0|(1<<CGEN_OPERAND_HASH_PREFIX), pc, length);
315 break;
316
317 default :
318 /* xgettext:c-format */
319 fprintf (stderr, _("Unrecognized field %d while printing insn.\n"),
320 opindex);
321 abort ();
322 }
323}
324
325cgen_print_fn * const fr30_cgen_print_handlers[] =
326{
327 print_insn_normal,
328};
329
330
331void
332fr30_cgen_init_dis (cd)
333 CGEN_CPU_DESC cd;
334{
335 fr30_cgen_init_opcode_table (cd);
336 fr30_cgen_init_ibld_table (cd);
337 cd->print_handlers = & fr30_cgen_print_handlers[0];
338 cd->print_operand = fr30_cgen_print_operand;
339}
340
341\f
342/* Default print handler. */
343
344static void
ffead7ae
MM		 345print_normal (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
346 void *dis_info,
347 long value,
348 unsigned int attrs,
349 bfd_vma pc ATTRIBUTE_UNUSED,
350 int length ATTRIBUTE_UNUSED)
252b5132
RH		 351{
352 disassemble_info *info = (disassemble_info *) dis_info;
353
354#ifdef CGEN_PRINT_NORMAL
355 CGEN_PRINT_NORMAL (cd, info, value, attrs, pc, length);
356#endif
357
358 /* Print the operand as directed by the attributes. */
359 if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SEM_ONLY))
360 ; /* nothing to do */
361 else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SIGNED))
362 (*info->fprintf_func) (info->stream, "%ld", value);
363 else
364 (*info->fprintf_func) (info->stream, "0x%lx", value);
365}
366
367/* Default address handler. */
368
369static void
ffead7ae
MM		 370print_address (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
371 void *dis_info,
372 bfd_vma value,
373 unsigned int attrs,
374 bfd_vma pc ATTRIBUTE_UNUSED,
375 int length ATTRIBUTE_UNUSED)
252b5132
RH		 376{
377 disassemble_info *info = (disassemble_info *) dis_info;
378
379#ifdef CGEN_PRINT_ADDRESS
380 CGEN_PRINT_ADDRESS (cd, info, value, attrs, pc, length);
381#endif
382
383 /* Print the operand as directed by the attributes. */
384 if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SEM_ONLY))
385 ; /* nothing to do */
386 else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_PCREL_ADDR))
387 (*info->print_address_func) (value, info);
388 else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_ABS_ADDR))
389 (*info->print_address_func) (value, info);
390 else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SIGNED))
391 (*info->fprintf_func) (info->stream, "%ld", (long) value);
392 else
393 (*info->fprintf_func) (info->stream, "0x%lx", (long) value);
394}
395
396/* Keyword print handler. */
397
398static void
ffead7ae
MM		 399print_keyword (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
400 void *dis_info,
401 CGEN_KEYWORD *keyword_table,
402 long value,
403 unsigned int attrs ATTRIBUTE_UNUSED)
252b5132
RH		 404{
405 disassemble_info *info = (disassemble_info *) dis_info;
406 const CGEN_KEYWORD_ENTRY *ke;
407
408 ke = cgen_keyword_lookup_value (keyword_table, value);
409 if (ke != NULL)
410 (*info->fprintf_func) (info->stream, "%s", ke->name);
411 else
412 (*info->fprintf_func) (info->stream, "???");
413}
414\f
415/* Default insn printer.
416
ffead7ae 417 DIS_INFO is defined as `void *' so the disassembler needn't know anything
252b5132
RH		 418 about disassemble_info. */
419
420static void
ffead7ae
MM		 421print_insn_normal (CGEN_CPU_DESC cd,
422 void *dis_info,
423 const CGEN_INSN *insn,
424 CGEN_FIELDS *fields,
425 bfd_vma pc,
426 int length)
252b5132
RH		 427{
428 const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn);
429 disassemble_info *info = (disassemble_info *) dis_info;
b3466c39 430 const CGEN_SYNTAX_CHAR_TYPE *syn;
252b5132
RH		 431
432 CGEN_INIT_PRINT (cd);
433
434 for (syn = CGEN_SYNTAX_STRING (syntax); *syn; ++syn)
435 {
436 if (CGEN_SYNTAX_MNEMONIC_P (*syn))
437 {
438 (*info->fprintf_func) (info->stream, "%s", CGEN_INSN_MNEMONIC (insn));
439 continue;
440 }
441 if (CGEN_SYNTAX_CHAR_P (*syn))
442 {
443 (*info->fprintf_func) (info->stream, "%c", CGEN_SYNTAX_CHAR (*syn));
444 continue;
445 }
446
447 /* We have an operand. */
448 fr30_cgen_print_operand (cd, CGEN_SYNTAX_FIELD (*syn), info,
449 fields, CGEN_INSN_ATTRS (insn), pc, length);
450 }
451}
452\f
6bb95a0f
DB		 453/* Subroutine of print_insn. Reads an insn into the given buffers and updates
454 the extract info.
455 Returns 0 if all is well, non-zero otherwise. */
0e2ee3ca 456
252b5132 457static int
ffead7ae
MM		 458read_insn (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
459 bfd_vma pc,
460 disassemble_info *info,
461 char *buf,
462 int buflen,
463 CGEN_EXTRACT_INFO *ex_info,
464 unsigned long *insn_value)
252b5132 465{
6bb95a0f
DB		 466 int status = (*info->read_memory_func) (pc, buf, buflen, info);
467 if (status != 0)
468 {
469 (*info->memory_error_func) (status, pc, info);
470 return -1;
471 }
252b5132 472
6bb95a0f
DB		 473 ex_info->dis_info = info;
474 ex_info->valid = (1 << buflen) - 1;
475 ex_info->insn_bytes = buf;
252b5132 476
b3466c39 477 *insn_value = bfd_get_bits (buf, buflen * 8, info->endian == BFD_ENDIAN_BIG);
6bb95a0f
DB		 478 return 0;
479}
480
481/* Utility to print an insn.
482 BUF is the base part of the insn, target byte order, BUFLEN bytes long.
483 The result is the size of the insn in bytes or zero for an unknown insn
484 or -1 if an error occurs fetching data (memory_error_func will have
485 been called). */
486
487static int
ffead7ae
MM		 488print_insn (CGEN_CPU_DESC cd,
489 bfd_vma pc,
490 disassemble_info *info,
491 char *buf,
492 unsigned int buflen)
6bb95a0f 493{
fc7bc883 494 CGEN_INSN_INT insn_value;
6bb95a0f
DB		 495 const CGEN_INSN_LIST *insn_list;
496 CGEN_EXTRACT_INFO ex_info;
2e1ef6b4 497 int basesize;
6bb95a0f 498
fc7bc883 499 /* Extract base part of instruction, just in case CGEN_DIS_* uses it. */
2e1ef6b4
DB		 500 basesize = cd->base_insn_bitsize < buflen * 8 ?
501 cd->base_insn_bitsize : buflen * 8;
502 insn_value = cgen_get_insn_value (cd, buf, basesize);
503
fc7bc883
RH		 504
505 /* Fill in ex_info fields like read_insn would. Don't actually call
506 read_insn, since the incoming buffer is already read (and possibly
507 modified a la m32r). */
508 ex_info.valid = (1 << buflen) - 1;
509 ex_info.dis_info = info;
510 ex_info.insn_bytes = buf;
6bb95a0f 511
252b5132
RH		 512 /* The instructions are stored in hash lists.
513 Pick the first one and keep trying until we find the right one. */
514
515 insn_list = CGEN_DIS_LOOKUP_INSN (cd, buf, insn_value);
516 while (insn_list != NULL)
517 {
518 const CGEN_INSN *insn = insn_list->insn;
519 CGEN_FIELDS fields;
520 int length;
fc7bc883 521 unsigned long insn_value_cropped;
252b5132 522
6bb95a0f 523#ifdef CGEN_VALIDATE_INSN_SUPPORTED
0e2ee3ca 524 /* Not needed as insn shouldn't be in hash lists if not supported. */
252b5132
RH		 525 /* Supported by this cpu? */
526 if (! fr30_cgen_insn_supported (cd, insn))
6bb95a0f
DB		 527 {
528 insn_list = CGEN_DIS_NEXT_INSN (insn_list);
529 continue;
530 }
252b5132
RH		 531#endif
532
533 /* Basic bit mask must be correct. */
534 /* ??? May wish to allow target to defer this check until the extract
535 handler. */
fc7bc883
RH		 536
537 /* Base size may exceed this instruction's size. Extract the
538 relevant part from the buffer. */
0e2ee3ca 539 if ((unsigned) (CGEN_INSN_BITSIZE (insn) / 8) < buflen &&
d5b2f4d6 540 (unsigned) (CGEN_INSN_BITSIZE (insn) / 8) <= sizeof (unsigned long))
fc7bc883
RH		 541 insn_value_cropped = bfd_get_bits (buf, CGEN_INSN_BITSIZE (insn),
542 info->endian == BFD_ENDIAN_BIG);
543 else
544 insn_value_cropped = insn_value;
545
546 if ((insn_value_cropped & CGEN_INSN_BASE_MASK (insn))
252b5132
RH		 547 == CGEN_INSN_BASE_VALUE (insn))
548 {
549 /* Printing is handled in two passes. The first pass parses the
550 machine insn and extracts the fields. The second pass prints
551 them. */
552
708b8a71
NC		 553 /* Make sure the entire insn is loaded into insn_value, if it
554 can fit. */
0e2ee3ca 555 if (((unsigned) CGEN_INSN_BITSIZE (insn) > cd->base_insn_bitsize) &&
d5b2f4d6 556 (unsigned) (CGEN_INSN_BITSIZE (insn) / 8) <= sizeof (unsigned long))
6bb95a0f
DB		 557 {
558 unsigned long full_insn_value;
559 int rc = read_insn (cd, pc, info, buf,
560 CGEN_INSN_BITSIZE (insn) / 8,
561 & ex_info, & full_insn_value);
562 if (rc != 0)
563 return rc;
564 length = CGEN_EXTRACT_FN (cd, insn)
565 (cd, insn, &ex_info, full_insn_value, &fields, pc);
566 }
567 else
708b8a71 568 length = CGEN_EXTRACT_FN (cd, insn)
fc7bc883 569 (cd, insn, &ex_info, insn_value_cropped, &fields, pc);
6bb95a0f 570
252b5132
RH		 571 /* length < 0 -> error */
572 if (length < 0)
573 return length;
574 if (length > 0)
575 {
576 CGEN_PRINT_FN (cd, insn) (cd, info, insn, &fields, pc, length);
577 /* length is in bits, result is in bytes */
578 return length / 8;
579 }
580 }
581
582 insn_list = CGEN_DIS_NEXT_INSN (insn_list);
583 }
584
585 return 0;
586}
587
588/* Default value for CGEN_PRINT_INSN.
589 The result is the size of the insn in bytes or zero for an unknown insn
590 or -1 if an error occured fetching bytes. */
591
592#ifndef CGEN_PRINT_INSN
593#define CGEN_PRINT_INSN default_print_insn
594#endif
595
596static int
ffead7ae 597default_print_insn (CGEN_CPU_DESC cd, bfd_vma pc, disassemble_info *info)
252b5132
RH		 598{
599 char buf[CGEN_MAX_INSN_SIZE];
fc7bc883 600 int buflen;
252b5132
RH		 601 int status;
602
fc7bc883
RH		 603 /* Attempt to read the base part of the insn. */
604 buflen = cd->base_insn_bitsize / 8;
605 status = (*info->read_memory_func) (pc, buf, buflen, info);
606
607 /* Try again with the minimum part, if min < base. */
608 if (status != 0 && (cd->min_insn_bitsize < cd->base_insn_bitsize))
609 {
610 buflen = cd->min_insn_bitsize / 8;
611 status = (*info->read_memory_func) (pc, buf, buflen, info);
612 }
252b5132 613
252b5132
RH		 614 if (status != 0)
615 {
616 (*info->memory_error_func) (status, pc, info);
617 return -1;
618 }
619
fc7bc883 620 return print_insn (cd, pc, info, buf, buflen);
252b5132
RH		 621}
622
623/* Main entry point.
624 Print one instruction from PC on INFO->STREAM.
625 Return the size of the instruction (in bytes). */
626
a978a3e5
NC		 627typedef struct cpu_desc_list {
628 struct cpu_desc_list *next;
629 int isa;
630 int mach;
631 int endian;
632 CGEN_CPU_DESC cd;
633} cpu_desc_list;
634
252b5132 635int
ffead7ae 636print_insn_fr30 (bfd_vma pc, disassemble_info *info)
252b5132 637{
a978a3e5
NC		 638 static cpu_desc_list *cd_list = 0;
639 cpu_desc_list *cl = 0;
252b5132 640 static CGEN_CPU_DESC cd = 0;
6bb95a0f
DB		 641 static int prev_isa;
642 static int prev_mach;
643 static int prev_endian;
252b5132
RH		 644 int length;
645 int isa,mach;
646 int endian = (info->endian == BFD_ENDIAN_BIG
647 ? CGEN_ENDIAN_BIG
648 : CGEN_ENDIAN_LITTLE);
649 enum bfd_architecture arch;
650
651 /* ??? gdb will set mach but leave the architecture as "unknown" */
652#ifndef CGEN_BFD_ARCH
653#define CGEN_BFD_ARCH bfd_arch_fr30
654#endif
655 arch = info->arch;
656 if (arch == bfd_arch_unknown)
657 arch = CGEN_BFD_ARCH;
27fca2d8
PM		 658
659 /* There's no standard way to compute the machine or isa number
252b5132 660 so we leave it to the target. */
27fca2d8
PM		 661#ifdef CGEN_COMPUTE_MACH
662 mach = CGEN_COMPUTE_MACH (info);
663#else
664 mach = info->mach;
665#endif
666
252b5132
RH		 667#ifdef CGEN_COMPUTE_ISA
668 isa = CGEN_COMPUTE_ISA (info);
669#else
a978a3e5 670 isa = info->insn_sets;
252b5132
RH		 671#endif
672
a978a3e5 673 /* If we've switched cpu's, try to find a handle we've used before */
252b5132
RH		 674 if (cd
675 && (isa != prev_isa
676 || mach != prev_mach
677 || endian != prev_endian))
678 {
252b5132 679 cd = 0;
a978a3e5
NC		 680 for (cl = cd_list; cl; cl = cl->next)
681 {
682 if (cl->isa == isa &&
683 cl->mach == mach &&
684 cl->endian == endian)
685 {
686 cd = cl->cd;
687 break;
688 }
689 }
690 }
252b5132
RH		 691
692 /* If we haven't initialized yet, initialize the opcode table. */
693 if (! cd)
694 {
695 const bfd_arch_info_type *arch_type = bfd_lookup_arch (arch, mach);
696 const char *mach_name;
697
698 if (!arch_type)
699 abort ();
700 mach_name = arch_type->printable_name;
701
702 prev_isa = isa;
703 prev_mach = mach;
704 prev_endian = endian;
705 cd = fr30_cgen_cpu_open (CGEN_CPU_OPEN_ISAS, prev_isa,
706 CGEN_CPU_OPEN_BFDMACH, mach_name,
707 CGEN_CPU_OPEN_ENDIAN, prev_endian,
708 CGEN_CPU_OPEN_END);
709 if (!cd)
710 abort ();
a978a3e5
NC		 711
712 /* save this away for future reference */
713 cl = xmalloc (sizeof (struct cpu_desc_list));
714 cl->cd = cd;
715 cl->isa = isa;
716 cl->mach = mach;
717 cl->endian = endian;
718 cl->next = cd_list;
719 cd_list = cl;
720
252b5132
RH		 721 fr30_cgen_init_dis (cd);
722 }
723
724 /* We try to have as much common code as possible.
725 But at this point some targets need to take over. */
726 /* ??? Some targets may need a hook elsewhere. Try to avoid this,
727 but if not possible try to move this hook elsewhere rather than
728 have two hooks. */
729 length = CGEN_PRINT_INSN (cd, pc, info);
730 if (length > 0)
731 return length;
732 if (length < 0)
733 return -1;
734
735 (*info->fprintf_func) (info->stream, UNKNOWN_INSN_MSG);
736 return cd->default_insn_bitsize / 8;
737}
GDB Binutils - Deliverables
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