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2001-01-10 Kazu Hirata <kazu@hxi.com>
[deliverable/binutils-gdb.git] / opcodes / i386-dis.c
CommitLineData
252b5132
RH		 1/* Print i386 instructions for GDB, the GNU debugger.
2 Copyright (C) 1988, 89, 91, 93, 94, 95, 96, 97, 98, 1999
3 Free Software Foundation, Inc.
4
5This file is part of GDB.
6
7This program is free software; you can redistribute it and/or modify
8it under the terms of the GNU General Public License as published by
9the Free Software Foundation; either version 2 of the License, or
10(at your option) any later version.
11
12This program is distributed in the hope that it will be useful,
13but WITHOUT ANY WARRANTY; without even the implied warranty of
14MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15GNU General Public License for more details.
16
17You should have received a copy of the GNU General Public License
18along with this program; if not, write to the Free Software
19Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
20
21/*
22 * 80386 instruction printer by Pace Willisson (pace@prep.ai.mit.edu)
23 * July 1988
24 * modified by John Hassey (hassey@dg-rtp.dg.com)
52b15da3 25 * x86-64 support added by Jan Hubicka (jh@suse.cz)
252b5132
RH		 26 */
27
28/*
29 * The main tables describing the instructions is essentially a copy
30 * of the "Opcode Map" chapter (Appendix A) of the Intel 80386
31 * Programmers Manual. Usually, there is a capital letter, followed
32 * by a small letter. The capital letter tell the addressing mode,
33 * and the small letter tells about the operand size. Refer to
34 * the Intel manual for details.
35 */
36
37#include "dis-asm.h"
38#include "sysdep.h"
39#include "opintl.h"
40
41#define MAXLEN 20
42
43#include <setjmp.h>
44
45#ifndef UNIXWARE_COMPAT
46/* Set non-zero for broken, compatible instructions. Set to zero for
47 non-broken opcodes. */
48#define UNIXWARE_COMPAT 1
49#endif
50
252b5132
RH		 51static int fetch_data PARAMS ((struct disassemble_info *, bfd_byte *));
52
53struct dis_private
54{
55 /* Points to first byte not fetched. */
56 bfd_byte *max_fetched;
57 bfd_byte the_buffer[MAXLEN];
58 bfd_vma insn_start;
59 jmp_buf bailout;
60};
61
5076851f
ILT		 62/* The opcode for the fwait instruction, which we treat as a prefix
63 when we can. */
64#define FWAIT_OPCODE (0x9b)
65
52b15da3
JH		 66/* Set to 1 for 64bit mode disassembly. */
67static int mode_64bit;
68
5076851f
ILT		 69/* Flags for the prefixes for the current instruction. See below. */
70static int prefixes;
71
52b15da3
JH		 72/* REX prefix the current instruction. See below. */
73static int rex;
74/* Bits of REX we've already used. */
75static int rex_used;
76#define REX_MODE64 8
77#define REX_EXTX 4
78#define REX_EXTY 2
79#define REX_EXTZ 1
80/* Mark parts used in the REX prefix. When we are testing for
81 empty prefix (for 8bit register REX extension), just mask it
82 out. Otherwise test for REX bit is excuse for existence of REX
83 only in case value is nonzero. */
84#define USED_REX(value) \
85 { \
86 if (value) \
87 rex_used |= (rex & value) ? (value) | 0x40 : 0; \
88 else \
89 rex_used |= 0x40; \
90 }
91
7d421014
ILT		 92/* Flags for prefixes which we somehow handled when printing the
93 current instruction. */
94static int used_prefixes;
95
5076851f
ILT		 96/* Flags stored in PREFIXES. */
97#define PREFIX_REPZ 1
98#define PREFIX_REPNZ 2
99#define PREFIX_LOCK 4
100#define PREFIX_CS 8
101#define PREFIX_SS 0x10
102#define PREFIX_DS 0x20
103#define PREFIX_ES 0x40
104#define PREFIX_FS 0x80
105#define PREFIX_GS 0x100
106#define PREFIX_DATA 0x200
107#define PREFIX_ADDR 0x400
108#define PREFIX_FWAIT 0x800
109
252b5132
RH		 110/* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive)
111 to ADDR (exclusive) are valid. Returns 1 for success, longjmps
112 on error. */
113#define FETCH_DATA(info, addr) \
114 ((addr) <= ((struct dis_private *)(info->private_data))->max_fetched \
115 ? 1 : fetch_data ((info), (addr)))
116
117static int
118fetch_data (info, addr)
119 struct disassemble_info *info;
120 bfd_byte *addr;
121{
122 int status;
123 struct dis_private *priv = (struct dis_private *)info->private_data;
124 bfd_vma start = priv->insn_start + (priv->max_fetched - priv->the_buffer);
125
126 status = (*info->read_memory_func) (start,
127 priv->max_fetched,
128 addr - priv->max_fetched,
129 info);
130 if (status != 0)
131 {
7d421014
ILT		 132 /* If we did manage to read at least one byte, then
133 print_insn_i386 will do something sensible. Otherwise, print
134 an error. We do that here because this is where we know
135 STATUS. */
136 if (priv->max_fetched == priv->the_buffer)
5076851f 137 (*info->memory_error_func) (status, start, info);
252b5132
RH		 138 longjmp (priv->bailout, 1);
139 }
140 else
141 priv->max_fetched = addr;
142 return 1;
143}
144
57d91c3c
ILT		 145#define XX NULL, 0
146
252b5132 147#define Eb OP_E, b_mode
52b15da3
JH		 148#define Ev OP_E, v_mode
149#define Ed OP_E, d_mode
252b5132
RH		 150#define indirEb OP_indirE, b_mode
151#define Gb OP_G, b_mode
152#define Ev OP_E, v_mode
2da11e11 153#define Ed OP_E, d_mode
252b5132
RH		 154#define indirEv OP_indirE, v_mode
155#define Ew OP_E, w_mode
156#define Ma OP_E, v_mode
2da11e11
AM		 157#define M OP_E, 0 /* lea */
158#define Mp OP_E, 0 /* 32 or 48 bit memory operand for LDS, LES etc */
252b5132
RH		 159#define Gv OP_G, v_mode
160#define Gw OP_G, w_mode
2da11e11 161#define Rd OP_Rd, d_mode
52b15da3 162#define Rm OP_Rd, m_mode
252b5132
RH		 163#define Ib OP_I, b_mode
164#define sIb OP_sI, b_mode /* sign extened byte */
165#define Iv OP_I, v_mode
52b15da3
JH		 166#define Iq OP_I, q_mode
167#define Iv64 OP_I64, v_mode
252b5132
RH		 168#define Iw OP_I, w_mode
169#define Jb OP_J, b_mode
170#define Jv OP_J, v_mode
52b15da3
JH		 171#define Cm OP_C, m_mode
172#define Dm OP_D, m_mode
252b5132
RH		 173#define Td OP_T, d_mode
174
52b15da3
JH		 175#define RMeAX OP_REG, eAX_reg
176#define RMeBX OP_REG, eBX_reg
177#define RMeCX OP_REG, eCX_reg
178#define RMeDX OP_REG, eDX_reg
179#define RMeSP OP_REG, eSP_reg
180#define RMeBP OP_REG, eBP_reg
181#define RMeSI OP_REG, eSI_reg
182#define RMeDI OP_REG, eDI_reg
183#define RMrAX OP_REG, rAX_reg
184#define RMrBX OP_REG, rBX_reg
185#define RMrCX OP_REG, rCX_reg
186#define RMrDX OP_REG, rDX_reg
187#define RMrSP OP_REG, rSP_reg
188#define RMrBP OP_REG, rBP_reg
189#define RMrSI OP_REG, rSI_reg
190#define RMrDI OP_REG, rDI_reg
191#define RMAL OP_REG, al_reg
192#define RMAL OP_REG, al_reg
193#define RMCL OP_REG, cl_reg
194#define RMDL OP_REG, dl_reg
195#define RMBL OP_REG, bl_reg
196#define RMAH OP_REG, ah_reg
197#define RMCH OP_REG, ch_reg
198#define RMDH OP_REG, dh_reg
199#define RMBH OP_REG, bh_reg
200#define RMAX OP_REG, ax_reg
201#define RMDX OP_REG, dx_reg
202
203#define eAX OP_IMREG, eAX_reg
204#define eBX OP_IMREG, eBX_reg
205#define eCX OP_IMREG, eCX_reg
206#define eDX OP_IMREG, eDX_reg
207#define eSP OP_IMREG, eSP_reg
208#define eBP OP_IMREG, eBP_reg
209#define eSI OP_IMREG, eSI_reg
210#define eDI OP_IMREG, eDI_reg
211#define AL OP_IMREG, al_reg
212#define AL OP_IMREG, al_reg
213#define CL OP_IMREG, cl_reg
214#define DL OP_IMREG, dl_reg
215#define BL OP_IMREG, bl_reg
216#define AH OP_IMREG, ah_reg
217#define CH OP_IMREG, ch_reg
218#define DH OP_IMREG, dh_reg
219#define BH OP_IMREG, bh_reg
220#define AX OP_IMREG, ax_reg
221#define DX OP_IMREG, dx_reg
222#define indirDX OP_IMREG, indir_dx_reg
252b5132
RH		 223
224#define Sw OP_SEG, w_mode
c608c12e 225#define Ap OP_DIR, 0
252b5132 226#define Ob OP_OFF, b_mode
52b15da3 227#define Ob64 OP_OFF64, b_mode
252b5132 228#define Ov OP_OFF, v_mode
52b15da3 229#define Ov64 OP_OFF64, v_mode
252b5132
RH		 230#define Xb OP_DSreg, eSI_reg
231#define Xv OP_DSreg, eSI_reg
232#define Yb OP_ESreg, eDI_reg
233#define Yv OP_ESreg, eDI_reg
234#define DSBX OP_DSreg, eBX_reg
235
236#define es OP_REG, es_reg
237#define ss OP_REG, ss_reg
238#define cs OP_REG, cs_reg
239#define ds OP_REG, ds_reg
240#define fs OP_REG, fs_reg
241#define gs OP_REG, gs_reg
242
243#define MX OP_MMX, 0
c608c12e 244#define XM OP_XMM, 0
252b5132 245#define EM OP_EM, v_mode
c608c12e 246#define EX OP_EX, v_mode
2da11e11 247#define MS OP_MS, v_mode
c608c12e 248#define None OP_E, 0
252b5132 249#define OPSUF OP_3DNowSuffix, 0
c608c12e 250#define OPSIMD OP_SIMD_Suffix, 0
252b5132
RH		 251
252/* bits in sizeflag */
253#if 0 /* leave undefined until someone adds the extra flag to objdump */
254#define SUFFIX_ALWAYS 4
255#endif
256#define AFLAG 2
257#define DFLAG 1
258
2da11e11 259typedef void (*op_rtn) PARAMS ((int bytemode, int sizeflag));
252b5132
RH		 260
261static void OP_E PARAMS ((int, int));
262static void OP_G PARAMS ((int, int));
263static void OP_I PARAMS ((int, int));
52b15da3
JH		 264static void OP_I64 PARAMS ((int, int));
265static void OP_OFF PARAMS ((int, int));
266static void OP_REG PARAMS ((int, int));
267static void OP_IMREG PARAMS ((int, int));
268static void OP_OFF64 PARAMS ((int, int));
252b5132
RH		 269static void OP_indirE PARAMS ((int, int));
270static void OP_sI PARAMS ((int, int));
271static void OP_REG PARAMS ((int, int));
272static void OP_J PARAMS ((int, int));
273static void OP_DIR PARAMS ((int, int));
274static void OP_OFF PARAMS ((int, int));
275static void OP_ESreg PARAMS ((int, int));
276static void OP_DSreg PARAMS ((int, int));
277static void OP_SEG PARAMS ((int, int));
278static void OP_C PARAMS ((int, int));
279static void OP_D PARAMS ((int, int));
280static void OP_T PARAMS ((int, int));
2da11e11 281static void OP_Rd PARAMS ((int, int));
252b5132
RH		 282static void OP_ST PARAMS ((int, int));
283static void OP_STi PARAMS ((int, int));
252b5132 284static void OP_MMX PARAMS ((int, int));
c608c12e 285static void OP_XMM PARAMS ((int, int));
252b5132 286static void OP_EM PARAMS ((int, int));
c608c12e 287static void OP_EX PARAMS ((int, int));
252b5132
RH		 288static void OP_MS PARAMS ((int, int));
289static void OP_3DNowSuffix PARAMS ((int, int));
c608c12e
AM		 290static void OP_SIMD_Suffix PARAMS ((int, int));
291static void SIMD_Fixup PARAMS ((int, int));
252b5132
RH		 292
293static void append_seg PARAMS ((void));
52b15da3 294static void set_op PARAMS ((unsigned int op, int));
2da11e11 295static void putop PARAMS ((const char *template, int sizeflag));
252b5132
RH		 296static void dofloat PARAMS ((int sizeflag));
297static int get16 PARAMS ((void));
52b15da3
JH		 298static bfd_vma get64 PARAMS ((void));
299static bfd_signed_vma get32 PARAMS ((void));
300static bfd_signed_vma get32s PARAMS ((void));
252b5132 301static void ckprefix PARAMS ((void));
7d421014 302static const char *prefix_name PARAMS ((int, int));
252b5132 303static void ptr_reg PARAMS ((int, int));
2da11e11 304static void BadOp PARAMS ((void));
252b5132 305
52b15da3
JH		 306#define b_mode 1 /* byte operand */
307#define v_mode 2 /* operand size depends on prefixes */
308#define w_mode 3 /* word operand */
309#define d_mode 4 /* double word operand */
310#define q_mode 5 /* quad word operand */
311#define x_mode 6
312#define m_mode 7 /* d_mode in 32bit, q_mode in 64bit mode. */
252b5132
RH		 313
314#define es_reg 100
315#define cs_reg 101
316#define ss_reg 102
317#define ds_reg 103
318#define fs_reg 104
319#define gs_reg 105
252b5132 320
c608c12e
AM		 321#define eAX_reg 108
322#define eCX_reg 109
323#define eDX_reg 110
324#define eBX_reg 111
325#define eSP_reg 112
326#define eBP_reg 113
327#define eSI_reg 114
328#define eDI_reg 115
252b5132
RH		 329
330#define al_reg 116
331#define cl_reg 117
332#define dl_reg 118
333#define bl_reg 119
334#define ah_reg 120
335#define ch_reg 121
336#define dh_reg 122
337#define bh_reg 123
338
339#define ax_reg 124
340#define cx_reg 125
341#define dx_reg 126
342#define bx_reg 127
343#define sp_reg 128
344#define bp_reg 129
345#define si_reg 130
346#define di_reg 131
347
52b15da3
JH		 348#define rAX_reg 132
349#define rCX_reg 133
350#define rDX_reg 134
351#define rBX_reg 135
352#define rSP_reg 136
353#define rBP_reg 137
354#define rSI_reg 138
355#define rDI_reg 139
356
252b5132
RH		 357#define indir_dx_reg 150
358
c608c12e
AM		 359#define USE_GROUPS 1
360#define USE_PREFIX_USER_TABLE 2
361
57d91c3c
ILT		 362#define GRP1b NULL, NULL, 0, NULL, USE_GROUPS, NULL, 0
363#define GRP1S NULL, NULL, 1, NULL, USE_GROUPS, NULL, 0
364#define GRP1Ss NULL, NULL, 2, NULL, USE_GROUPS, NULL, 0
365#define GRP2b NULL, NULL, 3, NULL, USE_GROUPS, NULL, 0
366#define GRP2S NULL, NULL, 4, NULL, USE_GROUPS, NULL, 0
367#define GRP2b_one NULL, NULL, 5, NULL, USE_GROUPS, NULL, 0
368#define GRP2S_one NULL, NULL, 6, NULL, USE_GROUPS, NULL, 0
369#define GRP2b_cl NULL, NULL, 7, NULL, USE_GROUPS, NULL, 0
370#define GRP2S_cl NULL, NULL, 8, NULL, USE_GROUPS, NULL, 0
371#define GRP3b NULL, NULL, 9, NULL, USE_GROUPS, NULL, 0
372#define GRP3S NULL, NULL, 10, NULL, USE_GROUPS, NULL, 0
373#define GRP4 NULL, NULL, 11, NULL, USE_GROUPS, NULL, 0
374#define GRP5 NULL, NULL, 12, NULL, USE_GROUPS, NULL, 0
375#define GRP6 NULL, NULL, 13, NULL, USE_GROUPS, NULL, 0
376#define GRP7 NULL, NULL, 14, NULL, USE_GROUPS, NULL, 0
377#define GRP8 NULL, NULL, 15, NULL, USE_GROUPS, NULL, 0
378#define GRP9 NULL, NULL, 16, NULL, USE_GROUPS, NULL, 0
379#define GRP10 NULL, NULL, 17, NULL, USE_GROUPS, NULL, 0
380#define GRP11 NULL, NULL, 18, NULL, USE_GROUPS, NULL, 0
381#define GRP12 NULL, NULL, 19, NULL, USE_GROUPS, NULL, 0
382#define GRP13 NULL, NULL, 20, NULL, USE_GROUPS, NULL, 0
383#define GRP14 NULL, NULL, 21, NULL, USE_GROUPS, NULL, 0
384#define GRPAMD NULL, NULL, 22, NULL, USE_GROUPS, NULL, 0
385
386#define PREGRP0 NULL, NULL, 0, NULL, USE_PREFIX_USER_TABLE, NULL, 0
387#define PREGRP1 NULL, NULL, 1, NULL, USE_PREFIX_USER_TABLE, NULL, 0
388#define PREGRP2 NULL, NULL, 2, NULL, USE_PREFIX_USER_TABLE, NULL, 0
389#define PREGRP3 NULL, NULL, 3, NULL, USE_PREFIX_USER_TABLE, NULL, 0
390#define PREGRP4 NULL, NULL, 4, NULL, USE_PREFIX_USER_TABLE, NULL, 0
391#define PREGRP5 NULL, NULL, 5, NULL, USE_PREFIX_USER_TABLE, NULL, 0
392#define PREGRP6 NULL, NULL, 6, NULL, USE_PREFIX_USER_TABLE, NULL, 0
393#define PREGRP7 NULL, NULL, 7, NULL, USE_PREFIX_USER_TABLE, NULL, 0
394#define PREGRP8 NULL, NULL, 8, NULL, USE_PREFIX_USER_TABLE, NULL, 0
395#define PREGRP9 NULL, NULL, 9, NULL, USE_PREFIX_USER_TABLE, NULL, 0
396#define PREGRP10 NULL, NULL, 10, NULL, USE_PREFIX_USER_TABLE, NULL, 0
397#define PREGRP11 NULL, NULL, 11, NULL, USE_PREFIX_USER_TABLE, NULL, 0
398#define PREGRP12 NULL, NULL, 12, NULL, USE_PREFIX_USER_TABLE, NULL, 0
399#define PREGRP13 NULL, NULL, 13, NULL, USE_PREFIX_USER_TABLE, NULL, 0
400#define PREGRP14 NULL, NULL, 14, NULL, USE_PREFIX_USER_TABLE, NULL, 0
252b5132
RH		 401
402#define FLOATCODE 50
57d91c3c 403#define FLOAT NULL, NULL, FLOATCODE, NULL, 0, NULL, 0
252b5132
RH		 404
405struct dis386 {
2da11e11 406 const char *name;
252b5132
RH		 407 op_rtn op1;
408 int bytemode1;
409 op_rtn op2;
410 int bytemode2;
411 op_rtn op3;
412 int bytemode3;
413};
414
415/* Upper case letters in the instruction names here are macros.
416 'A' => print 'b' if no register operands or suffix_always is true
417 'B' => print 'b' if suffix_always is true
418 'E' => print 'e' if 32-bit form of jcxz
419 'L' => print 'l' if suffix_always is true
420 'N' => print 'n' if instruction has no wait "prefix"
52b15da3
JH		 421 'O' => print 'd', or 'o'
422 'P' => print 'w', 'l' or 'q' if instruction has an operand size prefix,
252b5132 423 or suffix_always is true
52b15da3
JH		 424 print 'q' if rex prefix is present.
425 'I' => print 'q' in 64bit mode and behave as 'P' otherwise
426 'Q' => print 'w', 'l' or 'q' if no register operands or suffix_always is true
427 'R' => print 'w', 'l' or 'q' ("wd" or "dq" in intel mode)
428 'S' => print 'w', 'l' or 'q' if suffix_always is true
10084519 429 'W' => print 'b' or 'w' ("w" or "de" in intel mode)
252b5132
RH		 430*/
431
2da11e11 432static const struct dis386 dis386_att[] = {
252b5132 433 /* 00 */
57d91c3c
ILT		 434 { "addB", Eb, Gb, XX },
435 { "addS", Ev, Gv, XX },
436 { "addB", Gb, Eb, XX },
437 { "addS", Gv, Ev, XX },
438 { "addB", AL, Ib, XX },
439 { "addS", eAX, Iv, XX },
52b15da3
JH		 440 { "pushI", es, XX, XX },
441 { "popI", es, XX, XX },
252b5132 442 /* 08 */
57d91c3c
ILT		 443 { "orB", Eb, Gb, XX },
444 { "orS", Ev, Gv, XX },
445 { "orB", Gb, Eb, XX },
446 { "orS", Gv, Ev, XX },
447 { "orB", AL, Ib, XX },
448 { "orS", eAX, Iv, XX },
52b15da3 449 { "pushI", cs, XX, XX },
57d91c3c 450 { "(bad)", XX, XX, XX }, /* 0x0f extended opcode escape */
252b5132 451 /* 10 */
57d91c3c
ILT		 452 { "adcB", Eb, Gb, XX },
453 { "adcS", Ev, Gv, XX },
454 { "adcB", Gb, Eb, XX },
455 { "adcS", Gv, Ev, XX },
456 { "adcB", AL, Ib, XX },
457 { "adcS", eAX, Iv, XX },
52b15da3
JH		 458 { "pushI", ss, XX, XX },
459 { "popI", ss, XX, XX },
252b5132 460 /* 18 */
57d91c3c
ILT		 461 { "sbbB", Eb, Gb, XX },
462 { "sbbS", Ev, Gv, XX },
463 { "sbbB", Gb, Eb, XX },
464 { "sbbS", Gv, Ev, XX },
465 { "sbbB", AL, Ib, XX },
466 { "sbbS", eAX, Iv, XX },
52b15da3
JH		 467 { "pushI", ds, XX, XX },
468 { "popI", ds, XX, XX },
252b5132 469 /* 20 */
57d91c3c
ILT		 470 { "andB", Eb, Gb, XX },
471 { "andS", Ev, Gv, XX },
472 { "andB", Gb, Eb, XX },
473 { "andS", Gv, Ev, XX },
474 { "andB", AL, Ib, XX },
475 { "andS", eAX, Iv, XX },
476 { "(bad)", XX, XX, XX }, /* SEG ES prefix */
477 { "daa", XX, XX, XX },
252b5132 478 /* 28 */
57d91c3c
ILT		 479 { "subB", Eb, Gb, XX },
480 { "subS", Ev, Gv, XX },
481 { "subB", Gb, Eb, XX },
482 { "subS", Gv, Ev, XX },
483 { "subB", AL, Ib, XX },
484 { "subS", eAX, Iv, XX },
485 { "(bad)", XX, XX, XX }, /* SEG CS prefix */
486 { "das", XX, XX, XX },
252b5132 487 /* 30 */
57d91c3c
ILT		 488 { "xorB", Eb, Gb, XX },
489 { "xorS", Ev, Gv, XX },
490 { "xorB", Gb, Eb, XX },
491 { "xorS", Gv, Ev, XX },
492 { "xorB", AL, Ib, XX },
493 { "xorS", eAX, Iv, XX },
494 { "(bad)", XX, XX, XX }, /* SEG SS prefix */
495 { "aaa", XX, XX, XX },
252b5132 496 /* 38 */
57d91c3c
ILT		 497 { "cmpB", Eb, Gb, XX },
498 { "cmpS", Ev, Gv, XX },
499 { "cmpB", Gb, Eb, XX },
500 { "cmpS", Gv, Ev, XX },
501 { "cmpB", AL, Ib, XX },
502 { "cmpS", eAX, Iv, XX },
503 { "(bad)", XX, XX, XX }, /* SEG DS prefix */
504 { "aas", XX, XX, XX },
252b5132 505 /* 40 */
52b15da3
JH		 506 { "incS", RMeAX, XX, XX },
507 { "incS", RMeCX, XX, XX },
508 { "incS", RMeDX, XX, XX },
509 { "incS", RMeBX, XX, XX },
510 { "incS", RMeSP, XX, XX },
511 { "incS", RMeBP, XX, XX },
512 { "incS", RMeSI, XX, XX },
513 { "incS", RMeDI, XX, XX },
252b5132 514 /* 48 */
52b15da3
JH		 515 { "decS", RMeAX, XX, XX },
516 { "decS", RMeCX, XX, XX },
517 { "decS", RMeDX, XX, XX },
518 { "decS", RMeBX, XX, XX },
519 { "decS", RMeSP, XX, XX },
520 { "decS", RMeBP, XX, XX },
521 { "decS", RMeSI, XX, XX },
522 { "decS", RMeDI, XX, XX },
252b5132 523 /* 50 */
52b15da3
JH		 524 { "pushS", RMeAX, XX, XX },
525 { "pushS", RMeCX, XX, XX },
526 { "pushS", RMeDX, XX, XX },
527 { "pushS", RMeBX, XX, XX },
528 { "pushS", RMeSP, XX, XX },
529 { "pushS", RMeBP, XX, XX },
530 { "pushS", RMeSI, XX, XX },
531 { "pushS", RMeDI, XX, XX },
252b5132 532 /* 58 */
52b15da3
JH		 533 { "popS", RMeAX, XX, XX },
534 { "popS", RMeCX, XX, XX },
535 { "popS", RMeDX, XX, XX },
536 { "popS", RMeBX, XX, XX },
537 { "popS", RMeSP, XX, XX },
538 { "popS", RMeBP, XX, XX },
539 { "popS", RMeSI, XX, XX },
540 { "popS", RMeDI, XX, XX },
252b5132 541 /* 60 */
57d91c3c
ILT		 542 { "pushaP", XX, XX, XX },
543 { "popaP", XX, XX, XX },
544 { "boundS", Gv, Ma, XX },
545 { "arpl", Ew, Gw, XX },
546 { "(bad)", XX, XX, XX }, /* seg fs */
547 { "(bad)", XX, XX, XX }, /* seg gs */
548 { "(bad)", XX, XX, XX }, /* op size prefix */
549 { "(bad)", XX, XX, XX }, /* adr size prefix */
252b5132 550 /* 68 */
52b15da3 551 { "pushI", Iv, XX, XX }, /* 386 book wrong */
252b5132 552 { "imulS", Gv, Ev, Iv },
52b15da3 553 { "pushI", sIb, XX, XX }, /* push of byte really pushes 2 or 4 bytes */
252b5132 554 { "imulS", Gv, Ev, sIb },
57d91c3c
ILT		 555 { "insb", Yb, indirDX, XX },
556 { "insR", Yv, indirDX, XX },
557 { "outsb", indirDX, Xb, XX },
558 { "outsR", indirDX, Xv, XX },
252b5132 559 /* 70 */
57d91c3c
ILT		 560 { "jo", Jb, XX, XX },
561 { "jno", Jb, XX, XX },
562 { "jb", Jb, XX, XX },
563 { "jae", Jb, XX, XX },
564 { "je", Jb, XX, XX },
565 { "jne", Jb, XX, XX },
566 { "jbe", Jb, XX, XX },
567 { "ja", Jb, XX, XX },
252b5132 568 /* 78 */
57d91c3c
ILT		 569 { "js", Jb, XX, XX },
570 { "jns", Jb, XX, XX },
571 { "jp", Jb, XX, XX },
572 { "jnp", Jb, XX, XX },
573 { "jl", Jb, XX, XX },
574 { "jge", Jb, XX, XX },
575 { "jle", Jb, XX, XX },
576 { "jg", Jb, XX, XX },
252b5132
RH		 577 /* 80 */
578 { GRP1b },
579 { GRP1S },
57d91c3c 580 { "(bad)", XX, XX, XX },
252b5132 581 { GRP1Ss },
57d91c3c
ILT		 582 { "testB", Eb, Gb, XX },
583 { "testS", Ev, Gv, XX },
584 { "xchgB", Eb, Gb, XX },
585 { "xchgS", Ev, Gv, XX },
252b5132 586 /* 88 */
57d91c3c
ILT		 587 { "movB", Eb, Gb, XX },
588 { "movS", Ev, Gv, XX },
589 { "movB", Gb, Eb, XX },
590 { "movS", Gv, Ev, XX },
591 { "movQ", Ev, Sw, XX },
592 { "leaS", Gv, M, XX },
593 { "movQ", Sw, Ev, XX },
594 { "popQ", Ev, XX, XX },
252b5132 595 /* 90 */
57d91c3c 596 { "nop", XX, XX, XX },
52b15da3
JH		 597 { "xchgS", RMeCX, eAX, XX },
598 { "xchgS", RMeDX, eAX, XX },
599 { "xchgS", RMeBX, eAX, XX },
600 { "xchgS", RMeSP, eAX, XX },
601 { "xchgS", RMeBP, eAX, XX },
602 { "xchgS", RMeSI, eAX, XX },
603 { "xchgS", RMeDI, eAX, XX },
252b5132 604 /* 98 */
57d91c3c 605 { "cWtR", XX, XX, XX },
52b15da3
JH		 606 { "cRtO", XX, XX, XX },
607 { "lcallI", Ap, XX, XX },
57d91c3c 608 { "(bad)", XX, XX, XX }, /* fwait */
52b15da3
JH		 609 { "pushfI", XX, XX, XX },
610 { "popfI", XX, XX, XX },
57d91c3c
ILT		 611 { "sahf", XX, XX, XX },
612 { "lahf", XX, XX, XX },
252b5132 613 /* a0 */
57d91c3c
ILT		 614 { "movB", AL, Ob, XX },
615 { "movS", eAX, Ov, XX },
616 { "movB", Ob, AL, XX },
617 { "movS", Ov, eAX, XX },
618 { "movsb", Yb, Xb, XX },
619 { "movsR", Yv, Xv, XX },
620 { "cmpsb", Xb, Yb, XX },
621 { "cmpsR", Xv, Yv, XX },
252b5132 622 /* a8 */
57d91c3c
ILT		 623 { "testB", AL, Ib, XX },
624 { "testS", eAX, Iv, XX },
625 { "stosB", Yb, AL, XX },
626 { "stosS", Yv, eAX, XX },
627 { "lodsB", AL, Xb, XX },
628 { "lodsS", eAX, Xv, XX },
629 { "scasB", AL, Yb, XX },
630 { "scasS", eAX, Yv, XX },
252b5132 631 /* b0 */
52b15da3
JH		 632 { "movB", RMAL, Ib, XX },
633 { "movB", RMCL, Ib, XX },
634 { "movB", RMDL, Ib, XX },
635 { "movB", RMBL, Ib, XX },
636 { "movB", RMAH, Ib, XX },
637 { "movB", RMCH, Ib, XX },
638 { "movB", RMDH, Ib, XX },
639 { "movB", RMBH, Ib, XX },
252b5132 640 /* b8 */
52b15da3
JH		 641 { "movS", RMeAX, Iv, XX },
642 { "movS", RMeCX, Iv, XX },
643 { "movS", RMeDX, Iv, XX },
644 { "movS", RMeBX, Iv, XX },
645 { "movS", RMeSP, Iv, XX },
646 { "movS", RMeBP, Iv, XX },
647 { "movS", RMeSI, Iv, XX },
648 { "movS", RMeDI, Iv, XX },
252b5132
RH		 649 /* c0 */
650 { GRP2b },
651 { GRP2S },
57d91c3c
ILT		 652 { "retP", Iw, XX, XX },
653 { "retP", XX, XX, XX },
654 { "lesS", Gv, Mp, XX },
655 { "ldsS", Gv, Mp, XX },
656 { "movA", Eb, Ib, XX },
657 { "movQ", Ev, Iv, XX },
252b5132 658 /* c8 */
52b15da3
JH		 659 { "enterI", Iw, Ib, XX },
660 { "leaveI", XX, XX, XX },
661 { "lretI", Iw, XX, XX },
662 { "lretI", XX, XX, XX },
663 { "int3", XX, XX, XX },
664 { "int", Ib, XX, XX },
665 { "into", XX, XX, XX},
666 { "iretI", XX, XX, XX },
667 /* d0 */
668 { GRP2b_one },
669 { GRP2S_one },
670 { GRP2b_cl },
671 { GRP2S_cl },
672 { "aam", sIb, XX, XX },
673 { "aad", sIb, XX, XX },
674 { "(bad)", XX, XX, XX },
675 { "xlat", DSBX, XX, XX },
676 /* d8 */
677 { FLOAT },
678 { FLOAT },
679 { FLOAT },
680 { FLOAT },
681 { FLOAT },
682 { FLOAT },
683 { FLOAT },
684 { FLOAT },
685 /* e0 */
686 { "loopne", Jb, XX, XX },
687 { "loope", Jb, XX, XX },
688 { "loop", Jb, XX, XX },
689 { "jEcxz", Jb, XX, XX },
690 { "inB", AL, Ib, XX },
691 { "inS", eAX, Ib, XX },
692 { "outB", Ib, AL, XX },
693 { "outS", Ib, eAX, XX },
694 /* e8 */
695 { "callI", Jv, XX, XX },
696 { "jmpI", Jv, XX, XX },
697 { "ljmpI", Ap, XX, XX },
698 { "jmp", Jb, XX, XX },
699 { "inB", AL, indirDX, XX },
700 { "inS", eAX, indirDX, XX },
701 { "outB", indirDX, AL, XX },
702 { "outS", indirDX, eAX, XX },
703 /* f0 */
704 { "(bad)", XX, XX, XX }, /* lock prefix */
705 { "(bad)", XX, XX, XX },
706 { "(bad)", XX, XX, XX }, /* repne */
707 { "(bad)", XX, XX, XX }, /* repz */
708 { "hlt", XX, XX, XX },
709 { "cmc", XX, XX, XX },
710 { GRP3b },
711 { GRP3S },
712 /* f8 */
713 { "clc", XX, XX, XX },
714 { "stc", XX, XX, XX },
715 { "cli", XX, XX, XX },
716 { "sti", XX, XX, XX },
717 { "cld", XX, XX, XX },
718 { "std", XX, XX, XX },
719 { GRP4 },
720 { GRP5 },
721};
722
723static const struct dis386 dis386_intel[] = {
724 /* 00 */
725 { "add", Eb, Gb, XX },
726 { "add", Ev, Gv, XX },
727 { "add", Gb, Eb, XX },
728 { "add", Gv, Ev, XX },
729 { "add", AL, Ib, XX },
730 { "add", eAX, Iv, XX },
731 { "push", es, XX, XX },
732 { "pop", es, XX, XX },
733 /* 08 */
734 { "or", Eb, Gb, XX },
735 { "or", Ev, Gv, XX },
736 { "or", Gb, Eb, XX },
737 { "or", Gv, Ev, XX },
738 { "or", AL, Ib, XX },
739 { "or", eAX, Iv, XX },
740 { "push", cs, XX, XX },
741 { "(bad)", XX, XX, XX }, /* 0x0f extended opcode escape */
742 /* 10 */
743 { "adc", Eb, Gb, XX },
744 { "adc", Ev, Gv, XX },
745 { "adc", Gb, Eb, XX },
746 { "adc", Gv, Ev, XX },
747 { "adc", AL, Ib, XX },
748 { "adc", eAX, Iv, XX },
749 { "push", ss, XX, XX },
750 { "pop", ss, XX, XX },
751 /* 18 */
752 { "sbb", Eb, Gb, XX },
753 { "sbb", Ev, Gv, XX },
754 { "sbb", Gb, Eb, XX },
755 { "sbb", Gv, Ev, XX },
756 { "sbb", AL, Ib, XX },
757 { "sbb", eAX, Iv, XX },
758 { "push", ds, XX, XX },
759 { "pop", ds, XX, XX },
760 /* 20 */
761 { "and", Eb, Gb, XX },
762 { "and", Ev, Gv, XX },
763 { "and", Gb, Eb, XX },
764 { "and", Gv, Ev, XX },
765 { "and", AL, Ib, XX },
766 { "and", eAX, Iv, XX },
767 { "(bad)", XX, XX, XX }, /* SEG ES prefix */
768 { "daa", XX, XX, XX },
769 /* 28 */
770 { "sub", Eb, Gb, XX },
771 { "sub", Ev, Gv, XX },
772 { "sub", Gb, Eb, XX },
773 { "sub", Gv, Ev, XX },
774 { "sub", AL, Ib, XX },
775 { "sub", eAX, Iv, XX },
776 { "(bad)", XX, XX, XX }, /* SEG CS prefix */
777 { "das", XX, XX, XX },
778 /* 30 */
779 { "xor", Eb, Gb, XX },
780 { "xor", Ev, Gv, XX },
781 { "xor", Gb, Eb, XX },
782 { "xor", Gv, Ev, XX },
783 { "xor", AL, Ib, XX },
784 { "xor", eAX, Iv, XX },
785 { "(bad)", XX, XX, XX }, /* SEG SS prefix */
786 { "aaa", XX, XX, XX },
787 /* 38 */
788 { "cmp", Eb, Gb, XX },
789 { "cmp", Ev, Gv, XX },
790 { "cmp", Gb, Eb, XX },
791 { "cmp", Gv, Ev, XX },
792 { "cmp", AL, Ib, XX },
793 { "cmp", eAX, Iv, XX },
794 { "(bad)", XX, XX, XX }, /* SEG DS prefix */
795 { "aas", XX, XX, XX },
796 /* 40 */
797 { "inc", RMeAX, XX, XX },
798 { "inc", RMeCX, XX, XX },
799 { "inc", RMeDX, XX, XX },
800 { "inc", RMeBX, XX, XX },
801 { "inc", RMeSP, XX, XX },
802 { "inc", RMeBP, XX, XX },
803 { "inc", RMeSI, XX, XX },
804 { "inc", RMeDI, XX, XX },
805 /* 48 */
806 { "dec", RMeAX, XX, XX },
807 { "dec", RMeCX, XX, XX },
808 { "dec", RMeDX, XX, XX },
809 { "dec", RMeBX, XX, XX },
810 { "dec", RMeSP, XX, XX },
811 { "dec", RMeBP, XX, XX },
812 { "dec", RMeSI, XX, XX },
813 { "dec", RMeDI, XX, XX },
814 /* 50 */
815 { "push", RMeAX, XX, XX },
816 { "push", RMeCX, XX, XX },
817 { "push", RMeDX, XX, XX },
818 { "push", RMeBX, XX, XX },
819 { "push", RMeSP, XX, XX },
820 { "push", RMeBP, XX, XX },
821 { "push", RMeSI, XX, XX },
822 { "push", RMeDI, XX, XX },
823 /* 58 */
824 { "pop", RMeAX, XX, XX },
825 { "pop", RMeCX, XX, XX },
826 { "pop", RMeDX, XX, XX },
827 { "pop", RMeBX, XX, XX },
828 { "pop", RMeSP, XX, XX },
829 { "pop", RMeBP, XX, XX },
830 { "pop", RMeSI, XX, XX },
831 { "pop", RMeDI, XX, XX },
832 /* 60 */
833 { "pusha", XX, XX, XX },
834 { "popa", XX, XX, XX },
835 { "bound", Gv, Ma, XX },
836 { "arpl", Ew, Gw, XX },
837 { "(bad)", XX, XX, XX }, /* seg fs */
838 { "(bad)", XX, XX, XX }, /* seg gs */
839 { "(bad)", XX, XX, XX }, /* op size prefix */
840 { "(bad)", XX, XX, XX }, /* adr size prefix */
841 /* 68 */
842 { "push", Iv, XX, XX }, /* 386 book wrong */
843 { "imul", Gv, Ev, Iv },
844 { "push", sIb, XX, XX }, /* push of byte really pushes 2 or 4 bytes */
845 { "imul", Gv, Ev, sIb },
846 { "ins", Yb, indirDX, XX },
847 { "ins", Yv, indirDX, XX },
848 { "outs", indirDX, Xb, XX },
849 { "outs", indirDX, Xv, XX },
850 /* 70 */
851 { "jo", Jb, XX, XX },
852 { "jno", Jb, XX, XX },
853 { "jb", Jb, XX, XX },
854 { "jae", Jb, XX, XX },
855 { "je", Jb, XX, XX },
856 { "jne", Jb, XX, XX },
857 { "jbe", Jb, XX, XX },
858 { "ja", Jb, XX, XX },
859 /* 78 */
860 { "js", Jb, XX, XX },
861 { "jns", Jb, XX, XX },
862 { "jp", Jb, XX, XX },
863 { "jnp", Jb, XX, XX },
864 { "jl", Jb, XX, XX },
865 { "jge", Jb, XX, XX },
866 { "jle", Jb, XX, XX },
867 { "jg", Jb, XX, XX },
868 /* 80 */
869 { GRP1b },
870 { GRP1S },
871 { "(bad)", XX, XX, XX },
872 { GRP1Ss },
873 { "test", Eb, Gb, XX },
874 { "test", Ev, Gv, XX },
875 { "xchg", Eb, Gb, XX },
876 { "xchg", Ev, Gv, XX },
877 /* 88 */
878 { "mov", Eb, Gb, XX },
879 { "mov", Ev, Gv, XX },
880 { "mov", Gb, Eb, XX },
881 { "mov", Gv, Ev, XX },
882 { "mov", Ev, Sw, XX },
883 { "lea", Gv, M, XX },
884 { "mov", Sw, Ev, XX },
885 { "pop", Ev, XX, XX },
886 /* 90 */
887 { "nop", XX, XX, XX },
888 { "xchg", RMeCX, eAX, XX },
889 { "xchg", RMeDX, eAX, XX },
890 { "xchg", RMeBX, eAX, XX },
891 { "xchg", RMeSP, eAX, XX },
892 { "xchg", RMeBP, eAX, XX },
893 { "xchg", RMeSI, eAX, XX },
894 { "xchg", RMeDI, eAX, XX },
895 /* 98 */
896 { "cW", XX, XX, XX }, /* cwde and cbw */
897 { "cR", XX, XX, XX }, /* cdq and cwd */
898 { "lcall", Ap, XX, XX },
899 { "(bad)", XX, XX, XX }, /* fwait */
900 { "pushf", XX, XX, XX },
901 { "popf", XX, XX, XX },
902 { "sahf", XX, XX, XX },
903 { "lahf", XX, XX, XX },
904 /* a0 */
905 { "mov", AL, Ob, XX },
906 { "mov", eAX, Ov, XX },
907 { "mov", Ob, AL, XX },
908 { "mov", Ov, eAX, XX },
909 { "movs", Yb, Xb, XX },
910 { "movs", Yv, Xv, XX },
911 { "cmps", Xb, Yb, XX },
912 { "cmps", Xv, Yv, XX },
913 /* a8 */
914 { "test", AL, Ib, XX },
915 { "test", eAX, Iv, XX },
916 { "stos", Yb, AL, XX },
917 { "stos", Yv, eAX, XX },
918 { "lods", AL, Xb, XX },
919 { "lods", eAX, Xv, XX },
920 { "scas", AL, Yb, XX },
921 { "scas", eAX, Yv, XX },
922 /* b0 */
923 { "mov", RMAL, Ib, XX },
924 { "mov", RMCL, Ib, XX },
925 { "mov", RMDL, Ib, XX },
926 { "mov", RMBL, Ib, XX },
927 { "mov", RMAH, Ib, XX },
928 { "mov", RMCH, Ib, XX },
929 { "mov", RMDH, Ib, XX },
930 { "mov", RMBH, Ib, XX },
931 /* b8 */
932 { "mov", RMeAX, Iv, XX },
933 { "mov", RMeCX, Iv, XX },
934 { "mov", RMeDX, Iv, XX },
935 { "mov", RMeBX, Iv, XX },
936 { "mov", RMeSP, Iv, XX },
937 { "mov", RMeBP, Iv, XX },
938 { "mov", RMeSI, Iv, XX },
939 { "mov", RMeDI, Iv, XX },
940 /* c0 */
941 { GRP2b },
942 { GRP2S },
943 { "ret", Iw, XX, XX },
944 { "ret", XX, XX, XX },
945 { "les", Gv, Mp, XX },
946 { "lds", Gv, Mp, XX },
947 { "mov", Eb, Ib, XX },
948 { "mov", Ev, Iv, XX },
949 /* c8 */
950 { "enter", Iw, Ib, XX },
951 { "leave", XX, XX, XX },
952 { "lret", Iw, XX, XX },
953 { "lret", XX, XX, XX },
954 { "int3", XX, XX, XX },
955 { "int", Ib, XX, XX },
956 { "into", XX, XX, XX },
957 { "iret", XX, XX, XX },
958 /* d0 */
959 { GRP2b_one },
960 { GRP2S_one },
961 { GRP2b_cl },
962 { GRP2S_cl },
963 { "aam", sIb, XX, XX },
964 { "aad", sIb, XX, XX },
965 { "(bad)", XX, XX, XX },
966 { "xlat", DSBX, XX, XX },
967 /* d8 */
968 { FLOAT },
969 { FLOAT },
970 { FLOAT },
971 { FLOAT },
972 { FLOAT },
973 { FLOAT },
974 { FLOAT },
975 { FLOAT },
976 /* e0 */
977 { "loopne", Jb, XX, XX },
978 { "loope", Jb, XX, XX },
979 { "loop", Jb, XX, XX },
980 { "jEcxz", Jb, XX, XX },
981 { "in", AL, Ib, XX },
982 { "in", eAX, Ib, XX },
983 { "out", Ib, AL, XX },
984 { "out", Ib, eAX, XX },
985 /* e8 */
986 { "call", Jv, XX, XX },
987 { "jmp", Jv, XX, XX },
988 { "ljmp", Ap, XX, XX },
989 { "jmp", Jb, XX, XX },
990 { "in", AL, indirDX, XX },
991 { "in", eAX, indirDX, XX },
992 { "out", indirDX, AL, XX },
993 { "out", indirDX, eAX, XX },
994 /* f0 */
995 { "(bad)", XX, XX, XX }, /* lock prefix */
996 { "(bad)", XX, XX, XX },
997 { "(bad)", XX, XX, XX }, /* repne */
998 { "(bad)", XX, XX, XX }, /* repz */
999 { "hlt", XX, XX, XX },
1000 { "cmc", XX, XX, XX },
1001 { GRP3b },
1002 { GRP3S },
1003 /* f8 */
1004 { "clc", XX, XX, XX },
1005 { "stc", XX, XX, XX },
1006 { "cli", XX, XX, XX },
1007 { "sti", XX, XX, XX },
1008 { "cld", XX, XX, XX },
1009 { "std", XX, XX, XX },
1010 { GRP4 },
1011 { GRP5 },
1012};
1013
1014/* 64bit mode is having some instruction set differences, so separate table is
1015 needed. */
1016static const struct dis386 disx86_64_att[] = {
1017 /* 00 */
1018 { "addB", Eb, Gb, XX },
1019 { "addS", Ev, Gv, XX },
1020 { "addB", Gb, Eb, XX },
1021 { "addS", Gv, Ev, XX },
1022 { "addB", AL, Ib, XX },
1023 { "addS", eAX, Iv, XX },
1024 { "(bad)", XX, XX, XX }, /* Reserved. */
1025 { "(bad)", XX, XX, XX }, /* Reserved. */
1026 /* 08 */
1027 { "orB", Eb, Gb, XX },
1028 { "orS", Ev, Gv, XX },
1029 { "orB", Gb, Eb, XX },
1030 { "orS", Gv, Ev, XX },
1031 { "orB", AL, Ib, XX },
1032 { "orS", eAX, Iv, XX },
1033 { "(bad)", XX, XX, XX }, /* Reserved. */
1034 { "(bad)", XX, XX, XX }, /* 0x0f extended opcode escape */
1035 /* 10 */
1036 { "adcB", Eb, Gb, XX },
1037 { "adcS", Ev, Gv, XX },
1038 { "adcB", Gb, Eb, XX },
1039 { "adcS", Gv, Ev, XX },
1040 { "adcB", AL, Ib, XX },
1041 { "adcS", eAX, Iv, XX },
1042 { "(bad)", XX, XX, XX }, /* Reserved. */
1043 { "(bad)", XX, XX, XX }, /* Reserved. */
1044 /* 18 */
1045 { "sbbB", Eb, Gb, XX },
1046 { "sbbS", Ev, Gv, XX },
1047 { "sbbB", Gb, Eb, XX },
1048 { "sbbS", Gv, Ev, XX },
1049 { "sbbB", AL, Ib, XX },
1050 { "sbbS", eAX, Iv, XX },
1051 { "(bad)", XX, XX, XX }, /* Reserved. */
1052 { "(bad)", XX, XX, XX }, /* Reserved. */
1053 /* 20 */
1054 { "andB", Eb, Gb, XX },
1055 { "andS", Ev, Gv, XX },
1056 { "andB", Gb, Eb, XX },
1057 { "andS", Gv, Ev, XX },
1058 { "andB", AL, Ib, XX },
1059 { "andS", eAX, Iv, XX },
1060 { "(bad)", XX, XX, XX }, /* SEG ES prefix */
1061 { "(bad)", XX, XX, XX }, /* Reserved. */
1062 /* 28 */
1063 { "subB", Eb, Gb, XX },
1064 { "subS", Ev, Gv, XX },
1065 { "subB", Gb, Eb, XX },
1066 { "subS", Gv, Ev, XX },
1067 { "subB", AL, Ib, XX },
1068 { "subS", eAX, Iv, XX },
1069 { "(bad)", XX, XX, XX }, /* SEG CS prefix */
1070 { "(bad)", XX, XX, XX }, /* Reserved. */
1071 /* 30 */
1072 { "xorB", Eb, Gb, XX },
1073 { "xorS", Ev, Gv, XX },
1074 { "xorB", Gb, Eb, XX },
1075 { "xorS", Gv, Ev, XX },
1076 { "xorB", AL, Ib, XX },
1077 { "xorS", eAX, Iv, XX },
1078 { "(bad)", XX, XX, XX }, /* SEG SS prefix */
1079 { "(bad)", XX, XX, XX }, /* Reserved. */
1080 /* 38 */
1081 { "cmpB", Eb, Gb, XX },
1082 { "cmpS", Ev, Gv, XX },
1083 { "cmpB", Gb, Eb, XX },
1084 { "cmpS", Gv, Ev, XX },
1085 { "cmpB", AL, Ib, XX },
1086 { "cmpS", eAX, Iv, XX },
1087 { "(bad)", XX, XX, XX }, /* SEG DS prefix */
1088 { "(bad)", XX, XX, XX }, /* Reserved. */
1089 /* 40 */
1090 { "(bad)", XX, XX, XX }, /* REX prefix area. */
1091 { "(bad)", XX, XX, XX },
1092 { "(bad)", XX, XX, XX },
1093 { "(bad)", XX, XX, XX },
1094 { "(bad)", XX, XX, XX },
1095 { "(bad)", XX, XX, XX },
1096 { "(bad)", XX, XX, XX },
1097 { "(bad)", XX, XX, XX },
1098 /* 48 */
1099 { "(bad)", XX, XX, XX },
1100 { "(bad)", XX, XX, XX },
1101 { "(bad)", XX, XX, XX },
1102 { "(bad)", XX, XX, XX },
1103 { "(bad)", XX, XX, XX },
1104 { "(bad)", XX, XX, XX },
1105 { "(bad)", XX, XX, XX },
1106 { "(bad)", XX, XX, XX },
1107 /* 50 */
1108 { "pushI", RMrAX, XX, XX },
1109 { "pushI", RMrCX, XX, XX },
1110 { "pushI", RMrDX, XX, XX },
1111 { "pushI", RMrBX, XX, XX },
1112 { "pushI", RMrSP, XX, XX },
1113 { "pushI", RMrBP, XX, XX },
1114 { "pushI", RMrSI, XX, XX },
1115 { "pushI", RMrDI, XX, XX },
1116 /* 58 */
1117 { "popI", RMrAX, XX, XX },
1118 { "popI", RMrCX, XX, XX },
1119 { "popI", RMrDX, XX, XX },
1120 { "popI", RMrBX, XX, XX },
1121 { "popI", RMrSP, XX, XX },
1122 { "popI", RMrBP, XX, XX },
1123 { "popI", RMrSI, XX, XX },
1124 { "popI", RMrDI, XX, XX },
1125 /* 60 */
1126 { "(bad)", XX, XX, XX }, /* reserved. */
1127 { "(bad)", XX, XX, XX }, /* reserved. */
1128 { "(bad)", XX, XX, XX }, /* reserved. */
1129 { "movslR", Gv, Ed, XX },
1130 { "(bad)", XX, XX, XX }, /* seg fs */
1131 { "(bad)", XX, XX, XX }, /* seg gs */
1132 { "(bad)", XX, XX, XX }, /* op size prefix */
1133 { "(bad)", XX, XX, XX }, /* adr size prefix */
1134 /* 68 */
1135 { "pushI", Iq, XX, XX }, /* 386 book wrong */
1136 { "imulS", Gv, Ev, Iv },
1137 { "pushI", sIb, XX, XX }, /* push of byte really pushes 2 or 4 bytes */
1138 { "imulS", Gv, Ev, sIb },
1139 { "insb", Yb, indirDX, XX },
1140 { "insR", Yv, indirDX, XX },
1141 { "outsb", indirDX, Xb, XX },
1142 { "outsR", indirDX, Xv, XX },
1143 /* 70 */
1144 { "jo", Jb, XX, XX },
1145 { "jno", Jb, XX, XX },
1146 { "jb", Jb, XX, XX },
1147 { "jae", Jb, XX, XX },
1148 { "je", Jb, XX, XX },
1149 { "jne", Jb, XX, XX },
1150 { "jbe", Jb, XX, XX },
1151 { "ja", Jb, XX, XX },
1152 /* 78 */
1153 { "js", Jb, XX, XX },
1154 { "jns", Jb, XX, XX },
1155 { "jp", Jb, XX, XX },
1156 { "jnp", Jb, XX, XX },
1157 { "jl", Jb, XX, XX },
1158 { "jge", Jb, XX, XX },
1159 { "jle", Jb, XX, XX },
1160 { "jg", Jb, XX, XX },
1161 /* 80 */
1162 { GRP1b },
1163 { GRP1S },
1164 { "(bad)", XX, XX, XX },
1165 { GRP1Ss },
1166 { "testB", Eb, Gb, XX },
1167 { "testS", Ev, Gv, XX },
1168 { "xchgB", Eb, Gb, XX },
1169 { "xchgS", Ev, Gv, XX },
1170 /* 88 */
1171 { "movB", Eb, Gb, XX },
1172 { "movS", Ev, Gv, XX },
1173 { "movB", Gb, Eb, XX },
1174 { "movS", Gv, Ev, XX },
1175 { "movQ", Ev, Sw, XX },
1176 { "leaS", Gv, M, XX },
1177 { "movQ", Sw, Ev, XX },
1178 { "popI", Ev, XX, XX },
1179 /* 90 */
1180 { "nop", XX, XX, XX },
1181 { "xchgS", RMeCX, eAX, XX },
1182 { "xchgS", RMeDX, eAX, XX },
1183 { "xchgS", RMeBX, eAX, XX },
1184 { "xchgS", RMeSP, eAX, XX },
1185 { "xchgS", RMeBP, eAX, XX },
1186 { "xchgS", RMeSI, eAX, XX },
1187 { "xchgS", RMeDI, eAX, XX },
1188 /* 98 */
1189 { "cWtR", XX, XX, XX },
1190 { "cRtO", XX, XX, XX },
1191 { "(bad)", XX, XX, XX }, /* reserved. */
1192 { "(bad)", XX, XX, XX }, /* fwait */
1193 { "pushfI", XX, XX, XX },
1194 { "popfI", XX, XX, XX },
1195 { "(bad)", XX, XX, XX }, /* reserved. */
1196 { "(bad)", XX, XX, XX }, /* reserved. */
1197 /* a0 */
1198 { "movB", AL, Ob64, XX },
1199 { "movS", eAX, Ov64, XX },
1200 { "movB", Ob64, AL, XX },
1201 { "movS", Ov64, eAX, XX },
1202 { "movsb", Yb, Xb, XX },
1203 { "movsR", Yv, Xv, XX },
1204 { "cmpsb", Xb, Yb, XX },
1205 { "cmpsR", Xv, Yv, XX },
1206 /* a8 */
1207 { "testB", AL, Ib, XX },
1208 { "testS", eAX, Iv, XX },
1209 { "stosB", Yb, AL, XX },
1210 { "stosS", Yv, eAX, XX },
1211 { "lodsB", AL, Xb, XX },
1212 { "lodsS", eAX, Xv, XX },
1213 { "scasB", AL, Yb, XX },
1214 { "scasS", eAX, Yv, XX },
1215 /* b0 */
1216 { "movB", RMAL, Ib, XX },
1217 { "movB", RMCL, Ib, XX },
1218 { "movB", RMDL, Ib, XX },
1219 { "movB", RMBL, Ib, XX },
1220 { "movB", RMAH, Ib, XX },
1221 { "movB", RMCH, Ib, XX },
1222 { "movB", RMDH, Ib, XX },
1223 { "movB", RMBH, Ib, XX },
1224 /* b8 */
1225 { "movS", RMeAX, Iv64, XX },
1226 { "movS", RMeCX, Iv64, XX },
1227 { "movS", RMeDX, Iv64, XX },
1228 { "movS", RMeBX, Iv64, XX },
1229 { "movS", RMeSP, Iv64, XX },
1230 { "movS", RMeBP, Iv64, XX },
1231 { "movS", RMeSI, Iv64, XX },
1232 { "movS", RMeDI, Iv64, XX },
1233 /* c0 */
1234 { GRP2b },
1235 { GRP2S },
1236 { "retI", Iw, XX, XX },
1237 { "retI", XX, XX, XX },
1238 { "(bad)", XX, XX, XX }, /* reserved. */
1239 { "ldsS", Gv, Mp, XX },
1240 { "movA", Eb, Ib, XX },
1241 { "movQ", Ev, Iv, XX },
1242 /* c8 */
1243 { "enterI", Iw, Ib, XX },
1244 { "leaveI", XX, XX, XX },
1245 { "lretI", Iw, XX, XX },
1246 { "lretI", XX, XX, XX },
57d91c3c
ILT		 1247 { "int3", XX, XX, XX },
1248 { "int", Ib, XX, XX },
52b15da3
JH		 1249 { "(bad)", XX, XX, XX }, /* reserved. */
1250 { "iretI", XX, XX, XX },
252b5132
RH		 1251 /* d0 */
1252 { GRP2b_one },
1253 { GRP2S_one },
1254 { GRP2b_cl },
1255 { GRP2S_cl },
52b15da3
JH		 1256 { "(bad)", XX, XX, XX }, /* reserved. */
1257 { "(bad)", XX, XX, XX }, /* reserved. */
57d91c3c
ILT		 1258 { "(bad)", XX, XX, XX },
1259 { "xlat", DSBX, XX, XX },
252b5132
RH		 1260 /* d8 */
1261 { FLOAT },
1262 { FLOAT },
1263 { FLOAT },
1264 { FLOAT },
1265 { FLOAT },
1266 { FLOAT },
1267 { FLOAT },
1268 { FLOAT },
1269 /* e0 */
57d91c3c
ILT		 1270 { "loopne", Jb, XX, XX },
1271 { "loope", Jb, XX, XX },
1272 { "loop", Jb, XX, XX },
1273 { "jEcxz", Jb, XX, XX },
1274 { "inB", AL, Ib, XX },
1275 { "inS", eAX, Ib, XX },
1276 { "outB", Ib, AL, XX },
1277 { "outS", Ib, eAX, XX },
252b5132 1278 /* e8 */
52b15da3
JH		 1279 { "callI", Jv, XX, XX },
1280 { "jmpI", Jv, XX, XX },
1281 { "(bad)", XX, XX, XX }, /* reserved. */
57d91c3c
ILT		 1282 { "jmp", Jb, XX, XX },
1283 { "inB", AL, indirDX, XX },
1284 { "inS", eAX, indirDX, XX },
1285 { "outB", indirDX, AL, XX },
1286 { "outS", indirDX, eAX, XX },
252b5132 1287 /* f0 */
57d91c3c
ILT		 1288 { "(bad)", XX, XX, XX }, /* lock prefix */
1289 { "(bad)", XX, XX, XX },
1290 { "(bad)", XX, XX, XX }, /* repne */
1291 { "(bad)", XX, XX, XX }, /* repz */
1292 { "hlt", XX, XX, XX },
1293 { "cmc", XX, XX, XX },
252b5132
RH		 1294 { GRP3b },
1295 { GRP3S },
1296 /* f8 */
57d91c3c
ILT		 1297 { "clc", XX, XX, XX },
1298 { "stc", XX, XX, XX },
1299 { "cli", XX, XX, XX },
1300 { "sti", XX, XX, XX },
1301 { "cld", XX, XX, XX },
1302 { "std", XX, XX, XX },
252b5132
RH		 1303 { GRP4 },
1304 { GRP5 },
1305};
1306
52b15da3 1307static const struct dis386 dis386_64_intel[] = {
252b5132 1308 /* 00 */
57d91c3c
ILT		 1309 { "add", Eb, Gb, XX },
1310 { "add", Ev, Gv, XX },
1311 { "add", Gb, Eb, XX },
1312 { "add", Gv, Ev, XX },
1313 { "add", AL, Ib, XX },
1314 { "add", eAX, Iv, XX },
52b15da3
JH		 1315 { "(bad)", XX, XX, XX }, /* Reserved. */
1316 { "(bad)", XX, XX, XX }, /* Reserved. */
252b5132 1317 /* 08 */
57d91c3c
ILT		 1318 { "or", Eb, Gb, XX },
1319 { "or", Ev, Gv, XX },
1320 { "or", Gb, Eb, XX },
1321 { "or", Gv, Ev, XX },
1322 { "or", AL, Ib, XX },
1323 { "or", eAX, Iv, XX },
52b15da3 1324 { "(bad)", XX, XX, XX }, /* Reserved. */
57d91c3c 1325 { "(bad)", XX, XX, XX }, /* 0x0f extended opcode escape */
252b5132 1326 /* 10 */
57d91c3c
ILT		 1327 { "adc", Eb, Gb, XX },
1328 { "adc", Ev, Gv, XX },
1329 { "adc", Gb, Eb, XX },
1330 { "adc", Gv, Ev, XX },
1331 { "adc", AL, Ib, XX },
1332 { "adc", eAX, Iv, XX },
52b15da3
JH		 1333 { "(bad)", XX, XX, XX }, /* Reserved. */
1334 { "(bad)", XX, XX, XX }, /* Reserved. */
252b5132 1335 /* 18 */
57d91c3c
ILT		 1336 { "sbb", Eb, Gb, XX },
1337 { "sbb", Ev, Gv, XX },
1338 { "sbb", Gb, Eb, XX },
1339 { "sbb", Gv, Ev, XX },
1340 { "sbb", AL, Ib, XX },
1341 { "sbb", eAX, Iv, XX },
52b15da3
JH		 1342 { "(bad)", XX, XX, XX }, /* Reserved. */
1343 { "(bad)", XX, XX, XX }, /* Reserved. */
252b5132 1344 /* 20 */
57d91c3c
ILT		 1345 { "and", Eb, Gb, XX },
1346 { "and", Ev, Gv, XX },
1347 { "and", Gb, Eb, XX },
1348 { "and", Gv, Ev, XX },
1349 { "and", AL, Ib, XX },
1350 { "and", eAX, Iv, XX },
1351 { "(bad)", XX, XX, XX }, /* SEG ES prefix */
52b15da3 1352 { "(bad)", XX, XX, XX }, /* Reserved. */
252b5132 1353 /* 28 */
57d91c3c
ILT		 1354 { "sub", Eb, Gb, XX },
1355 { "sub", Ev, Gv, XX },
1356 { "sub", Gb, Eb, XX },
1357 { "sub", Gv, Ev, XX },
1358 { "sub", AL, Ib, XX },
1359 { "sub", eAX, Iv, XX },
1360 { "(bad)", XX, XX, XX }, /* SEG CS prefix */
52b15da3 1361 { "(bad)", XX, XX, XX }, /* Reserved. */
252b5132 1362 /* 30 */
57d91c3c
ILT		 1363 { "xor", Eb, Gb, XX },
1364 { "xor", Ev, Gv, XX },
1365 { "xor", Gb, Eb, XX },
1366 { "xor", Gv, Ev, XX },
1367 { "xor", AL, Ib, XX },
1368 { "xor", eAX, Iv, XX },
1369 { "(bad)", XX, XX, XX }, /* SEG SS prefix */
52b15da3 1370 { "(bad)", XX, XX, XX }, /* Reserved. */
252b5132 1371 /* 38 */
57d91c3c
ILT		 1372 { "cmp", Eb, Gb, XX },
1373 { "cmp", Ev, Gv, XX },
1374 { "cmp", Gb, Eb, XX },
1375 { "cmp", Gv, Ev, XX },
1376 { "cmp", AL, Ib, XX },
1377 { "cmp", eAX, Iv, XX },
1378 { "(bad)", XX, XX, XX }, /* SEG DS prefix */
52b15da3 1379 { "(bad)", XX, XX, XX }, /* Reserved. */
252b5132 1380 /* 40 */
52b15da3
JH		 1381 { "(bad)", XX, XX, XX }, /* REX prefix area. */
1382 { "(bad)", XX, XX, XX },
1383 { "(bad)", XX, XX, XX },
1384 { "(bad)", XX, XX, XX },
1385 { "(bad)", XX, XX, XX },
1386 { "(bad)", XX, XX, XX },
1387 { "(bad)", XX, XX, XX },
1388 { "(bad)", XX, XX, XX },
252b5132 1389 /* 48 */
52b15da3
JH		 1390 { "(bad)", XX, XX, XX },
1391 { "(bad)", XX, XX, XX },
1392 { "(bad)", XX, XX, XX },
1393 { "(bad)", XX, XX, XX },
1394 { "(bad)", XX, XX, XX },
1395 { "(bad)", XX, XX, XX },
1396 { "(bad)", XX, XX, XX },
1397 { "(bad)", XX, XX, XX },
252b5132 1398 /* 50 */
52b15da3
JH		 1399 { "push", RMrAX, XX, XX },
1400 { "push", RMrCX, XX, XX },
1401 { "push", RMrDX, XX, XX },
1402 { "push", RMrBX, XX, XX },
1403 { "push", RMrSP, XX, XX },
1404 { "push", RMrBP, XX, XX },
1405 { "push", RMrSI, XX, XX },
1406 { "push", RMrDI, XX, XX },
252b5132 1407 /* 58 */
52b15da3
JH		 1408 { "pop", RMrAX, XX, XX },
1409 { "pop", RMrCX, XX, XX },
1410 { "pop", RMrDX, XX, XX },
1411 { "pop", RMrBX, XX, XX },
1412 { "pop", RMrSP, XX, XX },
1413 { "pop", RMrBP, XX, XX },
1414 { "pop", RMrSI, XX, XX },
1415 { "pop", RMrDI, XX, XX },
252b5132 1416 /* 60 */
52b15da3
JH		 1417 { "(bad)", XX, XX, XX }, /* Reserved. */
1418 { "(bad)", XX, XX, XX }, /* Reserved. */
1419 { "(bad)", XX, XX, XX }, /* Reserved. */
1420 { "movsx", Gv, Ed, XX },
57d91c3c
ILT		 1421 { "(bad)", XX, XX, XX }, /* seg fs */
1422 { "(bad)", XX, XX, XX }, /* seg gs */
1423 { "(bad)", XX, XX, XX }, /* op size prefix */
1424 { "(bad)", XX, XX, XX }, /* adr size prefix */
252b5132 1425 /* 68 */
52b15da3 1426 { "push", Iq, XX, XX }, /* 386 book wrong */
c608c12e 1427 { "imul", Gv, Ev, Iv },
57d91c3c 1428 { "push", sIb, XX, XX }, /* push of byte really pushes 2 or 4 bytes */
c608c12e 1429 { "imul", Gv, Ev, sIb },
57d91c3c
ILT		 1430 { "ins", Yb, indirDX, XX },
1431 { "ins", Yv, indirDX, XX },
1432 { "outs", indirDX, Xb, XX },
1433 { "outs", indirDX, Xv, XX },
252b5132 1434 /* 70 */
57d91c3c
ILT		 1435 { "jo", Jb, XX, XX },
1436 { "jno", Jb, XX, XX },
1437 { "jb", Jb, XX, XX },
1438 { "jae", Jb, XX, XX },
1439 { "je", Jb, XX, XX },
1440 { "jne", Jb, XX, XX },
1441 { "jbe", Jb, XX, XX },
1442 { "ja", Jb, XX, XX },
252b5132 1443 /* 78 */
57d91c3c
ILT		 1444 { "js", Jb, XX, XX },
1445 { "jns", Jb, XX, XX },
1446 { "jp", Jb, XX, XX },
1447 { "jnp", Jb, XX, XX },
1448 { "jl", Jb, XX, XX },
1449 { "jge", Jb, XX, XX },
1450 { "jle", Jb, XX, XX },
1451 { "jg", Jb, XX, XX },
252b5132
RH		 1452 /* 80 */
1453 { GRP1b },
1454 { GRP1S },
57d91c3c 1455 { "(bad)", XX, XX, XX },
252b5132 1456 { GRP1Ss },
57d91c3c
ILT		 1457 { "test", Eb, Gb, XX },
1458 { "test", Ev, Gv, XX },
1459 { "xchg", Eb, Gb, XX },
1460 { "xchg", Ev, Gv, XX },
252b5132 1461 /* 88 */
57d91c3c
ILT		 1462 { "mov", Eb, Gb, XX },
1463 { "mov", Ev, Gv, XX },
1464 { "mov", Gb, Eb, XX },
1465 { "mov", Gv, Ev, XX },
1466 { "mov", Ev, Sw, XX },
1467 { "lea", Gv, M, XX },
1468 { "mov", Sw, Ev, XX },
1469 { "pop", Ev, XX, XX },
252b5132 1470 /* 90 */
57d91c3c 1471 { "nop", XX, XX, XX },
52b15da3
JH		 1472 { "xchg", RMeCX, eAX, XX },
1473 { "xchg", RMeDX, eAX, XX },
1474 { "xchg", RMeBX, eAX, XX },
1475 { "xchg", RMeSP, eAX, XX },
1476 { "xchg", RMeBP, eAX, XX },
1477 { "xchg", RMeSI, eAX, XX },
1478 { "xchg", RMeDI, eAX, XX },
252b5132 1479 /* 98 */
57d91c3c
ILT		 1480 { "cW", XX, XX, XX }, /* cwde and cbw */
1481 { "cR", XX, XX, XX }, /* cdq and cwd */
52b15da3 1482 { "(bad)", XX, XX, XX }, /* Reserved. */
57d91c3c
ILT		 1483 { "(bad)", XX, XX, XX }, /* fwait */
1484 { "pushf", XX, XX, XX },
1485 { "popf", XX, XX, XX },
52b15da3
JH		 1486 { "(bad)", XX, XX, XX }, /* Reserved. */
1487 { "(bad)", XX, XX, XX }, /* Reserved. */
252b5132 1488 /* a0 */
57d91c3c
ILT		 1489 { "mov", AL, Ob, XX },
1490 { "mov", eAX, Ov, XX },
1491 { "mov", Ob, AL, XX },
1492 { "mov", Ov, eAX, XX },
1493 { "movs", Yb, Xb, XX },
1494 { "movs", Yv, Xv, XX },
1495 { "cmps", Xb, Yb, XX },
1496 { "cmps", Xv, Yv, XX },
252b5132 1497 /* a8 */
57d91c3c
ILT		 1498 { "test", AL, Ib, XX },
1499 { "test", eAX, Iv, XX },
1500 { "stos", Yb, AL, XX },
1501 { "stos", Yv, eAX, XX },
1502 { "lods", AL, Xb, XX },
1503 { "lods", eAX, Xv, XX },
1504 { "scas", AL, Yb, XX },
1505 { "scas", eAX, Yv, XX },
252b5132 1506 /* b0 */
52b15da3
JH		 1507 { "mov", RMAL, Ib, XX },
1508 { "mov", RMCL, Ib, XX },
1509 { "mov", RMDL, Ib, XX },
1510 { "mov", RMBL, Ib, XX },
1511 { "mov", RMAH, Ib, XX },
1512 { "mov", RMCH, Ib, XX },
1513 { "mov", RMDH, Ib, XX },
1514 { "mov", RMBH, Ib, XX },
252b5132 1515 /* b8 */
52b15da3
JH		 1516 { "mov", RMeAX, Iv, XX },
1517 { "mov", RMeCX, Iv, XX },
1518 { "mov", RMeDX, Iv, XX },
1519 { "mov", RMeBX, Iv, XX },
1520 { "mov", RMeSP, Iv, XX },
1521 { "mov", RMeBP, Iv, XX },
1522 { "mov", RMeSI, Iv, XX },
1523 { "mov", RMeDI, Iv, XX },
252b5132
RH		 1524 /* c0 */
1525 { GRP2b },
1526 { GRP2S },
57d91c3c
ILT		 1527 { "ret", Iw, XX, XX },
1528 { "ret", XX, XX, XX },
52b15da3 1529 { "(bad)", XX, XX, XX }, /* Reserved. */
57d91c3c
ILT		 1530 { "lds", Gv, Mp, XX },
1531 { "mov", Eb, Ib, XX },
1532 { "mov", Ev, Iv, XX },
252b5132 1533 /* c8 */
57d91c3c
ILT		 1534 { "enter", Iw, Ib, XX },
1535 { "leave", XX, XX, XX },
1536 { "lret", Iw, XX, XX },
1537 { "lret", XX, XX, XX },
1538 { "int3", XX, XX, XX },
1539 { "int", Ib, XX, XX },
52b15da3 1540 { "(bad)", XX, XX, XX }, /* Reserved. */
57d91c3c 1541 { "iret", XX, XX, XX },
252b5132
RH		 1542 /* d0 */
1543 { GRP2b_one },
1544 { GRP2S_one },
1545 { GRP2b_cl },
1546 { GRP2S_cl },
52b15da3
JH		 1547 { "(bad)", XX, XX, XX }, /* Reserved. */
1548 { "(bad)", XX, XX, XX }, /* Reserved. */
57d91c3c
ILT		 1549 { "(bad)", XX, XX, XX },
1550 { "xlat", DSBX, XX, XX },
252b5132
RH		 1551 /* d8 */
1552 { FLOAT },
1553 { FLOAT },
1554 { FLOAT },
1555 { FLOAT },
1556 { FLOAT },
1557 { FLOAT },
1558 { FLOAT },
1559 { FLOAT },
1560 /* e0 */
57d91c3c
ILT		 1561 { "loopne", Jb, XX, XX },
1562 { "loope", Jb, XX, XX },
1563 { "loop", Jb, XX, XX },
1564 { "jEcxz", Jb, XX, XX },
1565 { "in", AL, Ib, XX },
1566 { "in", eAX, Ib, XX },
1567 { "out", Ib, AL, XX },
1568 { "out", Ib, eAX, XX },
252b5132 1569 /* e8 */
57d91c3c
ILT		 1570 { "call", Jv, XX, XX },
1571 { "jmp", Jv, XX, XX },
52b15da3 1572 { "(bad)", XX, XX, XX }, /* Reserved. */
57d91c3c
ILT		 1573 { "jmp", Jb, XX, XX },
1574 { "in", AL, indirDX, XX },
1575 { "in", eAX, indirDX, XX },
1576 { "out", indirDX, AL, XX },
1577 { "out", indirDX, eAX, XX },
252b5132 1578 /* f0 */
57d91c3c
ILT		 1579 { "(bad)", XX, XX, XX }, /* lock prefix */
1580 { "(bad)", XX, XX, XX },
1581 { "(bad)", XX, XX, XX }, /* repne */
1582 { "(bad)", XX, XX, XX }, /* repz */
1583 { "hlt", XX, XX, XX },
1584 { "cmc", XX, XX, XX },
252b5132
RH		 1585 { GRP3b },
1586 { GRP3S },
1587 /* f8 */
57d91c3c
ILT		 1588 { "clc", XX, XX, XX },
1589 { "stc", XX, XX, XX },
1590 { "cli", XX, XX, XX },
1591 { "sti", XX, XX, XX },
1592 { "cld", XX, XX, XX },
1593 { "std", XX, XX, XX },
252b5132
RH		 1594 { GRP4 },
1595 { GRP5 },
1596};
1597
2da11e11 1598static const struct dis386 dis386_twobyte_att[] = {
252b5132
RH		 1599 /* 00 */
1600 { GRP6 },
1601 { GRP7 },
57d91c3c
ILT		 1602 { "larS", Gv, Ew, XX },
1603 { "lslS", Gv, Ew, XX },
1604 { "(bad)", XX, XX, XX },
52b15da3 1605 { "syscall", XX, XX, XX },
57d91c3c 1606 { "clts", XX, XX, XX },
52b15da3 1607 { "sysretP", XX, XX, XX },
252b5132 1608 /* 08 */
57d91c3c
ILT		 1609 { "invd", XX, XX, XX },
1610 { "wbinvd", XX, XX, XX },
1611 { "(bad)", XX, XX, XX },
1612 { "ud2a", XX, XX, XX },
1613 { "(bad)", XX, XX, XX },
c608c12e 1614 { GRPAMD },
57d91c3c 1615 { "femms", XX, XX, XX },
252b5132
RH		 1616 { "", MX, EM, OPSUF }, /* See OP_3DNowSuffix */
1617 /* 10 */
c608c12e
AM		 1618 { PREGRP8 },
1619 { PREGRP9 },
1620 { "movlps", XM, EX, SIMD_Fixup, 'h' }, /* really only 2 operands */
1621 { "movlps", EX, XM, SIMD_Fixup, 'h' },
57d91c3c
ILT		 1622 { "unpcklps", XM, EX, XX },
1623 { "unpckhps", XM, EX, XX },
c608c12e
AM		 1624 { "movhps", XM, EX, SIMD_Fixup, 'l' },
1625 { "movhps", EX, XM, SIMD_Fixup, 'l' },
252b5132 1626 /* 18 */
c608c12e 1627 { GRP14 },
57d91c3c
ILT		 1628 { "(bad)", XX, XX, XX },
1629 { "(bad)", XX, XX, XX },
1630 { "(bad)", XX, XX, XX },
1631 { "(bad)", XX, XX, XX },
1632 { "(bad)", XX, XX, XX },
1633 { "(bad)", XX, XX, XX },
1634 { "(bad)", XX, XX, XX },
252b5132
RH		 1635 /* 20 */
1636 /* these are all backward in appendix A of the intel book */
52b15da3
JH		 1637 { "movL", Rm, Cm, XX },
1638 { "movL", Rm, Dm, XX },
1639 { "movL", Cm, Rm, XX },
1640 { "movL", Dm, Rm, XX },
57d91c3c
ILT		 1641 { "movL", Rd, Td, XX },
1642 { "(bad)", XX, XX, XX },
1643 { "movL", Td, Rd, XX },
1644 { "(bad)", XX, XX, XX },
252b5132 1645 /* 28 */
57d91c3c
ILT		 1646 { "movaps", XM, EX, XX },
1647 { "movaps", EX, XM, XX },
c608c12e 1648 { PREGRP2 },
57d91c3c 1649 { "movntps", Ev, XM, XX },
2da11e11 1650 { PREGRP4 },
c608c12e 1651 { PREGRP3 },
57d91c3c
ILT		 1652 { "ucomiss", XM, EX, XX },
1653 { "comiss", XM, EX, XX },
252b5132 1654 /* 30 */
57d91c3c
ILT		 1655 { "wrmsr", XX, XX, XX },
1656 { "rdtsc", XX, XX, XX },
1657 { "rdmsr", XX, XX, XX },
1658 { "rdpmc", XX, XX, XX },
1659 { "sysenter", XX, XX, XX },
1660 { "sysexit", XX, XX, XX },
1661 { "(bad)", XX, XX, XX },
1662 { "(bad)", XX, XX, XX },
252b5132 1663 /* 38 */
57d91c3c
ILT		 1664 { "(bad)", XX, XX, XX },
1665 { "(bad)", XX, XX, XX },
1666 { "(bad)", XX, XX, XX },
1667 { "(bad)", XX, XX, XX },
1668 { "(bad)", XX, XX, XX },
1669 { "(bad)", XX, XX, XX },
1670 { "(bad)", XX, XX, XX },
1671 { "(bad)", XX, XX, XX },
252b5132 1672 /* 40 */
57d91c3c
ILT		 1673 { "cmovo", Gv, Ev, XX },
1674 { "cmovno", Gv, Ev, XX },
1675 { "cmovb", Gv, Ev, XX },
1676 { "cmovae", Gv, Ev, XX },
1677 { "cmove", Gv, Ev, XX },
1678 { "cmovne", Gv, Ev, XX },
1679 { "cmovbe", Gv, Ev, XX },
1680 { "cmova", Gv, Ev, XX },
252b5132 1681 /* 48 */
57d91c3c
ILT		 1682 { "cmovs", Gv, Ev, XX },
1683 { "cmovns", Gv, Ev, XX },
1684 { "cmovp", Gv, Ev, XX },
1685 { "cmovnp", Gv, Ev, XX },
1686 { "cmovl", Gv, Ev, XX },
1687 { "cmovge", Gv, Ev, XX },
1688 { "cmovle", Gv, Ev, XX },
1689 { "cmovg", Gv, Ev, XX },
252b5132 1690 /* 50 */
57d91c3c 1691 { "movmskps", Gv, EX, XX },
c608c12e
AM		 1692 { PREGRP13 },
1693 { PREGRP12 },
1694 { PREGRP11 },
57d91c3c
ILT		 1695 { "andps", XM, EX, XX },
1696 { "andnps", XM, EX, XX },
1697 { "orps", XM, EX, XX },
1698 { "xorps", XM, EX, XX },
252b5132 1699 /* 58 */
c608c12e
AM		 1700 { PREGRP0 },
1701 { PREGRP10 },
57d91c3c
ILT		 1702 { "(bad)", XX, XX, XX },
1703 { "(bad)", XX, XX, XX },
c608c12e
AM		 1704 { PREGRP14 },
1705 { PREGRP7 },
1706 { PREGRP5 },
2da11e11 1707 { PREGRP6 },
252b5132 1708 /* 60 */
57d91c3c
ILT		 1709 { "punpcklbw", MX, EM, XX },
1710 { "punpcklwd", MX, EM, XX },
1711 { "punpckldq", MX, EM, XX },
1712 { "packsswb", MX, EM, XX },
1713 { "pcmpgtb", MX, EM, XX },
1714 { "pcmpgtw", MX, EM, XX },
1715 { "pcmpgtd", MX, EM, XX },
1716 { "packuswb", MX, EM, XX },
252b5132 1717 /* 68 */
57d91c3c
ILT		 1718 { "punpckhbw", MX, EM, XX },
1719 { "punpckhwd", MX, EM, XX },
1720 { "punpckhdq", MX, EM, XX },
1721 { "packssdw", MX, EM, XX },
1722 { "(bad)", XX, XX, XX },
1723 { "(bad)", XX, XX, XX },
1724 { "movd", MX, Ed, XX },
1725 { "movq", MX, EM, XX },
252b5132 1726 /* 70 */
c608c12e 1727 { "pshufw", MX, EM, Ib },
252b5132
RH		 1728 { GRP10 },
1729 { GRP11 },
1730 { GRP12 },
57d91c3c
ILT		 1731 { "pcmpeqb", MX, EM, XX },
1732 { "pcmpeqw", MX, EM, XX },
1733 { "pcmpeqd", MX, EM, XX },
1734 { "emms", XX, XX, XX },
252b5132 1735 /* 78 */
57d91c3c
ILT		 1736 { "(bad)", XX, XX, XX },
1737 { "(bad)", XX, XX, XX },
1738 { "(bad)", XX, XX, XX },
1739 { "(bad)", XX, XX, XX },
1740 { "(bad)", XX, XX, XX },
1741 { "(bad)", XX, XX, XX },
1742 { "movd", Ed, MX, XX },
1743 { "movq", EM, MX, XX },
252b5132 1744 /* 80 */
57d91c3c
ILT		 1745 { "jo", Jv, XX, XX },
1746 { "jno", Jv, XX, XX },
1747 { "jb", Jv, XX, XX },
1748 { "jae", Jv, XX, XX },
1749 { "je", Jv, XX, XX },
1750 { "jne", Jv, XX, XX },
1751 { "jbe", Jv, XX, XX },
1752 { "ja", Jv, XX, XX },
252b5132 1753 /* 88 */
57d91c3c
ILT		 1754 { "js", Jv, XX, XX },
1755 { "jns", Jv, XX, XX },
1756 { "jp", Jv, XX, XX },
1757 { "jnp", Jv, XX, XX },
1758 { "jl", Jv, XX, XX },
1759 { "jge", Jv, XX, XX },
1760 { "jle", Jv, XX, XX },
1761 { "jg", Jv, XX, XX },
252b5132 1762 /* 90 */
57d91c3c
ILT		 1763 { "seto", Eb, XX, XX },
1764 { "setno", Eb, XX, XX },
1765 { "setb", Eb, XX, XX },
1766 { "setae", Eb, XX, XX },
1767 { "sete", Eb, XX, XX },
1768 { "setne", Eb, XX, XX },
1769 { "setbe", Eb, XX, XX },
1770 { "seta", Eb, XX, XX },
252b5132 1771 /* 98 */
57d91c3c
ILT		 1772 { "sets", Eb, XX, XX },
1773 { "setns", Eb, XX, XX },
1774 { "setp", Eb, XX, XX },
1775 { "setnp", Eb, XX, XX },
1776 { "setl", Eb, XX, XX },
1777 { "setge", Eb, XX, XX },
1778 { "setle", Eb, XX, XX },
1779 { "setg", Eb, XX, XX },
252b5132 1780 /* a0 */
52b15da3
JH		 1781 { "pushI", fs, XX, XX },
1782 { "popI", fs, XX, XX },
57d91c3c
ILT		 1783 { "cpuid", XX, XX, XX },
1784 { "btS", Ev, Gv, XX },
252b5132
RH		 1785 { "shldS", Ev, Gv, Ib },
1786 { "shldS", Ev, Gv, CL },
57d91c3c
ILT		 1787 { "(bad)", XX, XX, XX },
1788 { "(bad)", XX, XX, XX },
252b5132 1789 /* a8 */
52b15da3
JH		 1790 { "pushI", gs, XX, XX },
1791 { "popI", gs, XX, XX },
57d91c3c
ILT		 1792 { "rsm", XX, XX, XX },
1793 { "btsS", Ev, Gv, XX },
252b5132
RH		 1794 { "shrdS", Ev, Gv, Ib },
1795 { "shrdS", Ev, Gv, CL },
1796 { GRP13 },
57d91c3c 1797 { "imulS", Gv, Ev, XX },
252b5132 1798 /* b0 */
57d91c3c
ILT		 1799 { "cmpxchgB", Eb, Gb, XX },
1800 { "cmpxchgS", Ev, Gv, XX },
1801 { "lssS", Gv, Mp, XX },
1802 { "btrS", Ev, Gv, XX },
1803 { "lfsS", Gv, Mp, XX },
1804 { "lgsS", Gv, Mp, XX },
1805 { "movzbR", Gv, Eb, XX },
1806 { "movzwR", Gv, Ew, XX }, /* yes, there really is movzww ! */
252b5132 1807 /* b8 */
57d91c3c
ILT		 1808 { "(bad)", XX, XX, XX },
1809 { "ud2b", XX, XX, XX },
252b5132 1810 { GRP8 },
57d91c3c
ILT		 1811 { "btcS", Ev, Gv, XX },
1812 { "bsfS", Gv, Ev, XX },
1813 { "bsrS", Gv, Ev, XX },
1814 { "movsbR", Gv, Eb, XX },
1815 { "movswR", Gv, Ew, XX }, /* yes, there really is movsww ! */
252b5132 1816 /* c0 */
57d91c3c
ILT		 1817 { "xaddB", Eb, Gb, XX },
1818 { "xaddS", Ev, Gv, XX },
c608c12e 1819 { PREGRP1 },
57d91c3c 1820 { "(bad)", XX, XX, XX },
c608c12e
AM		 1821 { "pinsrw", MX, Ev, Ib },
1822 { "pextrw", Ev, MX, Ib },
1823 { "shufps", XM, EX, Ib },
252b5132
RH		 1824 { GRP9 },
1825 /* c8 */
52b15da3
JH		 1826 { "bswap", RMeAX, XX, XX }, /* bswap doesn't support 16 bit regs */
1827 { "bswap", RMeCX, XX, XX },
1828 { "bswap", RMeDX, XX, XX },
1829 { "bswap", RMeBX, XX, XX },
1830 { "bswap", RMeSP, XX, XX },
1831 { "bswap", RMeBP, XX, XX },
1832 { "bswap", RMeSI, XX, XX },
1833 { "bswap", RMeDI, XX, XX },
252b5132 1834 /* d0 */
57d91c3c
ILT		 1835 { "(bad)", XX, XX, XX },
1836 { "psrlw", MX, EM, XX },
1837 { "psrld", MX, EM, XX },
1838 { "psrlq", MX, EM, XX },
1839 { "(bad)", XX, XX, XX },
1840 { "pmullw", MX, EM, XX },
1841 { "(bad)", XX, XX, XX },
1842 { "pmovmskb", Ev, MX, XX },
252b5132 1843 /* d8 */
57d91c3c
ILT		 1844 { "psubusb", MX, EM, XX },
1845 { "psubusw", MX, EM, XX },
1846 { "pminub", MX, EM, XX },
1847 { "pand", MX, EM, XX },
1848 { "paddusb", MX, EM, XX },
1849 { "paddusw", MX, EM, XX },
1850 { "pmaxub", MX, EM, XX },
1851 { "pandn", MX, EM, XX },
252b5132 1852 /* e0 */
57d91c3c
ILT		 1853 { "pavgb", MX, EM, XX },
1854 { "psraw", MX, EM, XX },
1855 { "psrad", MX, EM, XX },
1856 { "pavgw", MX, EM, XX },
1857 { "pmulhuw", MX, EM, XX },
1858 { "pmulhw", MX, EM, XX },
1859 { "(bad)", XX, XX, XX },
1860 { "movntq", Ev, MX, XX },
252b5132 1861 /* e8 */
57d91c3c
ILT		 1862 { "psubsb", MX, EM, XX },
1863 { "psubsw", MX, EM, XX },
1864 { "pminsw", MX, EM, XX },
1865 { "por", MX, EM, XX },
1866 { "paddsb", MX, EM, XX },
1867 { "paddsw", MX, EM, XX },
1868 { "pmaxsw", MX, EM, XX },
1869 { "pxor", MX, EM, XX },
252b5132 1870 /* f0 */
57d91c3c
ILT		 1871 { "(bad)", XX, XX, XX },
1872 { "psllw", MX, EM, XX },
1873 { "pslld", MX, EM, XX },
1874 { "psllq", MX, EM, XX },
1875 { "(bad)", XX, XX, XX },
1876 { "pmaddwd", MX, EM, XX },
1877 { "psadbw", MX, EM, XX },
1878 { "maskmovq", MX, EM, XX },
252b5132 1879 /* f8 */
57d91c3c
ILT		 1880 { "psubb", MX, EM, XX },
1881 { "psubw", MX, EM, XX },
1882 { "psubd", MX, EM, XX },
1883 { "(bad)", XX, XX, XX },
1884 { "paddb", MX, EM, XX },
1885 { "paddw", MX, EM, XX },
1886 { "paddd", MX, EM, XX },
1887 { "(bad)", XX, XX, XX }
252b5132
RH		 1888};
1889
2da11e11 1890static const struct dis386 dis386_twobyte_intel[] = {
252b5132
RH		 1891 /* 00 */
1892 { GRP6 },
1893 { GRP7 },
57d91c3c
ILT		 1894 { "lar", Gv, Ew, XX },
1895 { "lsl", Gv, Ew, XX },
1896 { "(bad)", XX, XX, XX },
52b15da3 1897 { "syscall", XX, XX, XX },
57d91c3c 1898 { "clts", XX, XX, XX },
52b15da3 1899 { "sysretP", XX, XX, XX },
252b5132 1900 /* 08 */
57d91c3c
ILT		 1901 { "invd", XX, XX, XX },
1902 { "wbinvd", XX, XX, XX },
1903 { "(bad)", XX, XX, XX },
1904 { "ud2a", XX, XX, XX },
1905 { "(bad)", XX, XX, XX },
c608c12e 1906 { GRPAMD },
57d91c3c 1907 { "femms" , XX, XX, XX},
252b5132
RH		 1908 { "", MX, EM, OPSUF }, /* See OP_3DNowSuffix */
1909 /* 10 */
c608c12e
AM		 1910 { PREGRP8 },
1911 { PREGRP9 },
1912 { "movlps", XM, EX, SIMD_Fixup, 'h' }, /* really only 2 operands */
1913 { "movlps", EX, XM, SIMD_Fixup, 'h' },
57d91c3c
ILT		 1914 { "unpcklps", XM, EX, XX },
1915 { "unpckhps", XM, EX, XX },
c608c12e
AM		 1916 { "movhps", XM, EX, SIMD_Fixup, 'l' },
1917 { "movhps", EX, XM, SIMD_Fixup, 'l' },
252b5132 1918 /* 18 */
c608c12e 1919 { GRP14 },
57d91c3c
ILT		 1920 { "(bad)", XX, XX, XX },
1921 { "(bad)", XX, XX, XX },
1922 { "(bad)", XX, XX, XX },
1923 { "(bad)", XX, XX, XX },
1924 { "(bad)", XX, XX, XX },
1925 { "(bad)", XX, XX, XX },
1926 { "(bad)", XX, XX, XX },
252b5132
RH		 1927 /* 20 */
1928 /* these are all backward in appendix A of the intel book */
52b15da3
JH		 1929 { "mov", Rm, Cm, XX },
1930 { "mov", Rm, Dm, XX },
1931 { "mov", Cm, Rm, XX },
1932 { "mov", Dm, Rm, XX },
57d91c3c
ILT		 1933 { "mov", Rd, Td, XX },
1934 { "(bad)", XX, XX, XX },
1935 { "mov", Td, Rd, XX },
1936 { "(bad)", XX, XX, XX },
252b5132 1937 /* 28 */
57d91c3c
ILT		 1938 { "movaps", XM, EX, XX },
1939 { "movaps", EX, XM, XX },
c608c12e 1940 { PREGRP2 },
57d91c3c 1941 { "movntps", Ev, XM, XX },
2da11e11 1942 { PREGRP4 },
c608c12e 1943 { PREGRP3 },
57d91c3c
ILT		 1944 { "ucomiss", XM, EX, XX },
1945 { "comiss", XM, EX, XX },
252b5132 1946 /* 30 */
57d91c3c
ILT		 1947 { "wrmsr", XX, XX, XX },
1948 { "rdtsc", XX, XX, XX },
1949 { "rdmsr", XX, XX, XX },
1950 { "rdpmc", XX, XX, XX },
1951 { "sysenter", XX, XX, XX },
1952 { "sysexit", XX, XX, XX },
1953 { "(bad)", XX, XX, XX },
1954 { "(bad)", XX, XX, XX },
252b5132 1955 /* 38 */
57d91c3c
ILT		 1956 { "(bad)", XX, XX, XX },
1957 { "(bad)", XX, XX, XX },
1958 { "(bad)", XX, XX, XX },
1959 { "(bad)", XX, XX, XX },
1960 { "(bad)", XX, XX, XX },
1961 { "(bad)", XX, XX, XX },
1962 { "(bad)", XX, XX, XX },
1963 { "(bad)", XX, XX, XX },
252b5132 1964 /* 40 */
57d91c3c
ILT		 1965 { "cmovo", Gv, Ev, XX },
1966 { "cmovno", Gv, Ev, XX },
1967 { "cmovb", Gv, Ev, XX },
1968 { "cmovae", Gv, Ev, XX },
1969 { "cmove", Gv, Ev, XX },
1970 { "cmovne", Gv, Ev, XX },
1971 { "cmovbe", Gv, Ev, XX },
1972 { "cmova", Gv, Ev, XX },
252b5132 1973 /* 48 */
57d91c3c
ILT		 1974 { "cmovs", Gv, Ev, XX },
1975 { "cmovns", Gv, Ev, XX },
1976 { "cmovp", Gv, Ev, XX },
1977 { "cmovnp", Gv, Ev, XX },
1978 { "cmovl", Gv, Ev, XX },
1979 { "cmovge", Gv, Ev, XX },
1980 { "cmovle", Gv, Ev, XX },
1981 { "cmovg", Gv, Ev, XX },
252b5132 1982 /* 50 */
57d91c3c 1983 { "movmskps", Gv, EX, XX },
c608c12e
AM		 1984 { PREGRP13 },
1985 { PREGRP12 },
1986 { PREGRP11 },
57d91c3c
ILT		 1987 { "andps", XM, EX, XX },
1988 { "andnps", XM, EX, XX },
1989 { "orps", XM, EX, XX },
1990 { "xorps", XM, EX, XX },
252b5132 1991 /* 58 */
c608c12e
AM		 1992 { PREGRP0 },
1993 { PREGRP10 },
57d91c3c
ILT		 1994 { "(bad)", XX, XX, XX },
1995 { "(bad)", XX, XX, XX },
c608c12e
AM		 1996 { PREGRP14 },
1997 { PREGRP7 },
1998 { PREGRP5 },
2da11e11 1999 { PREGRP6 },
252b5132 2000 /* 60 */
57d91c3c
ILT		 2001 { "punpcklbw", MX, EM, XX },
2002 { "punpcklwd", MX, EM, XX },
2003 { "punpckldq", MX, EM, XX },
2004 { "packsswb", MX, EM, XX },
2005 { "pcmpgtb", MX, EM, XX },
2006 { "pcmpgtw", MX, EM, XX },
2007 { "pcmpgtd", MX, EM, XX },
2008 { "packuswb", MX, EM, XX },
252b5132 2009 /* 68 */
57d91c3c
ILT		 2010 { "punpckhbw", MX, EM, XX },
2011 { "punpckhwd", MX, EM, XX },
2012 { "punpckhdq", MX, EM, XX },
2013 { "packssdw", MX, EM, XX },
2014 { "(bad)", XX, XX, XX },
2015 { "(bad)", XX, XX, XX },
2016 { "movd", MX, Ed, XX },
2017 { "movq", MX, EM, XX },
252b5132 2018 /* 70 */
c608c12e 2019 { "pshufw", MX, EM, Ib },
252b5132
RH		 2020 { GRP10 },
2021 { GRP11 },
2022 { GRP12 },
57d91c3c
ILT		 2023 { "pcmpeqb", MX, EM, XX },
2024 { "pcmpeqw", MX, EM, XX },
2025 { "pcmpeqd", MX, EM, XX },
2026 { "emms", XX, XX, XX },
252b5132 2027 /* 78 */
57d91c3c
ILT		 2028 { "(bad)", XX, XX, XX },
2029 { "(bad)", XX, XX, XX },
2030 { "(bad)", XX, XX, XX },
2031 { "(bad)", XX, XX, XX },
2032 { "(bad)", XX, XX, XX },
2033 { "(bad)", XX, XX, XX },
2034 { "movd", Ed, MX, XX },
2035 { "movq", EM, MX, XX },
252b5132 2036 /* 80 */
57d91c3c
ILT		 2037 { "jo", Jv, XX, XX },
2038 { "jno", Jv, XX, XX },
2039 { "jb", Jv, XX, XX },
2040 { "jae", Jv, XX, XX },
2041 { "je", Jv, XX, XX },
2042 { "jne", Jv, XX, XX },
2043 { "jbe", Jv, XX, XX },
2044 { "ja", Jv, XX, XX },
252b5132 2045 /* 88 */
57d91c3c
ILT		 2046 { "js", Jv, XX, XX },
2047 { "jns", Jv, XX, XX },
2048 { "jp", Jv, XX, XX },
2049 { "jnp", Jv, XX, XX },
2050 { "jl", Jv, XX, XX },
2051 { "jge", Jv, XX, XX },
2052 { "jle", Jv, XX, XX },
2053 { "jg", Jv, XX, XX },
252b5132 2054 /* 90 */
57d91c3c
ILT		 2055 { "seto", Eb, XX, XX },
2056 { "setno", Eb, XX, XX },
2057 { "setb", Eb, XX, XX },
2058 { "setae", Eb, XX, XX },
2059 { "sete", Eb, XX, XX },
2060 { "setne", Eb, XX, XX },
2061 { "setbe", Eb, XX, XX },
2062 { "seta", Eb, XX, XX },
252b5132 2063 /* 98 */
57d91c3c
ILT		 2064 { "sets", Eb, XX, XX },
2065 { "setns", Eb, XX, XX },
2066 { "setp", Eb, XX, XX },
2067 { "setnp", Eb, XX, XX },
2068 { "setl", Eb, XX, XX },
2069 { "setge", Eb, XX, XX },
2070 { "setle", Eb, XX, XX },
2071 { "setg", Eb, XX, XX },
252b5132 2072 /* a0 */
57d91c3c
ILT		 2073 { "push", fs, XX, XX },
2074 { "pop", fs, XX, XX },
2075 { "cpuid", XX, XX, XX },
2076 { "bt", Ev, Gv, XX },
c608c12e
AM		 2077 { "shld", Ev, Gv, Ib },
2078 { "shld", Ev, Gv, CL },
57d91c3c
ILT		 2079 { "(bad)", XX, XX, XX },
2080 { "(bad)", XX, XX, XX },
252b5132 2081 /* a8 */
57d91c3c
ILT		 2082 { "push", gs, XX, XX },
2083 { "pop", gs, XX, XX },
2084 { "rsm" , XX, XX, XX},
2085 { "bts", Ev, Gv, XX },
c608c12e
AM		 2086 { "shrd", Ev, Gv, Ib },
2087 { "shrd", Ev, Gv, CL },
252b5132 2088 { GRP13 },
57d91c3c 2089 { "imul", Gv, Ev, XX },
252b5132 2090 /* b0 */
57d91c3c
ILT		 2091 { "cmpxchg", Eb, Gb, XX },
2092 { "cmpxchg", Ev, Gv, XX },
2093 { "lss", Gv, Mp, XX },
2094 { "btr", Ev, Gv, XX },
2095 { "lfs", Gv, Mp, XX },
2096 { "lgs", Gv, Mp, XX },
2097 { "movzx", Gv, Eb, XX },
2098 { "movzx", Gv, Ew, XX },
252b5132 2099 /* b8 */
57d91c3c
ILT		 2100 { "(bad)", XX, XX, XX },
2101 { "ud2b", XX, XX, XX },
252b5132 2102 { GRP8 },
57d91c3c
ILT		 2103 { "btc", Ev, Gv, XX },
2104 { "bsf", Gv, Ev, XX },
2105 { "bsr", Gv, Ev, XX },
2106 { "movsx", Gv, Eb, XX },
2107 { "movsx", Gv, Ew, XX },
252b5132 2108 /* c0 */
57d91c3c
ILT		 2109 { "xadd", Eb, Gb, XX },
2110 { "xadd", Ev, Gv, XX },
c608c12e 2111 { PREGRP1 },
57d91c3c 2112 { "(bad)", XX, XX, XX },
c608c12e
AM		 2113 { "pinsrw", MX, Ev, Ib },
2114 { "pextrw", Ev, MX, Ib },
2115 { "shufps", XM, EX, Ib },
252b5132
RH		 2116 { GRP9 },
2117 /* c8 */
52b15da3
JH		 2118 { "bswap", RMeAX, XX, XX }, /* bswap doesn't support 16 bit regs */
2119 { "bswap", RMeCX, XX, XX },
2120 { "bswap", RMeDX, XX, XX },
2121 { "bswap", RMeBX, XX, XX },
2122 { "bswap", RMeSP, XX, XX },
2123 { "bswap", RMeBP, XX, XX },
2124 { "bswap", RMeSI, XX, XX },
2125 { "bswap", RMeDI, XX, XX },
252b5132 2126 /* d0 */
57d91c3c
ILT		 2127 { "(bad)", XX, XX, XX },
2128 { "psrlw", MX, EM, XX },
2129 { "psrld", MX, EM, XX },
2130 { "psrlq", MX, EM, XX },
2131 { "(bad)", XX, XX, XX },
2132 { "pmullw", MX, EM, XX },
2133 { "(bad)", XX, XX, XX },
2134 { "pmovmskb", Ev, MX, XX },
252b5132 2135 /* d8 */
57d91c3c
ILT		 2136 { "psubusb", MX, EM, XX },
2137 { "psubusw", MX, EM, XX },
2138 { "pminub", MX, EM, XX },
2139 { "pand", MX, EM, XX },
2140 { "paddusb", MX, EM, XX },
2141 { "paddusw", MX, EM, XX },
2142 { "pmaxub", MX, EM, XX },
2143 { "pandn", MX, EM, XX },
252b5132 2144 /* e0 */
57d91c3c
ILT		 2145 { "pavgb", MX, EM, XX },
2146 { "psraw", MX, EM, XX },
2147 { "psrad", MX, EM, XX },
2148 { "pavgw", MX, EM, XX },
2149 { "pmulhuw", MX, EM, XX },
2150 { "pmulhw", MX, EM, XX },
2151 { "(bad)", XX, XX, XX },
2152 { "movntq", Ev, MX, XX },
252b5132 2153 /* e8 */
57d91c3c
ILT		 2154 { "psubsb", MX, EM, XX },
2155 { "psubsw", MX, EM, XX },
2156 { "pminsw", MX, EM, XX },
2157 { "por", MX, EM, XX },
2158 { "paddsb", MX, EM, XX },
2159 { "paddsw", MX, EM, XX },
2160 { "pmaxsw", MX, EM, XX },
2161 { "pxor", MX, EM, XX },
252b5132 2162 /* f0 */
57d91c3c
ILT		 2163 { "(bad)", XX, XX, XX },
2164 { "psllw", MX, EM, XX },
2165 { "pslld", MX, EM, XX },
2166 { "psllq", MX, EM, XX },
2167 { "(bad)", XX, XX, XX },
2168 { "pmaddwd", MX, EM, XX },
2169 { "psadbw", MX, EM, XX },
2170 { "maskmovq", MX, EM, XX },
252b5132 2171 /* f8 */
57d91c3c
ILT		 2172 { "psubb", MX, EM, XX },
2173 { "psubw", MX, EM, XX },
2174 { "psubd", MX, EM, XX },
2175 { "(bad)", XX, XX, XX },
2176 { "paddb", MX, EM, XX },
2177 { "paddw", MX, EM, XX },
2178 { "paddd", MX, EM, XX },
2179 { "(bad)", XX, XX, XX }
252b5132
RH		 2180};
2181
2182static const unsigned char onebyte_has_modrm[256] = {
c608c12e
AM		 2183 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
2184 /* ------------------------------- */
2185 /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */
2186 /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */
2187 /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */
2188 /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */
2189 /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */
2190 /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */
2191 /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */
2192 /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */
2193 /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */
2194 /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */
2195 /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */
2196 /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */
2197 /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */
2198 /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */
2199 /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */
2200 /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1 /* f0 */
2201 /* ------------------------------- */
2202 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
252b5132
RH		 2203};
2204
2205static const unsigned char twobyte_has_modrm[256] = {
c608c12e
AM		 2206 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
2207 /* ------------------------------- */
252b5132 2208 /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */
c608c12e
AM		 2209 /* 10 */ 1,1,1,1,1,1,1,1,1,0,0,0,0,0,0,0, /* 1f */
2210 /* 20 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 2f */
252b5132
RH		 2211 /* 30 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 3f */
2212 /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */
c608c12e 2213 /* 50 */ 1,1,1,1,1,1,1,1,1,1,0,0,1,1,1,1, /* 5f */
252b5132 2214 /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,0,0,1,1, /* 6f */
c608c12e 2215 /* 70 */ 1,1,1,1,1,1,1,0,0,0,0,0,0,0,1,1, /* 7f */
252b5132
RH		 2216 /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */
2217 /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */
2218 /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */
2219 /* b0 */ 1,1,1,1,1,1,1,1,0,0,1,1,1,1,1,1, /* bf */
2220 /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */
c608c12e
AM		 2221 /* d0 */ 0,1,1,1,0,1,0,1,1,1,1,1,1,1,1,1, /* df */
2222 /* e0 */ 1,1,1,1,1,1,0,1,1,1,1,1,1,1,1,1, /* ef */
2223 /* f0 */ 0,1,1,1,0,1,1,1,1,1,1,0,1,1,1,0 /* ff */
2224 /* ------------------------------- */
2225 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
2226};
2227
2228static const unsigned char twobyte_uses_f3_prefix[256] = {
2229 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
2230 /* ------------------------------- */
2231 /* 00 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 0f */
2232 /* 10 */ 1,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 1f */
2233 /* 20 */ 0,0,0,0,0,0,0,0,0,0,1,0,1,1,0,0, /* 2f */
2234 /* 30 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 3f */
2235 /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 4f */
2236 /* 50 */ 0,1,1,1,0,0,0,0,1,1,0,0,1,1,1,1, /* 5f */
2237 /* 60 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 6f */
2238 /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 7f */
2239 /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */
2240 /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 9f */
2241 /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* af */
2242 /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* bf */
2243 /* c0 */ 0,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0, /* cf */
2244 /* d0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* df */
2245 /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* ef */
2246 /* f0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 /* ff */
2247 /* ------------------------------- */
2248 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
252b5132
RH		 2249};
2250
2251static char obuf[100];
2252static char *obufp;
2253static char scratchbuf[100];
2254static unsigned char *start_codep;
2255static unsigned char *insn_codep;
2256static unsigned char *codep;
2257static disassemble_info *the_info;
2258static int mod;
2259static int rm;
2260static int reg;
2da11e11 2261static void oappend PARAMS ((const char *s));
252b5132 2262
52b15da3
JH		 2263static const char *names64[] = {
2264 "%rax","%rcx","%rdx","%rbx", "%rsp","%rbp","%rsi","%rdi",
2265 "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15"
2266};
2267static const char *names32[] = {
252b5132 2268 "%eax","%ecx","%edx","%ebx", "%esp","%ebp","%esi","%edi",
52b15da3 2269 "%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d"
252b5132 2270};
2da11e11 2271static const char *names16[] = {
252b5132 2272 "%ax","%cx","%dx","%bx","%sp","%bp","%si","%di",
52b15da3 2273 "%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w"
252b5132 2274};
2da11e11 2275static const char *names8[] = {
252b5132
RH		 2276 "%al","%cl","%dl","%bl","%ah","%ch","%dh","%bh",
2277};
52b15da3
JH		 2278static const char *names8rex[] = {
2279 "%al","%cl","%dl","%bl","%spl", "%bpl", "%sil", "%dil",
2280 "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b"
2281};
2da11e11 2282static const char *names_seg[] = {
252b5132
RH		 2283 "%es","%cs","%ss","%ds","%fs","%gs","%?","%?",
2284};
2da11e11 2285static const char *index16[] = {
252b5132
RH		 2286 "%bx,%si","%bx,%di","%bp,%si","%bp,%di","%si","%di","%bp","%bx"
2287};
2288
2da11e11 2289static const struct dis386 grps[][8] = {
252b5132
RH		 2290 /* GRP1b */
2291 {
57d91c3c
ILT		 2292 { "addA", Eb, Ib, XX },
2293 { "orA", Eb, Ib, XX },
2294 { "adcA", Eb, Ib, XX },
2295 { "sbbA", Eb, Ib, XX },
2296 { "andA", Eb, Ib, XX },
2297 { "subA", Eb, Ib, XX },
2298 { "xorA", Eb, Ib, XX },
2299 { "cmpA", Eb, Ib, XX }
252b5132
RH		 2300 },
2301 /* GRP1S */
2302 {
57d91c3c
ILT		 2303 { "addQ", Ev, Iv, XX },
2304 { "orQ", Ev, Iv, XX },
2305 { "adcQ", Ev, Iv, XX },
2306 { "sbbQ", Ev, Iv, XX },
2307 { "andQ", Ev, Iv, XX },
2308 { "subQ", Ev, Iv, XX },
2309 { "xorQ", Ev, Iv, XX },
2310 { "cmpQ", Ev, Iv, XX }
252b5132
RH		 2311 },
2312 /* GRP1Ss */
2313 {
57d91c3c
ILT		 2314 { "addQ", Ev, sIb, XX },
2315 { "orQ", Ev, sIb, XX },
2316 { "adcQ", Ev, sIb, XX },
2317 { "sbbQ", Ev, sIb, XX },
2318 { "andQ", Ev, sIb, XX },
2319 { "subQ", Ev, sIb, XX },
2320 { "xorQ", Ev, sIb, XX },
2321 { "cmpQ", Ev, sIb, XX }
252b5132
RH		 2322 },
2323 /* GRP2b */
2324 {
57d91c3c
ILT		 2325 { "rolA", Eb, Ib, XX },
2326 { "rorA", Eb, Ib, XX },
2327 { "rclA", Eb, Ib, XX },
2328 { "rcrA", Eb, Ib, XX },
2329 { "shlA", Eb, Ib, XX },
2330 { "shrA", Eb, Ib, XX },
2331 { "(bad)", XX, XX, XX },
2332 { "sarA", Eb, Ib, XX },
252b5132
RH		 2333 },
2334 /* GRP2S */
2335 {
57d91c3c
ILT		 2336 { "rolQ", Ev, Ib, XX },
2337 { "rorQ", Ev, Ib, XX },
2338 { "rclQ", Ev, Ib, XX },
2339 { "rcrQ", Ev, Ib, XX },
2340 { "shlQ", Ev, Ib, XX },
2341 { "shrQ", Ev, Ib, XX },
2342 { "(bad)", XX, XX, XX },
2343 { "sarQ", Ev, Ib, XX },
252b5132
RH		 2344 },
2345 /* GRP2b_one */
2346 {
57d91c3c
ILT		 2347 { "rolA", Eb, XX, XX },
2348 { "rorA", Eb, XX, XX },
2349 { "rclA", Eb, XX, XX },
2350 { "rcrA", Eb, XX, XX },
2351 { "shlA", Eb, XX, XX },
2352 { "shrA", Eb, XX, XX },
2353 { "(bad)", XX, XX, XX },
2354 { "sarA", Eb, XX, XX },
252b5132
RH		 2355 },
2356 /* GRP2S_one */
2357 {
57d91c3c
ILT		 2358 { "rolQ", Ev, XX, XX },
2359 { "rorQ", Ev, XX, XX },
2360 { "rclQ", Ev, XX, XX },
2361 { "rcrQ", Ev, XX, XX },
2362 { "shlQ", Ev, XX, XX },
2363 { "shrQ", Ev, XX, XX },
2364 { "(bad)", XX, XX, XX},
2365 { "sarQ", Ev, XX, XX },
252b5132
RH		 2366 },
2367 /* GRP2b_cl */
2368 {
57d91c3c
ILT		 2369 { "rolA", Eb, CL, XX },
2370 { "rorA", Eb, CL, XX },
2371 { "rclA", Eb, CL, XX },
2372 { "rcrA", Eb, CL, XX },
2373 { "shlA", Eb, CL, XX },
2374 { "shrA", Eb, CL, XX },
2375 { "(bad)", XX, XX, XX },
2376 { "sarA", Eb, CL, XX },
252b5132
RH		 2377 },
2378 /* GRP2S_cl */
2379 {
57d91c3c
ILT		 2380 { "rolQ", Ev, CL, XX },
2381 { "rorQ", Ev, CL, XX },
2382 { "rclQ", Ev, CL, XX },
2383 { "rcrQ", Ev, CL, XX },
2384 { "shlQ", Ev, CL, XX },
2385 { "shrQ", Ev, CL, XX },
2386 { "(bad)", XX, XX, XX },
2387 { "sarQ", Ev, CL, XX }
252b5132
RH		 2388 },
2389 /* GRP3b */
2390 {
57d91c3c
ILT		 2391 { "testA", Eb, Ib, XX },
2392 { "(bad)", Eb, XX, XX },
2393 { "notA", Eb, XX, XX },
2394 { "negA", Eb, XX, XX },
2395 { "mulB", AL, Eb, XX },
2396 { "imulB", AL, Eb, XX },
2397 { "divB", AL, Eb, XX },
2398 { "idivB", AL, Eb, XX }
252b5132
RH		 2399 },
2400 /* GRP3S */
2401 {
57d91c3c
ILT		 2402 { "testQ", Ev, Iv, XX },
2403 { "(bad)", XX, XX, XX },
2404 { "notQ", Ev, XX, XX },
2405 { "negQ", Ev, XX, XX },
2406 { "mulS", eAX, Ev, XX },
2407 { "imulS", eAX, Ev, XX },
2408 { "divS", eAX, Ev, XX },
2409 { "idivS", eAX, Ev, XX },
252b5132
RH		 2410 },
2411 /* GRP4 */
2412 {
57d91c3c
ILT		 2413 { "incA", Eb, XX, XX },
2414 { "decA", Eb, XX, XX },
2415 { "(bad)", XX, XX, XX },
2416 { "(bad)", XX, XX, XX },
2417 { "(bad)", XX, XX, XX },
2418 { "(bad)", XX, XX, XX },
2419 { "(bad)", XX, XX, XX },
2420 { "(bad)", XX, XX, XX },
252b5132
RH		 2421 },
2422 /* GRP5 */
2423 {
57d91c3c
ILT		 2424 { "incQ", Ev, XX, XX },
2425 { "decQ", Ev, XX, XX },
52b15da3
JH		 2426 { "callI", indirEv, XX, XX },
2427 { "lcallI", indirEv, XX, XX },
2428 { "jmpI", indirEv, XX, XX },
2429 { "ljmpI", indirEv, XX, XX },
57d91c3c
ILT		 2430 { "pushQ", Ev, XX, XX },
2431 { "(bad)", XX, XX, XX },
252b5132
RH		 2432 },
2433 /* GRP6 */
2434 {
57d91c3c
ILT		 2435 { "sldt", Ew, XX, XX },
2436 { "str", Ew, XX, XX },
2437 { "lldt", Ew, XX, XX },
2438 { "ltr", Ew, XX, XX },
2439 { "verr", Ew, XX, XX },
2440 { "verw", Ew, XX, XX },
2441 { "(bad)", XX, XX, XX },
2442 { "(bad)", XX, XX, XX }
252b5132
RH		 2443 },
2444 /* GRP7 */
2445 {
57d91c3c
ILT		 2446 { "sgdt", Ew, XX, XX },
2447 { "sidt", Ew, XX, XX },
2448 { "lgdt", Ew, XX, XX },
2449 { "lidt", Ew, XX, XX },
2450 { "smsw", Ew, XX, XX },
2451 { "(bad)", XX, XX, XX },
2452 { "lmsw", Ew, XX, XX },
2453 { "invlpg", Ew, XX, XX },
252b5132
RH		 2454 },
2455 /* GRP8 */
2456 {
57d91c3c
ILT		 2457 { "(bad)", XX, XX, XX },
2458 { "(bad)", XX, XX, XX },
2459 { "(bad)", XX, XX, XX },
2460 { "(bad)", XX, XX, XX },
2461 { "btQ", Ev, Ib, XX },
2462 { "btsQ", Ev, Ib, XX },
2463 { "btrQ", Ev, Ib, XX },
2464 { "btcQ", Ev, Ib, XX },
252b5132
RH		 2465 },
2466 /* GRP9 */
2467 {
57d91c3c
ILT		 2468 { "(bad)", XX, XX, XX },
2469 { "cmpxchg8b", Ev, XX, XX },
2470 { "(bad)", XX, XX, XX },
2471 { "(bad)", XX, XX, XX },
2472 { "(bad)", XX, XX, XX },
2473 { "(bad)", XX, XX, XX },
2474 { "(bad)", XX, XX, XX },
2475 { "(bad)", XX, XX, XX },
252b5132
RH		 2476 },
2477 /* GRP10 */
2478 {
57d91c3c
ILT		 2479 { "(bad)", XX, XX, XX },
2480 { "(bad)", XX, XX, XX },
2481 { "psrlw", MS, Ib, XX },
2482 { "(bad)", XX, XX, XX },
2483 { "psraw", MS, Ib, XX },
2484 { "(bad)", XX, XX, XX },
2485 { "psllw", MS, Ib, XX },
2486 { "(bad)", XX, XX, XX },
252b5132
RH		 2487 },
2488 /* GRP11 */
2489 {
57d91c3c
ILT		 2490 { "(bad)", XX, XX, XX },
2491 { "(bad)", XX, XX, XX },
2492 { "psrld", MS, Ib, XX },
2493 { "(bad)", XX, XX, XX },
2494 { "psrad", MS, Ib, XX },
2495 { "(bad)", XX, XX, XX },
2496 { "pslld", MS, Ib, XX },
2497 { "(bad)", XX, XX, XX },
252b5132
RH		 2498 },
2499 /* GRP12 */
2500 {
57d91c3c
ILT		 2501 { "(bad)", XX, XX, XX },
2502 { "(bad)", XX, XX, XX },
2503 { "psrlq", MS, Ib, XX },
2504 { "(bad)", XX, XX, XX },
2505 { "(bad)", XX, XX, XX },
2506 { "(bad)", XX, XX, XX },
2507 { "psllq", MS, Ib, XX },
2508 { "(bad)", XX, XX, XX },
252b5132
RH		 2509 },
2510 /* GRP13 */
2511 {
57d91c3c
ILT		 2512 { "fxsave", Ev, XX, XX },
2513 { "fxrstor", Ev, XX, XX },
2514 { "ldmxcsr", Ev, XX, XX },
2515 { "stmxcsr", Ev, XX, XX },
2516 { "(bad)", XX, XX, XX },
2517 { "(bad)", XX, XX, XX },
2518 { "(bad)", XX, XX, XX },
2519 { "sfence", None, XX, XX },
c608c12e
AM		 2520 },
2521 /* GRP14 */
2522 {
57d91c3c
ILT		 2523 { "prefetchnta", Ev, XX, XX },
2524 { "prefetcht0", Ev, XX, XX },
2525 { "prefetcht1", Ev, XX, XX },
2526 { "prefetcht2", Ev, XX, XX },
2527 { "(bad)", XX, XX, XX },
2528 { "(bad)", XX, XX, XX },
2529 { "(bad)", XX, XX, XX },
2530 { "(bad)", XX, XX, XX },
252b5132 2531 },
c608c12e 2532 /* GRPAMD */
252b5132 2533 {
57d91c3c
ILT		 2534 { "prefetch", Eb, XX, XX },
2535 { "prefetchw", Eb, XX, XX },
2536 { "(bad)", XX, XX, XX },
2537 { "(bad)", XX, XX, XX },
2538 { "(bad)", XX, XX, XX },
2539 { "(bad)", XX, XX, XX },
2540 { "(bad)", XX, XX, XX },
2541 { "(bad)", XX, XX, XX },
252b5132
RH		 2542 }
2543
2544};
2545
2da11e11 2546static const struct dis386 prefix_user_table[][2] = {
c608c12e
AM		 2547 /* PREGRP0 */
2548 {
57d91c3c
ILT		 2549 { "addps", XM, EX, XX },
2550 { "addss", XM, EX, XX },
c608c12e
AM		 2551 },
2552 /* PREGRP1 */
2553 {
2554 { "", XM, EX, OPSIMD }, /* See OP_SIMD_SUFFIX */
2555 { "", XM, EX, OPSIMD },
2556 },
2557 /* PREGRP2 */
2558 {
57d91c3c
ILT		 2559 { "cvtpi2ps", XM, EM, XX },
2560 { "cvtsi2ss", XM, Ev, XX },
c608c12e
AM		 2561 },
2562 /* PREGRP3 */
2563 {
57d91c3c
ILT		 2564 { "cvtps2pi", MX, EX, XX },
2565 { "cvtss2si", Gv, EX, XX },
c608c12e
AM		 2566 },
2567 /* PREGRP4 */
2568 {
57d91c3c
ILT		 2569 { "cvttps2pi", MX, EX, XX },
2570 { "cvttss2si", Gv, EX, XX },
c608c12e
AM		 2571 },
2572 /* PREGRP5 */
2573 {
57d91c3c
ILT		 2574 { "divps", XM, EX, XX },
2575 { "divss", XM, EX, XX },
c608c12e
AM		 2576 },
2577 /* PREGRP6 */
2578 {
57d91c3c
ILT		 2579 { "maxps", XM, EX, XX },
2580 { "maxss", XM, EX, XX },
c608c12e
AM		 2581 },
2582 /* PREGRP7 */
2583 {
57d91c3c
ILT		 2584 { "minps", XM, EX, XX },
2585 { "minss", XM, EX, XX },
c608c12e
AM		 2586 },
2587 /* PREGRP8 */
2588 {
57d91c3c
ILT		 2589 { "movups", XM, EX, XX },
2590 { "movss", XM, EX, XX },
c608c12e
AM		 2591 },
2592 /* PREGRP9 */
2593 {
57d91c3c
ILT		 2594 { "movups", EX, XM, XX },
2595 { "movss", EX, XM, XX },
c608c12e
AM		 2596 },
2597 /* PREGRP10 */
2598 {
57d91c3c
ILT		 2599 { "mulps", XM, EX, XX },
2600 { "mulss", XM, EX, XX },
c608c12e
AM		 2601 },
2602 /* PREGRP11 */
2603 {
57d91c3c
ILT		 2604 { "rcpps", XM, EX, XX },
2605 { "rcpss", XM, EX, XX },
c608c12e
AM		 2606 },
2607 /* PREGRP12 */
2608 {
57d91c3c
ILT		 2609 { "rsqrtps", XM, EX, XX },
2610 { "rsqrtss", XM, EX, XX },
c608c12e
AM		 2611 },
2612 /* PREGRP13 */
2613 {
57d91c3c
ILT		 2614 { "sqrtps", XM, EX, XX },
2615 { "sqrtss", XM, EX, XX },
c608c12e
AM		 2616 },
2617 /* PREGRP14 */
2618 {
57d91c3c
ILT		 2619 { "subps", XM, EX, XX },
2620 { "subss", XM, EX, XX },
c608c12e
AM		 2621 }
2622};
2623
2624#define INTERNAL_DISASSEMBLER_ERROR _("<internal disassembler error>")
2625
252b5132
RH		 2626static void
2627ckprefix ()
2628{
52b15da3
JH		 2629 int newrex;
2630 rex = 0;
252b5132 2631 prefixes = 0;
7d421014 2632 used_prefixes = 0;
52b15da3 2633 rex_used = 0;
252b5132
RH		 2634 while (1)
2635 {
2636 FETCH_DATA (the_info, codep + 1);
52b15da3 2637 newrex = 0;
252b5132
RH		 2638 switch (*codep)
2639 {
52b15da3
JH		 2640 /* REX prefixes family. */
2641 case 0x40:
2642 case 0x41:
2643 case 0x42:
2644 case 0x43:
2645 case 0x44:
2646 case 0x45:
2647 case 0x46:
2648 case 0x47:
2649 case 0x48:
2650 case 0x49:
2651 case 0x4a:
2652 case 0x4b:
2653 case 0x4c:
2654 case 0x4d:
2655 case 0x4e:
2656 case 0x4f:
2657 if (mode_64bit)
2658 newrex = *codep;
2659 else
2660 return;
2661 break;
252b5132
RH		 2662 case 0xf3:
2663 prefixes |= PREFIX_REPZ;
2664 break;
2665 case 0xf2:
2666 prefixes |= PREFIX_REPNZ;
2667 break;
2668 case 0xf0:
2669 prefixes |= PREFIX_LOCK;
2670 break;
2671 case 0x2e:
2672 prefixes |= PREFIX_CS;
2673 break;
2674 case 0x36:
2675 prefixes |= PREFIX_SS;
2676 break;
2677 case 0x3e:
2678 prefixes |= PREFIX_DS;
2679 break;
2680 case 0x26:
2681 prefixes |= PREFIX_ES;
2682 break;
2683 case 0x64:
2684 prefixes |= PREFIX_FS;
2685 break;
2686 case 0x65:
2687 prefixes |= PREFIX_GS;
2688 break;
2689 case 0x66:
2690 prefixes |= PREFIX_DATA;
2691 break;
2692 case 0x67:
2693 prefixes |= PREFIX_ADDR;
2694 break;
5076851f 2695 case FWAIT_OPCODE:
252b5132
RH		 2696 /* fwait is really an instruction. If there are prefixes
2697 before the fwait, they belong to the fwait, *not* to the
2698 following instruction. */
2699 if (prefixes)
2700 {
2701 prefixes |= PREFIX_FWAIT;
2702 codep++;
2703 return;
2704 }
2705 prefixes = PREFIX_FWAIT;
2706 break;
2707 default:
2708 return;
2709 }
52b15da3
JH		 2710 /* Rex is ignored when followed by another prefix. */
2711 if (rex)
2712 {
2713 oappend (prefix_name (rex, 0));
2714 oappend (" ");
2715 }
2716 rex = newrex;
252b5132
RH		 2717 codep++;
2718 }
2719}
2720
7d421014
ILT		 2721/* Return the name of the prefix byte PREF, or NULL if PREF is not a
2722 prefix byte. */
2723
2724static const char *
2725prefix_name (pref, sizeflag)
2726 int pref;
2727 int sizeflag;
2728{
2729 switch (pref)
2730 {
52b15da3
JH		 2731 /* REX prefixes family. */
2732 case 0x40:
2733 return "rex";
2734 case 0x41:
2735 return "rexZ";
2736 case 0x42:
2737 return "rexY";
2738 case 0x43:
2739 return "rexYZ";
2740 case 0x44:
2741 return "rexX";
2742 case 0x45:
2743 return "rexXZ";
2744 case 0x46:
2745 return "rexXY";
2746 case 0x47:
2747 return "rexXYZ";
2748 case 0x48:
2749 return "rex64";
2750 case 0x49:
2751 return "rex64Z";
2752 case 0x4a:
2753 return "rex64Y";
2754 case 0x4b:
2755 return "rex64YZ";
2756 case 0x4c:
2757 return "rex64X";
2758 case 0x4d:
2759 return "rex64XZ";
2760 case 0x4e:
2761 return "rex64XY";
2762 case 0x4f:
2763 return "rex64XYZ";
7d421014
ILT		 2764 case 0xf3:
2765 return "repz";
2766 case 0xf2:
2767 return "repnz";
2768 case 0xf0:
2769 return "lock";
2770 case 0x2e:
2771 return "cs";
2772 case 0x36:
2773 return "ss";
2774 case 0x3e:
2775 return "ds";
2776 case 0x26:
2777 return "es";
2778 case 0x64:
2779 return "fs";
2780 case 0x65:
2781 return "gs";
2782 case 0x66:
2783 return (sizeflag & DFLAG) ? "data16" : "data32";
2784 case 0x67:
2785 return (sizeflag & AFLAG) ? "addr16" : "addr32";
2786 case FWAIT_OPCODE:
2787 return "fwait";
2788 default:
2789 return NULL;
2790 }
2791}
2792
252b5132
RH		 2793static char op1out[100], op2out[100], op3out[100];
2794static int op_ad, op_index[3];
2795static unsigned int op_address[3];
52b15da3
JH		 2796static unsigned int op_riprel[3];
2797static bfd_vma start_pc;
252b5132
RH		 2798
2799\f
2800/*
2801 * On the 386's of 1988, the maximum length of an instruction is 15 bytes.
2802 * (see topic "Redundant prefixes" in the "Differences from 8086"
2803 * section of the "Virtual 8086 Mode" chapter.)
2804 * 'pc' should be the address of this instruction, it will
2805 * be used to print the target address if this is a relative jump or call
2806 * The function returns the length of this instruction in bytes.
2807 */
2808
252b5132
RH		 2809static int print_insn_i386
2810 PARAMS ((bfd_vma pc, disassemble_info *info));
2811
2812static char intel_syntax;
2813static char open_char;
2814static char close_char;
2815static char separator_char;
2816static char scale_char;
2817
2818int
2819print_insn_i386_att (pc, info)
2820 bfd_vma pc;
2821 disassemble_info *info;
2822{
2823 intel_syntax = 0;
2824 open_char = '(';
2825 close_char = ')';
2826 separator_char = ',';
2827 scale_char = ',';
2828
2829 return print_insn_i386 (pc, info);
2830}
2831
2832int
2833print_insn_i386_intel (pc, info)
2834 bfd_vma pc;
2835 disassemble_info *info;
2836{
2837 intel_syntax = 1;
2838 open_char = '[';
2839 close_char = ']';
2840 separator_char = '+';
2841 scale_char = '*';
2842
2843 return print_insn_i386 (pc, info);
2844}
2845
2846static int
2847print_insn_i386 (pc, info)
2848 bfd_vma pc;
2849 disassemble_info *info;
2850{
2da11e11 2851 const struct dis386 *dp;
252b5132
RH		 2852 int i;
2853 int two_source_ops;
2854 char *first, *second, *third;
2855 int needcomma;
2856 unsigned char need_modrm;
c608c12e 2857 unsigned char uses_f3_prefix;
57d91c3c
ILT		 2858 VOLATILE int sizeflag;
2859 VOLATILE int orig_sizeflag;
252b5132
RH		 2860
2861 struct dis_private priv;
2862 bfd_byte *inbuf = priv.the_buffer;
2863
52b15da3
JH		 2864 mode_64bit = (info->mach == bfd_mach_x86_64_intel_syntax
2865 || info->mach == bfd_mach_x86_64);
2866
2da11e11 2867 if (info->mach == bfd_mach_i386_i386
52b15da3
JH		 2868 || info->mach == bfd_mach_x86_64
2869 || info->mach == bfd_mach_i386_i386_intel_syntax
2870 || info->mach == bfd_mach_x86_64_intel_syntax)
2da11e11
AM		 2871 sizeflag = AFLAG|DFLAG;
2872 else if (info->mach == bfd_mach_i386_i8086)
2873 sizeflag = 0;
2874 else
2875 abort ();
7d421014 2876 orig_sizeflag = sizeflag;
2da11e11 2877
4fe53c98 2878 /* The output looks better if we put 7 bytes on a line, since that
c608c12e 2879 puts most long word instructions on a single line. */
4fe53c98 2880 info->bytes_per_line = 7;
252b5132
RH		 2881
2882 info->private_data = (PTR) &priv;
2883 priv.max_fetched = priv.the_buffer;
2884 priv.insn_start = pc;
252b5132
RH		 2885
2886 obuf[0] = 0;
2887 op1out[0] = 0;
2888 op2out[0] = 0;
2889 op3out[0] = 0;
2890
2891 op_index[0] = op_index[1] = op_index[2] = -1;
2892
2893 the_info = info;
2894 start_pc = pc;
2895 start_codep = inbuf;
2896 codep = inbuf;
2897
5076851f
ILT		 2898 if (setjmp (priv.bailout) != 0)
2899 {
7d421014
ILT		 2900 const char *name;
2901
5076851f 2902 /* Getting here means we tried for data but didn't get it. That
7d421014
ILT		 2903 means we have an incomplete instruction of some sort. Just
2904 print the first byte as a prefix or a .byte pseudo-op. */
2905 if (codep > inbuf)
5076851f 2906 {
7d421014
ILT		 2907 name = prefix_name (inbuf[0], orig_sizeflag);
2908 if (name != NULL)
2909 (*info->fprintf_func) (info->stream, "%s", name);
2910 else
5076851f 2911 {
7d421014
ILT		 2912 /* Just print the first byte as a .byte instruction. */
2913 (*info->fprintf_func) (info->stream, ".byte 0x%x",
2914 (unsigned int) inbuf[0]);
5076851f 2915 }
5076851f 2916
7d421014 2917 return 1;
5076851f
ILT		 2918 }
2919
2920 return -1;
2921 }
2922
52b15da3 2923 obufp = obuf;
252b5132
RH		 2924 ckprefix ();
2925
2926 insn_codep = codep;
2927
2928 FETCH_DATA (info, codep + 1);
2929 two_source_ops = (*codep == 0x62) || (*codep == 0xc8);
2930
252b5132
RH		 2931 if ((prefixes & PREFIX_FWAIT)
2932 && ((*codep < 0xd8) || (*codep > 0xdf)))
2933 {
7d421014
ILT		 2934 const char *name;
2935
2936 /* fwait not followed by floating point instruction. Print the
2937 first prefix, which is probably fwait itself. */
2938 name = prefix_name (inbuf[0], orig_sizeflag);
2939 if (name == NULL)
2940 name = INTERNAL_DISASSEMBLER_ERROR;
2941 (*info->fprintf_func) (info->stream, "%s", name);
2942 return 1;
252b5132
RH		 2943 }
2944
252b5132
RH		 2945 if (*codep == 0x0f)
2946 {
2947 FETCH_DATA (info, codep + 2);
2948 if (intel_syntax)
2949 dp = &dis386_twobyte_intel[*++codep];
2950 else
2951 dp = &dis386_twobyte_att[*++codep];
2952 need_modrm = twobyte_has_modrm[*codep];
c608c12e 2953 uses_f3_prefix = twobyte_uses_f3_prefix[*codep];
252b5132
RH		 2954 }
2955 else
2956 {
2957 if (intel_syntax)
52b15da3
JH		 2958 if (mode_64bit)
2959 dp = &dis386_64_intel[*codep];
2960 else
2961 dp = &dis386_intel[*codep];
252b5132 2962 else
52b15da3
JH		 2963 if (mode_64bit)
2964 dp = &disx86_64_att[*codep];
2965 else
2966 dp = &dis386_att[*codep];
252b5132 2967 need_modrm = onebyte_has_modrm[*codep];
c608c12e 2968 uses_f3_prefix = 0;
252b5132
RH		 2969 }
2970 codep++;
2971
c608c12e 2972 if (!uses_f3_prefix && (prefixes & PREFIX_REPZ))
7d421014
ILT		 2973 {
2974 oappend ("repz ");
2975 used_prefixes |= PREFIX_REPZ;
2976 }
c608c12e 2977 if (prefixes & PREFIX_REPNZ)
7d421014
ILT		 2978 {
2979 oappend ("repnz ");
2980 used_prefixes |= PREFIX_REPNZ;
2981 }
c608c12e 2982 if (prefixes & PREFIX_LOCK)
7d421014
ILT		 2983 {
2984 oappend ("lock ");
2985 used_prefixes |= PREFIX_LOCK;
2986 }
c608c12e
AM		 2987
2988 if (prefixes & PREFIX_DATA)
2989 sizeflag ^= DFLAG;
2990
2991 if (prefixes & PREFIX_ADDR)
2992 {
2993 sizeflag ^= AFLAG;
2994 if (sizeflag & AFLAG)
2995 oappend ("addr32 ");
2996 else
2997 oappend ("addr16 ");
7d421014 2998 used_prefixes |= PREFIX_ADDR;
c608c12e
AM		 2999 }
3000
252b5132
RH		 3001 if (need_modrm)
3002 {
3003 FETCH_DATA (info, codep + 1);
3004 mod = (*codep >> 6) & 3;
3005 reg = (*codep >> 3) & 7;
3006 rm = *codep & 7;
3007 }
3008
3009 if (dp->name == NULL && dp->bytemode1 == FLOATCODE)
3010 {
3011 dofloat (sizeflag);
3012 }
3013 else
3014 {
3015 if (dp->name == NULL)
c608c12e
AM		 3016 {
3017 switch(dp->bytemode2)
3018 {
3019 case USE_GROUPS:
3020 dp = &grps[dp->bytemode1][reg];
3021 break;
3022 case USE_PREFIX_USER_TABLE:
3023 dp = &prefix_user_table[dp->bytemode1][prefixes & PREFIX_REPZ ? 1 : 0];
7d421014 3024 used_prefixes |= (prefixes & PREFIX_REPZ);
c608c12e
AM		 3025 break;
3026 default:
3027 oappend (INTERNAL_DISASSEMBLER_ERROR);
3028 break;
3029 }
3030 }
252b5132
RH		 3031
3032 putop (dp->name, sizeflag);
3033
3034 obufp = op1out;
3035 op_ad = 2;
3036 if (dp->op1)
3037 (*dp->op1)(dp->bytemode1, sizeflag);
3038
3039 obufp = op2out;
3040 op_ad = 1;
3041 if (dp->op2)
3042 (*dp->op2)(dp->bytemode2, sizeflag);
3043
3044 obufp = op3out;
3045 op_ad = 0;
3046 if (dp->op3)
3047 (*dp->op3)(dp->bytemode3, sizeflag);
3048 }
3049
7d421014
ILT		 3050 /* See if any prefixes were not used. If so, print the first one
3051 separately. If we don't do this, we'll wind up printing an
3052 instruction stream which does not precisely correspond to the
3053 bytes we are disassembling. */
3054 if ((prefixes & ~used_prefixes) != 0)
3055 {
3056 const char *name;
3057
3058 name = prefix_name (inbuf[0], orig_sizeflag);
3059 if (name == NULL)
3060 name = INTERNAL_DISASSEMBLER_ERROR;
3061 (*info->fprintf_func) (info->stream, "%s", name);
3062 return 1;
3063 }
52b15da3
JH		 3064 if (rex & ~rex_used)
3065 {
3066 const char *name;
3067 name = prefix_name (rex | 0x40, orig_sizeflag);
3068 if (name == NULL)
3069 name = INTERNAL_DISASSEMBLER_ERROR;
3070 (*info->fprintf_func) (info->stream, "%s ", name);
3071 }
7d421014 3072
252b5132
RH		 3073 obufp = obuf + strlen (obuf);
3074 for (i = strlen (obuf); i < 6; i++)
3075 oappend (" ");
3076 oappend (" ");
3077 (*info->fprintf_func) (info->stream, "%s", obuf);
3078
3079 /* The enter and bound instructions are printed with operands in the same
3080 order as the intel book; everything else is printed in reverse order. */
2da11e11 3081 if (intel_syntax || two_source_ops)
252b5132
RH		 3082 {
3083 first = op1out;
3084 second = op2out;
3085 third = op3out;
3086 op_ad = op_index[0];
3087 op_index[0] = op_index[2];
3088 op_index[2] = op_ad;
3089 }
3090 else
3091 {
3092 first = op3out;
3093 second = op2out;
3094 third = op1out;
3095 }
3096 needcomma = 0;
3097 if (*first)
3098 {
52b15da3 3099 if (op_index[0] != -1 && !op_riprel[0])
252b5132
RH		 3100 (*info->print_address_func) ((bfd_vma) op_address[op_index[0]], info);
3101 else
3102 (*info->fprintf_func) (info->stream, "%s", first);
3103 needcomma = 1;
3104 }
3105 if (*second)
3106 {
3107 if (needcomma)
3108 (*info->fprintf_func) (info->stream, ",");
52b15da3 3109 if (op_index[1] != -1 && !op_riprel[1])
252b5132
RH		 3110 (*info->print_address_func) ((bfd_vma) op_address[op_index[1]], info);
3111 else
3112 (*info->fprintf_func) (info->stream, "%s", second);
3113 needcomma = 1;
3114 }
3115 if (*third)
3116 {
3117 if (needcomma)
3118 (*info->fprintf_func) (info->stream, ",");
52b15da3 3119 if (op_index[2] != -1 && !op_riprel[2])
252b5132
RH		 3120 (*info->print_address_func) ((bfd_vma) op_address[op_index[2]], info);
3121 else
3122 (*info->fprintf_func) (info->stream, "%s", third);
3123 }
52b15da3
JH		 3124 for (i = 0; i < 3; i++)
3125 if (op_index[i] != -1 && op_riprel[i])
3126 {
3127 (*info->fprintf_func) (info->stream, " # ");
3128 (*info->print_address_func) ((bfd_vma) (start_pc + codep - start_codep
3129 + op_address[op_index[i]]), info);
3130 }
252b5132
RH		 3131 return codep - inbuf;
3132}
3133
2da11e11 3134static const char *float_mem_att[] = {
252b5132
RH		 3135 /* d8 */
3136 "fadds",
3137 "fmuls",
3138 "fcoms",
3139 "fcomps",
3140 "fsubs",
3141 "fsubrs",
3142 "fdivs",
3143 "fdivrs",
3144 /* d9 */
3145 "flds",
3146 "(bad)",
3147 "fsts",
3148 "fstps",
3149 "fldenv",
3150 "fldcw",
3151 "fNstenv",
3152 "fNstcw",
3153 /* da */
3154 "fiaddl",
3155 "fimull",
3156 "ficoml",
3157 "ficompl",
3158 "fisubl",
3159 "fisubrl",
3160 "fidivl",
3161 "fidivrl",
3162 /* db */
3163 "fildl",
3164 "(bad)",
3165 "fistl",
3166 "fistpl",
3167 "(bad)",
3168 "fldt",
3169 "(bad)",
3170 "fstpt",
3171 /* dc */
3172 "faddl",
3173 "fmull",
3174 "fcoml",
3175 "fcompl",
3176 "fsubl",
3177 "fsubrl",
3178 "fdivl",
3179 "fdivrl",
3180 /* dd */
3181 "fldl",
3182 "(bad)",
3183 "fstl",
3184 "fstpl",
3185 "frstor",
3186 "(bad)",
3187 "fNsave",
3188 "fNstsw",
3189 /* de */
3190 "fiadd",
3191 "fimul",
3192 "ficom",
3193 "ficomp",
3194 "fisub",
3195 "fisubr",
3196 "fidiv",
3197 "fidivr",
3198 /* df */
3199 "fild",
3200 "(bad)",
3201 "fist",
3202 "fistp",
3203 "fbld",
3204 "fildll",
3205 "fbstp",
3206 "fistpll",
3207};
3208
2da11e11 3209static const char *float_mem_intel[] = {
252b5132
RH		 3210 /* d8 */
3211 "fadd",
3212 "fmul",
3213 "fcom",
3214 "fcomp",
3215 "fsub",
3216 "fsubr",
3217 "fdiv",
3218 "fdivr",
3219 /* d9 */
3220 "fld",
3221 "(bad)",
3222 "fst",
3223 "fstp",
3224 "fldenv",
3225 "fldcw",
3226 "fNstenv",
3227 "fNstcw",
3228 /* da */
3229 "fiadd",
3230 "fimul",
3231 "ficom",
3232 "ficomp",
3233 "fisub",
3234 "fisubr",
3235 "fidiv",
3236 "fidivr",
3237 /* db */
3238 "fild",
3239 "(bad)",
3240 "fist",
3241 "fistp",
3242 "(bad)",
3243 "fld",
3244 "(bad)",
3245 "fstp",
3246 /* dc */
3247 "fadd",
3248 "fmul",
3249 "fcom",
3250 "fcomp",
3251 "fsub",
3252 "fsubr",
3253 "fdiv",
3254 "fdivr",
3255 /* dd */
3256 "fld",
3257 "(bad)",
3258 "fst",
3259 "fstp",
3260 "frstor",
3261 "(bad)",
3262 "fNsave",
3263 "fNstsw",
3264 /* de */
3265 "fiadd",
3266 "fimul",
3267 "ficom",
3268 "ficomp",
3269 "fisub",
3270 "fisubr",
3271 "fidiv",
3272 "fidivr",
3273 /* df */
3274 "fild",
3275 "(bad)",
3276 "fist",
3277 "fistp",
3278 "fbld",
3279 "fild",
3280 "fbstp",
3281 "fistpll",
3282};
3283
3284#define ST OP_ST, 0
3285#define STi OP_STi, 0
3286
57d91c3c
ILT		 3287#define FGRPd9_2 NULL, NULL, 0, NULL, 0, NULL, 0
3288#define FGRPd9_4 NULL, NULL, 1, NULL, 0, NULL, 0
3289#define FGRPd9_5 NULL, NULL, 2, NULL, 0, NULL, 0
3290#define FGRPd9_6 NULL, NULL, 3, NULL, 0, NULL, 0
3291#define FGRPd9_7 NULL, NULL, 4, NULL, 0, NULL, 0
3292#define FGRPda_5 NULL, NULL, 5, NULL, 0, NULL, 0
3293#define FGRPdb_4 NULL, NULL, 6, NULL, 0, NULL, 0
3294#define FGRPde_3 NULL, NULL, 7, NULL, 0, NULL, 0
3295#define FGRPdf_4 NULL, NULL, 8, NULL, 0, NULL, 0
252b5132 3296
2da11e11 3297static const struct dis386 float_reg[][8] = {
252b5132
RH		 3298 /* d8 */
3299 {
57d91c3c
ILT		 3300 { "fadd", ST, STi, XX },
3301 { "fmul", ST, STi, XX },
3302 { "fcom", STi, XX, XX },
3303 { "fcomp", STi, XX, XX },
3304 { "fsub", ST, STi, XX },
3305 { "fsubr", ST, STi, XX },
3306 { "fdiv", ST, STi, XX },
3307 { "fdivr", ST, STi, XX },
252b5132
RH		 3308 },
3309 /* d9 */
3310 {
57d91c3c
ILT		 3311 { "fld", STi, XX, XX },
3312 { "fxch", STi, XX, XX },
252b5132 3313 { FGRPd9_2 },
57d91c3c 3314 { "(bad)", XX, XX, XX },
252b5132
RH		 3315 { FGRPd9_4 },
3316 { FGRPd9_5 },
3317 { FGRPd9_6 },
3318 { FGRPd9_7 },
3319 },
3320 /* da */
3321 {
57d91c3c
ILT		 3322 { "fcmovb", ST, STi, XX },
3323 { "fcmove", ST, STi, XX },
3324 { "fcmovbe",ST, STi, XX },
3325 { "fcmovu", ST, STi, XX },
3326 { "(bad)", XX, XX, XX },
252b5132 3327 { FGRPda_5 },
57d91c3c
ILT		 3328 { "(bad)", XX, XX, XX },
3329 { "(bad)", XX, XX, XX },
252b5132
RH		 3330 },
3331 /* db */
3332 {
57d91c3c
ILT		 3333 { "fcmovnb",ST, STi, XX },
3334 { "fcmovne",ST, STi, XX },
3335 { "fcmovnbe",ST, STi, XX },
3336 { "fcmovnu",ST, STi, XX },
252b5132 3337 { FGRPdb_4 },
57d91c3c
ILT		 3338 { "fucomi", ST, STi, XX },
3339 { "fcomi", ST, STi, XX },
3340 { "(bad)", XX, XX, XX },
252b5132
RH		 3341 },
3342 /* dc */
3343 {
57d91c3c
ILT		 3344 { "fadd", STi, ST, XX },
3345 { "fmul", STi, ST, XX },
3346 { "(bad)", XX, XX, XX },
3347 { "(bad)", XX, XX, XX },
252b5132 3348#if UNIXWARE_COMPAT
57d91c3c
ILT		 3349 { "fsub", STi, ST, XX },
3350 { "fsubr", STi, ST, XX },
3351 { "fdiv", STi, ST, XX },
3352 { "fdivr", STi, ST, XX },
252b5132 3353#else
57d91c3c
ILT		 3354 { "fsubr", STi, ST, XX },
3355 { "fsub", STi, ST, XX },
3356 { "fdivr", STi, ST, XX },
3357 { "fdiv", STi, ST, XX },
252b5132
RH		 3358#endif
3359 },
3360 /* dd */
3361 {
57d91c3c
ILT		 3362 { "ffree", STi, XX, XX },
3363 { "(bad)", XX, XX, XX },
3364 { "fst", STi, XX, XX },
3365 { "fstp", STi, XX, XX },
3366 { "fucom", STi, XX, XX },
3367 { "fucomp", STi, XX, XX },
3368 { "(bad)", XX, XX, XX },
3369 { "(bad)", XX, XX, XX },
252b5132
RH		 3370 },
3371 /* de */
3372 {
57d91c3c
ILT		 3373 { "faddp", STi, ST, XX },
3374 { "fmulp", STi, ST, XX },
3375 { "(bad)", XX, XX, XX },
252b5132
RH		 3376 { FGRPde_3 },
3377#if UNIXWARE_COMPAT
57d91c3c
ILT		 3378 { "fsubp", STi, ST, XX },
3379 { "fsubrp", STi, ST, XX },
3380 { "fdivp", STi, ST, XX },
3381 { "fdivrp", STi, ST, XX },
252b5132 3382#else
57d91c3c
ILT		 3383 { "fsubrp", STi, ST, XX },
3384 { "fsubp", STi, ST, XX },
3385 { "fdivrp", STi, ST, XX },
3386 { "fdivp", STi, ST, XX },
252b5132
RH		 3387#endif
3388 },
3389 /* df */
3390 {
57d91c3c
ILT		 3391 { "(bad)", XX, XX, XX },
3392 { "(bad)", XX, XX, XX },
3393 { "(bad)", XX, XX, XX },
3394 { "(bad)", XX, XX, XX },
252b5132 3395 { FGRPdf_4 },
57d91c3c
ILT		 3396 { "fucomip",ST, STi, XX },
3397 { "fcomip", ST, STi, XX },
3398 { "(bad)", XX, XX, XX },
252b5132
RH		 3399 },
3400};
3401
3402
3403static char *fgrps[][8] = {
3404 /* d9_2 0 */
3405 {
3406 "fnop","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
3407 },
3408
3409 /* d9_4 1 */
3410 {
3411 "fchs","fabs","(bad)","(bad)","ftst","fxam","(bad)","(bad)",
3412 },
3413
3414 /* d9_5 2 */
3415 {
3416 "fld1","fldl2t","fldl2e","fldpi","fldlg2","fldln2","fldz","(bad)",
3417 },
3418
3419 /* d9_6 3 */
3420 {
3421 "f2xm1","fyl2x","fptan","fpatan","fxtract","fprem1","fdecstp","fincstp",
3422 },
3423
3424 /* d9_7 4 */
3425 {
3426 "fprem","fyl2xp1","fsqrt","fsincos","frndint","fscale","fsin","fcos",
3427 },
3428
3429 /* da_5 5 */
3430 {
3431 "(bad)","fucompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
3432 },
3433
3434 /* db_4 6 */
3435 {
3436 "feni(287 only)","fdisi(287 only)","fNclex","fNinit",
3437 "fNsetpm(287 only)","(bad)","(bad)","(bad)",
3438 },
3439
3440 /* de_3 7 */
3441 {
3442 "(bad)","fcompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
3443 },
3444
3445 /* df_4 8 */
3446 {
3447 "fNstsw","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
3448 },
3449};
3450
3451static void
3452dofloat (sizeflag)
3453 int sizeflag;
3454{
2da11e11 3455 const struct dis386 *dp;
252b5132
RH		 3456 unsigned char floatop;
3457
3458 floatop = codep[-1];
3459
3460 if (mod != 3)
3461 {
3462 if (intel_syntax)
3463 putop (float_mem_intel[(floatop - 0xd8 ) * 8 + reg], sizeflag);
3464 else
3465 putop (float_mem_att[(floatop - 0xd8 ) * 8 + reg], sizeflag);
3466 obufp = op1out;
3467 if (floatop == 0xdb)
3468 OP_E (x_mode, sizeflag);
3469 else if (floatop == 0xdd)
3470 OP_E (d_mode, sizeflag);
2da11e11 3471 else
252b5132
RH		 3472 OP_E (v_mode, sizeflag);
3473 return;
3474 }
3475 codep++;
3476
3477 dp = &float_reg[floatop - 0xd8][reg];
3478 if (dp->name == NULL)
3479 {
3480 putop (fgrps[dp->bytemode1][rm], sizeflag);
3481
3482 /* instruction fnstsw is only one with strange arg */
3483 if (floatop == 0xdf && codep[-1] == 0xe0)
3484 strcpy (op1out, names16[0]);
3485 }
3486 else
3487 {
3488 putop (dp->name, sizeflag);
3489
3490 obufp = op1out;
3491 if (dp->op1)
3492 (*dp->op1)(dp->bytemode1, sizeflag);
3493 obufp = op2out;
3494 if (dp->op2)
3495 (*dp->op2)(dp->bytemode2, sizeflag);
3496 }
3497}
3498
3499/* ARGSUSED */
3500static void
3501OP_ST (ignore, sizeflag)
57d91c3c
ILT		 3502 int ignore ATTRIBUTE_UNUSED;
3503 int sizeflag ATTRIBUTE_UNUSED;
252b5132
RH		 3504{
3505 oappend ("%st");
3506}
3507
3508/* ARGSUSED */
3509static void
3510OP_STi (ignore, sizeflag)
57d91c3c
ILT		 3511 int ignore ATTRIBUTE_UNUSED;
3512 int sizeflag ATTRIBUTE_UNUSED;
252b5132
RH		 3513{
3514 sprintf (scratchbuf, "%%st(%d)", rm);
3515 oappend (scratchbuf);
3516}
3517
3518
3519/* capital letters in template are macros */
3520static void
3521putop (template, sizeflag)
2da11e11 3522 const char *template;
252b5132
RH		 3523 int sizeflag;
3524{
2da11e11 3525 const char *p;
252b5132
RH		 3526
3527 for (p = template; *p; p++)
3528 {
3529 switch (*p)
3530 {
3531 default:
3532 *obufp++ = *p;
3533 break;
3534 case 'A':
3535 if (intel_syntax)
3536 break;
3537 if (mod != 3
3538#ifdef SUFFIX_ALWAYS
3539 || (sizeflag & SUFFIX_ALWAYS)
3540#endif
3541 )
3542 *obufp++ = 'b';
3543 break;
3544 case 'B':
3545 if (intel_syntax)
3546 break;
3547#ifdef SUFFIX_ALWAYS
3548 if (sizeflag & SUFFIX_ALWAYS)
3549 *obufp++ = 'b';
3550#endif
3551 break;
3552 case 'E': /* For jcxz/jecxz */
3553 if (sizeflag & AFLAG)
3554 *obufp++ = 'e';
3555 break;
3556 case 'L':
3557 if (intel_syntax)
3558 break;
3559#ifdef SUFFIX_ALWAYS
3560 if (sizeflag & SUFFIX_ALWAYS)
3561 *obufp++ = 'l';
3562#endif
3563 break;
3564 case 'N':
3565 if ((prefixes & PREFIX_FWAIT) == 0)
3566 *obufp++ = 'n';
7d421014
ILT		 3567 else
3568 used_prefixes |= PREFIX_FWAIT;
252b5132 3569 break;
52b15da3
JH		 3570 case 'O':
3571 USED_REX (REX_MODE64);
3572 if (rex & REX_MODE64)
3573 *obufp++ = 'o';
3574 else
3575 *obufp++ = 'd';
3576 break;
252b5132
RH		 3577 case 'P':
3578 if (intel_syntax)
3579 break;
3580 if ((prefixes & PREFIX_DATA)
52b15da3 3581 || (rex & REX_MODE64)
252b5132
RH		 3582#ifdef SUFFIX_ALWAYS
3583 || (sizeflag & SUFFIX_ALWAYS)
3584#endif
3585 )
3586 {
52b15da3
JH		 3587 USED_REX (REX_MODE64);
3588 if (rex & REX_MODE64)
3589 *obufp++ = 'q';
3590 else
3591 {
3592 if (sizeflag & DFLAG)
3593 *obufp++ = 'l';
3594 else
3595 *obufp++ = 'w';
3596 used_prefixes |= (prefixes & PREFIX_DATA);
3597 }
252b5132
RH		 3598 }
3599 break;
3600 case 'Q':
52b15da3 3601 USED_REX (REX_MODE64);
252b5132
RH		 3602 if (intel_syntax)
3603 break;
3604 if (mod != 3
3605#ifdef SUFFIX_ALWAYS
3606 || (sizeflag & SUFFIX_ALWAYS)
3607#endif
3608 )
3609 {
52b15da3
JH		 3610 if (rex & REX_MODE64)
3611 *obufp++ = 'q';
252b5132 3612 else
52b15da3
JH		 3613 {
3614 if (sizeflag & DFLAG)
3615 *obufp++ = 'l';
3616 else
3617 *obufp++ = 'w';
3618 used_prefixes |= (prefixes & PREFIX_DATA);
3619 }
252b5132
RH		 3620 }
3621 break;
3622 case 'R':
52b15da3 3623 USED_REX (REX_MODE64);
252b5132 3624 if (intel_syntax)
c608c12e 3625 {
52b15da3
JH		 3626 if (rex & REX_MODE64)
3627 {
3628 *obufp++ = 'q';
3629 *obufp++ = 't';
3630 }
3631 else if (sizeflag & DFLAG)
c608c12e
AM		 3632 {
3633 *obufp++ = 'd';
3634 *obufp++ = 'q';
3635 }
3636 else
3637 {
3638 *obufp++ = 'w';
3639 *obufp++ = 'd';
3640 }
3641 }
252b5132 3642 else
c608c12e 3643 {
52b15da3
JH		 3644 if (rex & REX_MODE64)
3645 *obufp++ = 'q';
3646 else if (sizeflag & DFLAG)
c608c12e
AM		 3647 *obufp++ = 'l';
3648 else
3649 *obufp++ = 'w';
3650 }
52b15da3
JH		 3651 if (!(rex & REX_MODE64))
3652 used_prefixes |= (prefixes & PREFIX_DATA);
252b5132
RH		 3653 break;
3654 case 'S':
3655 if (intel_syntax)
3656 break;
3657#ifdef SUFFIX_ALWAYS
3658 if (sizeflag & SUFFIX_ALWAYS)
3659 {
52b15da3
JH		 3660 if (rex & REX_MODE64)
3661 *obufp++ = 'q';
252b5132 3662 else
52b15da3
JH		 3663 {
3664 if (sizeflag & DFLAG)
3665 *obufp++ = 'l';
3666 else
3667 *obufp++ = 'w';
3668 used_prefixes |= (prefixes & PREFIX_DATA);
3669 }
252b5132
RH		 3670 }
3671#endif
3672 break;
52b15da3
JH		 3673 /* implicit operand size 'l' for i386 or 'q' for x86-64 */
3674 case 'I':
3675 if (mode_64bit)
3676 *obufp++ = 'q';
3677 else
3678 {
3679 if ((prefixes & PREFIX_DATA)
3680#ifdef SUFFIX_ALWAYS
3681 || (sizeflag & SUFFIX_ALWAYS)
3682#endif
3683 )
3684 {
3685 if (sizeflag & DFLAG)
3686 *obufp++ = 'l';
3687 else
3688 *obufp++ = 'w';
3689 used_prefixes |= (prefixes & PREFIX_DATA);
3690 }
3691 }
3692 break;
252b5132 3693 case 'W':
252b5132 3694 /* operand size flag for cwtl, cbtw */
52b15da3
JH		 3695 USED_REX (0);
3696 if (rex)
3697 *obufp++ = 'l';
3698 else if (sizeflag & DFLAG)
252b5132
RH		 3699 *obufp++ = 'w';
3700 else
3701 *obufp++ = 'b';
c608c12e
AM		 3702 if (intel_syntax)
3703 {
52b15da3
JH		 3704 if (rex)
3705 {
3706 *obufp++ = 'q';
3707 *obufp++ = 'e';
3708 }
c608c12e
AM		 3709 if (sizeflag & DFLAG)
3710 {
3711 *obufp++ = 'd';
3712 *obufp++ = 'e';
3713 }
3714 else
3715 {
3716 *obufp++ = 'w';
3717 }
3718 }
52b15da3
JH		 3719 if (!rex)
3720 used_prefixes |= (prefixes & PREFIX_DATA);
252b5132
RH		 3721 break;
3722 }
3723 }
3724 *obufp = 0;
3725}
3726
3727static void
3728oappend (s)
2da11e11 3729 const char *s;
252b5132
RH		 3730{
3731 strcpy (obufp, s);
3732 obufp += strlen (s);
3733}
3734
3735static void
3736append_seg ()
3737{
3738 if (prefixes & PREFIX_CS)
7d421014
ILT		 3739 {
3740 oappend ("%cs:");
3741 used_prefixes |= PREFIX_CS;
3742 }
252b5132 3743 if (prefixes & PREFIX_DS)
7d421014
ILT		 3744 {
3745 oappend ("%ds:");
3746 used_prefixes |= PREFIX_DS;
3747 }
252b5132 3748 if (prefixes & PREFIX_SS)
7d421014
ILT		 3749 {
3750 oappend ("%ss:");
3751 used_prefixes |= PREFIX_SS;
3752 }
252b5132 3753 if (prefixes & PREFIX_ES)
7d421014
ILT		 3754 {
3755 oappend ("%es:");
3756 used_prefixes |= PREFIX_ES;
3757 }
252b5132 3758 if (prefixes & PREFIX_FS)
7d421014
ILT		 3759 {
3760 oappend ("%fs:");
3761 used_prefixes |= PREFIX_FS;
3762 }
252b5132 3763 if (prefixes & PREFIX_GS)
7d421014
ILT		 3764 {
3765 oappend ("%gs:");
3766 used_prefixes |= PREFIX_GS;
3767 }
252b5132
RH		 3768}
3769
3770static void
3771OP_indirE (bytemode, sizeflag)
3772 int bytemode;
3773 int sizeflag;
3774{
3775 if (!intel_syntax)
3776 oappend ("*");
3777 OP_E (bytemode, sizeflag);
3778}
3779
52b15da3
JH		 3780static void
3781print_operand_value (buf, hex, disp)
3782 char *buf;
3783 int hex;
3784 bfd_vma disp;
3785{
3786 if (mode_64bit)
3787 {
3788 if (hex)
3789 {
3790 char tmp[30];
3791 int i;
3792 buf[0] = '0';
3793 buf[1] = 'x';
3794 sprintf_vma (tmp, disp);
3795 for (i = 0; tmp[i] == '0' && tmp[i+1]; i++);
3796 strcpy (buf + 2, tmp + i);
3797 }
3798 else
3799 {
3800 bfd_signed_vma v = disp;
3801 char tmp[30];
3802 int i;
3803 if (v < 0)
3804 {
3805 *(buf++) = '-';
3806 v = -disp;
3807 /* Check for possible overflow on 0x8000000000000000 */
3808 if (v < 0)
3809 {
3810 strcpy (buf, "9223372036854775808");
3811 return;
3812 }
3813 }
3814 if (!v)
3815 {
3816 strcpy (buf, "0");
3817 return;
3818 }
3819
3820 i = 0;
3821 tmp[29] = 0;
3822 while (v)
3823 {
3824 tmp[28-i] = (v % 10) + '0';
3825 v /= 10;
3826 i++;
3827 }
3828 strcpy (buf, tmp + 29 - i);
3829 }
3830 }
3831 else
3832 {
3833 if (hex)
3834 sprintf (buf, "0x%x", (unsigned int) disp);
3835 else
3836 sprintf (buf, "%d", (int) disp);
3837 }
3838}
3839
252b5132
RH		 3840static void
3841OP_E (bytemode, sizeflag)
3842 int bytemode;
3843 int sizeflag;
3844{
52b15da3
JH		 3845 bfd_vma disp;
3846 int add = 0;
3847 int riprel = 0;
3848 USED_REX (REX_EXTZ);
3849 if (rex & REX_EXTZ)
3850 add += 8;
252b5132
RH		 3851
3852 /* skip mod/rm byte */
3853 codep++;
3854
3855 if (mod == 3)
3856 {
3857 switch (bytemode)
3858 {
3859 case b_mode:
52b15da3
JH		 3860 USED_REX (0);
3861 if (rex)
3862 oappend (names8rex[rm + add]);
3863 else
3864 oappend (names8[rm + add]);
252b5132
RH		 3865 break;
3866 case w_mode:
52b15da3 3867 oappend (names16[rm + add]);
252b5132 3868 break;
2da11e11 3869 case d_mode:
52b15da3
JH		 3870 oappend (names32[rm + add]);
3871 break;
3872 case q_mode:
3873 oappend (names64[rm + add]);
3874 break;
3875 case m_mode:
3876 if (mode_64bit)
3877 oappend (names64[rm + add]);
3878 else
3879 oappend (names32[rm + add]);
2da11e11 3880 break;
252b5132 3881 case v_mode:
52b15da3
JH		 3882 USED_REX (REX_MODE64);
3883 if (rex & REX_MODE64)
3884 oappend (names64[rm + add]);
3885 else if (sizeflag & DFLAG)
3886 oappend (names32[rm + add]);
252b5132 3887 else
52b15da3 3888 oappend (names16[rm + add]);
7d421014 3889 used_prefixes |= (prefixes & PREFIX_DATA);
252b5132 3890 break;
2da11e11
AM		 3891 case 0:
3892 if ( !(codep[-2] == 0xAE && codep[-1] == 0xF8 /* sfence */))
3893 BadOp(); /* bad sfence,lea,lds,les,lfs,lgs,lss modrm */
c608c12e 3894 break;
252b5132 3895 default:
c608c12e 3896 oappend (INTERNAL_DISASSEMBLER_ERROR);
252b5132
RH		 3897 break;
3898 }
3899 return;
3900 }
3901
3902 disp = 0;
3903 append_seg ();
3904
3905 if (sizeflag & AFLAG) /* 32 bit address mode */
3906 {
3907 int havesib;
3908 int havebase;
3909 int base;
3910 int index = 0;
3911 int scale = 0;
3912
3913 havesib = 0;
3914 havebase = 1;
3915 base = rm;
3916
3917 if (base == 4)
3918 {
3919 havesib = 1;
3920 FETCH_DATA (the_info, codep + 1);
3921 scale = (*codep >> 6) & 3;
3922 index = (*codep >> 3) & 7;
3923 base = *codep & 7;
52b15da3
JH		 3924 USED_REX (REX_EXTY);
3925 USED_REX (REX_EXTZ);
3926 if (rex & REX_EXTY)
3927 index += 8;
3928 if (rex & REX_EXTZ)
3929 base += 8;
252b5132
RH		 3930 codep++;
3931 }
3932
3933 switch (mod)
3934 {
3935 case 0:
52b15da3 3936 if ((base & 7) == 5)
252b5132
RH		 3937 {
3938 havebase = 0;
52b15da3
JH		 3939 if (mode_64bit && !havesib)
3940 riprel = 1;
3941 disp = get32s ();
252b5132
RH		 3942 }
3943 break;
3944 case 1:
3945 FETCH_DATA (the_info, codep + 1);
3946 disp = *codep++;
3947 if ((disp & 0x80) != 0)
3948 disp -= 0x100;
3949 break;
3950 case 2:
52b15da3 3951 disp = get32s ();
252b5132
RH		 3952 break;
3953 }
3954
3955 if (!intel_syntax)
52b15da3 3956 if (mod != 0 || (base & 7) == 5)
252b5132 3957 {
52b15da3 3958 print_operand_value (scratchbuf, !riprel, disp);
252b5132 3959 oappend (scratchbuf);
52b15da3
JH		 3960 if (riprel)
3961 {
3962 set_op (disp, 1);
3963 oappend ("(%rip)");
3964 }
252b5132 3965 }
2da11e11 3966
252b5132
RH		 3967 if (havebase || (havesib && (index != 4 || scale != 0)))
3968 {
3969 if (intel_syntax)
3970 {
3971 switch (bytemode)
3972 {
3973 case b_mode:
52b15da3 3974 oappend ("BYTE PTR ");
252b5132
RH		 3975 break;
3976 case w_mode:
52b15da3 3977 oappend ("WORD PTR ");
252b5132
RH		 3978 break;
3979 case v_mode:
52b15da3 3980 oappend ("DWORD PTR ");
252b5132
RH		 3981 break;
3982 case d_mode:
52b15da3 3983 oappend ("QWORD PTR ");
252b5132 3984 break;
52b15da3
JH		 3985 case m_mode:
3986 if (mode_64bit)
3987 oappend ("DWORD PTR ");
3988 else
3989 oappend ("QWORD PTR ");
3990 break;
252b5132 3991 case x_mode:
52b15da3 3992 oappend ("XWORD PTR ");
252b5132
RH		 3993 break;
3994 default:
3995 break;
3996 }
3997 }
3998 *obufp++ = open_char;
52b15da3
JH		 3999 if (intel_syntax && riprel)
4000 oappend ("rip + ");
252b5132 4001 *obufp = '\0';
52b15da3
JH		 4002 USED_REX (REX_EXTZ);
4003 if (!havesib && (rex & REX_EXTZ))
4004 base += 8;
252b5132 4005 if (havebase)
52b15da3 4006 oappend (mode_64bit ? names64[base] : names32[base]);
252b5132
RH		 4007 if (havesib)
4008 {
4009 if (index != 4)
4010 {
4011 if (intel_syntax)
4012 {
4013 if (havebase)
4014 {
4015 *obufp++ = separator_char;
4016 *obufp = '\0';
4017 }
52b15da3 4018 sprintf (scratchbuf, "%s", mode_64bit ? names64[index] : names32[index]);
252b5132
RH		 4019 }
4020 else
52b15da3 4021 sprintf (scratchbuf, ",%s", mode_64bit ? names64[index] : names32[index]);
252b5132
RH		 4022 oappend (scratchbuf);
4023 }
4024 if (!intel_syntax
2da11e11 4025 || (intel_syntax
252b5132
RH		 4026 && bytemode != b_mode
4027 && bytemode != w_mode
4028 && bytemode != v_mode))
4029 {
4030 *obufp++ = scale_char;
4031 *obufp = '\0';
4032 sprintf (scratchbuf, "%d", 1 << scale);
4033 oappend (scratchbuf);
4034 }
4035 }
4036 if (intel_syntax)
52b15da3 4037 if (mod != 0 || (base & 7) == 5)
252b5132
RH		 4038 {
4039 /* Don't print zero displacements */
52b15da3 4040 if (disp != 0)
252b5132 4041 {
52b15da3 4042 print_operand_value (scratchbuf, 0, disp);
252b5132
RH		 4043 oappend (scratchbuf);
4044 }
4045 }
4046
4047 *obufp++ = close_char;
4048 *obufp = '\0';
4049 }
4050 else if (intel_syntax)
4051 {
52b15da3 4052 if (mod != 0 || (base & 7) == 5)
252b5132
RH		 4053 {
4054 if (prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS
4055 | PREFIX_ES | PREFIX_FS | PREFIX_GS))
4056 ;
4057 else
4058 {
4059 oappend (names_seg[3]);
4060 oappend (":");
4061 }
52b15da3 4062 print_operand_value (scratchbuf, 1, disp);
252b5132
RH		 4063 oappend (scratchbuf);
4064 }
4065 }
4066 }
4067 else
4068 { /* 16 bit address mode */
4069 switch (mod)
4070 {
4071 case 0:
52b15da3 4072 if ((rm & 7) == 6)
252b5132
RH		 4073 {
4074 disp = get16 ();
4075 if ((disp & 0x8000) != 0)
4076 disp -= 0x10000;
4077 }
4078 break;
4079 case 1:
4080 FETCH_DATA (the_info, codep + 1);
4081 disp = *codep++;
4082 if ((disp & 0x80) != 0)
4083 disp -= 0x100;
4084 break;
4085 case 2:
4086 disp = get16 ();
4087 if ((disp & 0x8000) != 0)
4088 disp -= 0x10000;
4089 break;
4090 }
4091
4092 if (!intel_syntax)
52b15da3 4093 if (mod != 0 || (rm & 7) == 6)
252b5132 4094 {
52b15da3 4095 print_operand_value (scratchbuf, 0, disp);
252b5132
RH		 4096 oappend (scratchbuf);
4097 }
4098
52b15da3 4099 if (mod != 0 || (rm & 7) != 6)
252b5132
RH		 4100 {
4101 *obufp++ = open_char;
4102 *obufp = '\0';
52b15da3 4103 oappend (index16[rm + add]);
252b5132
RH		 4104 *obufp++ = close_char;
4105 *obufp = '\0';
4106 }
4107 }
4108}
4109
252b5132
RH		 4110static void
4111OP_G (bytemode, sizeflag)
4112 int bytemode;
4113 int sizeflag;
4114{
52b15da3
JH		 4115 int add = 0;
4116 USED_REX (REX_EXTX);
4117 if (rex & REX_EXTX)
4118 add += 8;
252b5132
RH		 4119 switch (bytemode)
4120 {
4121 case b_mode:
52b15da3
JH		 4122 USED_REX (0);
4123 if (rex)
4124 oappend (names8rex[reg + add]);
4125 else
4126 oappend (names8[reg + add]);
252b5132
RH		 4127 break;
4128 case w_mode:
52b15da3 4129 oappend (names16[reg + add]);
252b5132
RH		 4130 break;
4131 case d_mode:
52b15da3
JH		 4132 oappend (names32[reg + add]);
4133 break;
4134 case q_mode:
4135 oappend (names64[reg + add]);
252b5132
RH		 4136 break;
4137 case v_mode:
52b15da3
JH		 4138 USED_REX (REX_MODE64);
4139 if (rex & REX_MODE64)
4140 oappend (names64[reg + add]);
4141 else if (sizeflag & DFLAG)
4142 oappend (names32[reg + add]);
252b5132 4143 else
52b15da3 4144 oappend (names16[reg + add]);
7d421014 4145 used_prefixes |= (prefixes & PREFIX_DATA);
252b5132
RH		 4146 break;
4147 default:
4148 oappend (INTERNAL_DISASSEMBLER_ERROR);
4149 break;
4150 }
4151}
4152
52b15da3
JH		 4153static bfd_vma
4154get64 ()
4155{
4156 unsigned int a = 0;
4157 unsigned int b = 0;
4158 bfd_vma x = 0;
4159
4160#ifdef BFD64
4161 FETCH_DATA (the_info, codep + 8);
4162 a = *codep++ & 0xff;
4163 a |= (*codep++ & 0xff) << 8;
4164 a |= (*codep++ & 0xff) << 16;
4165 a |= (*codep++ & 0xff) << 24;
4166 b |= (*codep++ & 0xff);
4167 b |= (*codep++ & 0xff) << 8;
4168 b |= (*codep++ & 0xff) << 16;
4169 b |= (*codep++ & 0xff) << 24;
4170 x = a + ((bfd_vma) b << 32);
4171#else
4172 abort();
4173#endif
4174 return x;
4175}
4176
4177static bfd_signed_vma
252b5132
RH		 4178get32 ()
4179{
52b15da3 4180 bfd_signed_vma x = 0;
252b5132
RH		 4181
4182 FETCH_DATA (the_info, codep + 4);
52b15da3
JH		 4183 x = *codep++ & (bfd_signed_vma) 0xff;
4184 x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
4185 x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
4186 x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
4187 return x;
4188}
4189
4190static bfd_signed_vma
4191get32s ()
4192{
4193 bfd_signed_vma x = 0;
4194
4195 FETCH_DATA (the_info, codep + 4);
4196 x = *codep++ & (bfd_signed_vma) 0xff;
4197 x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
4198 x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
4199 x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
4200
4201 x = (x ^ ((bfd_signed_vma) 1 << 31)) - ((bfd_signed_vma) 1 << 31);
4202
252b5132
RH		 4203 return x;
4204}
4205
4206static int
4207get16 ()
4208{
4209 int x = 0;
4210
4211 FETCH_DATA (the_info, codep + 2);
4212 x = *codep++ & 0xff;
4213 x |= (*codep++ & 0xff) << 8;
4214 return x;
4215}
4216
4217static void
52b15da3 4218set_op (op, riprel)
252b5132 4219 unsigned int op;
52b15da3 4220 int riprel;
252b5132
RH		 4221{
4222 op_index[op_ad] = op_ad;
4223 op_address[op_ad] = op;
52b15da3 4224 op_riprel[op_ad] = riprel;
252b5132
RH		 4225}
4226
4227static void
4228OP_REG (code, sizeflag)
4229 int code;
4230 int sizeflag;
4231{
2da11e11 4232 const char *s;
52b15da3
JH		 4233 int add = 0;
4234 USED_REX (REX_EXTZ);
4235 if (rex & REX_EXTZ)
4236 add = 8;
4237
4238 switch (code)
4239 {
4240 case indir_dx_reg:
4241 s = "(%dx)";
4242 break;
4243 case ax_reg: case cx_reg: case dx_reg: case bx_reg:
4244 case sp_reg: case bp_reg: case si_reg: case di_reg:
4245 s = names16[code - ax_reg + add];
4246 break;
4247 case es_reg: case ss_reg: case cs_reg:
4248 case ds_reg: case fs_reg: case gs_reg:
4249 s = names_seg[code - es_reg + add];
4250 break;
4251 case al_reg: case ah_reg: case cl_reg: case ch_reg:
4252 case dl_reg: case dh_reg: case bl_reg: case bh_reg:
4253 USED_REX (0);
4254 if (rex)
4255 s = names8rex[code - al_reg + add];
4256 else
4257 s = names8[code - al_reg];
4258 break;
4259 case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
4260 case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
4261 USED_REX (REX_MODE64);
4262 if (rex & REX_MODE64)
4263 s = names64[code - eAX_reg + add];
4264 else if (sizeflag & DFLAG)
4265 s = names32[code - eAX_reg + add];
4266 else
4267 s = names16[code - eAX_reg + add];
4268 used_prefixes |= (prefixes & PREFIX_DATA);
4269 break;
4270 case rAX_reg: case rCX_reg: case rDX_reg: case rBX_reg:
4271 case rSP_reg: case rBP_reg: case rSI_reg: case rDI_reg:
4272 s = names64[code - rAX_reg + add];
4273 break;
4274 default:
4275 s = INTERNAL_DISASSEMBLER_ERROR;
4276 break;
4277 }
4278 oappend (s);
4279}
4280
4281static void
4282OP_IMREG (code, sizeflag)
4283 int code;
4284 int sizeflag;
4285{
4286 const char *s;
252b5132
RH		 4287
4288 switch (code)
4289 {
4290 case indir_dx_reg:
4291 s = "(%dx)";
4292 break;
4293 case ax_reg: case cx_reg: case dx_reg: case bx_reg:
4294 case sp_reg: case bp_reg: case si_reg: case di_reg:
4295 s = names16[code - ax_reg];
4296 break;
4297 case es_reg: case ss_reg: case cs_reg:
4298 case ds_reg: case fs_reg: case gs_reg:
4299 s = names_seg[code - es_reg];
4300 break;
4301 case al_reg: case ah_reg: case cl_reg: case ch_reg:
4302 case dl_reg: case dh_reg: case bl_reg: case bh_reg:
52b15da3
JH		 4303 USED_REX (0);
4304 if (rex)
4305 s = names8rex[code - al_reg];
4306 else
4307 s = names8[code - al_reg];
252b5132
RH		 4308 break;
4309 case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
4310 case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
52b15da3
JH		 4311 USED_REX (REX_MODE64);
4312 if (rex & REX_MODE64)
4313 s = names64[code - eAX_reg];
4314 else if (sizeflag & DFLAG)
252b5132
RH		 4315 s = names32[code - eAX_reg];
4316 else
4317 s = names16[code - eAX_reg];
7d421014 4318 used_prefixes |= (prefixes & PREFIX_DATA);
252b5132
RH		 4319 break;
4320 default:
4321 s = INTERNAL_DISASSEMBLER_ERROR;
4322 break;
4323 }
4324 oappend (s);
4325}
4326
4327static void
4328OP_I (bytemode, sizeflag)
4329 int bytemode;
4330 int sizeflag;
4331{
52b15da3
JH		 4332 bfd_signed_vma op;
4333 bfd_signed_vma mask = -1;
252b5132
RH		 4334
4335 switch (bytemode)
4336 {
4337 case b_mode:
4338 FETCH_DATA (the_info, codep + 1);
52b15da3
JH		 4339 op = *codep++;
4340 mask = 0xff;
4341 break;
4342 case q_mode:
4343 op = get32s ();
252b5132
RH		 4344 break;
4345 case v_mode:
52b15da3
JH		 4346 USED_REX (REX_MODE64);
4347 if (rex & REX_MODE64)
4348 op = get32s ();
4349 else if (sizeflag & DFLAG)
4350 {
4351 op = get32 ();
4352 mask = 0xffffffff;
4353 }
252b5132 4354 else
52b15da3
JH		 4355 {
4356 op = get16 ();
4357 mask = 0xfffff;
4358 }
7d421014 4359 used_prefixes |= (prefixes & PREFIX_DATA);
252b5132
RH		 4360 break;
4361 case w_mode:
52b15da3 4362 mask = 0xfffff;
252b5132
RH		 4363 op = get16 ();
4364 break;
4365 default:
4366 oappend (INTERNAL_DISASSEMBLER_ERROR);
4367 return;
4368 }
4369
52b15da3
JH		 4370 op &= mask;
4371 scratchbuf[0] = '$';
4372 print_operand_value (scratchbuf + !intel_syntax, 1, op);
4373 oappend (scratchbuf);
4374 scratchbuf[0] = '\0';
4375}
4376
4377static void
4378OP_I64 (bytemode, sizeflag)
4379 int bytemode;
4380 int sizeflag;
4381{
4382 bfd_signed_vma op;
4383 bfd_signed_vma mask = -1;
4384
4385 switch (bytemode)
4386 {
4387 case b_mode:
4388 FETCH_DATA (the_info, codep + 1);
4389 op = *codep++;
4390 mask = 0xff;
4391 break;
4392 case v_mode:
4393 USED_REX (REX_MODE64);
4394 if (rex & REX_MODE64)
4395 op = get64 ();
4396 else if (sizeflag & DFLAG)
4397 {
4398 op = get32 ();
4399 mask = 0xffffffff;
4400 }
4401 else
4402 {
4403 op = get16 ();
4404 mask = 0xfffff;
4405 }
4406 used_prefixes |= (prefixes & PREFIX_DATA);
4407 break;
4408 case w_mode:
4409 mask = 0xfffff;
4410 op = get16 ();
4411 break;
4412 default:
4413 oappend (INTERNAL_DISASSEMBLER_ERROR);
4414 return;
4415 }
4416
4417 op &= mask;
4418 scratchbuf[0] = '$';
4419 print_operand_value (scratchbuf + !intel_syntax, 1, op);
252b5132
RH		 4420 oappend (scratchbuf);
4421 scratchbuf[0] = '\0';
4422}
4423
4424static void
4425OP_sI (bytemode, sizeflag)
4426 int bytemode;
4427 int sizeflag;
4428{
52b15da3
JH		 4429 bfd_signed_vma op;
4430 bfd_signed_vma mask = -1;
252b5132
RH		 4431
4432 switch (bytemode)
4433 {
4434 case b_mode:
4435 FETCH_DATA (the_info, codep + 1);
4436 op = *codep++;
4437 if ((op & 0x80) != 0)
4438 op -= 0x100;
52b15da3 4439 mask = 0xffffffff;
252b5132
RH		 4440 break;
4441 case v_mode:
52b15da3
JH		 4442 USED_REX (REX_MODE64);
4443 if (rex & REX_MODE64)
4444 op = get32s ();
4445 else if (sizeflag & DFLAG)
4446 {
4447 op = get32s ();
4448 mask = 0xffffffff;
4449 }
252b5132
RH		 4450 else
4451 {
52b15da3 4452 mask = 0xffffffff;
252b5132
RH		 4453 op = get16();
4454 if ((op & 0x8000) != 0)
4455 op -= 0x10000;
4456 }
7d421014 4457 used_prefixes |= (prefixes & PREFIX_DATA);
252b5132
RH		 4458 break;
4459 case w_mode:
4460 op = get16 ();
52b15da3 4461 mask = 0xffffffff;
252b5132
RH		 4462 if ((op & 0x8000) != 0)
4463 op -= 0x10000;
4464 break;
4465 default:
4466 oappend (INTERNAL_DISASSEMBLER_ERROR);
4467 return;
4468 }
52b15da3
JH		 4469
4470 scratchbuf[0] = '$';
4471 print_operand_value (scratchbuf + 1, 1, op);
252b5132
RH		 4472 oappend (scratchbuf);
4473}
4474
4475static void
4476OP_J (bytemode, sizeflag)
4477 int bytemode;
4478 int sizeflag;
4479{
52b15da3 4480 bfd_vma disp;
252b5132
RH		 4481 int mask = -1;
4482
4483 switch (bytemode)
4484 {
4485 case b_mode:
4486 FETCH_DATA (the_info, codep + 1);
4487 disp = *codep++;
4488 if ((disp & 0x80) != 0)
4489 disp -= 0x100;
4490 break;
4491 case v_mode:
4492 if (sizeflag & DFLAG)
52b15da3 4493 disp = get32s ();
252b5132
RH		 4494 else
4495 {
4496 disp = get16 ();
4497 /* for some reason, a data16 prefix on a jump instruction
4498 means that the pc is masked to 16 bits after the
4499 displacement is added! */
4500 mask = 0xffff;
4501 }
7d421014 4502 used_prefixes |= (prefixes & PREFIX_DATA);
252b5132
RH		 4503 break;
4504 default:
4505 oappend (INTERNAL_DISASSEMBLER_ERROR);
4506 return;
4507 }
4508 disp = (start_pc + codep - start_codep + disp) & mask;
52b15da3
JH		 4509 set_op (disp, 0);
4510 print_operand_value (scratchbuf, 1, disp);
252b5132
RH		 4511 oappend (scratchbuf);
4512}
4513
4514/* ARGSUSED */
4515static void
4516OP_SEG (dummy, sizeflag)
57d91c3c
ILT		 4517 int dummy ATTRIBUTE_UNUSED;
4518 int sizeflag ATTRIBUTE_UNUSED;
252b5132
RH		 4519{
4520 static char *sreg[] = {
4521 "%es","%cs","%ss","%ds","%fs","%gs","%?","%?",
4522 };
4523
4524 oappend (sreg[reg]);
4525}
4526
c608c12e 4527/* ARGSUSED */
252b5132 4528static void
c608c12e 4529OP_DIR (dummy, sizeflag)
57d91c3c 4530 int dummy ATTRIBUTE_UNUSED;
252b5132
RH		 4531 int sizeflag;
4532{
4533 int seg, offset;
4534
c608c12e 4535 if (sizeflag & DFLAG)
252b5132 4536 {
c608c12e
AM		 4537 offset = get32 ();
4538 seg = get16 ();
252b5132 4539 }
c608c12e
AM		 4540 else
4541 {
4542 offset = get16 ();
4543 seg = get16 ();
4544 }
7d421014 4545 used_prefixes |= (prefixes & PREFIX_DATA);
c608c12e
AM		 4546 sprintf (scratchbuf, "$0x%x,$0x%x", seg, offset);
4547 oappend (scratchbuf);
252b5132
RH		 4548}
4549
4550/* ARGSUSED */
4551static void
52b15da3
JH		 4552OP_OFF (ignored, sizeflag)
4553 int ignored ATTRIBUTE_UNUSED;
252b5132
RH		 4554 int sizeflag;
4555{
52b15da3 4556 bfd_vma off;
252b5132
RH		 4557
4558 append_seg ();
4559
4560 if (sizeflag & AFLAG)
4561 off = get32 ();
4562 else
4563 off = get16 ();
4564
4565 if (intel_syntax)
4566 {
4567 if (!(prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS
4568 | PREFIX_ES | PREFIX_FS | PREFIX_GS)))
4569 {
4570 oappend (names_seg[3]);
4571 oappend (":");
4572 }
4573 }
52b15da3
JH		 4574 print_operand_value (scratchbuf, 1, off);
4575 oappend (scratchbuf);
4576}
4577/* ARGSUSED */
4578static void
4579OP_OFF64 (ignored, sizeflag)
4580 int ignored ATTRIBUTE_UNUSED;
4581 int sizeflag ATTRIBUTE_UNUSED;
4582{
4583 bfd_vma off;
4584
4585 append_seg ();
4586
4587 off = get64();
4588
4589 if (intel_syntax)
4590 {
4591 if (!(prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS
4592 | PREFIX_ES | PREFIX_FS | PREFIX_GS)))
4593 {
4594 oappend (names_seg[3]);
4595 oappend (":");
4596 }
4597 }
4598 print_operand_value (scratchbuf, 1, off);
252b5132
RH		 4599 oappend (scratchbuf);
4600}
4601
4602static void
4603ptr_reg (code, sizeflag)
4604 int code;
4605 int sizeflag;
4606{
2da11e11 4607 const char *s;
252b5132 4608 oappend ("(");
52b15da3
JH		 4609 USED_REX (REX_MODE64);
4610 if (rex & REX_MODE64)
4611 s = names64[code - eAX_reg];
4612 else if (sizeflag & AFLAG)
252b5132
RH		 4613 s = names32[code - eAX_reg];
4614 else
4615 s = names16[code - eAX_reg];
4616 oappend (s);
4617 oappend (")");
4618}
4619
4620static void
4621OP_ESreg (code, sizeflag)
4622 int code;
4623 int sizeflag;
4624{
4625 oappend ("%es:");
4626 ptr_reg (code, sizeflag);
4627}
4628
4629static void
4630OP_DSreg (code, sizeflag)
4631 int code;
4632 int sizeflag;
4633{
4634 if ((prefixes
4635 & (PREFIX_CS
4636 | PREFIX_DS
4637 | PREFIX_SS
4638 | PREFIX_ES
4639 | PREFIX_FS
4640 | PREFIX_GS)) == 0)
4641 prefixes |= PREFIX_DS;
4642 append_seg();
4643 ptr_reg (code, sizeflag);
4644}
4645
252b5132
RH		 4646/* ARGSUSED */
4647static void
4648OP_C (dummy, sizeflag)
57d91c3c
ILT		 4649 int dummy ATTRIBUTE_UNUSED;
4650 int sizeflag ATTRIBUTE_UNUSED;
252b5132 4651{
52b15da3
JH		 4652 int add = 0;
4653 USED_REX (REX_EXTX);
4654 if (rex & REX_EXTX)
4655 add = 8;
4656 sprintf (scratchbuf, "%%cr%d", reg+add);
252b5132
RH		 4657 oappend (scratchbuf);
4658}
4659
4660/* ARGSUSED */
4661static void
4662OP_D (dummy, sizeflag)
57d91c3c
ILT		 4663 int dummy ATTRIBUTE_UNUSED;
4664 int sizeflag ATTRIBUTE_UNUSED;
252b5132 4665{
52b15da3
JH		 4666 int add = 0;
4667 USED_REX (REX_EXTX);
4668 if (rex & REX_EXTX)
4669 add = 8;
4670 sprintf (scratchbuf, "%%db%d", reg+add);
252b5132
RH		 4671 oappend (scratchbuf);
4672}
4673
4674/* ARGSUSED */
4675static void
4676OP_T (dummy, sizeflag)
57d91c3c
ILT		 4677 int dummy ATTRIBUTE_UNUSED;
4678 int sizeflag ATTRIBUTE_UNUSED;
252b5132 4679{
252b5132
RH		 4680 sprintf (scratchbuf, "%%tr%d", reg);
4681 oappend (scratchbuf);
4682}
4683
4684static void
2da11e11 4685OP_Rd (bytemode, sizeflag)
252b5132
RH		 4686 int bytemode;
4687 int sizeflag;
4688{
2da11e11
AM		 4689 if (mod == 3)
4690 OP_E (bytemode, sizeflag);
4691 else
4692 BadOp();
252b5132
RH		 4693}
4694
4695static void
4696OP_MMX (ignore, sizeflag)
57d91c3c
ILT		 4697 int ignore ATTRIBUTE_UNUSED;
4698 int sizeflag ATTRIBUTE_UNUSED;
252b5132
RH		 4699{
4700 sprintf (scratchbuf, "%%mm%d", reg);
4701 oappend (scratchbuf);
4702}
4703
c608c12e
AM		 4704static void
4705OP_XMM (bytemode, sizeflag)
57d91c3c
ILT		 4706 int bytemode ATTRIBUTE_UNUSED;
4707 int sizeflag ATTRIBUTE_UNUSED;
c608c12e
AM		 4708{
4709 sprintf (scratchbuf, "%%xmm%d", reg);
4710 oappend (scratchbuf);
4711}
4712
252b5132
RH		 4713static void
4714OP_EM (bytemode, sizeflag)
4715 int bytemode;
4716 int sizeflag;
4717{
4718 if (mod != 3)
4719 {
4720 OP_E (bytemode, sizeflag);
4721 return;
4722 }
4723
4724 codep++;
4725 sprintf (scratchbuf, "%%mm%d", rm);
4726 oappend (scratchbuf);
4727}
4728
c608c12e
AM		 4729static void
4730OP_EX (bytemode, sizeflag)
4731 int bytemode;
4732 int sizeflag;
4733{
4734 if (mod != 3)
4735 {
4736 OP_E (bytemode, sizeflag);
4737 return;
4738 }
4739
4740 codep++;
4741 sprintf (scratchbuf, "%%xmm%d", rm);
4742 oappend (scratchbuf);
4743}
4744
252b5132 4745static void
2da11e11
AM		 4746OP_MS (bytemode, sizeflag)
4747 int bytemode;
252b5132
RH		 4748 int sizeflag;
4749{
2da11e11
AM		 4750 if (mod == 3)
4751 OP_EM (bytemode, sizeflag);
4752 else
4753 BadOp();
252b5132
RH		 4754}
4755
4756static const char *Suffix3DNow[] = {
4757/* 00 */ NULL, NULL, NULL, NULL,
4758/* 04 */ NULL, NULL, NULL, NULL,
4759/* 08 */ NULL, NULL, NULL, NULL,
9e525108 4760/* 0C */ "pi2fw", "pi2fd", NULL, NULL,
252b5132
RH		 4761/* 10 */ NULL, NULL, NULL, NULL,
4762/* 14 */ NULL, NULL, NULL, NULL,
4763/* 18 */ NULL, NULL, NULL, NULL,
9e525108 4764/* 1C */ "pf2iw", "pf2id", NULL, NULL,
252b5132
RH		 4765/* 20 */ NULL, NULL, NULL, NULL,
4766/* 24 */ NULL, NULL, NULL, NULL,
4767/* 28 */ NULL, NULL, NULL, NULL,
4768/* 2C */ NULL, NULL, NULL, NULL,
4769/* 30 */ NULL, NULL, NULL, NULL,
4770/* 34 */ NULL, NULL, NULL, NULL,
4771/* 38 */ NULL, NULL, NULL, NULL,
4772/* 3C */ NULL, NULL, NULL, NULL,
4773/* 40 */ NULL, NULL, NULL, NULL,
4774/* 44 */ NULL, NULL, NULL, NULL,
4775/* 48 */ NULL, NULL, NULL, NULL,
4776/* 4C */ NULL, NULL, NULL, NULL,
4777/* 50 */ NULL, NULL, NULL, NULL,
4778/* 54 */ NULL, NULL, NULL, NULL,
4779/* 58 */ NULL, NULL, NULL, NULL,
4780/* 5C */ NULL, NULL, NULL, NULL,
4781/* 60 */ NULL, NULL, NULL, NULL,
4782/* 64 */ NULL, NULL, NULL, NULL,
4783/* 68 */ NULL, NULL, NULL, NULL,
4784/* 6C */ NULL, NULL, NULL, NULL,
4785/* 70 */ NULL, NULL, NULL, NULL,
4786/* 74 */ NULL, NULL, NULL, NULL,
4787/* 78 */ NULL, NULL, NULL, NULL,
4788/* 7C */ NULL, NULL, NULL, NULL,
4789/* 80 */ NULL, NULL, NULL, NULL,
4790/* 84 */ NULL, NULL, NULL, NULL,
9e525108
AM		 4791/* 88 */ NULL, NULL, "pfnacc", NULL,
4792/* 8C */ NULL, NULL, "pfpnacc", NULL,
252b5132
RH		 4793/* 90 */ "pfcmpge", NULL, NULL, NULL,
4794/* 94 */ "pfmin", NULL, "pfrcp", "pfrsqrt",
4795/* 98 */ NULL, NULL, "pfsub", NULL,
4796/* 9C */ NULL, NULL, "pfadd", NULL,
4797/* A0 */ "pfcmpgt", NULL, NULL, NULL,
4798/* A4 */ "pfmax", NULL, "pfrcpit1", "pfrsqit1",
4799/* A8 */ NULL, NULL, "pfsubr", NULL,
4800/* AC */ NULL, NULL, "pfacc", NULL,
4801/* B0 */ "pfcmpeq", NULL, NULL, NULL,
4802/* B4 */ "pfmul", NULL, "pfrcpit2", "pfmulhrw",
9e525108 4803/* B8 */ NULL, NULL, NULL, "pswapd",
252b5132
RH		 4804/* BC */ NULL, NULL, NULL, "pavgusb",
4805/* C0 */ NULL, NULL, NULL, NULL,
4806/* C4 */ NULL, NULL, NULL, NULL,
4807/* C8 */ NULL, NULL, NULL, NULL,
4808/* CC */ NULL, NULL, NULL, NULL,
4809/* D0 */ NULL, NULL, NULL, NULL,
4810/* D4 */ NULL, NULL, NULL, NULL,
4811/* D8 */ NULL, NULL, NULL, NULL,
4812/* DC */ NULL, NULL, NULL, NULL,
4813/* E0 */ NULL, NULL, NULL, NULL,
4814/* E4 */ NULL, NULL, NULL, NULL,
4815/* E8 */ NULL, NULL, NULL, NULL,
4816/* EC */ NULL, NULL, NULL, NULL,
4817/* F0 */ NULL, NULL, NULL, NULL,
4818/* F4 */ NULL, NULL, NULL, NULL,
4819/* F8 */ NULL, NULL, NULL, NULL,
4820/* FC */ NULL, NULL, NULL, NULL,
4821};
4822
4823static void
4824OP_3DNowSuffix (bytemode, sizeflag)
57d91c3c
ILT		 4825 int bytemode ATTRIBUTE_UNUSED;
4826 int sizeflag ATTRIBUTE_UNUSED;
252b5132
RH		 4827{
4828 const char *mnemonic;
4829
4830 FETCH_DATA (the_info, codep + 1);
4831 /* AMD 3DNow! instructions are specified by an opcode suffix in the
4832 place where an 8-bit immediate would normally go. ie. the last
4833 byte of the instruction. */
2da11e11 4834 obufp = obuf + strlen(obuf);
c608c12e 4835 mnemonic = Suffix3DNow[*codep++ & 0xff];
252b5132 4836 if (mnemonic)
2da11e11 4837 oappend (mnemonic);
252b5132
RH		 4838 else
4839 {
4840 /* Since a variable sized modrm/sib chunk is between the start
4841 of the opcode (0x0f0f) and the opcode suffix, we need to do
4842 all the modrm processing first, and don't know until now that
4843 we have a bad opcode. This necessitates some cleaning up. */
2da11e11
AM		 4844 op1out[0] = '\0';
4845 op2out[0] = '\0';
4846 BadOp();
252b5132
RH		 4847 }
4848}
c608c12e
AM		 4849
4850
4851static const char *simd_cmp_op [] = {
4852 "eq",
4853 "lt",
4854 "le",
4855 "unord",
4856 "neq",
4857 "nlt",
4858 "nle",
4859 "ord"
4860};
4861
4862static void
4863OP_SIMD_Suffix (bytemode, sizeflag)
57d91c3c
ILT		 4864 int bytemode ATTRIBUTE_UNUSED;
4865 int sizeflag ATTRIBUTE_UNUSED;
c608c12e
AM		 4866{
4867 unsigned int cmp_type;
4868
4869 FETCH_DATA (the_info, codep + 1);
2da11e11 4870 obufp = obuf + strlen(obuf);
c608c12e
AM		 4871 cmp_type = *codep++ & 0xff;
4872 if (cmp_type < 8)
4873 {
4874 sprintf (scratchbuf, "cmp%s%cs",
4875 simd_cmp_op[cmp_type],
4876 prefixes & PREFIX_REPZ ? 's' : 'p');
7d421014 4877 used_prefixes |= (prefixes & PREFIX_REPZ);
2da11e11 4878 oappend (scratchbuf);
c608c12e
AM		 4879 }
4880 else
4881 {
4882 /* We have a bad extension byte. Clean up. */
2da11e11
AM		 4883 op1out[0] = '\0';
4884 op2out[0] = '\0';
4885 BadOp();
c608c12e
AM		 4886 }
4887}
4888
4889static void
4890SIMD_Fixup (extrachar, sizeflag)
4891 int extrachar;
57d91c3c 4892 int sizeflag ATTRIBUTE_UNUSED;
c608c12e
AM		 4893{
4894 /* Change movlps/movhps to movhlps/movlhps for 2 register operand
4895 forms of these instructions. */
4896 if (mod == 3)
4897 {
4898 char *p = obuf + strlen(obuf);
4899 *(p+1) = '\0';
4900 *p = *(p-1);
4901 *(p-1) = *(p-2);
4902 *(p-2) = *(p-3);
4903 *(p-3) = extrachar;
4904 }
4905}
2da11e11
AM		 4906
4907static void BadOp (void)
4908{
4909 codep = insn_codep + 1; /* throw away prefixes and 1st. opcode byte */
4910 oappend ("(bad)");
4911}
GDB Binutils - Deliverables
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