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gdb: add target_ops::supports_displaced_step
[deliverable/binutils-gdb.git] / opcodes / iq2000-ibld.c
CommitLineData
4162bb66 1/* DO NOT EDIT! -*- buffer-read-only: t -*- vi:set ro: */
47b1a55a
SC		 2/* Instruction building/extraction support for iq2000. -*- C -*-
3
47b0e7ad
NC		 4 THIS FILE IS MACHINE GENERATED WITH CGEN: Cpu tools GENerator.
5 - the resultant file is machine generated, cgen-ibld.in isn't
47b1a55a 6
b3adc24a 7 Copyright (C) 1996-2020 Free Software Foundation, Inc.
47b1a55a 8
9b201bb5 9 This file is part of libopcodes.
47b1a55a 10
9b201bb5 11 This library is free software; you can redistribute it and/or modify
47b0e7ad 12 it under the terms of the GNU General Public License as published by
9b201bb5 13 the Free Software Foundation; either version 3, or (at your option)
47b0e7ad 14 any later version.
47b1a55a 15
9b201bb5
NC		 16 It is distributed in the hope that it will be useful, but WITHOUT
17 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
18 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
19 License for more details.
47b1a55a 20
47b0e7ad
NC		 21 You should have received a copy of the GNU General Public License
22 along with this program; if not, write to the Free Software Foundation, Inc.,
23 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
47b1a55a
SC		 24
25/* ??? Eventually more and more of this stuff can go to cpu-independent files.
26 Keep that in mind. */
27
28#include "sysdep.h"
29#include <stdio.h>
30#include "ansidecl.h"
31#include "dis-asm.h"
32#include "bfd.h"
33#include "symcat.h"
34#include "iq2000-desc.h"
35#include "iq2000-opc.h"
fe8afbc4 36#include "cgen/basic-modes.h"
47b1a55a
SC		 37#include "opintl.h"
38#include "safe-ctype.h"
39
47b0e7ad 40#undef min
47b1a55a 41#define min(a,b) ((a) < (b) ? (a) : (b))
47b0e7ad 42#undef max
47b1a55a
SC		 43#define max(a,b) ((a) > (b) ? (a) : (b))
44
45/* Used by the ifield rtx function. */
46#define FLD(f) (fields->f)
47
48static const char * insert_normal
ffead7ae
MM		 49 (CGEN_CPU_DESC, long, unsigned int, unsigned int, unsigned int,
50 unsigned int, unsigned int, unsigned int, CGEN_INSN_BYTES_PTR);
47b1a55a 51static const char * insert_insn_normal
ffead7ae
MM		 52 (CGEN_CPU_DESC, const CGEN_INSN *,
53 CGEN_FIELDS *, CGEN_INSN_BYTES_PTR, bfd_vma);
47b1a55a 54static int extract_normal
ffead7ae
MM		 55 (CGEN_CPU_DESC, CGEN_EXTRACT_INFO *, CGEN_INSN_INT,
56 unsigned int, unsigned int, unsigned int, unsigned int,
57 unsigned int, unsigned int, bfd_vma, long *);
47b1a55a 58static int extract_insn_normal
ffead7ae
MM		 59 (CGEN_CPU_DESC, const CGEN_INSN *, CGEN_EXTRACT_INFO *,
60 CGEN_INSN_INT, CGEN_FIELDS *, bfd_vma);
47b1a55a
SC		 61#if CGEN_INT_INSN_P
62static void put_insn_int_value
ffead7ae 63 (CGEN_CPU_DESC, CGEN_INSN_BYTES_PTR, int, int, CGEN_INSN_INT);
47b1a55a
SC		 64#endif
65#if ! CGEN_INT_INSN_P
66static CGEN_INLINE void insert_1
ffead7ae 67 (CGEN_CPU_DESC, unsigned long, int, int, int, unsigned char *);
47b1a55a 68static CGEN_INLINE int fill_cache
ffead7ae 69 (CGEN_CPU_DESC, CGEN_EXTRACT_INFO *, int, int, bfd_vma);
47b1a55a 70static CGEN_INLINE long extract_1
ffead7ae 71 (CGEN_CPU_DESC, CGEN_EXTRACT_INFO *, int, int, int, unsigned char *, bfd_vma);
47b1a55a
SC		 72#endif
73\f
74/* Operand insertion. */
75
76#if ! CGEN_INT_INSN_P
77
78/* Subroutine of insert_normal. */
79
80static CGEN_INLINE void
ffead7ae
MM		 81insert_1 (CGEN_CPU_DESC cd,
82 unsigned long value,
83 int start,
84 int length,
85 int word_length,
86 unsigned char *bufp)
47b1a55a
SC		 87{
88 unsigned long x,mask;
89 int shift;
90
91 x = cgen_get_insn_value (cd, bufp, word_length);
92
93 /* Written this way to avoid undefined behaviour. */
94 mask = (((1L << (length - 1)) - 1) << 1) | 1;
95 if (CGEN_INSN_LSB0_P)
96 shift = (start + 1) - length;
97 else
98 shift = (word_length - (start + length));
99 x = (x & ~(mask << shift)) | ((value & mask) << shift);
100
101 cgen_put_insn_value (cd, bufp, word_length, (bfd_vma) x);
102}
103
104#endif /* ! CGEN_INT_INSN_P */
105
106/* Default insertion routine.
107
108 ATTRS is a mask of the boolean attributes.
109 WORD_OFFSET is the offset in bits from the start of the insn of the value.
110 WORD_LENGTH is the length of the word in bits in which the value resides.
111 START is the starting bit number in the word, architecture origin.
112 LENGTH is the length of VALUE in bits.
113 TOTAL_LENGTH is the total length of the insn in bits.
114
115 The result is an error message or NULL if success. */
116
117/* ??? This duplicates functionality with bfd's howto table and
118 bfd_install_relocation. */
119/* ??? This doesn't handle bfd_vma's. Create another function when
120 necessary. */
121
122static const char *
ffead7ae
MM		 123insert_normal (CGEN_CPU_DESC cd,
124 long value,
125 unsigned int attrs,
126 unsigned int word_offset,
127 unsigned int start,
128 unsigned int length,
129 unsigned int word_length,
130 unsigned int total_length,
131 CGEN_INSN_BYTES_PTR buffer)
47b1a55a
SC		 132{
133 static char errbuf[100];
134 /* Written this way to avoid undefined behaviour. */
135 unsigned long mask = (((1L << (length - 1)) - 1) << 1) | 1;
136
137 /* If LENGTH is zero, this operand doesn't contribute to the value. */
138 if (length == 0)
139 return NULL;
140
b7cd1872 141 if (word_length > 8 * sizeof (CGEN_INSN_INT))
47b1a55a
SC		 142 abort ();
143
144 /* For architectures with insns smaller than the base-insn-bitsize,
145 word_length may be too big. */
146 if (cd->min_insn_bitsize < cd->base_insn_bitsize)
147 {
148 if (word_offset == 0
149 && word_length > total_length)
150 word_length = total_length;
151 }
152
153 /* Ensure VALUE will fit. */
154 if (CGEN_BOOL_ATTR (attrs, CGEN_IFLD_SIGN_OPT))
155 {
156 long minval = - (1L << (length - 1));
157 unsigned long maxval = mask;
43e65147 158
47b1a55a
SC		 159 if ((value > 0 && (unsigned long) value > maxval)
160 || value < minval)
161 {
162 /* xgettext:c-format */
163 sprintf (errbuf,
164 _("operand out of range (%ld not between %ld and %lu)"),
165 value, minval, maxval);
166 return errbuf;
167 }
168 }
169 else if (! CGEN_BOOL_ATTR (attrs, CGEN_IFLD_SIGNED))
170 {
171 unsigned long maxval = mask;
ed963e2d
NC		 172 unsigned long val = (unsigned long) value;
173
174 /* For hosts with a word size > 32 check to see if value has been sign
175 extended beyond 32 bits. If so then ignore these higher sign bits
176 as the user is attempting to store a 32-bit signed value into an
177 unsigned 32-bit field which is allowed. */
178 if (sizeof (unsigned long) > 4 && ((value >> 32) == -1))
179 val &= 0xFFFFFFFF;
180
181 if (val > maxval)
47b1a55a
SC		 182 {
183 /* xgettext:c-format */
184 sprintf (errbuf,
ed963e2d
NC		 185 _("operand out of range (0x%lx not between 0 and 0x%lx)"),
186 val, maxval);
47b1a55a
SC		 187 return errbuf;
188 }
189 }
190 else
191 {
192 if (! cgen_signed_overflow_ok_p (cd))
193 {
194 long minval = - (1L << (length - 1));
195 long maxval = (1L << (length - 1)) - 1;
43e65147 196
47b1a55a
SC		 197 if (value < minval || value > maxval)
198 {
199 sprintf
200 /* xgettext:c-format */
201 (errbuf, _("operand out of range (%ld not between %ld and %ld)"),
202 value, minval, maxval);
203 return errbuf;
204 }
205 }
206 }
207
208#if CGEN_INT_INSN_P
209
210 {
a143b004 211 int shift_within_word, shift_to_word, shift;
47b1a55a 212
a143b004
AB		 213 /* How to shift the value to BIT0 of the word. */
214 shift_to_word = total_length - (word_offset + word_length);
215
216 /* How to shift the value to the field within the word. */
47b1a55a 217 if (CGEN_INSN_LSB0_P)
a143b004 218 shift_within_word = start + 1 - length;
47b1a55a 219 else
a143b004
AB		 220 shift_within_word = word_length - start - length;
221
222 /* The total SHIFT, then mask in the value. */
223 shift = shift_to_word + shift_within_word;
47b1a55a
SC		 224 *buffer = (*buffer & ~(mask << shift)) | ((value & mask) << shift);
225 }
226
227#else /* ! CGEN_INT_INSN_P */
228
229 {
230 unsigned char *bufp = (unsigned char *) buffer + word_offset / 8;
231
232 insert_1 (cd, value, start, length, word_length, bufp);
233 }
234
235#endif /* ! CGEN_INT_INSN_P */
236
237 return NULL;
238}
239
240/* Default insn builder (insert handler).
241 The instruction is recorded in CGEN_INT_INSN_P byte order (meaning
242 that if CGEN_INSN_BYTES_PTR is an int * and thus, the value is
243 recorded in host byte order, otherwise BUFFER is an array of bytes
244 and the value is recorded in target byte order).
245 The result is an error message or NULL if success. */
246
247static const char *
ffead7ae
MM		 248insert_insn_normal (CGEN_CPU_DESC cd,
249 const CGEN_INSN * insn,
250 CGEN_FIELDS * fields,
251 CGEN_INSN_BYTES_PTR buffer,
252 bfd_vma pc)
47b1a55a
SC		 253{
254 const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn);
255 unsigned long value;
256 const CGEN_SYNTAX_CHAR_TYPE * syn;
257
258 CGEN_INIT_INSERT (cd);
259 value = CGEN_INSN_BASE_VALUE (insn);
260
261 /* If we're recording insns as numbers (rather than a string of bytes),
262 target byte order handling is deferred until later. */
263
264#if CGEN_INT_INSN_P
265
266 put_insn_int_value (cd, buffer, cd->base_insn_bitsize,
267 CGEN_FIELDS_BITSIZE (fields), value);
268
269#else
270
271 cgen_put_insn_value (cd, buffer, min ((unsigned) cd->base_insn_bitsize,
272 (unsigned) CGEN_FIELDS_BITSIZE (fields)),
273 value);
274
275#endif /* ! CGEN_INT_INSN_P */
276
277 /* ??? It would be better to scan the format's fields.
278 Still need to be able to insert a value based on the operand though;
279 e.g. storing a branch displacement that got resolved later.
280 Needs more thought first. */
281
282 for (syn = CGEN_SYNTAX_STRING (syntax); * syn; ++ syn)
283 {
284 const char *errmsg;
285
286 if (CGEN_SYNTAX_CHAR_P (* syn))
287 continue;
288
289 errmsg = (* cd->insert_operand) (cd, CGEN_SYNTAX_FIELD (*syn),
290 fields, buffer, pc);
291 if (errmsg)
292 return errmsg;
293 }
294
295 return NULL;
296}
297
298#if CGEN_INT_INSN_P
299/* Cover function to store an insn value into an integral insn. Must go here
47b0e7ad 300 because it needs <prefix>-desc.h for CGEN_INT_INSN_P. */
47b1a55a
SC		 301
302static void
ffead7ae
MM		 303put_insn_int_value (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
304 CGEN_INSN_BYTES_PTR buf,
305 int length,
306 int insn_length,
307 CGEN_INSN_INT value)
47b1a55a
SC		 308{
309 /* For architectures with insns smaller than the base-insn-bitsize,
310 length may be too big. */
311 if (length > insn_length)
312 *buf = value;
313 else
314 {
315 int shift = insn_length - length;
316 /* Written this way to avoid undefined behaviour. */
317 CGEN_INSN_INT mask = (((1L << (length - 1)) - 1) << 1) | 1;
47b0e7ad 318
47b1a55a
SC		 319 *buf = (*buf & ~(mask << shift)) | ((value & mask) << shift);
320 }
321}
322#endif
323\f
324/* Operand extraction. */
325
326#if ! CGEN_INT_INSN_P
327
328/* Subroutine of extract_normal.
329 Ensure sufficient bytes are cached in EX_INFO.
330 OFFSET is the offset in bytes from the start of the insn of the value.
331 BYTES is the length of the needed value.
332 Returns 1 for success, 0 for failure. */
333
334static CGEN_INLINE int
ffead7ae
MM		 335fill_cache (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
336 CGEN_EXTRACT_INFO *ex_info,
337 int offset,
338 int bytes,
339 bfd_vma pc)
47b1a55a
SC		 340{
341 /* It's doubtful that the middle part has already been fetched so
342 we don't optimize that case. kiss. */
343 unsigned int mask;
344 disassemble_info *info = (disassemble_info *) ex_info->dis_info;
345
346 /* First do a quick check. */
347 mask = (1 << bytes) - 1;
348 if (((ex_info->valid >> offset) & mask) == mask)
349 return 1;
350
351 /* Search for the first byte we need to read. */
352 for (mask = 1 << offset; bytes > 0; --bytes, ++offset, mask <<= 1)
353 if (! (mask & ex_info->valid))
354 break;
355
356 if (bytes)
357 {
358 int status;
359
360 pc += offset;
361 status = (*info->read_memory_func)
362 (pc, ex_info->insn_bytes + offset, bytes, info);
363
364 if (status != 0)
365 {
366 (*info->memory_error_func) (status, pc, info);
367 return 0;
368 }
369
370 ex_info->valid |= ((1 << bytes) - 1) << offset;
371 }
372
373 return 1;
374}
375
376/* Subroutine of extract_normal. */
377
378static CGEN_INLINE long
ffead7ae
MM		 379extract_1 (CGEN_CPU_DESC cd,
380 CGEN_EXTRACT_INFO *ex_info ATTRIBUTE_UNUSED,
381 int start,
382 int length,
383 int word_length,
384 unsigned char *bufp,
385 bfd_vma pc ATTRIBUTE_UNUSED)
47b1a55a
SC		 386{
387 unsigned long x;
388 int shift;
47b0e7ad 389
47b1a55a
SC		 390 x = cgen_get_insn_value (cd, bufp, word_length);
391
392 if (CGEN_INSN_LSB0_P)
393 shift = (start + 1) - length;
394 else
395 shift = (word_length - (start + length));
396 return x >> shift;
397}
398
399#endif /* ! CGEN_INT_INSN_P */
400
401/* Default extraction routine.
402
403 INSN_VALUE is the first base_insn_bitsize bits of the insn in host order,
404 or sometimes less for cases like the m32r where the base insn size is 32
405 but some insns are 16 bits.
406 ATTRS is a mask of the boolean attributes. We only need `SIGNED',
407 but for generality we take a bitmask of all of them.
408 WORD_OFFSET is the offset in bits from the start of the insn of the value.
409 WORD_LENGTH is the length of the word in bits in which the value resides.
410 START is the starting bit number in the word, architecture origin.
411 LENGTH is the length of VALUE in bits.
412 TOTAL_LENGTH is the total length of the insn in bits.
413
414 Returns 1 for success, 0 for failure. */
415
416/* ??? The return code isn't properly used. wip. */
417
418/* ??? This doesn't handle bfd_vma's. Create another function when
419 necessary. */
420
421static int
ffead7ae 422extract_normal (CGEN_CPU_DESC cd,
47b1a55a 423#if ! CGEN_INT_INSN_P
ffead7ae 424 CGEN_EXTRACT_INFO *ex_info,
47b1a55a 425#else
ffead7ae 426 CGEN_EXTRACT_INFO *ex_info ATTRIBUTE_UNUSED,
47b1a55a 427#endif
ffead7ae
MM		 428 CGEN_INSN_INT insn_value,
429 unsigned int attrs,
430 unsigned int word_offset,
431 unsigned int start,
432 unsigned int length,
433 unsigned int word_length,
434 unsigned int total_length,
47b1a55a 435#if ! CGEN_INT_INSN_P
ffead7ae 436 bfd_vma pc,
47b1a55a 437#else
ffead7ae 438 bfd_vma pc ATTRIBUTE_UNUSED,
47b1a55a 439#endif
ffead7ae 440 long *valuep)
47b1a55a
SC		 441{
442 long value, mask;
443
444 /* If LENGTH is zero, this operand doesn't contribute to the value
445 so give it a standard value of zero. */
446 if (length == 0)
447 {
448 *valuep = 0;
449 return 1;
450 }
451
b7cd1872 452 if (word_length > 8 * sizeof (CGEN_INSN_INT))
47b1a55a
SC		 453 abort ();
454
455 /* For architectures with insns smaller than the insn-base-bitsize,
456 word_length may be too big. */
457 if (cd->min_insn_bitsize < cd->base_insn_bitsize)
458 {
ed963e2d
NC		 459 if (word_offset + word_length > total_length)
460 word_length = total_length - word_offset;
47b1a55a
SC		 461 }
462
463 /* Does the value reside in INSN_VALUE, and at the right alignment? */
464
465 if (CGEN_INT_INSN_P || (word_offset == 0 && word_length == total_length))
466 {
467 if (CGEN_INSN_LSB0_P)
468 value = insn_value >> ((word_offset + start + 1) - length);
469 else
470 value = insn_value >> (total_length - ( word_offset + start + length));
471 }
472
473#if ! CGEN_INT_INSN_P
474
475 else
476 {
477 unsigned char *bufp = ex_info->insn_bytes + word_offset / 8;
478
b7cd1872 479 if (word_length > 8 * sizeof (CGEN_INSN_INT))
47b1a55a
SC		 480 abort ();
481
482 if (fill_cache (cd, ex_info, word_offset / 8, word_length / 8, pc) == 0)
2f5dd314
AM		 483 {
484 *valuep = 0;
485 return 0;
486 }
47b1a55a
SC		 487
488 value = extract_1 (cd, ex_info, start, length, word_length, bufp, pc);
489 }
490
491#endif /* ! CGEN_INT_INSN_P */
492
493 /* Written this way to avoid undefined behaviour. */
494 mask = (((1L << (length - 1)) - 1) << 1) | 1;
495
496 value &= mask;
497 /* sign extend? */
498 if (CGEN_BOOL_ATTR (attrs, CGEN_IFLD_SIGNED)
499 && (value & (1L << (length - 1))))
500 value |= ~mask;
501
502 *valuep = value;
503
504 return 1;
505}
506
507/* Default insn extractor.
508
509 INSN_VALUE is the first base_insn_bitsize bits, translated to host order.
510 The extracted fields are stored in FIELDS.
511 EX_INFO is used to handle reading variable length insns.
512 Return the length of the insn in bits, or 0 if no match,
513 or -1 if an error occurs fetching data (memory_error_func will have
514 been called). */
515
516static int
ffead7ae
MM		 517extract_insn_normal (CGEN_CPU_DESC cd,
518 const CGEN_INSN *insn,
519 CGEN_EXTRACT_INFO *ex_info,
520 CGEN_INSN_INT insn_value,
521 CGEN_FIELDS *fields,
522 bfd_vma pc)
47b1a55a
SC		 523{
524 const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn);
525 const CGEN_SYNTAX_CHAR_TYPE *syn;
526
527 CGEN_FIELDS_BITSIZE (fields) = CGEN_INSN_BITSIZE (insn);
528
529 CGEN_INIT_EXTRACT (cd);
530
531 for (syn = CGEN_SYNTAX_STRING (syntax); *syn; ++syn)
532 {
533 int length;
534
535 if (CGEN_SYNTAX_CHAR_P (*syn))
536 continue;
537
538 length = (* cd->extract_operand) (cd, CGEN_SYNTAX_FIELD (*syn),
539 ex_info, insn_value, fields, pc);
540 if (length <= 0)
541 return length;
542 }
543
544 /* We recognized and successfully extracted this insn. */
545 return CGEN_INSN_BITSIZE (insn);
546}
547\f
47b0e7ad 548/* Machine generated code added here. */
47b1a55a
SC		 549
550const char * iq2000_cgen_insert_operand
47b0e7ad 551 (CGEN_CPU_DESC, int, CGEN_FIELDS *, CGEN_INSN_BYTES_PTR, bfd_vma);
47b1a55a
SC		 552
553/* Main entry point for operand insertion.
554
555 This function is basically just a big switch statement. Earlier versions
556 used tables to look up the function to use, but
557 - if the table contains both assembler and disassembler functions then
558 the disassembler contains much of the assembler and vice-versa,
559 - there's a lot of inlining possibilities as things grow,
560 - using a switch statement avoids the function call overhead.
561
562 This function could be moved into `parse_insn_normal', but keeping it
563 separate makes clear the interface between `parse_insn_normal' and each of
564 the handlers. It's also needed by GAS to insert operands that couldn't be
565 resolved during parsing. */
566
567const char *
47b0e7ad
NC		 568iq2000_cgen_insert_operand (CGEN_CPU_DESC cd,
569 int opindex,
570 CGEN_FIELDS * fields,
571 CGEN_INSN_BYTES_PTR buffer,
572 bfd_vma pc ATTRIBUTE_UNUSED)
47b1a55a
SC		 573{
574 const char * errmsg = NULL;
575 unsigned int total_length = CGEN_FIELDS_BITSIZE (fields);
576
577 switch (opindex)
578 {
4030fa5a
NC		 579 case IQ2000_OPERAND__INDEX :
580 errmsg = insert_normal (cd, fields->f_index, 0, 0, 8, 9, 32, total_length, buffer);
581 break;
47b1a55a
SC		 582 case IQ2000_OPERAND_BASE :
583 errmsg = insert_normal (cd, fields->f_rs, 0, 0, 25, 5, 32, total_length, buffer);
584 break;
585 case IQ2000_OPERAND_BASEOFF :
586 errmsg = insert_normal (cd, fields->f_imm, 0, 0, 15, 16, 32, total_length, buffer);
587 break;
588 case IQ2000_OPERAND_BITNUM :
589 errmsg = insert_normal (cd, fields->f_rt, 0, 0, 20, 5, 32, total_length, buffer);
590 break;
591 case IQ2000_OPERAND_BYTECOUNT :
592 errmsg = insert_normal (cd, fields->f_bytecount, 0, 0, 7, 8, 32, total_length, buffer);
593 break;
594 case IQ2000_OPERAND_CAM_Y :
595 errmsg = insert_normal (cd, fields->f_cam_y, 0, 0, 2, 3, 32, total_length, buffer);
596 break;
597 case IQ2000_OPERAND_CAM_Z :
598 errmsg = insert_normal (cd, fields->f_cam_z, 0, 0, 5, 3, 32, total_length, buffer);
599 break;
600 case IQ2000_OPERAND_CM_3FUNC :
601 errmsg = insert_normal (cd, fields->f_cm_3func, 0, 0, 5, 3, 32, total_length, buffer);
602 break;
603 case IQ2000_OPERAND_CM_3Z :
604 errmsg = insert_normal (cd, fields->f_cm_3z, 0, 0, 1, 2, 32, total_length, buffer);
605 break;
606 case IQ2000_OPERAND_CM_4FUNC :
607 errmsg = insert_normal (cd, fields->f_cm_4func, 0, 0, 5, 4, 32, total_length, buffer);
608 break;
609 case IQ2000_OPERAND_CM_4Z :
610 errmsg = insert_normal (cd, fields->f_cm_4z, 0, 0, 2, 3, 32, total_length, buffer);
611 break;
612 case IQ2000_OPERAND_COUNT :
613 errmsg = insert_normal (cd, fields->f_count, 0, 0, 15, 7, 32, total_length, buffer);
614 break;
615 case IQ2000_OPERAND_EXECODE :
616 errmsg = insert_normal (cd, fields->f_excode, 0, 0, 25, 20, 32, total_length, buffer);
617 break;
618 case IQ2000_OPERAND_HI16 :
619 errmsg = insert_normal (cd, fields->f_imm, 0, 0, 15, 16, 32, total_length, buffer);
620 break;
621 case IQ2000_OPERAND_IMM :
622 errmsg = insert_normal (cd, fields->f_imm, 0, 0, 15, 16, 32, total_length, buffer);
623 break;
47b1a55a
SC		 624 case IQ2000_OPERAND_JMPTARG :
625 {
626 long value = fields->f_jtarg;
fe8afbc4 627 value = ((USI) (((value) & (262143))) >> (2));
47b1a55a
SC		 628 errmsg = insert_normal (cd, value, 0|(1<<CGEN_IFLD_ABS_ADDR), 0, 15, 16, 32, total_length, buffer);
629 }
630 break;
631 case IQ2000_OPERAND_JMPTARGQ10 :
632 {
633 long value = fields->f_jtargq10;
fe8afbc4 634 value = ((USI) (((value) & (8388607))) >> (2));
47b1a55a
SC		 635 errmsg = insert_normal (cd, value, 0|(1<<CGEN_IFLD_ABS_ADDR), 0, 20, 21, 32, total_length, buffer);
636 }
637 break;
638 case IQ2000_OPERAND_LO16 :
639 errmsg = insert_normal (cd, fields->f_imm, 0, 0, 15, 16, 32, total_length, buffer);
640 break;
641 case IQ2000_OPERAND_MASK :
642 errmsg = insert_normal (cd, fields->f_mask, 0, 0, 9, 4, 32, total_length, buffer);
643 break;
644 case IQ2000_OPERAND_MASKL :
645 errmsg = insert_normal (cd, fields->f_maskl, 0, 0, 4, 5, 32, total_length, buffer);
646 break;
647 case IQ2000_OPERAND_MASKQ10 :
648 errmsg = insert_normal (cd, fields->f_maskq10, 0, 0, 10, 5, 32, total_length, buffer);
649 break;
650 case IQ2000_OPERAND_MASKR :
651 errmsg = insert_normal (cd, fields->f_rs, 0, 0, 25, 5, 32, total_length, buffer);
652 break;
653 case IQ2000_OPERAND_MLO16 :
654 errmsg = insert_normal (cd, fields->f_imm, 0, 0, 15, 16, 32, total_length, buffer);
655 break;
656 case IQ2000_OPERAND_OFFSET :
657 {
658 long value = fields->f_offset;
fe8afbc4 659 value = ((SI) (((value) - (pc))) >> (2));
47b1a55a
SC		 660 errmsg = insert_normal (cd, value, 0|(1<<CGEN_IFLD_SIGNED)|(1<<CGEN_IFLD_PCREL_ADDR), 0, 15, 16, 32, total_length, buffer);
661 }
662 break;
663 case IQ2000_OPERAND_RD :
664 errmsg = insert_normal (cd, fields->f_rd, 0, 0, 15, 5, 32, total_length, buffer);
665 break;
666 case IQ2000_OPERAND_RD_RS :
667 {
668{
669 FLD (f_rd) = FLD (f_rd_rs);
670 FLD (f_rs) = FLD (f_rd_rs);
671}
672 errmsg = insert_normal (cd, fields->f_rd, 0, 0, 15, 5, 32, total_length, buffer);
673 if (errmsg)
674 break;
675 errmsg = insert_normal (cd, fields->f_rs, 0, 0, 25, 5, 32, total_length, buffer);
676 if (errmsg)
677 break;
678 }
679 break;
680 case IQ2000_OPERAND_RD_RT :
681 {
682{
683 FLD (f_rd) = FLD (f_rd_rt);
684 FLD (f_rt) = FLD (f_rd_rt);
685}
686 errmsg = insert_normal (cd, fields->f_rd, 0, 0, 15, 5, 32, total_length, buffer);
687 if (errmsg)
688 break;
689 errmsg = insert_normal (cd, fields->f_rt, 0, 0, 20, 5, 32, total_length, buffer);
690 if (errmsg)
691 break;
692 }
693 break;
694 case IQ2000_OPERAND_RS :
695 errmsg = insert_normal (cd, fields->f_rs, 0, 0, 25, 5, 32, total_length, buffer);
696 break;
697 case IQ2000_OPERAND_RT :
698 errmsg = insert_normal (cd, fields->f_rt, 0, 0, 20, 5, 32, total_length, buffer);
699 break;
700 case IQ2000_OPERAND_RT_RS :
701 {
702{
703 FLD (f_rt) = FLD (f_rt_rs);
704 FLD (f_rs) = FLD (f_rt_rs);
705}
706 errmsg = insert_normal (cd, fields->f_rt, 0, 0, 20, 5, 32, total_length, buffer);
707 if (errmsg)
708 break;
709 errmsg = insert_normal (cd, fields->f_rs, 0, 0, 25, 5, 32, total_length, buffer);
710 if (errmsg)
711 break;
712 }
713 break;
714 case IQ2000_OPERAND_SHAMT :
715 errmsg = insert_normal (cd, fields->f_shamt, 0, 0, 10, 5, 32, total_length, buffer);
716 break;
717
718 default :
719 /* xgettext:c-format */
a6743a54
AM		 720 opcodes_error_handler
721 (_("internal error: unrecognized field %d while building insn"),
722 opindex);
47b1a55a
SC		 723 abort ();
724 }
725
726 return errmsg;
727}
728
729int iq2000_cgen_extract_operand
47b0e7ad 730 (CGEN_CPU_DESC, int, CGEN_EXTRACT_INFO *, CGEN_INSN_INT, CGEN_FIELDS *, bfd_vma);
47b1a55a
SC		 731
732/* Main entry point for operand extraction.
733 The result is <= 0 for error, >0 for success.
734 ??? Actual values aren't well defined right now.
735
736 This function is basically just a big switch statement. Earlier versions
737 used tables to look up the function to use, but
738 - if the table contains both assembler and disassembler functions then
739 the disassembler contains much of the assembler and vice-versa,
740 - there's a lot of inlining possibilities as things grow,
741 - using a switch statement avoids the function call overhead.
742
743 This function could be moved into `print_insn_normal', but keeping it
744 separate makes clear the interface between `print_insn_normal' and each of
745 the handlers. */
746
747int
47b0e7ad
NC		 748iq2000_cgen_extract_operand (CGEN_CPU_DESC cd,
749 int opindex,
750 CGEN_EXTRACT_INFO *ex_info,
751 CGEN_INSN_INT insn_value,
752 CGEN_FIELDS * fields,
753 bfd_vma pc)
47b1a55a
SC		 754{
755 /* Assume success (for those operands that are nops). */
756 int length = 1;
757 unsigned int total_length = CGEN_FIELDS_BITSIZE (fields);
758
759 switch (opindex)
760 {
4030fa5a
NC		 761 case IQ2000_OPERAND__INDEX :
762 length = extract_normal (cd, ex_info, insn_value, 0, 0, 8, 9, 32, total_length, pc, & fields->f_index);
763 break;
47b1a55a
SC		 764 case IQ2000_OPERAND_BASE :
765 length = extract_normal (cd, ex_info, insn_value, 0, 0, 25, 5, 32, total_length, pc, & fields->f_rs);
766 break;
767 case IQ2000_OPERAND_BASEOFF :
768 length = extract_normal (cd, ex_info, insn_value, 0, 0, 15, 16, 32, total_length, pc, & fields->f_imm);
769 break;
770 case IQ2000_OPERAND_BITNUM :
771 length = extract_normal (cd, ex_info, insn_value, 0, 0, 20, 5, 32, total_length, pc, & fields->f_rt);
772 break;
773 case IQ2000_OPERAND_BYTECOUNT :
774 length = extract_normal (cd, ex_info, insn_value, 0, 0, 7, 8, 32, total_length, pc, & fields->f_bytecount);
775 break;
776 case IQ2000_OPERAND_CAM_Y :
777 length = extract_normal (cd, ex_info, insn_value, 0, 0, 2, 3, 32, total_length, pc, & fields->f_cam_y);
778 break;
779 case IQ2000_OPERAND_CAM_Z :
780 length = extract_normal (cd, ex_info, insn_value, 0, 0, 5, 3, 32, total_length, pc, & fields->f_cam_z);
781 break;
782 case IQ2000_OPERAND_CM_3FUNC :
783 length = extract_normal (cd, ex_info, insn_value, 0, 0, 5, 3, 32, total_length, pc, & fields->f_cm_3func);
784 break;
785 case IQ2000_OPERAND_CM_3Z :
786 length = extract_normal (cd, ex_info, insn_value, 0, 0, 1, 2, 32, total_length, pc, & fields->f_cm_3z);
787 break;
788 case IQ2000_OPERAND_CM_4FUNC :
789 length = extract_normal (cd, ex_info, insn_value, 0, 0, 5, 4, 32, total_length, pc, & fields->f_cm_4func);
790 break;
791 case IQ2000_OPERAND_CM_4Z :
792 length = extract_normal (cd, ex_info, insn_value, 0, 0, 2, 3, 32, total_length, pc, & fields->f_cm_4z);
793 break;
794 case IQ2000_OPERAND_COUNT :
795 length = extract_normal (cd, ex_info, insn_value, 0, 0, 15, 7, 32, total_length, pc, & fields->f_count);
796 break;
797 case IQ2000_OPERAND_EXECODE :
798 length = extract_normal (cd, ex_info, insn_value, 0, 0, 25, 20, 32, total_length, pc, & fields->f_excode);
799 break;
800 case IQ2000_OPERAND_HI16 :
801 length = extract_normal (cd, ex_info, insn_value, 0, 0, 15, 16, 32, total_length, pc, & fields->f_imm);
802 break;
803 case IQ2000_OPERAND_IMM :
804 length = extract_normal (cd, ex_info, insn_value, 0, 0, 15, 16, 32, total_length, pc, & fields->f_imm);
805 break;
47b1a55a
SC		 806 case IQ2000_OPERAND_JMPTARG :
807 {
808 long value;
809 length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_ABS_ADDR), 0, 15, 16, 32, total_length, pc, & value);
810 value = ((((pc) & (0xf0000000))) | (((value) << (2))));
811 fields->f_jtarg = value;
812 }
813 break;
814 case IQ2000_OPERAND_JMPTARGQ10 :
815 {
816 long value;
817 length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_ABS_ADDR), 0, 20, 21, 32, total_length, pc, & value);
818 value = ((((pc) & (0xf0000000))) | (((value) << (2))));
819 fields->f_jtargq10 = value;
820 }
821 break;
822 case IQ2000_OPERAND_LO16 :
823 length = extract_normal (cd, ex_info, insn_value, 0, 0, 15, 16, 32, total_length, pc, & fields->f_imm);
824 break;
825 case IQ2000_OPERAND_MASK :
826 length = extract_normal (cd, ex_info, insn_value, 0, 0, 9, 4, 32, total_length, pc, & fields->f_mask);
827 break;
828 case IQ2000_OPERAND_MASKL :
829 length = extract_normal (cd, ex_info, insn_value, 0, 0, 4, 5, 32, total_length, pc, & fields->f_maskl);
830 break;
831 case IQ2000_OPERAND_MASKQ10 :
832 length = extract_normal (cd, ex_info, insn_value, 0, 0, 10, 5, 32, total_length, pc, & fields->f_maskq10);
833 break;
834 case IQ2000_OPERAND_MASKR :
835 length = extract_normal (cd, ex_info, insn_value, 0, 0, 25, 5, 32, total_length, pc, & fields->f_rs);
836 break;
837 case IQ2000_OPERAND_MLO16 :
838 length = extract_normal (cd, ex_info, insn_value, 0, 0, 15, 16, 32, total_length, pc, & fields->f_imm);
839 break;
840 case IQ2000_OPERAND_OFFSET :
841 {
842 long value;
843 length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED)|(1<<CGEN_IFLD_PCREL_ADDR), 0, 15, 16, 32, total_length, pc, & value);
3e1056a1 844 value = ((((value) * (4))) + (((pc) + (4))));
47b1a55a
SC		 845 fields->f_offset = value;
846 }
847 break;
848 case IQ2000_OPERAND_RD :
849 length = extract_normal (cd, ex_info, insn_value, 0, 0, 15, 5, 32, total_length, pc, & fields->f_rd);
850 break;
851 case IQ2000_OPERAND_RD_RS :
852 {
853 length = extract_normal (cd, ex_info, insn_value, 0, 0, 15, 5, 32, total_length, pc, & fields->f_rd);
854 if (length <= 0) break;
855 length = extract_normal (cd, ex_info, insn_value, 0, 0, 25, 5, 32, total_length, pc, & fields->f_rs);
856 if (length <= 0) break;
857{
858 FLD (f_rd_rs) = FLD (f_rs);
859}
860 }
861 break;
862 case IQ2000_OPERAND_RD_RT :
863 {
864 length = extract_normal (cd, ex_info, insn_value, 0, 0, 15, 5, 32, total_length, pc, & fields->f_rd);
865 if (length <= 0) break;
866 length = extract_normal (cd, ex_info, insn_value, 0, 0, 20, 5, 32, total_length, pc, & fields->f_rt);
867 if (length <= 0) break;
868{
869 FLD (f_rd_rt) = FLD (f_rt);
870}
871 }
872 break;
873 case IQ2000_OPERAND_RS :
874 length = extract_normal (cd, ex_info, insn_value, 0, 0, 25, 5, 32, total_length, pc, & fields->f_rs);
875 break;
876 case IQ2000_OPERAND_RT :
877 length = extract_normal (cd, ex_info, insn_value, 0, 0, 20, 5, 32, total_length, pc, & fields->f_rt);
878 break;
879 case IQ2000_OPERAND_RT_RS :
880 {
881 length = extract_normal (cd, ex_info, insn_value, 0, 0, 20, 5, 32, total_length, pc, & fields->f_rt);
882 if (length <= 0) break;
883 length = extract_normal (cd, ex_info, insn_value, 0, 0, 25, 5, 32, total_length, pc, & fields->f_rs);
884 if (length <= 0) break;
885{
886 FLD (f_rd_rs) = FLD (f_rs);
887}
888 }
889 break;
890 case IQ2000_OPERAND_SHAMT :
891 length = extract_normal (cd, ex_info, insn_value, 0, 0, 10, 5, 32, total_length, pc, & fields->f_shamt);
892 break;
893
894 default :
895 /* xgettext:c-format */
a6743a54
AM		 896 opcodes_error_handler
897 (_("internal error: unrecognized field %d while decoding insn"),
898 opindex);
47b1a55a
SC		 899 abort ();
900 }
901
902 return length;
903}
904
43e65147 905cgen_insert_fn * const iq2000_cgen_insert_handlers[] =
47b1a55a
SC		 906{
907 insert_insn_normal,
908};
909
43e65147 910cgen_extract_fn * const iq2000_cgen_extract_handlers[] =
47b1a55a
SC		 911{
912 extract_insn_normal,
913};
914
47b0e7ad
NC		 915int iq2000_cgen_get_int_operand (CGEN_CPU_DESC, int, const CGEN_FIELDS *);
916bfd_vma iq2000_cgen_get_vma_operand (CGEN_CPU_DESC, int, const CGEN_FIELDS *);
47b1a55a
SC		 917
918/* Getting values from cgen_fields is handled by a collection of functions.
919 They are distinguished by the type of the VALUE argument they return.
920 TODO: floating point, inlining support, remove cases where result type
921 not appropriate. */
922
923int
47b0e7ad
NC		 924iq2000_cgen_get_int_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
925 int opindex,
926 const CGEN_FIELDS * fields)
47b1a55a
SC		 927{
928 int value;
929
930 switch (opindex)
931 {
4030fa5a
NC		 932 case IQ2000_OPERAND__INDEX :
933 value = fields->f_index;
934 break;
47b1a55a
SC		 935 case IQ2000_OPERAND_BASE :
936 value = fields->f_rs;
937 break;
938 case IQ2000_OPERAND_BASEOFF :
939 value = fields->f_imm;
940 break;
941 case IQ2000_OPERAND_BITNUM :
942 value = fields->f_rt;
943 break;
944 case IQ2000_OPERAND_BYTECOUNT :
945 value = fields->f_bytecount;
946 break;
947 case IQ2000_OPERAND_CAM_Y :
948 value = fields->f_cam_y;
949 break;
950 case IQ2000_OPERAND_CAM_Z :
951 value = fields->f_cam_z;
952 break;
953 case IQ2000_OPERAND_CM_3FUNC :
954 value = fields->f_cm_3func;
955 break;
956 case IQ2000_OPERAND_CM_3Z :
957 value = fields->f_cm_3z;
958 break;
959 case IQ2000_OPERAND_CM_4FUNC :
960 value = fields->f_cm_4func;
961 break;
962 case IQ2000_OPERAND_CM_4Z :
963 value = fields->f_cm_4z;
964 break;
965 case IQ2000_OPERAND_COUNT :
966 value = fields->f_count;
967 break;
968 case IQ2000_OPERAND_EXECODE :
969 value = fields->f_excode;
970 break;
971 case IQ2000_OPERAND_HI16 :
972 value = fields->f_imm;
973 break;
974 case IQ2000_OPERAND_IMM :
975 value = fields->f_imm;
976 break;
47b1a55a
SC		 977 case IQ2000_OPERAND_JMPTARG :
978 value = fields->f_jtarg;
979 break;
980 case IQ2000_OPERAND_JMPTARGQ10 :
981 value = fields->f_jtargq10;
982 break;
983 case IQ2000_OPERAND_LO16 :
984 value = fields->f_imm;
985 break;
986 case IQ2000_OPERAND_MASK :
987 value = fields->f_mask;
988 break;
989 case IQ2000_OPERAND_MASKL :
990 value = fields->f_maskl;
991 break;
992 case IQ2000_OPERAND_MASKQ10 :
993 value = fields->f_maskq10;
994 break;
995 case IQ2000_OPERAND_MASKR :
996 value = fields->f_rs;
997 break;
998 case IQ2000_OPERAND_MLO16 :
999 value = fields->f_imm;
1000 break;
1001 case IQ2000_OPERAND_OFFSET :
1002 value = fields->f_offset;
1003 break;
1004 case IQ2000_OPERAND_RD :
1005 value = fields->f_rd;
1006 break;
1007 case IQ2000_OPERAND_RD_RS :
1008 value = fields->f_rd_rs;
1009 break;
1010 case IQ2000_OPERAND_RD_RT :
1011 value = fields->f_rd_rt;
1012 break;
1013 case IQ2000_OPERAND_RS :
1014 value = fields->f_rs;
1015 break;
1016 case IQ2000_OPERAND_RT :
1017 value = fields->f_rt;
1018 break;
1019 case IQ2000_OPERAND_RT_RS :
1020 value = fields->f_rt_rs;
1021 break;
1022 case IQ2000_OPERAND_SHAMT :
1023 value = fields->f_shamt;
1024 break;
1025
1026 default :
1027 /* xgettext:c-format */
a6743a54
AM		 1028 opcodes_error_handler
1029 (_("internal error: unrecognized field %d while getting int operand"),
1030 opindex);
47b1a55a
SC		 1031 abort ();
1032 }
1033
1034 return value;
1035}
1036
1037bfd_vma
47b0e7ad
NC		 1038iq2000_cgen_get_vma_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
1039 int opindex,
1040 const CGEN_FIELDS * fields)
47b1a55a
SC		 1041{
1042 bfd_vma value;
1043
1044 switch (opindex)
1045 {
4030fa5a
NC		 1046 case IQ2000_OPERAND__INDEX :
1047 value = fields->f_index;
1048 break;
47b1a55a
SC		 1049 case IQ2000_OPERAND_BASE :
1050 value = fields->f_rs;
1051 break;
1052 case IQ2000_OPERAND_BASEOFF :
1053 value = fields->f_imm;
1054 break;
1055 case IQ2000_OPERAND_BITNUM :
1056 value = fields->f_rt;
1057 break;
1058 case IQ2000_OPERAND_BYTECOUNT :
1059 value = fields->f_bytecount;
1060 break;
1061 case IQ2000_OPERAND_CAM_Y :
1062 value = fields->f_cam_y;
1063 break;
1064 case IQ2000_OPERAND_CAM_Z :
1065 value = fields->f_cam_z;
1066 break;
1067 case IQ2000_OPERAND_CM_3FUNC :
1068 value = fields->f_cm_3func;
1069 break;
1070 case IQ2000_OPERAND_CM_3Z :
1071 value = fields->f_cm_3z;
1072 break;
1073 case IQ2000_OPERAND_CM_4FUNC :
1074 value = fields->f_cm_4func;
1075 break;
1076 case IQ2000_OPERAND_CM_4Z :
1077 value = fields->f_cm_4z;
1078 break;
1079 case IQ2000_OPERAND_COUNT :
1080 value = fields->f_count;
1081 break;
1082 case IQ2000_OPERAND_EXECODE :
1083 value = fields->f_excode;
1084 break;
1085 case IQ2000_OPERAND_HI16 :
1086 value = fields->f_imm;
1087 break;
1088 case IQ2000_OPERAND_IMM :
1089 value = fields->f_imm;
1090 break;
47b1a55a
SC		 1091 case IQ2000_OPERAND_JMPTARG :
1092 value = fields->f_jtarg;
1093 break;
1094 case IQ2000_OPERAND_JMPTARGQ10 :
1095 value = fields->f_jtargq10;
1096 break;
1097 case IQ2000_OPERAND_LO16 :
1098 value = fields->f_imm;
1099 break;
1100 case IQ2000_OPERAND_MASK :
1101 value = fields->f_mask;
1102 break;
1103 case IQ2000_OPERAND_MASKL :
1104 value = fields->f_maskl;
1105 break;
1106 case IQ2000_OPERAND_MASKQ10 :
1107 value = fields->f_maskq10;
1108 break;
1109 case IQ2000_OPERAND_MASKR :
1110 value = fields->f_rs;
1111 break;
1112 case IQ2000_OPERAND_MLO16 :
1113 value = fields->f_imm;
1114 break;
1115 case IQ2000_OPERAND_OFFSET :
1116 value = fields->f_offset;
1117 break;
1118 case IQ2000_OPERAND_RD :
1119 value = fields->f_rd;
1120 break;
1121 case IQ2000_OPERAND_RD_RS :
1122 value = fields->f_rd_rs;
1123 break;
1124 case IQ2000_OPERAND_RD_RT :
1125 value = fields->f_rd_rt;
1126 break;
1127 case IQ2000_OPERAND_RS :
1128 value = fields->f_rs;
1129 break;
1130 case IQ2000_OPERAND_RT :
1131 value = fields->f_rt;
1132 break;
1133 case IQ2000_OPERAND_RT_RS :
1134 value = fields->f_rt_rs;
1135 break;
1136 case IQ2000_OPERAND_SHAMT :
1137 value = fields->f_shamt;
1138 break;
1139
1140 default :
1141 /* xgettext:c-format */
a6743a54
AM		 1142 opcodes_error_handler
1143 (_("internal error: unrecognized field %d while getting vma operand"),
1144 opindex);
47b1a55a
SC		 1145 abort ();
1146 }
1147
1148 return value;
1149}
1150
47b0e7ad
NC		 1151void iq2000_cgen_set_int_operand (CGEN_CPU_DESC, int, CGEN_FIELDS *, int);
1152void iq2000_cgen_set_vma_operand (CGEN_CPU_DESC, int, CGEN_FIELDS *, bfd_vma);
47b1a55a
SC		 1153
1154/* Stuffing values in cgen_fields is handled by a collection of functions.
1155 They are distinguished by the type of the VALUE argument they accept.
1156 TODO: floating point, inlining support, remove cases where argument type
1157 not appropriate. */
1158
1159void
47b0e7ad
NC		 1160iq2000_cgen_set_int_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
1161 int opindex,
1162 CGEN_FIELDS * fields,
1163 int value)
47b1a55a
SC		 1164{
1165 switch (opindex)
1166 {
4030fa5a
NC		 1167 case IQ2000_OPERAND__INDEX :
1168 fields->f_index = value;
1169 break;
47b1a55a
SC		 1170 case IQ2000_OPERAND_BASE :
1171 fields->f_rs = value;
1172 break;
1173 case IQ2000_OPERAND_BASEOFF :
1174 fields->f_imm = value;
1175 break;
1176 case IQ2000_OPERAND_BITNUM :
1177 fields->f_rt = value;
1178 break;
1179 case IQ2000_OPERAND_BYTECOUNT :
1180 fields->f_bytecount = value;
1181 break;
1182 case IQ2000_OPERAND_CAM_Y :
1183 fields->f_cam_y = value;
1184 break;
1185 case IQ2000_OPERAND_CAM_Z :
1186 fields->f_cam_z = value;
1187 break;
1188 case IQ2000_OPERAND_CM_3FUNC :
1189 fields->f_cm_3func = value;
1190 break;
1191 case IQ2000_OPERAND_CM_3Z :
1192 fields->f_cm_3z = value;
1193 break;
1194 case IQ2000_OPERAND_CM_4FUNC :
1195 fields->f_cm_4func = value;
1196 break;
1197 case IQ2000_OPERAND_CM_4Z :
1198 fields->f_cm_4z = value;
1199 break;
1200 case IQ2000_OPERAND_COUNT :
1201 fields->f_count = value;
1202 break;
1203 case IQ2000_OPERAND_EXECODE :
1204 fields->f_excode = value;
1205 break;
1206 case IQ2000_OPERAND_HI16 :
1207 fields->f_imm = value;
1208 break;
1209 case IQ2000_OPERAND_IMM :
1210 fields->f_imm = value;
1211 break;
47b1a55a
SC		 1212 case IQ2000_OPERAND_JMPTARG :
1213 fields->f_jtarg = value;
1214 break;
1215 case IQ2000_OPERAND_JMPTARGQ10 :
1216 fields->f_jtargq10 = value;
1217 break;
1218 case IQ2000_OPERAND_LO16 :
1219 fields->f_imm = value;
1220 break;
1221 case IQ2000_OPERAND_MASK :
1222 fields->f_mask = value;
1223 break;
1224 case IQ2000_OPERAND_MASKL :
1225 fields->f_maskl = value;
1226 break;
1227 case IQ2000_OPERAND_MASKQ10 :
1228 fields->f_maskq10 = value;
1229 break;
1230 case IQ2000_OPERAND_MASKR :
1231 fields->f_rs = value;
1232 break;
1233 case IQ2000_OPERAND_MLO16 :
1234 fields->f_imm = value;
1235 break;
1236 case IQ2000_OPERAND_OFFSET :
1237 fields->f_offset = value;
1238 break;
1239 case IQ2000_OPERAND_RD :
1240 fields->f_rd = value;
1241 break;
1242 case IQ2000_OPERAND_RD_RS :
1243 fields->f_rd_rs = value;
1244 break;
1245 case IQ2000_OPERAND_RD_RT :
1246 fields->f_rd_rt = value;
1247 break;
1248 case IQ2000_OPERAND_RS :
1249 fields->f_rs = value;
1250 break;
1251 case IQ2000_OPERAND_RT :
1252 fields->f_rt = value;
1253 break;
1254 case IQ2000_OPERAND_RT_RS :
1255 fields->f_rt_rs = value;
1256 break;
1257 case IQ2000_OPERAND_SHAMT :
1258 fields->f_shamt = value;
1259 break;
1260
1261 default :
1262 /* xgettext:c-format */
a6743a54
AM		 1263 opcodes_error_handler
1264 (_("internal error: unrecognized field %d while setting int operand"),
1265 opindex);
47b1a55a
SC		 1266 abort ();
1267 }
1268}
1269
1270void
47b0e7ad
NC		 1271iq2000_cgen_set_vma_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
1272 int opindex,
1273 CGEN_FIELDS * fields,
1274 bfd_vma value)
47b1a55a
SC		 1275{
1276 switch (opindex)
1277 {
4030fa5a
NC		 1278 case IQ2000_OPERAND__INDEX :
1279 fields->f_index = value;
1280 break;
47b1a55a
SC		 1281 case IQ2000_OPERAND_BASE :
1282 fields->f_rs = value;
1283 break;
1284 case IQ2000_OPERAND_BASEOFF :
1285 fields->f_imm = value;
1286 break;
1287 case IQ2000_OPERAND_BITNUM :
1288 fields->f_rt = value;
1289 break;
1290 case IQ2000_OPERAND_BYTECOUNT :
1291 fields->f_bytecount = value;
1292 break;
1293 case IQ2000_OPERAND_CAM_Y :
1294 fields->f_cam_y = value;
1295 break;
1296 case IQ2000_OPERAND_CAM_Z :
1297 fields->f_cam_z = value;
1298 break;
1299 case IQ2000_OPERAND_CM_3FUNC :
1300 fields->f_cm_3func = value;
1301 break;
1302 case IQ2000_OPERAND_CM_3Z :
1303 fields->f_cm_3z = value;
1304 break;
1305 case IQ2000_OPERAND_CM_4FUNC :
1306 fields->f_cm_4func = value;
1307 break;
1308 case IQ2000_OPERAND_CM_4Z :
1309 fields->f_cm_4z = value;
1310 break;
1311 case IQ2000_OPERAND_COUNT :
1312 fields->f_count = value;
1313 break;
1314 case IQ2000_OPERAND_EXECODE :
1315 fields->f_excode = value;
1316 break;
1317 case IQ2000_OPERAND_HI16 :
1318 fields->f_imm = value;
1319 break;
1320 case IQ2000_OPERAND_IMM :
1321 fields->f_imm = value;
1322 break;
47b1a55a
SC		 1323 case IQ2000_OPERAND_JMPTARG :
1324 fields->f_jtarg = value;
1325 break;
1326 case IQ2000_OPERAND_JMPTARGQ10 :
1327 fields->f_jtargq10 = value;
1328 break;
1329 case IQ2000_OPERAND_LO16 :
1330 fields->f_imm = value;
1331 break;
1332 case IQ2000_OPERAND_MASK :
1333 fields->f_mask = value;
1334 break;
1335 case IQ2000_OPERAND_MASKL :
1336 fields->f_maskl = value;
1337 break;
1338 case IQ2000_OPERAND_MASKQ10 :
1339 fields->f_maskq10 = value;
1340 break;
1341 case IQ2000_OPERAND_MASKR :
1342 fields->f_rs = value;
1343 break;
1344 case IQ2000_OPERAND_MLO16 :
1345 fields->f_imm = value;
1346 break;
1347 case IQ2000_OPERAND_OFFSET :
1348 fields->f_offset = value;
1349 break;
1350 case IQ2000_OPERAND_RD :
1351 fields->f_rd = value;
1352 break;
1353 case IQ2000_OPERAND_RD_RS :
1354 fields->f_rd_rs = value;
1355 break;
1356 case IQ2000_OPERAND_RD_RT :
1357 fields->f_rd_rt = value;
1358 break;
1359 case IQ2000_OPERAND_RS :
1360 fields->f_rs = value;
1361 break;
1362 case IQ2000_OPERAND_RT :
1363 fields->f_rt = value;
1364 break;
1365 case IQ2000_OPERAND_RT_RS :
1366 fields->f_rt_rs = value;
1367 break;
1368 case IQ2000_OPERAND_SHAMT :
1369 fields->f_shamt = value;
1370 break;
1371
1372 default :
1373 /* xgettext:c-format */
a6743a54
AM		 1374 opcodes_error_handler
1375 (_("internal error: unrecognized field %d while setting vma operand"),
1376 opindex);
47b1a55a
SC		 1377 abort ();
1378 }
1379}
1380
1381/* Function to call before using the instruction builder tables. */
1382
1383void
47b0e7ad 1384iq2000_cgen_init_ibld_table (CGEN_CPU_DESC cd)
47b1a55a
SC		 1385{
1386 cd->insert_handlers = & iq2000_cgen_insert_handlers[0];
1387 cd->extract_handlers = & iq2000_cgen_extract_handlers[0];
1388
1389 cd->insert_operand = iq2000_cgen_insert_operand;
1390 cd->extract_operand = iq2000_cgen_extract_operand;
1391
1392 cd->get_int_operand = iq2000_cgen_get_int_operand;
1393 cd->set_int_operand = iq2000_cgen_set_int_operand;
1394 cd->get_vma_operand = iq2000_cgen_get_vma_operand;
1395 cd->set_vma_operand = iq2000_cgen_set_vma_operand;
1396}
GDB Binutils - Deliverables
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