[deliverable/binutils-gdb.git] / opcodes / microblaze-dis.c

/* Disassemble Xilinx microblaze instructions.

   Copyright (C) 2009-2020 Free Software Foundation, Inc.

   This file is part of the GNU opcodes library.

   This library is free software; you can redistribute it and/or modify
   it under the terms of the GNU General Public License as published by
   the Free Software Foundation; either version 3, or (at your option)
   any later version.

   It is distributed in the hope that it will be useful, but WITHOUT
   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
   License for more details.

   You should have received a copy of the GNU General Public License
   along with this file; see the file COPYING.  If not, write to the
   Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
   MA 02110-1301, USA.  */


#include "sysdep.h"
#define STATIC_TABLE
#define DEFINE_TABLE

#include "disassemble.h"
#include <strings.h>
#include "microblaze-opc.h"
#include "microblaze-dis.h"

#define get_field_rd(buf, instr)   get_field (buf, instr, RD_MASK, RD_LOW)
#define get_field_r1(buf, instr)   get_field (buf, instr, RA_MASK, RA_LOW)
#define get_field_r2(buf, instr)   get_field (buf, instr, RB_MASK, RB_LOW)
#define get_int_field_imm(instr)   ((instr & IMM_MASK) >> IMM_LOW)
#define get_int_field_r1(instr)    ((instr & RA_MASK) >> RA_LOW)

#define NUM_STRBUFS 3
#define STRBUF_SIZE 25

struct string_buf
{
  unsigned int which;
  char str[NUM_STRBUFS][STRBUF_SIZE];
};

static inline char *
strbuf (struct string_buf *buf)
{
#ifdef ENABLE_CHECKING
  if (buf->which >= NUM_STRBUFS)
    abort ();
#endif
  return buf->str[buf->which++];
}

static char *
get_field (struct string_buf *buf, long instr, long mask, unsigned short low)
{
  char *p = strbuf (buf);

  sprintf (p, "%s%d", register_prefix, (int)((instr & mask) >> low));
  return p;
}

static char *
get_field_imm (struct string_buf *buf, long instr)
{
  char *p = strbuf (buf);

  sprintf (p, "%d", (short)((instr & IMM_MASK) >> IMM_LOW));
  return p;
}

static char *
get_field_imm5 (struct string_buf *buf, long instr)
{
  char *p = strbuf (buf);

  sprintf (p, "%d", (short)((instr & IMM5_MASK) >> IMM_LOW));
  return p;
}

static char *
get_field_imm5_mbar (struct string_buf *buf, long instr)
{
  char *p = strbuf (buf);

  sprintf (p, "%d", (short)((instr & IMM5_MBAR_MASK) >> IMM_MBAR));
  return p;
}

static char *
get_field_rfsl (struct string_buf *buf, long instr)
{
  char *p = strbuf (buf);

  sprintf (p, "%s%d", fsl_register_prefix,
	   (short)((instr & RFSL_MASK) >> IMM_LOW));
  return p;
}

static char *
get_field_imm15 (struct string_buf *buf, long instr)
{
  char *p = strbuf (buf);

  sprintf (p, "%d", (short)((instr & IMM15_MASK) >> IMM_LOW));
  return p;
}

static char *
get_field_special (struct string_buf *buf, long instr,
		   struct op_code_struct *op)
{
  char *p = strbuf (buf);
  char *spr;

  switch ((((instr & IMM_MASK) >> IMM_LOW) ^ op->immval_mask))
    {
    case REG_MSR_MASK :
      spr = "msr";
      break;
    case REG_PC_MASK :
      spr = "pc";
      break;
    case REG_EAR_MASK :
      spr = "ear";
      break;
    case REG_ESR_MASK :
      spr = "esr";
      break;
    case REG_FSR_MASK :
      spr = "fsr";
      break;
    case REG_BTR_MASK :
      spr = "btr";
      break;
    case REG_EDR_MASK :
      spr = "edr";
      break;
    case REG_PID_MASK :
      spr = "pid";
      break;
    case REG_ZPR_MASK :
      spr = "zpr";
      break;
    case REG_TLBX_MASK :
      spr = "tlbx";
      break;
    case REG_TLBLO_MASK :
      spr = "tlblo";
      break;
    case REG_TLBHI_MASK :
      spr = "tlbhi";
      break;
    case REG_TLBSX_MASK :
      spr = "tlbsx";
      break;
    case REG_SHR_MASK :
      spr = "shr";
      break;
    case REG_SLR_MASK :
      spr = "slr";
      break;
    default :
      if (((((instr & IMM_MASK) >> IMM_LOW) ^ op->immval_mask) & 0xE000)
	  == REG_PVR_MASK)
	{
	  sprintf (p, "%spvr%d", register_prefix,
		   (unsigned short)(((instr & IMM_MASK) >> IMM_LOW)
				    ^ op->immval_mask) ^ REG_PVR_MASK);
	  return p;
	}
      else
	spr = "pc";
      break;
    }

   sprintf (p, "%s%s", register_prefix, spr);
   return p;
}

static unsigned long
read_insn_microblaze (bfd_vma memaddr,
		      struct disassemble_info *info,
		      struct op_code_struct **opr)
{
  unsigned char       ibytes[4];
  int                 status;
  struct op_code_struct * op;
  unsigned long inst;

  status = info->read_memory_func (memaddr, ibytes, 4, info);

  if (status != 0)
    {
      info->memory_error_func (status, memaddr, info);
      return 0;
    }

  if (info->endian == BFD_ENDIAN_BIG)
    inst = (((unsigned) ibytes[0] << 24) | (ibytes[1] << 16)
	    | (ibytes[2] << 8) | ibytes[3]);
  else if (info->endian == BFD_ENDIAN_LITTLE)
    inst = (((unsigned) ibytes[3] << 24) | (ibytes[2] << 16)
	    | (ibytes[1] << 8) | ibytes[0]);
  else
    abort ();

  /* Just a linear search of the table.  */
  for (op = opcodes; op->name != 0; op ++)
    if (op->bit_sequence == (inst & op->opcode_mask))
      break;

  *opr = op;
  return inst;
}


int
print_insn_microblaze (bfd_vma memaddr, struct disassemble_info * info)
{
  fprintf_ftype       print_func = info->fprintf_func;
  void *              stream = info->stream;
  unsigned long       inst, prev_inst;
  struct op_code_struct * op, *pop;
  int                 immval = 0;
  bfd_boolean         immfound = FALSE;
  static bfd_vma      prev_insn_addr = -1; /* Init the prev insn addr.  */
  static int          prev_insn_vma = -1;  /* Init the prev insn vma.  */
  int                 curr_insn_vma = info->buffer_vma;
  struct string_buf   buf;

  buf.which = 0;
  info->bytes_per_chunk = 4;

  inst = read_insn_microblaze (memaddr, info, &op);
  if (inst == 0)
    return -1;

  if (prev_insn_vma == curr_insn_vma)
    {
      if (memaddr-(info->bytes_per_chunk) == prev_insn_addr)
	{
	  prev_inst = read_insn_microblaze (prev_insn_addr, info, &pop);
	  if (prev_inst == 0)
	    return -1;
	  if (pop->instr == imm)
	    {
	      immval = (get_int_field_imm (prev_inst) << 16) & 0xffff0000;
	      immfound = TRUE;
	    }
	  else
	    {
	      immval = 0;
	      immfound = FALSE;
	    }
	}
    }

  /* Make curr insn as prev insn.  */
  prev_insn_addr = memaddr;
  prev_insn_vma = curr_insn_vma;

  if (op->name == NULL)
    print_func (stream, ".short 0x%04x", (unsigned int) inst);
  else
    {
      print_func (stream, "%s", op->name);

      switch (op->inst_type)
	{
	case INST_TYPE_RD_R1_R2:
	  print_func (stream, "\t%s, %s, %s", get_field_rd (&buf, inst),
		      get_field_r1 (&buf, inst), get_field_r2 (&buf, inst));
	  break;
	case INST_TYPE_RD_R1_IMM:
	  print_func (stream, "\t%s, %s, %s", get_field_rd (&buf, inst),
		      get_field_r1 (&buf, inst), get_field_imm (&buf, inst));
	  if (info->print_address_func && get_int_field_r1 (inst) == 0
	      && info->symbol_at_address_func)
	    {
	      if (immfound)
		immval |= (get_int_field_imm (inst) & 0x0000ffff);
	      else
		{
		  immval = get_int_field_imm (inst);
		  if (immval & 0x8000)
		    immval |= 0xFFFF0000;
		}
	      if (immval > 0 && info->symbol_at_address_func (immval, info))
		{
		  print_func (stream, "\t// ");
		  info->print_address_func (immval, info);
		}
	    }
	  break;
	case INST_TYPE_RD_R1_IMM5:
	  print_func (stream, "\t%s, %s, %s", get_field_rd (&buf, inst),
		      get_field_r1 (&buf, inst), get_field_imm5 (&buf, inst));
	  break;
	case INST_TYPE_RD_RFSL:
	  print_func (stream, "\t%s, %s", get_field_rd (&buf, inst),
		      get_field_rfsl (&buf, inst));
	  break;
	case INST_TYPE_R1_RFSL:
	  print_func (stream, "\t%s, %s", get_field_r1 (&buf, inst),
		      get_field_rfsl (&buf, inst));
	  break;
	case INST_TYPE_RD_SPECIAL:
	  print_func (stream, "\t%s, %s", get_field_rd (&buf, inst),
		      get_field_special (&buf, inst, op));
	  break;
	case INST_TYPE_SPECIAL_R1:
	  print_func (stream, "\t%s, %s", get_field_special (&buf, inst, op),
		      get_field_r1 (&buf, inst));
	  break;
	case INST_TYPE_RD_R1:
	  print_func (stream, "\t%s, %s", get_field_rd (&buf, inst),
		      get_field_r1 (&buf, inst));
	  break;
	case INST_TYPE_R1_R2:
	  print_func (stream, "\t%s, %s", get_field_r1 (&buf, inst),
		      get_field_r2 (&buf, inst));
	  break;
	case INST_TYPE_R1_IMM:
	  print_func (stream, "\t%s, %s", get_field_r1 (&buf, inst),
		      get_field_imm (&buf, inst));
	  /* The non-pc relative instructions are returns, which shouldn't
	     have a label printed.  */
	  if (info->print_address_func && op->inst_offset_type == INST_PC_OFFSET
	      && info->symbol_at_address_func)
	    {
	      if (immfound)
		immval |= (get_int_field_imm (inst) & 0x0000ffff);
	      else
		{
		  immval = get_int_field_imm (inst);
		  if (immval & 0x8000)
		    immval |= 0xFFFF0000;
		}
	      immval += memaddr;
	      if (immval > 0 && info->symbol_at_address_func (immval, info))
		{
		  print_func (stream, "\t// ");
		  info->print_address_func (immval, info);
		}
	      else
		{
		  print_func (stream, "\t\t// ");
		  print_func (stream, "%x", immval);
		}
	    }
	  break;
	case INST_TYPE_RD_IMM:
	  print_func (stream, "\t%s, %s", get_field_rd (&buf, inst),
		      get_field_imm (&buf, inst));
	  if (info->print_address_func && info->symbol_at_address_func)
	    {
	      if (immfound)
		immval |= (get_int_field_imm (inst) & 0x0000ffff);
	      else
		{
		  immval = get_int_field_imm (inst);
		  if (immval & 0x8000)
		    immval |= 0xFFFF0000;
		}
	      if (op->inst_offset_type == INST_PC_OFFSET)
		immval += (int) memaddr;
	      if (info->symbol_at_address_func (immval, info))
		{
		  print_func (stream, "\t// ");
		  info->print_address_func (immval, info);
		}
	    }
	  break;
	case INST_TYPE_IMM:
	  print_func (stream, "\t%s", get_field_imm (&buf, inst));
	  if (info->print_address_func && info->symbol_at_address_func
	      && op->instr != imm)
	    {
	      if (immfound)
		immval |= (get_int_field_imm (inst) & 0x0000ffff);
	      else
		{
		  immval = get_int_field_imm (inst);
		  if (immval & 0x8000)
		    immval |= 0xFFFF0000;
		}
	      if (op->inst_offset_type == INST_PC_OFFSET)
		immval += (int) memaddr;
	      if (immval > 0 && info->symbol_at_address_func (immval, info))
		{
		  print_func (stream, "\t// ");
		  info->print_address_func (immval, info);
		}
	      else if (op->inst_offset_type == INST_PC_OFFSET)
		{
		  print_func (stream, "\t\t// ");
		  print_func (stream, "%x", immval);
		}
	    }
	  break;
	case INST_TYPE_RD_R2:
	  print_func (stream, "\t%s, %s", get_field_rd (&buf, inst),
		      get_field_r2 (&buf, inst));
	  break;
	case INST_TYPE_R2:
	  print_func (stream, "\t%s", get_field_r2 (&buf, inst));
	  break;
	case INST_TYPE_R1:
	  print_func (stream, "\t%s", get_field_r1 (&buf, inst));
	  break;
	case INST_TYPE_R1_R2_SPECIAL:
	  print_func (stream, "\t%s, %s", get_field_r1 (&buf, inst),
		      get_field_r2 (&buf, inst));
	  break;
	case INST_TYPE_RD_IMM15:
	  print_func (stream, "\t%s, %s", get_field_rd (&buf, inst),
		      get_field_imm15 (&buf, inst));
	  break;
	  /* For mbar insn.  */
	case INST_TYPE_IMM5:
	  print_func (stream, "\t%s", get_field_imm5_mbar (&buf, inst));
	  break;
	  /* For mbar 16 or sleep insn.  */
	case INST_TYPE_NONE:
	  break;
	  /* For tuqula instruction */
	case INST_TYPE_RD:
	  print_func (stream, "\t%s", get_field_rd (&buf, inst));
	  break;
	case INST_TYPE_RFSL:
	  print_func (stream, "\t%s", get_field_rfsl (&buf, inst));
	  break;
	default:
	  /* If the disassembler lags the instruction set.  */
	  print_func (stream, "\tundecoded operands, inst is 0x%04x",
		      (unsigned int) inst);
	  break;
	}
    }

  /* Say how many bytes we consumed.  */
  return 4;
}

enum microblaze_instr
get_insn_microblaze (long inst,
  		     bfd_boolean *isunsignedimm,
  		     enum microblaze_instr_type *insn_type,
  		     short *delay_slots)
{
  struct op_code_struct * op;
  *isunsignedimm = FALSE;

  /* Just a linear search of the table.  */
  for (op = opcodes; op->name != 0; op ++)
    if (op->bit_sequence == (inst & op->opcode_mask))
      break;

  if (op->name == 0)
    return invalid_inst;
  else
    {
      *isunsignedimm = (op->inst_type == INST_TYPE_RD_R1_UNSIGNED_IMM);
      *insn_type = op->instr_type;
      *delay_slots = op->delay_slots;
      return op->instr;
    }
}

enum microblaze_instr
microblaze_decode_insn (long insn, int *rd, int *ra, int *rb, int *immed)
{
  enum microblaze_instr op;
  bfd_boolean t1;
  enum microblaze_instr_type t2;
  short t3;

  op = get_insn_microblaze (insn, &t1, &t2, &t3);
  *rd = (insn & RD_MASK) >> RD_LOW;
  *ra = (insn & RA_MASK) >> RA_LOW;
  *rb = (insn & RB_MASK) >> RB_LOW;
  t3 = (insn & IMM_MASK) >> IMM_LOW;
  *immed = (int) t3;
  return (op);
}

unsigned long
microblaze_get_target_address (long inst, bfd_boolean immfound, int immval,
			       long pcval, long r1val, long r2val,
			       bfd_boolean *targetvalid,
			       bfd_boolean *unconditionalbranch)
{
  struct op_code_struct * op;
  long targetaddr = 0;

  *unconditionalbranch = FALSE;
  /* Just a linear search of the table.  */
  for (op = opcodes; op->name != 0; op ++)
    if (op->bit_sequence == (inst & op->opcode_mask))
      break;

  if (op->name == 0)
    {
      *targetvalid = FALSE;
    }
  else if (op->instr_type == branch_inst)
    {
      switch (op->inst_type)
	{
        case INST_TYPE_R2:
          *unconditionalbranch = TRUE;
        /* Fall through.  */
        case INST_TYPE_RD_R2:
        case INST_TYPE_R1_R2:
          targetaddr = r2val;
          *targetvalid = TRUE;
          if (op->inst_offset_type == INST_PC_OFFSET)
	    targetaddr += pcval;
          break;
        case INST_TYPE_IMM:
          *unconditionalbranch = TRUE;
        /* Fall through.  */
        case INST_TYPE_RD_IMM:
        case INST_TYPE_R1_IMM:
          if (immfound)
	    {
	      targetaddr = (immval << 16) & 0xffff0000;
	      targetaddr |= (get_int_field_imm (inst) & 0x0000ffff);
	    }
	  else
	    {
	      targetaddr = get_int_field_imm (inst);
	      if (targetaddr & 0x8000)
	        targetaddr |= 0xFFFF0000;
            }
          if (op->inst_offset_type == INST_PC_OFFSET)
	    targetaddr += pcval;
          *targetvalid = TRUE;
          break;
	default:
	  *targetvalid = FALSE;
	  break;
        }
    }
  else if (op->instr_type == return_inst)
    {
      if (immfound)
	{
	  targetaddr = (immval << 16) & 0xffff0000;
	  targetaddr |= (get_int_field_imm (inst) & 0x0000ffff);
	}
      else
	{
	  targetaddr = get_int_field_imm (inst);
	  if (targetaddr & 0x8000)
	    targetaddr |= 0xFFFF0000;
	}
      targetaddr += r1val;
      *targetvalid = TRUE;
    }
  else
    *targetvalid = FALSE;
  return targetaddr;
}
Commit	Line	Data
7ba29e2a NC	1	/* Disassemble Xilinx microblaze instructions.
7ba29e2a NC	2
b3adc24a	3	Copyright (C) 2009-2020 Free Software Foundation, Inc.
7ba29e2a NC	4
	5	This file is part of the GNU opcodes library.
	6
	7	This library is free software; you can redistribute it and/or modify
	8	it under the terms of the GNU General Public License as published by
	9	the Free Software Foundation; either version 3, or (at your option)
	10	any later version.
	11
	12	It is distributed in the hope that it will be useful, but WITHOUT
	13	ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
	14	or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
	15	License for more details.
	16
	17	You should have received a copy of the GNU General Public License
	18	along with this file; see the file COPYING. If not, write to the
	19	Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
	20	MA 02110-1301, USA. */
	21
	22
	23	#include "sysdep.h"
	24	#define STATIC_TABLE
	25	#define DEFINE_TABLE
	26
88c1242d	27	#include "disassemble.h"
7ba29e2a	28	#include <strings.h>
ef299415 ME	29	#include "microblaze-opc.h"
ef299415 ME	30	#include "microblaze-dis.h"
7ba29e2a	31
378fd436 AM	32	#define get_field_rd(buf, instr) get_field (buf, instr, RD_MASK, RD_LOW)
	33	#define get_field_r1(buf, instr) get_field (buf, instr, RA_MASK, RA_LOW)
	34	#define get_field_r2(buf, instr) get_field (buf, instr, RB_MASK, RB_LOW)
7ba29e2a NC	35	#define get_int_field_imm(instr) ((instr & IMM_MASK) >> IMM_LOW)
	36	#define get_int_field_r1(instr) ((instr & RA_MASK) >> RA_LOW)
	37
378fd436 AM	38	#define NUM_STRBUFS 3
378fd436 AM	39	#define STRBUF_SIZE 25
fe2d172c	40
378fd436 AM	41	struct string_buf
	42	{
	43	unsigned int which;
	44	char str[NUM_STRBUFS][STRBUF_SIZE];
	45	};
	46
	47	static inline char *
	48	strbuf (struct string_buf *buf)
	49	{
	50	#ifdef ENABLE_CHECKING
	51	if (buf->which >= NUM_STRBUFS)
	52	abort ();
	53	#endif
	54	return buf->str[buf->which++];
	55	}
fe2d172c	56
7ba29e2a	57	static char *
378fd436	58	get_field (struct string_buf *buf, long instr, long mask, unsigned short low)
7ba29e2a	59	{
378fd436	60	char *p = strbuf (buf);
7ba29e2a	61
378fd436 AM	62	sprintf (p, "%s%d", register_prefix, (int)((instr & mask) >> low));
378fd436 AM	63	return p;
7ba29e2a NC	64	}
	65
	66	static char *
378fd436	67	get_field_imm (struct string_buf *buf, long instr)
7ba29e2a	68	{
378fd436	69	char *p = strbuf (buf);
7ba29e2a	70
378fd436 AM	71	sprintf (p, "%d", (short)((instr & IMM_MASK) >> IMM_LOW));
378fd436 AM	72	return p;
7ba29e2a NC	73	}
	74
	75	static char *
378fd436	76	get_field_imm5 (struct string_buf *buf, long instr)
7ba29e2a	77	{
378fd436	78	char *p = strbuf (buf);
7ba29e2a	79
378fd436 AM	80	sprintf (p, "%d", (short)((instr & IMM5_MASK) >> IMM_LOW));
378fd436 AM	81	return p;
7ba29e2a NC	82	}
7ba29e2a NC	83
d3da7741	84	static char *
378fd436	85	get_field_imm5_mbar (struct string_buf *buf, long instr)
d3da7741	86	{
378fd436	87	char *p = strbuf (buf);
d3da7741	88
378fd436 AM	89	sprintf (p, "%d", (short)((instr & IMM5_MBAR_MASK) >> IMM_MBAR));
378fd436 AM	90	return p;
d3da7741 ME	91	}
d3da7741 ME	92
7ba29e2a	93	static char *
378fd436	94	get_field_rfsl (struct string_buf *buf, long instr)
7ba29e2a	95	{
378fd436	96	char *p = strbuf (buf);
7ba29e2a	97
378fd436	98	sprintf (p, "%s%d", fsl_register_prefix,
7ba29e2a	99	(short)((instr & RFSL_MASK) >> IMM_LOW));
378fd436	100	return p;
7ba29e2a NC	101	}
	102
	103	static char *
378fd436	104	get_field_imm15 (struct string_buf *buf, long instr)
7ba29e2a	105	{
378fd436	106	char *p = strbuf (buf);
7ba29e2a	107
378fd436 AM	108	sprintf (p, "%d", (short)((instr & IMM15_MASK) >> IMM_LOW));
378fd436 AM	109	return p;
7ba29e2a NC	110	}
	111
	112	static char *
378fd436 AM	113	get_field_special (struct string_buf *buf, long instr,
378fd436 AM	114	struct op_code_struct *op)
7ba29e2a	115	{
378fd436 AM	116	char *p = strbuf (buf);
378fd436 AM	117	char *spr;
7ba29e2a NC	118
	119	switch ((((instr & IMM_MASK) >> IMM_LOW) ^ op->immval_mask))
	120	{
	121	case REG_MSR_MASK :
378fd436	122	spr = "msr";
7ba29e2a NC	123	break;
7ba29e2a NC	124	case REG_PC_MASK :
378fd436	125	spr = "pc";
7ba29e2a NC	126	break;
7ba29e2a NC	127	case REG_EAR_MASK :
378fd436	128	spr = "ear";
7ba29e2a NC	129	break;
7ba29e2a NC	130	case REG_ESR_MASK :
378fd436	131	spr = "esr";
7ba29e2a NC	132	break;
7ba29e2a NC	133	case REG_FSR_MASK :
378fd436	134	spr = "fsr";
7ba29e2a NC	135	break;
7ba29e2a NC	136	case REG_BTR_MASK :
378fd436	137	spr = "btr";
7ba29e2a NC	138	break;
7ba29e2a NC	139	case REG_EDR_MASK :
378fd436	140	spr = "edr";
7ba29e2a NC	141	break;
7ba29e2a NC	142	case REG_PID_MASK :
378fd436	143	spr = "pid";
7ba29e2a NC	144	break;
7ba29e2a NC	145	case REG_ZPR_MASK :
378fd436	146	spr = "zpr";
7ba29e2a NC	147	break;
7ba29e2a NC	148	case REG_TLBX_MASK :
378fd436	149	spr = "tlbx";
7ba29e2a NC	150	break;
7ba29e2a NC	151	case REG_TLBLO_MASK :
378fd436	152	spr = "tlblo";
7ba29e2a NC	153	break;
7ba29e2a NC	154	case REG_TLBHI_MASK :
378fd436	155	spr = "tlbhi";
7ba29e2a NC	156	break;
7ba29e2a NC	157	case REG_TLBSX_MASK :
378fd436	158	spr = "tlbsx";
7ba29e2a	159	break;
0db4b326	160	case REG_SHR_MASK :
378fd436	161	spr = "shr";
0db4b326 ME	162	break;
0db4b326 ME	163	case REG_SLR_MASK :
378fd436	164	spr = "slr";
0db4b326	165	break;
7ba29e2a NC	166	default :
7ba29e2a NC	167	if (((((instr & IMM_MASK) >> IMM_LOW) ^ op->immval_mask) & 0xE000)
378fd436 AM	168	== REG_PVR_MASK)
	169	{
	170	sprintf (p, "%spvr%d", register_prefix,
7ba29e2a	171	(unsigned short)(((instr & IMM_MASK) >> IMM_LOW)
378fd436 AM	172	^ op->immval_mask) ^ REG_PVR_MASK);
	173	return p;
	174	}
7ba29e2a	175	else
378fd436	176	spr = "pc";
7ba29e2a NC	177	break;
	178	}
	179
378fd436 AM	180	sprintf (p, "%s%s", register_prefix, spr);
378fd436 AM	181	return p;
7ba29e2a NC	182	}
	183
	184	static unsigned long
	185	read_insn_microblaze (bfd_vma memaddr,
	186	struct disassemble_info *info,
	187	struct op_code_struct **opr)
	188	{
	189	unsigned char ibytes[4];
	190	int status;
	191	struct op_code_struct * op;
	192	unsigned long inst;
	193
	194	status = info->read_memory_func (memaddr, ibytes, 4, info);
	195
	196	if (status != 0)
	197	{
	198	info->memory_error_func (status, memaddr, info);
	199	return 0;
	200	}
	201
	202	if (info->endian == BFD_ENDIAN_BIG)
488d02fe AM	203	inst = (((unsigned) ibytes[0] << 24) \| (ibytes[1] << 16)
488d02fe AM	204	\| (ibytes[2] << 8) \| ibytes[3]);
7ba29e2a	205	else if (info->endian == BFD_ENDIAN_LITTLE)
488d02fe AM	206	inst = (((unsigned) ibytes[3] << 24) \| (ibytes[2] << 16)
488d02fe AM	207	\| (ibytes[1] << 8) \| ibytes[0]);
7ba29e2a NC	208	else
	209	abort ();
	210
	211	/* Just a linear search of the table. */
	212	for (op = opcodes; op->name != 0; op ++)
	213	if (op->bit_sequence == (inst & op->opcode_mask))
	214	break;
	215
	216	*opr = op;
	217	return inst;
	218	}
	219
	220
	221	int
	222	print_insn_microblaze (bfd_vma memaddr, struct disassemble_info * info)
	223	{
91d6fa6a	224	fprintf_ftype print_func = info->fprintf_func;
7ba29e2a NC	225	void * stream = info->stream;
	226	unsigned long inst, prev_inst;
	227	struct op_code_struct * op, *pop;
	228	int immval = 0;
	229	bfd_boolean immfound = FALSE;
	230	static bfd_vma prev_insn_addr = -1; /* Init the prev insn addr. */
	231	static int prev_insn_vma = -1; /* Init the prev insn vma. */
	232	int curr_insn_vma = info->buffer_vma;
378fd436	233	struct string_buf buf;
7ba29e2a	234
378fd436	235	buf.which = 0;
7ba29e2a NC	236	info->bytes_per_chunk = 4;
	237
	238	inst = read_insn_microblaze (memaddr, info, &op);
	239	if (inst == 0)
	240	return -1;
	241
	242	if (prev_insn_vma == curr_insn_vma)
	243	{
	244	if (memaddr-(info->bytes_per_chunk) == prev_insn_addr)
378fd436 AM	245	{
378fd436 AM	246	prev_inst = read_insn_microblaze (prev_insn_addr, info, &pop);
7ba29e2a NC	247	if (prev_inst == 0)
	248	return -1;
	249	if (pop->instr == imm)
	250	{
	251	immval = (get_int_field_imm (prev_inst) << 16) & 0xffff0000;
	252	immfound = TRUE;
	253	}
	254	else
	255	{
	256	immval = 0;
	257	immfound = FALSE;
	258	}
	259	}
	260	}
	261
	262	/* Make curr insn as prev insn. */
	263	prev_insn_addr = memaddr;
	264	prev_insn_vma = curr_insn_vma;
	265
	266	if (op->name == NULL)
d908c8af	267	print_func (stream, ".short 0x%04x", (unsigned int) inst);
7ba29e2a NC	268	else
7ba29e2a NC	269	{
91d6fa6a	270	print_func (stream, "%s", op->name);
7ba29e2a NC	271
	272	switch (op->inst_type)
	273	{
378fd436 AM	274	case INST_TYPE_RD_R1_R2:
	275	print_func (stream, "\t%s, %s, %s", get_field_rd (&buf, inst),
	276	get_field_r1 (&buf, inst), get_field_r2 (&buf, inst));
	277	break;
	278	case INST_TYPE_RD_R1_IMM:
	279	print_func (stream, "\t%s, %s, %s", get_field_rd (&buf, inst),
	280	get_field_r1 (&buf, inst), get_field_imm (&buf, inst));
7ba29e2a NC	281	if (info->print_address_func && get_int_field_r1 (inst) == 0
	282	&& info->symbol_at_address_func)
	283	{
	284	if (immfound)
378fd436	285	immval \|= (get_int_field_imm (inst) & 0x0000ffff);
7ba29e2a NC	286	else
7ba29e2a NC	287	{
378fd436 AM	288	immval = get_int_field_imm (inst);
378fd436 AM	289	if (immval & 0x8000)
7ba29e2a	290	immval \|= 0xFFFF0000;
378fd436	291	}
7ba29e2a NC	292	if (immval > 0 && info->symbol_at_address_func (immval, info))
7ba29e2a NC	293	{
378fd436 AM	294	print_func (stream, "\t// ");
	295	info->print_address_func (immval, info);
	296	}
7ba29e2a NC	297	}
	298	break;
	299	case INST_TYPE_RD_R1_IMM5:
378fd436 AM	300	print_func (stream, "\t%s, %s, %s", get_field_rd (&buf, inst),
378fd436 AM	301	get_field_r1 (&buf, inst), get_field_imm5 (&buf, inst));
7ba29e2a NC	302	break;
7ba29e2a NC	303	case INST_TYPE_RD_RFSL:
378fd436 AM	304	print_func (stream, "\t%s, %s", get_field_rd (&buf, inst),
378fd436 AM	305	get_field_rfsl (&buf, inst));
7ba29e2a NC	306	break;
7ba29e2a NC	307	case INST_TYPE_R1_RFSL:
378fd436 AM	308	print_func (stream, "\t%s, %s", get_field_r1 (&buf, inst),
378fd436 AM	309	get_field_rfsl (&buf, inst));
7ba29e2a NC	310	break;
7ba29e2a NC	311	case INST_TYPE_RD_SPECIAL:
378fd436 AM	312	print_func (stream, "\t%s, %s", get_field_rd (&buf, inst),
378fd436 AM	313	get_field_special (&buf, inst, op));
7ba29e2a NC	314	break;
7ba29e2a NC	315	case INST_TYPE_SPECIAL_R1:
378fd436 AM	316	print_func (stream, "\t%s, %s", get_field_special (&buf, inst, op),
378fd436 AM	317	get_field_r1 (&buf, inst));
7ba29e2a NC	318	break;
7ba29e2a NC	319	case INST_TYPE_RD_R1:
378fd436 AM	320	print_func (stream, "\t%s, %s", get_field_rd (&buf, inst),
378fd436 AM	321	get_field_r1 (&buf, inst));
7ba29e2a NC	322	break;
7ba29e2a NC	323	case INST_TYPE_R1_R2:
378fd436 AM	324	print_func (stream, "\t%s, %s", get_field_r1 (&buf, inst),
378fd436 AM	325	get_field_r2 (&buf, inst));
7ba29e2a NC	326	break;
7ba29e2a NC	327	case INST_TYPE_R1_IMM:
378fd436 AM	328	print_func (stream, "\t%s, %s", get_field_r1 (&buf, inst),
378fd436 AM	329	get_field_imm (&buf, inst));
7ba29e2a NC	330	/* The non-pc relative instructions are returns, which shouldn't
	331	have a label printed. */
	332	if (info->print_address_func && op->inst_offset_type == INST_PC_OFFSET
	333	&& info->symbol_at_address_func)
	334	{
	335	if (immfound)
378fd436	336	immval \|= (get_int_field_imm (inst) & 0x0000ffff);
7ba29e2a NC	337	else
7ba29e2a NC	338	{
378fd436 AM	339	immval = get_int_field_imm (inst);
378fd436 AM	340	if (immval & 0x8000)
7ba29e2a	341	immval \|= 0xFFFF0000;
378fd436	342	}
7ba29e2a NC	343	immval += memaddr;
	344	if (immval > 0 && info->symbol_at_address_func (immval, info))
	345	{
378fd436 AM	346	print_func (stream, "\t// ");
	347	info->print_address_func (immval, info);
	348	}
7ba29e2a NC	349	else
7ba29e2a NC	350	{
378fd436 AM	351	print_func (stream, "\t\t// ");
	352	print_func (stream, "%x", immval);
	353	}
7ba29e2a NC	354	}
7ba29e2a NC	355	break;
378fd436 AM	356	case INST_TYPE_RD_IMM:
	357	print_func (stream, "\t%s, %s", get_field_rd (&buf, inst),
	358	get_field_imm (&buf, inst));
7ba29e2a NC	359	if (info->print_address_func && info->symbol_at_address_func)
7ba29e2a NC	360	{
378fd436 AM	361	if (immfound)
	362	immval \|= (get_int_field_imm (inst) & 0x0000ffff);
	363	else
	364	{
	365	immval = get_int_field_imm (inst);
	366	if (immval & 0x8000)
	367	immval \|= 0xFFFF0000;
	368	}
	369	if (op->inst_offset_type == INST_PC_OFFSET)
	370	immval += (int) memaddr;
	371	if (info->symbol_at_address_func (immval, info))
	372	{
	373	print_func (stream, "\t// ");
	374	info->print_address_func (immval, info);
	375	}
7ba29e2a NC	376	}
7ba29e2a NC	377	break;
378fd436 AM	378	case INST_TYPE_IMM:
378fd436 AM	379	print_func (stream, "\t%s", get_field_imm (&buf, inst));
7ba29e2a NC	380	if (info->print_address_func && info->symbol_at_address_func
	381	&& op->instr != imm)
	382	{
	383	if (immfound)
378fd436	384	immval \|= (get_int_field_imm (inst) & 0x0000ffff);
7ba29e2a NC	385	else
7ba29e2a NC	386	{
378fd436 AM	387	immval = get_int_field_imm (inst);
378fd436 AM	388	if (immval & 0x8000)
7ba29e2a	389	immval \|= 0xFFFF0000;
378fd436	390	}
7ba29e2a	391	if (op->inst_offset_type == INST_PC_OFFSET)
378fd436	392	immval += (int) memaddr;
7ba29e2a NC	393	if (immval > 0 && info->symbol_at_address_func (immval, info))
7ba29e2a NC	394	{
378fd436 AM	395	print_func (stream, "\t// ");
	396	info->print_address_func (immval, info);
	397	}
7ba29e2a NC	398	else if (op->inst_offset_type == INST_PC_OFFSET)
7ba29e2a NC	399	{
378fd436 AM	400	print_func (stream, "\t\t// ");
	401	print_func (stream, "%x", immval);
	402	}
7ba29e2a NC	403	}
7ba29e2a NC	404	break;
378fd436 AM	405	case INST_TYPE_RD_R2:
	406	print_func (stream, "\t%s, %s", get_field_rd (&buf, inst),
	407	get_field_r2 (&buf, inst));
7ba29e2a NC	408	break;
7ba29e2a NC	409	case INST_TYPE_R2:
378fd436	410	print_func (stream, "\t%s", get_field_r2 (&buf, inst));
7ba29e2a NC	411	break;
7ba29e2a NC	412	case INST_TYPE_R1:
378fd436	413	print_func (stream, "\t%s", get_field_r1 (&buf, inst));
7ba29e2a	414	break;
94dda8b7	415	case INST_TYPE_R1_R2_SPECIAL:
378fd436 AM	416	print_func (stream, "\t%s, %s", get_field_r1 (&buf, inst),
378fd436 AM	417	get_field_r2 (&buf, inst));
7ba29e2a NC	418	break;
7ba29e2a NC	419	case INST_TYPE_RD_IMM15:
378fd436 AM	420	print_func (stream, "\t%s, %s", get_field_rd (&buf, inst),
	421	get_field_imm15 (&buf, inst));
	422	break;
	423	/* For mbar insn. */
	424	case INST_TYPE_IMM5:
	425	print_func (stream, "\t%s", get_field_imm5_mbar (&buf, inst));
	426	break;
	427	/* For mbar 16 or sleep insn. */
	428	case INST_TYPE_NONE:
7ba29e2a	429	break;
378fd436	430	/* For tuqula instruction */
7ba29e2a	431	case INST_TYPE_RD:
378fd436	432	print_func (stream, "\t%s", get_field_rd (&buf, inst));
7ba29e2a NC	433	break;
7ba29e2a NC	434	case INST_TYPE_RFSL:
378fd436	435	print_func (stream, "\t%s", get_field_rfsl (&buf, inst));
7ba29e2a NC	436	break;
	437	default:
	438	/* If the disassembler lags the instruction set. */
378fd436 AM	439	print_func (stream, "\tundecoded operands, inst is 0x%04x",
378fd436 AM	440	(unsigned int) inst);
7ba29e2a NC	441	break;
	442	}
	443	}
	444
	445	/* Say how many bytes we consumed. */
	446	return 4;
	447	}
fe2d172c ME	448
fe2d172c ME	449	enum microblaze_instr
7ba29e2a NC	450	get_insn_microblaze (long inst,
	451	bfd_boolean *isunsignedimm,
	452	enum microblaze_instr_type *insn_type,
	453	short *delay_slots)
	454	{
	455	struct op_code_struct * op;
	456	*isunsignedimm = FALSE;
	457
	458	/* Just a linear search of the table. */
	459	for (op = opcodes; op->name != 0; op ++)
	460	if (op->bit_sequence == (inst & op->opcode_mask))
	461	break;
	462
	463	if (op->name == 0)
	464	return invalid_inst;
	465	else
	466	{
	467	*isunsignedimm = (op->inst_type == INST_TYPE_RD_R1_UNSIGNED_IMM);
	468	*insn_type = op->instr_type;
	469	*delay_slots = op->delay_slots;
	470	return op->instr;
	471	}
	472	}
	473
7ba29e2a	474	enum microblaze_instr
91d6fa6a	475	microblaze_decode_insn (long insn, int rd, int ra, int rb, int immed)
7ba29e2a NC	476	{
	477	enum microblaze_instr op;
	478	bfd_boolean t1;
	479	enum microblaze_instr_type t2;
	480	short t3;
	481
	482	op = get_insn_microblaze (insn, &t1, &t2, &t3);
	483	*rd = (insn & RD_MASK) >> RD_LOW;
	484	*ra = (insn & RA_MASK) >> RA_LOW;
	485	*rb = (insn & RB_MASK) >> RB_LOW;
	486	t3 = (insn & IMM_MASK) >> IMM_LOW;
91d6fa6a	487	*immed = (int) t3;
7ba29e2a NC	488	return (op);
	489	}
	490
	491	unsigned long
	492	microblaze_get_target_address (long inst, bfd_boolean immfound, int immval,
	493	long pcval, long r1val, long r2val,
	494	bfd_boolean *targetvalid,
	495	bfd_boolean *unconditionalbranch)
	496	{
	497	struct op_code_struct * op;
	498	long targetaddr = 0;
	499
	500	*unconditionalbranch = FALSE;
	501	/* Just a linear search of the table. */
	502	for (op = opcodes; op->name != 0; op ++)
	503	if (op->bit_sequence == (inst & op->opcode_mask))
	504	break;
	505
	506	if (op->name == 0)
	507	{
	508	*targetvalid = FALSE;
	509	}
	510	else if (op->instr_type == branch_inst)
	511	{
	512	switch (op->inst_type)
	513	{
	514	case INST_TYPE_R2:
	515	*unconditionalbranch = TRUE;
	516	/* Fall through. */
	517	case INST_TYPE_RD_R2:
	518	case INST_TYPE_R1_R2:
	519	targetaddr = r2val;
	520	*targetvalid = TRUE;
	521	if (op->inst_offset_type == INST_PC_OFFSET)
	522	targetaddr += pcval;
	523	break;
	524	case INST_TYPE_IMM:
	525	*unconditionalbranch = TRUE;
	526	/* Fall through. */
	527	case INST_TYPE_RD_IMM:
	528	case INST_TYPE_R1_IMM:
	529	if (immfound)
	530	{
	531	targetaddr = (immval << 16) & 0xffff0000;
	532	targetaddr \|= (get_int_field_imm (inst) & 0x0000ffff);
	533	}
	534	else
	535	{
	536	targetaddr = get_int_field_imm (inst);
	537	if (targetaddr & 0x8000)
	538	targetaddr \|= 0xFFFF0000;
	539	}
	540	if (op->inst_offset_type == INST_PC_OFFSET)
	541	targetaddr += pcval;
	542	*targetvalid = TRUE;
	543	break;
	544	default:
	545	*targetvalid = FALSE;
	546	break;
	547	}
	548	}
	549	else if (op->instr_type == return_inst)
	550	{
	551	if (immfound)
552	{
553	targetaddr = (immval << 16) & 0xffff0000;
554	targetaddr \|= (get_int_field_imm (inst) & 0x0000ffff);
555	}
556	else
557	{
558	targetaddr = get_int_field_imm (inst);
559	if (targetaddr & 0x8000)
560	targetaddr \|= 0xFFFF0000;
561	}
562	targetaddr += r1val;
563	*targetvalid = TRUE;
564	}
565	else
566	*targetvalid = FALSE;
567	return targetaddr;
568	}