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gdb: add target_ops::supports_displaced_step
[deliverable/binutils-gdb.git] / opcodes / nios2-dis.c
CommitLineData
36591ba1 1/* Altera Nios II disassemble routines
b3adc24a 2 Copyright (C) 2012-2020 Free Software Foundation, Inc.
36591ba1
SL		 3 Contributed by Nigel Gray (ngray@altera.com).
4 Contributed by Mentor Graphics, Inc.
5
6 This file is part of the GNU opcodes library.
7
8 This library is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3, or (at your option)
11 any later version.
12
13 It is distributed in the hope that it will be useful, but WITHOUT
14 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
16 License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with this file; see the file COPYING. If not, write to the
20 Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
21 MA 02110-1301, USA. */
22
23#include "sysdep.h"
88c1242d 24#include "disassemble.h"
a6743a54 25#include "opintl.h"
36591ba1
SL		 26#include "opcode/nios2.h"
27#include "libiberty.h"
28#include <string.h>
29#include <assert.h>
30
31/* No symbol table is available when this code runs out in an embedded
32 system as when it is used for disassembler support in a monitor. */
33#if !defined(EMBEDDED_ENV)
34#define SYMTAB_AVAILABLE 1
35#include "elf-bfd.h"
36#include "elf/nios2.h"
37#endif
38
96ba4233 39/* Default length of Nios II instruction in bytes. */
36591ba1
SL		 40#define INSNLEN 4
41
42/* Data structures used by the opcode hash table. */
43typedef struct _nios2_opcode_hash
44{
45 const struct nios2_opcode *opcode;
46 struct _nios2_opcode_hash *next;
47} nios2_opcode_hash;
48
96ba4233
SL		 49/* Hash table size. */
50#define OPCODE_HASH_SIZE (IW_R1_OP_UNSHIFTED_MASK + 1)
36591ba1 51
96ba4233
SL		 52/* Extract the opcode from an instruction word. */
53static unsigned int
54nios2_r1_extract_opcode (unsigned int x)
55{
56 return GET_IW_R1_OP (x);
57}
58
c8c8175b
SL		 59static unsigned int
60nios2_r2_extract_opcode (unsigned int x)
61{
62 return GET_IW_R2_OP (x);
63}
64
65/* We maintain separate hash tables for R1 and R2 opcodes, and pseudo-ops
66 are stored in a different table than regular instructions. */
96ba4233
SL		 67
68typedef struct _nios2_disassembler_state
69{
70 const struct nios2_opcode *opcodes;
71 const int *num_opcodes;
72 unsigned int (*extract_opcode) (unsigned int);
73 nios2_opcode_hash *hash[OPCODE_HASH_SIZE];
74 nios2_opcode_hash *ps_hash[OPCODE_HASH_SIZE];
75 const struct nios2_opcode *nop;
76 bfd_boolean init;
77} nios2_disassembler_state;
78
79static nios2_disassembler_state
80nios2_r1_disassembler_state = {
81 nios2_r1_opcodes,
82 &nios2_num_r1_opcodes,
83 nios2_r1_extract_opcode,
84 {},
85 {},
86 NULL,
87 0
88};
36591ba1 89
c8c8175b
SL		 90static nios2_disassembler_state
91nios2_r2_disassembler_state = {
92 nios2_r2_opcodes,
93 &nios2_num_r2_opcodes,
94 nios2_r2_extract_opcode,
95 {},
96 {},
97 NULL,
98 0
99};
43e65147 100
36591ba1
SL		 101/* Function to initialize the opcode hash table. */
102static void
96ba4233 103nios2_init_opcode_hash (nios2_disassembler_state *state)
36591ba1
SL		 104{
105 unsigned int i;
106 register const struct nios2_opcode *op;
107
96ba4233
SL		 108 for (i = 0; i < OPCODE_HASH_SIZE; i++)
109 for (op = state->opcodes; op < &state->opcodes[*(state->num_opcodes)]; op++)
36591ba1
SL		 110 {
111 nios2_opcode_hash *new_hash;
112 nios2_opcode_hash **bucket = NULL;
113
114 if ((op->pinfo & NIOS2_INSN_MACRO) == NIOS2_INSN_MACRO)
115 {
96ba4233 116 if (i == state->extract_opcode (op->match)
36591ba1
SL		 117 && (op->pinfo & (NIOS2_INSN_MACRO_MOV | NIOS2_INSN_MACRO_MOVI)
118 & 0x7fffffff))
96ba4233
SL		 119 {
120 bucket = &(state->ps_hash[i]);
121 if (strcmp (op->name, "nop") == 0)
122 state->nop = op;
123 }
36591ba1 124 }
96ba4233
SL		 125 else if (i == state->extract_opcode (op->match))
126 bucket = &(state->hash[i]);
36591ba1
SL		 127
128 if (bucket)
129 {
130 new_hash =
131 (nios2_opcode_hash *) malloc (sizeof (nios2_opcode_hash));
132 if (new_hash == NULL)
133 {
a6743a54
AM		 134 /* xgettext:c-format */
135 opcodes_error_handler (_("out of memory"));
136 exit (1);
36591ba1
SL		 137 }
138 new_hash->opcode = op;
139 new_hash->next = NULL;
140 while (*bucket)
141 bucket = &((*bucket)->next);
142 *bucket = new_hash;
143 }
144 }
96ba4233
SL		 145 state->init = 1;
146
36591ba1 147#ifdef DEBUG_HASHTABLE
96ba4233 148 for (i = 0; i < OPCODE_HASH_SIZE; ++i)
36591ba1 149 {
96ba4233 150 nios2_opcode_hash *tmp_hash = state->hash[i];
36591ba1
SL		 151 printf ("index: 0x%02X ops: ", i);
152 while (tmp_hash != NULL)
153 {
154 printf ("%s ", tmp_hash->opcode->name);
155 tmp_hash = tmp_hash->next;
156 }
157 printf ("\n");
158 }
159
96ba4233 160 for (i = 0; i < OPCODE_HASH_SIZE; ++i)
36591ba1 161 {
96ba4233 162 nios2_opcode_hash *tmp_hash = state->ps_hash[i];
36591ba1
SL		 163 printf ("index: 0x%02X ops: ", i);
164 while (tmp_hash != NULL)
165 {
166 printf ("%s ", tmp_hash->opcode->name);
167 tmp_hash = tmp_hash->next;
168 }
169 printf ("\n");
170 }
171#endif /* DEBUG_HASHTABLE */
172}
173
174/* Return a pointer to an nios2_opcode struct for a given instruction
b4714c7c 175 word OPCODE for bfd machine MACH, or NULL if there is an error. */
36591ba1 176const struct nios2_opcode *
c8c8175b 177nios2_find_opcode_hash (unsigned long opcode, unsigned long mach)
36591ba1
SL		 178{
179 nios2_opcode_hash *entry;
96ba4233
SL		 180 nios2_disassembler_state *state;
181
c8c8175b
SL		 182 /* Select the right instruction set, hash tables, and opcode accessor
183 for the mach variant. */
184 if (mach == bfd_mach_nios2r2)
185 state = &nios2_r2_disassembler_state;
186 else
187 state = &nios2_r1_disassembler_state;
36591ba1
SL		 188
189 /* Build a hash table to shorten the search time. */
96ba4233
SL		 190 if (!state->init)
191 nios2_init_opcode_hash (state);
192
193 /* Check for NOP first. Both NOP and MOV are macros that expand into
194 an ADD instruction, and we always want to give priority to NOP. */
195 if (state->nop->match == (opcode & state->nop->mask))
196 return state->nop;
36591ba1
SL		 197
198 /* First look in the pseudo-op hashtable. */
96ba4233 199 for (entry = state->ps_hash[state->extract_opcode (opcode)];
36591ba1
SL		 200 entry; entry = entry->next)
201 if (entry->opcode->match == (opcode & entry->opcode->mask))
202 return entry->opcode;
203
204 /* Otherwise look in the main hashtable. */
96ba4233 205 for (entry = state->hash[state->extract_opcode (opcode)];
36591ba1
SL		 206 entry; entry = entry->next)
207 if (entry->opcode->match == (opcode & entry->opcode->mask))
208 return entry->opcode;
209
210 return NULL;
211}
212
213/* There are 32 regular registers, 32 coprocessor registers,
214 and 32 control registers. */
215#define NUMREGNAMES 32
216
217/* Return a pointer to the base of the coprocessor register name array. */
218static struct nios2_reg *
219nios2_coprocessor_regs (void)
220{
221 static struct nios2_reg *cached = NULL;
43e65147 222
36591ba1
SL		 223 if (!cached)
224 {
225 int i;
226 for (i = NUMREGNAMES; i < nios2_num_regs; i++)
227 if (!strcmp (nios2_regs[i].name, "c0"))
228 {
229 cached = nios2_regs + i;
230 break;
231 }
232 assert (cached);
233 }
234 return cached;
235}
236
237/* Return a pointer to the base of the control register name array. */
238static struct nios2_reg *
239nios2_control_regs (void)
240{
241 static struct nios2_reg *cached = NULL;
43e65147 242
36591ba1
SL		 243 if (!cached)
244 {
245 int i;
246 for (i = NUMREGNAMES; i < nios2_num_regs; i++)
247 if (!strcmp (nios2_regs[i].name, "status"))
248 {
249 cached = nios2_regs + i;
250 break;
251 }
252 assert (cached);
253 }
254 return cached;
255}
256
96ba4233
SL		 257/* Helper routine to report internal errors. */
258static void
259bad_opcode (const struct nios2_opcode *op)
260{
a6743a54
AM		 261 opcodes_error_handler
262 /* xgettext:c-format */
263 (_("internal error: broken opcode descriptor for `%s %s'"),
264 op->name, op->args);
96ba4233
SL		 265 abort ();
266}
267
36591ba1
SL		 268/* The function nios2_print_insn_arg uses the character pointed
269 to by ARGPTR to determine how it print the next token or separator
270 character in the arguments to an instruction. */
271static int
272nios2_print_insn_arg (const char *argptr,
273 unsigned long opcode, bfd_vma address,
96ba4233
SL		 274 disassemble_info *info,
275 const struct nios2_opcode *op)
36591ba1
SL		 276{
277 unsigned long i = 0;
6031ac35 278 long s = 0;
efcf5fb5 279 int32_t o = 0;
36591ba1
SL		 280 struct nios2_reg *reg_base;
281
282 switch (*argptr)
283 {
284 case ',':
285 case '(':
286 case ')':
287 (*info->fprintf_func) (info->stream, "%c", *argptr);
288 break;
36591ba1 289
c8c8175b
SL		 290 case 'c':
291 /* Control register index. */
292 switch (op->format)
293 {
294 case iw_r_type:
295 i = GET_IW_R_IMM5 (opcode);
296 break;
297 case iw_F3X6L5_type:
298 i = GET_IW_F3X6L5_IMM5 (opcode);
299 break;
300 default:
301 bad_opcode (op);
302 }
303 reg_base = nios2_control_regs ();
304 (*info->fprintf_func) (info->stream, "%s", reg_base[i].name);
305 break;
306
96ba4233 307 case 'd':
c8c8175b 308 reg_base = nios2_regs;
96ba4233
SL		 309 switch (op->format)
310 {
311 case iw_r_type:
312 i = GET_IW_R_C (opcode);
96ba4233
SL		 313 break;
314 case iw_custom_type:
315 i = GET_IW_CUSTOM_C (opcode);
316 if (GET_IW_CUSTOM_READC (opcode) == 0)
317 reg_base = nios2_coprocessor_regs ();
c8c8175b
SL		 318 break;
319 case iw_F3X6L5_type:
320 case iw_F3X6_type:
321 i = GET_IW_F3X6L5_C (opcode);
322 break;
323 case iw_F3X8_type:
324 i = GET_IW_F3X8_C (opcode);
325 if (GET_IW_F3X8_READC (opcode) == 0)
326 reg_base = nios2_coprocessor_regs ();
327 break;
328 case iw_F2_type:
329 i = GET_IW_F2_B (opcode);
96ba4233
SL		 330 break;
331 default:
332 bad_opcode (op);
333 }
36591ba1
SL		 334 if (i < NUMREGNAMES)
335 (*info->fprintf_func) (info->stream, "%s", reg_base[i].name);
336 else
337 (*info->fprintf_func) (info->stream, "unknown");
338 break;
36591ba1 339
96ba4233 340 case 's':
c8c8175b 341 reg_base = nios2_regs;
96ba4233
SL		 342 switch (op->format)
343 {
344 case iw_r_type:
345 i = GET_IW_R_A (opcode);
96ba4233
SL		 346 break;
347 case iw_i_type:
348 i = GET_IW_I_A (opcode);
96ba4233
SL		 349 break;
350 case iw_custom_type:
351 i = GET_IW_CUSTOM_A (opcode);
352 if (GET_IW_CUSTOM_READA (opcode) == 0)
353 reg_base = nios2_coprocessor_regs ();
c8c8175b
SL		 354 break;
355 case iw_F2I16_type:
356 i = GET_IW_F2I16_A (opcode);
357 break;
358 case iw_F2X4I12_type:
359 i = GET_IW_F2X4I12_A (opcode);
360 break;
361 case iw_F1X4I12_type:
362 i = GET_IW_F1X4I12_A (opcode);
363 break;
364 case iw_F1X4L17_type:
365 i = GET_IW_F1X4L17_A (opcode);
366 break;
367 case iw_F3X6L5_type:
368 case iw_F3X6_type:
369 i = GET_IW_F3X6L5_A (opcode);
370 break;
371 case iw_F2X6L10_type:
372 i = GET_IW_F2X6L10_A (opcode);
373 break;
374 case iw_F3X8_type:
375 i = GET_IW_F3X8_A (opcode);
376 if (GET_IW_F3X8_READA (opcode) == 0)
377 reg_base = nios2_coprocessor_regs ();
378 break;
379 case iw_F1X1_type:
380 i = GET_IW_F1X1_A (opcode);
381 break;
382 case iw_F1I5_type:
383 i = 27; /* Implicit stack pointer reference. */
384 break;
385 case iw_F2_type:
386 i = GET_IW_F2_A (opcode);
96ba4233
SL		 387 break;
388 default:
389 bad_opcode (op);
390 }
36591ba1
SL		 391 if (i < NUMREGNAMES)
392 (*info->fprintf_func) (info->stream, "%s", reg_base[i].name);
393 else
394 (*info->fprintf_func) (info->stream, "unknown");
395 break;
36591ba1 396
96ba4233 397 case 't':
c8c8175b 398 reg_base = nios2_regs;
96ba4233
SL		 399 switch (op->format)
400 {
401 case iw_r_type:
402 i = GET_IW_R_B (opcode);
96ba4233
SL		 403 break;
404 case iw_i_type:
405 i = GET_IW_I_B (opcode);
96ba4233
SL		 406 break;
407 case iw_custom_type:
408 i = GET_IW_CUSTOM_B (opcode);
409 if (GET_IW_CUSTOM_READB (opcode) == 0)
410 reg_base = nios2_coprocessor_regs ();
c8c8175b
SL		 411 break;
412 case iw_F2I16_type:
413 i = GET_IW_F2I16_B (opcode);
414 break;
415 case iw_F2X4I12_type:
416 i = GET_IW_F2X4I12_B (opcode);
417 break;
418 case iw_F3X6L5_type:
419 case iw_F3X6_type:
420 i = GET_IW_F3X6L5_B (opcode);
421 break;
422 case iw_F2X6L10_type:
423 i = GET_IW_F2X6L10_B (opcode);
424 break;
425 case iw_F3X8_type:
426 i = GET_IW_F3X8_B (opcode);
427 if (GET_IW_F3X8_READB (opcode) == 0)
428 reg_base = nios2_coprocessor_regs ();
429 break;
430 case iw_F1I5_type:
431 i = GET_IW_F1I5_B (opcode);
432 break;
433 case iw_F2_type:
434 i = GET_IW_F2_B (opcode);
435 break;
436 case iw_T1X1I6_type:
437 i = 0;
96ba4233
SL		 438 break;
439 default:
440 bad_opcode (op);
441 }
36591ba1
SL		 442 if (i < NUMREGNAMES)
443 (*info->fprintf_func) (info->stream, "%s", reg_base[i].name);
444 else
445 (*info->fprintf_func) (info->stream, "unknown");
446 break;
96ba4233 447
c8c8175b
SL		 448 case 'D':
449 switch (op->format)
450 {
451 case iw_T1I7_type:
452 i = GET_IW_T1I7_A3 (opcode);
453 break;
454 case iw_T2X1L3_type:
455 i = GET_IW_T2X1L3_B3 (opcode);
456 break;
457 case iw_T2X1I3_type:
458 i = GET_IW_T2X1I3_B3 (opcode);
459 break;
460 case iw_T3X1_type:
461 i = GET_IW_T3X1_C3 (opcode);
462 break;
463 case iw_T2X3_type:
464 if (op->num_args == 3)
465 i = GET_IW_T2X3_A3 (opcode);
466 else
467 i = GET_IW_T2X3_B3 (opcode);
468 break;
469 default:
470 bad_opcode (op);
471 }
472 i = nios2_r2_reg3_mappings[i];
473 (*info->fprintf_func) (info->stream, "%s", nios2_regs[i].name);
474 break;
475
476 case 'M':
477 /* 6-bit unsigned immediate with no shift. */
478 switch (op->format)
479 {
480 case iw_T1X1I6_type:
481 i = GET_IW_T1X1I6_IMM6 (opcode);
482 break;
483 default:
484 bad_opcode (op);
485 }
486 (*info->fprintf_func) (info->stream, "%ld", i);
487 break;
488
489 case 'N':
490 /* 6-bit unsigned immediate with 2-bit shift. */
491 switch (op->format)
492 {
493 case iw_T1X1I6_type:
494 i = GET_IW_T1X1I6_IMM6 (opcode) << 2;
495 break;
496 default:
497 bad_opcode (op);
498 }
499 (*info->fprintf_func) (info->stream, "%ld", i);
500 break;
501
502 case 'S':
503 switch (op->format)
504 {
505 case iw_T1I7_type:
506 i = GET_IW_T1I7_A3 (opcode);
507 break;
508 case iw_T2I4_type:
509 i = GET_IW_T2I4_A3 (opcode);
510 break;
511 case iw_T2X1L3_type:
512 i = GET_IW_T2X1L3_A3 (opcode);
513 break;
514 case iw_T2X1I3_type:
515 i = GET_IW_T2X1I3_A3 (opcode);
516 break;
517 case iw_T3X1_type:
518 i = GET_IW_T3X1_A3 (opcode);
519 break;
520 case iw_T2X3_type:
521 i = GET_IW_T2X3_A3 (opcode);
522 break;
523 case iw_T1X1I6_type:
524 i = GET_IW_T1X1I6_A3 (opcode);
525 break;
526 default:
527 bad_opcode (op);
528 }
529 i = nios2_r2_reg3_mappings[i];
530 (*info->fprintf_func) (info->stream, "%s", nios2_regs[i].name);
531 break;
532
533 case 'T':
534 switch (op->format)
535 {
536 case iw_T2I4_type:
537 i = GET_IW_T2I4_B3 (opcode);
538 break;
539 case iw_T3X1_type:
540 i = GET_IW_T3X1_B3 (opcode);
541 break;
542 case iw_T2X3_type:
543 i = GET_IW_T2X3_B3 (opcode);
544 break;
545 default:
546 bad_opcode (op);
547 }
548 i = nios2_r2_reg3_mappings[i];
549 (*info->fprintf_func) (info->stream, "%s", nios2_regs[i].name);
550 break;
551
36591ba1
SL		 552 case 'i':
553 /* 16-bit signed immediate. */
96ba4233
SL		 554 switch (op->format)
555 {
556 case iw_i_type:
25e1eca8
SL		 557 s = ((int32_t) ((GET_IW_I_IMM16 (opcode) & 0xffff) ^ 0x8000)
558 - 0x8000);
96ba4233 559 break;
c8c8175b 560 case iw_F2I16_type:
25e1eca8
SL		 561 s = ((int32_t) ((GET_IW_F2I16_IMM16 (opcode) & 0xffff) ^ 0x8000)
562 - 0x8000);
c8c8175b
SL		 563 break;
564 default:
565 bad_opcode (op);
566 }
6031ac35 567 (*info->fprintf_func) (info->stream, "%ld", s);
c8c8175b
SL		 568 break;
569
570 case 'I':
571 /* 12-bit signed immediate. */
572 switch (op->format)
573 {
574 case iw_F2X4I12_type:
25e1eca8
SL		 575 s = ((int32_t) ((GET_IW_F2X4I12_IMM12 (opcode) & 0xfff) ^ 0x800)
576 - 0x800);
c8c8175b
SL		 577 break;
578 case iw_F1X4I12_type:
25e1eca8
SL		 579 s = ((int32_t) ((GET_IW_F1X4I12_IMM12 (opcode) & 0xfff) ^ 0x800)
580 - 0x800);
c8c8175b 581 break;
96ba4233
SL		 582 default:
583 bad_opcode (op);
584 }
6031ac35 585 (*info->fprintf_func) (info->stream, "%ld", s);
36591ba1 586 break;
96ba4233 587
36591ba1
SL		 588 case 'u':
589 /* 16-bit unsigned immediate. */
96ba4233
SL		 590 switch (op->format)
591 {
592 case iw_i_type:
593 i = GET_IW_I_IMM16 (opcode);
594 break;
c8c8175b
SL		 595 case iw_F2I16_type:
596 i = GET_IW_F2I16_IMM16 (opcode);
597 break;
598 default:
599 bad_opcode (op);
600 }
601 (*info->fprintf_func) (info->stream, "%ld", i);
602 break;
603
604 case 'U':
605 /* 7-bit unsigned immediate with 2-bit shift. */
606 switch (op->format)
607 {
608 case iw_T1I7_type:
609 i = GET_IW_T1I7_IMM7 (opcode) << 2;
610 break;
611 case iw_X1I7_type:
612 i = GET_IW_X1I7_IMM7 (opcode) << 2;
613 break;
614 default:
615 bad_opcode (op);
616 }
617 (*info->fprintf_func) (info->stream, "%ld", i);
618 break;
619
620 case 'V':
621 /* 5-bit unsigned immediate with 2-bit shift. */
622 switch (op->format)
623 {
624 case iw_F1I5_type:
625 i = GET_IW_F1I5_IMM5 (opcode) << 2;
626 break;
627 default:
628 bad_opcode (op);
629 }
630 (*info->fprintf_func) (info->stream, "%ld", i);
631 break;
632
633 case 'W':
634 /* 4-bit unsigned immediate with 2-bit shift. */
635 switch (op->format)
636 {
637 case iw_T2I4_type:
638 i = GET_IW_T2I4_IMM4 (opcode) << 2;
639 break;
640 case iw_L5I4X1_type:
641 i = GET_IW_L5I4X1_IMM4 (opcode) << 2;
642 break;
643 default:
644 bad_opcode (op);
645 }
646 (*info->fprintf_func) (info->stream, "%ld", i);
647 break;
648
649 case 'X':
650 /* 4-bit unsigned immediate with 1-bit shift. */
651 switch (op->format)
652 {
653 case iw_T2I4_type:
654 i = GET_IW_T2I4_IMM4 (opcode) << 1;
655 break;
656 default:
657 bad_opcode (op);
658 }
659 (*info->fprintf_func) (info->stream, "%ld", i);
660 break;
661
662 case 'Y':
663 /* 4-bit unsigned immediate without shift. */
664 switch (op->format)
665 {
666 case iw_T2I4_type:
667 i = GET_IW_T2I4_IMM4 (opcode);
668 break;
96ba4233
SL		 669 default:
670 bad_opcode (op);
671 }
36591ba1
SL		 672 (*info->fprintf_func) (info->stream, "%ld", i);
673 break;
96ba4233 674
36591ba1
SL		 675 case 'o':
676 /* 16-bit signed immediate address offset. */
96ba4233
SL		 677 switch (op->format)
678 {
679 case iw_i_type:
efcf5fb5 680 o = ((GET_IW_I_IMM16 (opcode) & 0xffff) ^ 0x8000) - 0x8000;
96ba4233 681 break;
c8c8175b 682 case iw_F2I16_type:
efcf5fb5 683 o = ((GET_IW_F2I16_IMM16 (opcode) & 0xffff) ^ 0x8000) - 0x8000;
c8c8175b 684 break;
96ba4233
SL		 685 default:
686 bad_opcode (op);
687 }
6031ac35 688 address = address + 4 + o;
36591ba1
SL		 689 (*info->print_address_func) (address, info);
690 break;
96ba4233 691
c8c8175b
SL		 692 case 'O':
693 /* 10-bit signed address offset with 1-bit shift. */
694 switch (op->format)
695 {
696 case iw_I10_type:
efcf5fb5 697 o = (((GET_IW_I10_IMM10 (opcode) & 0x3ff) ^ 0x400) - 0x400) * 2;
c8c8175b
SL		 698 break;
699 default:
700 bad_opcode (op);
701 }
6031ac35 702 address = address + 2 + o;
c8c8175b
SL		 703 (*info->print_address_func) (address, info);
704 break;
705
706 case 'P':
707 /* 7-bit signed address offset with 1-bit shift. */
708 switch (op->format)
709 {
710 case iw_T1I7_type:
efcf5fb5 711 o = (((GET_IW_T1I7_IMM7 (opcode) & 0x7f) ^ 0x40) - 0x40) * 2;
c8c8175b
SL		 712 break;
713 default:
714 bad_opcode (op);
715 }
6031ac35 716 address = address + 2 + o;
c8c8175b
SL		 717 (*info->print_address_func) (address, info);
718 break;
719
36591ba1
SL		 720 case 'j':
721 /* 5-bit unsigned immediate. */
96ba4233
SL		 722 switch (op->format)
723 {
724 case iw_r_type:
725 i = GET_IW_R_IMM5 (opcode);
726 break;
c8c8175b
SL		 727 case iw_F3X6L5_type:
728 i = GET_IW_F3X6L5_IMM5 (opcode);
729 break;
730 case iw_F2X6L10_type:
731 i = GET_IW_F2X6L10_MSB (opcode);
732 break;
733 case iw_X2L5_type:
734 i = GET_IW_X2L5_IMM5 (opcode);
735 break;
736 default:
737 bad_opcode (op);
738 }
739 (*info->fprintf_func) (info->stream, "%ld", i);
740 break;
741
742 case 'k':
743 /* Second 5-bit unsigned immediate field. */
744 switch (op->format)
745 {
746 case iw_F2X6L10_type:
747 i = GET_IW_F2X6L10_LSB (opcode);
748 break;
96ba4233
SL		 749 default:
750 bad_opcode (op);
751 }
36591ba1
SL		 752 (*info->fprintf_func) (info->stream, "%ld", i);
753 break;
96ba4233 754
36591ba1
SL		 755 case 'l':
756 /* 8-bit unsigned immediate. */
96ba4233
SL		 757 switch (op->format)
758 {
759 case iw_custom_type:
760 i = GET_IW_CUSTOM_N (opcode);
761 break;
c8c8175b
SL		 762 case iw_F3X8_type:
763 i = GET_IW_F3X8_N (opcode);
764 break;
96ba4233
SL		 765 default:
766 bad_opcode (op);
767 }
36591ba1
SL		 768 (*info->fprintf_func) (info->stream, "%lu", i);
769 break;
96ba4233 770
36591ba1
SL		 771 case 'm':
772 /* 26-bit unsigned immediate. */
96ba4233
SL		 773 switch (op->format)
774 {
775 case iw_j_type:
776 i = GET_IW_J_IMM26 (opcode);
777 break;
c8c8175b
SL		 778 case iw_L26_type:
779 i = GET_IW_L26_IMM26 (opcode);
780 break;
96ba4233
SL		 781 default:
782 bad_opcode (op);
783 }
36591ba1
SL		 784 /* This translates to an address because it's only used in call
785 instructions. */
786 address = (address & 0xf0000000) | (i << 2);
787 (*info->print_address_func) (address, info);
788 break;
96ba4233 789
c8c8175b
SL		 790 case 'e':
791 /* Encoded enumeration for addi.n/subi.n. */
96ba4233
SL		 792 switch (op->format)
793 {
c8c8175b
SL		 794 case iw_T2X1I3_type:
795 i = nios2_r2_asi_n_mappings[GET_IW_T2X1I3_IMM3 (opcode)];
796 break;
797 default:
798 bad_opcode (op);
799 }
800 (*info->fprintf_func) (info->stream, "%lu", i);
801 break;
802
803 case 'f':
804 /* Encoded enumeration for slli.n/srli.n. */
805 switch (op->format)
806 {
807 case iw_T2X1L3_type:
808 i = nios2_r2_shi_n_mappings[GET_IW_T2X1I3_IMM3 (opcode)];
809 break;
810 default:
811 bad_opcode (op);
812 }
813 (*info->fprintf_func) (info->stream, "%lu", i);
814 break;
815
816 case 'g':
817 /* Encoded enumeration for andi.n. */
818 switch (op->format)
819 {
820 case iw_T2I4_type:
821 i = nios2_r2_andi_n_mappings[GET_IW_T2I4_IMM4 (opcode)];
822 break;
823 default:
824 bad_opcode (op);
825 }
826 (*info->fprintf_func) (info->stream, "%lu", i);
827 break;
828
829 case 'h':
830 /* Encoded enumeration for movi.n. */
831 switch (op->format)
832 {
833 case iw_T1I7_type:
834 i = GET_IW_T1I7_IMM7 (opcode);
835 if (i == 125)
836 i = 0xff;
837 else if (i == 126)
838 i = -2;
839 else if (i == 127)
840 i = -1;
841 break;
842 default:
843 bad_opcode (op);
844 }
845 (*info->fprintf_func) (info->stream, "%ld", i);
846 break;
847
848 case 'R':
849 {
850 unsigned long reglist = 0;
851 int dir = 1;
852 int k, t;
853
854 switch (op->format)
855 {
856 case iw_F1X4L17_type:
857 /* Encoding for ldwm/stwm. */
858 i = GET_IW_F1X4L17_REGMASK (opcode);
859 if (GET_IW_F1X4L17_RS (opcode))
860 {
861 reglist = ((i << 14) & 0x00ffc000);
862 if (i & (1 << 10))
863 reglist |= (1 << 28);
864 if (i & (1 << 11))
8a92faab 865 reglist |= (1u << 31);
c8c8175b
SL		 866 }
867 else
868 reglist = i << 2;
869 dir = GET_IW_F1X4L17_REGMASK (opcode) ? 1 : -1;
870 break;
43e65147 871
c8c8175b
SL		 872 case iw_L5I4X1_type:
873 /* Encoding for push.n/pop.n. */
96f1f604 874 reglist |= (1u << 31);
c8c8175b
SL		 875 if (GET_IW_L5I4X1_FP (opcode))
876 reglist |= (1 << 28);
877 if (GET_IW_L5I4X1_CS (opcode))
878 {
879 int val = GET_IW_L5I4X1_REGRANGE (opcode);
880 reglist |= nios2_r2_reg_range_mappings[val];
881 }
882 dir = (op->match == MATCH_R2_POP_N ? 1 : -1);
883 break;
884
885 default:
886 bad_opcode (op);
887 }
888
889 t = 0;
890 (*info->fprintf_func) (info->stream, "{");
891 for (k = (dir == 1 ? 0 : 31);
892 (dir == 1 && k < 32) || (dir == -1 && k >= 0);
893 k += dir)
8a92faab 894 if (reglist & (1u << k))
c8c8175b
SL		 895 {
896 if (t)
897 (*info->fprintf_func) (info->stream, ",");
898 else
899 t++;
900 (*info->fprintf_func) (info->stream, "%s", nios2_regs[k].name);
901 }
902 (*info->fprintf_func) (info->stream, "}");
903 break;
904 }
905
906 case 'B':
907 /* Base register and options for ldwm/stwm. */
908 switch (op->format)
909 {
910 case iw_F1X4L17_type:
911 if (GET_IW_F1X4L17_ID (opcode) == 0)
912 (*info->fprintf_func) (info->stream, "--");
913
914 i = GET_IW_F1X4I12_A (opcode);
43e65147 915 (*info->fprintf_func) (info->stream, "(%s)",
c8c8175b
SL		 916 nios2_builtin_regs[i].name);
917
918 if (GET_IW_F1X4L17_ID (opcode))
919 (*info->fprintf_func) (info->stream, "++");
920 if (GET_IW_F1X4L17_WB (opcode))
921 (*info->fprintf_func) (info->stream, ",writeback");
922 if (GET_IW_F1X4L17_PC (opcode))
923 (*info->fprintf_func) (info->stream, ",ret");
96ba4233
SL		 924 break;
925 default:
926 bad_opcode (op);
927 }
36591ba1 928 break;
96ba4233 929
36591ba1
SL		 930 default:
931 (*info->fprintf_func) (info->stream, "unknown");
932 break;
933 }
934 return 0;
935}
936
937/* nios2_disassemble does all the work of disassembling a Nios II
938 instruction opcode. */
939static int
940nios2_disassemble (bfd_vma address, unsigned long opcode,
941 disassemble_info *info)
942{
943 const struct nios2_opcode *op;
944
945 info->bytes_per_line = INSNLEN;
946 info->bytes_per_chunk = INSNLEN;
947 info->display_endian = info->endian;
948 info->insn_info_valid = 1;
949 info->branch_delay_insns = 0;
950 info->data_size = 0;
951 info->insn_type = dis_nonbranch;
952 info->target = 0;
953 info->target2 = 0;
954
955 /* Find the major opcode and use this to disassemble
956 the instruction and its arguments. */
b4714c7c 957 op = nios2_find_opcode_hash (opcode, info->mach);
36591ba1
SL		 958
959 if (op != NULL)
960 {
96ba4233
SL		 961 const char *argstr = op->args;
962 (*info->fprintf_func) (info->stream, "%s", op->name);
963 if (argstr != NULL && *argstr != '\0')
36591ba1 964 {
96ba4233
SL		 965 (*info->fprintf_func) (info->stream, "\t");
966 while (*argstr != '\0')
36591ba1 967 {
96ba4233
SL		 968 nios2_print_insn_arg (argstr, opcode, address, info, op);
969 ++argstr;
36591ba1
SL		 970 }
971 }
96ba4233
SL		 972 /* Tell the caller how far to advance the program counter. */
973 info->bytes_per_chunk = op->size;
974 return op->size;
36591ba1
SL		 975 }
976 else
977 {
978 /* Handle undefined instructions. */
979 info->insn_type = dis_noninsn;
980 (*info->fprintf_func) (info->stream, "0x%lx", opcode);
96ba4233 981 return INSNLEN;
36591ba1 982 }
36591ba1
SL		 983}
984
985
986/* print_insn_nios2 is the main disassemble function for Nios II.
987 The function diassembler(abfd) (source in disassemble.c) returns a
988 pointer to this either print_insn_big_nios2 or
989 print_insn_little_nios2, which in turn call this function when the
990 bfd machine type is Nios II. print_insn_nios2 reads the
991 instruction word at the address given, and prints the disassembled
992 instruction on the stream info->stream using info->fprintf_func. */
993
994static int
995print_insn_nios2 (bfd_vma address, disassemble_info *info,
996 enum bfd_endian endianness)
997{
998 bfd_byte buffer[INSNLEN];
999 int status;
1000
1001 status = (*info->read_memory_func) (address, buffer, INSNLEN, info);
1002 if (status == 0)
1003 {
1004 unsigned long insn;
1005 if (endianness == BFD_ENDIAN_BIG)
1006 insn = (unsigned long) bfd_getb32 (buffer);
1007 else
1008 insn = (unsigned long) bfd_getl32 (buffer);
c8c8175b 1009 return nios2_disassemble (address, insn, info);
36591ba1 1010 }
c8c8175b
SL		 1011
1012 /* We might have a 16-bit R2 instruction at the end of memory. Try that. */
1013 if (info->mach == bfd_mach_nios2r2)
36591ba1 1014 {
c8c8175b
SL		 1015 status = (*info->read_memory_func) (address, buffer, 2, info);
1016 if (status == 0)
1017 {
1018 unsigned long insn;
1019 if (endianness == BFD_ENDIAN_BIG)
1020 insn = (unsigned long) bfd_getb16 (buffer);
1021 else
1022 insn = (unsigned long) bfd_getl16 (buffer);
1023 return nios2_disassemble (address, insn, info);
1024 }
36591ba1 1025 }
c8c8175b
SL		 1026
1027 /* If we got here, we couldn't read anything. */
1028 (*info->memory_error_func) (status, address, info);
1029 return -1;
36591ba1
SL		 1030}
1031
1032/* These two functions are the main entry points, accessed from
1033 disassemble.c. */
1034int
1035print_insn_big_nios2 (bfd_vma address, disassemble_info *info)
1036{
1037 return print_insn_nios2 (address, info, BFD_ENDIAN_BIG);
1038}
1039
1040int
1041print_insn_little_nios2 (bfd_vma address, disassemble_info *info)
1042{
1043 return print_insn_nios2 (address, info, BFD_ENDIAN_LITTLE);
1044}
GDB Binutils - Deliverables
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