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PR21990, Integer overflow in process_version_sections
[deliverable/binutils-gdb.git] / opcodes / ppc-opc.c
CommitLineData
252b5132 1/* ppc-opc.c -- PowerPC opcode list
2571583a 2 Copyright (C) 1994-2017 Free Software Foundation, Inc.
252b5132
RH		 3 Written by Ian Lance Taylor, Cygnus Support
4
9b201bb5 5 This file is part of the GNU opcodes library.
252b5132 6
9b201bb5
NC		 7 This library is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3, or (at your option)
10 any later version.
252b5132 11
9b201bb5
NC		 12 It is distributed in the hope that it will be useful, but WITHOUT
13 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
15 License for more details.
252b5132 16
112290ab 17 You should have received a copy of the GNU General Public License
9b201bb5
NC		 18 along with this file; see the file COPYING. If not, write to the
19 Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
20 MA 02110-1301, USA. */
252b5132 21
0d8dfecf 22#include "sysdep.h"
df7b86aa 23#include <stdio.h>
252b5132
RH		 24#include "opcode/ppc.h"
25#include "opintl.h"
26
27/* This file holds the PowerPC opcode table. The opcode table
28 includes almost all of the extended instruction mnemonics. This
29 permits the disassembler to use them, and simplifies the assembler
30 logic, at the cost of increasing the table size. The table is
31 strictly constant data, so the compiler should be able to put it in
32 the .text section.
33
34 This file also holds the operand table. All knowledge about
35 inserting operands into instructions and vice-versa is kept in this
36 file. */
37\f
38/* Local insertion and extraction functions. */
39
b9c361e0
JL		 40static unsigned long insert_arx (unsigned long, long, ppc_cpu_t, const char **);
41static long extract_arx (unsigned long, ppc_cpu_t, int *);
42static unsigned long insert_ary (unsigned long, long, ppc_cpu_t, const char **);
43static long extract_ary (unsigned long, ppc_cpu_t, int *);
fa452fa6
PB		 44static unsigned long insert_bat (unsigned long, long, ppc_cpu_t, const char **);
45static long extract_bat (unsigned long, ppc_cpu_t, int *);
46static unsigned long insert_bba (unsigned long, long, ppc_cpu_t, const char **);
47static long extract_bba (unsigned long, ppc_cpu_t, int *);
48static unsigned long insert_bdm (unsigned long, long, ppc_cpu_t, const char **);
49static long extract_bdm (unsigned long, ppc_cpu_t, int *);
50static unsigned long insert_bdp (unsigned long, long, ppc_cpu_t, const char **);
51static long extract_bdp (unsigned long, ppc_cpu_t, int *);
52static unsigned long insert_bo (unsigned long, long, ppc_cpu_t, const char **);
53static long extract_bo (unsigned long, ppc_cpu_t, int *);
54static unsigned long insert_boe (unsigned long, long, ppc_cpu_t, const char **);
55static long extract_boe (unsigned long, ppc_cpu_t, int *);
7b934113 56static unsigned long insert_esync (unsigned long, long, ppc_cpu_t, const char **);
73f07bff 57static long extract_esync (unsigned long, ppc_cpu_t, int *);
a680de9a
PB		 58static unsigned long insert_dcmxs (unsigned long, long, ppc_cpu_t, const char **);
59static long extract_dcmxs (unsigned long, ppc_cpu_t, int *);
60static unsigned long insert_dxd (unsigned long, long, ppc_cpu_t, const char **);
61static long extract_dxd (unsigned long, ppc_cpu_t, int *);
62static unsigned long insert_dxdn (unsigned long, long, ppc_cpu_t, const char **);
63static long extract_dxdn (unsigned long, ppc_cpu_t, int *);
fa452fa6
PB		 64static unsigned long insert_fxm (unsigned long, long, ppc_cpu_t, const char **);
65static long extract_fxm (unsigned long, ppc_cpu_t, int *);
b9c361e0
JL		 66static unsigned long insert_li20 (unsigned long, long, ppc_cpu_t, const char **);
67static long extract_li20 (unsigned long, ppc_cpu_t, int *);
aea77599 68static unsigned long insert_ls (unsigned long, long, ppc_cpu_t, const char **);
73f07bff 69static long extract_ls (unsigned long, ppc_cpu_t, int *);
fa452fa6
PB		 70static unsigned long insert_mbe (unsigned long, long, ppc_cpu_t, const char **);
71static long extract_mbe (unsigned long, ppc_cpu_t, int *);
72static unsigned long insert_mb6 (unsigned long, long, ppc_cpu_t, const char **);
73static long extract_mb6 (unsigned long, ppc_cpu_t, int *);
74static long extract_nb (unsigned long, ppc_cpu_t, int *);
989993d8 75static unsigned long insert_nbi (unsigned long, long, ppc_cpu_t, const char **);
fa452fa6
PB		 76static unsigned long insert_nsi (unsigned long, long, ppc_cpu_t, const char **);
77static long extract_nsi (unsigned long, ppc_cpu_t, int *);
b9c361e0
JL		 78static unsigned long insert_oimm (unsigned long, long, ppc_cpu_t, const char **);
79static long extract_oimm (unsigned long, ppc_cpu_t, int *);
fa452fa6 80static unsigned long insert_ral (unsigned long, long, ppc_cpu_t, const char **);
73f07bff 81static long extract_ral (unsigned long, ppc_cpu_t, int *);
fa452fa6 82static unsigned long insert_ram (unsigned long, long, ppc_cpu_t, const char **);
73f07bff 83static long extract_ram (unsigned long, ppc_cpu_t, int *);
fa452fa6 84static unsigned long insert_raq (unsigned long, long, ppc_cpu_t, const char **);
73f07bff 85static long extract_raq (unsigned long, ppc_cpu_t, int *);
fa452fa6 86static unsigned long insert_ras (unsigned long, long, ppc_cpu_t, const char **);
73f07bff 87static long extract_ras (unsigned long, ppc_cpu_t, int *);
fa452fa6
PB		 88static unsigned long insert_rbs (unsigned long, long, ppc_cpu_t, const char **);
89static long extract_rbs (unsigned long, ppc_cpu_t, int *);
989993d8 90static unsigned long insert_rbx (unsigned long, long, ppc_cpu_t, const char **);
73f07bff 91static long extract_rbx (unsigned long, ppc_cpu_t, int *);
b9c361e0
JL		 92static unsigned long insert_rx (unsigned long, long, ppc_cpu_t, const char **);
93static long extract_rx (unsigned long, ppc_cpu_t, int *);
94static unsigned long insert_ry (unsigned long, long, ppc_cpu_t, const char **);
95static long extract_ry (unsigned long, ppc_cpu_t, int *);
fa452fa6
PB		 96static unsigned long insert_sh6 (unsigned long, long, ppc_cpu_t, const char **);
97static long extract_sh6 (unsigned long, ppc_cpu_t, int *);
b9c361e0
JL		 98static unsigned long insert_sci8 (unsigned long, long, ppc_cpu_t, const char **);
99static long extract_sci8 (unsigned long, ppc_cpu_t, int *);
100static unsigned long insert_sci8n (unsigned long, long, ppc_cpu_t, const char **);
101static long extract_sci8n (unsigned long, ppc_cpu_t, int *);
102static unsigned long insert_sd4h (unsigned long, long, ppc_cpu_t, const char **);
103static long extract_sd4h (unsigned long, ppc_cpu_t, int *);
104static unsigned long insert_sd4w (unsigned long, long, ppc_cpu_t, const char **);
105static long extract_sd4w (unsigned long, ppc_cpu_t, int *);
fa452fa6
PB		 106static unsigned long insert_spr (unsigned long, long, ppc_cpu_t, const char **);
107static long extract_spr (unsigned long, ppc_cpu_t, int *);
108static unsigned long insert_sprg (unsigned long, long, ppc_cpu_t, const char **);
109static long extract_sprg (unsigned long, ppc_cpu_t, int *);
110static unsigned long insert_tbr (unsigned long, long, ppc_cpu_t, const char **);
111static long extract_tbr (unsigned long, ppc_cpu_t, int *);
9b4e5766
PB		 112static unsigned long insert_xt6 (unsigned long, long, ppc_cpu_t, const char **);
113static long extract_xt6 (unsigned long, ppc_cpu_t, int *);
a680de9a
PB		 114static unsigned long insert_xtq6 (unsigned long, long, ppc_cpu_t, const char **);
115static long extract_xtq6 (unsigned long, ppc_cpu_t, int *);
9b4e5766
PB		 116static unsigned long insert_xa6 (unsigned long, long, ppc_cpu_t, const char **);
117static long extract_xa6 (unsigned long, ppc_cpu_t, int *);
118static unsigned long insert_xb6 (unsigned long, long, ppc_cpu_t, const char **);
119static long extract_xb6 (unsigned long, ppc_cpu_t, int *);
120static unsigned long insert_xb6s (unsigned long, long, ppc_cpu_t, const char **);
121static long extract_xb6s (unsigned long, ppc_cpu_t, int *);
066be9f7
PB		 122static unsigned long insert_xc6 (unsigned long, long, ppc_cpu_t, const char **);
123static long extract_xc6 (unsigned long, ppc_cpu_t, int *);
124static unsigned long insert_dm (unsigned long, long, ppc_cpu_t, const char **);
125static long extract_dm (unsigned long, ppc_cpu_t, int *);
b9c361e0
JL		 126static unsigned long insert_vlesi (unsigned long, long, ppc_cpu_t, const char **);
127static long extract_vlesi (unsigned long, ppc_cpu_t, int *);
128static unsigned long insert_vlensi (unsigned long, long, ppc_cpu_t, const char **);
129static long extract_vlensi (unsigned long, ppc_cpu_t, int *);
130static unsigned long insert_vleui (unsigned long, long, ppc_cpu_t, const char **);
131static long extract_vleui (unsigned long, ppc_cpu_t, int *);
132static unsigned long insert_vleil (unsigned long, long, ppc_cpu_t, const char **);
133static long extract_vleil (unsigned long, ppc_cpu_t, int *);
e3c2f928
AF		 134static unsigned long insert_evuimm2_ex0 (unsigned long, long, ppc_cpu_t, const char **);
135static long extract_evuimm2_ex0 (unsigned long, ppc_cpu_t, int *);
136static unsigned long insert_evuimm4_ex0 (unsigned long, long, ppc_cpu_t, const char **);
137static long extract_evuimm4_ex0 (unsigned long, ppc_cpu_t, int *);
138static unsigned long insert_evuimm8_ex0 (unsigned long, long, ppc_cpu_t, const char **);
139static long extract_evuimm8_ex0 (unsigned long, ppc_cpu_t, int *);
140static unsigned long insert_evuimm_lt16 (unsigned long, long, ppc_cpu_t, const char **);
141static long extract_evuimm_lt16 (unsigned long, ppc_cpu_t, int *);
142static unsigned long insert_rD_rS_even (unsigned long, long, ppc_cpu_t, const char **);
143static long extract_rD_rS_even (unsigned long, ppc_cpu_t, int *);
144static unsigned long insert_off_lsp (unsigned long, long, ppc_cpu_t, const char **);
145static long extract_off_lsp (unsigned long, ppc_cpu_t, int *);
252b5132
RH		 146\f
147/* The operands table.
148
717bbdf1 149 The fields are bitm, shift, insert, extract, flags.
252b5132
RH		 150
151 We used to put parens around the various additions, like the one
152 for BA just below. However, that caused trouble with feeble
153 compilers with a limit on depth of a parenthesized expression, like
154 (reportedly) the compiler in Microsoft Developer Studio 5. So we
155 omit the parens, since the macros are never used in a context where
156 the addition will be ambiguous. */
157
158const struct powerpc_operand powerpc_operands[] =
159{
160 /* The zero index is used to indicate the end of the list of
161 operands. */
162#define UNUSED 0
bbac1f2a 163 { 0, 0, NULL, NULL, 0 },
252b5132
RH		 164
165 /* The BA field in an XL form instruction. */
166#define BA UNUSED + 1
717bbdf1
AM		 167 /* The BI field in a B form or XL form instruction. */
168#define BI BA
169#define BI_MASK (0x1f << 16)
b9c361e0 170 { 0x1f, 16, NULL, NULL, PPC_OPERAND_CR_BIT },
252b5132
RH		 171
172 /* The BA field in an XL form instruction when it must be the same
173 as the BT field in the same instruction. */
174#define BAT BA + 1
b84bf58a 175 { 0x1f, 16, insert_bat, extract_bat, PPC_OPERAND_FAKE },
252b5132
RH		 176
177 /* The BB field in an XL form instruction. */
178#define BB BAT + 1
179#define BB_MASK (0x1f << 11)
b9c361e0 180 { 0x1f, 11, NULL, NULL, PPC_OPERAND_CR_BIT },
252b5132
RH		 181
182 /* The BB field in an XL form instruction when it must be the same
183 as the BA field in the same instruction. */
184#define BBA BB + 1
c7a5aa9c
PB		 185 /* The VB field in a VX form instruction when it must be the same
186 as the VA field in the same instruction. */
187#define VBA BBA
b84bf58a 188 { 0x1f, 11, insert_bba, extract_bba, PPC_OPERAND_FAKE },
252b5132
RH		 189
190 /* The BD field in a B form instruction. The lower two bits are
191 forced to zero. */
192#define BD BBA + 1
b84bf58a 193 { 0xfffc, 0, NULL, NULL, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
252b5132
RH		 194
195 /* The BD field in a B form instruction when absolute addressing is
196 used. */
197#define BDA BD + 1
b84bf58a 198 { 0xfffc, 0, NULL, NULL, PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
252b5132
RH		 199
200 /* The BD field in a B form instruction when the - modifier is used.
201 This sets the y bit of the BO field appropriately. */
202#define BDM BDA + 1
b84bf58a 203 { 0xfffc, 0, insert_bdm, extract_bdm,
e43de63c 204 PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
252b5132
RH		 205
206 /* The BD field in a B form instruction when the - modifier is used
207 and absolute address is used. */
208#define BDMA BDM + 1
b84bf58a 209 { 0xfffc, 0, insert_bdm, extract_bdm,
e43de63c 210 PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
252b5132
RH		 211
212 /* The BD field in a B form instruction when the + modifier is used.
213 This sets the y bit of the BO field appropriately. */
214#define BDP BDMA + 1
b84bf58a 215 { 0xfffc, 0, insert_bdp, extract_bdp,
e43de63c 216 PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
252b5132
RH		 217
218 /* The BD field in a B form instruction when the + modifier is used
219 and absolute addressing is used. */
220#define BDPA BDP + 1
b84bf58a 221 { 0xfffc, 0, insert_bdp, extract_bdp,
e43de63c 222 PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
252b5132
RH		 223
224 /* The BF field in an X or XL form instruction. */
225#define BF BDPA + 1
717bbdf1
AM		 226 /* The CRFD field in an X form instruction. */
227#define CRFD BF
b9c361e0
JL		 228 /* The CRD field in an XL form instruction. */
229#define CRD BF
230 { 0x7, 23, NULL, NULL, PPC_OPERAND_CR_REG },
252b5132 231
ea192fa3
PB		 232 /* The BF field in an X or XL form instruction. */
233#define BFF BF + 1
234 { 0x7, 23, NULL, NULL, 0 },
235
252b5132
RH		 236 /* An optional BF field. This is used for comparison instructions,
237 in which an omitted BF field is taken as zero. */
ea192fa3 238#define OBF BFF + 1
b9c361e0 239 { 0x7, 23, NULL, NULL, PPC_OPERAND_CR_REG | PPC_OPERAND_OPTIONAL },
252b5132
RH		 240
241 /* The BFA field in an X or XL form instruction. */
242#define BFA OBF + 1
b9c361e0 243 { 0x7, 18, NULL, NULL, PPC_OPERAND_CR_REG },
252b5132 244
252b5132
RH		 245 /* The BO field in a B form instruction. Certain values are
246 illegal. */
717bbdf1 247#define BO BFA + 1
252b5132 248#define BO_MASK (0x1f << 21)
b84bf58a 249 { 0x1f, 21, insert_bo, extract_bo, 0 },
252b5132
RH		 250
251 /* The BO field in a B form instruction when the + or - modifier is
252 used. This is like the BO field, but it must be even. */
253#define BOE BO + 1
b84bf58a 254 { 0x1e, 21, insert_boe, extract_boe, 0 },
252b5132 255
6fd3a02d
PB		 256 /* The RM field in an X form instruction. */
257#define RM BOE + 1
258 { 0x3, 11, NULL, NULL, 0 },
259
260#define BH RM + 1
b84bf58a 261 { 0x3, 11, NULL, NULL, PPC_OPERAND_OPTIONAL },
d0618d1c 262
252b5132 263 /* The BT field in an X or XL form instruction. */
d0618d1c 264#define BT BH + 1
b9c361e0
JL		 265 { 0x1f, 21, NULL, NULL, PPC_OPERAND_CR_BIT },
266
267 /* The BI16 field in a BD8 form instruction. */
268#define BI16 BT + 1
269 { 0x3, 8, NULL, NULL, PPC_OPERAND_CR_BIT },
270
271 /* The BI32 field in a BD15 form instruction. */
272#define BI32 BI16 + 1
273 { 0xf, 16, NULL, NULL, PPC_OPERAND_CR_BIT },
274
275 /* The BO32 field in a BD15 form instruction. */
276#define BO32 BI32 + 1
277 { 0x3, 20, NULL, NULL, 0 },
278
279 /* The B8 field in a BD8 form instruction. */
280#define B8 BO32 + 1
281 { 0x1fe, -1, NULL, NULL, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
282
283 /* The B15 field in a BD15 form instruction. The lowest bit is
284 forced to zero. */
285#define B15 B8 + 1
286 { 0xfffe, 0, NULL, NULL, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
287
288 /* The B24 field in a BD24 form instruction. The lowest bit is
289 forced to zero. */
290#define B24 B15 + 1
291 { 0x1fffffe, 0, NULL, NULL, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
252b5132
RH		 292
293 /* The condition register number portion of the BI field in a B form
294 or XL form instruction. This is used for the extended
295 conditional branch mnemonics, which set the lower two bits of the
296 BI field. This field is optional. */
b9c361e0
JL		 297#define CR B24 + 1
298 { 0x7, 18, NULL, NULL, PPC_OPERAND_CR_REG | PPC_OPERAND_OPTIONAL },
252b5132 299
23976049
EZ		 300 /* The CRB field in an X form instruction. */
301#define CRB CR + 1
717bbdf1
AM		 302 /* The MB field in an M form instruction. */
303#define MB CRB
304#define MB_MASK (0x1f << 6)
b84bf58a 305 { 0x1f, 6, NULL, NULL, 0 },
23976049 306
b9c361e0
JL		 307 /* The CRD32 field in an XL form instruction. */
308#define CRD32 CRB + 1
309 { 0x3, 21, NULL, NULL, PPC_OPERAND_CR_REG },
310
23976049 311 /* The CRFS field in an X form instruction. */
b9c361e0
JL		 312#define CRFS CRD32 + 1
313 { 0x7, 0, NULL, NULL, PPC_OPERAND_CR_REG },
314
315#define CRS CRFS + 1
316 { 0x3, 18, NULL, NULL, PPC_OPERAND_CR_REG | PPC_OPERAND_OPTIONAL },
23976049 317
418c1742 318 /* The CT field in an X form instruction. */
b9c361e0 319#define CT CRS + 1
717bbdf1
AM		 320 /* The MO field in an mbar instruction. */
321#define MO CT
b84bf58a 322 { 0x1f, 21, NULL, NULL, PPC_OPERAND_OPTIONAL },
418c1742 323
252b5132
RH		 324 /* The D field in a D form instruction. This is a displacement off
325 a register, and implies that the next operand is a register in
326 parentheses. */
418c1742 327#define D CT + 1
b84bf58a 328 { 0xffff, 0, NULL, NULL, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED },
252b5132 329
b9c361e0
JL		 330 /* The D8 field in a D form instruction. This is a displacement off
331 a register, and implies that the next operand is a register in
332 parentheses. */
333#define D8 D + 1
334 { 0xff, 0, NULL, NULL, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED },
335
a680de9a
PB		 336 /* The DCMX field in an X form instruction. */
337#define DCMX D8 + 1
338 { 0x7f, 16, NULL, NULL, 0 },
339
340 /* The split DCMX field in an X form instruction. */
341#define DCMXS DCMX + 1
342 { 0x7f, PPC_OPSHIFT_INV, insert_dcmxs, extract_dcmxs, 0 },
343
adadcc0c
AM		 344 /* The DQ field in a DQ form instruction. This is like D, but the
345 lower four bits are forced to zero. */
a680de9a 346#define DQ DCMXS + 1
b84bf58a
AM		 347 { 0xfff0, 0, NULL, NULL,
348 PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED | PPC_OPERAND_DQ },
adadcc0c 349
252b5132
RH		 350 /* The DS field in a DS form instruction. This is like D, but the
351 lower two bits are forced to zero. */
adadcc0c 352#define DS DQ + 1
b84bf58a
AM		 353 { 0xfffc, 0, NULL, NULL,
354 PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED | PPC_OPERAND_DS },
252b5132 355
c0637f3a
PB		 356 /* The DUIS or BHRBE fields in a XFX form instruction, 10 bits
357 unsigned imediate */
19a6653c 358#define DUIS DS + 1
c0637f3a 359#define BHRBE DUIS
19a6653c
AM		 360 { 0x3ff, 11, NULL, NULL, 0 },
361
a680de9a
PB		 362 /* The split D field in a DX form instruction. */
363#define DXD DUIS + 1
364 { 0xffff, PPC_OPSHIFT_INV, insert_dxd, extract_dxd,
365 PPC_OPERAND_SIGNED | PPC_OPERAND_SIGNOPT},
366
367 /* The split ND field in a DX form instruction.
368 This is the same as the DX field, only negated. */
369#define NDXD DXD + 1
370 { 0xffff, PPC_OPSHIFT_INV, insert_dxdn, extract_dxdn,
371 PPC_OPERAND_NEGATIVE | PPC_OPERAND_SIGNED | PPC_OPERAND_SIGNOPT},
372
252b5132 373 /* The E field in a wrteei instruction. */
c3d65c1c 374 /* And the W bit in the pair singles instructions. */
c0637f3a 375 /* And the ST field in a VX form instruction. */
a680de9a 376#define E NDXD + 1
c3d65c1c 377#define PSW E
c0637f3a 378#define ST E
b84bf58a 379 { 0x1, 15, NULL, NULL, 0 },
252b5132
RH		 380
381 /* The FL1 field in a POWER SC form instruction. */
382#define FL1 E + 1
717bbdf1
AM		 383 /* The U field in an X form instruction. */
384#define U FL1
b84bf58a 385 { 0xf, 12, NULL, NULL, 0 },
252b5132
RH		 386
387 /* The FL2 field in a POWER SC form instruction. */
388#define FL2 FL1 + 1
b84bf58a 389 { 0x7, 2, NULL, NULL, 0 },
252b5132
RH		 390
391 /* The FLM field in an XFL form instruction. */
392#define FLM FL2 + 1
b84bf58a 393 { 0xff, 17, NULL, NULL, 0 },
252b5132
RH		 394
395 /* The FRA field in an X or A form instruction. */
396#define FRA FLM + 1
397#define FRA_MASK (0x1f << 16)
b84bf58a 398 { 0x1f, 16, NULL, NULL, PPC_OPERAND_FPR },
252b5132 399
989993d8
JB		 400 /* The FRAp field of DFP instructions. */
401#define FRAp FRA + 1
402 { 0x1e, 16, NULL, NULL, PPC_OPERAND_FPR },
403
252b5132 404 /* The FRB field in an X or A form instruction. */
989993d8 405#define FRB FRAp + 1
252b5132 406#define FRB_MASK (0x1f << 11)
b84bf58a 407 { 0x1f, 11, NULL, NULL, PPC_OPERAND_FPR },
252b5132 408
989993d8
JB		 409 /* The FRBp field of DFP instructions. */
410#define FRBp FRB + 1
411 { 0x1e, 11, NULL, NULL, PPC_OPERAND_FPR },
412
252b5132 413 /* The FRC field in an A form instruction. */
989993d8 414#define FRC FRBp + 1
252b5132 415#define FRC_MASK (0x1f << 6)
b84bf58a 416 { 0x1f, 6, NULL, NULL, PPC_OPERAND_FPR },
252b5132
RH		 417
418 /* The FRS field in an X form instruction or the FRT field in a D, X
419 or A form instruction. */
420#define FRS FRC + 1
421#define FRT FRS
b84bf58a 422 { 0x1f, 21, NULL, NULL, PPC_OPERAND_FPR },
252b5132 423
989993d8
JB		 424 /* The FRSp field of stfdp or the FRTp field of lfdp and DFP
425 instructions. */
426#define FRSp FRS + 1
427#define FRTp FRSp
428 { 0x1e, 21, NULL, NULL, PPC_OPERAND_FPR },
429
252b5132 430 /* The FXM field in an XFX instruction. */
989993d8 431#define FXM FRSp + 1
b84bf58a 432 { 0xff, 12, insert_fxm, extract_fxm, 0 },
c168870a
AM		 433
434 /* Power4 version for mfcr. */
435#define FXM4 FXM + 1
e43de63c
AM		 436 { 0xff, 12, insert_fxm, extract_fxm,
437 PPC_OPERAND_OPTIONAL | PPC_OPERAND_OPTIONAL_VALUE},
11a0cf2e
PB		 438 /* If the FXM4 operand is ommitted, use the sentinel value -1. */
439 { -1, -1, NULL, NULL, 0},
252b5132 440
b9c361e0 441 /* The IMM20 field in an LI instruction. */
11a0cf2e 442#define IMM20 FXM4 + 2
b9c361e0
JL		 443 { 0xfffff, PPC_OPSHIFT_INV, insert_li20, extract_li20, PPC_OPERAND_SIGNED},
444
252b5132 445 /* The L field in a D or X form instruction. */
b9c361e0 446#define L IMM20 + 1
a5721ba2
AM		 447 { 0x1, 21, NULL, NULL, 0 },
448
449 /* The optional L field in tlbie and tlbiel instructions. */
450#define LOPT L + 1
5817ffd1 451 /* The R field in a HTM X form instruction. */
a5721ba2 452#define HTM_R LOPT
b84bf58a 453 { 0x1, 21, NULL, NULL, PPC_OPERAND_OPTIONAL },
252b5132 454
a5721ba2
AM		 455 /* The optional (for 32-bit) L field in cmp[l][i] instructions. */
456#define L32OPT LOPT + 1
457 { 0x1, 21, NULL, NULL, PPC_OPERAND_OPTIONAL | PPC_OPERAND_OPTIONAL32 },
a680de9a 458
a5721ba2
AM		 459 /* The L field in dcbf instruction. */
460#define L2OPT L32OPT + 1
461 { 0x3, 21, NULL, NULL, PPC_OPERAND_OPTIONAL },
a680de9a 462
dce75bf9 463 /* The LEV field in a POWER SVC / POWER9 SCV form instruction. */
a5721ba2 464#define SVC_LEV L2OPT + 1
b84bf58a 465 { 0x7f, 5, NULL, NULL, 0 },
252b5132 466
1ed8e1e4
AM		 467 /* The LEV field in an SC form instruction. */
468#define LEV SVC_LEV + 1
b84bf58a 469 { 0x7f, 5, NULL, NULL, PPC_OPERAND_OPTIONAL },
1ed8e1e4 470
252b5132
RH		 471 /* The LI field in an I form instruction. The lower two bits are
472 forced to zero. */
473#define LI LEV + 1
b84bf58a 474 { 0x3fffffc, 0, NULL, NULL, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
252b5132
RH		 475
476 /* The LI field in an I form instruction when used as an absolute
477 address. */
478#define LIA LI + 1
b84bf58a 479 { 0x3fffffc, 0, NULL, NULL, PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
252b5132 480
066be9f7 481 /* The LS or WC field in an X (sync or wait) form instruction. */
6ba045b1 482#define LS LIA + 1
066be9f7 483#define WC LS
73f07bff 484 { 0x3, 21, insert_ls, extract_ls, PPC_OPERAND_OPTIONAL },
6ba045b1 485
252b5132 486 /* The ME field in an M form instruction. */
717bbdf1 487#define ME LS + 1
252b5132 488#define ME_MASK (0x1f << 1)
b84bf58a 489 { 0x1f, 1, NULL, NULL, 0 },
252b5132
RH		 490
491 /* The MB and ME fields in an M form instruction expressed a single
492 operand which is a bitmask indicating which bits to select. This
493 is a two operand form using PPC_OPERAND_NEXT. See the
494 description in opcode/ppc.h for what this means. */
495#define MBE ME + 1
b84bf58a 496 { 0x1f, 6, NULL, NULL, PPC_OPERAND_OPTIONAL | PPC_OPERAND_NEXT },
eb42fac1 497 { -1, 0, insert_mbe, extract_mbe, 0 },
252b5132
RH		 498
499 /* The MB or ME field in an MD or MDS form instruction. The high
500 bit is wrapped to the low end. */
501#define MB6 MBE + 2
502#define ME6 MB6
503#define MB6_MASK (0x3f << 5)
b84bf58a 504 { 0x3f, 5, insert_mb6, extract_mb6, 0 },
252b5132
RH		 505
506 /* The NB field in an X form instruction. The value 32 is stored as
507 0. */
717bbdf1 508#define NB MB6 + 1
b84bf58a 509 { 0x1f, 11, NULL, extract_nb, PPC_OPERAND_PLUS1 },
252b5132 510
989993d8
JB		 511 /* The NBI field in an lswi instruction, which has special value
512 restrictions. The value 32 is stored as 0. */
513#define NBI NB + 1
514 { 0x1f, 11, insert_nbi, extract_nb, PPC_OPERAND_PLUS1 },
515
252b5132
RH		 516 /* The NSI field in a D form instruction. This is the same as the
517 SI field, only negated. */
989993d8 518#define NSI NBI + 1
b84bf58a 519 { 0xffff, 0, insert_nsi, extract_nsi,
e43de63c
AM		 520 PPC_OPERAND_NEGATIVE | PPC_OPERAND_SIGNED },
521
522 /* The NSI field in a D form instruction when we accept a wide range
523 of positive values. */
524#define NSISIGNOPT NSI + 1
514e58b7 525 { 0xffff, 0, insert_nsi, extract_nsi,
e43de63c 526 PPC_OPERAND_NEGATIVE | PPC_OPERAND_SIGNED | PPC_OPERAND_SIGNOPT },
252b5132 527
adadcc0c 528 /* The RA field in an D, DS, DQ, X, XO, M, or MDS form instruction. */
e43de63c 529#define RA NSISIGNOPT + 1
252b5132 530#define RA_MASK (0x1f << 16)
b84bf58a 531 { 0x1f, 16, NULL, NULL, PPC_OPERAND_GPR },
252b5132 532
fdd12ef3
AM		 533 /* As above, but 0 in the RA field means zero, not r0. */
534#define RA0 RA + 1
b84bf58a 535 { 0x1f, 16, NULL, NULL, PPC_OPERAND_GPR_0 },
fdd12ef3 536
989993d8 537 /* The RA field in the DQ form lq or an lswx instruction, which have special
adadcc0c 538 value restrictions. */
fdd12ef3 539#define RAQ RA0 + 1
989993d8 540#define RAX RAQ
73f07bff 541 { 0x1f, 16, insert_raq, extract_raq, PPC_OPERAND_GPR_0 },
adadcc0c 542
252b5132
RH		 543 /* The RA field in a D or X form instruction which is an updating
544 load, which means that the RA field may not be zero and may not
545 equal the RT field. */
adadcc0c 546#define RAL RAQ + 1
73f07bff 547 { 0x1f, 16, insert_ral, extract_ral, PPC_OPERAND_GPR_0 },
252b5132
RH		 548
549 /* The RA field in an lmw instruction, which has special value
550 restrictions. */
551#define RAM RAL + 1
73f07bff 552 { 0x1f, 16, insert_ram, extract_ram, PPC_OPERAND_GPR_0 },
252b5132
RH		 553
554 /* The RA field in a D or X form instruction which is an updating
555 store or an updating floating point load, which means that the RA
556 field may not be zero. */
557#define RAS RAM + 1
73f07bff 558 { 0x1f, 16, insert_ras, extract_ras, PPC_OPERAND_GPR_0 },
252b5132 559
cee62821
PB		 560 /* The RA field of the tlbwe, dccci and iccci instructions,
561 which are optional. */
fdd12ef3 562#define RAOPT RAS + 1
b84bf58a 563 { 0x1f, 16, NULL, NULL, PPC_OPERAND_GPR | PPC_OPERAND_OPTIONAL },
1f6c9eb0 564
252b5132 565 /* The RB field in an X, XO, M, or MDS form instruction. */
fdd12ef3 566#define RB RAOPT + 1
252b5132 567#define RB_MASK (0x1f << 11)
b84bf58a 568 { 0x1f, 11, NULL, NULL, PPC_OPERAND_GPR },
252b5132
RH		 569
570 /* The RB field in an X form instruction when it must be the same as
571 the RS field in the instruction. This is used for extended
572 mnemonics like mr. */
573#define RBS RB + 1
b84bf58a 574 { 0x1f, 11, insert_rbs, extract_rbs, PPC_OPERAND_FAKE },
252b5132 575
989993d8
JB		 576 /* The RB field in an lswx instruction, which has special value
577 restrictions. */
578#define RBX RBS + 1
73f07bff 579 { 0x1f, 11, insert_rbx, extract_rbx, PPC_OPERAND_GPR },
989993d8 580
cee62821 581 /* The RB field of the dccci and iccci instructions, which are optional. */
989993d8 582#define RBOPT RBX + 1
cee62821
PB		 583 { 0x1f, 11, NULL, NULL, PPC_OPERAND_GPR | PPC_OPERAND_OPTIONAL },
584
a680de9a
PB		 585 /* The RC register field in an maddld, maddhd or maddhdu instruction. */
586#define RC RBOPT + 1
587 { 0x1f, 6, NULL, NULL, PPC_OPERAND_GPR },
588
252b5132
RH		 589 /* The RS field in a D, DS, X, XFX, XS, M, MD or MDS form
590 instruction or the RT field in a D, DS, X, XFX or XO form
591 instruction. */
a680de9a 592#define RS RC + 1
252b5132
RH		 593#define RT RS
594#define RT_MASK (0x1f << 21)
b9c361e0 595#define RD RS
b84bf58a 596 { 0x1f, 21, NULL, NULL, PPC_OPERAND_GPR },
252b5132 597
e3c2f928
AF		 598#define RD_EVEN RS + 1
599#define RS_EVEN RD_EVEN
600 { 0x1f, 21, insert_rD_rS_even, extract_rD_rS_even, PPC_OPERAND_GPR },
601
588925d0
PB		 602 /* The RS and RT fields of the DS form stq and DQ form lq instructions,
603 which have special value restrictions. */
e3c2f928 604#define RSQ RS_EVEN + 1
717bbdf1 605#define RTQ RSQ
73f07bff 606#define Q_MASK (1 << 21)
588925d0 607 { 0x1e, 21, NULL, NULL, PPC_OPERAND_GPR },
adadcc0c 608
1f6c9eb0 609 /* The RS field of the tlbwe instruction, which is optional. */
717bbdf1 610#define RSO RSQ + 1
eed0d89a 611#define RTO RSO
b84bf58a 612 { 0x1f, 21, NULL, NULL, PPC_OPERAND_GPR | PPC_OPERAND_OPTIONAL },
1f6c9eb0 613
b9c361e0
JL		 614 /* The RX field of the SE_RR form instruction. */
615#define RX RSO + 1
616 { 0x1f, PPC_OPSHIFT_INV, insert_rx, extract_rx, PPC_OPERAND_GPR },
617
618 /* The ARX field of the SE_RR form instruction. */
619#define ARX RX + 1
620 { 0x1f, PPC_OPSHIFT_INV, insert_arx, extract_arx, PPC_OPERAND_GPR },
621
622 /* The RY field of the SE_RR form instruction. */
623#define RY ARX + 1
624#define RZ RY
625 { 0x1f, PPC_OPSHIFT_INV, insert_ry, extract_ry, PPC_OPERAND_GPR },
626
627 /* The ARY field of the SE_RR form instruction. */
628#define ARY RY + 1
629 { 0x1f, PPC_OPSHIFT_INV, insert_ary, extract_ary, PPC_OPERAND_GPR },
630
631 /* The SCLSCI8 field in a D form instruction. */
632#define SCLSCI8 ARY + 1
633 { 0xffffffff, PPC_OPSHIFT_INV, insert_sci8, extract_sci8, 0 },
634
635 /* The SCLSCI8N field in a D form instruction. This is the same as the
636 SCLSCI8 field, only negated. */
637#define SCLSCI8N SCLSCI8 + 1
638 { 0xffffffff, PPC_OPSHIFT_INV, insert_sci8n, extract_sci8n,
e43de63c 639 PPC_OPERAND_NEGATIVE | PPC_OPERAND_SIGNED },
b9c361e0
JL		 640
641 /* The SD field of the SD4 form instruction. */
642#define SE_SD SCLSCI8N + 1
643 { 0xf, 8, NULL, NULL, PPC_OPERAND_PARENS },
644
645 /* The SD field of the SD4 form instruction, for halfword. */
646#define SE_SDH SE_SD + 1
647 { 0x1e, PPC_OPSHIFT_INV, insert_sd4h, extract_sd4h, PPC_OPERAND_PARENS },
648
649 /* The SD field of the SD4 form instruction, for word. */
650#define SE_SDW SE_SDH + 1
651 { 0x3c, PPC_OPSHIFT_INV, insert_sd4w, extract_sd4w, PPC_OPERAND_PARENS },
652
252b5132 653 /* The SH field in an X or M form instruction. */
b9c361e0 654#define SH SE_SDW + 1
252b5132 655#define SH_MASK (0x1f << 11)
717bbdf1
AM		 656 /* The other UIMM field in a EVX form instruction. */
657#define EVUIMM SH
a680de9a
PB		 658 /* The FC field in an atomic X form instruction. */
659#define FC SH
b84bf58a 660 { 0x1f, 11, NULL, NULL, 0 },
252b5132 661
e3c2f928
AF		 662#define EVUIMM_LT16 SH + 1
663 { 0x1f, 11, insert_evuimm_lt16, extract_evuimm_lt16, 0 },
664
5817ffd1 665 /* The SI field in a HTM X form instruction. */
e3c2f928 666#define HTM_SI EVUIMM_LT16 + 1
5817ffd1
PB		 667 { 0x1f, 11, NULL, NULL, PPC_OPERAND_SIGNED },
668
252b5132 669 /* The SH field in an MD form instruction. This is split. */
5817ffd1 670#define SH6 HTM_SI + 1
252b5132 671#define SH6_MASK ((0x1f << 11) | (1 << 1))
b9c361e0 672 { 0x3f, PPC_OPSHIFT_INV, insert_sh6, extract_sh6, 0 },
252b5132 673
a8cc8a54
AM		 674 /* The SH field of some variants of the tlbre and tlbwe
675 instructions, and the ELEV field of the e_sc instruction. */
1f6c9eb0 676#define SHO SH6 + 1
a8cc8a54 677#define ELEV SHO
b84bf58a 678 { 0x1f, 11, NULL, NULL, PPC_OPERAND_OPTIONAL },
1f6c9eb0 679
252b5132 680 /* The SI field in a D form instruction. */
1f6c9eb0 681#define SI SHO + 1
b84bf58a 682 { 0xffff, 0, NULL, NULL, PPC_OPERAND_SIGNED },
252b5132
RH		 683
684 /* The SI field in a D form instruction when we accept a wide range
685 of positive values. */
686#define SISIGNOPT SI + 1
b84bf58a 687 { 0xffff, 0, NULL, NULL, PPC_OPERAND_SIGNED | PPC_OPERAND_SIGNOPT },
252b5132 688
b9c361e0
JL		 689 /* The SI8 field in a D form instruction. */
690#define SI8 SISIGNOPT + 1
691 { 0xff, 0, NULL, NULL, PPC_OPERAND_SIGNED },
692
252b5132
RH		 693 /* The SPR field in an XFX form instruction. This is flipped--the
694 lower 5 bits are stored in the upper 5 and vice- versa. */
b9c361e0 695#define SPR SI8 + 1
914749f6 696#define PMR SPR
aea77599 697#define TMR SPR
252b5132 698#define SPR_MASK (0x3ff << 11)
7e0de605 699 { 0x3ff, 11, insert_spr, extract_spr, PPC_OPERAND_SPR },
252b5132
RH		 700
701 /* The BAT index number in an XFX form m[ft]ibat[lu] instruction. */
702#define SPRBAT SPR + 1
703#define SPRBAT_MASK (0x3 << 17)
b84bf58a 704 { 0x3, 17, NULL, NULL, 0 },
252b5132
RH		 705
706 /* The SPRG register number in an XFX form m[ft]sprg instruction. */
707#define SPRG SPRBAT + 1
7e0de605 708 { 0x1f, 16, insert_sprg, extract_sprg, PPC_OPERAND_SPR },
252b5132
RH		 709
710 /* The SR field in an X form instruction. */
711#define SR SPRG + 1
fb048c26
PB		 712 /* The 4-bit UIMM field in a VX form instruction. */
713#define UIMM4 SR
b84bf58a 714 { 0xf, 16, NULL, NULL, 0 },
252b5132 715
f5c120c5
MG		 716 /* The STRM field in an X AltiVec form instruction. */
717#define STRM SR + 1
19a6653c
AM		 718 /* The T field in a tlbilx form instruction. */
719#define T STRM
a5721ba2
AM		 720 /* The L field in wclr instructions. */
721#define L2 STRM
b84bf58a 722 { 0x3, 21, NULL, NULL, 0 },
f5c120c5 723
aea77599
AM		 724 /* The ESYNC field in an X (sync) form instruction. */
725#define ESYNC STRM + 1
73f07bff 726 { 0xf, 16, insert_esync, extract_esync, PPC_OPERAND_OPTIONAL },
aea77599 727
252b5132 728 /* The SV field in a POWER SC form instruction. */
aea77599 729#define SV ESYNC + 1
b84bf58a 730 { 0x3fff, 2, NULL, NULL, 0 },
252b5132
RH		 731
732 /* The TBR field in an XFX form instruction. This is like the SPR
733 field, but it is optional. */
734#define TBR SV + 1
e43de63c 735 { 0x3ff, 11, insert_tbr, extract_tbr,
7e0de605 736 PPC_OPERAND_SPR | PPC_OPERAND_OPTIONAL | PPC_OPERAND_OPTIONAL_VALUE},
11a0cf2e
PB		 737 /* If the TBR operand is ommitted, use the value 268. */
738 { -1, 268, NULL, NULL, 0},
252b5132
RH		 739
740 /* The TO field in a D or X form instruction. */
11a0cf2e 741#define TO TBR + 2
19a6653c 742#define DUI TO
252b5132 743#define TO_MASK (0x1f << 21)
b84bf58a 744 { 0x1f, 21, NULL, NULL, 0 },
252b5132 745
252b5132 746 /* The UI field in a D form instruction. */
717bbdf1 747#define UI TO + 1
b84bf58a 748 { 0xffff, 0, NULL, NULL, 0 },
786e2c0f 749
a47622ac
AM		 750#define UISIGNOPT UI + 1
751 { 0xffff, 0, NULL, NULL, PPC_OPERAND_SIGNOPT },
752
b9c361e0 753 /* The IMM field in an SE_IM5 instruction. */
a47622ac 754#define UI5 UISIGNOPT + 1
b9c361e0
JL		 755 { 0x1f, 4, NULL, NULL, 0 },
756
757 /* The OIMM field in an SE_OIM5 instruction. */
758#define OIMM5 UI5 + 1
759 { 0x1f, PPC_OPSHIFT_INV, insert_oimm, extract_oimm, PPC_OPERAND_PLUS1 },
760
761 /* The UI7 field in an SE_LI instruction. */
762#define UI7 OIMM5 + 1
763 { 0x7f, 4, NULL, NULL, 0 },
764
112290ab 765 /* The VA field in a VA, VX or VXR form instruction. */
b9c361e0 766#define VA UI7 + 1
b84bf58a 767 { 0x1f, 16, NULL, NULL, PPC_OPERAND_VR },
786e2c0f 768
112290ab 769 /* The VB field in a VA, VX or VXR form instruction. */
786e2c0f 770#define VB VA + 1
b84bf58a 771 { 0x1f, 11, NULL, NULL, PPC_OPERAND_VR },
786e2c0f 772
112290ab 773 /* The VC field in a VA form instruction. */
786e2c0f 774#define VC VB + 1
b84bf58a 775 { 0x1f, 6, NULL, NULL, PPC_OPERAND_VR },
786e2c0f 776
112290ab 777 /* The VD or VS field in a VA, VX, VXR or X form instruction. */
786e2c0f
C		 778#define VD VC + 1
779#define VS VD
b84bf58a 780 { 0x1f, 21, NULL, NULL, PPC_OPERAND_VR },
786e2c0f 781
8dbcd839 782 /* The SIMM field in a VX form instruction, and TE in Z form. */
786e2c0f 783#define SIMM VD + 1
8dbcd839 784#define TE SIMM
b84bf58a 785 { 0x1f, 16, NULL, NULL, PPC_OPERAND_SIGNED},
786e2c0f 786
8dbcd839 787 /* The UIMM field in a VX form instruction. */
786e2c0f 788#define UIMM SIMM + 1
aea77599 789#define DCTL UIMM
b84bf58a 790 { 0x1f, 16, NULL, NULL, 0 },
786e2c0f 791
fb048c26
PB		 792 /* The 3-bit UIMM field in a VX form instruction. */
793#define UIMM3 UIMM + 1
794 { 0x7, 16, NULL, NULL, 0 },
795
a680de9a
PB		 796 /* The 6-bit UIM field in a X form instruction. */
797#define UIM6 UIMM3 + 1
798 { 0x3f, 16, NULL, NULL, 0 },
799
c0637f3a 800 /* The SIX field in a VX form instruction. */
a680de9a 801#define SIX UIM6 + 1
c0637f3a
PB		 802 { 0xf, 11, NULL, NULL, 0 },
803
804 /* The PS field in a VX form instruction. */
805#define PS SIX + 1
806 { 0x1, 9, NULL, NULL, 0 },
807
112290ab 808 /* The SHB field in a VA form instruction. */
c0637f3a 809#define SHB PS + 1
b84bf58a 810 { 0xf, 6, NULL, NULL, 0 },
ff3a6ee3 811
112290ab 812 /* The other UIMM field in a half word EVX form instruction. */
717bbdf1 813#define EVUIMM_2 SHB + 1
b84bf58a 814 { 0x3e, 10, NULL, NULL, PPC_OPERAND_PARENS },
23976049 815
e3c2f928
AF		 816#define EVUIMM_2_EX0 EVUIMM_2 + 1
817 { 0x3e, 10, insert_evuimm2_ex0, extract_evuimm2_ex0, PPC_OPERAND_PARENS },
818
112290ab 819 /* The other UIMM field in a word EVX form instruction. */
e3c2f928 820#define EVUIMM_4 EVUIMM_2_EX0 + 1
b84bf58a 821 { 0x7c, 9, NULL, NULL, PPC_OPERAND_PARENS },
23976049 822
e3c2f928
AF		 823#define EVUIMM_4_EX0 EVUIMM_4 + 1
824 { 0x7c, 9, insert_evuimm4_ex0, extract_evuimm4_ex0, PPC_OPERAND_PARENS },
825
112290ab 826 /* The other UIMM field in a double EVX form instruction. */
e3c2f928 827#define EVUIMM_8 EVUIMM_4_EX0 + 1
b84bf58a 828 { 0xf8, 8, NULL, NULL, PPC_OPERAND_PARENS },
23976049 829
e3c2f928
AF		 830#define EVUIMM_8_EX0 EVUIMM_8 + 1
831 { 0xf8, 8, insert_evuimm8_ex0, extract_evuimm8_ex0, PPC_OPERAND_PARENS },
832
6fd3a02d 833 /* The WS or DRM field in an X form instruction. */
e3c2f928 834#define WS EVUIMM_8_EX0 + 1
6fd3a02d 835#define DRM WS
b84bf58a 836 { 0x7, 11, NULL, NULL, 0 },
ff3a6ee3 837
c3d65c1c
BE		 838 /* PowerPC paired singles extensions. */
839 /* W bit in the pair singles instructions for x type instructions. */
840#define PSWM WS + 1
b9c361e0
JL		 841 /* The BO16 field in a BD8 form instruction. */
842#define BO16 PSWM
c3d65c1c
BE		 843 { 0x1, 10, 0, 0, 0 },
844
845 /* IDX bits for quantization in the pair singles instructions. */
846#define PSQ PSWM + 1
7e0de605 847 { 0x7, 12, 0, 0, PPC_OPERAND_GQR },
c3d65c1c
BE		 848
849 /* IDX bits for quantization in the pair singles x-type instructions. */
850#define PSQM PSQ + 1
7e0de605 851 { 0x7, 7, 0, 0, PPC_OPERAND_GQR },
c3d65c1c
BE		 852
853 /* Smaller D field for quantization in the pair singles instructions. */
854#define PSD PSQM + 1
855 { 0xfff, 0, 0, 0, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED },
856
a680de9a 857 /* The L field in an mtmsrd or A form instruction or R or W in an X form. */
c3d65c1c 858#define A_L PSD + 1
ea192fa3 859#define W A_L
a680de9a 860#define X_R A_L
b84bf58a 861 { 0x1, 16, NULL, NULL, PPC_OPERAND_OPTIONAL },
5ae2e65e 862
19dfcc89 863 /* The RMC or CY field in a Z23 form instruction. */
99a2c561 864#define RMC A_L + 1
19dfcc89 865#define CY RMC
b84bf58a 866 { 0x3, 9, NULL, NULL, 0 },
702f0fb4
PB		 867
868#define R RMC + 1
b84bf58a 869 { 0x1, 16, NULL, NULL, 0 },
702f0fb4 870
a680de9a
PB		 871#define RIC R + 1
872 { 0x3, 18, NULL, NULL, PPC_OPERAND_OPTIONAL },
873
874#define PRS RIC + 1
875 { 0x1, 17, NULL, NULL, PPC_OPERAND_OPTIONAL },
876
877#define SP PRS + 1
b84bf58a 878 { 0x3, 19, NULL, NULL, 0 },
702f0fb4
PB		 879
880#define S SP + 1
b84bf58a 881 { 0x1, 20, NULL, NULL, 0 },
702f0fb4 882
c0637f3a
PB		 883 /* The S field in a XL form instruction. */
884#define SXL S + 1
11a0cf2e
PB		 885 { 0x1, 11, NULL, NULL, PPC_OPERAND_OPTIONAL | PPC_OPERAND_OPTIONAL_VALUE},
886 /* If the SXL operand is ommitted, use the value 1. */
887 { -1, 1, NULL, NULL, 0},
c0637f3a 888
702f0fb4 889 /* SH field starting at bit position 16. */
11a0cf2e 890#define SH16 SXL + 2
0bbdef92
AM		 891 /* The DCM and DGM fields in a Z form instruction. */
892#define DCM SH16
893#define DGM DCM
b84bf58a 894 { 0x3f, 10, NULL, NULL, 0 },
702f0fb4 895
702f0fb4 896 /* The EH field in larx instruction. */
717bbdf1 897#define EH SH16 + 1
b84bf58a 898 { 0x1, 0, NULL, NULL, PPC_OPERAND_OPTIONAL },
ea192fa3
PB		 899
900 /* The L field in an mtfsf or XFL form instruction. */
5817ffd1 901 /* The A field in a HTM X form instruction. */
ea192fa3 902#define XFL_L EH + 1
5817ffd1 903#define HTM_A XFL_L
ea192fa3 904 { 0x1, 25, NULL, NULL, PPC_OPERAND_OPTIONAL},
081ba1b3
AM		 905
906 /* Xilinx APU related masks and macros */
907#define FCRT XFL_L + 1
908#define FCRT_MASK (0x1f << 21)
909 { 0x1f, 21, 0, 0, PPC_OPERAND_FCR },
910
43e65147 911 /* Xilinx FSL related masks and macros */
081ba1b3
AM		 912#define FSL FCRT + 1
913#define FSL_MASK (0x1f << 11)
43e65147 914 { 0x1f, 11, 0, 0, PPC_OPERAND_FSL },
081ba1b3 915
43e65147 916 /* Xilinx UDI related masks and macros */
081ba1b3
AM		 917#define URT FSL + 1
918 { 0x1f, 21, 0, 0, PPC_OPERAND_UDI },
919
920#define URA URT + 1
921 { 0x1f, 16, 0, 0, PPC_OPERAND_UDI },
922
923#define URB URA + 1
924 { 0x1f, 11, 0, 0, PPC_OPERAND_UDI },
925
926#define URC URB + 1
927 { 0x1f, 6, 0, 0, PPC_OPERAND_UDI },
928
b9c361e0
JL		 929 /* The VLESIMM field in a D form instruction. */
930#define VLESIMM URC + 1
931 { 0xffff, PPC_OPSHIFT_INV, insert_vlesi, extract_vlesi,
e43de63c 932 PPC_OPERAND_SIGNED | PPC_OPERAND_SIGNOPT },
b9c361e0
JL		 933
934 /* The VLENSIMM field in a D form instruction. */
935#define VLENSIMM VLESIMM + 1
936 { 0xffff, PPC_OPSHIFT_INV, insert_vlensi, extract_vlensi,
e43de63c 937 PPC_OPERAND_NEGATIVE | PPC_OPERAND_SIGNED | PPC_OPERAND_SIGNOPT },
b9c361e0
JL		 938
939 /* The VLEUIMM field in a D form instruction. */
940#define VLEUIMM VLENSIMM + 1
941 { 0xffff, PPC_OPSHIFT_INV, insert_vleui, extract_vleui, 0 },
942
943 /* The VLEUIMML field in a D form instruction. */
944#define VLEUIMML VLEUIMM + 1
945 { 0xffff, PPC_OPSHIFT_INV, insert_vleil, extract_vleil, 0 },
946
9b4e5766 947 /* The XT and XS fields in an XX1 or XX3 form instruction. This is split. */
b9c361e0 948#define XS6 VLEUIMML + 1
9b4e5766 949#define XT6 XS6
b9c361e0 950 { 0x3f, PPC_OPSHIFT_INV, insert_xt6, extract_xt6, PPC_OPERAND_VSR },
9b4e5766 951
a680de9a
PB		 952 /* The XT and XS fields in an DQ form VSX instruction. This is split. */
953#define XSQ6 XT6 + 1
954#define XTQ6 XSQ6
955 { 0x3f, PPC_OPSHIFT_INV, insert_xtq6, extract_xtq6, PPC_OPERAND_VSR },
956
9b4e5766 957 /* The XA field in an XX3 form instruction. This is split. */
a680de9a 958#define XA6 XTQ6 + 1
b9c361e0 959 { 0x3f, PPC_OPSHIFT_INV, insert_xa6, extract_xa6, PPC_OPERAND_VSR },
9b4e5766 960
066be9f7 961 /* The XB field in an XX2 or XX3 form instruction. This is split. */
9b4e5766 962#define XB6 XA6 + 1
b9c361e0 963 { 0x3f, PPC_OPSHIFT_INV, insert_xb6, extract_xb6, PPC_OPERAND_VSR },
9b4e5766
PB		 964
965 /* The XB field in an XX3 form instruction when it must be the same as
966 the XA field in the instruction. This is used in extended mnemonics
967 like xvmovdp. This is split. */
968#define XB6S XB6 + 1
b9c361e0 969 { 0x3f, PPC_OPSHIFT_INV, insert_xb6s, extract_xb6s, PPC_OPERAND_FAKE },
9b4e5766 970
066be9f7
PB		 971 /* The XC field in an XX4 form instruction. This is split. */
972#define XC6 XB6S + 1
b9c361e0 973 { 0x3f, PPC_OPSHIFT_INV, insert_xc6, extract_xc6, PPC_OPERAND_VSR },
066be9f7
PB		 974
975 /* The DM or SHW field in an XX3 form instruction. */
976#define DM XC6 + 1
977#define SHW DM
9b4e5766 978 { 0x3, 8, NULL, NULL, 0 },
066be9f7
PB		 979
980 /* The DM field in an extended mnemonic XX3 form instruction. */
981#define DMEX DM + 1
982 { 0x3, 8, insert_dm, extract_dm, 0 },
983
984 /* The UIM field in an XX2 form instruction. */
985#define UIM DMEX + 1
fb048c26
PB		 986 /* The 2-bit UIMM field in a VX form instruction. */
987#define UIMM2 UIM
a680de9a
PB		 988 /* The 2-bit L field in a darn instruction. */
989#define LRAND UIM
066be9f7 990 { 0x3, 16, NULL, NULL, 0 },
e0d602ec
BE		 991
992#define ERAT_T UIM + 1
993 { 0x7, 21, NULL, NULL, 0 },
4bc0608a
PB		 994
995#define IH ERAT_T + 1
996 { 0x7, 21, NULL, NULL, PPC_OPERAND_OPTIONAL },
a680de9a
PB		 997
998 /* The 8-bit IMM8 field in a XX1 form instruction. */
999#define IMM8 IH + 1
1178da44 1000 { 0xff, 11, NULL, NULL, PPC_OPERAND_SIGNOPT },
e3c2f928
AF		 1001
1002#define VX_OFF IMM8 + 1
1003 { 0x3, 0, insert_off_lsp, extract_off_lsp, 0 },
252b5132
RH		 1004};
1005
b84bf58a
AM		 1006const unsigned int num_powerpc_operands = (sizeof (powerpc_operands)
1007 / sizeof (powerpc_operands[0]));
1008
252b5132
RH		 1009/* The functions used to insert and extract complicated operands. */
1010
b9c361e0
JL		 1011/* The ARX, ARY, RX and RY operands are alternate encodings of GPRs. */
1012
1013static unsigned long
1014insert_arx (unsigned long insn,
1015 long value,
1016 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1017 const char **errmsg ATTRIBUTE_UNUSED)
1018{
1019 if (value >= 8 && value < 24)
1020 return insn | ((value - 8) & 0xf);
1021 else
1022 {
1023 *errmsg = _("invalid register");
1024 return 0;
1025 }
1026}
1027
1028static long
1029extract_arx (unsigned long insn,
1030 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1031 int *invalid ATTRIBUTE_UNUSED)
43e65147 1032{
b9c361e0
JL		 1033 return (insn & 0xf) + 8;
1034}
1035
1036static unsigned long
1037insert_ary (unsigned long insn,
1038 long value,
1039 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1040 const char **errmsg ATTRIBUTE_UNUSED)
1041{
1042 if (value >= 8 && value < 24)
1043 return insn | (((value - 8) & 0xf) << 4);
1044 else
1045 {
1046 *errmsg = _("invalid register");
1047 return 0;
1048 }
1049}
1050
1051static long
1052extract_ary (unsigned long insn,
1053 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1054 int *invalid ATTRIBUTE_UNUSED)
1055{
1056 return ((insn >> 4) & 0xf) + 8;
1057}
1058
1059static unsigned long
1060insert_rx (unsigned long insn,
1061 long value,
1062 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1063 const char **errmsg)
1064{
1065 if (value >= 0 && value < 8)
1066 return insn | value;
1067 else if (value >= 24 && value <= 31)
1068 return insn | (value - 16);
1069 else
1070 {
1071 *errmsg = _("invalid register");
1072 return 0;
1073 }
1074}
1075
1076static long
1077extract_rx (unsigned long insn,
1078 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1079 int *invalid ATTRIBUTE_UNUSED)
1080{
1081 int value = insn & 0xf;
1082 if (value >= 0 && value < 8)
1083 return value;
1084 else
1085 return value + 16;
1086}
1087
1088static unsigned long
1089insert_ry (unsigned long insn,
1090 long value,
1091 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1092 const char **errmsg)
1093{
1094 if (value >= 0 && value < 8)
1095 return insn | (value << 4);
1096 else if (value >= 24 && value <= 31)
1097 return insn | ((value - 16) << 4);
1098 else
1099 {
1100 *errmsg = _("invalid register");
1101 return 0;
1102 }
1103}
1104
1105static long
1106extract_ry (unsigned long insn,
1107 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1108 int *invalid ATTRIBUTE_UNUSED)
1109{
1110 int value = (insn >> 4) & 0xf;
1111 if (value >= 0 && value < 8)
1112 return value;
1113 else
1114 return value + 16;
1115}
1116
252b5132
RH		 1117/* The BA field in an XL form instruction when it must be the same as
1118 the BT field in the same instruction. This operand is marked FAKE.
1119 The insertion function just copies the BT field into the BA field,
1120 and the extraction function just checks that the fields are the
1121 same. */
1122
252b5132 1123static unsigned long
2fbfdc41
AM		 1124insert_bat (unsigned long insn,
1125 long value ATTRIBUTE_UNUSED,
fa452fa6 1126 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2fbfdc41 1127 const char **errmsg ATTRIBUTE_UNUSED)
252b5132
RH		 1128{
1129 return insn | (((insn >> 21) & 0x1f) << 16);
1130}
1131
1132static long
2fbfdc41 1133extract_bat (unsigned long insn,
fa452fa6 1134 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2fbfdc41 1135 int *invalid)
252b5132 1136{
8427c424 1137 if (((insn >> 21) & 0x1f) != ((insn >> 16) & 0x1f))
252b5132
RH		 1138 *invalid = 1;
1139 return 0;
1140}
1141
1142/* The BB field in an XL form instruction when it must be the same as
1143 the BA field in the same instruction. This operand is marked FAKE.
1144 The insertion function just copies the BA field into the BB field,
1145 and the extraction function just checks that the fields are the
1146 same. */
1147
252b5132 1148static unsigned long
2fbfdc41
AM		 1149insert_bba (unsigned long insn,
1150 long value ATTRIBUTE_UNUSED,
fa452fa6 1151 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2fbfdc41 1152 const char **errmsg ATTRIBUTE_UNUSED)
252b5132
RH		 1153{
1154 return insn | (((insn >> 16) & 0x1f) << 11);
1155}
1156
1157static long
2fbfdc41 1158extract_bba (unsigned long insn,
fa452fa6 1159 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2fbfdc41 1160 int *invalid)
252b5132 1161{
8427c424 1162 if (((insn >> 16) & 0x1f) != ((insn >> 11) & 0x1f))
252b5132
RH		 1163 *invalid = 1;
1164 return 0;
1165}
1166
252b5132
RH		 1167/* The BD field in a B form instruction when the - modifier is used.
1168 This modifier means that the branch is not expected to be taken.
94efba12
AM		 1169 For chips built to versions of the architecture prior to version 2
1170 (ie. not Power4 compatible), we set the y bit of the BO field to 1
1171 if the offset is negative. When extracting, we require that the y
1172 bit be 1 and that the offset be positive, since if the y bit is 0
1173 we just want to print the normal form of the instruction.
1174 Power4 compatible targets use two bits, "a", and "t", instead of
1175 the "y" bit. "at" == 00 => no hint, "at" == 01 => unpredictable,
1176 "at" == 10 => not taken, "at" == 11 => taken. The "t" bit is 00001
1177 in BO field, the "a" bit is 00010 for branch on CR(BI) and 01000
ba4e851b
AM		 1178 for branch on CTR. We only handle the taken/not-taken hint here.
1179 Note that we don't relax the conditions tested here when
1180 disassembling with -Many because insns using extract_bdm and
1181 extract_bdp always occur in pairs. One or the other will always
1182 be valid. */
252b5132 1183
8ebac3aa
AM		 1184#define ISA_V2 (PPC_OPCODE_POWER4 | PPC_OPCODE_E500MC | PPC_OPCODE_TITAN)
1185
252b5132 1186static unsigned long
2fbfdc41
AM		 1187insert_bdm (unsigned long insn,
1188 long value,
fa452fa6 1189 ppc_cpu_t dialect,
2fbfdc41 1190 const char **errmsg ATTRIBUTE_UNUSED)
252b5132 1191{
8ebac3aa 1192 if ((dialect & ISA_V2) == 0)
802a735e
AM		 1193 {
1194 if ((value & 0x8000) != 0)
1195 insn |= 1 << 21;
1196 }
1197 else
1198 {
1199 if ((insn & (0x14 << 21)) == (0x04 << 21))
1200 insn |= 0x02 << 21;
1201 else if ((insn & (0x14 << 21)) == (0x10 << 21))
1202 insn |= 0x08 << 21;
1203 }
252b5132
RH		 1204 return insn | (value & 0xfffc);
1205}
1206
1207static long
2fbfdc41 1208extract_bdm (unsigned long insn,
fa452fa6 1209 ppc_cpu_t dialect,
2fbfdc41 1210 int *invalid)
252b5132 1211{
8ebac3aa 1212 if ((dialect & ISA_V2) == 0)
802a735e 1213 {
8427c424
AM		 1214 if (((insn & (1 << 21)) == 0) != ((insn & (1 << 15)) == 0))
1215 *invalid = 1;
802a735e 1216 }
8427c424
AM		 1217 else
1218 {
1219 if ((insn & (0x17 << 21)) != (0x06 << 21)
1220 && (insn & (0x1d << 21)) != (0x18 << 21))
1221 *invalid = 1;
1222 }
1223
802a735e 1224 return ((insn & 0xfffc) ^ 0x8000) - 0x8000;
252b5132
RH		 1225}
1226
1227/* The BD field in a B form instruction when the + modifier is used.
1228 This is like BDM, above, except that the branch is expected to be
1229 taken. */
1230
252b5132 1231static unsigned long
2fbfdc41
AM		 1232insert_bdp (unsigned long insn,
1233 long value,
fa452fa6 1234 ppc_cpu_t dialect,
2fbfdc41 1235 const char **errmsg ATTRIBUTE_UNUSED)
252b5132 1236{
8ebac3aa 1237 if ((dialect & ISA_V2) == 0)
802a735e
AM		 1238 {
1239 if ((value & 0x8000) == 0)
1240 insn |= 1 << 21;
1241 }
1242 else
1243 {
1244 if ((insn & (0x14 << 21)) == (0x04 << 21))
1245 insn |= 0x03 << 21;
1246 else if ((insn & (0x14 << 21)) == (0x10 << 21))
1247 insn |= 0x09 << 21;
1248 }
252b5132
RH		 1249 return insn | (value & 0xfffc);
1250}
1251
1252static long
2fbfdc41 1253extract_bdp (unsigned long insn,
fa452fa6 1254 ppc_cpu_t dialect,
2fbfdc41 1255 int *invalid)
252b5132 1256{
8ebac3aa 1257 if ((dialect & ISA_V2) == 0)
802a735e 1258 {
8427c424
AM		 1259 if (((insn & (1 << 21)) == 0) == ((insn & (1 << 15)) == 0))
1260 *invalid = 1;
1261 }
1262 else
1263 {
1264 if ((insn & (0x17 << 21)) != (0x07 << 21)
1265 && (insn & (0x1d << 21)) != (0x19 << 21))
1266 *invalid = 1;
802a735e 1267 }
8427c424 1268
802a735e 1269 return ((insn & 0xfffc) ^ 0x8000) - 0x8000;
252b5132
RH		 1270}
1271
8ebac3aa
AM		 1272static inline int
1273valid_bo_pre_v2 (long value)
252b5132 1274{
8ebac3aa
AM		 1275 /* Certain encodings have bits that are required to be zero.
1276 These are (z must be zero, y may be anything):
43e65147
L		 1277 0000y
1278 0001y
8ebac3aa 1279 001zy
43e65147
L		 1280 0100y
1281 0101y
8ebac3aa
AM		 1282 011zy
1283 1z00y
1284 1z01y
1285 1z1zz
1286 */
1287 if ((value & 0x14) == 0)
1288 return 1;
1289 else if ((value & 0x14) == 0x4)
1290 return (value & 0x2) == 0;
1291 else if ((value & 0x14) == 0x10)
1292 return (value & 0x8) == 0;
1293 else
1294 return value == 0x14;
1295}
ba4e851b 1296
8ebac3aa
AM		 1297static inline int
1298valid_bo_post_v2 (long value)
1299{
ba4e851b
AM		 1300 /* Certain encodings have bits that are required to be zero.
1301 These are (z must be zero, a & t may be anything):
1302 0000z
1303 0001z
8ebac3aa 1304 001at
ba4e851b
AM		 1305 0100z
1306 0101z
ba4e851b
AM		 1307 011at
1308 1a00t
1309 1a01t
1310 1z1zz
1311 */
1312 if ((value & 0x14) == 0)
1313 return (value & 0x1) == 0;
1314 else if ((value & 0x14) == 0x14)
1315 return value == 0x14;
802a735e 1316 else
ba4e851b 1317 return 1;
252b5132
RH		 1318}
1319
8ebac3aa
AM		 1320/* Check for legal values of a BO field. */
1321
1322static int
1323valid_bo (long value, ppc_cpu_t dialect, int extract)
1324{
1325 int valid_y = valid_bo_pre_v2 (value);
1326 int valid_at = valid_bo_post_v2 (value);
1327
1328 /* When disassembling with -Many, accept either encoding on the
1329 second pass through opcodes. */
1330 if (extract && dialect == ~(ppc_cpu_t) PPC_OPCODE_ANY)
1331 return valid_y || valid_at;
1332 if ((dialect & ISA_V2) == 0)
1333 return valid_y;
1334 else
1335 return valid_at;
1336}
1337
252b5132
RH		 1338/* The BO field in a B form instruction. Warn about attempts to set
1339 the field to an illegal value. */
1340
1341static unsigned long
2fbfdc41
AM		 1342insert_bo (unsigned long insn,
1343 long value,
fa452fa6 1344 ppc_cpu_t dialect,
2fbfdc41 1345 const char **errmsg)
252b5132 1346{
ba4e851b 1347 if (!valid_bo (value, dialect, 0))
252b5132 1348 *errmsg = _("invalid conditional option");
989993d8
JB		 1349 else if (PPC_OP (insn) == 19 && (insn & 0x400) && ! (value & 4))
1350 *errmsg = _("invalid counter access");
252b5132
RH		 1351 return insn | ((value & 0x1f) << 21);
1352}
1353
1354static long
2fbfdc41 1355extract_bo (unsigned long insn,
fa452fa6 1356 ppc_cpu_t dialect,
2fbfdc41 1357 int *invalid)
252b5132
RH		 1358{
1359 long value;
1360
1361 value = (insn >> 21) & 0x1f;
ba4e851b 1362 if (!valid_bo (value, dialect, 1))
252b5132
RH		 1363 *invalid = 1;
1364 return value;
1365}
1366
1367/* The BO field in a B form instruction when the + or - modifier is
1368 used. This is like the BO field, but it must be even. When
1369 extracting it, we force it to be even. */
1370
1371static unsigned long
2fbfdc41
AM		 1372insert_boe (unsigned long insn,
1373 long value,
fa452fa6 1374 ppc_cpu_t dialect,
2fbfdc41 1375 const char **errmsg)
252b5132 1376{
ba4e851b 1377 if (!valid_bo (value, dialect, 0))
8427c424 1378 *errmsg = _("invalid conditional option");
989993d8
JB		 1379 else if (PPC_OP (insn) == 19 && (insn & 0x400) && ! (value & 4))
1380 *errmsg = _("invalid counter access");
8427c424
AM		 1381 else if ((value & 1) != 0)
1382 *errmsg = _("attempt to set y bit when using + or - modifier");
1383
252b5132
RH		 1384 return insn | ((value & 0x1f) << 21);
1385}
1386
1387static long
2fbfdc41 1388extract_boe (unsigned long insn,
fa452fa6 1389 ppc_cpu_t dialect,
2fbfdc41 1390 int *invalid)
252b5132
RH		 1391{
1392 long value;
1393
1394 value = (insn >> 21) & 0x1f;
ba4e851b 1395 if (!valid_bo (value, dialect, 1))
252b5132
RH		 1396 *invalid = 1;
1397 return value & 0x1e;
1398}
1399
a680de9a
PB		 1400/* The DCMX field in a X form instruction when the field is split
1401 into separate DC, DM and DX fields. */
1402
1403static unsigned long
1404insert_dcmxs (unsigned long insn,
1405 long value,
1406 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1407 const char **errmsg ATTRIBUTE_UNUSED)
1408{
1409 return insn | ((value & 0x1f) << 16) | ((value & 0x20) >> 3) | (value & 0x40);
1410}
1411
1412static long
1413extract_dcmxs (unsigned long insn,
1414 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1415 int *invalid ATTRIBUTE_UNUSED)
1416{
1417 return (insn & 0x40) | ((insn << 3) & 0x20) | ((insn >> 16) & 0x1f);
1418}
1419
1420/* The D field in a DX form instruction when the field is split
1421 into separate D0, D1 and D2 fields. */
1422
1423static unsigned long
1424insert_dxd (unsigned long insn,
1425 long value,
1426 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1427 const char **errmsg ATTRIBUTE_UNUSED)
1428{
1429 return insn | (value & 0xffc1) | ((value & 0x3e) << 15);
1430}
1431
1432static long
1433extract_dxd (unsigned long insn,
1434 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1435 int *invalid ATTRIBUTE_UNUSED)
1436{
1437 unsigned long dxd = (insn & 0xffc1) | ((insn >> 15) & 0x3e);
1438 return (dxd ^ 0x8000) - 0x8000;
1439}
1440
1441static unsigned long
1442insert_dxdn (unsigned long insn,
1443 long value,
1444 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1445 const char **errmsg ATTRIBUTE_UNUSED)
1446{
1447 return insert_dxd (insn, -value, dialect, errmsg);
1448}
1449
1450static long
1451extract_dxdn (unsigned long insn,
1452 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1453 int *invalid ATTRIBUTE_UNUSED)
1454{
1455 return -extract_dxd (insn, dialect, invalid);
1456}
1457
2fbfdc41
AM		 1458/* FXM mask in mfcr and mtcrf instructions. */
1459
1460static unsigned long
1461insert_fxm (unsigned long insn,
1462 long value,
fa452fa6 1463 ppc_cpu_t dialect,
2fbfdc41 1464 const char **errmsg)
c168870a 1465{
98e69875
AM		 1466 /* If we're handling the mfocrf and mtocrf insns ensure that exactly
1467 one bit of the mask field is set. */
1468 if ((insn & (1 << 20)) != 0)
1469 {
1470 if (value == 0 || (value & -value) != value)
1471 {
1472 *errmsg = _("invalid mask field");
1473 value = 0;
1474 }
1475 }
1476
c168870a 1477 /* If only one bit of the FXM field is set, we can use the new form
661bd698 1478 of the instruction, which is faster. Unlike the Power4 branch hint
a30e9cc4
AM		 1479 encoding, this is not backward compatible. Do not generate the
1480 new form unless -mpower4 has been given, or -many and the two
1481 operand form of mfcr was used. */
11a0cf2e
PB		 1482 else if (value > 0
1483 && (value & -value) == value
a30e9cc4
AM		 1484 && ((dialect & PPC_OPCODE_POWER4) != 0
1485 || ((dialect & PPC_OPCODE_ANY) != 0
1486 && (insn & (0x3ff << 1)) == 19 << 1)))
c168870a
AM		 1487 insn |= 1 << 20;
1488
1489 /* Any other value on mfcr is an error. */
1490 else if ((insn & (0x3ff << 1)) == 19 << 1)
1491 {
11a0cf2e
PB		 1492 /* A value of -1 means we used the one operand form of
1493 mfcr which is valid. */
1494 if (value != -1)
b817670b 1495 *errmsg = _("invalid mfcr mask");
c168870a
AM		 1496 value = 0;
1497 }
1498
1499 return insn | ((value & 0xff) << 12);
1500}
1501
2fbfdc41
AM		 1502static long
1503extract_fxm (unsigned long insn,
fa452fa6 1504 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2fbfdc41 1505 int *invalid)
c168870a
AM		 1506{
1507 long mask = (insn >> 12) & 0xff;
1508
1509 /* Is this a Power4 insn? */
1510 if ((insn & (1 << 20)) != 0)
1511 {
98e69875
AM		 1512 /* Exactly one bit of MASK should be set. */
1513 if (mask == 0 || (mask & -mask) != mask)
8427c424 1514 *invalid = 1;
c168870a
AM		 1515 }
1516
1517 /* Check that non-power4 form of mfcr has a zero MASK. */
1518 else if ((insn & (0x3ff << 1)) == 19 << 1)
1519 {
8427c424 1520 if (mask != 0)
c168870a 1521 *invalid = 1;
11a0cf2e
PB		 1522 else
1523 mask = -1;
c168870a
AM		 1524 }
1525
1526 return mask;
1527}
1528
b9c361e0
JL		 1529static unsigned long
1530insert_li20 (unsigned long insn,
1531 long value,
1532 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1533 const char **errmsg ATTRIBUTE_UNUSED)
1534{
1535 return insn | ((value & 0xf0000) >> 5) | ((value & 0x0f800) << 5) | (value & 0x7ff);
1536}
1537
1538static long
1539extract_li20 (unsigned long insn,
1540 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1541 int *invalid ATTRIBUTE_UNUSED)
1542{
1543 long ext = ((insn & 0x4000) == 0x4000) ? 0xfff00000 : 0x00000000;
1544
1545 return ext
1546 | (((insn >> 11) & 0xf) << 16)
1547 | (((insn >> 17) & 0xf) << 12)
1548 | (((insn >> 16) & 0x1) << 11)
1549 | (insn & 0x7ff);
1550}
1551
7b934113
PB		 1552/* The 2-bit L field in a SYNC or WC field in a WAIT instruction.
1553 For SYNC, some L values are reserved:
1554 * Value 3 is reserved on newer server cpus.
1555 * Values 2 and 3 are reserved on all other cpus. */
aea77599
AM		 1556
1557static unsigned long
1558insert_ls (unsigned long insn,
1559 long value,
7b934113
PB		 1560 ppc_cpu_t dialect,
1561 const char **errmsg)
1562{
1563 /* For SYNC, some L values are illegal. */
1564 if (((insn >> 1) & 0x3ff) == 598)
1565 {
1566 long max_lvalue = (dialect & PPC_OPCODE_POWER4) ? 2 : 1;
1567 if (value > max_lvalue)
1568 {
1569 *errmsg = _("illegal L operand value");
1570 return insn;
1571 }
1572 }
1573
1574 return insn | ((value & 0x3) << 21);
1575}
1576
73f07bff
AM		 1577static long
1578extract_ls (unsigned long insn,
1579 ppc_cpu_t dialect,
1580 int *invalid)
1581{
1582 unsigned long lvalue = (insn >> 21) & 3;
1583
1584 if (((insn >> 1) & 0x3ff) == 598)
1585 {
1586 unsigned long max_lvalue = (dialect & PPC_OPCODE_POWER4) ? 2 : 1;
1587 if (lvalue > max_lvalue)
1588 *invalid = 1;
1589 }
1590 return lvalue;
1591}
1592
7b934113
PB		 1593/* The 4-bit E field in a sync instruction that accepts 2 operands.
1594 If ESYNC is non-zero, then the L field must be either 0 or 1 and
1595 the complement of ESYNC-bit2. */
1596
1597static unsigned long
1598insert_esync (unsigned long insn,
1599 long value,
a680de9a 1600 ppc_cpu_t dialect,
7b934113 1601 const char **errmsg)
aea77599 1602{
a680de9a 1603 unsigned long ls = (insn >> 21) & 0x03;
aea77599 1604
aea77599
AM		 1605 if (value == 0)
1606 {
a680de9a
PB		 1607 if (((dialect & PPC_OPCODE_E6500) != 0 && ls > 1)
1608 || ((dialect & PPC_OPCODE_POWER9) != 0 && ls > 2))
1609 *errmsg = _("illegal L operand value");
aea77599
AM		 1610 return insn;
1611 }
7b934113
PB		 1612
1613 if ((ls & ~0x1)
1614 || (((value >> 1) & 0x1) ^ ls) == 0)
1615 *errmsg = _("incompatible L operand value");
1616
1617 return insn | ((value & 0xf) << 16);
aea77599
AM		 1618}
1619
73f07bff
AM		 1620static long
1621extract_esync (unsigned long insn,
1622 ppc_cpu_t dialect,
1623 int *invalid)
1624{
1625 unsigned long ls = (insn >> 21) & 0x3;
1626 unsigned long lvalue = (insn >> 16) & 0xf;
1627
1628 if (lvalue == 0)
1629 {
1630 if (((dialect & PPC_OPCODE_E6500) != 0 && ls > 1)
1631 || ((dialect & PPC_OPCODE_POWER9) != 0 && ls > 2))
1632 *invalid = 1;
1633 }
1634 else if ((ls & ~0x1)
1635 || (((lvalue >> 1) & 0x1) ^ ls) == 0)
1636 *invalid = 1;
1637
1638 return lvalue;
1639}
1640
252b5132
RH		 1641/* The MB and ME fields in an M form instruction expressed as a single
1642 operand which is itself a bitmask. The extraction function always
1643 marks it as invalid, since we never want to recognize an
1644 instruction which uses a field of this type. */
1645
1646static unsigned long
2fbfdc41
AM		 1647insert_mbe (unsigned long insn,
1648 long value,
fa452fa6 1649 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2fbfdc41 1650 const char **errmsg)
252b5132
RH		 1651{
1652 unsigned long uval, mask;
1653 int mb, me, mx, count, last;
1654
1655 uval = value;
1656
1657 if (uval == 0)
1658 {
8427c424 1659 *errmsg = _("illegal bitmask");
252b5132
RH		 1660 return insn;
1661 }
1662
1663 mb = 0;
1664 me = 32;
1665 if ((uval & 1) != 0)
1666 last = 1;
1667 else
1668 last = 0;
1669 count = 0;
1670
1671 /* mb: location of last 0->1 transition */
1672 /* me: location of last 1->0 transition */
1673 /* count: # transitions */
1674
0deb7ac5 1675 for (mx = 0, mask = 1L << 31; mx < 32; ++mx, mask >>= 1)
252b5132
RH		 1676 {
1677 if ((uval & mask) && !last)
1678 {
1679 ++count;
1680 mb = mx;
1681 last = 1;
1682 }
1683 else if (!(uval & mask) && last)
1684 {
1685 ++count;
1686 me = mx;
1687 last = 0;
1688 }
1689 }
1690 if (me == 0)
1691 me = 32;
1692
1693 if (count != 2 && (count != 0 || ! last))
8427c424 1694 *errmsg = _("illegal bitmask");
252b5132
RH		 1695
1696 return insn | (mb << 6) | ((me - 1) << 1);
1697}
1698
1699static long
2fbfdc41 1700extract_mbe (unsigned long insn,
fa452fa6 1701 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2fbfdc41 1702 int *invalid)
252b5132
RH		 1703{
1704 long ret;
1705 int mb, me;
1706 int i;
1707
8427c424 1708 *invalid = 1;
252b5132
RH		 1709
1710 mb = (insn >> 6) & 0x1f;
1711 me = (insn >> 1) & 0x1f;
1712 if (mb < me + 1)
1713 {
1714 ret = 0;
1715 for (i = mb; i <= me; i++)
0deb7ac5 1716 ret |= 1L << (31 - i);
252b5132
RH		 1717 }
1718 else if (mb == me + 1)
8427c424 1719 ret = ~0;
252b5132
RH		 1720 else /* (mb > me + 1) */
1721 {
2fbfdc41 1722 ret = ~0;
252b5132 1723 for (i = me + 1; i < mb; i++)
0deb7ac5 1724 ret &= ~(1L << (31 - i));
252b5132
RH		 1725 }
1726 return ret;
1727}
1728
1729/* The MB or ME field in an MD or MDS form instruction. The high bit
1730 is wrapped to the low end. */
1731
252b5132 1732static unsigned long
2fbfdc41
AM		 1733insert_mb6 (unsigned long insn,
1734 long value,
fa452fa6 1735 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2fbfdc41 1736 const char **errmsg ATTRIBUTE_UNUSED)
252b5132
RH		 1737{
1738 return insn | ((value & 0x1f) << 6) | (value & 0x20);
1739}
1740
252b5132 1741static long
2fbfdc41 1742extract_mb6 (unsigned long insn,
fa452fa6 1743 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2fbfdc41 1744 int *invalid ATTRIBUTE_UNUSED)
252b5132
RH		 1745{
1746 return ((insn >> 6) & 0x1f) | (insn & 0x20);
1747}
1748
1749/* The NB field in an X form instruction. The value 32 is stored as
1750 0. */
1751
252b5132 1752static long
2fbfdc41 1753extract_nb (unsigned long insn,
fa452fa6 1754 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2fbfdc41 1755 int *invalid ATTRIBUTE_UNUSED)
252b5132
RH		 1756{
1757 long ret;
1758
1759 ret = (insn >> 11) & 0x1f;
1760 if (ret == 0)
1761 ret = 32;
1762 return ret;
1763}
1764
989993d8
JB		 1765/* The NB field in an lswi instruction, which has special value
1766 restrictions. The value 32 is stored as 0. */
1767
1768static unsigned long
1769insert_nbi (unsigned long insn,
1770 long value,
1771 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1772 const char **errmsg ATTRIBUTE_UNUSED)
1773{
1774 long rtvalue = (insn & RT_MASK) >> 21;
1775 long ravalue = (insn & RA_MASK) >> 16;
1776
1777 if (value == 0)
1778 value = 32;
1779 if (rtvalue + (value + 3) / 4 > (rtvalue > ravalue ? ravalue + 32
1780 : ravalue))
1781 *errmsg = _("address register in load range");
1782 return insn | ((value & 0x1f) << 11);
1783}
1784
252b5132
RH		 1785/* The NSI field in a D form instruction. This is the same as the SI
1786 field, only negated. The extraction function always marks it as
1787 invalid, since we never want to recognize an instruction which uses
1788 a field of this type. */
1789
252b5132 1790static unsigned long
2fbfdc41
AM		 1791insert_nsi (unsigned long insn,
1792 long value,
fa452fa6 1793 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2fbfdc41 1794 const char **errmsg ATTRIBUTE_UNUSED)
252b5132 1795{
2fbfdc41 1796 return insn | (-value & 0xffff);
252b5132
RH		 1797}
1798
1799static long
2fbfdc41 1800extract_nsi (unsigned long insn,
fa452fa6 1801 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2fbfdc41 1802 int *invalid)
252b5132 1803{
8427c424 1804 *invalid = 1;
2fbfdc41 1805 return -(((insn & 0xffff) ^ 0x8000) - 0x8000);
252b5132
RH		 1806}
1807
1808/* The RA field in a D or X form instruction which is an updating
1809 load, which means that the RA field may not be zero and may not
1810 equal the RT field. */
1811
1812static unsigned long
2fbfdc41
AM		 1813insert_ral (unsigned long insn,
1814 long value,
fa452fa6 1815 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2fbfdc41 1816 const char **errmsg)
252b5132
RH		 1817{
1818 if (value == 0
1819 || (unsigned long) value == ((insn >> 21) & 0x1f))
1820 *errmsg = "invalid register operand when updating";
1821 return insn | ((value & 0x1f) << 16);
1822}
1823
73f07bff
AM		 1824static long
1825extract_ral (unsigned long insn,
1826 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1827 int *invalid)
1828{
1829 long rtvalue = (insn >> 21) & 0x1f;
1830 long ravalue = (insn >> 16) & 0x1f;
1831
1832 if (rtvalue == ravalue || ravalue == 0)
1833 *invalid = 1;
1834 return ravalue;
1835}
1836
252b5132
RH		 1837/* The RA field in an lmw instruction, which has special value
1838 restrictions. */
1839
1840static unsigned long
2fbfdc41
AM		 1841insert_ram (unsigned long insn,
1842 long value,
fa452fa6 1843 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2fbfdc41 1844 const char **errmsg)
252b5132
RH		 1845{
1846 if ((unsigned long) value >= ((insn >> 21) & 0x1f))
1847 *errmsg = _("index register in load range");
1848 return insn | ((value & 0x1f) << 16);
1849}
1850
73f07bff
AM		 1851static long
1852extract_ram (unsigned long insn,
1853 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1854 int *invalid)
1855{
1856 unsigned long rtvalue = (insn >> 21) & 0x1f;
1857 unsigned long ravalue = (insn >> 16) & 0x1f;
1858
1859 if (ravalue >= rtvalue)
1860 *invalid = 1;
1861 return ravalue;
1862}
1863
989993d8 1864/* The RA field in the DQ form lq or an lswx instruction, which have special
8427c424 1865 value restrictions. */
adadcc0c 1866
adadcc0c 1867static unsigned long
2fbfdc41
AM		 1868insert_raq (unsigned long insn,
1869 long value,
fa452fa6 1870 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2fbfdc41 1871 const char **errmsg)
adadcc0c
AM		 1872{
1873 long rtvalue = (insn & RT_MASK) >> 21;
1874
8427c424 1875 if (value == rtvalue)
adadcc0c
AM		 1876 *errmsg = _("source and target register operands must be different");
1877 return insn | ((value & 0x1f) << 16);
1878}
1879
73f07bff
AM		 1880static long
1881extract_raq (unsigned long insn,
1882 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1883 int *invalid)
1884{
1885 unsigned long rtvalue = (insn >> 21) & 0x1f;
1886 unsigned long ravalue = (insn >> 16) & 0x1f;
1887
1888 if (ravalue == rtvalue)
1889 *invalid = 1;
1890 return ravalue;
1891}
1892
252b5132
RH		 1893/* The RA field in a D or X form instruction which is an updating
1894 store or an updating floating point load, which means that the RA
1895 field may not be zero. */
1896
1897static unsigned long
2fbfdc41
AM		 1898insert_ras (unsigned long insn,
1899 long value,
fa452fa6 1900 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2fbfdc41 1901 const char **errmsg)
252b5132
RH		 1902{
1903 if (value == 0)
1904 *errmsg = _("invalid register operand when updating");
1905 return insn | ((value & 0x1f) << 16);
1906}
1907
73f07bff
AM		 1908static long
1909extract_ras (unsigned long insn,
1910 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1911 int *invalid)
1912{
1913 unsigned long ravalue = (insn >> 16) & 0x1f;
1914
1915 if (ravalue == 0)
1916 *invalid = 1;
1917 return ravalue;
1918}
1919
252b5132
RH		 1920/* The RB field in an X form instruction when it must be the same as
1921 the RS field in the instruction. This is used for extended
1922 mnemonics like mr. This operand is marked FAKE. The insertion
1923 function just copies the BT field into the BA field, and the
1924 extraction function just checks that the fields are the same. */
1925
252b5132 1926static unsigned long
2fbfdc41
AM		 1927insert_rbs (unsigned long insn,
1928 long value ATTRIBUTE_UNUSED,
fa452fa6 1929 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2fbfdc41 1930 const char **errmsg ATTRIBUTE_UNUSED)
252b5132
RH		 1931{
1932 return insn | (((insn >> 21) & 0x1f) << 11);
1933}
1934
1935static long
2fbfdc41 1936extract_rbs (unsigned long insn,
fa452fa6 1937 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2fbfdc41 1938 int *invalid)
252b5132 1939{
8427c424 1940 if (((insn >> 21) & 0x1f) != ((insn >> 11) & 0x1f))
252b5132
RH		 1941 *invalid = 1;
1942 return 0;
1943}
1944
989993d8
JB		 1945/* The RB field in an lswx instruction, which has special value
1946 restrictions. */
1947
1948static unsigned long
1949insert_rbx (unsigned long insn,
1950 long value,
1951 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1952 const char **errmsg)
1953{
1954 long rtvalue = (insn & RT_MASK) >> 21;
1955
1956 if (value == rtvalue)
1957 *errmsg = _("source and target register operands must be different");
1958 return insn | ((value & 0x1f) << 11);
1959}
1960
73f07bff
AM		 1961static long
1962extract_rbx (unsigned long insn,
1963 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1964 int *invalid)
1965{
1966 unsigned long rtvalue = (insn >> 21) & 0x1f;
1967 unsigned long rbvalue = (insn >> 11) & 0x1f;
1968
1969 if (rbvalue == rtvalue)
1970 *invalid = 1;
1971 return rbvalue;
1972}
1973
b9c361e0
JL		 1974/* The SCI8 field is made up of SCL and {U,N}I8 fields. */
1975static unsigned long
1976insert_sci8 (unsigned long insn,
1977 long value,
1978 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1979 const char **errmsg)
1980{
943d398f
AM		 1981 unsigned int fill_scale = 0;
1982 unsigned long ui8 = value;
b9c361e0 1983
943d398f
AM		 1984 if ((ui8 & 0xffffff00) == 0)
1985 ;
1986 else if ((ui8 & 0xffffff00) == 0xffffff00)
1987 fill_scale = 0x400;
1988 else if ((ui8 & 0xffff00ff) == 0)
b9c361e0 1989 {
943d398f
AM		 1990 fill_scale = 1 << 8;
1991 ui8 >>= 8;
b9c361e0 1992 }
943d398f 1993 else if ((ui8 & 0xffff00ff) == 0xffff00ff)
b9c361e0 1994 {
943d398f
AM		 1995 fill_scale = 0x400 | (1 << 8);
1996 ui8 >>= 8;
b9c361e0 1997 }
943d398f 1998 else if ((ui8 & 0xff00ffff) == 0)
b9c361e0 1999 {
943d398f
AM		 2000 fill_scale = 2 << 8;
2001 ui8 >>= 16;
b9c361e0 2002 }
943d398f 2003 else if ((ui8 & 0xff00ffff) == 0xff00ffff)
b9c361e0 2004 {
943d398f
AM		 2005 fill_scale = 0x400 | (2 << 8);
2006 ui8 >>= 16;
b9c361e0 2007 }
943d398f 2008 else if ((ui8 & 0x00ffffff) == 0)
b9c361e0 2009 {
943d398f
AM		 2010 fill_scale = 3 << 8;
2011 ui8 >>= 24;
b9c361e0 2012 }
943d398f 2013 else if ((ui8 & 0x00ffffff) == 0x00ffffff)
b9c361e0 2014 {
943d398f
AM		 2015 fill_scale = 0x400 | (3 << 8);
2016 ui8 >>= 24;
b9c361e0 2017 }
943d398f 2018 else
b9c361e0 2019 {
943d398f
AM		 2020 *errmsg = _("illegal immediate value");
2021 ui8 = 0;
b9c361e0 2022 }
b9c361e0 2023
943d398f 2024 return insn | fill_scale | (ui8 & 0xff);
b9c361e0
JL		 2025}
2026
2027static long
2028extract_sci8 (unsigned long insn,
2029 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2030 int *invalid ATTRIBUTE_UNUSED)
2031{
943d398f
AM		 2032 int fill = insn & 0x400;
2033 int scale_factor = (insn & 0x300) >> 5;
2034 long value = (insn & 0xff) << scale_factor;
2035
2036 if (fill != 0)
2037 value |= ~((long) 0xff << scale_factor);
2038 return value;
b9c361e0
JL		 2039}
2040
2041static unsigned long
2042insert_sci8n (unsigned long insn,
2043 long value,
943d398f 2044 ppc_cpu_t dialect,
b9c361e0
JL		 2045 const char **errmsg)
2046{
943d398f 2047 return insert_sci8 (insn, -value, dialect, errmsg);
b9c361e0
JL		 2048}
2049
2050static long
2051extract_sci8n (unsigned long insn,
943d398f
AM		 2052 ppc_cpu_t dialect,
2053 int *invalid)
b9c361e0 2054{
943d398f 2055 return -extract_sci8 (insn, dialect, invalid);
b9c361e0
JL		 2056}
2057
2058static unsigned long
2059insert_sd4h (unsigned long insn,
2060 long value,
2061 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2062 const char **errmsg ATTRIBUTE_UNUSED)
2063{
2064 return insn | ((value & 0x1e) << 7);
2065}
2066
2067static long
2068extract_sd4h (unsigned long insn,
2069 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2070 int *invalid ATTRIBUTE_UNUSED)
2071{
2072 return ((insn >> 8) & 0xf) << 1;
2073}
2074
2075static unsigned long
2076insert_sd4w (unsigned long insn,
2077 long value,
2078 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2079 const char **errmsg ATTRIBUTE_UNUSED)
2080{
2081 return insn | ((value & 0x3c) << 6);
2082}
2083
2084static long
2085extract_sd4w (unsigned long insn,
2086 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2087 int *invalid ATTRIBUTE_UNUSED)
2088{
2089 return ((insn >> 8) & 0xf) << 2;
2090}
2091
2092static unsigned long
2093insert_oimm (unsigned long insn,
2094 long value,
2095 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2096 const char **errmsg ATTRIBUTE_UNUSED)
2097{
2098 return insn | (((value - 1) & 0x1f) << 4);
2099}
2100
2101static long
2102extract_oimm (unsigned long insn,
2103 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2104 int *invalid ATTRIBUTE_UNUSED)
2105{
2106 return ((insn >> 4) & 0x1f) + 1;
2107}
2108
252b5132
RH		 2109/* The SH field in an MD form instruction. This is split. */
2110
252b5132 2111static unsigned long
2fbfdc41
AM		 2112insert_sh6 (unsigned long insn,
2113 long value,
fa452fa6 2114 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2fbfdc41 2115 const char **errmsg ATTRIBUTE_UNUSED)
252b5132 2116{
6fd3a02d
PB		 2117 /* SH6 operand in the rldixor instructions. */
2118 if (PPC_OP (insn) == 4)
2119 return insn | ((value & 0x1f) << 6) | ((value & 0x20) >> 5);
2120 else
2121 return insn | ((value & 0x1f) << 11) | ((value & 0x20) >> 4);
252b5132
RH		 2122}
2123
252b5132 2124static long
2fbfdc41 2125extract_sh6 (unsigned long insn,
fa452fa6 2126 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2fbfdc41 2127 int *invalid ATTRIBUTE_UNUSED)
252b5132 2128{
6fd3a02d
PB		 2129 /* SH6 operand in the rldixor instructions. */
2130 if (PPC_OP (insn) == 4)
2131 return ((insn >> 6) & 0x1f) | ((insn << 5) & 0x20);
2132 else
2133 return ((insn >> 11) & 0x1f) | ((insn << 4) & 0x20);
252b5132
RH		 2134}
2135
2136/* The SPR field in an XFX form instruction. This is flipped--the
2137 lower 5 bits are stored in the upper 5 and vice- versa. */
2138
2139static unsigned long
2fbfdc41
AM		 2140insert_spr (unsigned long insn,
2141 long value,
fa452fa6 2142 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2fbfdc41 2143 const char **errmsg ATTRIBUTE_UNUSED)
252b5132
RH		 2144{
2145 return insn | ((value & 0x1f) << 16) | ((value & 0x3e0) << 6);
2146}
2147
2148static long
2fbfdc41 2149extract_spr (unsigned long insn,
fa452fa6 2150 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2fbfdc41 2151 int *invalid ATTRIBUTE_UNUSED)
252b5132
RH		 2152{
2153 return ((insn >> 16) & 0x1f) | ((insn >> 6) & 0x3e0);
2154}
2155
da99ee72 2156/* Some dialects have 8 SPRG registers instead of the standard 4. */
14b57c7c 2157#define ALLOW8_SPRG (PPC_OPCODE_BOOKE | PPC_OPCODE_405)
da99ee72
AM		 2158
2159static unsigned long
2160insert_sprg (unsigned long insn,
2161 long value,
fa452fa6 2162 ppc_cpu_t dialect,
da99ee72
AM		 2163 const char **errmsg)
2164{
da99ee72 2165 if (value > 7
98c76446 2166 || (value > 3 && (dialect & ALLOW8_SPRG) == 0))
da99ee72
AM		 2167 *errmsg = _("invalid sprg number");
2168
2169 /* If this is mfsprg4..7 then use spr 260..263 which can be read in
2170 user mode. Anything else must use spr 272..279. */
2171 if (value <= 3 || (insn & 0x100) != 0)
2172 value |= 0x10;
2173
2174 return insn | ((value & 0x17) << 16);
2175}
2176
2177static long
2178extract_sprg (unsigned long insn,
fa452fa6 2179 ppc_cpu_t dialect,
da99ee72
AM		 2180 int *invalid)
2181{
2182 unsigned long val = (insn >> 16) & 0x1f;
2183
2184 /* mfsprg can use 260..263 and 272..279. mtsprg only uses spr 272..279
98c76446
AM		 2185 If not BOOKE, 405 or VLE, then both use only 272..275. */
2186 if ((val - 0x10 > 3 && (dialect & ALLOW8_SPRG) == 0)
e1c93c69
AM		 2187 || (val - 0x10 > 7 && (insn & 0x100) != 0)
2188 || val <= 3
2189 || (val & 8) != 0)
da99ee72
AM		 2190 *invalid = 1;
2191 return val & 7;
2192}
2193
252b5132 2194/* The TBR field in an XFX instruction. This is just like SPR, but it
11a0cf2e 2195 is optional. */
252b5132 2196
252b5132 2197static unsigned long
2fbfdc41
AM		 2198insert_tbr (unsigned long insn,
2199 long value,
fa452fa6 2200 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
8514e4db 2201 const char **errmsg)
252b5132 2202{
8514e4db
AM		 2203 if (value != 268 && value != 269)
2204 *errmsg = _("invalid tbr number");
252b5132
RH		 2205 return insn | ((value & 0x1f) << 16) | ((value & 0x3e0) << 6);
2206}
2207
2208static long
2fbfdc41 2209extract_tbr (unsigned long insn,
fa452fa6 2210 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
8514e4db 2211 int *invalid)
252b5132
RH		 2212{
2213 long ret;
2214
2215 ret = ((insn >> 16) & 0x1f) | ((insn >> 6) & 0x3e0);
8514e4db
AM		 2216 if (ret != 268 && ret != 269)
2217 *invalid = 1;
252b5132
RH		 2218 return ret;
2219}
9b4e5766
PB		 2220
2221/* The XT and XS fields in an XX1 or XX3 form instruction. This is split. */
2222
2223static unsigned long
2224insert_xt6 (unsigned long insn,
2225 long value,
2226 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2227 const char **errmsg ATTRIBUTE_UNUSED)
2228{
2229 return insn | ((value & 0x1f) << 21) | ((value & 0x20) >> 5);
2230}
2231
2232static long
2233extract_xt6 (unsigned long insn,
2234 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2235 int *invalid ATTRIBUTE_UNUSED)
2236{
2237 return ((insn << 5) & 0x20) | ((insn >> 21) & 0x1f);
2238}
2239
a680de9a
PB		 2240/* The XT and XS fields in an DQ form VSX instruction. This is split. */
2241static unsigned long
2242insert_xtq6 (unsigned long insn,
2243 long value,
2244 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2245 const char **errmsg ATTRIBUTE_UNUSED)
2246{
2247 return insn | ((value & 0x1f) << 21) | ((value & 0x20) >> 2);
2248}
2249
2250static long
2251extract_xtq6 (unsigned long insn,
2252 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2253 int *invalid ATTRIBUTE_UNUSED)
2254{
2255 return ((insn << 2) & 0x20) | ((insn >> 21) & 0x1f);
2256}
2257
9b4e5766
PB		 2258/* The XA field in an XX3 form instruction. This is split. */
2259
2260static unsigned long
2261insert_xa6 (unsigned long insn,
2262 long value,
2263 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2264 const char **errmsg ATTRIBUTE_UNUSED)
2265{
2266 return insn | ((value & 0x1f) << 16) | ((value & 0x20) >> 3);
2267}
2268
2269static long
2270extract_xa6 (unsigned long insn,
2271 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2272 int *invalid ATTRIBUTE_UNUSED)
2273{
2274 return ((insn << 3) & 0x20) | ((insn >> 16) & 0x1f);
2275}
2276
2277/* The XB field in an XX3 form instruction. This is split. */
2278
2279static unsigned long
2280insert_xb6 (unsigned long insn,
2281 long value,
2282 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2283 const char **errmsg ATTRIBUTE_UNUSED)
2284{
2285 return insn | ((value & 0x1f) << 11) | ((value & 0x20) >> 4);
2286}
2287
2288static long
2289extract_xb6 (unsigned long insn,
2290 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2291 int *invalid ATTRIBUTE_UNUSED)
2292{
2293 return ((insn << 4) & 0x20) | ((insn >> 11) & 0x1f);
2294}
2295
2296/* The XB field in an XX3 form instruction when it must be the same as
2297 the XA field in the instruction. This is used for extended
2298 mnemonics like xvmovdp. This operand is marked FAKE. The insertion
2299 function just copies the XA field into the XB field, and the
2300 extraction function just checks that the fields are the same. */
2301
2302static unsigned long
2303insert_xb6s (unsigned long insn,
2304 long value ATTRIBUTE_UNUSED,
2305 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2306 const char **errmsg ATTRIBUTE_UNUSED)
2307{
2308 return insn | (((insn >> 16) & 0x1f) << 11) | (((insn >> 2) & 0x1) << 1);
2309}
2310
2311static long
2312extract_xb6s (unsigned long insn,
2313 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2314 int *invalid)
2315{
2316 if ((((insn >> 16) & 0x1f) != ((insn >> 11) & 0x1f))
2317 || (((insn >> 2) & 0x1) != ((insn >> 1) & 0x1)))
2318 *invalid = 1;
2319 return 0;
2320}
066be9f7
PB		 2321
2322/* The XC field in an XX4 form instruction. This is split. */
2323
2324static unsigned long
2325insert_xc6 (unsigned long insn,
2326 long value,
2327 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2328 const char **errmsg ATTRIBUTE_UNUSED)
2329{
2330 return insn | ((value & 0x1f) << 6) | ((value & 0x20) >> 2);
2331}
2332
2333static long
2334extract_xc6 (unsigned long insn,
2335 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2336 int *invalid ATTRIBUTE_UNUSED)
2337{
2338 return ((insn << 2) & 0x20) | ((insn >> 6) & 0x1f);
2339}
2340
2341static unsigned long
2342insert_dm (unsigned long insn,
2343 long value,
2344 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2345 const char **errmsg)
2346{
2347 if (value != 0 && value != 1)
2348 *errmsg = _("invalid constant");
2349 return insn | (((value) ? 3 : 0) << 8);
2350}
2351
2352static long
2353extract_dm (unsigned long insn,
2354 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2355 int *invalid)
2356{
2357 long value;
2358
2359 value = (insn >> 8) & 3;
2360 if (value != 0 && value != 3)
2361 *invalid = 1;
2362 return (value) ? 1 : 0;
2363}
7b934113 2364
b9c361e0
JL		 2365/* The VLESIMM field in an I16A form instruction. This is split. */
2366
2367static unsigned long
2368insert_vlesi (unsigned long insn,
2369 long value,
2370 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2371 const char **errmsg ATTRIBUTE_UNUSED)
2372{
2373 return insn | ((value & 0xf800) << 10) | (value & 0x7ff);
2374}
2375
2376static long
2377extract_vlesi (unsigned long insn,
2378 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2379 int *invalid ATTRIBUTE_UNUSED)
2380{
b9c361e0 2381 long value = ((insn >> 10) & 0xf800) | (insn & 0x7ff);
9f0682fe 2382 value = (value ^ 0x8000) - 0x8000;
b9c361e0
JL		 2383 return value;
2384}
2385
2386static unsigned long
2387insert_vlensi (unsigned long insn,
2388 long value,
2389 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2390 const char **errmsg ATTRIBUTE_UNUSED)
2391{
2392 value = -value;
2393 return insn | ((value & 0xf800) << 10) | (value & 0x7ff);
2394}
2395static long
2396extract_vlensi (unsigned long insn,
2397 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2398 int *invalid ATTRIBUTE_UNUSED)
2399{
2400 long value = ((insn >> 10) & 0xf800) | (insn & 0x7ff);
9f0682fe
AM		 2401 value = (value ^ 0x8000) - 0x8000;
2402 /* Don't use for disassembly. */
b9c361e0
JL		 2403 *invalid = 1;
2404 return -value;
2405}
2406
2407/* The VLEUIMM field in an I16A form instruction. This is split. */
2408
2409static unsigned long
2410insert_vleui (unsigned long insn,
2411 long value,
2412 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2413 const char **errmsg ATTRIBUTE_UNUSED)
2414{
2415 return insn | ((value & 0xf800) << 10) | (value & 0x7ff);
2416}
2417
2418static long
2419extract_vleui (unsigned long insn,
2420 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2421 int *invalid ATTRIBUTE_UNUSED)
2422{
2423 return ((insn >> 10) & 0xf800) | (insn & 0x7ff);
2424}
2425
2426/* The VLEUIMML field in an I16L form instruction. This is split. */
2427
2428static unsigned long
2429insert_vleil (unsigned long insn,
2430 long value,
2431 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2432 const char **errmsg ATTRIBUTE_UNUSED)
2433{
2434 return insn | ((value & 0xf800) << 5) | (value & 0x7ff);
2435}
2436
2437static long
2438extract_vleil (unsigned long insn,
2439 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2440 int *invalid ATTRIBUTE_UNUSED)
2441{
2442 return ((insn >> 5) & 0xf800) | (insn & 0x7ff);
2443}
2444
e3c2f928
AF		 2445static unsigned long
2446insert_evuimm2_ex0 (unsigned long insn,
2447 long value,
2448 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2449 const char **errmsg)
2450{
2451 if (value > 0 && value <= 0x3e)
2452 return insn | ((value & 0x3e) << 10);
2453 else
2454 {
2455 *errmsg = _("UIMM = 00000 is illegal");
2456 return 0;
2457 }
2458}
2459
2460static long
2461extract_evuimm2_ex0 (unsigned long insn,
2462 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2463 int *invalid)
2464{
2465 long value = ((insn >> 10) & 0x3e);
2466 if (value == 0)
2467 *invalid = 1;
2468
2469 return value;
2470}
2471
2472static unsigned long
2473insert_evuimm4_ex0 (unsigned long insn,
2474 long value,
2475 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2476 const char **errmsg)
2477{
2478 if (value > 0 && value <= 0x7c)
2479 return insn | ((value & 0x7c) << 9);
2480 else
2481 {
2482 *errmsg = _("UIMM = 00000 is illegal");
2483 return 0;
2484 }
2485}
2486
2487static long
2488extract_evuimm4_ex0 (unsigned long insn,
2489 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2490 int *invalid)
2491{
2492 long value = ((insn >> 9) & 0x7c);
2493 if (value == 0)
2494 *invalid = 1;
2495
2496 return value;
2497}
2498
2499static unsigned long
2500insert_evuimm8_ex0 (unsigned long insn,
2501 long value,
2502 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2503 const char **errmsg)
2504{
2505 if (value > 0 && value <= 0xf8)
2506 return insn | ((value & 0xf8) << 8);
2507 else
2508 {
2509 *errmsg = _("UIMM = 00000 is illegal");
2510 return 0;
2511 }
2512}
2513
2514static long
2515extract_evuimm8_ex0 (unsigned long insn,
2516 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2517 int *invalid)
2518{
2519 long value = ((insn >> 8) & 0xf8);
2520 if (value == 0)
2521 *invalid = 1;
2522
2523 return value;
2524}
2525
2526static unsigned long
2527insert_evuimm_lt16 (unsigned long insn,
2528 long value,
2529 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2530 const char **errmsg)
2531{
2532 if (value >= 0 && value <= 15)
2533 return insn | ((value & 0xf) << 11);
2534 else
2535 {
2536 *errmsg = _("UIMM values >15 are illegal");
2537 return 0;
2538 }
2539}
2540
2541static long
2542extract_evuimm_lt16 (unsigned long insn,
2543 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2544 int *invalid)
2545{
2546 long value = ((insn >> 11) & 0x1f);
2547 if (value > 15)
2548 *invalid = 1;
2549
2550 return value;
2551}
2552
2553static unsigned long
2554insert_rD_rS_even (unsigned long insn,
2555 long value,
2556 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2557 const char **errmsg)
2558{
2559 if ((value & 0x1) == 0)
2560 return insn | ((value & 0x1e) << 21);
2561 else
2562 {
2563 *errmsg = _("GPR odd is illegal");
2564 return 0;
2565 }
2566}
2567
2568static long
2569extract_rD_rS_even (unsigned long insn,
2570 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2571 int *invalid)
2572{
2573 long value = ((insn >> 21) & 0x1f);
2574 if ((value & 0x1) != 0)
2575 *invalid = 1;
2576
2577 return value;
2578}
2579
2580static unsigned long
2581insert_off_lsp (unsigned long insn,
2582 long value,
2583 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2584 const char **errmsg)
2585{
2586 if (value > 0 && value <= 0x3)
2587 return insn | (value & 0x3);
2588 else
2589 {
2590 *errmsg = _("invalid offset");
2591 return 0;
2592 }
2593}
2594
2595static long
2596extract_off_lsp (unsigned long insn,
2597 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2598 int *invalid)
2599{
2600 long value = (insn & 0x3);
2601 if (value == 0)
2602 *invalid = 1;
2603
2604 return value;
2605}
252b5132
RH		 2606\f
2607/* Macros used to form opcodes. */
2608
2609/* The main opcode. */
2610#define OP(x) ((((unsigned long)(x)) & 0x3f) << 26)
2611#define OP_MASK OP (0x3f)
2612
2613/* The main opcode combined with a trap code in the TO field of a D
2614 form instruction. Used for extended mnemonics for the trap
2615 instructions. */
2616#define OPTO(x,to) (OP (x) | ((((unsigned long)(to)) & 0x1f) << 21))
2617#define OPTO_MASK (OP_MASK | TO_MASK)
2618
2619/* The main opcode combined with a comparison size bit in the L field
2620 of a D form or X form instruction. Used for extended mnemonics for
2621 the comparison instructions. */
2622#define OPL(x,l) (OP (x) | ((((unsigned long)(l)) & 1) << 21))
2623#define OPL_MASK OPL (0x3f,1)
2624
b9c361e0
JL		 2625/* The main opcode combined with an update code in D form instruction.
2626 Used for extended mnemonics for VLE memory instructions. */
2627#define OPVUP(x,vup) (OP (x) | ((((unsigned long)(vup)) & 0xff) << 8))
2628#define OPVUP_MASK OPVUP (0x3f, 0xff)
2629
dfdaec14
AJ		 2630/* The main opcode combined with an update code and the RT fields specified in
2631 D form instruction. Used for VLE volatile context save/restore
2632 instructions. */
2633#define OPVUPRT(x,vup,rt) (OPVUP (x, vup) | ((((unsigned long)(rt)) & 0x1f) << 21))
2634#define OPVUPRT_MASK OPVUPRT (0x3f, 0xff, 0x1f)
2635
252b5132
RH		 2636/* An A form instruction. */
2637#define A(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x1f) << 1) | (((unsigned long)(rc)) & 1))
2638#define A_MASK A (0x3f, 0x1f, 1)
2639
2640/* An A_MASK with the FRB field fixed. */
2641#define AFRB_MASK (A_MASK | FRB_MASK)
2642
2643/* An A_MASK with the FRC field fixed. */
2644#define AFRC_MASK (A_MASK | FRC_MASK)
2645
2646/* An A_MASK with the FRA and FRC fields fixed. */
2647#define AFRAFRC_MASK (A_MASK | FRA_MASK | FRC_MASK)
2648
702f0fb4
PB		 2649/* An AFRAFRC_MASK, but with L bit clear. */
2650#define AFRALFRC_MASK (AFRAFRC_MASK & ~((unsigned long) 1 << 16))
2651
252b5132
RH		 2652/* A B form instruction. */
2653#define B(op, aa, lk) (OP (op) | ((((unsigned long)(aa)) & 1) << 1) | ((lk) & 1))
2654#define B_MASK B (0x3f, 1, 1)
2655
b9c361e0
JL		 2656/* A BD8 form instruction. This is a 16-bit instruction. */
2657#define BD8(op, aa, lk) (((((unsigned long)(op)) & 0x3f) << 10) | (((aa) & 1) << 9) | (((lk) & 1) << 8))
2658#define BD8_MASK BD8 (0x3f, 1, 1)
2659
2660/* Another BD8 form instruction. This is a 16-bit instruction. */
2661#define BD8IO(op) ((((unsigned long)(op)) & 0x1f) << 11)
2662#define BD8IO_MASK BD8IO (0x1f)
2663
2664/* A BD8 form instruction for simplified mnemonics. */
2665#define EBD8IO(op, bo, bi) (BD8IO ((op)) | ((bo) << 10) | ((bi) << 8))
2666/* A mask that excludes BO32 and BI32. */
2667#define EBD8IO1_MASK 0xf800
2668/* A mask that includes BO32 and excludes BI32. */
2669#define EBD8IO2_MASK 0xfc00
2670/* A mask that include BO32 AND BI32. */
2671#define EBD8IO3_MASK 0xff00
2672
2673/* A BD15 form instruction. */
2674#define BD15(op, aa, lk) (OP (op) | ((((unsigned long)(aa)) & 0xf) << 22) | ((lk) & 1))
2675#define BD15_MASK BD15 (0x3f, 0xf, 1)
2676
2677/* A BD15 form instruction for extended conditional branch mnemonics. */
2678#define EBD15(op, aa, bo, lk) (((op) & 0x3f) << 26) | (((aa) & 0xf) << 22) | (((bo) & 0x3) << 20) | ((lk) & 1)
2679#define EBD15_MASK 0xfff00001
2680
2681/* A BD15 form instruction for extended conditional branch mnemonics with BI. */
2682#define EBD15BI(op, aa, bo, bi, lk) (((op) & 0x3f) << 26) \
2683 | (((aa) & 0xf) << 22) \
2684 | (((bo) & 0x3) << 20) \
2685 | (((bi) & 0x3) << 16) \
2686 | ((lk) & 1)
2687#define EBD15BI_MASK 0xfff30001
2688
2689/* A BD24 form instruction. */
2690#define BD24(op, aa, lk) (OP (op) | ((((unsigned long)(aa)) & 1) << 25) | ((lk) & 1))
2691#define BD24_MASK BD24 (0x3f, 1, 1)
2692
252b5132
RH		 2693/* A B form instruction setting the BO field. */
2694#define BBO(op, bo, aa, lk) (B ((op), (aa), (lk)) | ((((unsigned long)(bo)) & 0x1f) << 21))
2695#define BBO_MASK BBO (0x3f, 0x1f, 1, 1)
2696
2697/* A BBO_MASK with the y bit of the BO field removed. This permits
2698 matching a conditional branch regardless of the setting of the y
94efba12 2699 bit. Similarly for the 'at' bits used for power4 branch hints. */
de866fcc 2700#define Y_MASK (((unsigned long) 1) << 21)
802a735e
AM		 2701#define AT1_MASK (((unsigned long) 3) << 21)
2702#define AT2_MASK (((unsigned long) 9) << 21)
2703#define BBOY_MASK (BBO_MASK &~ Y_MASK)
2704#define BBOAT_MASK (BBO_MASK &~ AT1_MASK)
252b5132
RH		 2705
2706/* A B form instruction setting the BO field and the condition bits of
2707 the BI field. */
2708#define BBOCB(op, bo, cb, aa, lk) \
2709 (BBO ((op), (bo), (aa), (lk)) | ((((unsigned long)(cb)) & 0x3) << 16))
2710#define BBOCB_MASK BBOCB (0x3f, 0x1f, 0x3, 1, 1)
2711
2712/* A BBOCB_MASK with the y bit of the BO field removed. */
2713#define BBOYCB_MASK (BBOCB_MASK &~ Y_MASK)
802a735e
AM		 2714#define BBOATCB_MASK (BBOCB_MASK &~ AT1_MASK)
2715#define BBOAT2CB_MASK (BBOCB_MASK &~ AT2_MASK)
252b5132
RH		 2716
2717/* A BBOYCB_MASK in which the BI field is fixed. */
2718#define BBOYBI_MASK (BBOYCB_MASK | BI_MASK)
802a735e 2719#define BBOATBI_MASK (BBOAT2CB_MASK | BI_MASK)
252b5132 2720
b9c361e0
JL		 2721/* A VLE C form instruction. */
2722#define C_LK(x, lk) (((((unsigned long)(x)) & 0x7fff) << 1) | ((lk) & 1))
2723#define C_LK_MASK C_LK(0x7fff, 1)
2724#define C(x) ((((unsigned long)(x)) & 0xffff))
2725#define C_MASK C(0xffff)
2726
23976049
EZ		 2727/* An Context form instruction. */
2728#define CTX(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x7))
fdd12ef3 2729#define CTX_MASK CTX(0x3f, 0x7)
23976049
EZ		 2730
2731/* An User Context form instruction. */
2732#define UCTX(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x1f))
fdd12ef3 2733#define UCTX_MASK UCTX(0x3f, 0x1f)
23976049 2734
252b5132
RH		 2735/* The main opcode mask with the RA field clear. */
2736#define DRA_MASK (OP_MASK | RA_MASK)
2737
a680de9a
PB		 2738/* A DQ form VSX instruction. */
2739#define DQX(op, xop) (OP (op) | ((xop) & 0x7))
2740#define DQX_MASK DQX (0x3f, 7)
2741
252b5132
RH		 2742/* A DS form instruction. */
2743#define DSO(op, xop) (OP (op) | ((xop) & 0x3))
2744#define DS_MASK DSO (0x3f, 3)
2745
a680de9a
PB		 2746/* An DX form instruction. */
2747#define DX(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x1f) << 1))
2748#define DX_MASK DX (0x3f, 0x1f)
1437d063
PB		 2749/* An DX form instruction with the D bits specified. */
2750#define NODX_MASK (DX_MASK | 0x1fffc1)
a680de9a 2751
23976049
EZ		 2752/* An EVSEL form instruction. */
2753#define EVSEL(op, xop) (OP (op) | (((unsigned long)(xop)) & 0xff) << 3)
2754#define EVSEL_MASK EVSEL(0x3f, 0xff)
2755
b9c361e0
JL		 2756/* An IA16 form instruction. */
2757#define IA16(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x1f) << 11)
2758#define IA16_MASK IA16(0x3f, 0x1f)
2759
2760/* An I16A form instruction. */
2761#define I16A(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x1f) << 11)
2762#define I16A_MASK I16A(0x3f, 0x1f)
2763
2764/* An I16L form instruction. */
2765#define I16L(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x1f) << 11)
2766#define I16L_MASK I16L(0x3f, 0x1f)
2767
2768/* An IM7 form instruction. */
2769#define IM7(op) ((((unsigned long)(op)) & 0x1f) << 11)
2770#define IM7_MASK IM7(0x1f)
2771
252b5132
RH		 2772/* An M form instruction. */
2773#define M(op, rc) (OP (op) | ((rc) & 1))
2774#define M_MASK M (0x3f, 1)
2775
b9c361e0
JL		 2776/* An LI20 form instruction. */
2777#define LI20(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x1) << 15)
2778#define LI20_MASK LI20(0x3f, 0x1)
2779
252b5132
RH		 2780/* An M form instruction with the ME field specified. */
2781#define MME(op, me, rc) (M ((op), (rc)) | ((((unsigned long)(me)) & 0x1f) << 1))
2782
2783/* An M_MASK with the MB and ME fields fixed. */
2784#define MMBME_MASK (M_MASK | MB_MASK | ME_MASK)
2785
2786/* An M_MASK with the SH and ME fields fixed. */
2787#define MSHME_MASK (M_MASK | SH_MASK | ME_MASK)
2788
2789/* An MD form instruction. */
2790#define MD(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x7) << 2) | ((rc) & 1))
2791#define MD_MASK MD (0x3f, 0x7, 1)
2792
2793/* An MD_MASK with the MB field fixed. */
2794#define MDMB_MASK (MD_MASK | MB6_MASK)
2795
2796/* An MD_MASK with the SH field fixed. */
2797#define MDSH_MASK (MD_MASK | SH6_MASK)
2798
2799/* An MDS form instruction. */
2800#define MDS(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0xf) << 1) | ((rc) & 1))
2801#define MDS_MASK MDS (0x3f, 0xf, 1)
2802
2803/* An MDS_MASK with the MB field fixed. */
2804#define MDSMB_MASK (MDS_MASK | MB6_MASK)
2805
2806/* An SC form instruction. */
2807#define SC(op, sa, lk) (OP (op) | ((((unsigned long)(sa)) & 1) << 1) | ((lk) & 1))
2808#define SC_MASK (OP_MASK | (((unsigned long)0x3ff) << 16) | (((unsigned long)1) << 1) | 1)
2809
b9c361e0
JL		 2810/* An SCI8 form instruction. */
2811#define SCI8(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x1f) << 11))
2812#define SCI8_MASK SCI8(0x3f, 0x1f)
2813
2814/* An SCI8 form instruction. */
2815#define SCI8BF(op, fop, xop) (OP (op) | ((((unsigned long)(xop)) & 0x1f) << 11) | (((fop) & 7) << 23))
2816#define SCI8BF_MASK SCI8BF(0x3f, 7, 0x1f)
2817
2818/* An SD4 form instruction. This is a 16-bit instruction. */
43e65147 2819#define SD4(op) ((((unsigned long)(op)) & 0xf) << 12)
b9c361e0
JL		 2820#define SD4_MASK SD4(0xf)
2821
2822/* An SE_IM5 form instruction. This is a 16-bit instruction. */
2823#define SE_IM5(op, xop) (((((unsigned long)(op)) & 0x3f) << 10) | (((xop) & 0x1) << 9))
2824#define SE_IM5_MASK SE_IM5(0x3f, 1)
2825
2826/* An SE_R form instruction. This is a 16-bit instruction. */
2827#define SE_R(op, xop) (((((unsigned long)(op)) & 0x3f) << 10) | (((xop) & 0x3f) << 4))
2828#define SE_R_MASK SE_R(0x3f, 0x3f)
2829
2830/* An SE_RR form instruction. This is a 16-bit instruction. */
2831#define SE_RR(op, xop) (((((unsigned long)(op)) & 0x3f) << 10) | (((xop) & 0x3) << 8))
2832#define SE_RR_MASK SE_RR(0x3f, 3)
2833
2834/* A VX form instruction. */
786e2c0f
C		 2835#define VX(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x7ff))
2836
112290ab 2837/* The mask for an VX form instruction. */
786e2c0f
C		 2838#define VX_MASK VX(0x3f, 0x7ff)
2839
e3c2f928
AF		 2840/* A VX LSP form instruction. */
2841#define VX_LSP(op, xop) (OP (op) | (((unsigned long)(xop)) & 0xffff))
2842
2843/* The mask for an VX LSP form instruction. */
2844#define VX_LSP_MASK VX_LSP(0x3f, 0xffff)
2845#define VX_LSP_OFF_MASK VX_LSP(0x3f, 0x7fc)
2846
fb048c26
PB		 2847/* A VX_MASK with the VA field fixed. */
2848#define VXVA_MASK (VX_MASK | (0x1f << 16))
2849
2850/* A VX_MASK with the VB field fixed. */
2851#define VXVB_MASK (VX_MASK | (0x1f << 11))
2852
2853/* A VX_MASK with the VA and VB fields fixed. */
2854#define VXVAVB_MASK (VX_MASK | (0x1f << 16) | (0x1f << 11))
2855
2856/* A VX_MASK with the VD and VA fields fixed. */
2857#define VXVDVA_MASK (VX_MASK | (0x1f << 21) | (0x1f << 16))
2858
2859/* A VX_MASK with a UIMM4 field. */
2860#define VXUIMM4_MASK (VX_MASK | (0x1 << 20))
2861
2862/* A VX_MASK with a UIMM3 field. */
2863#define VXUIMM3_MASK (VX_MASK | (0x3 << 19))
2864
2865/* A VX_MASK with a UIMM2 field. */
2866#define VXUIMM2_MASK (VX_MASK | (0x7 << 18))
2867
c0637f3a
PB		 2868/* A VX_MASK with a PS field. */
2869#define VXPS_MASK (VX_MASK & ~(0x1 << 9))
2870
a680de9a
PB		 2871/* A VX_MASK with the VA field fixed with a PS field. */
2872#define VXVAPS_MASK ((VX_MASK | (0x1f << 16)) & ~(0x1 << 9))
2873
b9c361e0 2874/* A VA form instruction. */
2613489e 2875#define VXA(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x03f))
786e2c0f 2876
112290ab 2877/* The mask for an VA form instruction. */
2613489e 2878#define VXA_MASK VXA(0x3f, 0x3f)
786e2c0f 2879
382c72e9
PB		 2880/* A VXA_MASK with a SHB field. */
2881#define VXASHB_MASK (VXA_MASK | (1 << 10))
2882
b9c361e0 2883/* A VXR form instruction. */
786e2c0f
C		 2884#define VXR(op, xop, rc) (OP (op) | (((rc) & 1) << 10) | (((unsigned long)(xop)) & 0x3ff))
2885
112290ab 2886/* The mask for a VXR form instruction. */
786e2c0f
C		 2887#define VXR_MASK VXR(0x3f, 0x3ff, 1)
2888
a680de9a
PB		 2889/* A VX form instruction with a VA tertiary opcode. */
2890#define VXVA(op, xop, vaop) (VX(op,xop) | (((vaop) & 0x1f) << 16))
2891
6fd3a02d
PB		 2892#define VXASH(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x1f) << 1))
2893#define VXASH_MASK VXASH (0x3f, 0x1f)
2894
252b5132
RH		 2895/* An X form instruction. */
2896#define X(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1))
2897
a680de9a
PB		 2898/* A X form instruction for Quad-Precision FP Instructions. */
2899#define XVA(op, xop, vaop) (X(op,xop) | (((vaop) & 0x1f) << 16))
2900
b9c361e0
JL		 2901/* An EX form instruction. */
2902#define EX(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x7ff))
2903
2904/* The mask for an EX form instruction. */
2905#define EX_MASK EX (0x3f, 0x7ff)
2906
066be9f7
PB		 2907/* An XX2 form instruction. */
2908#define XX2(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x1ff) << 2))
2909
a680de9a
PB		 2910/* A XX2 form instruction with the VA bits specified. */
2911#define XX2VA(op, xop, vaop) (XX2(op,xop) | (((vaop) & 0x1f) << 16))
2912
9b4e5766
PB		 2913/* An XX3 form instruction. */
2914#define XX3(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0xff) << 3))
2915
066be9f7
PB		 2916/* An XX3 form instruction with the RC bit specified. */
2917#define XX3RC(op, xop, rc) (OP (op) | (((rc) & 1) << 10) | ((((unsigned long)(xop)) & 0x7f) << 3))
2918
2919/* An XX4 form instruction. */
2920#define XX4(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x3) << 4))
9b4e5766 2921
702f0fb4
PB		 2922/* A Z form instruction. */
2923#define Z(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x1ff) << 1))
2924
252b5132
RH		 2925/* An X form instruction with the RC bit specified. */
2926#define XRC(op, xop, rc) (X ((op), (xop)) | ((rc) & 1))
2927
a680de9a
PB		 2928/* A X form instruction for Quad-Precision FP Instructions with RC bit. */
2929#define XVARC(op, xop, vaop, rc) (XVA ((op), (xop), (vaop)) | ((rc) & 1))
2930
6fd3a02d
PB		 2931/* An X form instruction with the RA bits specified as two ops. */
2932#define XMMF(op, xop, mop0, mop1) (X ((op), (xop)) | ((mop0) & 3) << 19 | ((mop1) & 7) << 16)
2933
702f0fb4
PB		 2934/* A Z form instruction with the RC bit specified. */
2935#define ZRC(op, xop, rc) (Z ((op), (xop)) | ((rc) & 1))
2936
252b5132
RH		 2937/* The mask for an X form instruction. */
2938#define X_MASK XRC (0x3f, 0x3ff, 1)
2939
a680de9a
PB		 2940/* The mask for an X form instruction with the BF bits specified. */
2941#define XBF_MASK (X_MASK | (3 << 21))
2942
e0d602ec
BE		 2943/* An X form wait instruction with everything filled in except the WC field. */
2944#define XWC_MASK (XRC (0x3f, 0x3ff, 1) | (7 << 23) | RA_MASK | RB_MASK)
2945
9b4e5766
PB		 2946/* The mask for an XX1 form instruction. */
2947#define XX1_MASK X (0x3f, 0x3ff)
2948
c0637f3a
PB		 2949/* An XX1_MASK with the RB field fixed. */
2950#define XX1RB_MASK (XX1_MASK | RB_MASK)
2951
066be9f7
PB		 2952/* The mask for an XX2 form instruction. */
2953#define XX2_MASK (XX2 (0x3f, 0x1ff) | (0x1f << 16))
2954
2955/* The mask for an XX2 form instruction with the UIM bits specified. */
2956#define XX2UIM_MASK (XX2 (0x3f, 0x1ff) | (7 << 18))
2957
a680de9a
PB		 2958/* The mask for an XX2 form instruction with the 4 UIM bits specified. */
2959#define XX2UIM4_MASK (XX2 (0x3f, 0x1ff) | (1 << 20))
2960
066be9f7
PB		 2961/* The mask for an XX2 form instruction with the BF bits specified. */
2962#define XX2BF_MASK (XX2_MASK | (3 << 21) | (1))
2963
a680de9a
PB		 2964/* The mask for an XX2 form instruction with the BF and DCMX bits specified. */
2965#define XX2BFD_MASK (XX2 (0x3f, 0x1ff) | 1)
2966
2967/* The mask for an XX2 form instruction with a split DCMX bits specified. */
2968#define XX2DCMXS_MASK XX2 (0x3f, 0x1ee)
2969
9b4e5766
PB		 2970/* The mask for an XX3 form instruction. */
2971#define XX3_MASK XX3 (0x3f, 0xff)
2972
066be9f7
PB		 2973/* The mask for an XX3 form instruction with the BF bits specified. */
2974#define XX3BF_MASK (XX3 (0x3f, 0xff) | (3 << 21) | (1))
2975
2976/* The mask for an XX3 form instruction with the DM or SHW bits specified. */
9b4e5766 2977#define XX3DM_MASK (XX3 (0x3f, 0x1f) | (1 << 10))
066be9f7
PB		 2978#define XX3SHW_MASK XX3DM_MASK
2979
2980/* The mask for an XX4 form instruction. */
2981#define XX4_MASK XX4 (0x3f, 0x3)
2982
2983/* An X form wait instruction with everything filled in except the WC field. */
2984#define XWC_MASK (XRC (0x3f, 0x3ff, 1) | (7 << 23) | RA_MASK | RB_MASK)
9b4e5766 2985
6fd3a02d
PB		 2986/* The mask for an XMMF form instruction. */
2987#define XMMF_MASK (XMMF (0x3f, 0x3ff, 3, 7) | (1))
2988
702f0fb4
PB		 2989/* The mask for a Z form instruction. */
2990#define Z_MASK ZRC (0x3f, 0x1ff, 1)
0bbdef92 2991#define Z2_MASK ZRC (0x3f, 0xff, 1)
702f0fb4 2992
a680de9a 2993/* An X_MASK with the RA/VA field fixed. */
252b5132 2994#define XRA_MASK (X_MASK | RA_MASK)
a680de9a 2995#define XVA_MASK XRA_MASK
252b5132 2996
a680de9a 2997/* An XRA_MASK with the A_L/W field clear. */
ea192fa3 2998#define XWRA_MASK (XRA_MASK & ~((unsigned long) 1 << 16))
a680de9a 2999#define XRLA_MASK XWRA_MASK
ea192fa3 3000
252b5132
RH		 3001/* An X_MASK with the RB field fixed. */
3002#define XRB_MASK (X_MASK | RB_MASK)
3003
3004/* An X_MASK with the RT field fixed. */
3005#define XRT_MASK (X_MASK | RT_MASK)
3006
702f0fb4
PB		 3007/* An XRT_MASK mask with the L bits clear. */
3008#define XLRT_MASK (XRT_MASK & ~((unsigned long) 0x3 << 21))
3009
252b5132
RH		 3010/* An X_MASK with the RA and RB fields fixed. */
3011#define XRARB_MASK (X_MASK | RA_MASK | RB_MASK)
3012
a680de9a
PB		 3013/* An XBF_MASK with the RA and RB fields fixed. */
3014#define XBFRARB_MASK (XBF_MASK | RA_MASK | RB_MASK)
3015
112290ab 3016/* An XRARB_MASK, but with the L bit clear. */
5ae2e65e
AM		 3017#define XRLARB_MASK (XRARB_MASK & ~((unsigned long) 1 << 16))
3018
a680de9a
PB		 3019/* An XRARB_MASK, but with the L bits in a darn instruction clear. */
3020#define XLRAND_MASK (XRARB_MASK & ~((unsigned long) 3 << 16))
3021
252b5132
RH		 3022/* An X_MASK with the RT and RA fields fixed. */
3023#define XRTRA_MASK (X_MASK | RT_MASK | RA_MASK)
3024
5817ffd1
PB		 3025/* An X_MASK with the RT and RB fields fixed. */
3026#define XRTRB_MASK (X_MASK | RT_MASK | RB_MASK)
3027
98acc1c5
AM		 3028/* An XRTRA_MASK, but with L bit clear. */
3029#define XRTLRA_MASK (XRTRA_MASK & ~((unsigned long) 1 << 21))
3030
5817ffd1
PB		 3031/* An X_MASK with the RT, RA and RB fields fixed. */
3032#define XRTRARB_MASK (X_MASK | RT_MASK | RA_MASK | RB_MASK)
3033
3034/* An XRTRARB_MASK, but with L bit clear. */
3035#define XRTLRARB_MASK (XRTRARB_MASK & ~((unsigned long) 1 << 21))
3036
3037/* An XRTRARB_MASK, but with A bit clear. */
3038#define XRTARARB_MASK (XRTRARB_MASK & ~((unsigned long) 1 << 25))
3039
3040/* An XRTRARB_MASK, but with BF bits clear. */
3041#define XRTBFRARB_MASK (XRTRARB_MASK & ~((unsigned long) 7 << 23))
3042
f3806e43
BE		 3043/* An X form instruction with the L bit specified. */
3044#define XOPL(op, xop, l) (X ((op), (xop)) | ((((unsigned long)(l)) & 1) << 21))
252b5132 3045
e0d602ec
BE		 3046/* An X form instruction with the L bits specified. */
3047#define XOPL2(op, xop, l) (X ((op), (xop)) | ((((unsigned long)(l)) & 3) << 21))
3048
5817ffd1
PB		 3049/* An X form instruction with the L bit and RC bit specified. */
3050#define XRCL(op, xop, l, rc) (XRC ((op), (xop), (rc)) | ((((unsigned long)(l)) & 1) << 21))
3051
19a6653c
AM		 3052/* An X form instruction with RT fields specified */
3053#define XRT(op, xop, rt) (X ((op), (xop)) \
3054 | ((((unsigned long)(rt)) & 0x1f) << 21))
3055
3056/* An X form instruction with RT and RA fields specified */
3057#define XRTRA(op, xop, rt, ra) (X ((op), (xop)) \
3058 | ((((unsigned long)(rt)) & 0x1f) << 21) \
3059 | ((((unsigned long)(ra)) & 0x1f) << 16))
3060
252b5132
RH		 3061/* The mask for an X form comparison instruction. */
3062#define XCMP_MASK (X_MASK | (((unsigned long)1) << 22))
3063
520ceea4
BE		 3064/* The mask for an X form comparison instruction with the L field
3065 fixed. */
3066#define XCMPL_MASK (XCMP_MASK | (((unsigned long)1) << 21))
252b5132
RH		 3067
3068/* An X form trap instruction with the TO field specified. */
3069#define XTO(op, xop, to) (X ((op), (xop)) | ((((unsigned long)(to)) & 0x1f) << 21))
3070#define XTO_MASK (X_MASK | TO_MASK)
3071
e0c21649
GK		 3072/* An X form tlb instruction with the SH field specified. */
3073#define XTLB(op, xop, sh) (X ((op), (xop)) | ((((unsigned long)(sh)) & 0x1f) << 11))
3074#define XTLB_MASK (X_MASK | SH_MASK)
3075
6ba045b1
AM		 3076/* An X form sync instruction. */
3077#define XSYNC(op, xop, l) (X ((op), (xop)) | ((((unsigned long)(l)) & 3) << 21))
3078
3079/* An X form sync instruction with everything filled in except the LS field. */
3080#define XSYNC_MASK (0xff9fffff)
3081
aea77599
AM		 3082/* An X form sync instruction with everything filled in except the L and E fields. */
3083#define XSYNCLE_MASK (0xff90ffff)
3084
702f0fb4
PB		 3085/* An X_MASK, but with the EH bit clear. */
3086#define XEH_MASK (X_MASK & ~((unsigned long )1))
3087
f5c120c5
MG		 3088/* An X form AltiVec dss instruction. */
3089#define XDSS(op, xop, a) (X ((op), (xop)) | ((((unsigned long)(a)) & 1) << 25))
3090#define XDSS_MASK XDSS(0x3f, 0x3ff, 1)
3091
252b5132
RH		 3092/* An XFL form instruction. */
3093#define XFL(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1) | (((unsigned long)(rc)) & 1))
ea192fa3 3094#define XFL_MASK XFL (0x3f, 0x3ff, 1)
252b5132 3095
23976049 3096/* An X form isel instruction. */
de866fcc
AM		 3097#define XISEL(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x1f) << 1))
3098#define XISEL_MASK XISEL(0x3f, 0x1f)
23976049 3099
252b5132
RH		 3100/* An XL form instruction with the LK field set to 0. */
3101#define XL(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1))
3102
3103/* An XL form instruction which uses the LK field. */
3104#define XLLK(op, xop, lk) (XL ((op), (xop)) | ((lk) & 1))
3105
3106/* The mask for an XL form instruction. */
3107#define XL_MASK XLLK (0x3f, 0x3ff, 1)
3108
c0637f3a
PB		 3109/* An XL_MASK with the RT, RA and RB fields fixed, but S bit clear. */
3110#define XLS_MASK ((XL_MASK | RT_MASK | RA_MASK | RB_MASK) & ~(1 << 11))
3111
252b5132
RH		 3112/* An XL form instruction which explicitly sets the BO field. */
3113#define XLO(op, bo, xop, lk) \
3114 (XLLK ((op), (xop), (lk)) | ((((unsigned long)(bo)) & 0x1f) << 21))
3115#define XLO_MASK (XL_MASK | BO_MASK)
3116
3117/* An XL form instruction which explicitly sets the y bit of the BO
3118 field. */
3119#define XLYLK(op, xop, y, lk) (XLLK ((op), (xop), (lk)) | ((((unsigned long)(y)) & 1) << 21))
3120#define XLYLK_MASK (XL_MASK | Y_MASK)
3121
3122/* An XL form instruction which sets the BO field and the condition
3123 bits of the BI field. */
3124#define XLOCB(op, bo, cb, xop, lk) \
3125 (XLO ((op), (bo), (xop), (lk)) | ((((unsigned long)(cb)) & 3) << 16))
3126#define XLOCB_MASK XLOCB (0x3f, 0x1f, 0x3, 0x3ff, 1)
3127
3128/* An XL_MASK or XLYLK_MASK or XLOCB_MASK with the BB field fixed. */
3129#define XLBB_MASK (XL_MASK | BB_MASK)
3130#define XLYBB_MASK (XLYLK_MASK | BB_MASK)
3131#define XLBOCBBB_MASK (XLOCB_MASK | BB_MASK)
3132
d0618d1c
AM		 3133/* A mask for branch instructions using the BH field. */
3134#define XLBH_MASK (XL_MASK | (0x1c << 11))
3135
252b5132
RH		 3136/* An XL_MASK with the BO and BB fields fixed. */
3137#define XLBOBB_MASK (XL_MASK | BO_MASK | BB_MASK)
3138
3139/* An XL_MASK with the BO, BI and BB fields fixed. */
3140#define XLBOBIBB_MASK (XL_MASK | BO_MASK | BI_MASK | BB_MASK)
3141
e01d869a
AM		 3142/* An X form mbar instruction with MO field. */
3143#define XMBAR(op, xop, mo) (X ((op), (xop)) | ((((unsigned long)(mo)) & 1) << 21))
3144
252b5132
RH		 3145/* An XO form instruction. */
3146#define XO(op, xop, oe, rc) \
3147 (OP (op) | ((((unsigned long)(xop)) & 0x1ff) << 1) | ((((unsigned long)(oe)) & 1) << 10) | (((unsigned long)(rc)) & 1))
3148#define XO_MASK XO (0x3f, 0x1ff, 1, 1)
3149
3150/* An XO_MASK with the RB field fixed. */
3151#define XORB_MASK (XO_MASK | RB_MASK)
3152
c3d65c1c
BE		 3153/* An XOPS form instruction for paired singles. */
3154#define XOPS(op, xop, rc) \
3155 (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1) | (((unsigned long)(rc)) & 1))
3156#define XOPS_MASK XOPS (0x3f, 0x3ff, 1)
3157
3158
252b5132
RH		 3159/* An XS form instruction. */
3160#define XS(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x1ff) << 2) | (((unsigned long)(rc)) & 1))
3161#define XS_MASK XS (0x3f, 0x1ff, 1)
3162
3163/* A mask for the FXM version of an XFX form instruction. */
98e69875 3164#define XFXFXM_MASK (X_MASK | (1 << 11) | (1 << 20))
252b5132
RH		 3165
3166/* An XFX form instruction with the FXM field filled in. */
98e69875
AM		 3167#define XFXM(op, xop, fxm, p4) \
3168 (X ((op), (xop)) | ((((unsigned long)(fxm)) & 0xff) << 12) \
3169 | ((unsigned long)(p4) << 20))
252b5132
RH		 3170
3171/* An XFX form instruction with the SPR field filled in. */
3172#define XSPR(op, xop, spr) \
3173 (X ((op), (xop)) | ((((unsigned long)(spr)) & 0x1f) << 16) | ((((unsigned long)(spr)) & 0x3e0) << 6))
3174#define XSPR_MASK (X_MASK | SPR_MASK)
3175
3176/* An XFX form instruction with the SPR field filled in except for the
3177 SPRBAT field. */
3178#define XSPRBAT_MASK (XSPR_MASK &~ SPRBAT_MASK)
3179
3180/* An XFX form instruction with the SPR field filled in except for the
3181 SPRG field. */
b84bf58a 3182#define XSPRG_MASK (XSPR_MASK & ~(0x1f << 16))
252b5132
RH		 3183
3184/* An X form instruction with everything filled in except the E field. */
3185#define XE_MASK (0xffff7fff)
3186
23976049
EZ		 3187/* An X form user context instruction. */
3188#define XUC(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x1f))
3189#define XUC_MASK XUC(0x3f, 0x1f)
3190
c3d65c1c
BE		 3191/* An XW form instruction. */
3192#define XW(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x3f) << 1) | ((rc) & 1))
3193/* The mask for a G form instruction. rc not supported at present. */
3194#define XW_MASK XW (0x3f, 0x3f, 0)
3195
081ba1b3
AM		 3196/* An APU form instruction. */
3197#define APU(op, xop, rc) (OP (op) | (((unsigned long)(xop)) & 0x3ff) << 1 | ((rc) & 1))
3198
3199/* The mask for an APU form instruction. */
3200#define APU_MASK APU (0x3f, 0x3ff, 1)
3201#define APU_RT_MASK (APU_MASK | RT_MASK)
3202#define APU_RA_MASK (APU_MASK | RA_MASK)
3203
252b5132
RH		 3204/* The BO encodings used in extended conditional branch mnemonics. */
3205#define BODNZF (0x0)
3206#define BODNZFP (0x1)
3207#define BODZF (0x2)
3208#define BODZFP (0x3)
252b5132
RH		 3209#define BODNZT (0x8)
3210#define BODNZTP (0x9)
3211#define BODZT (0xa)
3212#define BODZTP (0xb)
802a735e
AM		 3213
3214#define BOF (0x4)
3215#define BOFP (0x5)
94efba12
AM		 3216#define BOFM4 (0x6)
3217#define BOFP4 (0x7)
252b5132
RH		 3218#define BOT (0xc)
3219#define BOTP (0xd)
94efba12
AM		 3220#define BOTM4 (0xe)
3221#define BOTP4 (0xf)
802a735e 3222
252b5132
RH		 3223#define BODNZ (0x10)
3224#define BODNZP (0x11)
3225#define BODZ (0x12)
3226#define BODZP (0x13)
94efba12
AM		 3227#define BODNZM4 (0x18)
3228#define BODNZP4 (0x19)
3229#define BODZM4 (0x1a)
3230#define BODZP4 (0x1b)
802a735e 3231
252b5132
RH		 3232#define BOU (0x14)
3233
b9c361e0
JL		 3234/* The BO16 encodings used in extended VLE conditional branch mnemonics. */
3235#define BO16F (0x0)
3236#define BO16T (0x1)
3237
3238/* The BO32 encodings used in extended VLE conditional branch mnemonics. */
3239#define BO32F (0x0)
3240#define BO32T (0x1)
3241#define BO32DNZ (0x2)
3242#define BO32DZ (0x3)
3243
252b5132
RH		 3244/* The BI condition bit encodings used in extended conditional branch
3245 mnemonics. */
3246#define CBLT (0)
3247#define CBGT (1)
3248#define CBEQ (2)
3249#define CBSO (3)
3250
3251/* The TO encodings used in extended trap mnemonics. */
3252#define TOLGT (0x1)
3253#define TOLLT (0x2)
3254#define TOEQ (0x4)
3255#define TOLGE (0x5)
3256#define TOLNL (0x5)
3257#define TOLLE (0x6)
3258#define TOLNG (0x6)
3259#define TOGT (0x8)
3260#define TOGE (0xc)
3261#define TONL (0xc)
3262#define TOLT (0x10)
3263#define TOLE (0x14)
3264#define TONG (0x14)
3265#define TONE (0x18)
3266#define TOU (0x1f)
3267\f
3268/* Smaller names for the flags so each entry in the opcodes table will
3269 fit on a single line. */
3270#undef PPC
de866fcc 3271#define PPC PPC_OPCODE_PPC
661bd698 3272#define PPCCOM PPC_OPCODE_PPC | PPC_OPCODE_COMMON
661bd698 3273#define POWER4 PPC_OPCODE_POWER4
1ed8e1e4 3274#define POWER5 PPC_OPCODE_POWER5
702f0fb4 3275#define POWER6 PPC_OPCODE_POWER6
066be9f7 3276#define POWER7 PPC_OPCODE_POWER7
5817ffd1 3277#define POWER8 PPC_OPCODE_POWER8
a680de9a 3278#define POWER9 PPC_OPCODE_POWER9
ede602d7 3279#define CELL PPC_OPCODE_CELL
bdc70b4a 3280#define PPC64 PPC_OPCODE_64 | PPC_OPCODE_64_BRIDGE
6b069ee7 3281#define NON32 (PPC_OPCODE_64 | PPC_OPCODE_POWER4 \
bdc70b4a 3282 | PPC_OPCODE_EFS | PPC_OPCODE_E500MC | PPC_OPCODE_TITAN)
418c1742 3283#define PPC403 PPC_OPCODE_403
081ba1b3 3284#define PPC405 PPC_OPCODE_405
7d5b217e 3285#define PPC440 PPC_OPCODE_440
c8187e15 3286#define PPC464 PPC440
9fe54b1c 3287#define PPC476 PPC_OPCODE_476
ef5a96d5
AM		 3288#define PPC750 PPC_OPCODE_750
3289#define PPC7450 PPC_OPCODE_7450
3290#define PPC860 PPC_OPCODE_860
c3d65c1c 3291#define PPCPS PPC_OPCODE_PPCPS
a404d431 3292#define PPCVEC PPC_OPCODE_ALTIVEC
9a85b496
AM		 3293#define PPCVEC2 (PPC_OPCODE_POWER8 | PPC_OPCODE_E6500)
3294#define PPCVEC3 PPC_OPCODE_POWER9
9b4e5766 3295#define PPCVSX PPC_OPCODE_VSX
9570835e
AM		 3296#define PPCVSX2 PPC_OPCODE_POWER8
3297#define PPCVSX3 PPC_OPCODE_POWER9
de866fcc
AM		 3298#define POWER PPC_OPCODE_POWER
3299#define POWER2 PPC_OPCODE_POWER | PPC_OPCODE_POWER2
81a0b7e2
AM		 3300#define PWR2COM PPC_OPCODE_POWER | PPC_OPCODE_POWER2 | PPC_OPCODE_COMMON
3301#define PPCPWR2 PPC_OPCODE_PPC | PPC_OPCODE_POWER | PPC_OPCODE_POWER2 | PPC_OPCODE_COMMON
de866fcc 3302#define COM PPC_OPCODE_POWER | PPC_OPCODE_PPC | PPC_OPCODE_COMMON
de866fcc 3303#define M601 PPC_OPCODE_POWER | PPC_OPCODE_601
661bd698 3304#define PWRCOM PPC_OPCODE_POWER | PPC_OPCODE_601 | PPC_OPCODE_COMMON
de866fcc 3305#define MFDEC1 PPC_OPCODE_POWER
bdc70b4a 3306#define MFDEC2 PPC_OPCODE_PPC | PPC_OPCODE_601 | PPC_OPCODE_BOOKE | PPC_OPCODE_TITAN
418c1742 3307#define BOOKE PPC_OPCODE_BOOKE
14b57c7c 3308#define NO371 PPC_OPCODE_BOOKE | PPC_OPCODE_PPCPS | PPC_OPCODE_EFS
36ae0db3 3309#define PPCE300 PPC_OPCODE_E300
14b57c7c
AM		 3310#define PPCSPE PPC_OPCODE_SPE
3311#define PPCISEL PPC_OPCODE_ISEL
3312#define PPCEFS PPC_OPCODE_EFS
de866fcc 3313#define PPCBRLK PPC_OPCODE_BRLOCK
23976049 3314#define PPCPMR PPC_OPCODE_PMR
aea77599 3315#define PPCTMR PPC_OPCODE_TMR
de866fcc 3316#define PPCCHLK PPC_OPCODE_CACHELCK
23976049 3317#define PPCRFMCI PPC_OPCODE_RFMCI
19a6653c 3318#define E500MC PPC_OPCODE_E500MC
634b50f2 3319#define PPCA2 PPC_OPCODE_A2
43e65147 3320#define TITAN PPC_OPCODE_TITAN
62adc510 3321#define MULHW PPC_OPCODE_405 | PPC_OPCODE_440 | PPC_OPCODE_476 | TITAN
e01d869a 3322#define E500 PPC_OPCODE_E500
aea77599 3323#define E6500 PPC_OPCODE_E6500
b9c361e0 3324#define PPCVLE PPC_OPCODE_VLE
ef85eab0 3325#define PPCHTM PPC_OPCODE_POWER8
dfdaec14 3326#define E200Z4 PPC_OPCODE_E200Z4
e3c2f928 3327#define PPCLSP PPC_OPCODE_LSP
4fff86c5
PB		 3328/* The list of embedded processors that use the embedded operand ordering
3329 for the 3 operand dcbt and dcbtst instructions. */
3330#define DCBT_EO (PPC_OPCODE_E500 | PPC_OPCODE_E500MC | PPC_OPCODE_476 \
14b57c7c 3331 | PPC_OPCODE_A2)
4fff86c5
PB		 3332
3333
252b5132
RH		 3334\f
3335/* The opcode table.
3336
3337 The format of the opcode table is:
3338
8ebac3aa 3339 NAME OPCODE MASK FLAGS ANTI {OPERANDS}
252b5132
RH		 3340
3341 NAME is the name of the instruction.
3342 OPCODE is the instruction opcode.
3343 MASK is the opcode mask; this is used to tell the disassembler
3344 which bits in the actual opcode must match OPCODE.
8ebac3aa
AM		 3345 FLAGS are flags indicating which processors support the instruction.
3346 ANTI indicates which processors don't support the instruction.
252b5132
RH		 3347 OPERANDS is the list of operands.
3348
3349 The disassembler reads the table in order and prints the first
3350 instruction which matches, so this table is sorted to put more
de866fcc
AM		 3351 specific instructions before more general instructions.
3352
3353 This table must be sorted by major opcode. Please try to keep it
3354 vaguely sorted within major opcode too, except of course where
3355 constrained otherwise by disassembler operation. */
252b5132
RH		 3356
3357const struct powerpc_opcode powerpc_opcodes[] = {
14b57c7c
AM		 3358{"attn", X(0,256), X_MASK, POWER4|PPCA2, PPC476|PPCVLE, {0}},
3359{"tdlgti", OPTO(2,TOLGT), OPTO_MASK, PPC64, PPCVLE, {RA, SI}},
3360{"tdllti", OPTO(2,TOLLT), OPTO_MASK, PPC64, PPCVLE, {RA, SI}},
3361{"tdeqi", OPTO(2,TOEQ), OPTO_MASK, PPC64, PPCVLE, {RA, SI}},
3362{"tdlgei", OPTO(2,TOLGE), OPTO_MASK, PPC64, PPCVLE, {RA, SI}},
3363{"tdlnli", OPTO(2,TOLNL), OPTO_MASK, PPC64, PPCVLE, {RA, SI}},
3364{"tdllei", OPTO(2,TOLLE), OPTO_MASK, PPC64, PPCVLE, {RA, SI}},
3365{"tdlngi", OPTO(2,TOLNG), OPTO_MASK, PPC64, PPCVLE, {RA, SI}},
3366{"tdgti", OPTO(2,TOGT), OPTO_MASK, PPC64, PPCVLE, {RA, SI}},
3367{"tdgei", OPTO(2,TOGE), OPTO_MASK, PPC64, PPCVLE, {RA, SI}},
3368{"tdnli", OPTO(2,TONL), OPTO_MASK, PPC64, PPCVLE, {RA, SI}},
3369{"tdlti", OPTO(2,TOLT), OPTO_MASK, PPC64, PPCVLE, {RA, SI}},
3370{"tdlei", OPTO(2,TOLE), OPTO_MASK, PPC64, PPCVLE, {RA, SI}},
3371{"tdngi", OPTO(2,TONG), OPTO_MASK, PPC64, PPCVLE, {RA, SI}},
3372{"tdnei", OPTO(2,TONE), OPTO_MASK, PPC64, PPCVLE, {RA, SI}},
3373{"tdui", OPTO(2,TOU), OPTO_MASK, PPC64, PPCVLE, {RA, SI}},
3374{"tdi", OP(2), OP_MASK, PPC64, PPCVLE, {TO, RA, SI}},
3375
3376{"twlgti", OPTO(3,TOLGT), OPTO_MASK, PPCCOM, PPCVLE, {RA, SI}},
3377{"tlgti", OPTO(3,TOLGT), OPTO_MASK, PWRCOM, PPCVLE, {RA, SI}},
3378{"twllti", OPTO(3,TOLLT), OPTO_MASK, PPCCOM, PPCVLE, {RA, SI}},
3379{"tllti", OPTO(3,TOLLT), OPTO_MASK, PWRCOM, PPCVLE, {RA, SI}},
3380{"tweqi", OPTO(3,TOEQ), OPTO_MASK, PPCCOM, PPCVLE, {RA, SI}},
3381{"teqi", OPTO(3,TOEQ), OPTO_MASK, PWRCOM, PPCVLE, {RA, SI}},
3382{"twlgei", OPTO(3,TOLGE), OPTO_MASK, PPCCOM, PPCVLE, {RA, SI}},
3383{"tlgei", OPTO(3,TOLGE), OPTO_MASK, PWRCOM, PPCVLE, {RA, SI}},
3384{"twlnli", OPTO(3,TOLNL), OPTO_MASK, PPCCOM, PPCVLE, {RA, SI}},
3385{"tlnli", OPTO(3,TOLNL), OPTO_MASK, PWRCOM, PPCVLE, {RA, SI}},
3386{"twllei", OPTO(3,TOLLE), OPTO_MASK, PPCCOM, PPCVLE, {RA, SI}},
3387{"tllei", OPTO(3,TOLLE), OPTO_MASK, PWRCOM, PPCVLE, {RA, SI}},
3388{"twlngi", OPTO(3,TOLNG), OPTO_MASK, PPCCOM, PPCVLE, {RA, SI}},
3389{"tlngi", OPTO(3,TOLNG), OPTO_MASK, PWRCOM, PPCVLE, {RA, SI}},
3390{"twgti", OPTO(3,TOGT), OPTO_MASK, PPCCOM, PPCVLE, {RA, SI}},
3391{"tgti", OPTO(3,TOGT), OPTO_MASK, PWRCOM, PPCVLE, {RA, SI}},
3392{"twgei", OPTO(3,TOGE), OPTO_MASK, PPCCOM, PPCVLE, {RA, SI}},
3393{"tgei", OPTO(3,TOGE), OPTO_MASK, PWRCOM, PPCVLE, {RA, SI}},
3394{"twnli", OPTO(3,TONL), OPTO_MASK, PPCCOM, PPCVLE, {RA, SI}},
3395{"tnli", OPTO(3,TONL), OPTO_MASK, PWRCOM, PPCVLE, {RA, SI}},
3396{"twlti", OPTO(3,TOLT), OPTO_MASK, PPCCOM, PPCVLE, {RA, SI}},
3397{"tlti", OPTO(3,TOLT), OPTO_MASK, PWRCOM, PPCVLE, {RA, SI}},
3398{"twlei", OPTO(3,TOLE), OPTO_MASK, PPCCOM, PPCVLE, {RA, SI}},
3399{"tlei", OPTO(3,TOLE), OPTO_MASK, PWRCOM, PPCVLE, {RA, SI}},
3400{"twngi", OPTO(3,TONG), OPTO_MASK, PPCCOM, PPCVLE, {RA, SI}},
3401{"tngi", OPTO(3,TONG), OPTO_MASK, PWRCOM, PPCVLE, {RA, SI}},
3402{"twnei", OPTO(3,TONE), OPTO_MASK, PPCCOM, PPCVLE, {RA, SI}},
3403{"tnei", OPTO(3,TONE), OPTO_MASK, PWRCOM, PPCVLE, {RA, SI}},
3404{"twui", OPTO(3,TOU), OPTO_MASK, PPCCOM, PPCVLE, {RA, SI}},
3405{"tui", OPTO(3,TOU), OPTO_MASK, PWRCOM, PPCVLE, {RA, SI}},
3406{"twi", OP(3), OP_MASK, PPCCOM, PPCVLE, {TO, RA, SI}},
3407{"ti", OP(3), OP_MASK, PWRCOM, PPCVLE, {TO, RA, SI}},
3408
3409{"ps_cmpu0", X (4, 0), XBF_MASK, PPCPS, 0, {BF, FRA, FRB}},
3410{"vaddubm", VX (4, 0), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3411{"vmul10cuq", VX (4, 1), VXVB_MASK, PPCVEC3, 0, {VD, VA}},
3412{"vmaxub", VX (4, 2), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3413{"vrlb", VX (4, 4), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3414{"vcmpequb", VXR(4, 6,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
3415{"vcmpneb", VXR(4, 7,0), VXR_MASK, PPCVEC3, 0, {VD, VA, VB}},
3416{"vmuloub", VX (4, 8), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3417{"vaddfp", VX (4, 10), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3418{"psq_lx", XW (4, 6,0), XW_MASK, PPCPS, 0, {FRT,RA,RB,PSWM,PSQM}},
3419{"vmrghb", VX (4, 12), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3420{"psq_stx", XW (4, 7,0), XW_MASK, PPCPS, 0, {FRS,RA,RB,PSWM,PSQM}},
3421{"vpkuhum", VX (4, 14), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3422{"mulhhwu", XRC(4, 8,0), X_MASK, MULHW, 0, {RT, RA, RB}},
3423{"mulhhwu.", XRC(4, 8,1), X_MASK, MULHW, 0, {RT, RA, RB}},
3424{"ps_sum0", A (4, 10,0), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
3425{"ps_sum0.", A (4, 10,1), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
3426{"ps_sum1", A (4, 11,0), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
3427{"ps_sum1.", A (4, 11,1), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
3428{"ps_muls0", A (4, 12,0), AFRB_MASK, PPCPS, 0, {FRT, FRA, FRC}},
3429{"machhwu", XO (4, 12,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3430{"ps_muls0.", A (4, 12,1), AFRB_MASK, PPCPS, 0, {FRT, FRA, FRC}},
3431{"machhwu.", XO (4, 12,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3432{"ps_muls1", A (4, 13,0), AFRB_MASK, PPCPS, 0, {FRT, FRA, FRC}},
3433{"ps_muls1.", A (4, 13,1), AFRB_MASK, PPCPS, 0, {FRT, FRA, FRC}},
3434{"ps_madds0", A (4, 14,0), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
3435{"ps_madds0.", A (4, 14,1), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
3436{"ps_madds1", A (4, 15,0), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
3437{"ps_madds1.", A (4, 15,1), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
3438{"vmhaddshs", VXA(4, 32), VXA_MASK, PPCVEC, 0, {VD, VA, VB, VC}},
3439{"vmhraddshs", VXA(4, 33), VXA_MASK, PPCVEC, 0, {VD, VA, VB, VC}},
3440{"vmladduhm", VXA(4, 34), VXA_MASK, PPCVEC, 0, {VD, VA, VB, VC}},
3441{"vmsumudm", VXA(4, 35), VXA_MASK, PPCVEC3, 0, {VD, VA, VB, VC}},
3442{"ps_div", A (4, 18,0), AFRC_MASK, PPCPS, 0, {FRT, FRA, FRB}},
3443{"vmsumubm", VXA(4, 36), VXA_MASK, PPCVEC, 0, {VD, VA, VB, VC}},
3444{"ps_div.", A (4, 18,1), AFRC_MASK, PPCPS, 0, {FRT, FRA, FRB}},
3445{"vmsummbm", VXA(4, 37), VXA_MASK, PPCVEC, 0, {VD, VA, VB, VC}},
3446{"vmsumuhm", VXA(4, 38), VXA_MASK, PPCVEC, 0, {VD, VA, VB, VC}},
3447{"vmsumuhs", VXA(4, 39), VXA_MASK, PPCVEC, 0, {VD, VA, VB, VC}},
3448{"ps_sub", A (4, 20,0), AFRC_MASK, PPCPS, 0, {FRT, FRA, FRB}},
3449{"vmsumshm", VXA(4, 40), VXA_MASK, PPCVEC, 0, {VD, VA, VB, VC}},
3450{"ps_sub.", A (4, 20,1), AFRC_MASK, PPCPS, 0, {FRT, FRA, FRB}},
3451{"vmsumshs", VXA(4, 41), VXA_MASK, PPCVEC, 0, {VD, VA, VB, VC}},
3452{"ps_add", A (4, 21,0), AFRC_MASK, PPCPS, 0, {FRT, FRA, FRB}},
3453{"vsel", VXA(4, 42), VXA_MASK, PPCVEC, 0, {VD, VA, VB, VC}},
3454{"ps_add.", A (4, 21,1), AFRC_MASK, PPCPS, 0, {FRT, FRA, FRB}},
3455{"vperm", VXA(4, 43), VXA_MASK, PPCVEC, 0, {VD, VA, VB, VC}},
3456{"vsldoi", VXA(4, 44), VXASHB_MASK, PPCVEC, 0, {VD, VA, VB, SHB}},
3457{"vpermxor", VXA(4, 45), VXA_MASK, PPCVEC2, 0, {VD, VA, VB, VC}},
3458{"ps_sel", A (4, 23,0), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
3459{"vmaddfp", VXA(4, 46), VXA_MASK, PPCVEC, 0, {VD, VA, VC, VB}},
3460{"ps_sel.", A (4, 23,1), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
3461{"vnmsubfp", VXA(4, 47), VXA_MASK, PPCVEC, 0, {VD, VA, VC, VB}},
3462{"ps_res", A (4, 24,0), AFRAFRC_MASK, PPCPS, 0, {FRT, FRB}},
3463{"maddhd", VXA(4, 48), VXA_MASK, POWER9, 0, {RT, RA, RB, RC}},
3464{"ps_res.", A (4, 24,1), AFRAFRC_MASK, PPCPS, 0, {FRT, FRB}},
3465{"maddhdu", VXA(4, 49), VXA_MASK, POWER9, 0, {RT, RA, RB, RC}},
3466{"ps_mul", A (4, 25,0), AFRB_MASK, PPCPS, 0, {FRT, FRA, FRC}},
3467{"ps_mul.", A (4, 25,1), AFRB_MASK, PPCPS, 0, {FRT, FRA, FRC}},
3468{"maddld", VXA(4, 51), VXA_MASK, POWER9, 0, {RT, RA, RB, RC}},
3469{"ps_rsqrte", A (4, 26,0), AFRAFRC_MASK, PPCPS, 0, {FRT, FRB}},
3470{"ps_rsqrte.", A (4, 26,1), AFRAFRC_MASK, PPCPS, 0, {FRT, FRB}},
3471{"ps_msub", A (4, 28,0), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
3472{"ps_msub.", A (4, 28,1), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
3473{"ps_madd", A (4, 29,0), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
3474{"ps_madd.", A (4, 29,1), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
3475{"vpermr", VXA(4, 59), VXA_MASK, PPCVEC3, 0, {VD, VA, VB, VC}},
3476{"ps_nmsub", A (4, 30,0), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
3477{"vaddeuqm", VXA(4, 60), VXA_MASK, PPCVEC2, 0, {VD, VA, VB, VC}},
3478{"ps_nmsub.", A (4, 30,1), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
3479{"vaddecuq", VXA(4, 61), VXA_MASK, PPCVEC2, 0, {VD, VA, VB, VC}},
3480{"ps_nmadd", A (4, 31,0), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
3481{"vsubeuqm", VXA(4, 62), VXA_MASK, PPCVEC2, 0, {VD, VA, VB, VC}},
3482{"ps_nmadd.", A (4, 31,1), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
3483{"vsubecuq", VXA(4, 63), VXA_MASK, PPCVEC2, 0, {VD, VA, VB, VC}},
3484{"ps_cmpo0", X (4, 32), XBF_MASK, PPCPS, 0, {BF, FRA, FRB}},
3485{"vadduhm", VX (4, 64), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3486{"vmul10ecuq", VX (4, 65), VX_MASK, PPCVEC3, 0, {VD, VA, VB}},
3487{"vmaxuh", VX (4, 66), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3488{"vrlh", VX (4, 68), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3489{"vcmpequh", VXR(4, 70,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
3490{"vcmpneh", VXR(4, 71,0), VXR_MASK, PPCVEC3, 0, {VD, VA, VB}},
3491{"vmulouh", VX (4, 72), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3492{"vsubfp", VX (4, 74), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3493{"psq_lux", XW (4, 38,0), XW_MASK, PPCPS, 0, {FRT,RA,RB,PSWM,PSQM}},
3494{"vmrghh", VX (4, 76), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3495{"psq_stux", XW (4, 39,0), XW_MASK, PPCPS, 0, {FRS,RA,RB,PSWM,PSQM}},
3496{"vpkuwum", VX (4, 78), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3497{"ps_neg", XRC(4, 40,0), XRA_MASK, PPCPS, 0, {FRT, FRB}},
3498{"mulhhw", XRC(4, 40,0), X_MASK, MULHW, 0, {RT, RA, RB}},
3499{"ps_neg.", XRC(4, 40,1), XRA_MASK, PPCPS, 0, {FRT, FRB}},
3500{"mulhhw.", XRC(4, 40,1), X_MASK, MULHW, 0, {RT, RA, RB}},
3501{"machhw", XO (4, 44,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3502{"machhw.", XO (4, 44,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3503{"nmachhw", XO (4, 46,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3504{"nmachhw.", XO (4, 46,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3505{"ps_cmpu1", X (4, 64), XBF_MASK, PPCPS, 0, {BF, FRA, FRB}},
3506{"vadduwm", VX (4, 128), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3507{"vmaxuw", VX (4, 130), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3508{"vrlw", VX (4, 132), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3509{"vrlwmi", VX (4, 133), VX_MASK, PPCVEC3, 0, {VD, VA, VB}},
3510{"vcmpequw", VXR(4, 134,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
3511{"vcmpnew", VXR(4, 135,0), VXR_MASK, PPCVEC3, 0, {VD, VA, VB}},
3512{"vmulouw", VX (4, 136), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3513{"vmuluwm", VX (4, 137), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3514{"vmrghw", VX (4, 140), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3515{"vpkuhus", VX (4, 142), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3516{"ps_mr", XRC(4, 72,0), XRA_MASK, PPCPS, 0, {FRT, FRB}},
3517{"ps_mr.", XRC(4, 72,1), XRA_MASK, PPCPS, 0, {FRT, FRB}},
3518{"machhwsu", XO (4, 76,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3519{"machhwsu.", XO (4, 76,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3520{"ps_cmpo1", X (4, 96), XBF_MASK, PPCPS, 0, {BF, FRA, FRB}},
3521{"vaddudm", VX (4, 192), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3522{"vmaxud", VX (4, 194), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3523{"vrld", VX (4, 196), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3524{"vrldmi", VX (4, 197), VX_MASK, PPCVEC3, 0, {VD, VA, VB}},
3525{"vcmpeqfp", VXR(4, 198,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
3526{"vcmpequd", VXR(4, 199,0), VXR_MASK, PPCVEC2, 0, {VD, VA, VB}},
3527{"vpkuwus", VX (4, 206), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3528{"machhws", XO (4, 108,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3529{"machhws.", XO (4, 108,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3530{"nmachhws", XO (4, 110,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3531{"nmachhws.", XO (4, 110,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3532{"vadduqm", VX (4, 256), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3533{"vmaxsb", VX (4, 258), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3534{"vslb", VX (4, 260), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3535{"vcmpnezb", VXR(4, 263,0), VXR_MASK, PPCVEC3, 0, {VD, VA, VB}},
3536{"vmulosb", VX (4, 264), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3537{"vrefp", VX (4, 266), VXVA_MASK, PPCVEC, 0, {VD, VB}},
3538{"vmrglb", VX (4, 268), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3539{"vpkshus", VX (4, 270), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3540{"ps_nabs", XRC(4, 136,0), XRA_MASK, PPCPS, 0, {FRT, FRB}},
3541{"mulchwu", XRC(4, 136,0), X_MASK, MULHW, 0, {RT, RA, RB}},
3542{"ps_nabs.", XRC(4, 136,1), XRA_MASK, PPCPS, 0, {FRT, FRB}},
3543{"mulchwu.", XRC(4, 136,1), X_MASK, MULHW, 0, {RT, RA, RB}},
3544{"macchwu", XO (4, 140,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3545{"macchwu.", XO (4, 140,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3546{"vaddcuq", VX (4, 320), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3547{"vmaxsh", VX (4, 322), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3548{"vslh", VX (4, 324), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3549{"vcmpnezh", VXR(4, 327,0), VXR_MASK, PPCVEC3, 0, {VD, VA, VB}},
3550{"vmulosh", VX (4, 328), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3551{"vrsqrtefp", VX (4, 330), VXVA_MASK, PPCVEC, 0, {VD, VB}},
3552{"vmrglh", VX (4, 332), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3553{"vpkswus", VX (4, 334), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3554{"mulchw", XRC(4, 168,0), X_MASK, MULHW, 0, {RT, RA, RB}},
3555{"mulchw.", XRC(4, 168,1), X_MASK, MULHW, 0, {RT, RA, RB}},
3556{"macchw", XO (4, 172,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3557{"macchw.", XO (4, 172,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3558{"nmacchw", XO (4, 174,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3559{"nmacchw.", XO (4, 174,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3560{"vaddcuw", VX (4, 384), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3561{"vmaxsw", VX (4, 386), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3562{"vslw", VX (4, 388), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3563{"vrlwnm", VX (4, 389), VX_MASK, PPCVEC3, 0, {VD, VA, VB}},
3564{"vcmpnezw", VXR(4, 391,0), VXR_MASK, PPCVEC3, 0, {VD, VA, VB}},
3565{"vmulosw", VX (4, 392), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3566{"vexptefp", VX (4, 394), VXVA_MASK, PPCVEC, 0, {VD, VB}},
3567{"vmrglw", VX (4, 396), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3568{"vpkshss", VX (4, 398), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3569{"macchwsu", XO (4, 204,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3570{"macchwsu.", XO (4, 204,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3571{"vmaxsd", VX (4, 450), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3572{"vsl", VX (4, 452), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3573{"vrldnm", VX (4, 453), VX_MASK, PPCVEC3, 0, {VD, VA, VB}},
3574{"vcmpgefp", VXR(4, 454,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
3575{"vlogefp", VX (4, 458), VXVA_MASK, PPCVEC, 0, {VD, VB}},
3576{"vpkswss", VX (4, 462), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3577{"macchws", XO (4, 236,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3578{"macchws.", XO (4, 236,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3579{"nmacchws", XO (4, 238,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3580{"nmacchws.", XO (4, 238,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3581{"evaddw", VX (4, 512), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3582{"vaddubs", VX (4, 512), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3583{"vmul10uq", VX (4, 513), VXVB_MASK, PPCVEC3, 0, {VD, VA}},
3584{"evaddiw", VX (4, 514), VX_MASK, PPCSPE, 0, {RS, RB, UIMM}},
3585{"vminub", VX (4, 514), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3586{"evsubfw", VX (4, 516), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3587{"evsubw", VX (4, 516), VX_MASK, PPCSPE, 0, {RS, RB, RA}},
3588{"vsrb", VX (4, 516), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3589{"evsubifw", VX (4, 518), VX_MASK, PPCSPE, 0, {RS, UIMM, RB}},
3590{"evsubiw", VX (4, 518), VX_MASK, PPCSPE, 0, {RS, RB, UIMM}},
3591{"vcmpgtub", VXR(4, 518,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
3592{"evabs", VX (4, 520), VX_MASK, PPCSPE, 0, {RS, RA}},
3593{"vmuleub", VX (4, 520), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3594{"evneg", VX (4, 521), VX_MASK, PPCSPE, 0, {RS, RA}},
3595{"evextsb", VX (4, 522), VX_MASK, PPCSPE, 0, {RS, RA}},
3596{"vrfin", VX (4, 522), VXVA_MASK, PPCVEC, 0, {VD, VB}},
3597{"evextsh", VX (4, 523), VX_MASK, PPCSPE, 0, {RS, RA}},
3598{"evrndw", VX (4, 524), VX_MASK, PPCSPE, 0, {RS, RA}},
3599{"vspltb", VX (4, 524), VXUIMM4_MASK, PPCVEC, 0, {VD, VB, UIMM4}},
3600{"vextractub", VX (4, 525), VXUIMM4_MASK, PPCVEC3, 0, {VD, VB, UIMM4}},
3601{"evcntlzw", VX (4, 525), VX_MASK, PPCSPE, 0, {RS, RA}},
3602{"evcntlsw", VX (4, 526), VX_MASK, PPCSPE, 0, {RS, RA}},
3603{"vupkhsb", VX (4, 526), VXVA_MASK, PPCVEC, 0, {VD, VB}},
3604{"brinc", VX (4, 527), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3605{"ps_abs", XRC(4, 264,0), XRA_MASK, PPCPS, 0, {FRT, FRB}},
3606{"ps_abs.", XRC(4, 264,1), XRA_MASK, PPCPS, 0, {FRT, FRB}},
3607{"evand", VX (4, 529), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3608{"evandc", VX (4, 530), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3609{"evxor", VX (4, 534), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3610{"evmr", VX (4, 535), VX_MASK, PPCSPE, 0, {RS, RA, BBA}},
3611{"evor", VX (4, 535), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3612{"evnor", VX (4, 536), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3613{"evnot", VX (4, 536), VX_MASK, PPCSPE, 0, {RS, RA, BBA}},
3614{"get", APU(4, 268,0), APU_RA_MASK, PPC405, 0, {RT, FSL}},
3615{"eveqv", VX (4, 537), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3616{"evorc", VX (4, 539), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3617{"evnand", VX (4, 542), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3618{"evsrwu", VX (4, 544), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3619{"evsrws", VX (4, 545), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3620{"evsrwiu", VX (4, 546), VX_MASK, PPCSPE, 0, {RS, RA, EVUIMM}},
3621{"evsrwis", VX (4, 547), VX_MASK, PPCSPE, 0, {RS, RA, EVUIMM}},
3622{"evslw", VX (4, 548), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3623{"evslwi", VX (4, 550), VX_MASK, PPCSPE, 0, {RS, RA, EVUIMM}},
3624{"evrlw", VX (4, 552), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3625{"evsplati", VX (4, 553), VX_MASK, PPCSPE, 0, {RS, SIMM}},
3626{"evrlwi", VX (4, 554), VX_MASK, PPCSPE, 0, {RS, RA, EVUIMM}},
3627{"evsplatfi", VX (4, 555), VX_MASK, PPCSPE, 0, {RS, SIMM}},
3628{"evmergehi", VX (4, 556), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3629{"evmergelo", VX (4, 557), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3630{"evmergehilo", VX (4, 558), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3631{"evmergelohi", VX (4, 559), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3632{"evcmpgtu", VX (4, 560), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}},
3633{"evcmpgts", VX (4, 561), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}},
3634{"evcmpltu", VX (4, 562), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}},
3635{"evcmplts", VX (4, 563), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}},
3636{"evcmpeq", VX (4, 564), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}},
3637{"cget", APU(4, 284,0), APU_RA_MASK, PPC405, 0, {RT, FSL}},
3638{"vadduhs", VX (4, 576), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3639{"vmul10euq", VX (4, 577), VX_MASK, PPCVEC3, 0, {VD, VA, VB}},
3640{"vminuh", VX (4, 578), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3641{"vsrh", VX (4, 580), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3642{"vcmpgtuh", VXR(4, 582,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
3643{"vmuleuh", VX (4, 584), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3644{"vrfiz", VX (4, 586), VXVA_MASK, PPCVEC, 0, {VD, VB}},
3645{"vsplth", VX (4, 588), VXUIMM3_MASK, PPCVEC, 0, {VD, VB, UIMM3}},
3646{"vextractuh", VX (4, 589), VXUIMM4_MASK, PPCVEC3, 0, {VD, VB, UIMM4}},
3647{"vupkhsh", VX (4, 590), VXVA_MASK, PPCVEC, 0, {VD, VB}},
3648{"nget", APU(4, 300,0), APU_RA_MASK, PPC405, 0, {RT, FSL}},
3649{"evsel", EVSEL(4,79), EVSEL_MASK, PPCSPE, 0, {RS, RA, RB, CRFS}},
3650{"ncget", APU(4, 316,0), APU_RA_MASK, PPC405, 0, {RT, FSL}},
3651{"evfsadd", VX (4, 640), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3652{"vadduws", VX (4, 640), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3653{"evfssub", VX (4, 641), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3654{"vminuw", VX (4, 642), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3655{"evfsabs", VX (4, 644), VX_MASK, PPCSPE, 0, {RS, RA}},
3656{"vsrw", VX (4, 644), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3657{"evfsnabs", VX (4, 645), VX_MASK, PPCSPE, 0, {RS, RA}},
3658{"evfsneg", VX (4, 646), VX_MASK, PPCSPE, 0, {RS, RA}},
3659{"vcmpgtuw", VXR(4, 646,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
3660{"vmuleuw", VX (4, 648), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3661{"evfsmul", VX (4, 648), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3662{"evfsdiv", VX (4, 649), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3663{"vrfip", VX (4, 650), VXVA_MASK, PPCVEC, 0, {VD, VB}},
3664{"evfscmpgt", VX (4, 652), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}},
3665{"vspltw", VX (4, 652), VXUIMM2_MASK, PPCVEC, 0, {VD, VB, UIMM2}},
3666{"vextractuw", VX (4, 653), VXUIMM4_MASK, PPCVEC3, 0, {VD, VB, UIMM4}},
3667{"evfscmplt", VX (4, 653), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}},
3668{"evfscmpeq", VX (4, 654), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}},
3669{"vupklsb", VX (4, 654), VXVA_MASK, PPCVEC, 0, {VD, VB}},
3670{"evfscfui", VX (4, 656), VX_MASK, PPCSPE, 0, {RS, RB}},
3671{"evfscfsi", VX (4, 657), VX_MASK, PPCSPE, 0, {RS, RB}},
3672{"evfscfuf", VX (4, 658), VX_MASK, PPCSPE, 0, {RS, RB}},
3673{"evfscfsf", VX (4, 659), VX_MASK, PPCSPE, 0, {RS, RB}},
3674{"evfsctui", VX (4, 660), VX_MASK, PPCSPE, 0, {RS, RB}},
3675{"evfsctsi", VX (4, 661), VX_MASK, PPCSPE, 0, {RS, RB}},
3676{"evfsctuf", VX (4, 662), VX_MASK, PPCSPE, 0, {RS, RB}},
3677{"evfsctsf", VX (4, 663), VX_MASK, PPCSPE, 0, {RS, RB}},
3678{"evfsctuiz", VX (4, 664), VX_MASK, PPCSPE, 0, {RS, RB}},
3679{"put", APU(4, 332,0), APU_RT_MASK, PPC405, 0, {RA, FSL}},
3680{"evfsctsiz", VX (4, 666), VX_MASK, PPCSPE, 0, {RS, RB}},
3681{"evfststgt", VX (4, 668), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}},
3682{"evfststlt", VX (4, 669), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}},
3683{"evfststeq", VX (4, 670), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}},
3684{"cput", APU(4, 348,0), APU_RT_MASK, PPC405, 0, {RA, FSL}},
3685{"efsadd", VX (4, 704), VX_MASK, PPCEFS, 0, {RS, RA, RB}},
3686{"efssub", VX (4, 705), VX_MASK, PPCEFS, 0, {RS, RA, RB}},
3687{"vminud", VX (4, 706), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3688{"efsabs", VX (4, 708), VX_MASK, PPCEFS, 0, {RS, RA}},
3689{"vsr", VX (4, 708), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3690{"efsnabs", VX (4, 709), VX_MASK, PPCEFS, 0, {RS, RA}},
3691{"efsneg", VX (4, 710), VX_MASK, PPCEFS, 0, {RS, RA}},
3692{"vcmpgtfp", VXR(4, 710,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
3693{"vcmpgtud", VXR(4, 711,0), VXR_MASK, PPCVEC2, 0, {VD, VA, VB}},
3694{"efsmul", VX (4, 712), VX_MASK, PPCEFS, 0, {RS, RA, RB}},
3695{"efsdiv", VX (4, 713), VX_MASK, PPCEFS, 0, {RS, RA, RB}},
3696{"vrfim", VX (4, 714), VXVA_MASK, PPCVEC, 0, {VD, VB}},
3697{"efscmpgt", VX (4, 716), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}},
3698{"vextractd", VX (4, 717), VXUIMM4_MASK, PPCVEC3, 0, {VD, VB, UIMM4}},
3699{"efscmplt", VX (4, 717), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}},
3700{"efscmpeq", VX (4, 718), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}},
3701{"vupklsh", VX (4, 718), VXVA_MASK, PPCVEC, 0, {VD, VB}},
3702{"efscfd", VX (4, 719), VX_MASK, PPCEFS, 0, {RS, RB}},
3703{"efscfui", VX (4, 720), VX_MASK, PPCEFS, 0, {RS, RB}},
3704{"efscfsi", VX (4, 721), VX_MASK, PPCEFS, 0, {RS, RB}},
3705{"efscfuf", VX (4, 722), VX_MASK, PPCEFS, 0, {RS, RB}},
3706{"efscfsf", VX (4, 723), VX_MASK, PPCEFS, 0, {RS, RB}},
3707{"efsctui", VX (4, 724), VX_MASK, PPCEFS, 0, {RS, RB}},
3708{"efsctsi", VX (4, 725), VX_MASK, PPCEFS, 0, {RS, RB}},
3709{"efsctuf", VX (4, 726), VX_MASK, PPCEFS, 0, {RS, RB}},
3710{"efsctsf", VX (4, 727), VX_MASK, PPCEFS, 0, {RS, RB}},
3711{"efsctuiz", VX (4, 728), VX_MASK, PPCEFS, 0, {RS, RB}},
3712{"nput", APU(4, 364,0), APU_RT_MASK, PPC405, 0, {RA, FSL}},
3713{"efsctsiz", VX (4, 730), VX_MASK, PPCEFS, 0, {RS, RB}},
3714{"efststgt", VX (4, 732), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}},
3715{"efststlt", VX (4, 733), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}},
3716{"efststeq", VX (4, 734), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}},
3717{"efdadd", VX (4, 736), VX_MASK, PPCEFS, 0, {RS, RA, RB}},
3718{"efdsub", VX (4, 737), VX_MASK, PPCEFS, 0, {RS, RA, RB}},
3719{"efdcfuid", VX (4, 738), VX_MASK, PPCEFS, 0, {RS, RB}},
3720{"efdcfsid", VX (4, 739), VX_MASK, PPCEFS, 0, {RS, RB}},
3721{"efdabs", VX (4, 740), VX_MASK, PPCEFS, 0, {RS, RA}},
3722{"efdnabs", VX (4, 741), VX_MASK, PPCEFS, 0, {RS, RA}},
3723{"efdneg", VX (4, 742), VX_MASK, PPCEFS, 0, {RS, RA}},
3724{"efdmul", VX (4, 744), VX_MASK, PPCEFS, 0, {RS, RA, RB}},
3725{"efddiv", VX (4, 745), VX_MASK, PPCEFS, 0, {RS, RA, RB}},
3726{"efdctuidz", VX (4, 746), VX_MASK, PPCEFS, 0, {RS, RB}},
3727{"efdctsidz", VX (4, 747), VX_MASK, PPCEFS, 0, {RS, RB}},
3728{"efdcmpgt", VX (4, 748), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}},
3729{"efdcmplt", VX (4, 749), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}},
3730{"efdcmpeq", VX (4, 750), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}},
3731{"efdcfs", VX (4, 751), VX_MASK, PPCEFS, 0, {RS, RB}},
3732{"efdcfui", VX (4, 752), VX_MASK, PPCEFS, 0, {RS, RB}},
3733{"efdcfsi", VX (4, 753), VX_MASK, PPCEFS, 0, {RS, RB}},
3734{"efdcfuf", VX (4, 754), VX_MASK, PPCEFS, 0, {RS, RB}},
3735{"efdcfsf", VX (4, 755), VX_MASK, PPCEFS, 0, {RS, RB}},
3736{"efdctui", VX (4, 756), VX_MASK, PPCEFS, 0, {RS, RB}},
3737{"efdctsi", VX (4, 757), VX_MASK, PPCEFS, 0, {RS, RB}},
3738{"efdctuf", VX (4, 758), VX_MASK, PPCEFS, 0, {RS, RB}},
3739{"efdctsf", VX (4, 759), VX_MASK, PPCEFS, 0, {RS, RB}},
3740{"efdctuiz", VX (4, 760), VX_MASK, PPCEFS, 0, {RS, RB}},
3741{"ncput", APU(4, 380,0), APU_RT_MASK, PPC405, 0, {RA, FSL}},
3742{"efdctsiz", VX (4, 762), VX_MASK, PPCEFS, 0, {RS, RB}},
3743{"efdtstgt", VX (4, 764), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}},
3744{"efdtstlt", VX (4, 765), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}},
3745{"efdtsteq", VX (4, 766), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}},
3746{"evlddx", VX (4, 768), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3747{"vaddsbs", VX (4, 768), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3748{"evldd", VX (4, 769), VX_MASK, PPCSPE, 0, {RS, EVUIMM_8, RA}},
3749{"evldwx", VX (4, 770), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3750{"vminsb", VX (4, 770), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3751{"evldw", VX (4, 771), VX_MASK, PPCSPE, 0, {RS, EVUIMM_8, RA}},
3752{"evldhx", VX (4, 772), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3753{"vsrab", VX (4, 772), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3754{"evldh", VX (4, 773), VX_MASK, PPCSPE, 0, {RS, EVUIMM_8, RA}},
3755{"vcmpgtsb", VXR(4, 774,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
3756{"evlhhesplatx",VX (4, 776), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3757{"vmulesb", VX (4, 776), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3758{"evlhhesplat", VX (4, 777), VX_MASK, PPCSPE, 0, {RS, EVUIMM_2, RA}},
3759{"vcfux", VX (4, 778), VX_MASK, PPCVEC, 0, {VD, VB, UIMM}},
3760{"vcuxwfp", VX (4, 778), VX_MASK, PPCVEC, 0, {VD, VB, UIMM}},
3761{"evlhhousplatx",VX(4, 780), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3762{"vspltisb", VX (4, 780), VXVB_MASK, PPCVEC, 0, {VD, SIMM}},
3763{"vinsertb", VX (4, 781), VXUIMM4_MASK, PPCVEC3, 0, {VD, VB, UIMM4}},
3764{"evlhhousplat",VX (4, 781), VX_MASK, PPCSPE, 0, {RS, EVUIMM_2, RA}},
3765{"evlhhossplatx",VX(4, 782), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3766{"vpkpx", VX (4, 782), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3767{"evlhhossplat",VX (4, 783), VX_MASK, PPCSPE, 0, {RS, EVUIMM_2, RA}},
3768{"mullhwu", XRC(4, 392,0), X_MASK, MULHW, 0, {RT, RA, RB}},
3769{"evlwhex", VX (4, 784), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3770{"mullhwu.", XRC(4, 392,1), X_MASK, MULHW, 0, {RT, RA, RB}},
3771{"evlwhe", VX (4, 785), VX_MASK, PPCSPE, 0, {RS, EVUIMM_4, RA}},
3772{"evlwhoux", VX (4, 788), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3773{"evlwhou", VX (4, 789), VX_MASK, PPCSPE, 0, {RS, EVUIMM_4, RA}},
3774{"evlwhosx", VX (4, 790), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3775{"evlwhos", VX (4, 791), VX_MASK, PPCSPE, 0, {RS, EVUIMM_4, RA}},
3776{"maclhwu", XO (4, 396,0,0),XO_MASK, MULHW, 0, {RT, RA, RB}},
3777{"evlwwsplatx", VX (4, 792), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3778{"maclhwu.", XO (4, 396,0,1),XO_MASK, MULHW, 0, {RT, RA, RB}},
3779{"evlwwsplat", VX (4, 793), VX_MASK, PPCSPE, 0, {RS, EVUIMM_4, RA}},
3780{"evlwhsplatx", VX (4, 796), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3781{"evlwhsplat", VX (4, 797), VX_MASK, PPCSPE, 0, {RS, EVUIMM_4, RA}},
3782{"evstddx", VX (4, 800), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3783{"evstdd", VX (4, 801), VX_MASK, PPCSPE, 0, {RS, EVUIMM_8, RA}},
3784{"evstdwx", VX (4, 802), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3785{"evstdw", VX (4, 803), VX_MASK, PPCSPE, 0, {RS, EVUIMM_8, RA}},
3786{"evstdhx", VX (4, 804), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3787{"evstdh", VX (4, 805), VX_MASK, PPCSPE, 0, {RS, EVUIMM_8, RA}},
3788{"evstwhex", VX (4, 816), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3789{"evstwhe", VX (4, 817), VX_MASK, PPCSPE, 0, {RS, EVUIMM_4, RA}},
3790{"evstwhox", VX (4, 820), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3791{"evstwho", VX (4, 821), VX_MASK, PPCSPE, 0, {RS, EVUIMM_4, RA}},
3792{"evstwwex", VX (4, 824), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3793{"evstwwe", VX (4, 825), VX_MASK, PPCSPE, 0, {RS, EVUIMM_4, RA}},
3794{"evstwwox", VX (4, 828), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3795{"evstwwo", VX (4, 829), VX_MASK, PPCSPE, 0, {RS, EVUIMM_4, RA}},
3796{"vaddshs", VX (4, 832), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3797{"bcdcpsgn.", VX (4, 833), VX_MASK, PPCVEC3, 0, {VD, VA, VB}},
3798{"vminsh", VX (4, 834), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3799{"vsrah", VX (4, 836), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3800{"vcmpgtsh", VXR(4, 838,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
3801{"vmulesh", VX (4, 840), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3802{"vcfsx", VX (4, 842), VX_MASK, PPCVEC, 0, {VD, VB, UIMM}},
3803{"vcsxwfp", VX (4, 842), VX_MASK, PPCVEC, 0, {VD, VB, UIMM}},
3804{"vspltish", VX (4, 844), VXVB_MASK, PPCVEC, 0, {VD, SIMM}},
3805{"vinserth", VX (4, 845), VXUIMM4_MASK, PPCVEC3, 0, {VD, VB, UIMM4}},
3806{"vupkhpx", VX (4, 846), VXVA_MASK, PPCVEC, 0, {VD, VB}},
3807{"mullhw", XRC(4, 424,0), X_MASK, MULHW, 0, {RT, RA, RB}},
3808{"mullhw.", XRC(4, 424,1), X_MASK, MULHW, 0, {RT, RA, RB}},
3809{"maclhw", XO (4, 428,0,0),XO_MASK, MULHW, 0, {RT, RA, RB}},
3810{"maclhw.", XO (4, 428,0,1),XO_MASK, MULHW, 0, {RT, RA, RB}},
3811{"nmaclhw", XO (4, 430,0,0),XO_MASK, MULHW, 0, {RT, RA, RB}},
3812{"nmaclhw.", XO (4, 430,0,1),XO_MASK, MULHW, 0, {RT, RA, RB}},
3813{"vaddsws", VX (4, 896), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3814{"vminsw", VX (4, 898), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3815{"vsraw", VX (4, 900), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3816{"vcmpgtsw", VXR(4, 902,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
3817{"vmulesw", VX (4, 904), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3818{"vctuxs", VX (4, 906), VX_MASK, PPCVEC, 0, {VD, VB, UIMM}},
3819{"vcfpuxws", VX (4, 906), VX_MASK, PPCVEC, 0, {VD, VB, UIMM}},
3820{"vspltisw", VX (4, 908), VXVB_MASK, PPCVEC, 0, {VD, SIMM}},
3821{"vinsertw", VX (4, 909), VXUIMM4_MASK, PPCVEC3, 0, {VD, VB, UIMM4}},
3822{"maclhwsu", XO (4, 460,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3823{"maclhwsu.", XO (4, 460,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3824{"vminsd", VX (4, 962), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3825{"vsrad", VX (4, 964), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3826{"vcmpbfp", VXR(4, 966,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
3827{"vcmpgtsd", VXR(4, 967,0), VXR_MASK, PPCVEC2, 0, {VD, VA, VB}},
3828{"vctsxs", VX (4, 970), VX_MASK, PPCVEC, 0, {VD, VB, UIMM}},
3829{"vcfpsxws", VX (4, 970), VX_MASK, PPCVEC, 0, {VD, VB, UIMM}},
3830{"vinsertd", VX (4, 973), VXUIMM4_MASK, PPCVEC3, 0, {VD, VB, UIMM4}},
3831{"vupklpx", VX (4, 974), VXVA_MASK, PPCVEC, 0, {VD, VB}},
3832{"maclhws", XO (4, 492,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3833{"maclhws.", XO (4, 492,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3834{"nmaclhws", XO (4, 494,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3835{"nmaclhws.", XO (4, 494,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3836{"vsububm", VX (4,1024), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3837{"bcdadd.", VX (4,1025), VXPS_MASK, PPCVEC2, 0, {VD, VA, VB, PS}},
3838{"vavgub", VX (4,1026), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3839{"vabsdub", VX (4,1027), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3840{"evmhessf", VX (4,1027), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3841{"vand", VX (4,1028), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3842{"vcmpequb.", VXR(4, 6,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
3843{"vcmpneb.", VXR(4, 7,1), VXR_MASK, PPCVEC3, 0, {VD, VA, VB}},
62adc510
AM		 3844{"udi0fcm.", APU(4, 515,0), APU_MASK, PPC405|PPC440, 0, {URT, URA, URB}},
3845{"udi0fcm", APU(4, 515,1), APU_MASK, PPC405|PPC440, 0, {URT, URA, URB}},
14b57c7c
AM		 3846{"evmhossf", VX (4,1031), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3847{"vpmsumb", VX (4,1032), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3848{"evmheumi", VX (4,1032), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3849{"evmhesmi", VX (4,1033), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3850{"vmaxfp", VX (4,1034), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3851{"evmhesmf", VX (4,1035), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3852{"evmhoumi", VX (4,1036), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3853{"vslo", VX (4,1036), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3854{"evmhosmi", VX (4,1037), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3855{"evmhosmf", VX (4,1039), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3856{"machhwuo", XO (4, 12,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3857{"machhwuo.", XO (4, 12,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3858{"ps_merge00", XOPS(4,528,0), XOPS_MASK, PPCPS, 0, {FRT, FRA, FRB}},
3859{"ps_merge00.", XOPS(4,528,1), XOPS_MASK, PPCPS, 0, {FRT, FRA, FRB}},
3860{"evmhessfa", VX (4,1059), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3861{"evmhossfa", VX (4,1063), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3862{"evmheumia", VX (4,1064), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3863{"evmhesmia", VX (4,1065), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3864{"evmhesmfa", VX (4,1067), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3865{"evmhoumia", VX (4,1068), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3866{"evmhosmia", VX (4,1069), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3867{"evmhosmfa", VX (4,1071), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3868{"vsubuhm", VX (4,1088), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3869{"bcdsub.", VX (4,1089), VXPS_MASK, PPCVEC2, 0, {VD, VA, VB, PS}},
3870{"vavguh", VX (4,1090), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3871{"vabsduh", VX (4,1091), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3872{"vandc", VX (4,1092), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3873{"vcmpequh.", VXR(4, 70,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
62adc510
AM		 3874{"udi1fcm.", APU(4, 547,0), APU_MASK, PPC405|PPC440, 0, {URT, URA, URB}},
3875{"udi1fcm", APU(4, 547,1), APU_MASK, PPC405|PPC440, 0, {URT, URA, URB}},
14b57c7c
AM		 3876{"vcmpneh.", VXR(4, 71,1), VXR_MASK, PPCVEC3, 0, {VD, VA, VB}},
3877{"evmwhssf", VX (4,1095), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3878{"vpmsumh", VX (4,1096), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3879{"evmwlumi", VX (4,1096), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3880{"vminfp", VX (4,1098), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3881{"evmwhumi", VX (4,1100), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3882{"vsro", VX (4,1100), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3883{"evmwhsmi", VX (4,1101), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3884{"vpkudum", VX (4,1102), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3885{"evmwhsmf", VX (4,1103), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3886{"evmwssf", VX (4,1107), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3887{"machhwo", XO (4, 44,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3888{"evmwumi", VX (4,1112), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3889{"machhwo.", XO (4, 44,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3890{"evmwsmi", VX (4,1113), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3891{"evmwsmf", VX (4,1115), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3892{"nmachhwo", XO (4, 46,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3893{"nmachhwo.", XO (4, 46,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3894{"ps_merge01", XOPS(4,560,0), XOPS_MASK, PPCPS, 0, {FRT, FRA, FRB}},
3895{"ps_merge01.", XOPS(4,560,1), XOPS_MASK, PPCPS, 0, {FRT, FRA, FRB}},
3896{"evmwhssfa", VX (4,1127), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3897{"evmwlumia", VX (4,1128), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3898{"evmwhumia", VX (4,1132), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3899{"evmwhsmia", VX (4,1133), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3900{"evmwhsmfa", VX (4,1135), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3901{"evmwssfa", VX (4,1139), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3902{"evmwumia", VX (4,1144), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3903{"evmwsmia", VX (4,1145), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3904{"evmwsmfa", VX (4,1147), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3905{"vsubuwm", VX (4,1152), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3906{"bcdus.", VX (4,1153), VX_MASK, PPCVEC3, 0, {VD, VA, VB}},
3907{"vavguw", VX (4,1154), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3908{"vabsduw", VX (4,1155), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3909{"vmr", VX (4,1156), VX_MASK, PPCVEC, 0, {VD, VA, VBA}},
3910{"vor", VX (4,1156), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3911{"vcmpnew.", VXR(4, 135,1), VXR_MASK, PPCVEC3, 0, {VD, VA, VB}},
3912{"vpmsumw", VX (4,1160), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3913{"vcmpequw.", VXR(4, 134,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
62adc510
AM		 3914{"udi2fcm.", APU(4, 579,0), APU_MASK, PPC405|PPC440, 0, {URT, URA, URB}},
3915{"udi2fcm", APU(4, 579,1), APU_MASK, PPC405|PPC440, 0, {URT, URA, URB}},
14b57c7c
AM		 3916{"machhwsuo", XO (4, 76,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3917{"machhwsuo.", XO (4, 76,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3918{"ps_merge10", XOPS(4,592,0), XOPS_MASK, PPCPS, 0, {FRT, FRA, FRB}},
3919{"ps_merge10.", XOPS(4,592,1), XOPS_MASK, PPCPS, 0, {FRT, FRA, FRB}},
3920{"vsubudm", VX (4,1216), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3921{"evaddusiaaw", VX (4,1216), VX_MASK, PPCSPE, 0, {RS, RA}},
3922{"bcds.", VX (4,1217), VXPS_MASK, PPCVEC3, 0, {VD, VA, VB, PS}},
3923{"evaddssiaaw", VX (4,1217), VX_MASK, PPCSPE, 0, {RS, RA}},
3924{"evsubfusiaaw",VX (4,1218), VX_MASK, PPCSPE, 0, {RS, RA}},
3925{"evsubfssiaaw",VX (4,1219), VX_MASK, PPCSPE, 0, {RS, RA}},
3926{"evmra", VX (4,1220), VX_MASK, PPCSPE, 0, {RS, RA}},
3927{"vxor", VX (4,1220), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3928{"evdivws", VX (4,1222), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3929{"vcmpeqfp.", VXR(4, 198,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
62adc510 3930{"udi3fcm.", APU(4, 611,0), APU_MASK, PPC405|PPC440, 0, {URT, URA, URB}},
14b57c7c 3931{"vcmpequd.", VXR(4, 199,1), VXR_MASK, PPCVEC2, 0, {VD, VA, VB}},
62adc510 3932{"udi3fcm", APU(4, 611,1), APU_MASK, PPC405|PPC440, 0, {URT, URA, URB}},
14b57c7c
AM		 3933{"evdivwu", VX (4,1223), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3934{"vpmsumd", VX (4,1224), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3935{"evaddumiaaw", VX (4,1224), VX_MASK, PPCSPE, 0, {RS, RA}},
3936{"evaddsmiaaw", VX (4,1225), VX_MASK, PPCSPE, 0, {RS, RA}},
3937{"evsubfumiaaw",VX (4,1226), VX_MASK, PPCSPE, 0, {RS, RA}},
3938{"evsubfsmiaaw",VX (4,1227), VX_MASK, PPCSPE, 0, {RS, RA}},
3939{"vpkudus", VX (4,1230), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3940{"machhwso", XO (4, 108,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3941{"machhwso.", XO (4, 108,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3942{"nmachhwso", XO (4, 110,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3943{"nmachhwso.", XO (4, 110,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3944{"ps_merge11", XOPS(4,624,0), XOPS_MASK, PPCPS, 0, {FRT, FRA, FRB}},
3945{"ps_merge11.", XOPS(4,624,1), XOPS_MASK, PPCPS, 0, {FRT, FRA, FRB}},
3946{"vsubuqm", VX (4,1280), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3947{"evmheusiaaw", VX (4,1280), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3948{"bcdtrunc.", VX (4,1281), VXPS_MASK, PPCVEC3, 0, {VD, VA, VB, PS}},
3949{"evmhessiaaw", VX (4,1281), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3950{"vavgsb", VX (4,1282), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3951{"evmhessfaaw", VX (4,1283), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3952{"evmhousiaaw", VX (4,1284), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3953{"vnot", VX (4,1284), VX_MASK, PPCVEC, 0, {VD, VA, VBA}},
3954{"vnor", VX (4,1284), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3955{"evmhossiaaw", VX (4,1285), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
62adc510
AM		 3956{"udi4fcm.", APU(4, 643,0), APU_MASK, PPC405|PPC440, 0, {URT, URA, URB}},
3957{"udi4fcm", APU(4, 643,1), APU_MASK, PPC405|PPC440, 0, {URT, URA, URB}},
14b57c7c
AM		 3958{"vcmpnezb.", VXR(4, 263,1), VXR_MASK, PPCVEC3, 0, {VD, VA, VB}},
3959{"evmhossfaaw", VX (4,1287), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3960{"evmheumiaaw", VX (4,1288), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3961{"vcipher", VX (4,1288), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3962{"vcipherlast", VX (4,1289), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3963{"evmhesmiaaw", VX (4,1289), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3964{"evmhesmfaaw", VX (4,1291), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3965{"vgbbd", VX (4,1292), VXVA_MASK, PPCVEC2, 0, {VD, VB}},
3966{"evmhoumiaaw", VX (4,1292), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3967{"evmhosmiaaw", VX (4,1293), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3968{"evmhosmfaaw", VX (4,1295), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3969{"macchwuo", XO (4, 140,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3970{"macchwuo.", XO (4, 140,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3971{"evmhegumiaa", VX (4,1320), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3972{"evmhegsmiaa", VX (4,1321), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3973{"evmhegsmfaa", VX (4,1323), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3974{"evmhogumiaa", VX (4,1324), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3975{"evmhogsmiaa", VX (4,1325), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3976{"evmhogsmfaa", VX (4,1327), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3977{"vsubcuq", VX (4,1344), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3978{"evmwlusiaaw", VX (4,1344), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3979{"bcdutrunc.", VX (4,1345), VX_MASK, PPCVEC3, 0, {VD, VA, VB}},
3980{"evmwlssiaaw", VX (4,1345), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3981{"vavgsh", VX (4,1346), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3982{"vorc", VX (4,1348), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
62adc510
AM		 3983{"udi5fcm.", APU(4, 675,0), APU_MASK, PPC405|PPC440, 0, {URT, URA, URB}},
3984{"udi5fcm", APU(4, 675,1), APU_MASK, PPC405|PPC440, 0, {URT, URA, URB}},
14b57c7c
AM		 3985{"vcmpnezh.", VXR(4, 327,1), VXR_MASK, PPCVEC3, 0, {VD, VA, VB}},
3986{"vncipher", VX (4,1352), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3987{"evmwlumiaaw", VX (4,1352), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3988{"vncipherlast",VX (4,1353), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3989{"evmwlsmiaaw", VX (4,1353), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3990{"vbpermq", VX (4,1356), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3991{"vpksdus", VX (4,1358), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3992{"evmwssfaa", VX (4,1363), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3993{"macchwo", XO (4, 172,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3994{"evmwumiaa", VX (4,1368), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3995{"macchwo.", XO (4, 172,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3996{"evmwsmiaa", VX (4,1369), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3997{"evmwsmfaa", VX (4,1371), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3998{"nmacchwo", XO (4, 174,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3999{"nmacchwo.", XO (4, 174,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
4000{"evmheusianw", VX (4,1408), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
4001{"vsubcuw", VX (4,1408), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
4002{"evmhessianw", VX (4,1409), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
4003{"bcdctsq.", VXVA(4,1409,0), VXVA_MASK, PPCVEC3, 0, {VD, VB}},
4004{"bcdcfsq.", VXVA(4,1409,2), VXVAPS_MASK, PPCVEC3, 0, {VD, VB, PS}},
4005{"bcdctz.", VXVA(4,1409,4), VXVAPS_MASK, PPCVEC3, 0, {VD, VB, PS}},
4006{"bcdctn.", VXVA(4,1409,5), VXVA_MASK, PPCVEC3, 0, {VD, VB}},
4007{"bcdcfz.", VXVA(4,1409,6), VXVAPS_MASK, PPCVEC3, 0, {VD, VB, PS}},
4008{"bcdcfn.", VXVA(4,1409,7), VXVAPS_MASK, PPCVEC3, 0, {VD, VB, PS}},
4009{"bcdsetsgn.", VXVA(4,1409,31), VXVAPS_MASK, PPCVEC3, 0, {VD, VB, PS}},
4010{"vavgsw", VX (4,1410), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
4011{"evmhessfanw", VX (4,1411), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
4012{"vnand", VX (4,1412), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
4013{"evmhousianw", VX (4,1412), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
4014{"evmhossianw", VX (4,1413), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
62adc510
AM		 4015{"udi6fcm.", APU(4, 707,0), APU_MASK, PPC405|PPC440, 0, {URT, URA, URB}},
4016{"udi6fcm", APU(4, 707,1), APU_MASK, PPC405|PPC440, 0, {URT, URA, URB}},
14b57c7c
AM		 4017{"vcmpnezw.", VXR(4, 391,1), VXR_MASK, PPCVEC3, 0, {VD, VA, VB}},
4018{"evmhossfanw", VX (4,1415), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
4019{"evmheumianw", VX (4,1416), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
4020{"evmhesmianw", VX (4,1417), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
4021{"evmhesmfanw", VX (4,1419), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
4022{"evmhoumianw", VX (4,1420), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
4023{"evmhosmianw", VX (4,1421), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
4024{"evmhosmfanw", VX (4,1423), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
4025{"macchwsuo", XO (4, 204,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
4026{"macchwsuo.", XO (4, 204,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
4027{"evmhegumian", VX (4,1448), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
4028{"evmhegsmian", VX (4,1449), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
4029{"evmhegsmfan", VX (4,1451), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
4030{"evmhogumian", VX (4,1452), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
4031{"evmhogsmian", VX (4,1453), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
4032{"evmhogsmfan", VX (4,1455), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
4033{"evmwlusianw", VX (4,1472), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
4034{"bcdsr.", VX (4,1473), VXPS_MASK, PPCVEC3, 0, {VD, VA, VB, PS}},
4035{"evmwlssianw", VX (4,1473), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
4036{"vsld", VX (4,1476), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
4037{"vcmpgefp.", VXR(4, 454,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
62adc510
AM		 4038{"udi7fcm.", APU(4, 739,0), APU_MASK, PPC405|PPC440, 0, {URT, URA, URB}},
4039{"udi7fcm", APU(4, 739,1), APU_MASK, PPC405|PPC440, 0, {URT, URA, URB}},
14b57c7c
AM		 4040{"vsbox", VX (4,1480), VXVB_MASK, PPCVEC2, 0, {VD, VA}},
4041{"evmwlumianw", VX (4,1480), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
4042{"evmwlsmianw", VX (4,1481), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
4043{"vbpermd", VX (4,1484), VX_MASK, PPCVEC3, 0, {VD, VA, VB}},
4044{"vpksdss", VX (4,1486), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
4045{"evmwssfan", VX (4,1491), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
4046{"macchwso", XO (4, 236,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
4047{"evmwumian", VX (4,1496), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
4048{"macchwso.", XO (4, 236,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
4049{"evmwsmian", VX (4,1497), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
4050{"evmwsmfan", VX (4,1499), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
4051{"nmacchwso", XO (4, 238,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
4052{"nmacchwso.", XO (4, 238,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
4053{"vsububs", VX (4,1536), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
4054{"vclzlsbb", VXVA(4,1538,0), VXVA_MASK, PPCVEC3, 0, {RT, VB}},
4055{"vctzlsbb", VXVA(4,1538,1), VXVA_MASK, PPCVEC3, 0, {RT, VB}},
4056{"vnegw", VXVA(4,1538,6), VXVA_MASK, PPCVEC3, 0, {VD, VB}},
4057{"vnegd", VXVA(4,1538,7), VXVA_MASK, PPCVEC3, 0, {VD, VB}},
4058{"vprtybw", VXVA(4,1538,8), VXVA_MASK, PPCVEC3, 0, {VD, VB}},
4059{"vprtybd", VXVA(4,1538,9), VXVA_MASK, PPCVEC3, 0, {VD, VB}},
4060{"vprtybq", VXVA(4,1538,10), VXVA_MASK, PPCVEC3, 0, {VD, VB}},
4061{"vextsb2w", VXVA(4,1538,16), VXVA_MASK, PPCVEC3, 0, {VD, VB}},
4062{"vextsh2w", VXVA(4,1538,17), VXVA_MASK, PPCVEC3, 0, {VD, VB}},
4063{"vextsb2d", VXVA(4,1538,24), VXVA_MASK, PPCVEC3, 0, {VD, VB}},
4064{"vextsh2d", VXVA(4,1538,25), VXVA_MASK, PPCVEC3, 0, {VD, VB}},
4065{"vextsw2d", VXVA(4,1538,26), VXVA_MASK, PPCVEC3, 0, {VD, VB}},
4066{"vctzb", VXVA(4,1538,28), VXVA_MASK, PPCVEC3, 0, {VD, VB}},
4067{"vctzh", VXVA(4,1538,29), VXVA_MASK, PPCVEC3, 0, {VD, VB}},
4068{"vctzw", VXVA(4,1538,30), VXVA_MASK, PPCVEC3, 0, {VD, VB}},
4069{"vctzd", VXVA(4,1538,31), VXVA_MASK, PPCVEC3, 0, {VD, VB}},
4070{"mfvscr", VX (4,1540), VXVAVB_MASK, PPCVEC, 0, {VD}},
4071{"vcmpgtub.", VXR(4, 518,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
62adc510
AM		 4072{"udi8fcm.", APU(4, 771,0), APU_MASK, PPC440, 0, {URT, URA, URB}},
4073{"udi8fcm", APU(4, 771,1), APU_MASK, PPC440, 0, {URT, URA, URB}},
14b57c7c
AM		 4074{"vsum4ubs", VX (4,1544), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
4075{"vextublx", VX (4,1549), VX_MASK, PPCVEC3, 0, {RT, RA, VB}},
4076{"vsubuhs", VX (4,1600), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
4077{"mtvscr", VX (4,1604), VXVDVA_MASK, PPCVEC, 0, {VB}},
4078{"vcmpgtuh.", VXR(4, 582,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
4079{"vsum4shs", VX (4,1608), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
62adc510
AM		 4080{"udi9fcm.", APU(4, 804,0), APU_MASK, PPC440, 0, {URT, URA, URB}},
4081{"udi9fcm", APU(4, 804,1), APU_MASK, PPC440, 0, {URT, URA, URB}},
14b57c7c
AM		 4082{"vextuhlx", VX (4,1613), VX_MASK, PPCVEC3, 0, {RT, RA, VB}},
4083{"vupkhsw", VX (4,1614), VXVA_MASK, PPCVEC2, 0, {VD, VB}},
4084{"vsubuws", VX (4,1664), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
4085{"vshasigmaw", VX (4,1666), VX_MASK, PPCVEC2, 0, {VD, VA, ST, SIX}},
4086{"veqv", VX (4,1668), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
4087{"vcmpgtuw.", VXR(4, 646,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
62adc510
AM		 4088{"udi10fcm.", APU(4, 835,0), APU_MASK, PPC440, 0, {URT, URA, URB}},
4089{"udi10fcm", APU(4, 835,1), APU_MASK, PPC440, 0, {URT, URA, URB}},
14b57c7c
AM		 4090{"vsum2sws", VX (4,1672), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
4091{"vmrgow", VX (4,1676), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
4092{"vextuwlx", VX (4,1677), VX_MASK, PPCVEC3, 0, {RT, RA, VB}},
4093{"vshasigmad", VX (4,1730), VX_MASK, PPCVEC2, 0, {VD, VA, ST, SIX}},
4094{"vsrd", VX (4,1732), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
4095{"vcmpgtfp.", VXR(4, 710,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
62adc510 4096{"udi11fcm.", APU(4, 867,0), APU_MASK, PPC440, 0, {URT, URA, URB}},
14b57c7c 4097{"vcmpgtud.", VXR(4, 711,1), VXR_MASK, PPCVEC2, 0, {VD, VA, VB}},
62adc510 4098{"udi11fcm", APU(4, 867,1), APU_MASK, PPC440, 0, {URT, URA, URB}},
14b57c7c
AM		 4099{"vupklsw", VX (4,1742), VXVA_MASK, PPCVEC2, 0, {VD, VB}},
4100{"vsubsbs", VX (4,1792), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
4101{"vclzb", VX (4,1794), VXVA_MASK, PPCVEC2, 0, {VD, VB}},
4102{"vpopcntb", VX (4,1795), VXVA_MASK, PPCVEC2, 0, {VD, VB}},
4103{"vsrv", VX (4,1796), VX_MASK, PPCVEC3, 0, {VD, VA, VB}},
4104{"vcmpgtsb.", VXR(4, 774,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
62adc510
AM		 4105{"udi12fcm.", APU(4, 899,0), APU_MASK, PPC440, 0, {URT, URA, URB}},
4106{"udi12fcm", APU(4, 899,1), APU_MASK, PPC440, 0, {URT, URA, URB}},
14b57c7c
AM		 4107{"vsum4sbs", VX (4,1800), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
4108{"vextubrx", VX (4,1805), VX_MASK, PPCVEC3, 0, {RT, RA, VB}},
4109{"maclhwuo", XO (4, 396,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
4110{"maclhwuo.", XO (4, 396,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
4111{"vsubshs", VX (4,1856), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
4112{"vclzh", VX (4,1858), VXVA_MASK, PPCVEC2, 0, {VD, VB}},
4113{"vpopcnth", VX (4,1859), VXVA_MASK, PPCVEC2, 0, {VD, VB}},
4114{"vslv", VX (4,1860), VX_MASK, PPCVEC3, 0, {VD, VA, VB}},
4115{"vcmpgtsh.", VXR(4, 838,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
4116{"vextuhrx", VX (4,1869), VX_MASK, PPCVEC3, 0, {RT, RA, VB}},
62adc510
AM		 4117{"udi13fcm.", APU(4, 931,0), APU_MASK, PPC440, 0, {URT, URA, URB}},
4118{"udi13fcm", APU(4, 931,1), APU_MASK, PPC440, 0, {URT, URA, URB}},
14b57c7c
AM		 4119{"maclhwo", XO (4, 428,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
4120{"maclhwo.", XO (4, 428,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
4121{"nmaclhwo", XO (4, 430,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
4122{"nmaclhwo.", XO (4, 430,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
4123{"vsubsws", VX (4,1920), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
4124{"vclzw", VX (4,1922), VXVA_MASK, PPCVEC2, 0, {VD, VB}},
4125{"vpopcntw", VX (4,1923), VXVA_MASK, PPCVEC2, 0, {VD, VB}},
4126{"vcmpgtsw.", VXR(4, 902,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
62adc510
AM		 4127{"udi14fcm.", APU(4, 963,0), APU_MASK, PPC440, 0, {URT, URA, URB}},
4128{"udi14fcm", APU(4, 963,1), APU_MASK, PPC440, 0, {URT, URA, URB}},
14b57c7c
AM		 4129{"vsumsws", VX (4,1928), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
4130{"vmrgew", VX (4,1932), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
4131{"vextuwrx", VX (4,1933), VX_MASK, PPCVEC3, 0, {RT, RA, VB}},
4132{"maclhwsuo", XO (4, 460,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
4133{"maclhwsuo.", XO (4, 460,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
4134{"vclzd", VX (4,1986), VXVA_MASK, PPCVEC2, 0, {VD, VB}},
4135{"vpopcntd", VX (4,1987), VXVA_MASK, PPCVEC2, 0, {VD, VB}},
4136{"vcmpbfp.", VXR(4, 966,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
62adc510 4137{"udi15fcm.", APU(4, 995,0), APU_MASK, PPC440, 0, {URT, URA, URB}},
14b57c7c 4138{"vcmpgtsd.", VXR(4, 967,1), VXR_MASK, PPCVEC2, 0, {VD, VA, VB}},
62adc510 4139{"udi15fcm", APU(4, 995,1), APU_MASK, PPC440, 0, {URT, URA, URB}},
14b57c7c
AM		 4140{"maclhwso", XO (4, 492,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
4141{"maclhwso.", XO (4, 492,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
4142{"nmaclhwso", XO (4, 494,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
4143{"nmaclhwso.", XO (4, 494,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
4144{"dcbz_l", X (4,1014), XRT_MASK, PPCPS, 0, {RA, RB}},
4145
4146{"mulli", OP(7), OP_MASK, PPCCOM, PPCVLE, {RT, RA, SI}},
4147{"muli", OP(7), OP_MASK, PWRCOM, PPCVLE, {RT, RA, SI}},
4148
4149{"subfic", OP(8), OP_MASK, PPCCOM, PPCVLE, {RT, RA, SI}},
4150{"sfi", OP(8), OP_MASK, PWRCOM, PPCVLE, {RT, RA, SI}},
4151
4152{"dozi", OP(9), OP_MASK, M601, PPCVLE, {RT, RA, SI}},
4153
4154{"cmplwi", OPL(10,0), OPL_MASK, PPCCOM, PPCVLE, {OBF, RA, UISIGNOPT}},
4155{"cmpldi", OPL(10,1), OPL_MASK, PPC64, PPCVLE, {OBF, RA, UISIGNOPT}},
a5721ba2 4156{"cmpli", OP(10), OP_MASK, PPC, PPCVLE, {BF, L32OPT, RA, UISIGNOPT}},
14b57c7c
AM		 4157{"cmpli", OP(10), OP_MASK, PWRCOM, PPC|PPCVLE, {BF, RA, UISIGNOPT}},
4158
4159{"cmpwi", OPL(11,0), OPL_MASK, PPCCOM, PPCVLE, {OBF, RA, SI}},
4160{"cmpdi", OPL(11,1), OPL_MASK, PPC64, PPCVLE, {OBF, RA, SI}},
a5721ba2 4161{"cmpi", OP(11), OP_MASK, PPC, PPCVLE, {BF, L32OPT, RA, SI}},
14b57c7c
AM		 4162{"cmpi", OP(11), OP_MASK, PWRCOM, PPC|PPCVLE, {BF, RA, SI}},
4163
4164{"addic", OP(12), OP_MASK, PPCCOM, PPCVLE, {RT, RA, SI}},
4165{"ai", OP(12), OP_MASK, PWRCOM, PPCVLE, {RT, RA, SI}},
4166{"subic", OP(12), OP_MASK, PPCCOM, PPCVLE, {RT, RA, NSI}},
4167
4168{"addic.", OP(13), OP_MASK, PPCCOM, PPCVLE, {RT, RA, SI}},
4169{"ai.", OP(13), OP_MASK, PWRCOM, PPCVLE, {RT, RA, SI}},
4170{"subic.", OP(13), OP_MASK, PPCCOM, PPCVLE, {RT, RA, NSI}},
4171
4172{"li", OP(14), DRA_MASK, PPCCOM, PPCVLE, {RT, SI}},
4173{"lil", OP(14), DRA_MASK, PWRCOM, PPCVLE, {RT, SI}},
4174{"addi", OP(14), OP_MASK, PPCCOM, PPCVLE, {RT, RA0, SI}},
4175{"cal", OP(14), OP_MASK, PWRCOM, PPCVLE, {RT, D, RA0}},
4176{"subi", OP(14), OP_MASK, PPCCOM, PPCVLE, {RT, RA0, NSI}},
4177{"la", OP(14), OP_MASK, PPCCOM, PPCVLE, {RT, D, RA0}},
4178
4179{"lis", OP(15), DRA_MASK, PPCCOM, PPCVLE, {RT, SISIGNOPT}},
4180{"liu", OP(15), DRA_MASK, PWRCOM, PPCVLE, {RT, SISIGNOPT}},
4181{"addis", OP(15), OP_MASK, PPCCOM, PPCVLE, {RT, RA0, SISIGNOPT}},
4182{"cau", OP(15), OP_MASK, PWRCOM, PPCVLE, {RT, RA0, SISIGNOPT}},
4183{"subis", OP(15), OP_MASK, PPCCOM, PPCVLE, {RT, RA0, NSISIGNOPT}},
4184
4185{"bdnz-", BBO(16,BODNZ,0,0), BBOATBI_MASK, PPCCOM, PPCVLE, {BDM}},
4186{"bdnz+", BBO(16,BODNZ,0,0), BBOATBI_MASK, PPCCOM, PPCVLE, {BDP}},
4187{"bdnz", BBO(16,BODNZ,0,0), BBOATBI_MASK, PPCCOM, PPCVLE, {BD}},
4188{"bdn", BBO(16,BODNZ,0,0), BBOATBI_MASK, PWRCOM, PPCVLE, {BD}},
4189{"bdnzl-", BBO(16,BODNZ,0,1), BBOATBI_MASK, PPCCOM, PPCVLE, {BDM}},
4190{"bdnzl+", BBO(16,BODNZ,0,1), BBOATBI_MASK, PPCCOM, PPCVLE, {BDP}},
4191{"bdnzl", BBO(16,BODNZ,0,1), BBOATBI_MASK, PPCCOM, PPCVLE, {BD}},
4192{"bdnl", BBO(16,BODNZ,0,1), BBOATBI_MASK, PWRCOM, PPCVLE, {BD}},
4193{"bdnza-", BBO(16,BODNZ,1,0), BBOATBI_MASK, PPCCOM, PPCVLE, {BDMA}},
4194{"bdnza+", BBO(16,BODNZ,1,0), BBOATBI_MASK, PPCCOM, PPCVLE, {BDPA}},
4195{"bdnza", BBO(16,BODNZ,1,0), BBOATBI_MASK, PPCCOM, PPCVLE, {BDA}},
4196{"bdna", BBO(16,BODNZ,1,0), BBOATBI_MASK, PWRCOM, PPCVLE, {BDA}},
4197{"bdnzla-", BBO(16,BODNZ,1,1), BBOATBI_MASK, PPCCOM, PPCVLE, {BDMA}},
4198{"bdnzla+", BBO(16,BODNZ,1,1), BBOATBI_MASK, PPCCOM, PPCVLE, {BDPA}},
4199{"bdnzla", BBO(16,BODNZ,1,1), BBOATBI_MASK, PPCCOM, PPCVLE, {BDA}},
4200{"bdnla", BBO(16,BODNZ,1,1), BBOATBI_MASK, PWRCOM, PPCVLE, {BDA}},
4201{"bdz-", BBO(16,BODZ,0,0), BBOATBI_MASK, PPCCOM, PPCVLE, {BDM}},
4202{"bdz+", BBO(16,BODZ,0,0), BBOATBI_MASK, PPCCOM, PPCVLE, {BDP}},
4203{"bdz", BBO(16,BODZ,0,0), BBOATBI_MASK, COM, PPCVLE, {BD}},
4204{"bdzl-", BBO(16,BODZ,0,1), BBOATBI_MASK, PPCCOM, PPCVLE, {BDM}},
4205{"bdzl+", BBO(16,BODZ,0,1), BBOATBI_MASK, PPCCOM, PPCVLE, {BDP}},
4206{"bdzl", BBO(16,BODZ,0,1), BBOATBI_MASK, COM, PPCVLE, {BD}},
4207{"bdza-", BBO(16,BODZ,1,0), BBOATBI_MASK, PPCCOM, PPCVLE, {BDMA}},
4208{"bdza+", BBO(16,BODZ,1,0), BBOATBI_MASK, PPCCOM, PPCVLE, {BDPA}},
4209{"bdza", BBO(16,BODZ,1,0), BBOATBI_MASK, COM, PPCVLE, {BDA}},
4210{"bdzla-", BBO(16,BODZ,1,1), BBOATBI_MASK, PPCCOM, PPCVLE, {BDMA}},
4211{"bdzla+", BBO(16,BODZ,1,1), BBOATBI_MASK, PPCCOM, PPCVLE, {BDPA}},
4212{"bdzla", BBO(16,BODZ,1,1), BBOATBI_MASK, COM, PPCVLE, {BDA}},
4213
4214{"bge-", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}},
4215{"bge+", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}},
4216{"bge", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, COM, PPCVLE, {CR, BD}},
4217{"bnl-", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}},
4218{"bnl+", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}},
4219{"bnl", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, COM, PPCVLE, {CR, BD}},
4220{"bgel-", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}},
4221{"bgel+", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}},
4222{"bgel", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, COM, PPCVLE, {CR, BD}},
4223{"bnll-", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}},
4224{"bnll+", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}},
4225{"bnll", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, COM, PPCVLE, {CR, BD}},
4226{"bgea-", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}},
4227{"bgea+", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}},
4228{"bgea", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}},
4229{"bnla-", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}},
4230{"bnla+", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}},
4231{"bnla", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}},
4232{"bgela-", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}},
4233{"bgela+", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}},
4234{"bgela", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}},
4235{"bnlla-", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}},
4236{"bnlla+", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}},
4237{"bnlla", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}},
4238{"ble-", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}},
4239{"ble+", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}},
4240{"ble", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, COM, PPCVLE, {CR, BD}},
4241{"bng-", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}},
4242{"bng+", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}},
4243{"bng", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, COM, PPCVLE, {CR, BD}},
4244{"blel-", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}},
4245{"blel+", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}},
4246{"blel", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, COM, PPCVLE, {CR, BD}},
4247{"bngl-", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}},
4248{"bngl+", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}},
4249{"bngl", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, COM, PPCVLE, {CR, BD}},
4250{"blea-", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}},
4251{"blea+", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}},
4252{"blea", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}},
4253{"bnga-", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}},
4254{"bnga+", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}},
4255{"bnga", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}},
4256{"blela-", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}},
4257{"blela+", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}},
4258{"blela", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}},
4259{"bngla-", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}},
4260{"bngla+", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}},
4261{"bngla", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}},
4262{"bne-", BBOCB(16,BOF,CBEQ,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}},
4263{"bne+", BBOCB(16,BOF,CBEQ,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}},
4264{"bne", BBOCB(16,BOF,CBEQ,0,0), BBOATCB_MASK, COM, PPCVLE, {CR, BD}},
4265{"bnel-", BBOCB(16,BOF,CBEQ,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}},
4266{"bnel+", BBOCB(16,BOF,CBEQ,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}},
4267{"bnel", BBOCB(16,BOF,CBEQ,0,1), BBOATCB_MASK, COM, PPCVLE, {CR, BD}},
4268{"bnea-", BBOCB(16,BOF,CBEQ,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}},
4269{"bnea+", BBOCB(16,BOF,CBEQ,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}},
4270{"bnea", BBOCB(16,BOF,CBEQ,1,0), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}},
4271{"bnela-", BBOCB(16,BOF,CBEQ,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}},
4272{"bnela+", BBOCB(16,BOF,CBEQ,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}},
4273{"bnela", BBOCB(16,BOF,CBEQ,1,1), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}},
4274{"bns-", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}},
4275{"bns+", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}},
4276{"bns", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, COM, PPCVLE, {CR, BD}},
4277{"bnu-", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}},
4278{"bnu+", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}},
4279{"bnu", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BD}},
4280{"bnsl-", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}},
4281{"bnsl+", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}},
4282{"bnsl", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, COM, PPCVLE, {CR, BD}},
4283{"bnul-", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}},
4284{"bnul+", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}},
4285{"bnul", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BD}},
4286{"bnsa-", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}},
4287{"bnsa+", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}},
4288{"bnsa", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}},
4289{"bnua-", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}},
4290{"bnua+", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}},
4291{"bnua", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDA}},
4292{"bnsla-", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}},
4293{"bnsla+", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}},
4294{"bnsla", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}},
4295{"bnula-", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}},
4296{"bnula+", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}},
4297{"bnula", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDA}},
4298
4299{"blt-", BBOCB(16,BOT,CBLT,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}},
4300{"blt+", BBOCB(16,BOT,CBLT,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}},
4301{"blt", BBOCB(16,BOT,CBLT,0,0), BBOATCB_MASK, COM, PPCVLE, {CR, BD}},
4302{"bltl-", BBOCB(16,BOT,CBLT,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}},
4303{"bltl+", BBOCB(16,BOT,CBLT,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}},
4304{"bltl", BBOCB(16,BOT,CBLT,0,1), BBOATCB_MASK, COM, PPCVLE, {CR, BD}},
4305{"blta-", BBOCB(16,BOT,CBLT,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}},
4306{"blta+", BBOCB(16,BOT,CBLT,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}},
4307{"blta", BBOCB(16,BOT,CBLT,1,0), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}},
4308{"bltla-", BBOCB(16,BOT,CBLT,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}},
4309{"bltla+", BBOCB(16,BOT,CBLT,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}},
4310{"bltla", BBOCB(16,BOT,CBLT,1,1), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}},
4311{"bgt-", BBOCB(16,BOT,CBGT,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}},
4312{"bgt+", BBOCB(16,BOT,CBGT,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}},
4313{"bgt", BBOCB(16,BOT,CBGT,0,0), BBOATCB_MASK, COM, PPCVLE, {CR, BD}},
4314{"bgtl-", BBOCB(16,BOT,CBGT,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}},
4315{"bgtl+", BBOCB(16,BOT,CBGT,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}},
4316{"bgtl", BBOCB(16,BOT,CBGT,0,1), BBOATCB_MASK, COM, PPCVLE, {CR, BD}},
4317{"bgta-", BBOCB(16,BOT,CBGT,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}},
4318{"bgta+", BBOCB(16,BOT,CBGT,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}},
4319{"bgta", BBOCB(16,BOT,CBGT,1,0), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}},
4320{"bgtla-", BBOCB(16,BOT,CBGT,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}},
4321{"bgtla+", BBOCB(16,BOT,CBGT,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}},
4322{"bgtla", BBOCB(16,BOT,CBGT,1,1), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}},
4323{"beq-", BBOCB(16,BOT,CBEQ,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}},
4324{"beq+", BBOCB(16,BOT,CBEQ,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}},
4325{"beq", BBOCB(16,BOT,CBEQ,0,0), BBOATCB_MASK, COM, PPCVLE, {CR, BD}},
4326{"beql-", BBOCB(16,BOT,CBEQ,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}},
4327{"beql+", BBOCB(16,BOT,CBEQ,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}},
4328{"beql", BBOCB(16,BOT,CBEQ,0,1), BBOATCB_MASK, COM, PPCVLE, {CR, BD}},
4329{"beqa-", BBOCB(16,BOT,CBEQ,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}},
4330{"beqa+", BBOCB(16,BOT,CBEQ,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}},
4331{"beqa", BBOCB(16,BOT,CBEQ,1,0), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}},
4332{"beqla-", BBOCB(16,BOT,CBEQ,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}},
4333{"beqla+", BBOCB(16,BOT,CBEQ,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}},
4334{"beqla", BBOCB(16,BOT,CBEQ,1,1), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}},
4335{"bso-", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}},
4336{"bso+", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}},
4337{"bso", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, COM, PPCVLE, {CR, BD}},
4338{"bun-", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}},
4339{"bun+", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}},
4340{"bun", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BD}},
4341{"bsol-", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}},
4342{"bsol+", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}},
4343{"bsol", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, COM, PPCVLE, {CR, BD}},
4344{"bunl-", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}},
4345{"bunl+", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}},
4346{"bunl", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BD}},
4347{"bsoa-", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}},
4348{"bsoa+", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}},
4349{"bsoa", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}},
4350{"buna-", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}},
4351{"buna+", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}},
4352{"buna", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDA}},
4353{"bsola-", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}},
4354{"bsola+", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}},
4355{"bsola", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}},
4356{"bunla-", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}},
4357{"bunla+", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}},
4358{"bunla", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDA}},
4359
4360{"bdnzf-", BBO(16,BODNZF,0,0), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDM}},
4361{"bdnzf+", BBO(16,BODNZF,0,0), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDP}},
4362{"bdnzf", BBO(16,BODNZF,0,0), BBOY_MASK, PPCCOM, PPCVLE, {BI, BD}},
4363{"bdnzfl-", BBO(16,BODNZF,0,1), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDM}},
4364{"bdnzfl+", BBO(16,BODNZF,0,1), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDP}},
4365{"bdnzfl", BBO(16,BODNZF,0,1), BBOY_MASK, PPCCOM, PPCVLE, {BI, BD}},
4366{"bdnzfa-", BBO(16,BODNZF,1,0), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDMA}},
4367{"bdnzfa+", BBO(16,BODNZF,1,0), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDPA}},
4368{"bdnzfa", BBO(16,BODNZF,1,0), BBOY_MASK, PPCCOM, PPCVLE, {BI, BDA}},
4369{"bdnzfla-", BBO(16,BODNZF,1,1), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDMA}},
4370{"bdnzfla+", BBO(16,BODNZF,1,1), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDPA}},
4371{"bdnzfla", BBO(16,BODNZF,1,1), BBOY_MASK, PPCCOM, PPCVLE, {BI, BDA}},
4372{"bdzf-", BBO(16,BODZF,0,0), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDM}},
4373{"bdzf+", BBO(16,BODZF,0,0), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDP}},
4374{"bdzf", BBO(16,BODZF,0,0), BBOY_MASK, PPCCOM, PPCVLE, {BI, BD}},
4375{"bdzfl-", BBO(16,BODZF,0,1), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDM}},
4376{"bdzfl+", BBO(16,BODZF,0,1), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDP}},
4377{"bdzfl", BBO(16,BODZF,0,1), BBOY_MASK, PPCCOM, PPCVLE, {BI, BD}},
4378{"bdzfa-", BBO(16,BODZF,1,0), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDMA}},
4379{"bdzfa+", BBO(16,BODZF,1,0), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDPA}},
4380{"bdzfa", BBO(16,BODZF,1,0), BBOY_MASK, PPCCOM, PPCVLE, {BI, BDA}},
4381{"bdzfla-", BBO(16,BODZF,1,1), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDMA}},
4382{"bdzfla+", BBO(16,BODZF,1,1), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDPA}},
4383{"bdzfla", BBO(16,BODZF,1,1), BBOY_MASK, PPCCOM, PPCVLE, {BI, BDA}},
4384
4385{"bf-", BBO(16,BOF,0,0), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDM}},
4386{"bf+", BBO(16,BOF,0,0), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDP}},
4387{"bf", BBO(16,BOF,0,0), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BD}},
4388{"bbf", BBO(16,BOF,0,0), BBOAT_MASK, PWRCOM, PPCVLE, {BI, BD}},
4389{"bfl-", BBO(16,BOF,0,1), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDM}},
4390{"bfl+", BBO(16,BOF,0,1), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDP}},
4391{"bfl", BBO(16,BOF,0,1), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BD}},
4392{"bbfl", BBO(16,BOF,0,1), BBOAT_MASK, PWRCOM, PPCVLE, {BI, BD}},
4393{"bfa-", BBO(16,BOF,1,0), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDMA}},
4394{"bfa+", BBO(16,BOF,1,0), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDPA}},
4395{"bfa", BBO(16,BOF,1,0), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDA}},
4396{"bbfa", BBO(16,BOF,1,0), BBOAT_MASK, PWRCOM, PPCVLE, {BI, BDA}},
4397{"bfla-", BBO(16,BOF,1,1), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDMA}},
4398{"bfla+", BBO(16,BOF,1,1), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDPA}},
4399{"bfla", BBO(16,BOF,1,1), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDA}},
4400{"bbfla", BBO(16,BOF,1,1), BBOAT_MASK, PWRCOM, PPCVLE, {BI, BDA}},
4401
4402{"bdnzt-", BBO(16,BODNZT,0,0), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDM}},
4403{"bdnzt+", BBO(16,BODNZT,0,0), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDP}},
4404{"bdnzt", BBO(16,BODNZT,0,0), BBOY_MASK, PPCCOM, PPCVLE, {BI, BD}},
4405{"bdnztl-", BBO(16,BODNZT,0,1), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDM}},
4406{"bdnztl+", BBO(16,BODNZT,0,1), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDP}},
4407{"bdnztl", BBO(16,BODNZT,0,1), BBOY_MASK, PPCCOM, PPCVLE, {BI, BD}},
4408{"bdnzta-", BBO(16,BODNZT,1,0), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDMA}},
4409{"bdnzta+", BBO(16,BODNZT,1,0), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDPA}},
4410{"bdnzta", BBO(16,BODNZT,1,0), BBOY_MASK, PPCCOM, PPCVLE, {BI, BDA}},
4411{"bdnztla-", BBO(16,BODNZT,1,1), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDMA}},
4412{"bdnztla+", BBO(16,BODNZT,1,1), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDPA}},
4413{"bdnztla", BBO(16,BODNZT,1,1), BBOY_MASK, PPCCOM, PPCVLE, {BI, BDA}},
4414{"bdzt-", BBO(16,BODZT,0,0), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDM}},
4415{"bdzt+", BBO(16,BODZT,0,0), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDP}},
4416{"bdzt", BBO(16,BODZT,0,0), BBOY_MASK, PPCCOM, PPCVLE, {BI, BD}},
4417{"bdztl-", BBO(16,BODZT,0,1), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDM}},
4418{"bdztl+", BBO(16,BODZT,0,1), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDP}},
4419{"bdztl", BBO(16,BODZT,0,1), BBOY_MASK, PPCCOM, PPCVLE, {BI, BD}},
4420{"bdzta-", BBO(16,BODZT,1,0), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDMA}},
4421{"bdzta+", BBO(16,BODZT,1,0), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDPA}},
4422{"bdzta", BBO(16,BODZT,1,0), BBOY_MASK, PPCCOM, PPCVLE, {BI, BDA}},
4423{"bdztla-", BBO(16,BODZT,1,1), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDMA}},
4424{"bdztla+", BBO(16,BODZT,1,1), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDPA}},
4425{"bdztla", BBO(16,BODZT,1,1), BBOY_MASK, PPCCOM, PPCVLE, {BI, BDA}},
4426
4427{"bt-", BBO(16,BOT,0,0), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDM}},
4428{"bt+", BBO(16,BOT,0,0), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDP}},
4429{"bt", BBO(16,BOT,0,0), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BD}},
4430{"bbt", BBO(16,BOT,0,0), BBOAT_MASK, PWRCOM, PPCVLE, {BI, BD}},
4431{"btl-", BBO(16,BOT,0,1), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDM}},
4432{"btl+", BBO(16,BOT,0,1), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDP}},
4433{"btl", BBO(16,BOT,0,1), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BD}},
4434{"bbtl", BBO(16,BOT,0,1), BBOAT_MASK, PWRCOM, PPCVLE, {BI, BD}},
4435{"bta-", BBO(16,BOT,1,0), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDMA}},
4436{"bta+", BBO(16,BOT,1,0), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDPA}},
4437{"bta", BBO(16,BOT,1,0), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDA}},
4438{"bbta", BBO(16,BOT,1,0), BBOAT_MASK, PWRCOM, PPCVLE, {BI, BDA}},
4439{"btla-", BBO(16,BOT,1,1), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDMA}},
4440{"btla+", BBO(16,BOT,1,1), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDPA}},
4441{"btla", BBO(16,BOT,1,1), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDA}},
4442{"bbtla", BBO(16,BOT,1,1), BBOAT_MASK, PWRCOM, PPCVLE, {BI, BDA}},
4443
4444{"bc-", B(16,0,0), B_MASK, PPCCOM, PPCVLE, {BOE, BI, BDM}},
4445{"bc+", B(16,0,0), B_MASK, PPCCOM, PPCVLE, {BOE, BI, BDP}},
4446{"bc", B(16,0,0), B_MASK, COM, PPCVLE, {BO, BI, BD}},
4447{"bcl-", B(16,0,1), B_MASK, PPCCOM, PPCVLE, {BOE, BI, BDM}},
4448{"bcl+", B(16,0,1), B_MASK, PPCCOM, PPCVLE, {BOE, BI, BDP}},
4449{"bcl", B(16,0,1), B_MASK, COM, PPCVLE, {BO, BI, BD}},
4450{"bca-", B(16,1,0), B_MASK, PPCCOM, PPCVLE, {BOE, BI, BDMA}},
4451{"bca+", B(16,1,0), B_MASK, PPCCOM, PPCVLE, {BOE, BI, BDPA}},
4452{"bca", B(16,1,0), B_MASK, COM, PPCVLE, {BO, BI, BDA}},
4453{"bcla-", B(16,1,1), B_MASK, PPCCOM, PPCVLE, {BOE, BI, BDMA}},
4454{"bcla+", B(16,1,1), B_MASK, PPCCOM, PPCVLE, {BOE, BI, BDPA}},
4455{"bcla", B(16,1,1), B_MASK, COM, PPCVLE, {BO, BI, BDA}},
4456
4457{"svc", SC(17,0,0), SC_MASK, POWER, PPCVLE, {SVC_LEV, FL1, FL2}},
dce75bf9 4458{"scv", SC(17,0,1), SC_MASK, POWER9, PPCVLE, {SVC_LEV}},
14b57c7c
AM		 4459{"svcl", SC(17,0,1), SC_MASK, POWER, PPCVLE, {SVC_LEV, FL1, FL2}},
4460{"sc", SC(17,1,0), SC_MASK, PPC, PPCVLE, {LEV}},
4461{"svca", SC(17,1,0), SC_MASK, PWRCOM, PPCVLE, {SV}},
4462{"svcla", SC(17,1,1), SC_MASK, POWER, PPCVLE, {SV}},
4463
4464{"b", B(18,0,0), B_MASK, COM, PPCVLE, {LI}},
4465{"bl", B(18,0,1), B_MASK, COM, PPCVLE, {LI}},
4466{"ba", B(18,1,0), B_MASK, COM, PPCVLE, {LIA}},
4467{"bla", B(18,1,1), B_MASK, COM, PPCVLE, {LIA}},
4468
4469{"mcrf", XL(19,0), XLBB_MASK|(3<<21)|(3<<16), COM, PPCVLE, {BF, BFA}},
4470
1437d063 4471{"lnia", DX(19,2), NODX_MASK, POWER9, PPCVLE, {RT}},
14b57c7c
AM		 4472{"addpcis", DX(19,2), DX_MASK, POWER9, PPCVLE, {RT, DXD}},
4473{"subpcis", DX(19,2), DX_MASK, POWER9, PPCVLE, {RT, NDXD}},
4474
4475{"bdnzlr", XLO(19,BODNZ,16,0), XLBOBIBB_MASK, PPCCOM, PPCVLE, {0}},
4476{"bdnzlr-", XLO(19,BODNZ,16,0), XLBOBIBB_MASK, PPCCOM, ISA_V2|PPCVLE, {0}},
4477{"bdnzlrl", XLO(19,BODNZ,16,1), XLBOBIBB_MASK, PPCCOM, PPCVLE, {0}},
4478{"bdnzlrl-", XLO(19,BODNZ,16,1), XLBOBIBB_MASK, PPCCOM, ISA_V2|PPCVLE, {0}},
4479{"bdnzlr+", XLO(19,BODNZP,16,0), XLBOBIBB_MASK, PPCCOM, ISA_V2|PPCVLE, {0}},
4480{"bdnzlrl+", XLO(19,BODNZP,16,1), XLBOBIBB_MASK, PPCCOM, ISA_V2|PPCVLE, {0}},
4481{"bdzlr", XLO(19,BODZ,16,0), XLBOBIBB_MASK, PPCCOM, PPCVLE, {0}},
4482{"bdzlr-", XLO(19,BODZ,16,0), XLBOBIBB_MASK, PPCCOM, ISA_V2|PPCVLE, {0}},
4483{"bdzlrl", XLO(19,BODZ,16,1), XLBOBIBB_MASK, PPCCOM, PPCVLE, {0}},
4484{"bdzlrl-", XLO(19,BODZ,16,1), XLBOBIBB_MASK, PPCCOM, ISA_V2|PPCVLE, {0}},
4485{"bdzlr+", XLO(19,BODZP,16,0), XLBOBIBB_MASK, PPCCOM, ISA_V2|PPCVLE, {0}},
4486{"bdzlrl+", XLO(19,BODZP,16,1), XLBOBIBB_MASK, PPCCOM, ISA_V2|PPCVLE, {0}},
4487{"blr", XLO(19,BOU,16,0), XLBOBIBB_MASK, PPCCOM, PPCVLE, {0}},
4488{"br", XLO(19,BOU,16,0), XLBOBIBB_MASK, PWRCOM, PPCVLE, {0}},
4489{"blrl", XLO(19,BOU,16,1), XLBOBIBB_MASK, PPCCOM, PPCVLE, {0}},
4490{"brl", XLO(19,BOU,16,1), XLBOBIBB_MASK, PWRCOM, PPCVLE, {0}},
4491{"bdnzlr-", XLO(19,BODNZM4,16,0), XLBOBIBB_MASK, ISA_V2, PPCVLE, {0}},
4492{"bdnzlrl-", XLO(19,BODNZM4,16,1), XLBOBIBB_MASK, ISA_V2, PPCVLE, {0}},
4493{"bdnzlr+", XLO(19,BODNZP4,16,0), XLBOBIBB_MASK, ISA_V2, PPCVLE, {0}},
4494{"bdnzlrl+", XLO(19,BODNZP4,16,1), XLBOBIBB_MASK, ISA_V2, PPCVLE, {0}},
4495{"bdzlr-", XLO(19,BODZM4,16,0), XLBOBIBB_MASK, ISA_V2, PPCVLE, {0}},
4496{"bdzlrl-", XLO(19,BODZM4,16,1), XLBOBIBB_MASK, ISA_V2, PPCVLE, {0}},
4497{"bdzlr+", XLO(19,BODZP4,16,0), XLBOBIBB_MASK, ISA_V2, PPCVLE, {0}},
4498{"bdzlrl+", XLO(19,BODZP4,16,1), XLBOBIBB_MASK, ISA_V2, PPCVLE, {0}},
4499
4500{"bgelr", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4501{"bgelr-", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4502{"bger", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}},
4503{"bnllr", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4504{"bnllr-", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4505{"bnlr", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}},
4506{"bgelrl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4507{"bgelrl-", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4508{"bgerl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}},
4509{"bnllrl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4510{"bnllrl-", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4511{"bnlrl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}},
4512{"blelr", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4513{"blelr-", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4514{"bler", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}},
4515{"bnglr", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4516{"bnglr-", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4517{"bngr", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}},
4518{"blelrl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4519{"blelrl-", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4520{"blerl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}},
4521{"bnglrl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4522{"bnglrl-", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4523{"bngrl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}},
4524{"bnelr", XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4525{"bnelr-", XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4526{"bner", XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}},
4527{"bnelrl", XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4528{"bnelrl-", XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4529{"bnerl", XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}},
4530{"bnslr", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4531{"bnslr-", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4532{"bnsr", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}},
4533{"bnulr", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4534{"bnulr-", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4535{"bnslrl", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4536{"bnslrl-", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4537{"bnsrl", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}},
4538{"bnulrl", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4539{"bnulrl-", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4540{"bgelr+", XLOCB(19,BOFP,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4541{"bnllr+", XLOCB(19,BOFP,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4542{"bgelrl+", XLOCB(19,BOFP,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4543{"bnllrl+", XLOCB(19,BOFP,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4544{"blelr+", XLOCB(19,BOFP,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4545{"bnglr+", XLOCB(19,BOFP,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4546{"blelrl+", XLOCB(19,BOFP,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4547{"bnglrl+", XLOCB(19,BOFP,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4548{"bnelr+", XLOCB(19,BOFP,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4549{"bnelrl+", XLOCB(19,BOFP,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4550{"bnslr+", XLOCB(19,BOFP,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4551{"bnulr+", XLOCB(19,BOFP,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4552{"bnslrl+", XLOCB(19,BOFP,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4553{"bnulrl+", XLOCB(19,BOFP,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4554{"bgelr-", XLOCB(19,BOFM4,CBLT,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4555{"bnllr-", XLOCB(19,BOFM4,CBLT,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4556{"bgelrl-", XLOCB(19,BOFM4,CBLT,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4557{"bnllrl-", XLOCB(19,BOFM4,CBLT,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4558{"blelr-", XLOCB(19,BOFM4,CBGT,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4559{"bnglr-", XLOCB(19,BOFM4,CBGT,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4560{"blelrl-", XLOCB(19,BOFM4,CBGT,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4561{"bnglrl-", XLOCB(19,BOFM4,CBGT,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4562{"bnelr-", XLOCB(19,BOFM4,CBEQ,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4563{"bnelrl-", XLOCB(19,BOFM4,CBEQ,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4564{"bnslr-", XLOCB(19,BOFM4,CBSO,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4565{"bnulr-", XLOCB(19,BOFM4,CBSO,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4566{"bnslrl-", XLOCB(19,BOFM4,CBSO,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4567{"bnulrl-", XLOCB(19,BOFM4,CBSO,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4568{"bgelr+", XLOCB(19,BOFP4,CBLT,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4569{"bnllr+", XLOCB(19,BOFP4,CBLT,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4570{"bgelrl+", XLOCB(19,BOFP4,CBLT,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4571{"bnllrl+", XLOCB(19,BOFP4,CBLT,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4572{"blelr+", XLOCB(19,BOFP4,CBGT,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4573{"bnglr+", XLOCB(19,BOFP4,CBGT,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4574{"blelrl+", XLOCB(19,BOFP4,CBGT,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4575{"bnglrl+", XLOCB(19,BOFP4,CBGT,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4576{"bnelr+", XLOCB(19,BOFP4,CBEQ,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4577{"bnelrl+", XLOCB(19,BOFP4,CBEQ,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4578{"bnslr+", XLOCB(19,BOFP4,CBSO,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4579{"bnulr+", XLOCB(19,BOFP4,CBSO,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4580{"bnslrl+", XLOCB(19,BOFP4,CBSO,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4581{"bnulrl+", XLOCB(19,BOFP4,CBSO,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4582{"bltlr", XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4583{"bltlr-", XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4584{"bltr", XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}},
4585{"bltlrl", XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4586{"bltlrl-", XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4587{"bltrl", XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}},
4588{"bgtlr", XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4589{"bgtlr-", XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4590{"bgtr", XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}},
4591{"bgtlrl", XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4592{"bgtlrl-", XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4593{"bgtrl", XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}},
4594{"beqlr", XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4595{"beqlr-", XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4596{"beqr", XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}},
4597{"beqlrl", XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4598{"beqlrl-", XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4599{"beqrl", XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}},
4600{"bsolr", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4601{"bsolr-", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4602{"bsor", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}},
4603{"bunlr", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4604{"bunlr-", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4605{"bsolrl", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4606{"bsolrl-", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4607{"bsorl", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}},
4608{"bunlrl", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4609{"bunlrl-", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4610{"bltlr+", XLOCB(19,BOTP,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4611{"bltlrl+", XLOCB(19,BOTP,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4612{"bgtlr+", XLOCB(19,BOTP,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4613{"bgtlrl+", XLOCB(19,BOTP,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4614{"beqlr+", XLOCB(19,BOTP,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4615{"beqlrl+", XLOCB(19,BOTP,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4616{"bsolr+", XLOCB(19,BOTP,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4617{"bunlr+", XLOCB(19,BOTP,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4618{"bsolrl+", XLOCB(19,BOTP,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4619{"bunlrl+", XLOCB(19,BOTP,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4620{"bltlr-", XLOCB(19,BOTM4,CBLT,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4621{"bltlrl-", XLOCB(19,BOTM4,CBLT,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4622{"bgtlr-", XLOCB(19,BOTM4,CBGT,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4623{"bgtlrl-", XLOCB(19,BOTM4,CBGT,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4624{"beqlr-", XLOCB(19,BOTM4,CBEQ,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4625{"beqlrl-", XLOCB(19,BOTM4,CBEQ,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4626{"bsolr-", XLOCB(19,BOTM4,CBSO,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4627{"bunlr-", XLOCB(19,BOTM4,CBSO,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4628{"bsolrl-", XLOCB(19,BOTM4,CBSO,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4629{"bunlrl-", XLOCB(19,BOTM4,CBSO,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4630{"bltlr+", XLOCB(19,BOTP4,CBLT,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4631{"bltlrl+", XLOCB(19,BOTP4,CBLT,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4632{"bgtlr+", XLOCB(19,BOTP4,CBGT,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4633{"bgtlrl+", XLOCB(19,BOTP4,CBGT,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4634{"beqlr+", XLOCB(19,BOTP4,CBEQ,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4635{"beqlrl+", XLOCB(19,BOTP4,CBEQ,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4636{"bsolr+", XLOCB(19,BOTP4,CBSO,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4637{"bunlr+", XLOCB(19,BOTP4,CBSO,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4638{"bsolrl+", XLOCB(19,BOTP4,CBSO,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4639{"bunlrl+", XLOCB(19,BOTP4,CBSO,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4640
4641{"bdnzflr", XLO(19,BODNZF,16,0), XLBOBB_MASK, PPCCOM, PPCVLE, {BI}},
4642{"bdnzflr-", XLO(19,BODNZF,16,0), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
4643{"bdnzflrl", XLO(19,BODNZF,16,1), XLBOBB_MASK, PPCCOM, PPCVLE, {BI}},
4644{"bdnzflrl-",XLO(19,BODNZF,16,1), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
4645{"bdnzflr+", XLO(19,BODNZFP,16,0), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
4646{"bdnzflrl+",XLO(19,BODNZFP,16,1), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
4647{"bdzflr", XLO(19,BODZF,16,0), XLBOBB_MASK, PPCCOM, PPCVLE, {BI}},
4648{"bdzflr-", XLO(19,BODZF,16,0), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
4649{"bdzflrl", XLO(19,BODZF,16,1), XLBOBB_MASK, PPCCOM, PPCVLE, {BI}},
4650{"bdzflrl-", XLO(19,BODZF,16,1), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
4651{"bdzflr+", XLO(19,BODZFP,16,0), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
4652{"bdzflrl+", XLO(19,BODZFP,16,1), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
4653{"bflr", XLO(19,BOF,16,0), XLBOBB_MASK, PPCCOM, PPCVLE, {BI}},
4654{"bflr-", XLO(19,BOF,16,0), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
4655{"bbfr", XLO(19,BOF,16,0), XLBOBB_MASK, PWRCOM, PPCVLE, {BI}},
4656{"bflrl", XLO(19,BOF,16,1), XLBOBB_MASK, PPCCOM, PPCVLE, {BI}},
4657{"bflrl-", XLO(19,BOF,16,1), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
4658{"bbfrl", XLO(19,BOF,16,1), XLBOBB_MASK, PWRCOM, PPCVLE, {BI}},
4659{"bflr+", XLO(19,BOFP,16,0), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
4660{"bflrl+", XLO(19,BOFP,16,1), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
4661{"bflr-", XLO(19,BOFM4,16,0), XLBOBB_MASK, ISA_V2, PPCVLE, {BI}},
4662{"bflrl-", XLO(19,BOFM4,16,1), XLBOBB_MASK, ISA_V2, PPCVLE, {BI}},
4663{"bflr+", XLO(19,BOFP4,16,0), XLBOBB_MASK, ISA_V2, PPCVLE, {BI}},
4664{"bflrl+", XLO(19,BOFP4,16,1), XLBOBB_MASK, ISA_V2, PPCVLE, {BI}},
4665{"bdnztlr", XLO(19,BODNZT,16,0), XLBOBB_MASK, PPCCOM, PPCVLE, {BI}},
4666{"bdnztlr-", XLO(19,BODNZT,16,0), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
4667{"bdnztlrl", XLO(19,BODNZT,16,1), XLBOBB_MASK, PPCCOM, PPCVLE, {BI}},
4668{"bdnztlrl-", XLO(19,BODNZT,16,1), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
4669{"bdnztlr+", XLO(19,BODNZTP,16,0), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
4670{"bdnztlrl+", XLO(19,BODNZTP,16,1), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
4671{"bdztlr", XLO(19,BODZT,16,0), XLBOBB_MASK, PPCCOM, PPCVLE, {BI}},
4672{"bdztlr-", XLO(19,BODZT,16,0), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
4673{"bdztlrl", XLO(19,BODZT,16,1), XLBOBB_MASK, PPCCOM, PPCVLE, {BI}},
4674{"bdztlrl-", XLO(19,BODZT,16,1), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
4675{"bdztlr+", XLO(19,BODZTP,16,0), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
4676{"bdztlrl+", XLO(19,BODZTP,16,1), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
4677{"btlr", XLO(19,BOT,16,0), XLBOBB_MASK, PPCCOM, PPCVLE, {BI}},
4678{"btlr-", XLO(19,BOT,16,0), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
4679{"bbtr", XLO(19,BOT,16,0), XLBOBB_MASK, PWRCOM, PPCVLE, {BI}},
4680{"btlrl", XLO(19,BOT,16,1), XLBOBB_MASK, PPCCOM, PPCVLE, {BI}},
4681{"btlrl-", XLO(19,BOT,16,1), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
4682{"bbtrl", XLO(19,BOT,16,1), XLBOBB_MASK, PWRCOM, PPCVLE, {BI}},
4683{"btlr+", XLO(19,BOTP,16,0), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
4684{"btlrl+", XLO(19,BOTP,16,1), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
4685{"btlr-", XLO(19,BOTM4,16,0), XLBOBB_MASK, ISA_V2, PPCVLE, {BI}},
4686{"btlrl-", XLO(19,BOTM4,16,1), XLBOBB_MASK, ISA_V2, PPCVLE, {BI}},
4687{"btlr+", XLO(19,BOTP4,16,0), XLBOBB_MASK, ISA_V2, PPCVLE, {BI}},
4688{"btlrl+", XLO(19,BOTP4,16,1), XLBOBB_MASK, ISA_V2, PPCVLE, {BI}},
4689
4690{"bclr-", XLYLK(19,16,0,0), XLYBB_MASK, PPCCOM, PPCVLE, {BOE, BI}},
4691{"bclrl-", XLYLK(19,16,0,1), XLYBB_MASK, PPCCOM, PPCVLE, {BOE, BI}},
4692{"bclr+", XLYLK(19,16,1,0), XLYBB_MASK, PPCCOM, PPCVLE, {BOE, BI}},
4693{"bclrl+", XLYLK(19,16,1,1), XLYBB_MASK, PPCCOM, PPCVLE, {BOE, BI}},
4694{"bclr", XLLK(19,16,0), XLBH_MASK, PPCCOM, PPCVLE, {BO, BI, BH}},
4695{"bcr", XLLK(19,16,0), XLBB_MASK, PWRCOM, PPCVLE, {BO, BI}},
4696{"bclrl", XLLK(19,16,1), XLBH_MASK, PPCCOM, PPCVLE, {BO, BI, BH}},
4697{"bcrl", XLLK(19,16,1), XLBB_MASK, PWRCOM, PPCVLE, {BO, BI}},
4698
4699{"rfid", XL(19,18), 0xffffffff, PPC64, PPCVLE, {0}},
4700
4701{"crnot", XL(19,33), XL_MASK, PPCCOM, PPCVLE, {BT, BA, BBA}},
4702{"crnor", XL(19,33), XL_MASK, COM, PPCVLE, {BT, BA, BB}},
4703{"rfmci", X(19,38), 0xffffffff, PPCRFMCI|PPCA2|PPC476, PPCVLE, {0}},
4704
4705{"rfdi", XL(19,39), 0xffffffff, E500MC, PPCVLE, {0}},
4706{"rfi", XL(19,50), 0xffffffff, COM, PPCVLE, {0}},
4707{"rfci", XL(19,51), 0xffffffff, PPC403|BOOKE|PPCE300|PPCA2|PPC476, PPCVLE, {0}},
4708
dce75bf9 4709{"rfscv", XL(19,82), 0xffffffff, POWER9, PPCVLE, {0}},
14b57c7c
AM		 4710{"rfsvc", XL(19,82), 0xffffffff, POWER, PPCVLE, {0}},
4711
4712{"rfgi", XL(19,102), 0xffffffff, E500MC|PPCA2, PPCVLE, {0}},
4713
4714{"crandc", XL(19,129), XL_MASK, COM, PPCVLE, {BT, BA, BB}},
4715
4716{"rfebb", XL(19,146), XLS_MASK, POWER8, PPCVLE, {SXL}},
4717
4718{"isync", XL(19,150), 0xffffffff, PPCCOM, PPCVLE, {0}},
4719{"ics", XL(19,150), 0xffffffff, PWRCOM, PPCVLE, {0}},
4720
4721{"crclr", XL(19,193), XL_MASK, PPCCOM, PPCVLE, {BT, BAT, BBA}},
4722{"crxor", XL(19,193), XL_MASK, COM, PPCVLE, {BT, BA, BB}},
4723
4724{"dnh", X(19,198), X_MASK, E500MC, PPCVLE, {DUI, DUIS}},
4725
4726{"crnand", XL(19,225), XL_MASK, COM, PPCVLE, {BT, BA, BB}},
4727
4728{"crand", XL(19,257), XL_MASK, COM, PPCVLE, {BT, BA, BB}},
4729
4730{"hrfid", XL(19,274), 0xffffffff, POWER5|CELL, PPC476|PPCVLE, {0}},
4731
4732{"crset", XL(19,289), XL_MASK, PPCCOM, PPCVLE, {BT, BAT, BBA}},
4733{"creqv", XL(19,289), XL_MASK, COM, PPCVLE, {BT, BA, BB}},
4734
4735{"urfid", XL(19,306), 0xffffffff, POWER9, PPCVLE, {0}},
4736{"stop", XL(19,370), 0xffffffff, POWER9, PPCVLE, {0}},
4737
4738{"doze", XL(19,402), 0xffffffff, POWER6, POWER9|PPCVLE, {0}},
4739
4740{"crorc", XL(19,417), XL_MASK, COM, PPCVLE, {BT, BA, BB}},
4741
4742{"nap", XL(19,434), 0xffffffff, POWER6, POWER9|PPCVLE, {0}},
4743
4744{"crmove", XL(19,449), XL_MASK, PPCCOM, PPCVLE, {BT, BA, BBA}},
4745{"cror", XL(19,449), XL_MASK, COM, PPCVLE, {BT, BA, BB}},
4746
4747{"sleep", XL(19,466), 0xffffffff, POWER6, POWER9|PPCVLE, {0}},
4748{"rvwinkle", XL(19,498), 0xffffffff, POWER6, POWER9|PPCVLE, {0}},
4749
4750{"bctr", XLO(19,BOU,528,0), XLBOBIBB_MASK, COM, PPCVLE, {0}},
4751{"bctrl", XLO(19,BOU,528,1), XLBOBIBB_MASK, COM, PPCVLE, {0}},
4752
4753{"bgectr", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4754{"bgectr-", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4755{"bnlctr", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4756{"bnlctr-", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4757{"bgectrl", XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4758{"bgectrl-",XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4759{"bnlctrl", XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4760{"bnlctrl-",XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4761{"blectr", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4762{"blectr-", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4763{"bngctr", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4764{"bngctr-", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4765{"blectrl", XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4766{"blectrl-",XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4767{"bngctrl", XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4768{"bngctrl-",XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4769{"bnectr", XLOCB(19,BOF,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4770{"bnectr-", XLOCB(19,BOF,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4771{"bnectrl", XLOCB(19,BOF,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4772{"bnectrl-",XLOCB(19,BOF,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4773{"bnsctr", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4774{"bnsctr-", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4775{"bnuctr", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4776{"bnuctr-", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4777{"bnsctrl", XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4778{"bnsctrl-",XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4779{"bnuctrl", XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4780{"bnuctrl-",XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4781{"bgectr+", XLOCB(19,BOFP,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4782{"bnlctr+", XLOCB(19,BOFP,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4783{"bgectrl+",XLOCB(19,BOFP,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4784{"bnlctrl+",XLOCB(19,BOFP,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4785{"blectr+", XLOCB(19,BOFP,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4786{"bngctr+", XLOCB(19,BOFP,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4787{"blectrl+",XLOCB(19,BOFP,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4788{"bngctrl+",XLOCB(19,BOFP,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4789{"bnectr+", XLOCB(19,BOFP,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4790{"bnectrl+",XLOCB(19,BOFP,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4791{"bnsctr+", XLOCB(19,BOFP,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4792{"bnuctr+", XLOCB(19,BOFP,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4793{"bnsctrl+",XLOCB(19,BOFP,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4794{"bnuctrl+",XLOCB(19,BOFP,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4795{"bgectr-", XLOCB(19,BOFM4,CBLT,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4796{"bnlctr-", XLOCB(19,BOFM4,CBLT,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4797{"bgectrl-",XLOCB(19,BOFM4,CBLT,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4798{"bnlctrl-",XLOCB(19,BOFM4,CBLT,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4799{"blectr-", XLOCB(19,BOFM4,CBGT,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4800{"bngctr-", XLOCB(19,BOFM4,CBGT,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4801{"blectrl-",XLOCB(19,BOFM4,CBGT,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4802{"bngctrl-",XLOCB(19,BOFM4,CBGT,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4803{"bnectr-", XLOCB(19,BOFM4,CBEQ,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4804{"bnectrl-",XLOCB(19,BOFM4,CBEQ,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4805{"bnsctr-", XLOCB(19,BOFM4,CBSO,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4806{"bnuctr-", XLOCB(19,BOFM4,CBSO,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4807{"bnsctrl-",XLOCB(19,BOFM4,CBSO,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4808{"bnuctrl-",XLOCB(19,BOFM4,CBSO,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4809{"bgectr+", XLOCB(19,BOFP4,CBLT,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4810{"bnlctr+", XLOCB(19,BOFP4,CBLT,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4811{"bgectrl+",XLOCB(19,BOFP4,CBLT,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4812{"bnlctrl+",XLOCB(19,BOFP4,CBLT,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4813{"blectr+", XLOCB(19,BOFP4,CBGT,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4814{"bngctr+", XLOCB(19,BOFP4,CBGT,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4815{"blectrl+",XLOCB(19,BOFP4,CBGT,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4816{"bngctrl+",XLOCB(19,BOFP4,CBGT,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4817{"bnectr+", XLOCB(19,BOFP4,CBEQ,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4818{"bnectrl+",XLOCB(19,BOFP4,CBEQ,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4819{"bnsctr+", XLOCB(19,BOFP4,CBSO,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4820{"bnuctr+", XLOCB(19,BOFP4,CBSO,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4821{"bnsctrl+",XLOCB(19,BOFP4,CBSO,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4822{"bnuctrl+",XLOCB(19,BOFP4,CBSO,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4823{"bltctr", XLOCB(19,BOT,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4824{"bltctr-", XLOCB(19,BOT,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4825{"bltctrl", XLOCB(19,BOT,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4826{"bltctrl-",XLOCB(19,BOT,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4827{"bgtctr", XLOCB(19,BOT,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4828{"bgtctr-", XLOCB(19,BOT,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4829{"bgtctrl", XLOCB(19,BOT,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4830{"bgtctrl-",XLOCB(19,BOT,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4831{"beqctr", XLOCB(19,BOT,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4832{"beqctr-", XLOCB(19,BOT,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4833{"beqctrl", XLOCB(19,BOT,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4834{"beqctrl-",XLOCB(19,BOT,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4835{"bsoctr", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4836{"bsoctr-", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4837{"bunctr", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4838{"bunctr-", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4839{"bsoctrl", XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4840{"bsoctrl-",XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4841{"bunctrl", XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4842{"bunctrl-",XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4843{"bltctr+", XLOCB(19,BOTP,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4844{"bltctrl+",XLOCB(19,BOTP,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4845{"bgtctr+", XLOCB(19,BOTP,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4846{"bgtctrl+",XLOCB(19,BOTP,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4847{"beqctr+", XLOCB(19,BOTP,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4848{"beqctrl+",XLOCB(19,BOTP,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4849{"bsoctr+", XLOCB(19,BOTP,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4850{"bunctr+", XLOCB(19,BOTP,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4851{"bsoctrl+",XLOCB(19,BOTP,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4852{"bunctrl+",XLOCB(19,BOTP,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4853{"bltctr-", XLOCB(19,BOTM4,CBLT,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4854{"bltctrl-",XLOCB(19,BOTM4,CBLT,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4855{"bgtctr-", XLOCB(19,BOTM4,CBGT,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4856{"bgtctrl-",XLOCB(19,BOTM4,CBGT,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4857{"beqctr-", XLOCB(19,BOTM4,CBEQ,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4858{"beqctrl-",XLOCB(19,BOTM4,CBEQ,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4859{"bsoctr-", XLOCB(19,BOTM4,CBSO,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4860{"bunctr-", XLOCB(19,BOTM4,CBSO,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4861{"bsoctrl-",XLOCB(19,BOTM4,CBSO,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4862{"bunctrl-",XLOCB(19,BOTM4,CBSO,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4863{"bltctr+", XLOCB(19,BOTP4,CBLT,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4864{"bltctrl+",XLOCB(19,BOTP4,CBLT,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4865{"bgtctr+", XLOCB(19,BOTP4,CBGT,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4866{"bgtctrl+",XLOCB(19,BOTP4,CBGT,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4867{"beqctr+", XLOCB(19,BOTP4,CBEQ,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4868{"beqctrl+",XLOCB(19,BOTP4,CBEQ,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4869{"bsoctr+", XLOCB(19,BOTP4,CBSO,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4870{"bunctr+", XLOCB(19,BOTP4,CBSO,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4871{"bsoctrl+",XLOCB(19,BOTP4,CBSO,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4872{"bunctrl+",XLOCB(19,BOTP4,CBSO,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4873
4874{"bfctr", XLO(19,BOF,528,0), XLBOBB_MASK, PPCCOM, PPCVLE, {BI}},
4875{"bfctr-", XLO(19,BOF,528,0), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
4876{"bfctrl", XLO(19,BOF,528,1), XLBOBB_MASK, PPCCOM, PPCVLE, {BI}},
4877{"bfctrl-", XLO(19,BOF,528,1), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
4878{"bfctr+", XLO(19,BOFP,528,0), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
4879{"bfctrl+", XLO(19,BOFP,528,1), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
4880{"bfctr-", XLO(19,BOFM4,528,0), XLBOBB_MASK, ISA_V2, PPCVLE, {BI}},
4881{"bfctrl-", XLO(19,BOFM4,528,1), XLBOBB_MASK, ISA_V2, PPCVLE, {BI}},
4882{"bfctr+", XLO(19,BOFP4,528,0), XLBOBB_MASK, ISA_V2, PPCVLE, {BI}},
4883{"bfctrl+", XLO(19,BOFP4,528,1), XLBOBB_MASK, ISA_V2, PPCVLE, {BI}},
4884{"btctr", XLO(19,BOT,528,0), XLBOBB_MASK, PPCCOM, PPCVLE, {BI}},
4885{"btctr-", XLO(19,BOT,528,0), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
4886{"btctrl", XLO(19,BOT,528,1), XLBOBB_MASK, PPCCOM, PPCVLE, {BI}},
4887{"btctrl-", XLO(19,BOT,528,1), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
4888{"btctr+", XLO(19,BOTP,528,0), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
4889{"btctrl+", XLO(19,BOTP,528,1), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
4890{"btctr-", XLO(19,BOTM4,528,0), XLBOBB_MASK, ISA_V2, PPCVLE, {BI}},
4891{"btctrl-", XLO(19,BOTM4,528,1), XLBOBB_MASK, ISA_V2, PPCVLE, {BI}},
4892{"btctr+", XLO(19,BOTP4,528,0), XLBOBB_MASK, ISA_V2, PPCVLE, {BI}},
4893{"btctrl+", XLO(19,BOTP4,528,1), XLBOBB_MASK, ISA_V2, PPCVLE, {BI}},
4894
4895{"bcctr-", XLYLK(19,528,0,0), XLYBB_MASK, PPCCOM, PPCVLE, {BOE, BI}},
4896{"bcctrl-", XLYLK(19,528,0,1), XLYBB_MASK, PPCCOM, PPCVLE, {BOE, BI}},
4897{"bcctr+", XLYLK(19,528,1,0), XLYBB_MASK, PPCCOM, PPCVLE, {BOE, BI}},
4898{"bcctrl+", XLYLK(19,528,1,1), XLYBB_MASK, PPCCOM, PPCVLE, {BOE, BI}},
4899{"bcctr", XLLK(19,528,0), XLBH_MASK, PPCCOM, PPCVLE, {BO, BI, BH}},
4900{"bcc", XLLK(19,528,0), XLBB_MASK, PWRCOM, PPCVLE, {BO, BI}},
4901{"bcctrl", XLLK(19,528,1), XLBH_MASK, PPCCOM, PPCVLE, {BO, BI, BH}},
4902{"bccl", XLLK(19,528,1), XLBB_MASK, PWRCOM, PPCVLE, {BO, BI}},
4903
4904{"bctar-", XLYLK(19,560,0,0), XLYBB_MASK, POWER8, PPCVLE, {BOE, BI}},
4905{"bctarl-", XLYLK(19,560,0,1), XLYBB_MASK, POWER8, PPCVLE, {BOE, BI}},
4906{"bctar+", XLYLK(19,560,1,0), XLYBB_MASK, POWER8, PPCVLE, {BOE, BI}},
4907{"bctarl+", XLYLK(19,560,1,1), XLYBB_MASK, POWER8, PPCVLE, {BOE, BI}},
4908{"bctar", XLLK(19,560,0), XLBH_MASK, POWER8, PPCVLE, {BO, BI, BH}},
4909{"bctarl", XLLK(19,560,1), XLBH_MASK, POWER8, PPCVLE, {BO, BI, BH}},
4910
4911{"rlwimi", M(20,0), M_MASK, PPCCOM, PPCVLE, {RA, RS, SH, MBE, ME}},
4912{"rlimi", M(20,0), M_MASK, PWRCOM, PPCVLE, {RA, RS, SH, MBE, ME}},
4913
4914{"rlwimi.", M(20,1), M_MASK, PPCCOM, PPCVLE, {RA, RS, SH, MBE, ME}},
4915{"rlimi.", M(20,1), M_MASK, PWRCOM, PPCVLE, {RA, RS, SH, MBE, ME}},
4916
4917{"rotlwi", MME(21,31,0), MMBME_MASK, PPCCOM, PPCVLE, {RA, RS, SH}},
4918{"clrlwi", MME(21,31,0), MSHME_MASK, PPCCOM, PPCVLE, {RA, RS, MB}},
4919{"rlwinm", M(21,0), M_MASK, PPCCOM, PPCVLE, {RA, RS, SH, MBE, ME}},
4920{"rlinm", M(21,0), M_MASK, PWRCOM, PPCVLE, {RA, RS, SH, MBE, ME}},
4921{"rotlwi.", MME(21,31,1), MMBME_MASK, PPCCOM, PPCVLE, {RA, RS, SH}},
4922{"clrlwi.", MME(21,31,1), MSHME_MASK, PPCCOM, PPCVLE, {RA, RS, MB}},
4923{"rlwinm.", M(21,1), M_MASK, PPCCOM, PPCVLE, {RA, RS, SH, MBE, ME}},
4924{"rlinm.", M(21,1), M_MASK, PWRCOM, PPCVLE, {RA, RS, SH, MBE, ME}},
4925
4926{"rlmi", M(22,0), M_MASK, M601, PPCVLE, {RA, RS, RB, MBE, ME}},
4927{"rlmi.", M(22,1), M_MASK, M601, PPCVLE, {RA, RS, RB, MBE, ME}},
4928
4929{"rotlw", MME(23,31,0), MMBME_MASK, PPCCOM, PPCVLE, {RA, RS, RB}},
4930{"rlwnm", M(23,0), M_MASK, PPCCOM, PPCVLE, {RA, RS, RB, MBE, ME}},
4931{"rlnm", M(23,0), M_MASK, PWRCOM, PPCVLE, {RA, RS, RB, MBE, ME}},
4932{"rotlw.", MME(23,31,1), MMBME_MASK, PPCCOM, PPCVLE, {RA, RS, RB}},
4933{"rlwnm.", M(23,1), M_MASK, PPCCOM, PPCVLE, {RA, RS, RB, MBE, ME}},
4934{"rlnm.", M(23,1), M_MASK, PWRCOM, PPCVLE, {RA, RS, RB, MBE, ME}},
4935
4936{"nop", OP(24), 0xffffffff, PPCCOM, PPCVLE, {0}},
4937{"ori", OP(24), OP_MASK, PPCCOM, PPCVLE, {RA, RS, UI}},
4938{"oril", OP(24), OP_MASK, PWRCOM, PPCVLE, {RA, RS, UI}},
4939
4940{"oris", OP(25), OP_MASK, PPCCOM, PPCVLE, {RA, RS, UI}},
4941{"oriu", OP(25), OP_MASK, PWRCOM, PPCVLE, {RA, RS, UI}},
4942
4943{"xnop", OP(26), 0xffffffff, PPCCOM, PPCVLE, {0}},
4944{"xori", OP(26), OP_MASK, PPCCOM, PPCVLE, {RA, RS, UI}},
4945{"xoril", OP(26), OP_MASK, PWRCOM, PPCVLE, {RA, RS, UI}},
4946
4947{"xoris", OP(27), OP_MASK, PPCCOM, PPCVLE, {RA, RS, UI}},
4948{"xoriu", OP(27), OP_MASK, PWRCOM, PPCVLE, {RA, RS, UI}},
4949
4950{"andi.", OP(28), OP_MASK, PPCCOM, PPCVLE, {RA, RS, UI}},
4951{"andil.", OP(28), OP_MASK, PWRCOM, PPCVLE, {RA, RS, UI}},
4952
4953{"andis.", OP(29), OP_MASK, PPCCOM, PPCVLE, {RA, RS, UI}},
4954{"andiu.", OP(29), OP_MASK, PWRCOM, PPCVLE, {RA, RS, UI}},
4955
4956{"rotldi", MD(30,0,0), MDMB_MASK, PPC64, PPCVLE, {RA, RS, SH6}},
4957{"clrldi", MD(30,0,0), MDSH_MASK, PPC64, PPCVLE, {RA, RS, MB6}},
4958{"rldicl", MD(30,0,0), MD_MASK, PPC64, PPCVLE, {RA, RS, SH6, MB6}},
4959{"rotldi.", MD(30,0,1), MDMB_MASK, PPC64, PPCVLE, {RA, RS, SH6}},
4960{"clrldi.", MD(30,0,1), MDSH_MASK, PPC64, PPCVLE, {RA, RS, MB6}},
4961{"rldicl.", MD(30,0,1), MD_MASK, PPC64, PPCVLE, {RA, RS, SH6, MB6}},
4962
4963{"rldicr", MD(30,1,0), MD_MASK, PPC64, PPCVLE, {RA, RS, SH6, ME6}},
4964{"rldicr.", MD(30,1,1), MD_MASK, PPC64, PPCVLE, {RA, RS, SH6, ME6}},
4965
4966{"rldic", MD(30,2,0), MD_MASK, PPC64, PPCVLE, {RA, RS, SH6, MB6}},
4967{"rldic.", MD(30,2,1), MD_MASK, PPC64, PPCVLE, {RA, RS, SH6, MB6}},
4968
4969{"rldimi", MD(30,3,0), MD_MASK, PPC64, PPCVLE, {RA, RS, SH6, MB6}},
4970{"rldimi.", MD(30,3,1), MD_MASK, PPC64, PPCVLE, {RA, RS, SH6, MB6}},
4971
4972{"rotld", MDS(30,8,0), MDSMB_MASK, PPC64, PPCVLE, {RA, RS, RB}},
4973{"rldcl", MDS(30,8,0), MDS_MASK, PPC64, PPCVLE, {RA, RS, RB, MB6}},
4974{"rotld.", MDS(30,8,1), MDSMB_MASK, PPC64, PPCVLE, {RA, RS, RB}},
4975{"rldcl.", MDS(30,8,1), MDS_MASK, PPC64, PPCVLE, {RA, RS, RB, MB6}},
4976
4977{"rldcr", MDS(30,9,0), MDS_MASK, PPC64, PPCVLE, {RA, RS, RB, ME6}},
4978{"rldcr.", MDS(30,9,1), MDS_MASK, PPC64, PPCVLE, {RA, RS, RB, ME6}},
4979
4980{"cmpw", XOPL(31,0,0), XCMPL_MASK, PPCCOM, 0, {OBF, RA, RB}},
4981{"cmpd", XOPL(31,0,1), XCMPL_MASK, PPC64, 0, {OBF, RA, RB}},
a5721ba2 4982{"cmp", X(31,0), XCMP_MASK, PPC, 0, {BF, L32OPT, RA, RB}},
bdc70b4a 4983{"cmp", X(31,0), XCMPL_MASK, PWRCOM, PPC, {BF, RA, RB}},
1cb0a767 4984
14b57c7c
AM		 4985{"twlgt", XTO(31,4,TOLGT), XTO_MASK, PPCCOM, 0, {RA, RB}},
4986{"tlgt", XTO(31,4,TOLGT), XTO_MASK, PWRCOM, 0, {RA, RB}},
4987{"twllt", XTO(31,4,TOLLT), XTO_MASK, PPCCOM, 0, {RA, RB}},
4988{"tllt", XTO(31,4,TOLLT), XTO_MASK, PWRCOM, 0, {RA, RB}},
4989{"tweq", XTO(31,4,TOEQ), XTO_MASK, PPCCOM, 0, {RA, RB}},
4990{"teq", XTO(31,4,TOEQ), XTO_MASK, PWRCOM, 0, {RA, RB}},
4991{"twlge", XTO(31,4,TOLGE), XTO_MASK, PPCCOM, 0, {RA, RB}},
4992{"tlge", XTO(31,4,TOLGE), XTO_MASK, PWRCOM, 0, {RA, RB}},
4993{"twlnl", XTO(31,4,TOLNL), XTO_MASK, PPCCOM, 0, {RA, RB}},
4994{"tlnl", XTO(31,4,TOLNL), XTO_MASK, PWRCOM, 0, {RA, RB}},
4995{"twlle", XTO(31,4,TOLLE), XTO_MASK, PPCCOM, 0, {RA, RB}},
4996{"tlle", XTO(31,4,TOLLE), XTO_MASK, PWRCOM, 0, {RA, RB}},
4997{"twlng", XTO(31,4,TOLNG), XTO_MASK, PPCCOM, 0, {RA, RB}},
4998{"tlng", XTO(31,4,TOLNG), XTO_MASK, PWRCOM, 0, {RA, RB}},
4999{"twgt", XTO(31,4,TOGT), XTO_MASK, PPCCOM, 0, {RA, RB}},
5000{"tgt", XTO(31,4,TOGT), XTO_MASK, PWRCOM, 0, {RA, RB}},
5001{"twge", XTO(31,4,TOGE), XTO_MASK, PPCCOM, 0, {RA, RB}},
5002{"tge", XTO(31,4,TOGE), XTO_MASK, PWRCOM, 0, {RA, RB}},
5003{"twnl", XTO(31,4,TONL), XTO_MASK, PPCCOM, 0, {RA, RB}},
5004{"tnl", XTO(31,4,TONL), XTO_MASK, PWRCOM, 0, {RA, RB}},
5005{"twlt", XTO(31,4,TOLT), XTO_MASK, PPCCOM, 0, {RA, RB}},
5006{"tlt", XTO(31,4,TOLT), XTO_MASK, PWRCOM, 0, {RA, RB}},
5007{"twle", XTO(31,4,TOLE), XTO_MASK, PPCCOM, 0, {RA, RB}},
5008{"tle", XTO(31,4,TOLE), XTO_MASK, PWRCOM, 0, {RA, RB}},
5009{"twng", XTO(31,4,TONG), XTO_MASK, PPCCOM, 0, {RA, RB}},
5010{"tng", XTO(31,4,TONG), XTO_MASK, PWRCOM, 0, {RA, RB}},
5011{"twne", XTO(31,4,TONE), XTO_MASK, PPCCOM, 0, {RA, RB}},
5012{"tne", XTO(31,4,TONE), XTO_MASK, PWRCOM, 0, {RA, RB}},
5013{"trap", XTO(31,4,TOU), 0xffffffff, PPCCOM, 0, {0}},
5014{"twu", XTO(31,4,TOU), XTO_MASK, PPCCOM, 0, {RA, RB}},
5015{"tu", XTO(31,4,TOU), XTO_MASK, PWRCOM, 0, {RA, RB}},
5016{"tw", X(31,4), X_MASK, PPCCOM, 0, {TO, RA, RB}},
5017{"t", X(31,4), X_MASK, PWRCOM, 0, {TO, RA, RB}},
5018
5019{"lvsl", X(31,6), X_MASK, PPCVEC, 0, {VD, RA0, RB}},
5020{"lvebx", X(31,7), X_MASK, PPCVEC, 0, {VD, RA0, RB}},
5021{"lbfcmx", APU(31,7,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},
5022
5023{"subfc", XO(31,8,0,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
5024{"sf", XO(31,8,0,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
5025{"subc", XO(31,8,0,0), XO_MASK, PPCCOM, 0, {RT, RB, RA}},
5026{"subfc.", XO(31,8,0,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
5027{"sf.", XO(31,8,0,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
5028{"subc.", XO(31,8,0,1), XO_MASK, PPCCOM, 0, {RT, RB, RA}},
5029
5030{"mulhdu", XO(31,9,0,0), XO_MASK, PPC64, 0, {RT, RA, RB}},
5031{"mulhdu.", XO(31,9,0,1), XO_MASK, PPC64, 0, {RT, RA, RB}},
5032
5033{"addc", XO(31,10,0,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
5034{"a", XO(31,10,0,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
5035{"addc.", XO(31,10,0,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
5036{"a.", XO(31,10,0,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
5037
5038{"mulhwu", XO(31,11,0,0), XO_MASK, PPC, 0, {RT, RA, RB}},
5039{"mulhwu.", XO(31,11,0,1), XO_MASK, PPC, 0, {RT, RA, RB}},
5040
5041{"lxsiwzx", X(31,12), XX1_MASK, PPCVSX2, 0, {XT6, RA0, RB}},
5042
5043{"isellt", X(31,15), X_MASK, PPCISEL, 0, {RT, RA0, RB}},
5044
5045{"tlbilxlpid", XTO(31,18,0), XTO_MASK, E500MC|PPCA2, 0, {0}},
5046{"tlbilxpid", XTO(31,18,1), XTO_MASK, E500MC|PPCA2, 0, {0}},
5047{"tlbilxva", XTO(31,18,3), XTO_MASK, E500MC|PPCA2, 0, {RA0, RB}},
5048{"tlbilx", X(31,18), X_MASK, E500MC|PPCA2, 0, {T, RA0, RB}},
5049
5050{"mfcr", XFXM(31,19,0,0), XFXFXM_MASK, COM, 0, {RT, FXM4}},
5051{"mfocrf", XFXM(31,19,0,1), XFXFXM_MASK, COM, 0, {RT, FXM}},
5052
5053{"lwarx", X(31,20), XEH_MASK, PPC, 0, {RT, RA0, RB, EH}},
5054
5055{"ldx", X(31,21), X_MASK, PPC64, 0, {RT, RA0, RB}},
5056
5057{"icbt", X(31,22), X_MASK, BOOKE|PPCE300|PPCA2|PPC476, 0, {CT, RA0, RB}},
5058
5059{"lwzx", X(31,23), X_MASK, PPCCOM, 0, {RT, RA0, RB}},
5060{"lx", X(31,23), X_MASK, PWRCOM, 0, {RT, RA, RB}},
5061
5062{"slw", XRC(31,24,0), X_MASK, PPCCOM, 0, {RA, RS, RB}},
5063{"sl", XRC(31,24,0), X_MASK, PWRCOM, 0, {RA, RS, RB}},
5064{"slw.", XRC(31,24,1), X_MASK, PPCCOM, 0, {RA, RS, RB}},
5065{"sl.", XRC(31,24,1), X_MASK, PWRCOM, 0, {RA, RS, RB}},
5066
5067{"cntlzw", XRC(31,26,0), XRB_MASK, PPCCOM, 0, {RA, RS}},
5068{"cntlz", XRC(31,26,0), XRB_MASK, PWRCOM, 0, {RA, RS}},
5069{"cntlzw.", XRC(31,26,1), XRB_MASK, PPCCOM, 0, {RA, RS}},
5070{"cntlz.", XRC(31,26,1), XRB_MASK, PWRCOM, 0, {RA, RS}},
5071
5072{"sld", XRC(31,27,0), X_MASK, PPC64, 0, {RA, RS, RB}},
5073{"sld.", XRC(31,27,1), X_MASK, PPC64, 0, {RA, RS, RB}},
5074
5075{"and", XRC(31,28,0), X_MASK, COM, 0, {RA, RS, RB}},
5076{"and.", XRC(31,28,1), X_MASK, COM, 0, {RA, RS, RB}},
5077
5078{"maskg", XRC(31,29,0), X_MASK, M601, PPCA2, {RA, RS, RB}},
5079{"maskg.", XRC(31,29,1), X_MASK, M601, PPCA2, {RA, RS, RB}},
5080
5081{"ldepx", X(31,29), X_MASK, E500MC|PPCA2, 0, {RT, RA0, RB}},
5082
5083{"waitasec", X(31,30), XRTRARB_MASK, POWER8, POWER9, {0}},
5084{"wait", X(31,30), XWC_MASK, POWER9, 0, {WC}},
5085
5086{"lwepx", X(31,31), X_MASK, E500MC|PPCA2, 0, {RT, RA0, RB}},
5087
5088{"cmplw", XOPL(31,32,0), XCMPL_MASK, PPCCOM, 0, {OBF, RA, RB}},
5089{"cmpld", XOPL(31,32,1), XCMPL_MASK, PPC64, 0, {OBF, RA, RB}},
a5721ba2 5090{"cmpl", X(31,32), XCMP_MASK, PPC, 0, {BF, L32OPT, RA, RB}},
bdc70b4a 5091{"cmpl", X(31,32), XCMPL_MASK, PWRCOM, PPC, {BF, RA, RB}},
de866fcc 5092
14b57c7c
AM		 5093{"lvsr", X(31,38), X_MASK, PPCVEC, 0, {VD, RA0, RB}},
5094{"lvehx", X(31,39), X_MASK, PPCVEC, 0, {VD, RA0, RB}},
5095{"lhfcmx", APU(31,39,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},
de866fcc 5096
ac8f0f72 5097{"mviwsplt", X(31,46), X_MASK, E6500, 0, {VD, RA, RB}},
e67ed0e8 5098
14b57c7c 5099{"iselgt", X(31,47), X_MASK, PPCISEL, 0, {RT, RA0, RB}},
de866fcc 5100
14b57c7c 5101{"lvewx", X(31,71), X_MASK, PPCVEC, 0, {VD, RA0, RB}},
de866fcc 5102
14b57c7c 5103{"addg6s", XO(31,74,0,0), XO_MASK, POWER6, 0, {RT, RA, RB}},
066be9f7 5104
14b57c7c 5105{"lxsiwax", X(31,76), XX1_MASK, PPCVSX2, 0, {XT6, RA0, RB}},
c0637f3a 5106
14b57c7c 5107{"iseleq", X(31,79), X_MASK, PPCISEL, 0, {RT, RA0, RB}},
de866fcc 5108
14b57c7c 5109{"isel", XISEL(31,15), XISEL_MASK, PPCISEL|TITAN, 0, {RT, RA0, RB, CRB}},
de866fcc 5110
14b57c7c
AM		 5111{"subf", XO(31,40,0,0), XO_MASK, PPC, 0, {RT, RA, RB}},
5112{"sub", XO(31,40,0,0), XO_MASK, PPC, 0, {RT, RB, RA}},
5113{"subf.", XO(31,40,0,1), XO_MASK, PPC, 0, {RT, RA, RB}},
5114{"sub.", XO(31,40,0,1), XO_MASK, PPC, 0, {RT, RB, RA}},
de866fcc 5115
14b57c7c
AM		 5116{"mfvsrd", X(31,51), XX1RB_MASK, PPCVSX2, 0, {RA, XS6}},
5117{"mffprd", X(31,51), XX1RB_MASK|1, PPCVSX2, 0, {RA, FRS}},
5118{"mfvrd", X(31,51)|1, XX1RB_MASK|1, PPCVSX2, 0, {RA, VS}},
5119{"eratilx", X(31,51), X_MASK, PPCA2, 0, {ERAT_T, RA, RB}},
e0d602ec 5120
14b57c7c 5121{"lbarx", X(31,52), XEH_MASK, POWER8|E6500, 0, {RT, RA0, RB, EH}},
066be9f7 5122
14b57c7c 5123{"ldux", X(31,53), X_MASK, PPC64, 0, {RT, RAL, RB}},
43e65147 5124
14b57c7c 5125{"dcbst", X(31,54), XRT_MASK, PPC, 0, {RA0, RB}},
43e65147 5126
14b57c7c
AM		 5127{"lwzux", X(31,55), X_MASK, PPCCOM, 0, {RT, RAL, RB}},
5128{"lux", X(31,55), X_MASK, PWRCOM, 0, {RT, RA, RB}},
de866fcc 5129
14b57c7c
AM		 5130{"cntlzd", XRC(31,58,0), XRB_MASK, PPC64, 0, {RA, RS}},
5131{"cntlzd.", XRC(31,58,1), XRB_MASK, PPC64, 0, {RA, RS}},
de866fcc 5132
14b57c7c
AM		 5133{"andc", XRC(31,60,0), X_MASK, COM, 0, {RA, RS, RB}},
5134{"andc.", XRC(31,60,1), X_MASK, COM, 0, {RA, RS, RB}},
de866fcc 5135
14b57c7c
AM		 5136{"waitrsv", X(31,62)|(1<<21), 0xffffffff, E500MC|PPCA2, 0, {0}},
5137{"waitimpl", X(31,62)|(2<<21), 0xffffffff, E500MC|PPCA2, 0, {0}},
5138{"wait", X(31,62), XWC_MASK, E500MC|PPCA2, 0, {WC}},
43e65147 5139
14b57c7c 5140{"dcbstep", XRT(31,63,0), XRT_MASK, E500MC|PPCA2, 0, {RA0, RB}},
19a6653c 5141
14b57c7c
AM		 5142{"tdlgt", XTO(31,68,TOLGT), XTO_MASK, PPC64, 0, {RA, RB}},
5143{"tdllt", XTO(31,68,TOLLT), XTO_MASK, PPC64, 0, {RA, RB}},
5144{"tdeq", XTO(31,68,TOEQ), XTO_MASK, PPC64, 0, {RA, RB}},
5145{"tdlge", XTO(31,68,TOLGE), XTO_MASK, PPC64, 0, {RA, RB}},
5146{"tdlnl", XTO(31,68,TOLNL), XTO_MASK, PPC64, 0, {RA, RB}},
5147{"tdlle", XTO(31,68,TOLLE), XTO_MASK, PPC64, 0, {RA, RB}},
5148{"tdlng", XTO(31,68,TOLNG), XTO_MASK, PPC64, 0, {RA, RB}},
5149{"tdgt", XTO(31,68,TOGT), XTO_MASK, PPC64, 0, {RA, RB}},
5150{"tdge", XTO(31,68,TOGE), XTO_MASK, PPC64, 0, {RA, RB}},
5151{"tdnl", XTO(31,68,TONL), XTO_MASK, PPC64, 0, {RA, RB}},
5152{"tdlt", XTO(31,68,TOLT), XTO_MASK, PPC64, 0, {RA, RB}},
5153{"tdle", XTO(31,68,TOLE), XTO_MASK, PPC64, 0, {RA, RB}},
5154{"tdng", XTO(31,68,TONG), XTO_MASK, PPC64, 0, {RA, RB}},
5155{"tdne", XTO(31,68,TONE), XTO_MASK, PPC64, 0, {RA, RB}},
5156{"tdu", XTO(31,68,TOU), XTO_MASK, PPC64, 0, {RA, RB}},
5157{"td", X(31,68), X_MASK, PPC64, 0, {TO, RA, RB}},
de866fcc 5158
14b57c7c
AM		 5159{"lwfcmx", APU(31,71,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},
5160{"mulhd", XO(31,73,0,0), XO_MASK, PPC64, 0, {RT, RA, RB}},
5161{"mulhd.", XO(31,73,0,1), XO_MASK, PPC64, 0, {RT, RA, RB}},
43e65147 5162
14b57c7c
AM		 5163{"mulhw", XO(31,75,0,0), XO_MASK, PPC, 0, {RT, RA, RB}},
5164{"mulhw.", XO(31,75,0,1), XO_MASK, PPC, 0, {RT, RA, RB}},
de866fcc 5165
62adc510
AM		 5166{"dlmzb", XRC(31,78,0), X_MASK, PPC403|PPC440|PPC476|TITAN, 0, {RA, RS, RB}},
5167{"dlmzb.", XRC(31,78,1), X_MASK, PPC403|PPC440|PPC476|TITAN, 0, {RA, RS, RB}},
de866fcc 5168
14b57c7c 5169{"mtsrd", X(31,82), XRB_MASK|(1<<20), PPC64, 0, {SR, RS}},
de866fcc 5170
14b57c7c 5171{"mfmsr", X(31,83), XRARB_MASK, COM, 0, {RT}},
43e65147 5172
14b57c7c 5173{"ldarx", X(31,84), XEH_MASK, PPC64, 0, {RT, RA0, RB, EH}},
de866fcc 5174
c7a8dbf9 5175{"dcbfl", XOPL(31,86,1), XRT_MASK, POWER5, PPC476, {RA0, RB}},
a5721ba2 5176{"dcbf", X(31,86), XLRT_MASK, PPC, 0, {RA0, RB, L2OPT}},
de866fcc 5177
14b57c7c 5178{"lbzx", X(31,87), X_MASK, COM, 0, {RT, RA0, RB}},
43e65147 5179
14b57c7c 5180{"lbepx", X(31,95), X_MASK, E500MC|PPCA2, 0, {RT, RA0, RB}},
de866fcc 5181
14b57c7c 5182{"dni", XRC(31,97,1), XRB_MASK, E6500, 0, {DUI, DCTL}},
aea77599 5183
14b57c7c
AM		 5184{"lvx", X(31,103), X_MASK, PPCVEC, 0, {VD, RA0, RB}},
5185{"lqfcmx", APU(31,103,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},
de866fcc 5186
14b57c7c
AM		 5187{"neg", XO(31,104,0,0), XORB_MASK, COM, 0, {RT, RA}},
5188{"neg.", XO(31,104,0,1), XORB_MASK, COM, 0, {RT, RA}},
de866fcc 5189
14b57c7c
AM		 5190{"mul", XO(31,107,0,0), XO_MASK, M601, 0, {RT, RA, RB}},
5191{"mul.", XO(31,107,0,1), XO_MASK, M601, 0, {RT, RA, RB}},
de866fcc 5192
ac8f0f72 5193{"mvidsplt", X(31,110), X_MASK, E6500, 0, {VD, RA, RB}},
aea77599 5194
14b57c7c 5195{"mtsrdin", X(31,114), XRA_MASK, PPC64, 0, {RS, RB}},
de866fcc 5196
14b57c7c
AM		 5197{"mffprwz", X(31,115), XX1RB_MASK|1, PPCVSX2, 0, {RA, FRS}},
5198{"mfvrwz", X(31,115)|1, XX1RB_MASK|1, PPCVSX2, 0, {RA, VS}},
5199{"mfvsrwz", X(31,115), XX1RB_MASK, PPCVSX2, 0, {RA, XS6}},
c0637f3a 5200
14b57c7c 5201{"lharx", X(31,116), XEH_MASK, POWER8|E6500, 0, {RT, RA0, RB, EH}},
066be9f7 5202
14b57c7c 5203{"clf", X(31,118), XTO_MASK, POWER, 0, {RA, RB}},
de866fcc 5204
14b57c7c 5205{"lbzux", X(31,119), X_MASK, COM, 0, {RT, RAL, RB}},
43e65147 5206
14b57c7c 5207{"popcntb", X(31,122), XRB_MASK, POWER5, 0, {RA, RS}},
de866fcc 5208
14b57c7c
AM		 5209{"not", XRC(31,124,0), X_MASK, COM, 0, {RA, RS, RBS}},
5210{"nor", XRC(31,124,0), X_MASK, COM, 0, {RA, RS, RB}},
5211{"not.", XRC(31,124,1), X_MASK, COM, 0, {RA, RS, RBS}},
5212{"nor.", XRC(31,124,1), X_MASK, COM, 0, {RA, RS, RB}},
19a6653c 5213
14b57c7c 5214{"dcbfep", XRT(31,127,0), XRT_MASK, E500MC|PPCA2, 0, {RA0, RB}},
43e65147 5215
fd486b63 5216{"setb", X(31,128), XRB_MASK|(3<<16), POWER9, 0, {RT, BFA}},
a680de9a 5217
14b57c7c 5218{"wrtee", X(31,131), XRARB_MASK, PPC403|BOOKE|PPCA2|PPC476, 0, {RS}},
43e65147 5219
14b57c7c 5220{"dcbtstls", X(31,134), X_MASK, PPCCHLK|PPC476|TITAN, 0, {CT, RA0, RB}},
de866fcc 5221
14b57c7c
AM		 5222{"stvebx", X(31,135), X_MASK, PPCVEC, 0, {VS, RA0, RB}},
5223{"stbfcmx", APU(31,135,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},
de866fcc 5224
14b57c7c
AM		 5225{"subfe", XO(31,136,0,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
5226{"sfe", XO(31,136,0,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
5227{"subfe.", XO(31,136,0,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
5228{"sfe.", XO(31,136,0,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
de866fcc 5229
14b57c7c
AM		 5230{"adde", XO(31,138,0,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
5231{"ae", XO(31,138,0,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
5232{"adde.", XO(31,138,0,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
5233{"ae.", XO(31,138,0,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
de866fcc 5234
14b57c7c 5235{"stxsiwx", X(31,140), XX1_MASK, PPCVSX2, 0, {XS6, RA0, RB}},
c0637f3a 5236
14b57c7c
AM		 5237{"msgsndp", XRTRA(31,142,0,0), XRTRA_MASK, POWER8, 0, {RB}},
5238{"dcbtstlse", X(31,142), X_MASK, PPCCHLK, E500MC, {CT, RA0, RB}},
de866fcc 5239
14b57c7c
AM		 5240{"mtcr", XFXM(31,144,0xff,0), XRARB_MASK, COM, 0, {RS}},
5241{"mtcrf", XFXM(31,144,0,0), XFXFXM_MASK, COM, 0, {FXM, RS}},
5242{"mtocrf", XFXM(31,144,0,1), XFXFXM_MASK, COM, 0, {FXM, RS}},
de866fcc 5243
14b57c7c 5244{"mtmsr", X(31,146), XRLARB_MASK, COM, 0, {RS, A_L}},
de866fcc 5245
14b57c7c 5246{"mtsle", X(31,147), XRTLRARB_MASK, POWER8, 0, {L}},
c0637f3a 5247
14b57c7c
AM		 5248{"eratsx", XRC(31,147,0), X_MASK, PPCA2, 0, {RT, RA0, RB}},
5249{"eratsx.", XRC(31,147,1), X_MASK, PPCA2, 0, {RT, RA0, RB}},
e0d602ec 5250
14b57c7c 5251{"stdx", X(31,149), X_MASK, PPC64, 0, {RS, RA0, RB}},
43e65147 5252
14b57c7c 5253{"stwcx.", XRC(31,150,1), X_MASK, PPC, 0, {RS, RA0, RB}},
43e65147 5254
14b57c7c
AM		 5255{"stwx", X(31,151), X_MASK, PPCCOM, 0, {RS, RA0, RB}},
5256{"stx", X(31,151), X_MASK, PWRCOM, 0, {RS, RA, RB}},
de866fcc 5257
14b57c7c
AM		 5258{"slq", XRC(31,152,0), X_MASK, M601, 0, {RA, RS, RB}},
5259{"slq.", XRC(31,152,1), X_MASK, M601, 0, {RA, RS, RB}},
de866fcc 5260
14b57c7c
AM		 5261{"sle", XRC(31,153,0), X_MASK, M601, 0, {RA, RS, RB}},
5262{"sle.", XRC(31,153,1), X_MASK, M601, 0, {RA, RS, RB}},
de866fcc 5263
14b57c7c 5264{"prtyw", X(31,154), XRB_MASK, POWER6|PPCA2|PPC476, 0, {RA, RS}},
de866fcc 5265
14b57c7c 5266{"stdepx", X(31,157), X_MASK, E500MC|PPCA2, 0, {RS, RA0, RB}},
43e65147 5267
14b57c7c 5268{"stwepx", X(31,159), X_MASK, E500MC|PPCA2, 0, {RS, RA0, RB}},
43e65147 5269
14b57c7c 5270{"wrteei", X(31,163), XE_MASK, PPC403|BOOKE|PPCA2|PPC476, 0, {E}},
43e65147 5271
14b57c7c 5272{"dcbtls", X(31,166), X_MASK, PPCCHLK|PPC476|TITAN, 0, {CT, RA0, RB}},
de866fcc 5273
14b57c7c
AM		 5274{"stvehx", X(31,167), X_MASK, PPCVEC, 0, {VS, RA0, RB}},
5275{"sthfcmx", APU(31,167,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},
de866fcc 5276
14b57c7c 5277{"addex", ZRC(31,170,0), Z2_MASK, POWER9, 0, {RT, RA, RB, CY}},
19dfcc89 5278
14b57c7c
AM		 5279{"msgclrp", XRTRA(31,174,0,0), XRTRA_MASK, POWER8, 0, {RB}},
5280{"dcbtlse", X(31,174), X_MASK, PPCCHLK, E500MC, {CT, RA0, RB}},
de866fcc 5281
14b57c7c 5282{"mtmsrd", X(31,178), XRLARB_MASK, PPC64, 0, {RS, A_L}},
de866fcc 5283
14b57c7c
AM		 5284{"mtvsrd", X(31,179), XX1RB_MASK, PPCVSX2, 0, {XT6, RA}},
5285{"mtfprd", X(31,179), XX1RB_MASK|1, PPCVSX2, 0, {FRT, RA}},
5286{"mtvrd", X(31,179)|1, XX1RB_MASK|1, PPCVSX2, 0, {VD, RA}},
5287{"eratre", X(31,179), X_MASK, PPCA2, 0, {RT, RA, WS}},
e0d602ec 5288
14b57c7c 5289{"stdux", X(31,181), X_MASK, PPC64, 0, {RS, RAS, RB}},
de866fcc 5290
73f07bff 5291{"stqcx.", XRC(31,182,1), X_MASK|Q_MASK, POWER8, 0, {RSQ, RA0, RB}},
14b57c7c 5292{"wchkall", X(31,182), X_MASK, PPCA2, 0, {OBF}},
e0d602ec 5293
14b57c7c
AM		 5294{"stwux", X(31,183), X_MASK, PPCCOM, 0, {RS, RAS, RB}},
5295{"stux", X(31,183), X_MASK, PWRCOM, 0, {RS, RA0, RB}},
de866fcc 5296
14b57c7c
AM		 5297{"sliq", XRC(31,184,0), X_MASK, M601, 0, {RA, RS, SH}},
5298{"sliq.", XRC(31,184,1), X_MASK, M601, 0, {RA, RS, SH}},
de866fcc 5299
14b57c7c 5300{"prtyd", X(31,186), XRB_MASK, POWER6|PPCA2, 0, {RA, RS}},
252b5132 5301
14b57c7c 5302{"cmprb", X(31,192), XCMP_MASK, POWER9, 0, {BF, L, RA, RB}},
a680de9a 5303
14b57c7c 5304{"icblq.", XRC(31,198,1), X_MASK, E6500, 0, {CT, RA0, RB}},
aea77599 5305
14b57c7c
AM		 5306{"stvewx", X(31,199), X_MASK, PPCVEC, 0, {VS, RA0, RB}},
5307{"stwfcmx", APU(31,199,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},
252b5132 5308
14b57c7c
AM		 5309{"subfze", XO(31,200,0,0), XORB_MASK, PPCCOM, 0, {RT, RA}},
5310{"sfze", XO(31,200,0,0), XORB_MASK, PWRCOM, 0, {RT, RA}},
5311{"subfze.", XO(31,200,0,1), XORB_MASK, PPCCOM, 0, {RT, RA}},
5312{"sfze.", XO(31,200,0,1), XORB_MASK, PWRCOM, 0, {RT, RA}},
252b5132 5313
14b57c7c
AM		 5314{"addze", XO(31,202,0,0), XORB_MASK, PPCCOM, 0, {RT, RA}},
5315{"aze", XO(31,202,0,0), XORB_MASK, PWRCOM, 0, {RT, RA}},
5316{"addze.", XO(31,202,0,1), XORB_MASK, PPCCOM, 0, {RT, RA}},
5317{"aze.", XO(31,202,0,1), XORB_MASK, PWRCOM, 0, {RT, RA}},
418c1742 5318
14b57c7c 5319{"msgsnd", XRTRA(31,206,0,0), XRTRA_MASK, E500MC|PPCA2|POWER8, 0, {RB}},
19a6653c 5320
14b57c7c 5321{"mtsr", X(31,210), XRB_MASK|(1<<20), COM, NON32, {SR, RS}},
418c1742 5322
14b57c7c
AM		 5323{"mtfprwa", X(31,211), XX1RB_MASK|1, PPCVSX2, 0, {FRT, RA}},
5324{"mtvrwa", X(31,211)|1, XX1RB_MASK|1, PPCVSX2, 0, {VD, RA}},
5325{"mtvsrwa", X(31,211), XX1RB_MASK, PPCVSX2, 0, {XT6, RA}},
5326{"eratwe", X(31,211), X_MASK, PPCA2, 0, {RS, RA, WS}},
e0d602ec 5327
14b57c7c 5328{"ldawx.", XRC(31,212,1), X_MASK, PPCA2, 0, {RT, RA0, RB}},
e0d602ec 5329
14b57c7c 5330{"stdcx.", XRC(31,214,1), X_MASK, PPC64, 0, {RS, RA0, RB}},
43e65147 5331
14b57c7c 5332{"stbx", X(31,215), X_MASK, COM, 0, {RS, RA0, RB}},
252b5132 5333
14b57c7c
AM		 5334{"sllq", XRC(31,216,0), X_MASK, M601, 0, {RA, RS, RB}},
5335{"sllq.", XRC(31,216,1), X_MASK, M601, 0, {RA, RS, RB}},
252b5132 5336
14b57c7c
AM		 5337{"sleq", XRC(31,217,0), X_MASK, M601, 0, {RA, RS, RB}},
5338{"sleq.", XRC(31,217,1), X_MASK, M601, 0, {RA, RS, RB}},
252b5132 5339
14b57c7c 5340{"stbepx", X(31,223), X_MASK, E500MC|PPCA2, 0, {RS, RA0, RB}},
43e65147 5341
14b57c7c 5342{"cmpeqb", X(31,224), XCMPL_MASK, POWER9, 0, {BF, RA, RB}},
a680de9a 5343
14b57c7c 5344{"icblc", X(31,230), X_MASK, PPCCHLK|PPC476|TITAN, 0, {CT, RA0, RB}},
7d5b217e 5345
14b57c7c
AM		 5346{"stvx", X(31,231), X_MASK, PPCVEC, 0, {VS, RA0, RB}},
5347{"stqfcmx", APU(31,231,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},
f509565f 5348
14b57c7c
AM		 5349{"subfme", XO(31,232,0,0), XORB_MASK, PPCCOM, 0, {RT, RA}},
5350{"sfme", XO(31,232,0,0), XORB_MASK, PWRCOM, 0, {RT, RA}},
5351{"subfme.", XO(31,232,0,1), XORB_MASK, PPCCOM, 0, {RT, RA}},
5352{"sfme.", XO(31,232,0,1), XORB_MASK, PWRCOM, 0, {RT, RA}},
252b5132 5353
14b57c7c
AM		 5354{"mulld", XO(31,233,0,0), XO_MASK, PPC64, 0, {RT, RA, RB}},
5355{"mulld.", XO(31,233,0,1), XO_MASK, PPC64, 0, {RT, RA, RB}},
43e65147 5356
14b57c7c
AM		 5357{"addme", XO(31,234,0,0), XORB_MASK, PPCCOM, 0, {RT, RA}},
5358{"ame", XO(31,234,0,0), XORB_MASK, PWRCOM, 0, {RT, RA}},
5359{"addme.", XO(31,234,0,1), XORB_MASK, PPCCOM, 0, {RT, RA}},
5360{"ame.", XO(31,234,0,1), XORB_MASK, PWRCOM, 0, {RT, RA}},
252b5132 5361
14b57c7c
AM		 5362{"mullw", XO(31,235,0,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
5363{"muls", XO(31,235,0,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
5364{"mullw.", XO(31,235,0,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
5365{"muls.", XO(31,235,0,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
252b5132 5366
14b57c7c
AM		 5367{"icblce", X(31,238), X_MASK, PPCCHLK, E500MC|PPCA2, {CT, RA, RB}},
5368{"msgclr", XRTRA(31,238,0,0), XRTRA_MASK, E500MC|PPCA2|POWER8, 0, {RB}},
5369{"mtsrin", X(31,242), XRA_MASK, PPC, NON32, {RS, RB}},
bdc70b4a 5370{"mtsri", X(31,242), XRA_MASK, POWER, NON32, {RS, RB}},
418c1742 5371
14b57c7c
AM		 5372{"mtfprwz", X(31,243), XX1RB_MASK|1, PPCVSX2, 0, {FRT, RA}},
5373{"mtvrwz", X(31,243)|1, XX1RB_MASK|1, PPCVSX2, 0, {VD, RA}},
5374{"mtvsrwz", X(31,243), XX1RB_MASK, PPCVSX2, 0, {XT6, RA}},
c0637f3a 5375
14b57c7c
AM		 5376{"dcbtstt", XRT(31,246,0x10), XRT_MASK, POWER7, 0, {RA0, RB}},
5377{"dcbtst", X(31,246), X_MASK, POWER4, DCBT_EO, {RA0, RB, CT}},
5378{"dcbtst", X(31,246), X_MASK, DCBT_EO, 0, {CT, RA0, RB}},
5379{"dcbtst", X(31,246), X_MASK, PPC, POWER4|DCBT_EO, {RA0, RB}},
4fff86c5 5380
14b57c7c 5381{"stbux", X(31,247), X_MASK, COM, 0, {RS, RAS, RB}},
252b5132 5382
14b57c7c
AM		 5383{"slliq", XRC(31,248,0), X_MASK, M601, 0, {RA, RS, SH}},
5384{"slliq.", XRC(31,248,1), X_MASK, M601, 0, {RA, RS, SH}},
252b5132 5385
14b57c7c 5386{"bpermd", X(31,252), X_MASK, POWER7|PPCA2, 0, {RA, RS, RB}},
066be9f7 5387
14b57c7c 5388{"dcbtstep", XRT(31,255,0), X_MASK, E500MC|PPCA2, 0, {RT, RA0, RB}},
19a6653c 5389
14b57c7c
AM		 5390{"mfdcrx", X(31,259), X_MASK, BOOKE|PPCA2|PPC476, TITAN, {RS, RA}},
5391{"mfdcrx.", XRC(31,259,1), X_MASK, PPCA2, 0, {RS, RA}},
252b5132 5392
ac8f0f72 5393{"lvexbx", X(31,261), X_MASK, E6500, 0, {VD, RA0, RB}},
aea77599 5394
14b57c7c 5395{"icbt", X(31,262), XRT_MASK, PPC403, 0, {RA, RB}},
1ed8e1e4 5396
ac8f0f72 5397{"lvepxl", X(31,263), X_MASK, E6500, 0, {VD, RA0, RB}},
aea77599 5398
14b57c7c
AM		 5399{"ldfcmx", APU(31,263,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},
5400{"doz", XO(31,264,0,0), XO_MASK, M601, 0, {RT, RA, RB}},
5401{"doz.", XO(31,264,0,1), XO_MASK, M601, 0, {RT, RA, RB}},
252b5132 5402
14b57c7c 5403{"modud", X(31,265), X_MASK, POWER9, 0, {RT, RA, RB}},
a680de9a 5404
14b57c7c
AM		 5405{"add", XO(31,266,0,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
5406{"cax", XO(31,266,0,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
5407{"add.", XO(31,266,0,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
5408{"cax.", XO(31,266,0,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
418c1742 5409
14b57c7c 5410{"moduw", X(31,267), X_MASK, POWER9, 0, {RT, RA, RB}},
a680de9a 5411
14b57c7c
AM		 5412{"lxvx", X(31,268), XX1_MASK|1<<6, PPCVSX3, 0, {XT6, RA0, RB}},
5413{"lxvl", X(31,269), XX1_MASK, PPCVSX3, 0, {XT6, RA0, RB}},
a680de9a 5414
14b57c7c 5415{"ehpriv", X(31,270), 0xffffffff, E500MC|PPCA2, 0, {0}},
19a6653c 5416
62adc510 5417{"tlbiel", X(31,274), X_MASK|1<<20,POWER9, 0, {RB, RSO, RIC, PRS, X_R}},
a5721ba2 5418{"tlbiel", X(31,274), XRTLRA_MASK, POWER4, POWER9|PPC476, {RB, LOPT}},
418c1742 5419
14b57c7c 5420{"mfapidi", X(31,275), X_MASK, BOOKE, E500|TITAN, {RT, RA}},
1cb0a767 5421
73f07bff 5422{"lqarx", X(31,276), XEH_MASK|Q_MASK, POWER8, 0, {RTQ, RAX, RBX, EH}},
c0637f3a 5423
14b57c7c
AM		 5424{"lscbx", XRC(31,277,0), X_MASK, M601, 0, {RT, RA, RB}},
5425{"lscbx.", XRC(31,277,1), X_MASK, M601, 0, {RT, RA, RB}},
1cb0a767 5426
14b57c7c
AM		 5427{"dcbtt", XRT(31,278,0x10), XRT_MASK, POWER7, 0, {RA0, RB}},
5428{"dcbt", X(31,278), X_MASK, POWER4, DCBT_EO, {RA0, RB, CT}},
5429{"dcbt", X(31,278), X_MASK, DCBT_EO, 0, {CT, RA0, RB}},
5430{"dcbt", X(31,278), X_MASK, PPC, POWER4|DCBT_EO, {RA0, RB}},
4fff86c5 5431
14b57c7c 5432{"lhzx", X(31,279), X_MASK, COM, 0, {RT, RA0, RB}},
1cb0a767 5433
14b57c7c 5434{"cdtbcd", X(31,282), XRB_MASK, POWER6, 0, {RA, RS}},
066be9f7 5435
14b57c7c
AM		 5436{"eqv", XRC(31,284,0), X_MASK, COM, 0, {RA, RS, RB}},
5437{"eqv.", XRC(31,284,1), X_MASK, COM, 0, {RA, RS, RB}},
1cb0a767 5438
14b57c7c 5439{"lhepx", X(31,287), X_MASK, E500MC|PPCA2, 0, {RT, RA0, RB}},
1cb0a767 5440
62adc510 5441{"mfdcrux", X(31,291), X_MASK, PPC464|PPC476, 0, {RS, RA}},
1cb0a767 5442
ac8f0f72
AM		 5443{"lvexhx", X(31,293), X_MASK, E6500, 0, {VD, RA0, RB}},
5444{"lvepx", X(31,295), X_MASK, E6500, 0, {VD, RA0, RB}},
aea77599 5445
14b57c7c 5446{"lxvll", X(31,301), XX1_MASK, PPCVSX3, 0, {XT6, RA0, RB}},
a680de9a 5447
14b57c7c 5448{"mfbhrbe", X(31,302), X_MASK, POWER8, 0, {RT, BHRBE}},
c0637f3a 5449
14b57c7c
AM		 5450{"tlbie", X(31,306), X_MASK|1<<20,POWER9, TITAN, {RB, RS, RIC, PRS, X_R}},
5451{"tlbie", X(31,306), XRA_MASK, POWER7, POWER9|TITAN, {RB, RS}},
a5721ba2 5452{"tlbie", X(31,306), XRTLRA_MASK, PPC, E500|POWER7|TITAN, {RB, LOPT}},
14b57c7c 5453{"tlbi", X(31,306), XRT_MASK, POWER, 0, {RA0, RB}},
1cb0a767 5454
14b57c7c 5455{"mfvsrld", X(31,307), XX1RB_MASK, PPCVSX3, 0, {RA, XS6}},
a680de9a 5456
14b57c7c 5457{"ldmx", X(31,309), X_MASK, POWER9, 0, {RT, RA0, RB}},
a680de9a 5458
14b57c7c 5459{"eciwx", X(31,310), X_MASK, PPC, E500|TITAN, {RT, RA0, RB}},
1cb0a767 5460
14b57c7c 5461{"lhzux", X(31,311), X_MASK, COM, 0, {RT, RAL, RB}},
1cb0a767 5462
14b57c7c 5463{"cbcdtd", X(31,314), XRB_MASK, POWER6, 0, {RA, RS}},
066be9f7 5464
14b57c7c
AM		 5465{"xor", XRC(31,316,0), X_MASK, COM, 0, {RA, RS, RB}},
5466{"xor.", XRC(31,316,1), X_MASK, COM, 0, {RA, RS, RB}},
1cb0a767 5467
14b57c7c 5468{"dcbtep", XRT(31,319,0), X_MASK, E500MC|PPCA2, 0, {RT, RA0, RB}},
1cb0a767 5469
14b57c7c
AM		 5470{"mfexisr", XSPR(31,323, 64), XSPR_MASK, PPC403, 0, {RT}},
5471{"mfexier", XSPR(31,323, 66), XSPR_MASK, PPC403, 0, {RT}},
5472{"mfbr0", XSPR(31,323,128), XSPR_MASK, PPC403, 0, {RT}},
5473{"mfbr1", XSPR(31,323,129), XSPR_MASK, PPC403, 0, {RT}},
5474{"mfbr2", XSPR(31,323,130), XSPR_MASK, PPC403, 0, {RT}},
5475{"mfbr3", XSPR(31,323,131), XSPR_MASK, PPC403, 0, {RT}},
5476{"mfbr4", XSPR(31,323,132), XSPR_MASK, PPC403, 0, {RT}},
5477{"mfbr5", XSPR(31,323,133), XSPR_MASK, PPC403, 0, {RT}},
5478{"mfbr6", XSPR(31,323,134), XSPR_MASK, PPC403, 0, {RT}},
5479{"mfbr7", XSPR(31,323,135), XSPR_MASK, PPC403, 0, {RT}},
5480{"mfbear", XSPR(31,323,144), XSPR_MASK, PPC403, 0, {RT}},
5481{"mfbesr", XSPR(31,323,145), XSPR_MASK, PPC403, 0, {RT}},
5482{"mfiocr", XSPR(31,323,160), XSPR_MASK, PPC403, 0, {RT}},
5483{"mfdmacr0", XSPR(31,323,192), XSPR_MASK, PPC403, 0, {RT}},
5484{"mfdmact0", XSPR(31,323,193), XSPR_MASK, PPC403, 0, {RT}},
5485{"mfdmada0", XSPR(31,323,194), XSPR_MASK, PPC403, 0, {RT}},
5486{"mfdmasa0", XSPR(31,323,195), XSPR_MASK, PPC403, 0, {RT}},
5487{"mfdmacc0", XSPR(31,323,196), XSPR_MASK, PPC403, 0, {RT}},
5488{"mfdmacr1", XSPR(31,323,200), XSPR_MASK, PPC403, 0, {RT}},
5489{"mfdmact1", XSPR(31,323,201), XSPR_MASK, PPC403, 0, {RT}},
5490{"mfdmada1", XSPR(31,323,202), XSPR_MASK, PPC403, 0, {RT}},
5491{"mfdmasa1", XSPR(31,323,203), XSPR_MASK, PPC403, 0, {RT}},
5492{"mfdmacc1", XSPR(31,323,204), XSPR_MASK, PPC403, 0, {RT}},
5493{"mfdmacr2", XSPR(31,323,208), XSPR_MASK, PPC403, 0, {RT}},
5494{"mfdmact2", XSPR(31,323,209), XSPR_MASK, PPC403, 0, {RT}},
5495{"mfdmada2", XSPR(31,323,210), XSPR_MASK, PPC403, 0, {RT}},
5496{"mfdmasa2", XSPR(31,323,211), XSPR_MASK, PPC403, 0, {RT}},
5497{"mfdmacc2", XSPR(31,323,212), XSPR_MASK, PPC403, 0, {RT}},
5498{"mfdmacr3", XSPR(31,323,216), XSPR_MASK, PPC403, 0, {RT}},
5499{"mfdmact3", XSPR(31,323,217), XSPR_MASK, PPC403, 0, {RT}},
5500{"mfdmada3", XSPR(31,323,218), XSPR_MASK, PPC403, 0, {RT}},
5501{"mfdmasa3", XSPR(31,323,219), XSPR_MASK, PPC403, 0, {RT}},
5502{"mfdmacc3", XSPR(31,323,220), XSPR_MASK, PPC403, 0, {RT}},
5503{"mfdmasr", XSPR(31,323,224), XSPR_MASK, PPC403, 0, {RT}},
5504{"mfdcr", X(31,323), X_MASK, PPC403|BOOKE|PPCA2|PPC476, E500|TITAN, {RT, SPR}},
5505{"mfdcr.", XRC(31,323,1), X_MASK, PPCA2, 0, {RT, SPR}},
1cb0a767 5506
ac8f0f72 5507{"lvexwx", X(31,325), X_MASK, E6500, 0, {VD, RA0, RB}},
aea77599 5508
14b57c7c 5509{"dcread", X(31,326), X_MASK, PPC476|TITAN, 0, {RT, RA0, RB}},
9fe54b1c 5510
14b57c7c
AM		 5511{"div", XO(31,331,0,0), XO_MASK, M601, 0, {RT, RA, RB}},
5512{"div.", XO(31,331,0,1), XO_MASK, M601, 0, {RT, RA, RB}},
1cb0a767 5513
14b57c7c 5514{"lxvdsx", X(31,332), XX1_MASK, PPCVSX, 0, {XT6, RA0, RB}},
066be9f7 5515
14b57c7c 5516{"mfpmr", X(31,334), X_MASK, PPCPMR|PPCE300, 0, {RT, PMR}},
c03dc33b 5517{"mftmr", X(31,366), X_MASK, PPCTMR, 0, {RT, TMR}},
1cb0a767 5518
14b57c7c
AM		 5519{"slbsync", X(31,338), 0xffffffff, POWER9, 0, {0}},
5520
5521{"mfmq", XSPR(31,339, 0), XSPR_MASK, M601, 0, {RT}},
5522{"mfxer", XSPR(31,339, 1), XSPR_MASK, COM, 0, {RT}},
5523{"mfrtcu", XSPR(31,339, 4), XSPR_MASK, COM, TITAN, {RT}},
5524{"mfrtcl", XSPR(31,339, 5), XSPR_MASK, COM, TITAN, {RT}},
5525{"mfdec", XSPR(31,339, 6), XSPR_MASK, MFDEC1, 0, {RT}},
5526{"mflr", XSPR(31,339, 8), XSPR_MASK, COM, 0, {RT}},
5527{"mfctr", XSPR(31,339, 9), XSPR_MASK, COM, 0, {RT}},
5528{"mfdscr", XSPR(31,339, 17), XSPR_MASK, POWER6, 0, {RT}},
5529{"mftid", XSPR(31,339, 17), XSPR_MASK, POWER, 0, {RT}},
5530{"mfdsisr", XSPR(31,339, 18), XSPR_MASK, COM, TITAN, {RT}},
5531{"mfdar", XSPR(31,339, 19), XSPR_MASK, COM, TITAN, {RT}},
bdc70b4a 5532{"mfdec", XSPR(31,339, 22), XSPR_MASK, MFDEC2, MFDEC1, {RT}},
14b57c7c
AM		 5533{"mfsdr0", XSPR(31,339, 24), XSPR_MASK, POWER, 0, {RT}},
5534{"mfsdr1", XSPR(31,339, 25), XSPR_MASK, COM, TITAN, {RT}},
5535{"mfsrr0", XSPR(31,339, 26), XSPR_MASK, COM, 0, {RT}},
5536{"mfsrr1", XSPR(31,339, 27), XSPR_MASK, COM, 0, {RT}},
5537{"mfcfar", XSPR(31,339, 28), XSPR_MASK, POWER6, 0, {RT}},
5538{"mfpid", XSPR(31,339, 48), XSPR_MASK, BOOKE, 0, {RT}},
5539{"mfcsrr0", XSPR(31,339, 58), XSPR_MASK, BOOKE, 0, {RT}},
5540{"mfcsrr1", XSPR(31,339, 59), XSPR_MASK, BOOKE, 0, {RT}},
5541{"mfdear", XSPR(31,339, 61), XSPR_MASK, BOOKE, 0, {RT}},
5542{"mfesr", XSPR(31,339, 62), XSPR_MASK, BOOKE, 0, {RT}},
5543{"mfivpr", XSPR(31,339, 63), XSPR_MASK, BOOKE, 0, {RT}},
5544{"mfctrl", XSPR(31,339,136), XSPR_MASK, POWER4, 0, {RT}},
5545{"mfcmpa", XSPR(31,339,144), XSPR_MASK, PPC860, 0, {RT}},
5546{"mfcmpb", XSPR(31,339,145), XSPR_MASK, PPC860, 0, {RT}},
5547{"mfcmpc", XSPR(31,339,146), XSPR_MASK, PPC860, 0, {RT}},
5548{"mfcmpd", XSPR(31,339,147), XSPR_MASK, PPC860, 0, {RT}},
5549{"mficr", XSPR(31,339,148), XSPR_MASK, PPC860, 0, {RT}},
5550{"mfder", XSPR(31,339,149), XSPR_MASK, PPC860, 0, {RT}},
5551{"mfcounta", XSPR(31,339,150), XSPR_MASK, PPC860, 0, {RT}},
5552{"mfcountb", XSPR(31,339,151), XSPR_MASK, PPC860, 0, {RT}},
5553{"mfcmpe", XSPR(31,339,152), XSPR_MASK, PPC860, 0, {RT}},
5554{"mfcmpf", XSPR(31,339,153), XSPR_MASK, PPC860, 0, {RT}},
5555{"mfcmpg", XSPR(31,339,154), XSPR_MASK, PPC860, 0, {RT}},
5556{"mfcmph", XSPR(31,339,155), XSPR_MASK, PPC860, 0, {RT}},
5557{"mflctrl1", XSPR(31,339,156), XSPR_MASK, PPC860, 0, {RT}},
5558{"mflctrl2", XSPR(31,339,157), XSPR_MASK, PPC860, 0, {RT}},
5559{"mfictrl", XSPR(31,339,158), XSPR_MASK, PPC860, 0, {RT}},
5560{"mfbar", XSPR(31,339,159), XSPR_MASK, PPC860, 0, {RT}},
5561{"mfvrsave", XSPR(31,339,256), XSPR_MASK, PPCVEC, 0, {RT}},
5562{"mfusprg0", XSPR(31,339,256), XSPR_MASK, BOOKE, 0, {RT}},
5563{"mfsprg", XSPR(31,339,256), XSPRG_MASK, PPC, 0, {RT, SPRG}},
5564{"mfsprg4", XSPR(31,339,260), XSPR_MASK, PPC405|BOOKE, 0, {RT}},
5565{"mfsprg5", XSPR(31,339,261), XSPR_MASK, PPC405|BOOKE, 0, {RT}},
5566{"mfsprg6", XSPR(31,339,262), XSPR_MASK, PPC405|BOOKE, 0, {RT}},
5567{"mfsprg7", XSPR(31,339,263), XSPR_MASK, PPC405|BOOKE, 0, {RT}},
5568{"mftbu", XSPR(31,339,269), XSPR_MASK, POWER4|BOOKE, 0, {RT}},
5569{"mftb", X(31,339), X_MASK, POWER4|BOOKE, 0, {RT, TBR}},
5570{"mftbl", XSPR(31,339,268), XSPR_MASK, POWER4|BOOKE, 0, {RT}},
5571{"mfsprg0", XSPR(31,339,272), XSPR_MASK, PPC, 0, {RT}},
5572{"mfsprg1", XSPR(31,339,273), XSPR_MASK, PPC, 0, {RT}},
5573{"mfsprg2", XSPR(31,339,274), XSPR_MASK, PPC, 0, {RT}},
5574{"mfsprg3", XSPR(31,339,275), XSPR_MASK, PPC, 0, {RT}},
5575{"mfasr", XSPR(31,339,280), XSPR_MASK, PPC64, 0, {RT}},
5576{"mfear", XSPR(31,339,282), XSPR_MASK, PPC, TITAN, {RT}},
5577{"mfpir", XSPR(31,339,286), XSPR_MASK, BOOKE, 0, {RT}},
5578{"mfpvr", XSPR(31,339,287), XSPR_MASK, PPC, 0, {RT}},
5579{"mfdbsr", XSPR(31,339,304), XSPR_MASK, BOOKE, 0, {RT}},
5580{"mfdbcr0", XSPR(31,339,308), XSPR_MASK, BOOKE, 0, {RT}},
5581{"mfdbcr1", XSPR(31,339,309), XSPR_MASK, BOOKE, 0, {RT}},
5582{"mfdbcr2", XSPR(31,339,310), XSPR_MASK, BOOKE, 0, {RT}},
5583{"mfiac1", XSPR(31,339,312), XSPR_MASK, BOOKE, 0, {RT}},
5584{"mfiac2", XSPR(31,339,313), XSPR_MASK, BOOKE, 0, {RT}},
5585{"mfiac3", XSPR(31,339,314), XSPR_MASK, BOOKE, 0, {RT}},
5586{"mfiac4", XSPR(31,339,315), XSPR_MASK, BOOKE, 0, {RT}},
5587{"mfdac1", XSPR(31,339,316), XSPR_MASK, BOOKE, 0, {RT}},
5588{"mfdac2", XSPR(31,339,317), XSPR_MASK, BOOKE, 0, {RT}},
5589{"mfdvc1", XSPR(31,339,318), XSPR_MASK, BOOKE, 0, {RT}},
5590{"mfdvc2", XSPR(31,339,319), XSPR_MASK, BOOKE, 0, {RT}},
5591{"mftsr", XSPR(31,339,336), XSPR_MASK, BOOKE, 0, {RT}},
5592{"mftcr", XSPR(31,339,340), XSPR_MASK, BOOKE, 0, {RT}},
5593{"mfivor0", XSPR(31,339,400), XSPR_MASK, BOOKE, 0, {RT}},
5594{"mfivor1", XSPR(31,339,401), XSPR_MASK, BOOKE, 0, {RT}},
5595{"mfivor2", XSPR(31,339,402), XSPR_MASK, BOOKE, 0, {RT}},
5596{"mfivor3", XSPR(31,339,403), XSPR_MASK, BOOKE, 0, {RT}},
5597{"mfivor4", XSPR(31,339,404), XSPR_MASK, BOOKE, 0, {RT}},
5598{"mfivor5", XSPR(31,339,405), XSPR_MASK, BOOKE, 0, {RT}},
5599{"mfivor6", XSPR(31,339,406), XSPR_MASK, BOOKE, 0, {RT}},
5600{"mfivor7", XSPR(31,339,407), XSPR_MASK, BOOKE, 0, {RT}},
5601{"mfivor8", XSPR(31,339,408), XSPR_MASK, BOOKE, 0, {RT}},
5602{"mfivor9", XSPR(31,339,409), XSPR_MASK, BOOKE, 0, {RT}},
5603{"mfivor10", XSPR(31,339,410), XSPR_MASK, BOOKE, 0, {RT}},
5604{"mfivor11", XSPR(31,339,411), XSPR_MASK, BOOKE, 0, {RT}},
5605{"mfivor12", XSPR(31,339,412), XSPR_MASK, BOOKE, 0, {RT}},
5606{"mfivor13", XSPR(31,339,413), XSPR_MASK, BOOKE, 0, {RT}},
5607{"mfivor14", XSPR(31,339,414), XSPR_MASK, BOOKE, 0, {RT}},
5608{"mfivor15", XSPR(31,339,415), XSPR_MASK, BOOKE, 0, {RT}},
5609{"mfspefscr", XSPR(31,339,512), XSPR_MASK, PPCSPE, 0, {RT}},
5610{"mfbbear", XSPR(31,339,513), XSPR_MASK, PPCBRLK, 0, {RT}},
5611{"mfbbtar", XSPR(31,339,514), XSPR_MASK, PPCBRLK, 0, {RT}},
4b94dd2d
AM		 5612{"mfivor32", XSPR(31,339,528), XSPR_MASK, PPCSPE|E6500, 0, {RT}},
5613{"mfivor33", XSPR(31,339,529), XSPR_MASK, PPCSPE|E6500, 0, {RT}},
14b57c7c
AM		 5614{"mfivor34", XSPR(31,339,530), XSPR_MASK, PPCSPE, 0, {RT}},
5615{"mfivor35", XSPR(31,339,531), XSPR_MASK, PPCPMR, 0, {RT}},
4b94dd2d
AM		 5616{"mfibatu", XSPR(31,339,528), XSPRBAT_MASK, PPC, TITAN, {RT, SPRBAT}},
5617{"mfibatl", XSPR(31,339,529), XSPRBAT_MASK, PPC, TITAN, {RT, SPRBAT}},
14b57c7c
AM		 5618{"mfdbatu", XSPR(31,339,536), XSPRBAT_MASK, PPC, TITAN, {RT, SPRBAT}},
5619{"mfdbatl", XSPR(31,339,537), XSPRBAT_MASK, PPC, TITAN, {RT, SPRBAT}},
5620{"mfic_cst", XSPR(31,339,560), XSPR_MASK, PPC860, 0, {RT}},
5621{"mfic_adr", XSPR(31,339,561), XSPR_MASK, PPC860, 0, {RT}},
5622{"mfic_dat", XSPR(31,339,562), XSPR_MASK, PPC860, 0, {RT}},
5623{"mfdc_cst", XSPR(31,339,568), XSPR_MASK, PPC860, 0, {RT}},
5624{"mfdc_adr", XSPR(31,339,569), XSPR_MASK, PPC860, 0, {RT}},
5625{"mfdc_dat", XSPR(31,339,570), XSPR_MASK, PPC860, 0, {RT}},
5626{"mfmcsrr0", XSPR(31,339,570), XSPR_MASK, PPCRFMCI, 0, {RT}},
5627{"mfmcsrr1", XSPR(31,339,571), XSPR_MASK, PPCRFMCI, 0, {RT}},
5628{"mfmcsr", XSPR(31,339,572), XSPR_MASK, PPCRFMCI, 0, {RT}},
5629{"mfmcar", XSPR(31,339,573), XSPR_MASK, PPCRFMCI, TITAN, {RT}},
5630{"mfdpdr", XSPR(31,339,630), XSPR_MASK, PPC860, 0, {RT}},
5631{"mfdpir", XSPR(31,339,631), XSPR_MASK, PPC860, 0, {RT}},
5632{"mfimmr", XSPR(31,339,638), XSPR_MASK, PPC860, 0, {RT}},
5633{"mfmi_ctr", XSPR(31,339,784), XSPR_MASK, PPC860, 0, {RT}},
5634{"mfmi_ap", XSPR(31,339,786), XSPR_MASK, PPC860, 0, {RT}},
5635{"mfmi_epn", XSPR(31,339,787), XSPR_MASK, PPC860, 0, {RT}},
5636{"mfmi_twc", XSPR(31,339,789), XSPR_MASK, PPC860, 0, {RT}},
5637{"mfmi_rpn", XSPR(31,339,790), XSPR_MASK, PPC860, 0, {RT}},
5638{"mfmd_ctr", XSPR(31,339,792), XSPR_MASK, PPC860, 0, {RT}},
5639{"mfm_casid", XSPR(31,339,793), XSPR_MASK, PPC860, 0, {RT}},
5640{"mfmd_ap", XSPR(31,339,794), XSPR_MASK, PPC860, 0, {RT}},
5641{"mfmd_epn", XSPR(31,339,795), XSPR_MASK, PPC860, 0, {RT}},
5642{"mfmd_twb", XSPR(31,339,796), XSPR_MASK, PPC860, 0, {RT}},
5643{"mfmd_twc", XSPR(31,339,797), XSPR_MASK, PPC860, 0, {RT}},
5644{"mfmd_rpn", XSPR(31,339,798), XSPR_MASK, PPC860, 0, {RT}},
5645{"mfm_tw", XSPR(31,339,799), XSPR_MASK, PPC860, 0, {RT}},
5646{"mfmi_dbcam", XSPR(31,339,816), XSPR_MASK, PPC860, 0, {RT}},
5647{"mfmi_dbram0", XSPR(31,339,817), XSPR_MASK, PPC860, 0, {RT}},
5648{"mfmi_dbram1", XSPR(31,339,818), XSPR_MASK, PPC860, 0, {RT}},
5649{"mfmd_dbcam", XSPR(31,339,824), XSPR_MASK, PPC860, 0, {RT}},
5650{"mfmd_dbram0", XSPR(31,339,825), XSPR_MASK, PPC860, 0, {RT}},
5651{"mfmd_dbram1", XSPR(31,339,826), XSPR_MASK, PPC860, 0, {RT}},
5652{"mfivndx", XSPR(31,339,880), XSPR_MASK, TITAN, 0, {RT}},
5653{"mfdvndx", XSPR(31,339,881), XSPR_MASK, TITAN, 0, {RT}},
5654{"mfivlim", XSPR(31,339,882), XSPR_MASK, TITAN, 0, {RT}},
5655{"mfdvlim", XSPR(31,339,883), XSPR_MASK, TITAN, 0, {RT}},
5656{"mfclcsr", XSPR(31,339,884), XSPR_MASK, TITAN, 0, {RT}},
5657{"mfccr1", XSPR(31,339,888), XSPR_MASK, TITAN, 0, {RT}},
5658{"mfppr", XSPR(31,339,896), XSPR_MASK, POWER7, 0, {RT}},
5659{"mfppr32", XSPR(31,339,898), XSPR_MASK, POWER7, 0, {RT}},
5660{"mfrstcfg", XSPR(31,339,923), XSPR_MASK, TITAN, 0, {RT}},
5661{"mfdcdbtrl", XSPR(31,339,924), XSPR_MASK, TITAN, 0, {RT}},
5662{"mfdcdbtrh", XSPR(31,339,925), XSPR_MASK, TITAN, 0, {RT}},
5663{"mficdbtr", XSPR(31,339,927), XSPR_MASK, TITAN, 0, {RT}},
5664{"mfummcr0", XSPR(31,339,936), XSPR_MASK, PPC750, 0, {RT}},
5665{"mfupmc1", XSPR(31,339,937), XSPR_MASK, PPC750, 0, {RT}},
5666{"mfupmc2", XSPR(31,339,938), XSPR_MASK, PPC750, 0, {RT}},
5667{"mfusia", XSPR(31,339,939), XSPR_MASK, PPC750, 0, {RT}},
5668{"mfummcr1", XSPR(31,339,940), XSPR_MASK, PPC750, 0, {RT}},
5669{"mfupmc3", XSPR(31,339,941), XSPR_MASK, PPC750, 0, {RT}},
5670{"mfupmc4", XSPR(31,339,942), XSPR_MASK, PPC750, 0, {RT}},
5671{"mfzpr", XSPR(31,339,944), XSPR_MASK, PPC403, 0, {RT}},
5672{"mfpid", XSPR(31,339,945), XSPR_MASK, PPC403, 0, {RT}},
5673{"mfmmucr", XSPR(31,339,946), XSPR_MASK, TITAN, 0, {RT}},
5674{"mfccr0", XSPR(31,339,947), XSPR_MASK, PPC405|TITAN, 0, {RT}},
5675{"mfiac3", XSPR(31,339,948), XSPR_MASK, PPC405, 0, {RT}},
5676{"mfiac4", XSPR(31,339,949), XSPR_MASK, PPC405, 0, {RT}},
5677{"mfdvc1", XSPR(31,339,950), XSPR_MASK, PPC405, 0, {RT}},
5678{"mfdvc2", XSPR(31,339,951), XSPR_MASK, PPC405, 0, {RT}},
5679{"mfmmcr0", XSPR(31,339,952), XSPR_MASK, PPC750, 0, {RT}},
5680{"mfpmc1", XSPR(31,339,953), XSPR_MASK, PPC750, 0, {RT}},
5681{"mfsgr", XSPR(31,339,953), XSPR_MASK, PPC403, 0, {RT}},
5682{"mfdcwr", XSPR(31,339,954), XSPR_MASK, PPC403, 0, {RT}},
5683{"mfpmc2", XSPR(31,339,954), XSPR_MASK, PPC750, 0, {RT}},
5684{"mfsia", XSPR(31,339,955), XSPR_MASK, PPC750, 0, {RT}},
5685{"mfsler", XSPR(31,339,955), XSPR_MASK, PPC405, 0, {RT}},
5686{"mfmmcr1", XSPR(31,339,956), XSPR_MASK, PPC750, 0, {RT}},
5687{"mfsu0r", XSPR(31,339,956), XSPR_MASK, PPC405, 0, {RT}},
5688{"mfdbcr1", XSPR(31,339,957), XSPR_MASK, PPC405, 0, {RT}},
5689{"mfpmc3", XSPR(31,339,957), XSPR_MASK, PPC750, 0, {RT}},
5690{"mfpmc4", XSPR(31,339,958), XSPR_MASK, PPC750, 0, {RT}},
5691{"mficdbdr", XSPR(31,339,979), XSPR_MASK, PPC403|TITAN, 0, {RT}},
5692{"mfesr", XSPR(31,339,980), XSPR_MASK, PPC403, 0, {RT}},
5693{"mfdear", XSPR(31,339,981), XSPR_MASK, PPC403, 0, {RT}},
5694{"mfevpr", XSPR(31,339,982), XSPR_MASK, PPC403, 0, {RT}},
5695{"mfcdbcr", XSPR(31,339,983), XSPR_MASK, PPC403, 0, {RT}},
5696{"mftsr", XSPR(31,339,984), XSPR_MASK, PPC403, 0, {RT}},
5697{"mftcr", XSPR(31,339,986), XSPR_MASK, PPC403, 0, {RT}},
5698{"mfpit", XSPR(31,339,987), XSPR_MASK, PPC403, 0, {RT}},
5699{"mftbhi", XSPR(31,339,988), XSPR_MASK, PPC403, 0, {RT}},
5700{"mftblo", XSPR(31,339,989), XSPR_MASK, PPC403, 0, {RT}},
5701{"mfsrr2", XSPR(31,339,990), XSPR_MASK, PPC403, 0, {RT}},
5702{"mfsrr3", XSPR(31,339,991), XSPR_MASK, PPC403, 0, {RT}},
5703{"mfdbsr", XSPR(31,339,1008), XSPR_MASK, PPC403, 0, {RT}},
5704{"mfdbcr0", XSPR(31,339,1010), XSPR_MASK, PPC405, 0, {RT}},
5705{"mfdbdr", XSPR(31,339,1011), XSPR_MASK, TITAN, 0, {RS}},
5706{"mfiac1", XSPR(31,339,1012), XSPR_MASK, PPC403, 0, {RT}},
5707{"mfiac2", XSPR(31,339,1013), XSPR_MASK, PPC403, 0, {RT}},
5708{"mfdac1", XSPR(31,339,1014), XSPR_MASK, PPC403, 0, {RT}},
5709{"mfdac2", XSPR(31,339,1015), XSPR_MASK, PPC403, 0, {RT}},
5710{"mfl2cr", XSPR(31,339,1017), XSPR_MASK, PPC750, 0, {RT}},
5711{"mfdccr", XSPR(31,339,1018), XSPR_MASK, PPC403, 0, {RT}},
5712{"mficcr", XSPR(31,339,1019), XSPR_MASK, PPC403, 0, {RT}},
5713{"mfictc", XSPR(31,339,1019), XSPR_MASK, PPC750, 0, {RT}},
5714{"mfpbl1", XSPR(31,339,1020), XSPR_MASK, PPC403, 0, {RT}},
5715{"mfthrm1", XSPR(31,339,1020), XSPR_MASK, PPC750, 0, {RT}},
5716{"mfpbu1", XSPR(31,339,1021), XSPR_MASK, PPC403, 0, {RT}},
5717{"mfthrm2", XSPR(31,339,1021), XSPR_MASK, PPC750, 0, {RT}},
5718{"mfpbl2", XSPR(31,339,1022), XSPR_MASK, PPC403, 0, {RT}},
5719{"mfthrm3", XSPR(31,339,1022), XSPR_MASK, PPC750, 0, {RT}},
5720{"mfpbu2", XSPR(31,339,1023), XSPR_MASK, PPC403, 0, {RT}},
5721{"mfspr", X(31,339), X_MASK, COM, 0, {RT, SPR}},
5722
5723{"lwax", X(31,341), X_MASK, PPC64, 0, {RT, RA0, RB}},
5724
5725{"dst", XDSS(31,342,0), XDSS_MASK, PPCVEC, 0, {RA, RB, STRM}},
5726
5727{"lhax", X(31,343), X_MASK, COM, 0, {RT, RA0, RB}},
5728
5729{"lvxl", X(31,359), X_MASK, PPCVEC, 0, {VD, RA0, RB}},
5730
5731{"abs", XO(31,360,0,0), XORB_MASK, M601, 0, {RT, RA}},
5732{"abs.", XO(31,360,0,1), XORB_MASK, M601, 0, {RT, RA}},
5733
5734{"divs", XO(31,363,0,0), XO_MASK, M601, 0, {RT, RA, RB}},
5735{"divs.", XO(31,363,0,1), XO_MASK, M601, 0, {RT, RA, RB}},
5736
5737{"lxvwsx", X(31,364), XX1_MASK, PPCVSX3, 0, {XT6, RA0, RB}},
5738
5739{"tlbia", X(31,370), 0xffffffff, PPC, E500|TITAN, {0}},
1cb0a767 5740
db76a700 5741{"mftbu", XSPR(31,371,269), XSPR_MASK, PPC, NO371|POWER4, {RT}},
14b57c7c 5742{"mftb", X(31,371), X_MASK, PPC, NO371|POWER4, {RT, TBR}},
db76a700 5743{"mftbl", XSPR(31,371,268), XSPR_MASK, PPC, NO371|POWER4, {RT}},
1cb0a767 5744
14b57c7c 5745{"lwaux", X(31,373), X_MASK, PPC64, 0, {RT, RAL, RB}},
1cb0a767 5746
14b57c7c 5747{"dstst", XDSS(31,374,0), XDSS_MASK, PPCVEC, 0, {RA, RB, STRM}},
1cb0a767 5748
14b57c7c 5749{"lhaux", X(31,375), X_MASK, COM, 0, {RT, RAL, RB}},
1cb0a767 5750
14b57c7c 5751{"popcntw", X(31,378), XRB_MASK, POWER7|PPCA2, 0, {RA, RS}},
066be9f7 5752
14b57c7c
AM		 5753{"mtdcrx", X(31,387), X_MASK, BOOKE|PPCA2|PPC476, TITAN, {RA, RS}},
5754{"mtdcrx.", XRC(31,387,1), X_MASK, PPCA2, 0, {RA, RS}},
1cb0a767 5755
ac8f0f72 5756{"stvexbx", X(31,389), X_MASK, E6500, 0, {VS, RA0, RB}},
aea77599 5757
14b57c7c
AM		 5758{"dcblc", X(31,390), X_MASK, PPCCHLK|PPC476|TITAN, 0, {CT, RA0, RB}},
5759{"stdfcmx", APU(31,391,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},
1cb0a767 5760
14b57c7c
AM		 5761{"divdeu", XO(31,393,0,0), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}},
5762{"divdeu.", XO(31,393,0,1), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}},
5763{"divweu", XO(31,395,0,0), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}},
5764{"divweu.", XO(31,395,0,1), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}},
066be9f7 5765
14b57c7c
AM		 5766{"stxvx", X(31,396), XX1_MASK, PPCVSX3, 0, {XS6, RA0, RB}},
5767{"stxvl", X(31,397), XX1_MASK, PPCVSX3, 0, {XS6, RA0, RB}},
a680de9a 5768
14b57c7c 5769{"dcblce", X(31,398), X_MASK, PPCCHLK, E500MC, {CT, RA, RB}},
1cb0a767 5770
14b57c7c 5771{"slbmte", X(31,402), XRA_MASK, PPC64, 0, {RS, RB}},
1cb0a767 5772
14b57c7c 5773{"mtvsrws", X(31,403), XX1RB_MASK, PPCVSX3, 0, {XT6, RA}},
a680de9a 5774
14b57c7c 5775{"pbt.", XRC(31,404,1), X_MASK, POWER8, 0, {RS, RA0, RB}},
c0637f3a 5776
14b57c7c
AM		 5777{"icswx", XRC(31,406,0), X_MASK, POWER7|PPCA2, 0, {RS, RA, RB}},
5778{"icswx.", XRC(31,406,1), X_MASK, POWER7|PPCA2, 0, {RS, RA, RB}},
e0d602ec 5779
14b57c7c 5780{"sthx", X(31,407), X_MASK, COM, 0, {RS, RA0, RB}},
1cb0a767 5781
14b57c7c
AM		 5782{"orc", XRC(31,412,0), X_MASK, COM, 0, {RA, RS, RB}},
5783{"orc.", XRC(31,412,1), X_MASK, COM, 0, {RA, RS, RB}},
1cb0a767 5784
14b57c7c 5785{"sthepx", X(31,415), X_MASK, E500MC|PPCA2, 0, {RS, RA0, RB}},
1cb0a767 5786
62adc510 5787{"mtdcrux", X(31,419), X_MASK, PPC464|PPC476, 0, {RA, RS}},
1cb0a767 5788
ac8f0f72 5789{"stvexhx", X(31,421), X_MASK, E6500, 0, {VS, RA0, RB}},
aea77599 5790
14b57c7c 5791{"dcblq.", XRC(31,422,1), X_MASK, E6500, 0, {CT, RA0, RB}},
aea77599 5792
14b57c7c
AM		 5793{"divde", XO(31,425,0,0), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}},
5794{"divde.", XO(31,425,0,1), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}},
5795{"divwe", XO(31,427,0,0), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}},
5796{"divwe.", XO(31,427,0,1), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}},
066be9f7 5797
14b57c7c 5798{"stxvll", X(31,429), XX1_MASK, PPCVSX3, 0, {XS6, RA0, RB}},
a680de9a 5799
14b57c7c 5800{"clrbhrb", X(31,430), 0xffffffff, POWER8, 0, {0}},
c0637f3a 5801
14b57c7c 5802{"slbie", X(31,434), XRTRA_MASK, PPC64, 0, {RB}},
1cb0a767 5803
14b57c7c 5804{"mtvsrdd", X(31,435), XX1_MASK, PPCVSX3, 0, {XT6, RA0, RB}},
a680de9a 5805
14b57c7c 5806{"ecowx", X(31,438), X_MASK, PPC, E500|TITAN, {RT, RA0, RB}},
1cb0a767 5807
14b57c7c 5808{"sthux", X(31,439), X_MASK, COM, 0, {RS, RAS, RB}},
1cb0a767 5809
14b57c7c 5810{"mdors", 0x7f9ce378, 0xffffffff, E500MC, 0, {0}},
1cb0a767 5811
14b57c7c 5812{"miso", 0x7f5ad378, 0xffffffff, E6500, 0, {0}},
aea77599 5813
9f6a6cc0 5814/* The "yield", "mdoio" and "mdoom" instructions are extended mnemonics for
14b57c7c
AM		 5815 "or rX,rX,rX", with rX being r27, r29 and r30 respectively. */
5816{"yield", 0x7f7bdb78, 0xffffffff, POWER7, 0, {0}},
5817{"mdoio", 0x7fbdeb78, 0xffffffff, POWER7, 0, {0}},
5818{"mdoom", 0x7fdef378, 0xffffffff, POWER7, 0, {0}},
5819{"mr", XRC(31,444,0), X_MASK, COM, 0, {RA, RS, RBS}},
5820{"or", XRC(31,444,0), X_MASK, COM, 0, {RA, RS, RB}},
5821{"mr.", XRC(31,444,1), X_MASK, COM, 0, {RA, RS, RBS}},
5822{"or.", XRC(31,444,1), X_MASK, COM, 0, {RA, RS, RB}},
5823
5824{"mtexisr", XSPR(31,451, 64), XSPR_MASK, PPC403, 0, {RS}},
5825{"mtexier", XSPR(31,451, 66), XSPR_MASK, PPC403, 0, {RS}},
5826{"mtbr0", XSPR(31,451,128), XSPR_MASK, PPC403, 0, {RS}},
5827{"mtbr1", XSPR(31,451,129), XSPR_MASK, PPC403, 0, {RS}},
5828{"mtbr2", XSPR(31,451,130), XSPR_MASK, PPC403, 0, {RS}},
5829{"mtbr3", XSPR(31,451,131), XSPR_MASK, PPC403, 0, {RS}},
5830{"mtbr4", XSPR(31,451,132), XSPR_MASK, PPC403, 0, {RS}},
5831{"mtbr5", XSPR(31,451,133), XSPR_MASK, PPC403, 0, {RS}},
5832{"mtbr6", XSPR(31,451,134), XSPR_MASK, PPC403, 0, {RS}},
5833{"mtbr7", XSPR(31,451,135), XSPR_MASK, PPC403, 0, {RS}},
5834{"mtbear", XSPR(31,451,144), XSPR_MASK, PPC403, 0, {RS}},
5835{"mtbesr", XSPR(31,451,145), XSPR_MASK, PPC403, 0, {RS}},
5836{"mtiocr", XSPR(31,451,160), XSPR_MASK, PPC403, 0, {RS}},
5837{"mtdmacr0", XSPR(31,451,192), XSPR_MASK, PPC403, 0, {RS}},
5838{"mtdmact0", XSPR(31,451,193), XSPR_MASK, PPC403, 0, {RS}},
5839{"mtdmada0", XSPR(31,451,194), XSPR_MASK, PPC403, 0, {RS}},
5840{"mtdmasa0", XSPR(31,451,195), XSPR_MASK, PPC403, 0, {RS}},
5841{"mtdmacc0", XSPR(31,451,196), XSPR_MASK, PPC403, 0, {RS}},
5842{"mtdmacr1", XSPR(31,451,200), XSPR_MASK, PPC403, 0, {RS}},
5843{"mtdmact1", XSPR(31,451,201), XSPR_MASK, PPC403, 0, {RS}},
5844{"mtdmada1", XSPR(31,451,202), XSPR_MASK, PPC403, 0, {RS}},
5845{"mtdmasa1", XSPR(31,451,203), XSPR_MASK, PPC403, 0, {RS}},
5846{"mtdmacc1", XSPR(31,451,204), XSPR_MASK, PPC403, 0, {RS}},
5847{"mtdmacr2", XSPR(31,451,208), XSPR_MASK, PPC403, 0, {RS}},
5848{"mtdmact2", XSPR(31,451,209), XSPR_MASK, PPC403, 0, {RS}},
5849{"mtdmada2", XSPR(31,451,210), XSPR_MASK, PPC403, 0, {RS}},
5850{"mtdmasa2", XSPR(31,451,211), XSPR_MASK, PPC403, 0, {RS}},
5851{"mtdmacc2", XSPR(31,451,212), XSPR_MASK, PPC403, 0, {RS}},
5852{"mtdmacr3", XSPR(31,451,216), XSPR_MASK, PPC403, 0, {RS}},
5853{"mtdmact3", XSPR(31,451,217), XSPR_MASK, PPC403, 0, {RS}},
5854{"mtdmada3", XSPR(31,451,218), XSPR_MASK, PPC403, 0, {RS}},
5855{"mtdmasa3", XSPR(31,451,219), XSPR_MASK, PPC403, 0, {RS}},
5856{"mtdmacc3", XSPR(31,451,220), XSPR_MASK, PPC403, 0, {RS}},
5857{"mtdmasr", XSPR(31,451,224), XSPR_MASK, PPC403, 0, {RS}},
5858{"mtdcr", X(31,451), X_MASK, PPC403|BOOKE|PPCA2|PPC476, E500|TITAN, {SPR, RS}},
5859{"mtdcr.", XRC(31,451,1), X_MASK, PPCA2, 0, {SPR, RS}},
5860
ac8f0f72 5861{"stvexwx", X(31,453), X_MASK, E6500, 0, {VS, RA0, RB}},
14b57c7c 5862
62adc510 5863{"dccci", X(31,454), XRT_MASK, PPC403|PPC440|PPC476|TITAN|PPCA2, 0, {RAOPT, RBOPT}},
14b57c7c
AM		 5864{"dci", X(31,454), XRARB_MASK, PPCA2|PPC476, 0, {CT}},
5865
5866{"divdu", XO(31,457,0,0), XO_MASK, PPC64, 0, {RT, RA, RB}},
5867{"divdu.", XO(31,457,0,1), XO_MASK, PPC64, 0, {RT, RA, RB}},
5868
5869{"divwu", XO(31,459,0,0), XO_MASK, PPC, 0, {RT, RA, RB}},
5870{"divwu.", XO(31,459,0,1), XO_MASK, PPC, 0, {RT, RA, RB}},
5871
5872{"mtpmr", X(31,462), X_MASK, PPCPMR|PPCE300, 0, {PMR, RS}},
c03dc33b 5873{"mttmr", X(31,494), X_MASK, PPCTMR, 0, {TMR, RS}},
14b57c7c
AM		 5874
5875{"slbieg", X(31,466), XRA_MASK, POWER9, 0, {RS, RB}},
5876
5877{"mtmq", XSPR(31,467, 0), XSPR_MASK, M601, 0, {RS}},
5878{"mtxer", XSPR(31,467, 1), XSPR_MASK, COM, 0, {RS}},
5879{"mtlr", XSPR(31,467, 8), XSPR_MASK, COM, 0, {RS}},
5880{"mtctr", XSPR(31,467, 9), XSPR_MASK, COM, 0, {RS}},
5881{"mtdscr", XSPR(31,467, 17), XSPR_MASK, POWER6, 0, {RS}},
5882{"mttid", XSPR(31,467, 17), XSPR_MASK, POWER, 0, {RS}},
5883{"mtdsisr", XSPR(31,467, 18), XSPR_MASK, COM, TITAN, {RS}},
5884{"mtdar", XSPR(31,467, 19), XSPR_MASK, COM, TITAN, {RS}},
5885{"mtrtcu", XSPR(31,467, 20), XSPR_MASK, COM, TITAN, {RS}},
5886{"mtrtcl", XSPR(31,467, 21), XSPR_MASK, COM, TITAN, {RS}},
5887{"mtdec", XSPR(31,467, 22), XSPR_MASK, COM, 0, {RS}},
5888{"mtsdr0", XSPR(31,467, 24), XSPR_MASK, POWER, 0, {RS}},
5889{"mtsdr1", XSPR(31,467, 25), XSPR_MASK, COM, TITAN, {RS}},
5890{"mtsrr0", XSPR(31,467, 26), XSPR_MASK, COM, 0, {RS}},
5891{"mtsrr1", XSPR(31,467, 27), XSPR_MASK, COM, 0, {RS}},
5892{"mtcfar", XSPR(31,467, 28), XSPR_MASK, POWER6, 0, {RS}},
5893{"mtpid", XSPR(31,467, 48), XSPR_MASK, BOOKE, 0, {RS}},
5894{"mtdecar", XSPR(31,467, 54), XSPR_MASK, BOOKE, 0, {RS}},
5895{"mtcsrr0", XSPR(31,467, 58), XSPR_MASK, BOOKE, 0, {RS}},
5896{"mtcsrr1", XSPR(31,467, 59), XSPR_MASK, BOOKE, 0, {RS}},
5897{"mtdear", XSPR(31,467, 61), XSPR_MASK, BOOKE, 0, {RS}},
5898{"mtesr", XSPR(31,467, 62), XSPR_MASK, BOOKE, 0, {RS}},
5899{"mtivpr", XSPR(31,467, 63), XSPR_MASK, BOOKE, 0, {RS}},
5900{"mtcmpa", XSPR(31,467,144), XSPR_MASK, PPC860, 0, {RS}},
5901{"mtcmpb", XSPR(31,467,145), XSPR_MASK, PPC860, 0, {RS}},
5902{"mtcmpc", XSPR(31,467,146), XSPR_MASK, PPC860, 0, {RS}},
5903{"mtcmpd", XSPR(31,467,147), XSPR_MASK, PPC860, 0, {RS}},
5904{"mticr", XSPR(31,467,148), XSPR_MASK, PPC860, 0, {RS}},
5905{"mtder", XSPR(31,467,149), XSPR_MASK, PPC860, 0, {RS}},
5906{"mtcounta", XSPR(31,467,150), XSPR_MASK, PPC860, 0, {RS}},
5907{"mtcountb", XSPR(31,467,151), XSPR_MASK, PPC860, 0, {RS}},
5908{"mtctrl", XSPR(31,467,152), XSPR_MASK, POWER4, 0, {RS}},
5909{"mtcmpe", XSPR(31,467,152), XSPR_MASK, PPC860, 0, {RS}},
5910{"mtcmpf", XSPR(31,467,153), XSPR_MASK, PPC860, 0, {RS}},
5911{"mtcmpg", XSPR(31,467,154), XSPR_MASK, PPC860, 0, {RS}},
5912{"mtcmph", XSPR(31,467,155), XSPR_MASK, PPC860, 0, {RS}},
5913{"mtlctrl1", XSPR(31,467,156), XSPR_MASK, PPC860, 0, {RS}},
5914{"mtlctrl2", XSPR(31,467,157), XSPR_MASK, PPC860, 0, {RS}},
5915{"mtictrl", XSPR(31,467,158), XSPR_MASK, PPC860, 0, {RS}},
5916{"mtbar", XSPR(31,467,159), XSPR_MASK, PPC860, 0, {RS}},
5917{"mtvrsave", XSPR(31,467,256), XSPR_MASK, PPCVEC, 0, {RS}},
5918{"mtusprg0", XSPR(31,467,256), XSPR_MASK, BOOKE, 0, {RS}},
5919{"mtsprg", XSPR(31,467,256), XSPRG_MASK, PPC, 0, {SPRG, RS}},
5920{"mtsprg0", XSPR(31,467,272), XSPR_MASK, PPC, 0, {RS}},
5921{"mtsprg1", XSPR(31,467,273), XSPR_MASK, PPC, 0, {RS}},
5922{"mtsprg2", XSPR(31,467,274), XSPR_MASK, PPC, 0, {RS}},
5923{"mtsprg3", XSPR(31,467,275), XSPR_MASK, PPC, 0, {RS}},
5924{"mtsprg4", XSPR(31,467,276), XSPR_MASK, PPC405|BOOKE, 0, {RS}},
5925{"mtsprg5", XSPR(31,467,277), XSPR_MASK, PPC405|BOOKE, 0, {RS}},
5926{"mtsprg6", XSPR(31,467,278), XSPR_MASK, PPC405|BOOKE, 0, {RS}},
5927{"mtsprg7", XSPR(31,467,279), XSPR_MASK, PPC405|BOOKE, 0, {RS}},
5928{"mtasr", XSPR(31,467,280), XSPR_MASK, PPC64, 0, {RS}},
5929{"mtear", XSPR(31,467,282), XSPR_MASK, PPC, TITAN, {RS}},
5930{"mttbl", XSPR(31,467,284), XSPR_MASK, PPC, 0, {RS}},
5931{"mttbu", XSPR(31,467,285), XSPR_MASK, PPC, 0, {RS}},
5932{"mtdbsr", XSPR(31,467,304), XSPR_MASK, BOOKE, 0, {RS}},
5933{"mtdbcr0", XSPR(31,467,308), XSPR_MASK, BOOKE, 0, {RS}},
5934{"mtdbcr1", XSPR(31,467,309), XSPR_MASK, BOOKE, 0, {RS}},
5935{"mtdbcr2", XSPR(31,467,310), XSPR_MASK, BOOKE, 0, {RS}},
5936{"mtiac1", XSPR(31,467,312), XSPR_MASK, BOOKE, 0, {RS}},
5937{"mtiac2", XSPR(31,467,313), XSPR_MASK, BOOKE, 0, {RS}},
5938{"mtiac3", XSPR(31,467,314), XSPR_MASK, BOOKE, 0, {RS}},
5939{"mtiac4", XSPR(31,467,315), XSPR_MASK, BOOKE, 0, {RS}},
5940{"mtdac1", XSPR(31,467,316), XSPR_MASK, BOOKE, 0, {RS}},
5941{"mtdac2", XSPR(31,467,317), XSPR_MASK, BOOKE, 0, {RS}},
5942{"mtdvc1", XSPR(31,467,318), XSPR_MASK, BOOKE, 0, {RS}},
5943{"mtdvc2", XSPR(31,467,319), XSPR_MASK, BOOKE, 0, {RS}},
5944{"mttsr", XSPR(31,467,336), XSPR_MASK, BOOKE, 0, {RS}},
5945{"mttcr", XSPR(31,467,340), XSPR_MASK, BOOKE, 0, {RS}},
5946{"mtivor0", XSPR(31,467,400), XSPR_MASK, BOOKE, 0, {RS}},
5947{"mtivor1", XSPR(31,467,401), XSPR_MASK, BOOKE, 0, {RS}},
5948{"mtivor2", XSPR(31,467,402), XSPR_MASK, BOOKE, 0, {RS}},
5949{"mtivor3", XSPR(31,467,403), XSPR_MASK, BOOKE, 0, {RS}},
5950{"mtivor4", XSPR(31,467,404), XSPR_MASK, BOOKE, 0, {RS}},
5951{"mtivor5", XSPR(31,467,405), XSPR_MASK, BOOKE, 0, {RS}},
5952{"mtivor6", XSPR(31,467,406), XSPR_MASK, BOOKE, 0, {RS}},
5953{"mtivor7", XSPR(31,467,407), XSPR_MASK, BOOKE, 0, {RS}},
5954{"mtivor8", XSPR(31,467,408), XSPR_MASK, BOOKE, 0, {RS}},
5955{"mtivor9", XSPR(31,467,409), XSPR_MASK, BOOKE, 0, {RS}},
5956{"mtivor10", XSPR(31,467,410), XSPR_MASK, BOOKE, 0, {RS}},
5957{"mtivor11", XSPR(31,467,411), XSPR_MASK, BOOKE, 0, {RS}},
5958{"mtivor12", XSPR(31,467,412), XSPR_MASK, BOOKE, 0, {RS}},
5959{"mtivor13", XSPR(31,467,413), XSPR_MASK, BOOKE, 0, {RS}},
5960{"mtivor14", XSPR(31,467,414), XSPR_MASK, BOOKE, 0, {RS}},
5961{"mtivor15", XSPR(31,467,415), XSPR_MASK, BOOKE, 0, {RS}},
5962{"mtspefscr", XSPR(31,467,512), XSPR_MASK, PPCSPE, 0, {RS}},
5963{"mtbbear", XSPR(31,467,513), XSPR_MASK, PPCBRLK, 0, {RS}},
5964{"mtbbtar", XSPR(31,467,514), XSPR_MASK, PPCBRLK, 0, {RS}},
4b94dd2d
AM		 5965{"mtivor32", XSPR(31,467,528), XSPR_MASK, PPCSPE|E6500, 0, {RS}},
5966{"mtivor33", XSPR(31,467,529), XSPR_MASK, PPCSPE|E6500, 0, {RS}},
14b57c7c
AM		 5967{"mtivor34", XSPR(31,467,530), XSPR_MASK, PPCSPE, 0, {RS}},
5968{"mtivor35", XSPR(31,467,531), XSPR_MASK, PPCPMR, 0, {RS}},
4b94dd2d
AM		 5969{"mtibatu", XSPR(31,467,528), XSPRBAT_MASK, PPC, TITAN, {SPRBAT, RS}},
5970{"mtibatl", XSPR(31,467,529), XSPRBAT_MASK, PPC, TITAN, {SPRBAT, RS}},
14b57c7c
AM		 5971{"mtdbatu", XSPR(31,467,536), XSPRBAT_MASK, PPC, TITAN, {SPRBAT, RS}},
5972{"mtdbatl", XSPR(31,467,537), XSPRBAT_MASK, PPC, TITAN, {SPRBAT, RS}},
5973{"mtmcsrr0", XSPR(31,467,570), XSPR_MASK, PPCRFMCI, 0, {RS}},
5974{"mtmcsrr1", XSPR(31,467,571), XSPR_MASK, PPCRFMCI, 0, {RS}},
5975{"mtmcsr", XSPR(31,467,572), XSPR_MASK, PPCRFMCI, 0, {RS}},
5976{"mtivndx", XSPR(31,467,880), XSPR_MASK, TITAN, 0, {RS}},
5977{"mtdvndx", XSPR(31,467,881), XSPR_MASK, TITAN, 0, {RS}},
5978{"mtivlim", XSPR(31,467,882), XSPR_MASK, TITAN, 0, {RS}},
5979{"mtdvlim", XSPR(31,467,883), XSPR_MASK, TITAN, 0, {RS}},
5980{"mtclcsr", XSPR(31,467,884), XSPR_MASK, TITAN, 0, {RS}},
5981{"mtccr1", XSPR(31,467,888), XSPR_MASK, TITAN, 0, {RS}},
5982{"mtppr", XSPR(31,467,896), XSPR_MASK, POWER7, 0, {RS}},
5983{"mtppr32", XSPR(31,467,898), XSPR_MASK, POWER7, 0, {RS}},
5984{"mtummcr0", XSPR(31,467,936), XSPR_MASK, PPC750, 0, {RS}},
5985{"mtupmc1", XSPR(31,467,937), XSPR_MASK, PPC750, 0, {RS}},
5986{"mtupmc2", XSPR(31,467,938), XSPR_MASK, PPC750, 0, {RS}},
5987{"mtusia", XSPR(31,467,939), XSPR_MASK, PPC750, 0, {RS}},
5988{"mtummcr1", XSPR(31,467,940), XSPR_MASK, PPC750, 0, {RS}},
5989{"mtupmc3", XSPR(31,467,941), XSPR_MASK, PPC750, 0, {RS}},
5990{"mtupmc4", XSPR(31,467,942), XSPR_MASK, PPC750, 0, {RS}},
5991{"mtzpr", XSPR(31,467,944), XSPR_MASK, PPC403, 0, {RS}},
5992{"mtpid", XSPR(31,467,945), XSPR_MASK, PPC403, 0, {RS}},
5993{"mtrmmucr", XSPR(31,467,946), XSPR_MASK, TITAN, 0, {RS}},
5994{"mtccr0", XSPR(31,467,947), XSPR_MASK, PPC405|TITAN, 0, {RS}},
5995{"mtiac3", XSPR(31,467,948), XSPR_MASK, PPC405, 0, {RS}},
5996{"mtiac4", XSPR(31,467,949), XSPR_MASK, PPC405, 0, {RS}},
5997{"mtdvc1", XSPR(31,467,950), XSPR_MASK, PPC405, 0, {RS}},
5998{"mtdvc2", XSPR(31,467,951), XSPR_MASK, PPC405, 0, {RS}},
5999{"mtmmcr0", XSPR(31,467,952), XSPR_MASK, PPC750, 0, {RS}},
6000{"mtpmc1", XSPR(31,467,953), XSPR_MASK, PPC750, 0, {RS}},
6001{"mtsgr", XSPR(31,467,953), XSPR_MASK, PPC403, 0, {RS}},
6002{"mtdcwr", XSPR(31,467,954), XSPR_MASK, PPC403, 0, {RS}},
6003{"mtpmc2", XSPR(31,467,954), XSPR_MASK, PPC750, 0, {RS}},
6004{"mtsia", XSPR(31,467,955), XSPR_MASK, PPC750, 0, {RS}},
6005{"mtsler", XSPR(31,467,955), XSPR_MASK, PPC405, 0, {RS}},
6006{"mtmmcr1", XSPR(31,467,956), XSPR_MASK, PPC750, 0, {RS}},
6007{"mtsu0r", XSPR(31,467,956), XSPR_MASK, PPC405, 0, {RS}},
6008{"mtdbcr1", XSPR(31,467,957), XSPR_MASK, PPC405, 0, {RS}},
6009{"mtpmc3", XSPR(31,467,957), XSPR_MASK, PPC750, 0, {RS}},
6010{"mtpmc4", XSPR(31,467,958), XSPR_MASK, PPC750, 0, {RS}},
6011{"mticdbdr", XSPR(31,467,979), XSPR_MASK, PPC403, 0, {RS}},
6012{"mtesr", XSPR(31,467,980), XSPR_MASK, PPC403, 0, {RS}},
6013{"mtdear", XSPR(31,467,981), XSPR_MASK, PPC403, 0, {RS}},
6014{"mtevpr", XSPR(31,467,982), XSPR_MASK, PPC403, 0, {RS}},
6015{"mtcdbcr", XSPR(31,467,983), XSPR_MASK, PPC403, 0, {RS}},
6016{"mttsr", XSPR(31,467,984), XSPR_MASK, PPC403, 0, {RS}},
6017{"mttcr", XSPR(31,467,986), XSPR_MASK, PPC403, 0, {RS}},
6018{"mtpit", XSPR(31,467,987), XSPR_MASK, PPC403, 0, {RS}},
6019{"mttbhi", XSPR(31,467,988), XSPR_MASK, PPC403, 0, {RS}},
6020{"mttblo", XSPR(31,467,989), XSPR_MASK, PPC403, 0, {RS}},
6021{"mtsrr2", XSPR(31,467,990), XSPR_MASK, PPC403, 0, {RS}},
6022{"mtsrr3", XSPR(31,467,991), XSPR_MASK, PPC403, 0, {RS}},
6023{"mtdbsr", XSPR(31,467,1008), XSPR_MASK, PPC403, 0, {RS}},
6024{"mtdbdr", XSPR(31,467,1011), XSPR_MASK, TITAN, 0, {RS}},
6025{"mtdbcr0", XSPR(31,467,1010), XSPR_MASK, PPC405, 0, {RS}},
6026{"mtiac1", XSPR(31,467,1012), XSPR_MASK, PPC403, 0, {RS}},
6027{"mtiac2", XSPR(31,467,1013), XSPR_MASK, PPC403, 0, {RS}},
6028{"mtdac1", XSPR(31,467,1014), XSPR_MASK, PPC403, 0, {RS}},
6029{"mtdac2", XSPR(31,467,1015), XSPR_MASK, PPC403, 0, {RS}},
6030{"mtl2cr", XSPR(31,467,1017), XSPR_MASK, PPC750, 0, {RS}},
6031{"mtdccr", XSPR(31,467,1018), XSPR_MASK, PPC403, 0, {RS}},
6032{"mticcr", XSPR(31,467,1019), XSPR_MASK, PPC403, 0, {RS}},
6033{"mtictc", XSPR(31,467,1019), XSPR_MASK, PPC750, 0, {RS}},
6034{"mtpbl1", XSPR(31,467,1020), XSPR_MASK, PPC403, 0, {RS}},
6035{"mtthrm1", XSPR(31,467,1020), XSPR_MASK, PPC750, 0, {RS}},
6036{"mtpbu1", XSPR(31,467,1021), XSPR_MASK, PPC403, 0, {RS}},
6037{"mtthrm2", XSPR(31,467,1021), XSPR_MASK, PPC750, 0, {RS}},
6038{"mtpbl2", XSPR(31,467,1022), XSPR_MASK, PPC403, 0, {RS}},
6039{"mtthrm3", XSPR(31,467,1022), XSPR_MASK, PPC750, 0, {RS}},
6040{"mtpbu2", XSPR(31,467,1023), XSPR_MASK, PPC403, 0, {RS}},
6041{"mtspr", X(31,467), X_MASK, COM, 0, {SPR, RS}},
6042
6043{"dcbi", X(31,470), XRT_MASK, PPC, 0, {RA0, RB}},
6044
6045{"nand", XRC(31,476,0), X_MASK, COM, 0, {RA, RS, RB}},
6046{"nand.", XRC(31,476,1), X_MASK, COM, 0, {RA, RS, RB}},
6047
6048{"dsn", X(31,483), XRT_MASK, E500MC, 0, {RA, RB}},
6049
62adc510 6050{"dcread", X(31,486), X_MASK, PPC403|PPC440, PPCA2, {RT, RA0, RB}},
14b57c7c
AM		 6051
6052{"icbtls", X(31,486), X_MASK, PPCCHLK|PPC476|TITAN, 0, {CT, RA0, RB}},
6053
6054{"stvxl", X(31,487), X_MASK, PPCVEC, 0, {VS, RA0, RB}},
6055
6056{"nabs", XO(31,488,0,0), XORB_MASK, M601, 0, {RT, RA}},
6057{"nabs.", XO(31,488,0,1), XORB_MASK, M601, 0, {RT, RA}},
6058
6059{"divd", XO(31,489,0,0), XO_MASK, PPC64, 0, {RT, RA, RB}},
6060{"divd.", XO(31,489,0,1), XO_MASK, PPC64, 0, {RT, RA, RB}},
6061
6062{"divw", XO(31,491,0,0), XO_MASK, PPC, 0, {RT, RA, RB}},
6063{"divw.", XO(31,491,0,1), XO_MASK, PPC, 0, {RT, RA, RB}},
6064
6065{"icbtlse", X(31,494), X_MASK, PPCCHLK, E500MC, {CT, RA, RB}},
6066
6067{"slbia", X(31,498), 0xff1fffff, POWER6, 0, {IH}},
4bc0608a 6068{"slbia", X(31,498), 0xffffffff, PPC64, POWER6, {0}},
1cb0a767 6069
14b57c7c 6070{"cli", X(31,502), XRB_MASK, POWER, 0, {RT, RA}},
1cb0a767 6071
14b57c7c 6072{"popcntd", X(31,506), XRB_MASK, POWER7|PPCA2, 0, {RA, RS}},
066be9f7 6073
14b57c7c 6074{"cmpb", X(31,508), X_MASK, POWER6|PPCA2|PPC476, 0, {RA, RS, RB}},
1cb0a767 6075
14b57c7c 6076{"mcrxr", X(31,512), XBFRARB_MASK, COM, POWER7, {BF}},
252b5132 6077
dfdaec14 6078{"lbdcbx", X(31,514), X_MASK, E200Z4, 0, {RT, RA, RB}},
a8cc8a54 6079{"lbdx", X(31,515), X_MASK, E500MC|E200Z4, 0, {RT, RA, RB}},
19a6653c 6080
14b57c7c 6081{"bblels", X(31,518), X_MASK, PPCBRLK, 0, {0}},
252b5132 6082
14b57c7c
AM		 6083{"lvlx", X(31,519), X_MASK, CELL, 0, {VD, RA0, RB}},
6084{"lbfcmux", APU(31,519,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},
252b5132 6085
14b57c7c
AM		 6086{"subfco", XO(31,8,1,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
6087{"sfo", XO(31,8,1,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
6088{"subco", XO(31,8,1,0), XO_MASK, PPCCOM, 0, {RT, RB, RA}},
6089{"subfco.", XO(31,8,1,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
6090{"sfo.", XO(31,8,1,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
6091{"subco.", XO(31,8,1,1), XO_MASK, PPCCOM, 0, {RT, RB, RA}},
43e65147 6092
14b57c7c
AM		 6093{"addco", XO(31,10,1,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
6094{"ao", XO(31,10,1,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
6095{"addco.", XO(31,10,1,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
6096{"ao.", XO(31,10,1,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
252b5132 6097
14b57c7c 6098{"lxsspx", X(31,524), XX1_MASK, PPCVSX2, 0, {XT6, RA0, RB}},
c0637f3a 6099
14b57c7c 6100{"clcs", X(31,531), XRB_MASK, M601, 0, {RT, RA}},
418c1742 6101
14b57c7c 6102{"ldbrx", X(31,532), X_MASK, CELL|POWER7|PPCA2, 0, {RT, RA0, RB}},
418c1742 6103
14b57c7c
AM		 6104{"lswx", X(31,533), X_MASK, PPCCOM, E500|E500MC, {RT, RAX, RBX}},
6105{"lsx", X(31,533), X_MASK, PWRCOM, 0, {RT, RA, RB}},
252b5132 6106
14b57c7c
AM		 6107{"lwbrx", X(31,534), X_MASK, PPCCOM, 0, {RT, RA0, RB}},
6108{"lbrx", X(31,534), X_MASK, PWRCOM, 0, {RT, RA, RB}},
252b5132 6109
14b57c7c 6110{"lfsx", X(31,535), X_MASK, COM, PPCEFS, {FRT, RA0, RB}},
702f0fb4 6111
14b57c7c
AM		 6112{"srw", XRC(31,536,0), X_MASK, PPCCOM, 0, {RA, RS, RB}},
6113{"sr", XRC(31,536,0), X_MASK, PWRCOM, 0, {RA, RS, RB}},
6114{"srw.", XRC(31,536,1), X_MASK, PPCCOM, 0, {RA, RS, RB}},
6115{"sr.", XRC(31,536,1), X_MASK, PWRCOM, 0, {RA, RS, RB}},
252b5132 6116
14b57c7c
AM		 6117{"rrib", XRC(31,537,0), X_MASK, M601, 0, {RA, RS, RB}},
6118{"rrib.", XRC(31,537,1), X_MASK, M601, 0, {RA, RS, RB}},
23976049 6119
14b57c7c
AM		 6120{"cnttzw", XRC(31,538,0), XRB_MASK, POWER9, 0, {RA, RS}},
6121{"cnttzw.", XRC(31,538,1), XRB_MASK, POWER9, 0, {RA, RS}},
a680de9a 6122
14b57c7c
AM		 6123{"srd", XRC(31,539,0), X_MASK, PPC64, 0, {RA, RS, RB}},
6124{"srd.", XRC(31,539,1), X_MASK, PPC64, 0, {RA, RS, RB}},
f509565f 6125
14b57c7c
AM		 6126{"maskir", XRC(31,541,0), X_MASK, M601, 0, {RA, RS, RB}},
6127{"maskir.", XRC(31,541,1), X_MASK, M601, 0, {RA, RS, RB}},
252b5132 6128
dfdaec14 6129{"lhdcbx", X(31,546), X_MASK, E200Z4, 0, {RT, RA, RB}},
a8cc8a54 6130{"lhdx", X(31,547), X_MASK, E500MC|E200Z4, 0, {RT, RA, RB}},
19a6653c 6131
ac8f0f72 6132{"lvtrx", X(31,549), X_MASK, E6500, 0, {VD, RA0, RB}},
aea77599 6133
14b57c7c 6134{"bbelr", X(31,550), X_MASK, PPCBRLK, 0, {0}},
418c1742 6135
14b57c7c
AM		 6136{"lvrx", X(31,551), X_MASK, CELL, 0, {VD, RA0, RB}},
6137{"lhfcmux", APU(31,551,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},
252b5132 6138
14b57c7c
AM		 6139{"subfo", XO(31,40,1,0), XO_MASK, PPC, 0, {RT, RA, RB}},
6140{"subo", XO(31,40,1,0), XO_MASK, PPC, 0, {RT, RB, RA}},
6141{"subfo.", XO(31,40,1,1), XO_MASK, PPC, 0, {RT, RA, RB}},
6142{"subo.", XO(31,40,1,1), XO_MASK, PPC, 0, {RT, RB, RA}},
252b5132 6143
14b57c7c 6144{"tlbsync", X(31,566), 0xffffffff, PPC, 0, {0}},
252b5132 6145
14b57c7c 6146{"lfsux", X(31,567), X_MASK, COM, PPCEFS, {FRT, RAS, RB}},
252b5132 6147
14b57c7c
AM		 6148{"cnttzd", XRC(31,570,0), XRB_MASK, POWER9, 0, {RA, RS}},
6149{"cnttzd.", XRC(31,570,1), XRB_MASK, POWER9, 0, {RA, RS}},
a680de9a 6150
14b57c7c 6151{"mcrxrx", X(31,576), XBFRARB_MASK, POWER9, 0, {BF}},
a680de9a 6152
dfdaec14 6153{"lwdcbx", X(31,578), X_MASK, E200Z4, 0, {RT, RA, RB}},
a8cc8a54 6154{"lwdx", X(31,579), X_MASK, E500MC|E200Z4, 0, {RT, RA, RB}},
19a6653c 6155
ac8f0f72 6156{"lvtlx", X(31,581), X_MASK, E6500, 0, {VD, RA0, RB}},
aea77599 6157
14b57c7c 6158{"lwat", X(31,582), X_MASK, POWER9, 0, {RT, RA0, FC}},
a680de9a 6159
14b57c7c 6160{"lwfcmux", APU(31,583,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},
081ba1b3 6161
14b57c7c 6162{"lxsdx", X(31,588), XX1_MASK, PPCVSX, 0, {XT6, RA0, RB}},
066be9f7 6163
14b57c7c 6164{"mfsr", X(31,595), XRB_MASK|(1<<20), COM, NON32, {RT, SR}},
252b5132 6165
14b57c7c
AM		 6166{"lswi", X(31,597), X_MASK, PPCCOM, E500|E500MC, {RT, RAX, NBI}},
6167{"lsi", X(31,597), X_MASK, PWRCOM, 0, {RT, RA0, NB}},
252b5132 6168
dc302c00 6169{"hwsync", XSYNC(31,598,0), 0xffffffff, POWER4, BOOKE|PPC476, {0}},
e01d869a 6170{"lwsync", XSYNC(31,598,1), 0xffffffff, PPC, E500, {0}},
14b57c7c 6171{"ptesync", XSYNC(31,598,2), 0xffffffff, PPC64, 0, {0}},
fd486b63
PB		 6172{"sync", X(31,598), XSYNCLE_MASK, E6500, 0, {LS, ESYNC}},
6173{"sync", X(31,598), XSYNC_MASK, PPCCOM, BOOKE|PPC476, {LS}},
14b57c7c
AM		 6174{"msync", X(31,598), 0xffffffff, BOOKE|PPCA2|PPC476, 0, {0}},
6175{"sync", X(31,598), 0xffffffff, BOOKE|PPC476, E6500, {0}},
6176{"lwsync", X(31,598), 0xffffffff, E500, 0, {0}},
6177{"dcs", X(31,598), 0xffffffff, PWRCOM, 0, {0}},
418c1742 6178
14b57c7c 6179{"lfdx", X(31,599), X_MASK, COM, PPCEFS, {FRT, RA0, RB}},
23976049 6180
066be9f7 6181{"mffgpr", XRC(31,607,0), XRA_MASK, POWER6, POWER7, {FRT, RB}},
14b57c7c 6182{"lfdepx", X(31,607), X_MASK, E500MC|PPCA2, 0, {FRT, RA0, RB}},
252b5132 6183
14b57c7c 6184{"lddx", X(31,611), X_MASK, E500MC, 0, {RT, RA, RB}},
19a6653c 6185
ac8f0f72 6186{"lvswx", X(31,613), X_MASK, E6500, 0, {VD, RA0, RB}},
aea77599 6187
14b57c7c 6188{"ldat", X(31,614), X_MASK, POWER9, 0, {RT, RA0, FC}},
a680de9a 6189
14b57c7c 6190{"lqfcmux", APU(31,615,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},
081ba1b3 6191
14b57c7c
AM		 6192{"nego", XO(31,104,1,0), XORB_MASK, COM, 0, {RT, RA}},
6193{"nego.", XO(31,104,1,1), XORB_MASK, COM, 0, {RT, RA}},
252b5132 6194
14b57c7c
AM		 6195{"mulo", XO(31,107,1,0), XO_MASK, M601, 0, {RT, RA, RB}},
6196{"mulo.", XO(31,107,1,1), XO_MASK, M601, 0, {RT, RA, RB}},
252b5132 6197
14b57c7c 6198{"mfsri", X(31,627), X_MASK, M601, 0, {RT, RA, RB}},
252b5132 6199
14b57c7c 6200{"dclst", X(31,630), XRB_MASK, M601, 0, {RS, RA}},
252b5132 6201
14b57c7c 6202{"lfdux", X(31,631), X_MASK, COM, PPCEFS, {FRT, RAS, RB}},
252b5132 6203
dfdaec14 6204{"stbdcbx", X(31,642), X_MASK, E200Z4, 0, {RS, RA, RB}},
a8cc8a54 6205{"stbdx", X(31,643), X_MASK, E500MC|E200Z4, 0, {RS, RA, RB}},
19a6653c 6206
14b57c7c
AM		 6207{"stvlx", X(31,647), X_MASK, CELL, 0, {VS, RA0, RB}},
6208{"stbfcmux", APU(31,647,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},
23976049 6209
14b57c7c 6210{"stxsspx", X(31,652), XX1_MASK, PPCVSX2, 0, {XS6, RA0, RB}},
c0637f3a 6211
14b57c7c 6212{"tbegin.", XRC(31,654,1), XRTLRARB_MASK, PPCHTM, 0, {HTM_R}},
5817ffd1 6213
14b57c7c
AM		 6214{"subfeo", XO(31,136,1,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
6215{"sfeo", XO(31,136,1,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
6216{"subfeo.", XO(31,136,1,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
6217{"sfeo.", XO(31,136,1,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
252b5132 6218
14b57c7c
AM		 6219{"addeo", XO(31,138,1,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
6220{"aeo", XO(31,138,1,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
6221{"addeo.", XO(31,138,1,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
6222{"aeo.", XO(31,138,1,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
252b5132 6223
14b57c7c 6224{"mfsrin", X(31,659), XRA_MASK, PPC, NON32, {RT, RB}},
418c1742 6225
14b57c7c 6226{"stdbrx", X(31,660), X_MASK, CELL|POWER7|PPCA2, 0, {RS, RA0, RB}},
252b5132 6227
14b57c7c
AM		 6228{"stswx", X(31,661), X_MASK, PPCCOM, E500|E500MC, {RS, RA0, RB}},
6229{"stsx", X(31,661), X_MASK, PWRCOM, 0, {RS, RA0, RB}},
418c1742 6230
14b57c7c
AM		 6231{"stwbrx", X(31,662), X_MASK, PPCCOM, 0, {RS, RA0, RB}},
6232{"stbrx", X(31,662), X_MASK, PWRCOM, 0, {RS, RA0, RB}},
252b5132 6233
14b57c7c 6234{"stfsx", X(31,663), X_MASK, COM, PPCEFS, {FRS, RA0, RB}},
ede602d7 6235
14b57c7c
AM		 6236{"srq", XRC(31,664,0), X_MASK, M601, 0, {RA, RS, RB}},
6237{"srq.", XRC(31,664,1), X_MASK, M601, 0, {RA, RS, RB}},
252b5132 6238
14b57c7c
AM		 6239{"sre", XRC(31,665,0), X_MASK, M601, 0, {RA, RS, RB}},
6240{"sre.", XRC(31,665,1), X_MASK, M601, 0, {RA, RS, RB}},
252b5132 6241
dfdaec14 6242{"sthdcbx", X(31,674), X_MASK, E200Z4, 0, {RS, RA, RB}},
a8cc8a54 6243{"sthdx", X(31,675), X_MASK, E500MC|E200Z4, 0, {RS, RA, RB}},
19a6653c 6244
ac8f0f72 6245{"stvfrx", X(31,677), X_MASK, E6500, 0, {VS, RA0, RB}},
aea77599 6246
14b57c7c
AM		 6247{"stvrx", X(31,679), X_MASK, CELL, 0, {VS, RA0, RB}},
6248{"sthfcmux", APU(31,679,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},
252b5132 6249
14b57c7c
AM		 6250{"tendall.", XRC(31,686,1)|(1<<25), XRTRARB_MASK, PPCHTM, 0, {0}},
6251{"tend.", XRC(31,686,1), XRTARARB_MASK, PPCHTM, 0, {HTM_A}},
5817ffd1 6252
14b57c7c 6253{"stbcx.", XRC(31,694,1), X_MASK, POWER8|E6500, 0, {RS, RA0, RB}},
066be9f7 6254
14b57c7c 6255{"stfsux", X(31,695), X_MASK, COM, PPCEFS, {FRS, RAS, RB}},
252b5132 6256
14b57c7c
AM		 6257{"sriq", XRC(31,696,0), X_MASK, M601, 0, {RA, RS, SH}},
6258{"sriq.", XRC(31,696,1), X_MASK, M601, 0, {RA, RS, SH}},
252b5132 6259
dfdaec14 6260{"stwdcbx", X(31,706), X_MASK, E200Z4, 0, {RS, RA, RB}},
a8cc8a54 6261{"stwdx", X(31,707), X_MASK, E500MC|E200Z4, 0, {RS, RA, RB}},
19a6653c 6262
ac8f0f72 6263{"stvflx", X(31,709), X_MASK, E6500, 0, {VS, RA0, RB}},
aea77599 6264
14b57c7c 6265{"stwat", X(31,710), X_MASK, POWER9, 0, {RS, RA0, FC}},
a680de9a 6266
14b57c7c 6267{"stwfcmux", APU(31,711,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},
081ba1b3 6268
14b57c7c 6269{"stxsdx", X(31,716), XX1_MASK, PPCVSX, 0, {XS6, RA0, RB}},
066be9f7 6270
14b57c7c 6271{"tcheck", X(31,718), XRTBFRARB_MASK, PPCHTM, 0, {BF}},
5817ffd1 6272
14b57c7c
AM		 6273{"subfzeo", XO(31,200,1,0), XORB_MASK, PPCCOM, 0, {RT, RA}},
6274{"sfzeo", XO(31,200,1,0), XORB_MASK, PWRCOM, 0, {RT, RA}},
6275{"subfzeo.", XO(31,200,1,1), XORB_MASK, PPCCOM, 0, {RT, RA}},
6276{"sfzeo.", XO(31,200,1,1), XORB_MASK, PWRCOM, 0, {RT, RA}},
418c1742 6277
14b57c7c
AM		 6278{"addzeo", XO(31,202,1,0), XORB_MASK, PPCCOM, 0, {RT, RA}},
6279{"azeo", XO(31,202,1,0), XORB_MASK, PWRCOM, 0, {RT, RA}},
6280{"addzeo.", XO(31,202,1,1), XORB_MASK, PPCCOM, 0, {RT, RA}},
6281{"azeo.", XO(31,202,1,1), XORB_MASK, PWRCOM, 0, {RT, RA}},
fdd12ef3 6282
14b57c7c
AM		 6283{"stswi", X(31,725), X_MASK, PPCCOM, E500|E500MC, {RS, RA0, NB}},
6284{"stsi", X(31,725), X_MASK, PWRCOM, 0, {RS, RA0, NB}},
252b5132 6285
14b57c7c 6286{"sthcx.", XRC(31,726,1), X_MASK, POWER8|E6500, 0, {RS, RA0, RB}},
066be9f7 6287
14b57c7c 6288{"stfdx", X(31,727), X_MASK, COM, PPCEFS, {FRS, RA0, RB}},
252b5132 6289
14b57c7c
AM		 6290{"srlq", XRC(31,728,0), X_MASK, M601, 0, {RA, RS, RB}},
6291{"srlq.", XRC(31,728,1), X_MASK, M601, 0, {RA, RS, RB}},
418c1742 6292
14b57c7c
AM		 6293{"sreq", XRC(31,729,0), X_MASK, M601, 0, {RA, RS, RB}},
6294{"sreq.", XRC(31,729,1), X_MASK, M601, 0, {RA, RS, RB}},
252b5132 6295
066be9f7 6296{"mftgpr", XRC(31,735,0), XRA_MASK, POWER6, POWER7, {RT, FRB}},
14b57c7c 6297{"stfdepx", X(31,735), X_MASK, E500MC|PPCA2, 0, {FRS, RA0, RB}},
252b5132 6298
14b57c7c 6299{"stddx", X(31,739), X_MASK, E500MC, 0, {RS, RA, RB}},
19a6653c 6300
ac8f0f72 6301{"stvswx", X(31,741), X_MASK, E6500, 0, {VS, RA0, RB}},
aea77599 6302
14b57c7c 6303{"stdat", X(31,742), X_MASK, POWER9, 0, {RS, RA0, FC}},
a680de9a 6304
14b57c7c 6305{"stqfcmux", APU(31,743,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},
081ba1b3 6306
14b57c7c
AM		 6307{"subfmeo", XO(31,232,1,0), XORB_MASK, PPCCOM, 0, {RT, RA}},
6308{"sfmeo", XO(31,232,1,0), XORB_MASK, PWRCOM, 0, {RT, RA}},
6309{"subfmeo.", XO(31,232,1,1), XORB_MASK, PPCCOM, 0, {RT, RA}},
6310{"sfmeo.", XO(31,232,1,1), XORB_MASK, PWRCOM, 0, {RT, RA}},
252b5132 6311
14b57c7c
AM		 6312{"mulldo", XO(31,233,1,0), XO_MASK, PPC64, 0, {RT, RA, RB}},
6313{"mulldo.", XO(31,233,1,1), XO_MASK, PPC64, 0, {RT, RA, RB}},
252b5132 6314
14b57c7c
AM		 6315{"addmeo", XO(31,234,1,0), XORB_MASK, PPCCOM, 0, {RT, RA}},
6316{"ameo", XO(31,234,1,0), XORB_MASK, PWRCOM, 0, {RT, RA}},
6317{"addmeo.", XO(31,234,1,1), XORB_MASK, PPCCOM, 0, {RT, RA}},
6318{"ameo.", XO(31,234,1,1), XORB_MASK, PWRCOM, 0, {RT, RA}},
418c1742 6319
14b57c7c
AM		 6320{"mullwo", XO(31,235,1,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
6321{"mulso", XO(31,235,1,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
6322{"mullwo.", XO(31,235,1,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
6323{"mulso.", XO(31,235,1,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
702f0fb4 6324
14b57c7c
AM		 6325{"tsuspend.", XRCL(31,750,0,1), XRTRARB_MASK,PPCHTM, 0, {0}},
6326{"tresume.", XRCL(31,750,1,1), XRTRARB_MASK,PPCHTM, 0, {0}},
6327{"tsr.", XRC(31,750,1), XRTLRARB_MASK,PPCHTM, 0, {L}},
5817ffd1 6328
14b57c7c 6329{"darn", X(31,755), XLRAND_MASK, POWER9, 0, {RT, LRAND}},
a680de9a 6330
14b57c7c
AM		 6331{"dcba", X(31,758), XRT_MASK, PPC405|PPC7450|BOOKE|PPCA2|PPC476, 0, {RA0, RB}},
6332{"dcbal", XOPL(31,758,1), XRT_MASK, E500MC, 0, {RA0, RB}},
252b5132 6333
14b57c7c 6334{"stfdux", X(31,759), X_MASK, COM, PPCEFS, {FRS, RAS, RB}},
252b5132 6335
14b57c7c
AM		 6336{"srliq", XRC(31,760,0), X_MASK, M601, 0, {RA, RS, SH}},
6337{"srliq.", XRC(31,760,1), X_MASK, M601, 0, {RA, RS, SH}},
252b5132 6338
ac8f0f72 6339{"lvsm", X(31,773), X_MASK, E6500, 0, {VD, RA0, RB}},
a680de9a 6340
fd486b63 6341{"copy", XOPL(31,774,1), XRT_MASK, POWER9, 0, {RA0, RB}},
a680de9a 6342
ac8f0f72 6343{"stvepxl", X(31,775), X_MASK, E6500, 0, {VS, RA0, RB}},
14b57c7c
AM		 6344{"lvlxl", X(31,775), X_MASK, CELL, 0, {VD, RA0, RB}},
6345{"ldfcmux", APU(31,775,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},
ede602d7 6346
14b57c7c
AM		 6347{"dozo", XO(31,264,1,0), XO_MASK, M601, 0, {RT, RA, RB}},
6348{"dozo.", XO(31,264,1,1), XO_MASK, M601, 0, {RT, RA, RB}},
252b5132 6349
14b57c7c
AM		 6350{"addo", XO(31,266,1,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
6351{"caxo", XO(31,266,1,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
6352{"addo.", XO(31,266,1,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
6353{"caxo.", XO(31,266,1,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
252b5132 6354
14b57c7c
AM		 6355{"modsd", X(31,777), X_MASK, POWER9, 0, {RT, RA, RB}},
6356{"modsw", X(31,779), X_MASK, POWER9, 0, {RT, RA, RB}},
a680de9a 6357
14b57c7c
AM		 6358{"lxvw4x", X(31,780), XX1_MASK, PPCVSX, 0, {XT6, RA0, RB}},
6359{"lxsibzx", X(31,781), XX1_MASK, PPCVSX3, 0, {XT6, RA0, RB}},
066be9f7 6360
14b57c7c 6361{"tabortwc.", XRC(31,782,1), X_MASK, PPCHTM, 0, {TO, RA, RB}},
5817ffd1 6362
14b57c7c 6363{"tlbivax", X(31,786), XRT_MASK, BOOKE|PPCA2|PPC476, 0, {RA0, RB}},
252b5132 6364
14b57c7c 6365{"lwzcix", X(31,789), X_MASK, POWER6, 0, {RT, RA0, RB}},
252b5132 6366
14b57c7c 6367{"lhbrx", X(31,790), X_MASK, COM, 0, {RT, RA0, RB}},
252b5132 6368
73f07bff 6369{"lfdpx", X(31,791), X_MASK|Q_MASK, POWER6, POWER7, {FRTp, RA0, RB}},
14b57c7c 6370{"lfqx", X(31,791), X_MASK, POWER2, 0, {FRT, RA, RB}},
418c1742 6371
14b57c7c
AM		 6372{"sraw", XRC(31,792,0), X_MASK, PPCCOM, 0, {RA, RS, RB}},
6373{"sra", XRC(31,792,0), X_MASK, PWRCOM, 0, {RA, RS, RB}},
6374{"sraw.", XRC(31,792,1), X_MASK, PPCCOM, 0, {RA, RS, RB}},
6375{"sra.", XRC(31,792,1), X_MASK, PWRCOM, 0, {RA, RS, RB}},
fdd12ef3 6376
14b57c7c
AM		 6377{"srad", XRC(31,794,0), X_MASK, PPC64, 0, {RA, RS, RB}},
6378{"srad.", XRC(31,794,1), X_MASK, PPC64, 0, {RA, RS, RB}},
252b5132 6379
14b57c7c 6380{"lfddx", X(31,803), X_MASK, E500MC, 0, {FRT, RA, RB}},
19a6653c 6381
ac8f0f72
AM		 6382{"lvtrxl", X(31,805), X_MASK, E6500, 0, {VD, RA0, RB}},
6383{"stvepx", X(31,807), X_MASK, E6500, 0, {VS, RA0, RB}},
14b57c7c 6384{"lvrxl", X(31,807), X_MASK, CELL, 0, {VD, RA0, RB}},
252b5132 6385
14b57c7c
AM		 6386{"lxvh8x", X(31,812), XX1_MASK, PPCVSX3, 0, {XT6, RA0, RB}},
6387{"lxsihzx", X(31,813), XX1_MASK, PPCVSX3, 0, {XT6, RA0, RB}},
a680de9a 6388
14b57c7c 6389{"tabortdc.", XRC(31,814,1), X_MASK, PPCHTM, 0, {TO, RA, RB}},
5817ffd1 6390
14b57c7c 6391{"rac", X(31,818), X_MASK, M601, 0, {RT, RA, RB}},
252b5132 6392
14b57c7c 6393{"erativax", X(31,819), X_MASK, PPCA2, 0, {RS, RA0, RB}},
e0d602ec 6394
14b57c7c 6395{"lhzcix", X(31,821), X_MASK, POWER6, 0, {RT, RA0, RB}},
252b5132 6396
14b57c7c 6397{"dss", XDSS(31,822,0), XDSS_MASK, PPCVEC, 0, {STRM}},
252b5132 6398
14b57c7c 6399{"lfqux", X(31,823), X_MASK, POWER2, 0, {FRT, RA, RB}},
fdd12ef3 6400
14b57c7c
AM		 6401{"srawi", XRC(31,824,0), X_MASK, PPCCOM, 0, {RA, RS, SH}},
6402{"srai", XRC(31,824,0), X_MASK, PWRCOM, 0, {RA, RS, SH}},
6403{"srawi.", XRC(31,824,1), X_MASK, PPCCOM, 0, {RA, RS, SH}},
6404{"srai.", XRC(31,824,1), X_MASK, PWRCOM, 0, {RA, RS, SH}},
702f0fb4 6405
14b57c7c
AM		 6406{"sradi", XS(31,413,0), XS_MASK, PPC64, 0, {RA, RS, SH6}},
6407{"sradi.", XS(31,413,1), XS_MASK, PPC64, 0, {RA, RS, SH6}},
e0c21649 6408
ac8f0f72 6409{"lvtlxl", X(31,837), X_MASK, E6500, 0, {VD, RA0, RB}},
aea77599 6410
fd486b63 6411{"cpabort", X(31,838), XRTRARB_MASK,POWER9, 0, {0}},
a680de9a 6412
14b57c7c
AM		 6413{"divo", XO(31,331,1,0), XO_MASK, M601, 0, {RT, RA, RB}},
6414{"divo.", XO(31,331,1,1), XO_MASK, M601, 0, {RT, RA, RB}},
252b5132 6415
14b57c7c 6416{"lxvd2x", X(31,844), XX1_MASK, PPCVSX, 0, {XT6, RA0, RB}},
a680de9a 6417{"lxvx", X(31,844), XX1_MASK, POWER8, POWER9|PPCVSX3, {XT6, RA0, RB}},
9b4e5766 6418
14b57c7c 6419{"tabortwci.", XRC(31,846,1), X_MASK, PPCHTM, 0, {TO, RA, HTM_SI}},
5817ffd1 6420
14b57c7c 6421{"tlbsrx.", XRC(31,850,1), XRT_MASK, PPCA2, 0, {RA0, RB}},
e0d602ec 6422
fd486b63 6423{"slbiag", X(31,850), XRARB_MASK, POWER9, 0, {RS}},
14b57c7c 6424{"slbmfev", X(31,851), XRLA_MASK, POWER9, 0, {RT, RB, A_L}},
a680de9a 6425{"slbmfev", X(31,851), XRA_MASK, PPC64, POWER9, {RT, RB}},
252b5132 6426
14b57c7c 6427{"lbzcix", X(31,853), X_MASK, POWER6, 0, {RT, RA0, RB}},
418c1742 6428
9fe54b1c 6429{"eieio", X(31,854), 0xffffffff, PPC, BOOKE|PPCA2|PPC476, {0}},
14b57c7c
AM		 6430{"mbar", X(31,854), X_MASK, BOOKE|PPCA2|PPC476, 0, {MO}},
6431{"eieio", XMBAR(31,854,1),0xffffffff, E500, 0, {0}},
6432{"eieio", X(31,854), 0xffffffff, PPCA2|PPC476, 0, {0}},
418c1742 6433
14b57c7c 6434{"lfiwax", X(31,855), X_MASK, POWER6|PPCA2|PPC476, 0, {FRT, RA0, RB}},
418c1742 6435
ac8f0f72 6436{"lvswxl", X(31,869), X_MASK, E6500, 0, {VD, RA0, RB}},
aea77599 6437
14b57c7c
AM		 6438{"abso", XO(31,360,1,0), XORB_MASK, M601, 0, {RT, RA}},
6439{"abso.", XO(31,360,1,1), XORB_MASK, M601, 0, {RT, RA}},
702f0fb4 6440
14b57c7c
AM		 6441{"divso", XO(31,363,1,0), XO_MASK, M601, 0, {RT, RA, RB}},
6442{"divso.", XO(31,363,1,1), XO_MASK, M601, 0, {RT, RA, RB}},
252b5132 6443
14b57c7c 6444{"lxvb16x", X(31,876), XX1_MASK, PPCVSX3, 0, {XT6, RA0, RB}},
a680de9a 6445
14b57c7c 6446{"tabortdci.", XRC(31,878,1), X_MASK, PPCHTM, 0, {TO, RA, HTM_SI}},
5817ffd1 6447
14b57c7c 6448{"rmieg", X(31,882), XRTRA_MASK, POWER9, 0, {RB}},
a680de9a 6449
14b57c7c 6450{"ldcix", X(31,885), X_MASK, POWER6, 0, {RT, RA0, RB}},
252b5132 6451
14b57c7c 6452{"msgsync", X(31,886), 0xffffffff, POWER9, 0, {0}},
a680de9a 6453
14b57c7c 6454{"lfiwzx", X(31,887), X_MASK, POWER7|PPCA2, 0, {FRT, RA0, RB}},
066be9f7 6455
14b57c7c
AM		 6456{"extswsli", XS(31,445,0), XS_MASK, POWER9, 0, {RA, RS, SH6}},
6457{"extswsli.", XS(31,445,1), XS_MASK, POWER9, 0, {RA, RS, SH6}},
a680de9a 6458
fd486b63 6459{"paste.", XRCL(31,902,1,1),XRT_MASK, POWER9, 0, {RA0, RB}},
a680de9a 6460
14b57c7c
AM		 6461{"stvlxl", X(31,903), X_MASK, CELL, 0, {VS, RA0, RB}},
6462{"stdfcmux", APU(31,903,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},
252b5132 6463
14b57c7c
AM		 6464{"divdeuo", XO(31,393,1,0), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}},
6465{"divdeuo.", XO(31,393,1,1), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}},
6466{"divweuo", XO(31,395,1,0), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}},
6467{"divweuo.", XO(31,395,1,1), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}},
066be9f7 6468
14b57c7c
AM		 6469{"stxvw4x", X(31,908), XX1_MASK, PPCVSX, 0, {XS6, RA0, RB}},
6470{"stxsibx", X(31,909), XX1_MASK, PPCVSX3, 0, {XS6, RA0, RB}},
066be9f7 6471
14b57c7c 6472{"tabort.", XRC(31,910,1), XRTRB_MASK, PPCHTM, 0, {RA}},
5817ffd1 6473
14b57c7c
AM		 6474{"tlbsx", XRC(31,914,0), X_MASK, PPC403|BOOKE|PPCA2|PPC476, 0, {RTO, RA0, RB}},
6475{"tlbsx.", XRC(31,914,1), X_MASK, PPC403|BOOKE|PPCA2|PPC476, 0, {RTO, RA0, RB}},
252b5132 6476
14b57c7c 6477{"slbmfee", X(31,915), XRLA_MASK, POWER9, 0, {RT, RB, A_L}},
a680de9a 6478{"slbmfee", X(31,915), XRA_MASK, PPC64, POWER9, {RT, RB}},
702f0fb4 6479
14b57c7c 6480{"stwcix", X(31,917), X_MASK, POWER6, 0, {RS, RA0, RB}},
f5c120c5 6481
14b57c7c 6482{"sthbrx", X(31,918), X_MASK, COM, 0, {RS, RA0, RB}},
252b5132 6483
73f07bff 6484{"stfdpx", X(31,919), X_MASK|Q_MASK, POWER6, POWER7, {FRSp, RA0, RB}},
14b57c7c 6485{"stfqx", X(31,919), X_MASK, POWER2, 0, {FRS, RA0, RB}},
6ba045b1 6486
14b57c7c
AM		 6487{"sraq", XRC(31,920,0), X_MASK, M601, 0, {RA, RS, RB}},
6488{"sraq.", XRC(31,920,1), X_MASK, M601, 0, {RA, RS, RB}},
702f0fb4 6489
14b57c7c
AM		 6490{"srea", XRC(31,921,0), X_MASK, M601, 0, {RA, RS, RB}},
6491{"srea.", XRC(31,921,1), X_MASK, M601, 0, {RA, RS, RB}},
252b5132 6492
14b57c7c
AM		 6493{"extsh", XRC(31,922,0), XRB_MASK, PPCCOM, 0, {RA, RS}},
6494{"exts", XRC(31,922,0), XRB_MASK, PWRCOM, 0, {RA, RS}},
6495{"extsh.", XRC(31,922,1), XRB_MASK, PPCCOM, 0, {RA, RS}},
6496{"exts.", XRC(31,922,1), XRB_MASK, PWRCOM, 0, {RA, RS}},
702f0fb4 6497
14b57c7c 6498{"stfddx", X(31,931), X_MASK, E500MC, 0, {FRS, RA, RB}},
19a6653c 6499
ac8f0f72 6500{"stvfrxl", X(31,933), X_MASK, E6500, 0, {VS, RA0, RB}},
aea77599 6501
14b57c7c 6502{"wclrone", XOPL2(31,934,2),XRT_MASK, PPCA2, 0, {RA0, RB}},
a5721ba2
AM		 6503{"wclrall", X(31,934), XRARB_MASK, PPCA2, 0, {L2}},
6504{"wclr", X(31,934), X_MASK, PPCA2, 0, {L2, RA0, RB}},
85d4ac0b 6505
14b57c7c 6506{"stvrxl", X(31,935), X_MASK, CELL, 0, {VS, RA0, RB}},
6ba045b1 6507
14b57c7c
AM		 6508{"divdeo", XO(31,425,1,0), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}},
6509{"divdeo.", XO(31,425,1,1), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}},
6510{"divweo", XO(31,427,1,0), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}},
6511{"divweo.", XO(31,427,1,1), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}},
066be9f7 6512
14b57c7c
AM		 6513{"stxvh8x", X(31,940), XX1_MASK, PPCVSX3, 0, {XS6, RA0, RB}},
6514{"stxsihx", X(31,941), XX1_MASK, PPCVSX3, 0, {XS6, RA0, RB}},
a680de9a 6515
14b57c7c 6516{"treclaim.", XRC(31,942,1), XRTRB_MASK, PPCHTM, 0, {RA}},
5817ffd1 6517
e0d602ec
BE		 6518{"tlbrehi", XTLB(31,946,0), XTLB_MASK, PPC403, PPCA2, {RT, RA}},
6519{"tlbrelo", XTLB(31,946,1), XTLB_MASK, PPC403, PPCA2, {RT, RA}},
14b57c7c 6520{"tlbre", X(31,946), X_MASK, PPC403|BOOKE|PPCA2|PPC476, 0, {RSO, RAOPT, SHO}},
702f0fb4 6521
14b57c7c 6522{"sthcix", X(31,949), X_MASK, POWER6, 0, {RS, RA0, RB}},
252b5132 6523
14b57c7c
AM		 6524{"icswepx", XRC(31,950,0), X_MASK, PPCA2, 0, {RS, RA, RB}},
6525{"icswepx.", XRC(31,950,1), X_MASK, PPCA2, 0, {RS, RA, RB}},
51b5d4a8 6526
14b57c7c 6527{"stfqux", X(31,951), X_MASK, POWER2, 0, {FRS, RA, RB}},
252b5132 6528
14b57c7c
AM		 6529{"sraiq", XRC(31,952,0), X_MASK, M601, 0, {RA, RS, SH}},
6530{"sraiq.", XRC(31,952,1), X_MASK, M601, 0, {RA, RS, SH}},
252b5132 6531
14b57c7c
AM		 6532{"extsb", XRC(31,954,0), XRB_MASK, PPC, 0, {RA, RS}},
6533{"extsb.", XRC(31,954,1), XRB_MASK, PPC, 0, {RA, RS}},
252b5132 6534
ac8f0f72 6535{"stvflxl", X(31,965), X_MASK, E6500, 0, {VS, RA0, RB}},
aea77599 6536
62adc510 6537{"iccci", X(31,966), XRT_MASK, PPC403|PPC440|PPC476|TITAN|PPCA2, 0, {RAOPT, RBOPT}},
14b57c7c 6538{"ici", X(31,966), XRARB_MASK, PPCA2|PPC476, 0, {CT}},
43e65147 6539
14b57c7c
AM		 6540{"divduo", XO(31,457,1,0), XO_MASK, PPC64, 0, {RT, RA, RB}},
6541{"divduo.", XO(31,457,1,1), XO_MASK, PPC64, 0, {RT, RA, RB}},
43e65147 6542
14b57c7c
AM		 6543{"divwuo", XO(31,459,1,0), XO_MASK, PPC, 0, {RT, RA, RB}},
6544{"divwuo.", XO(31,459,1,1), XO_MASK, PPC, 0, {RT, RA, RB}},
252b5132 6545
14b57c7c 6546{"stxvd2x", X(31,972), XX1_MASK, PPCVSX, 0, {XS6, RA0, RB}},
a680de9a 6547{"stxvx", X(31,972), XX1_MASK, POWER8, POWER9|PPCVSX3, {XS6, RA0, RB}},
9b4e5766 6548
9fe54b1c 6549{"tlbld", X(31,978), XRTRA_MASK, PPC, PPC403|BOOKE|PPCA2|PPC476, {RB}},
14b57c7c
AM		 6550{"tlbwehi", XTLB(31,978,0), XTLB_MASK, PPC403, 0, {RT, RA}},
6551{"tlbwelo", XTLB(31,978,1), XTLB_MASK, PPC403, 0, {RT, RA}},
6552{"tlbwe", X(31,978), X_MASK, PPC403|BOOKE|PPCA2|PPC476, 0, {RSO, RAOPT, SHO}},
418c1742 6553
14b57c7c 6554{"slbfee.", XRC(31,979,1), XRA_MASK, POWER6, 0, {RT, RB}},
c4e676f1 6555
14b57c7c 6556{"stbcix", X(31,981), X_MASK, POWER6, 0, {RS, RA0, RB}},
252b5132 6557
14b57c7c 6558{"icbi", X(31,982), XRT_MASK, PPC, 0, {RA0, RB}},
252b5132 6559
14b57c7c 6560{"stfiwx", X(31,983), X_MASK, PPC, PPCEFS, {FRS, RA0, RB}},
702f0fb4 6561
14b57c7c
AM		 6562{"extsw", XRC(31,986,0), XRB_MASK, PPC64, 0, {RA, RS}},
6563{"extsw.", XRC(31,986,1), XRB_MASK, PPC64, 0, {RA, RS}},
252b5132 6564
14b57c7c 6565{"icbiep", XRT(31,991,0), XRT_MASK, E500MC|PPCA2, 0, {RA0, RB}},
19a6653c 6566
ac8f0f72 6567{"stvswxl", X(31,997), X_MASK, E6500, 0, {VS, RA0, RB}},
aea77599 6568
14b57c7c 6569{"icread", X(31,998), XRT_MASK, PPC403|PPC440|PPC476|TITAN, 0, {RA0, RB}},
252b5132 6570
14b57c7c
AM		 6571{"nabso", XO(31,488,1,0), XORB_MASK, M601, 0, {RT, RA}},
6572{"nabso.", XO(31,488,1,1), XORB_MASK, M601, 0, {RT, RA}},
252b5132 6573
14b57c7c
AM		 6574{"divdo", XO(31,489,1,0), XO_MASK, PPC64, 0, {RT, RA, RB}},
6575{"divdo.", XO(31,489,1,1), XO_MASK, PPC64, 0, {RT, RA, RB}},
43e65147 6576
14b57c7c
AM		 6577{"divwo", XO(31,491,1,0), XO_MASK, PPC, 0, {RT, RA, RB}},
6578{"divwo.", XO(31,491,1,1), XO_MASK, PPC, 0, {RT, RA, RB}},
418c1742 6579
14b57c7c 6580{"stxvb16x", X(31,1004), XX1_MASK, PPCVSX3, 0, {XS6, RA0, RB}},
a680de9a 6581
14b57c7c 6582{"trechkpt.", XRC(31,1006,1), XRTRARB_MASK,PPCHTM, 0, {0}},
702f0fb4 6583
14b57c7c 6584{"tlbli", X(31,1010), XRTRA_MASK, PPC, TITAN, {RB}},
252b5132 6585
14b57c7c 6586{"stdcix", X(31,1013), X_MASK, POWER6, 0, {RS, RA0, RB}},
418c1742 6587
14b57c7c
AM		 6588{"dcbz", X(31,1014), XRT_MASK, PPC, 0, {RA0, RB}},
6589{"dclz", X(31,1014), XRT_MASK, PPC, 0, {RA0, RB}},
786e2c0f 6590
14b57c7c 6591{"dcbzep", XRT(31,1023,0), XRT_MASK, E500MC|PPCA2, 0, {RA0, RB}},
ede602d7 6592
14b57c7c 6593{"dcbzl", XOPL(31,1014,1), XRT_MASK, POWER4|E500MC, PPC476, {RA0, RB}},
252b5132 6594
14b57c7c
AM		 6595{"cctpl", 0x7c210b78, 0xffffffff, CELL, 0, {0}},
6596{"cctpm", 0x7c421378, 0xffffffff, CELL, 0, {0}},
6597{"cctph", 0x7c631b78, 0xffffffff, CELL, 0, {0}},
252b5132 6598
14b57c7c
AM		 6599{"dstt", XDSS(31,342,1), XDSS_MASK, PPCVEC, 0, {RA, RB, STRM}},
6600{"dststt", XDSS(31,374,1), XDSS_MASK, PPCVEC, 0, {RA, RB, STRM}},
6601{"dssall", XDSS(31,822,1), XDSS_MASK, PPCVEC, 0, {0}},
252b5132 6602
14b57c7c
AM		 6603{"db8cyc", 0x7f9ce378, 0xffffffff, CELL, 0, {0}},
6604{"db10cyc", 0x7fbdeb78, 0xffffffff, CELL, 0, {0}},
6605{"db12cyc", 0x7fdef378, 0xffffffff, CELL, 0, {0}},
6606{"db16cyc", 0x7ffffb78, 0xffffffff, CELL, 0, {0}},
252b5132 6607
14b57c7c
AM		 6608{"lwz", OP(32), OP_MASK, PPCCOM, PPCVLE, {RT, D, RA0}},
6609{"l", OP(32), OP_MASK, PWRCOM, PPCVLE, {RT, D, RA0}},
252b5132 6610
14b57c7c
AM		 6611{"lwzu", OP(33), OP_MASK, PPCCOM, PPCVLE, {RT, D, RAL}},
6612{"lu", OP(33), OP_MASK, PWRCOM, PPCVLE, {RT, D, RA0}},
252b5132 6613
14b57c7c 6614{"lbz", OP(34), OP_MASK, COM, PPCVLE, {RT, D, RA0}},
252b5132 6615
14b57c7c 6616{"lbzu", OP(35), OP_MASK, COM, PPCVLE, {RT, D, RAL}},
252b5132 6617
14b57c7c
AM		 6618{"stw", OP(36), OP_MASK, PPCCOM, PPCVLE, {RS, D, RA0}},
6619{"st", OP(36), OP_MASK, PWRCOM, PPCVLE, {RS, D, RA0}},
252b5132 6620
14b57c7c
AM		 6621{"stwu", OP(37), OP_MASK, PPCCOM, PPCVLE, {RS, D, RAS}},
6622{"stu", OP(37), OP_MASK, PWRCOM, PPCVLE, {RS, D, RA0}},
252b5132 6623
14b57c7c 6624{"stb", OP(38), OP_MASK, COM, PPCVLE, {RS, D, RA0}},
252b5132 6625
14b57c7c 6626{"stbu", OP(39), OP_MASK, COM, PPCVLE, {RS, D, RAS}},
252b5132 6627
14b57c7c 6628{"lhz", OP(40), OP_MASK, COM, PPCVLE, {RT, D, RA0}},
252b5132 6629
14b57c7c 6630{"lhzu", OP(41), OP_MASK, COM, PPCVLE, {RT, D, RAL}},
252b5132 6631
14b57c7c 6632{"lha", OP(42), OP_MASK, COM, PPCVLE, {RT, D, RA0}},
252b5132 6633
14b57c7c 6634{"lhau", OP(43), OP_MASK, COM, PPCVLE, {RT, D, RAL}},
252b5132 6635
14b57c7c 6636{"sth", OP(44), OP_MASK, COM, PPCVLE, {RS, D, RA0}},
252b5132 6637
14b57c7c 6638{"sthu", OP(45), OP_MASK, COM, PPCVLE, {RS, D, RAS}},
252b5132 6639
14b57c7c
AM		 6640{"lmw", OP(46), OP_MASK, PPCCOM, PPCVLE, {RT, D, RAM}},
6641{"lm", OP(46), OP_MASK, PWRCOM, PPCVLE, {RT, D, RA0}},
252b5132 6642
14b57c7c
AM		 6643{"stmw", OP(47), OP_MASK, PPCCOM, PPCVLE, {RS, D, RA0}},
6644{"stm", OP(47), OP_MASK, PWRCOM, PPCVLE, {RS, D, RA0}},
252b5132 6645
14b57c7c 6646{"lfs", OP(48), OP_MASK, COM, PPCEFS|PPCVLE, {FRT, D, RA0}},
252b5132 6647
14b57c7c 6648{"lfsu", OP(49), OP_MASK, COM, PPCEFS|PPCVLE, {FRT, D, RAS}},
252b5132 6649
14b57c7c 6650{"lfd", OP(50), OP_MASK, COM, PPCEFS|PPCVLE, {FRT, D, RA0}},
252b5132 6651
14b57c7c 6652{"lfdu", OP(51), OP_MASK, COM, PPCEFS|PPCVLE, {FRT, D, RAS}},
252b5132 6653
14b57c7c 6654{"stfs", OP(52), OP_MASK, COM, PPCEFS|PPCVLE, {FRS, D, RA0}},
adadcc0c 6655
14b57c7c 6656{"stfsu", OP(53), OP_MASK, COM, PPCEFS|PPCVLE, {FRS, D, RAS}},
252b5132 6657
14b57c7c 6658{"stfd", OP(54), OP_MASK, COM, PPCEFS|PPCVLE, {FRS, D, RA0}},
c3d65c1c 6659
14b57c7c 6660{"stfdu", OP(55), OP_MASK, COM, PPCEFS|PPCVLE, {FRS, D, RAS}},
252b5132 6661
73f07bff 6662{"lq", OP(56), OP_MASK|Q_MASK, POWER4, PPC476|PPCVLE, {RTQ, DQ, RAQ}},
14b57c7c
AM		 6663{"psq_l", OP(56), OP_MASK, PPCPS, PPCVLE, {FRT,PSD,RA,PSW,PSQ}},
6664{"lfq", OP(56), OP_MASK, POWER2, PPCVLE, {FRT, D, RA0}},
418c1742 6665
14b57c7c
AM		 6666{"lxsd", DSO(57,2), DS_MASK, PPCVSX3, PPCVLE, {VD, DS, RA0}},
6667{"lxssp", DSO(57,3), DS_MASK, PPCVSX3, PPCVLE, {VD, DS, RA0}},
73f07bff 6668{"lfdp", OP(57), OP_MASK|Q_MASK, POWER6, POWER7|PPCVLE, {FRTp, DS, RA0}},
14b57c7c
AM		 6669{"psq_lu", OP(57), OP_MASK, PPCPS, PPCVLE, {FRT,PSD,RA,PSW,PSQ}},
6670{"lfqu", OP(57), OP_MASK, POWER2, PPCVLE, {FRT, D, RA0}},
802a735e 6671
14b57c7c
AM		 6672{"ld", DSO(58,0), DS_MASK, PPC64, PPCVLE, {RT, DS, RA0}},
6673{"ldu", DSO(58,1), DS_MASK, PPC64, PPCVLE, {RT, DS, RAL}},
6674{"lwa", DSO(58,2), DS_MASK, PPC64, PPCVLE, {RT, DS, RA0}},
702f0fb4 6675
14b57c7c
AM		 6676{"dadd", XRC(59,2,0), X_MASK, POWER6, PPCVLE, {FRT, FRA, FRB}},
6677{"dadd.", XRC(59,2,1), X_MASK, POWER6, PPCVLE, {FRT, FRA, FRB}},
252b5132 6678
14b57c7c
AM		 6679{"dqua", ZRC(59,3,0), Z2_MASK, POWER6, PPCVLE, {FRT,FRA,FRB,RMC}},
6680{"dqua.", ZRC(59,3,1), Z2_MASK, POWER6, PPCVLE, {FRT,FRA,FRB,RMC}},
252b5132 6681
14b57c7c
AM		 6682{"fdivs", A(59,18,0), AFRC_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRB}},
6683{"fdivs.", A(59,18,1), AFRC_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRB}},
252b5132 6684
14b57c7c
AM		 6685{"fsubs", A(59,20,0), AFRC_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRB}},
6686{"fsubs.", A(59,20,1), AFRC_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRB}},
252b5132 6687
14b57c7c
AM		 6688{"fadds", A(59,21,0), AFRC_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRB}},
6689{"fadds.", A(59,21,1), AFRC_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRB}},
252b5132 6690
14b57c7c
AM		 6691{"fsqrts", A(59,22,0), AFRAFRC_MASK, PPC, TITAN|PPCVLE, {FRT, FRB}},
6692{"fsqrts.", A(59,22,1), AFRAFRC_MASK, PPC, TITAN|PPCVLE, {FRT, FRB}},
252b5132 6693
14b57c7c
AM		 6694{"fres", A(59,24,0), AFRAFRC_MASK, POWER7, PPCVLE, {FRT, FRB}},
6695{"fres", A(59,24,0), AFRALFRC_MASK, PPC, POWER7|PPCVLE, {FRT, FRB, A_L}},
6696{"fres.", A(59,24,1), AFRAFRC_MASK, POWER7, PPCVLE, {FRT, FRB}},
6697{"fres.", A(59,24,1), AFRALFRC_MASK, PPC, POWER7|PPCVLE, {FRT, FRB, A_L}},
1ed8e1e4 6698
14b57c7c
AM		 6699{"fmuls", A(59,25,0), AFRB_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRC}},
6700{"fmuls.", A(59,25,1), AFRB_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRC}},
252b5132 6701
14b57c7c
AM		 6702{"frsqrtes", A(59,26,0), AFRAFRC_MASK, POWER7, PPCVLE, {FRT, FRB}},
6703{"frsqrtes", A(59,26,0), AFRALFRC_MASK, POWER5, POWER7|PPCVLE, {FRT, FRB, A_L}},
6704{"frsqrtes.", A(59,26,1), AFRAFRC_MASK, POWER7, PPCVLE, {FRT, FRB}},
6705{"frsqrtes.", A(59,26,1), AFRALFRC_MASK, POWER5, POWER7|PPCVLE, {FRT, FRB, A_L}},
252b5132 6706
14b57c7c
AM		 6707{"fmsubs", A(59,28,0), A_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}},
6708{"fmsubs.", A(59,28,1), A_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}},
252b5132 6709
14b57c7c
AM		 6710{"fmadds", A(59,29,0), A_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}},
6711{"fmadds.", A(59,29,1), A_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}},
252b5132 6712
14b57c7c
AM		 6713{"fnmsubs", A(59,30,0), A_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}},
6714{"fnmsubs.", A(59,30,1), A_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}},
702f0fb4 6715
14b57c7c
AM		 6716{"fnmadds", A(59,31,0), A_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}},
6717{"fnmadds.", A(59,31,1), A_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}},
702f0fb4 6718
14b57c7c
AM		 6719{"dmul", XRC(59,34,0), X_MASK, POWER6, PPCVLE, {FRT, FRA, FRB}},
6720{"dmul.", XRC(59,34,1), X_MASK, POWER6, PPCVLE, {FRT, FRA, FRB}},
702f0fb4 6721
14b57c7c
AM		 6722{"drrnd", ZRC(59,35,0), Z2_MASK, POWER6, PPCVLE, {FRT, FRA, FRB, RMC}},
6723{"drrnd.", ZRC(59,35,1), Z2_MASK, POWER6, PPCVLE, {FRT, FRA, FRB, RMC}},
702f0fb4 6724
14b57c7c
AM		 6725{"dscli", ZRC(59,66,0), Z_MASK, POWER6, PPCVLE, {FRT, FRA, SH16}},
6726{"dscli.", ZRC(59,66,1), Z_MASK, POWER6, PPCVLE, {FRT, FRA, SH16}},
702f0fb4 6727
14b57c7c
AM		 6728{"dquai", ZRC(59,67,0), Z2_MASK, POWER6, PPCVLE, {TE, FRT,FRB,RMC}},
6729{"dquai.", ZRC(59,67,1), Z2_MASK, POWER6, PPCVLE, {TE, FRT,FRB,RMC}},
702f0fb4 6730
14b57c7c
AM		 6731{"dscri", ZRC(59,98,0), Z_MASK, POWER6, PPCVLE, {FRT, FRA, SH16}},
6732{"dscri.", ZRC(59,98,1), Z_MASK, POWER6, PPCVLE, {FRT, FRA, SH16}},
702f0fb4 6733
14b57c7c
AM		 6734{"drintx", ZRC(59,99,0), Z2_MASK, POWER6, PPCVLE, {R, FRT, FRB, RMC}},
6735{"drintx.", ZRC(59,99,1), Z2_MASK, POWER6, PPCVLE, {R, FRT, FRB, RMC}},
702f0fb4 6736
14b57c7c 6737{"dcmpo", X(59,130), X_MASK, POWER6, PPCVLE, {BF, FRA, FRB}},
702f0fb4 6738
14b57c7c
AM		 6739{"dtstex", X(59,162), X_MASK, POWER6, PPCVLE, {BF, FRA, FRB}},
6740{"dtstdc", Z(59,194), Z_MASK, POWER6, PPCVLE, {BF, FRA, DCM}},
6741{"dtstdg", Z(59,226), Z_MASK, POWER6, PPCVLE, {BF, FRA, DGM}},
6742
6743{"drintn", ZRC(59,227,0), Z2_MASK, POWER6, PPCVLE, {R, FRT, FRB, RMC}},
6744{"drintn.", ZRC(59,227,1), Z2_MASK, POWER6, PPCVLE, {R, FRT, FRB, RMC}},
6745
6746{"dctdp", XRC(59,258,0), X_MASK, POWER6, PPCVLE, {FRT, FRB}},
6747{"dctdp.", XRC(59,258,1), X_MASK, POWER6, PPCVLE, {FRT, FRB}},
6748
6749{"dctfix", XRC(59,290,0), X_MASK, POWER6, PPCVLE, {FRT, FRB}},
6750{"dctfix.", XRC(59,290,1), X_MASK, POWER6, PPCVLE, {FRT, FRB}},
6751
6752{"ddedpd", XRC(59,322,0), X_MASK, POWER6, PPCVLE, {SP, FRT, FRB}},
6753{"ddedpd.", XRC(59,322,1), X_MASK, POWER6, PPCVLE, {SP, FRT, FRB}},
6754
6755{"dxex", XRC(59,354,0), X_MASK, POWER6, PPCVLE, {FRT, FRB}},
6756{"dxex.", XRC(59,354,1), X_MASK, POWER6, PPCVLE, {FRT, FRB}},
6757
6758{"dsub", XRC(59,514,0), X_MASK, POWER6, PPCVLE, {FRT, FRA, FRB}},
6759{"dsub.", XRC(59,514,1), X_MASK, POWER6, PPCVLE, {FRT, FRA, FRB}},
6760
6761{"ddiv", XRC(59,546,0), X_MASK, POWER6, PPCVLE, {FRT, FRA, FRB}},
6762{"ddiv.", XRC(59,546,1), X_MASK, POWER6, PPCVLE, {FRT, FRA, FRB}},
6763
6764{"dcmpu", X(59,642), X_MASK, POWER6, PPCVLE, {BF, FRA, FRB}},
6765
6766{"dtstsf", X(59,674), X_MASK, POWER6, PPCVLE, {BF, FRA, FRB}},
6767{"dtstsfi", X(59,675), X_MASK|1<<22,POWER9, PPCVLE, {BF, UIM6, FRB}},
6768
6769{"drsp", XRC(59,770,0), X_MASK, POWER6, PPCVLE, {FRT, FRB}},
6770{"drsp.", XRC(59,770,1), X_MASK, POWER6, PPCVLE, {FRT, FRB}},
6771
6772{"dcffix", XRC(59,802,0), X_MASK|FRA_MASK, POWER7, PPCVLE, {FRT, FRB}},
6773{"dcffix.", XRC(59,802,1), X_MASK|FRA_MASK, POWER7, PPCVLE, {FRT, FRB}},
6774
6775{"denbcd", XRC(59,834,0), X_MASK, POWER6, PPCVLE, {S, FRT, FRB}},
6776{"denbcd.", XRC(59,834,1), X_MASK, POWER6, PPCVLE, {S, FRT, FRB}},
6777
6778{"fcfids", XRC(59,846,0), XRA_MASK, POWER7|PPCA2, PPCVLE, {FRT, FRB}},
6779{"fcfids.", XRC(59,846,1), XRA_MASK, POWER7|PPCA2, PPCVLE, {FRT, FRB}},
6780
6781{"diex", XRC(59,866,0), X_MASK, POWER6, PPCVLE, {FRT, FRA, FRB}},
6782{"diex.", XRC(59,866,1), X_MASK, POWER6, PPCVLE, {FRT, FRA, FRB}},
6783
6784{"fcfidus", XRC(59,974,0), XRA_MASK, POWER7|PPCA2, PPCVLE, {FRT, FRB}},
6785{"fcfidus.", XRC(59,974,1), XRA_MASK, POWER7|PPCA2, PPCVLE, {FRT, FRB}},
6786
6787{"xsaddsp", XX3(60,0), XX3_MASK, PPCVSX2, PPCVLE, {XT6, XA6, XB6}},
6788{"xsmaddasp", XX3(60,1), XX3_MASK, PPCVSX2, PPCVLE, {XT6, XA6, XB6}},
6789{"xxsldwi", XX3(60,2), XX3SHW_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6, SHW}},
6790{"xscmpeqdp", XX3(60,3), XX3_MASK, PPCVSX3, PPCVLE, {XT6, XA6, XB6}},
6791{"xsrsqrtesp", XX2(60,10), XX2_MASK, PPCVSX2, PPCVLE, {XT6, XB6}},
6792{"xssqrtsp", XX2(60,11), XX2_MASK, PPCVSX2, PPCVLE, {XT6, XB6}},
6793{"xxsel", XX4(60,3), XX4_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6, XC6}},
6794{"xssubsp", XX3(60,8), XX3_MASK, PPCVSX2, PPCVLE, {XT6, XA6, XB6}},
6795{"xsmaddmsp", XX3(60,9), XX3_MASK, PPCVSX2, PPCVLE, {XT6, XA6, XB6}},
6796{"xxspltd", XX3(60,10), XX3DM_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6S, DMEX}},
6797{"xxmrghd", XX3(60,10), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6798{"xxswapd", XX3(60,10)|(2<<8), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6S}},
6799{"xxmrgld", XX3(60,10)|(3<<8), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6800{"xxpermdi", XX3(60,10), XX3DM_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6, DM}},
6801{"xscmpgtdp", XX3(60,11), XX3_MASK, PPCVSX3, PPCVLE, {XT6, XA6, XB6}},
6802{"xsresp", XX2(60,26), XX2_MASK, PPCVSX2, PPCVLE, {XT6, XB6}},
6803{"xsmulsp", XX3(60,16), XX3_MASK, PPCVSX2, PPCVLE, {XT6, XA6, XB6}},
6804{"xsmsubasp", XX3(60,17), XX3_MASK, PPCVSX2, PPCVLE, {XT6, XA6, XB6}},
6805{"xxmrghw", XX3(60,18), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6806{"xscmpgedp", XX3(60,19), XX3_MASK, PPCVSX3, PPCVLE, {XT6, XA6, XB6}},
6807{"xsdivsp", XX3(60,24), XX3_MASK, PPCVSX2, PPCVLE, {XT6, XA6, XB6}},
6808{"xsmsubmsp", XX3(60,25), XX3_MASK, PPCVSX2, PPCVLE, {XT6, XA6, XB6}},
6809{"xxperm", XX3(60,26), XX3_MASK, PPCVSX3, PPCVLE, {XT6, XA6, XB6}},
6810{"xsadddp", XX3(60,32), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6811{"xsmaddadp", XX3(60,33), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6812{"xscmpudp", XX3(60,35), XX3BF_MASK, PPCVSX, PPCVLE, {BF, XA6, XB6}},
6813{"xscvdpuxws", XX2(60,72), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6814{"xsrdpi", XX2(60,73), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6815{"xsrsqrtedp", XX2(60,74), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6816{"xssqrtdp", XX2(60,75), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6817{"xssubdp", XX3(60,40), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6818{"xsmaddmdp", XX3(60,41), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6819{"xscmpodp", XX3(60,43), XX3BF_MASK, PPCVSX, PPCVLE, {BF, XA6, XB6}},
6820{"xscvdpsxws", XX2(60,88), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6821{"xsrdpiz", XX2(60,89), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6822{"xsredp", XX2(60,90), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6823{"xsmuldp", XX3(60,48), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6824{"xsmsubadp", XX3(60,49), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6825{"xxmrglw", XX3(60,50), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6826{"xsrdpip", XX2(60,105), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6827{"xstsqrtdp", XX2(60,106), XX2BF_MASK, PPCVSX, PPCVLE, {BF, XB6}},
6828{"xsrdpic", XX2(60,107), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6829{"xsdivdp", XX3(60,56), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6830{"xsmsubmdp", XX3(60,57), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6831{"xxpermr", XX3(60,58), XX3_MASK, PPCVSX3, PPCVLE, {XT6, XA6, XB6}},
6832{"xscmpexpdp", XX3(60,59), XX3BF_MASK, PPCVSX3, PPCVLE, {BF, XA6, XB6}},
6833{"xsrdpim", XX2(60,121), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6834{"xstdivdp", XX3(60,61), XX3BF_MASK, PPCVSX, PPCVLE, {BF, XA6, XB6}},
6835{"xvaddsp", XX3(60,64), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6836{"xvmaddasp", XX3(60,65), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6837{"xvcmpeqsp", XX3RC(60,67,0), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6838{"xvcmpeqsp.", XX3RC(60,67,1), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6839{"xvcvspuxws", XX2(60,136), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6840{"xvrspi", XX2(60,137), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6841{"xvrsqrtesp", XX2(60,138), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6842{"xvsqrtsp", XX2(60,139), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6843{"xvsubsp", XX3(60,72), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6844{"xvmaddmsp", XX3(60,73), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6845{"xvcmpgtsp", XX3RC(60,75,0), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6846{"xvcmpgtsp.", XX3RC(60,75,1), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6847{"xvcvspsxws", XX2(60,152), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6848{"xvrspiz", XX2(60,153), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6849{"xvresp", XX2(60,154), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6850{"xvmulsp", XX3(60,80), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6851{"xvmsubasp", XX3(60,81), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6852{"xxspltw", XX2(60,164), XX2UIM_MASK, PPCVSX, PPCVLE, {XT6, XB6, UIM}},
6853{"xxextractuw", XX2(60,165), XX2UIM4_MASK, PPCVSX3, PPCVLE, {XT6, XB6, UIMM4}},
6854{"xvcmpgesp", XX3RC(60,83,0), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6855{"xvcmpgesp.", XX3RC(60,83,1), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6856{"xvcvuxwsp", XX2(60,168), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6857{"xvrspip", XX2(60,169), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6858{"xvtsqrtsp", XX2(60,170), XX2BF_MASK, PPCVSX, PPCVLE, {BF, XB6}},
6859{"xvrspic", XX2(60,171), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6860{"xvdivsp", XX3(60,88), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6861{"xvmsubmsp", XX3(60,89), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6862{"xxspltib", X(60,360), XX1_MASK|3<<19, PPCVSX3, PPCVLE, {XT6, IMM8}},
6863{"xxinsertw", XX2(60,181), XX2UIM4_MASK, PPCVSX3, PPCVLE, {XT6, XB6, UIMM4}},
6864{"xvcvsxwsp", XX2(60,184), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6865{"xvrspim", XX2(60,185), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6866{"xvtdivsp", XX3(60,93), XX3BF_MASK, PPCVSX, PPCVLE, {BF, XA6, XB6}},
6867{"xvadddp", XX3(60,96), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6868{"xvmaddadp", XX3(60,97), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6869{"xvcmpeqdp", XX3RC(60,99,0), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6870{"xvcmpeqdp.", XX3RC(60,99,1), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6871{"xvcvdpuxws", XX2(60,200), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6872{"xvrdpi", XX2(60,201), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6873{"xvrsqrtedp", XX2(60,202), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6874{"xvsqrtdp", XX2(60,203), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6875{"xvsubdp", XX3(60,104), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6876{"xvmaddmdp", XX3(60,105), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6877{"xvcmpgtdp", XX3RC(60,107,0), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6878{"xvcmpgtdp.", XX3RC(60,107,1), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6879{"xvcvdpsxws", XX2(60,216), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6880{"xvrdpiz", XX2(60,217), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6881{"xvredp", XX2(60,218), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6882{"xvmuldp", XX3(60,112), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6883{"xvmsubadp", XX3(60,113), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6884{"xvcmpgedp", XX3RC(60,115,0), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6885{"xvcmpgedp.", XX3RC(60,115,1), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6886{"xvcvuxwdp", XX2(60,232), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6887{"xvrdpip", XX2(60,233), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6888{"xvtsqrtdp", XX2(60,234), XX2BF_MASK, PPCVSX, PPCVLE, {BF, XB6}},
6889{"xvrdpic", XX2(60,235), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6890{"xvdivdp", XX3(60,120), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6891{"xvmsubmdp", XX3(60,121), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6892{"xvcvsxwdp", XX2(60,248), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6893{"xvrdpim", XX2(60,249), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6894{"xvtdivdp", XX3(60,125), XX3BF_MASK, PPCVSX, PPCVLE, {BF, XA6, XB6}},
6895{"xsmaxcdp", XX3(60,128), XX3_MASK, PPCVSX3, PPCVLE, {XT6, XA6, XB6}},
6896{"xsnmaddasp", XX3(60,129), XX3_MASK, PPCVSX2, PPCVLE, {XT6, XA6, XB6}},
6897{"xxland", XX3(60,130), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6898{"xscvdpsp", XX2(60,265), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6899{"xscvdpspn", XX2(60,267), XX2_MASK, PPCVSX2, PPCVLE, {XT6, XB6}},
6900{"xsmincdp", XX3(60,136), XX3_MASK, PPCVSX3, PPCVLE, {XT6, XA6, XB6}},
6901{"xsnmaddmsp", XX3(60,137), XX3_MASK, PPCVSX2, PPCVLE, {XT6, XA6, XB6}},
6902{"xxlandc", XX3(60,138), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6903{"xsrsp", XX2(60,281), XX2_MASK, PPCVSX2, PPCVLE, {XT6, XB6}},
6904{"xsmaxjdp", XX3(60,144), XX3_MASK, PPCVSX3, PPCVLE, {XT6, XA6, XB6}},
6905{"xsnmsubasp", XX3(60,145), XX3_MASK, PPCVSX2, PPCVLE, {XT6, XA6, XB6}},
6906{"xxlor", XX3(60,146), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6907{"xscvuxdsp", XX2(60,296), XX2_MASK, PPCVSX2, PPCVLE, {XT6, XB6}},
6908{"xststdcsp", XX2(60,298), XX2BFD_MASK, PPCVSX3, PPCVLE, {BF, XB6, DCMX}},
6909{"xsminjdp", XX3(60,152), XX3_MASK, PPCVSX3, PPCVLE, {XT6, XA6, XB6}},
6910{"xsnmsubmsp", XX3(60,153), XX3_MASK, PPCVSX2, PPCVLE, {XT6, XA6, XB6}},
6911{"xxlxor", XX3(60,154), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6912{"xscvsxdsp", XX2(60,312), XX2_MASK, PPCVSX2, PPCVLE, {XT6, XB6}},
6913{"xsmaxdp", XX3(60,160), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6914{"xsnmaddadp", XX3(60,161), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6915{"xxlnor", XX3(60,162), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6916{"xscvdpuxds", XX2(60,328), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6917{"xscvspdp", XX2(60,329), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6918{"xscvspdpn", XX2(60,331), XX2_MASK, PPCVSX2, PPCVLE, {XT6, XB6}},
6919{"xsmindp", XX3(60,168), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6920{"xsnmaddmdp", XX3(60,169), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6921{"xxlorc", XX3(60,170), XX3_MASK, PPCVSX2, PPCVLE, {XT6, XA6, XB6}},
6922{"xscvdpsxds", XX2(60,344), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6923{"xsabsdp", XX2(60,345), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6924{"xsxexpdp", XX2VA(60,347,0),XX2_MASK|1, PPCVSX3, PPCVLE, {RT, XB6}},
6925{"xsxsigdp", XX2VA(60,347,1),XX2_MASK|1, PPCVSX3, PPCVLE, {RT, XB6}},
6926{"xscvhpdp", XX2VA(60,347,16),XX2_MASK, PPCVSX3, PPCVLE, {XT6, XB6}},
6927{"xscvdphp", XX2VA(60,347,17),XX2_MASK, PPCVSX3, PPCVLE, {XT6, XB6}},
6928{"xscpsgndp", XX3(60,176), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6929{"xsnmsubadp", XX3(60,177), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6930{"xxlnand", XX3(60,178), XX3_MASK, PPCVSX2, PPCVLE, {XT6, XA6, XB6}},
6931{"xscvuxddp", XX2(60,360), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6932{"xsnabsdp", XX2(60,361), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6933{"xststdcdp", XX2(60,362), XX2BFD_MASK, PPCVSX3, PPCVLE, {BF, XB6, DCMX}},
6934{"xsnmsubmdp", XX3(60,185), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6935{"xxleqv", XX3(60,186), XX3_MASK, PPCVSX2, PPCVLE, {XT6, XA6, XB6}},
6936{"xscvsxddp", XX2(60,376), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6937{"xsnegdp", XX2(60,377), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6938{"xvmaxsp", XX3(60,192), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6939{"xvnmaddasp", XX3(60,193), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6940{"xvcvspuxds", XX2(60,392), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6941{"xvcvdpsp", XX2(60,393), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6942{"xvminsp", XX3(60,200), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6943{"xvnmaddmsp", XX3(60,201), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6944{"xvcvspsxds", XX2(60,408), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6945{"xvabssp", XX2(60,409), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6946{"xvmovsp", XX3(60,208), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6S}},
6947{"xvcpsgnsp", XX3(60,208), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6948{"xvnmsubasp", XX3(60,209), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6949{"xvcvuxdsp", XX2(60,424), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6950{"xvnabssp", XX2(60,425), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6951{"xvtstdcsp", XX2(60,426), XX2DCMXS_MASK, PPCVSX3, PPCVLE, {XT6, XB6, DCMXS}},
6952{"xviexpsp", XX3(60,216), XX3_MASK, PPCVSX3, PPCVLE, {XT6, XA6, XB6}},
6953{"xvnmsubmsp", XX3(60,217), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6954{"xvcvsxdsp", XX2(60,440), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6955{"xvnegsp", XX2(60,441), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6956{"xvmaxdp", XX3(60,224), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6957{"xvnmaddadp", XX3(60,225), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6958{"xvcvdpuxds", XX2(60,456), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6959{"xvcvspdp", XX2(60,457), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6960{"xsiexpdp", X(60,918), XX1_MASK, PPCVSX3, PPCVLE, {XT6, RA, RB}},
6961{"xvmindp", XX3(60,232), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6962{"xvnmaddmdp", XX3(60,233), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6963{"xvcvdpsxds", XX2(60,472), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6964{"xvabsdp", XX2(60,473), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6965{"xvxexpdp", XX2VA(60,475,0),XX2_MASK, PPCVSX3, PPCVLE, {XT6, XB6}},
6966{"xvxsigdp", XX2VA(60,475,1),XX2_MASK, PPCVSX3, PPCVLE, {XT6, XB6}},
6967{"xxbrh", XX2VA(60,475,7),XX2_MASK, PPCVSX3, PPCVLE, {XT6, XB6}},
6968{"xvxexpsp", XX2VA(60,475,8),XX2_MASK, PPCVSX3, PPCVLE, {XT6, XB6}},
6969{"xvxsigsp", XX2VA(60,475,9),XX2_MASK, PPCVSX3, PPCVLE, {XT6, XB6}},
6970{"xxbrw", XX2VA(60,475,15),XX2_MASK, PPCVSX3, PPCVLE, {XT6, XB6}},
6971{"xxbrd", XX2VA(60,475,23),XX2_MASK, PPCVSX3, PPCVLE, {XT6, XB6}},
6972{"xvcvhpsp", XX2VA(60,475,24),XX2_MASK, PPCVSX3, PPCVLE, {XT6, XB6}},
6973{"xvcvsphp", XX2VA(60,475,25),XX2_MASK, PPCVSX3, PPCVLE, {XT6, XB6}},
6974{"xxbrq", XX2VA(60,475,31),XX2_MASK, PPCVSX3, PPCVLE, {XT6, XB6}},
6975{"xvmovdp", XX3(60,240), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6S}},
6976{"xvcpsgndp", XX3(60,240), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6977{"xvnmsubadp", XX3(60,241), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6978{"xvcvuxddp", XX2(60,488), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6979{"xvnabsdp", XX2(60,489), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6980{"xvtstdcdp", XX2(60,490), XX2DCMXS_MASK, PPCVSX3, PPCVLE, {XT6, XB6, DCMXS}},
6981{"xviexpdp", XX3(60,248), XX3_MASK, PPCVSX3, PPCVLE, {XT6, XA6, XB6}},
6982{"xvnmsubmdp", XX3(60,249), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6983{"xvcvsxddp", XX2(60,504), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6984{"xvnegdp", XX2(60,505), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6985
6986{"psq_st", OP(60), OP_MASK, PPCPS, PPCVLE, {FRS,PSD,RA,PSW,PSQ}},
6987{"stfq", OP(60), OP_MASK, POWER2, PPCVLE, {FRS, D, RA}},
6988
6989{"lxv", DQX(61,1), DQX_MASK, PPCVSX3, PPCVLE, {XTQ6, DQ, RA0}},
6990{"stxv", DQX(61,5), DQX_MASK, PPCVSX3, PPCVLE, {XSQ6, DQ, RA0}},
6991{"stxsd", DSO(61,2), DS_MASK, PPCVSX3, PPCVLE, {VS, DS, RA0}},
6992{"stxssp", DSO(61,3), DS_MASK, PPCVSX3, PPCVLE, {VS, DS, RA0}},
73f07bff 6993{"stfdp", OP(61), OP_MASK|Q_MASK, POWER6, POWER7|PPCVLE, {FRSp, DS, RA0}},
14b57c7c
AM		 6994{"psq_stu", OP(61), OP_MASK, PPCPS, PPCVLE, {FRS,PSD,RA,PSW,PSQ}},
6995{"stfqu", OP(61), OP_MASK, POWER2, PPCVLE, {FRS, D, RA}},
6996
6997{"std", DSO(62,0), DS_MASK, PPC64, PPCVLE, {RS, DS, RA0}},
6998{"stdu", DSO(62,1), DS_MASK, PPC64, PPCVLE, {RS, DS, RAS}},
73f07bff 6999{"stq", DSO(62,2), DS_MASK|Q_MASK, POWER4, PPC476|PPCVLE, {RSQ, DS, RA0}},
14b57c7c
AM		 7000
7001{"fcmpu", X(63,0), XBF_MASK, COM, PPCEFS|PPCVLE, {BF, FRA, FRB}},
7002
73f07bff
AM		 7003{"daddq", XRC(63,2,0), X_MASK|Q_MASK, POWER6, PPCVLE, {FRTp, FRAp, FRBp}},
7004{"daddq.", XRC(63,2,1), X_MASK|Q_MASK, POWER6, PPCVLE, {FRTp, FRAp, FRBp}},
14b57c7c 7005
73f07bff
AM		 7006{"dquaq", ZRC(63,3,0), Z2_MASK|Q_MASK, POWER6, PPCVLE, {FRTp, FRAp, FRBp, RMC}},
7007{"dquaq.", ZRC(63,3,1), Z2_MASK|Q_MASK, POWER6, PPCVLE, {FRTp, FRAp, FRBp, RMC}},
14b57c7c
AM		 7008
7009{"xsaddqp", XRC(63,4,0), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}},
7010{"xsaddqpo", XRC(63,4,1), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}},
7011
7012{"xsrqpi", ZRC(63,5,0), Z2_MASK, PPCVSX3, PPCVLE, {R, VD, VB, RMC}},
7013{"xsrqpix", ZRC(63,5,1), Z2_MASK, PPCVSX3, PPCVLE, {R, VD, VB, RMC}},
7014
7015{"fcpsgn", XRC(63,8,0), X_MASK, POWER6|PPCA2|PPC476, PPCVLE, {FRT, FRA, FRB}},
7016{"fcpsgn.", XRC(63,8,1), X_MASK, POWER6|PPCA2|PPC476, PPCVLE, {FRT, FRA, FRB}},
7017
7018{"frsp", XRC(63,12,0), XRA_MASK, COM, PPCEFS|PPCVLE, {FRT, FRB}},
7019{"frsp.", XRC(63,12,1), XRA_MASK, COM, PPCEFS|PPCVLE, {FRT, FRB}},
7020
7021{"fctiw", XRC(63,14,0), XRA_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRB}},
7022{"fcir", XRC(63,14,0), XRA_MASK, PWR2COM, PPCVLE, {FRT, FRB}},
7023{"fctiw.", XRC(63,14,1), XRA_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRB}},
7024{"fcir.", XRC(63,14,1), XRA_MASK, PWR2COM, PPCVLE, {FRT, FRB}},
7025
7026{"fctiwz", XRC(63,15,0), XRA_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRB}},
7027{"fcirz", XRC(63,15,0), XRA_MASK, PWR2COM, PPCVLE, {FRT, FRB}},
7028{"fctiwz.", XRC(63,15,1), XRA_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRB}},
7029{"fcirz.", XRC(63,15,1), XRA_MASK, PWR2COM, PPCVLE, {FRT, FRB}},
7030
7031{"fdiv", A(63,18,0), AFRC_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRA, FRB}},
7032{"fd", A(63,18,0), AFRC_MASK, PWRCOM, PPCVLE, {FRT, FRA, FRB}},
7033{"fdiv.", A(63,18,1), AFRC_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRA, FRB}},
7034{"fd.", A(63,18,1), AFRC_MASK, PWRCOM, PPCVLE, {FRT, FRA, FRB}},
7035
7036{"fsub", A(63,20,0), AFRC_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRA, FRB}},
7037{"fs", A(63,20,0), AFRC_MASK, PWRCOM, PPCVLE, {FRT, FRA, FRB}},
7038{"fsub.", A(63,20,1), AFRC_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRA, FRB}},
7039{"fs.", A(63,20,1), AFRC_MASK, PWRCOM, PPCVLE, {FRT, FRA, FRB}},
7040
7041{"fadd", A(63,21,0), AFRC_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRA, FRB}},
7042{"fa", A(63,21,0), AFRC_MASK, PWRCOM, PPCVLE, {FRT, FRA, FRB}},
7043{"fadd.", A(63,21,1), AFRC_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRA, FRB}},
7044{"fa.", A(63,21,1), AFRC_MASK, PWRCOM, PPCVLE, {FRT, FRA, FRB}},
7045
7046{"fsqrt", A(63,22,0), AFRAFRC_MASK, PPCPWR2, TITAN|PPCVLE, {FRT, FRB}},
7047{"fsqrt.", A(63,22,1), AFRAFRC_MASK, PPCPWR2, TITAN|PPCVLE, {FRT, FRB}},
7048
7049{"fsel", A(63,23,0), A_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}},
7050{"fsel.", A(63,23,1), A_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}},
7051
7052{"fre", A(63,24,0), AFRAFRC_MASK, POWER7, PPCVLE, {FRT, FRB}},
7053{"fre", A(63,24,0), AFRALFRC_MASK, POWER5, POWER7|PPCVLE, {FRT, FRB, A_L}},
7054{"fre.", A(63,24,1), AFRAFRC_MASK, POWER7, PPCVLE, {FRT, FRB}},
7055{"fre.", A(63,24,1), AFRALFRC_MASK, POWER5, POWER7|PPCVLE, {FRT, FRB, A_L}},
1ed8e1e4 7056
14b57c7c
AM		 7057{"fmul", A(63,25,0), AFRB_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRA, FRC}},
7058{"fm", A(63,25,0), AFRB_MASK, PWRCOM, PPCVLE|PPCVLE, {FRT, FRA, FRC}},
7059{"fmul.", A(63,25,1), AFRB_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRA, FRC}},
7060{"fm.", A(63,25,1), AFRB_MASK, PWRCOM, PPCVLE|PPCVLE, {FRT, FRA, FRC}},
252b5132 7061
14b57c7c
AM		 7062{"frsqrte", A(63,26,0), AFRAFRC_MASK, POWER7, PPCVLE, {FRT, FRB}},
7063{"frsqrte", A(63,26,0), AFRALFRC_MASK, PPC, POWER7|PPCVLE, {FRT, FRB, A_L}},
7064{"frsqrte.", A(63,26,1), AFRAFRC_MASK, POWER7, PPCVLE, {FRT, FRB}},
7065{"frsqrte.", A(63,26,1), AFRALFRC_MASK, PPC, POWER7|PPCVLE, {FRT, FRB, A_L}},
252b5132 7066
14b57c7c
AM		 7067{"fmsub", A(63,28,0), A_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}},
7068{"fms", A(63,28,0), A_MASK, PWRCOM, PPCVLE, {FRT, FRA, FRC, FRB}},
7069{"fmsub.", A(63,28,1), A_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}},
7070{"fms.", A(63,28,1), A_MASK, PWRCOM, PPCVLE, {FRT, FRA, FRC, FRB}},
252b5132 7071
14b57c7c
AM		 7072{"fmadd", A(63,29,0), A_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}},
7073{"fma", A(63,29,0), A_MASK, PWRCOM, PPCVLE, {FRT, FRA, FRC, FRB}},
7074{"fmadd.", A(63,29,1), A_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}},
7075{"fma.", A(63,29,1), A_MASK, PWRCOM, PPCVLE, {FRT, FRA, FRC, FRB}},
252b5132 7076
14b57c7c
AM		 7077{"fnmsub", A(63,30,0), A_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}},
7078{"fnms", A(63,30,0), A_MASK, PWRCOM, PPCVLE, {FRT, FRA, FRC, FRB}},
7079{"fnmsub.", A(63,30,1), A_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}},
7080{"fnms.", A(63,30,1), A_MASK, PWRCOM, PPCVLE, {FRT, FRA, FRC, FRB}},
252b5132 7081
14b57c7c
AM		 7082{"fnmadd", A(63,31,0), A_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}},
7083{"fnma", A(63,31,0), A_MASK, PWRCOM, PPCVLE, {FRT, FRA, FRC, FRB}},
7084{"fnmadd.", A(63,31,1), A_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}},
7085{"fnma.", A(63,31,1), A_MASK, PWRCOM, PPCVLE, {FRT, FRA, FRC, FRB}},
252b5132 7086
14b57c7c 7087{"fcmpo", X(63,32), XBF_MASK, COM, PPCEFS|PPCVLE, {BF, FRA, FRB}},
252b5132 7088
73f07bff
AM		 7089{"dmulq", XRC(63,34,0), X_MASK|Q_MASK, POWER6, PPCVLE, {FRTp, FRAp, FRBp}},
7090{"dmulq.", XRC(63,34,1), X_MASK|Q_MASK, POWER6, PPCVLE, {FRTp, FRAp, FRBp}},
702f0fb4 7091
73f07bff
AM		 7092{"drrndq", ZRC(63,35,0), Z2_MASK|Q_MASK, POWER6, PPCVLE, {FRTp, FRA, FRBp, RMC}},
7093{"drrndq.", ZRC(63,35,1), Z2_MASK|Q_MASK, POWER6, PPCVLE, {FRTp, FRA, FRBp, RMC}},
702f0fb4 7094
14b57c7c
AM		 7095{"xsmulqp", XRC(63,36,0), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}},
7096{"xsmulqpo", XRC(63,36,1), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}},
a680de9a 7097
14b57c7c 7098{"xsrqpxp", Z(63,37), Z2_MASK, PPCVSX3, PPCVLE, {R, VD, VB, RMC}},
a680de9a 7099
14b57c7c
AM		 7100{"mtfsb1", XRC(63,38,0), XRARB_MASK, COM, PPCVLE, {BT}},
7101{"mtfsb1.", XRC(63,38,1), XRARB_MASK, COM, PPCVLE, {BT}},
252b5132 7102
14b57c7c
AM		 7103{"fneg", XRC(63,40,0), XRA_MASK, COM, PPCEFS|PPCVLE, {FRT, FRB}},
7104{"fneg.", XRC(63,40,1), XRA_MASK, COM, PPCEFS|PPCVLE, {FRT, FRB}},
252b5132 7105
14b57c7c 7106{"mcrfs", X(63,64), XRB_MASK|(3<<21)|(3<<16), COM, PPCVLE, {BF, BFA}},
252b5132 7107
73f07bff
AM		 7108{"dscliq", ZRC(63,66,0), Z_MASK|Q_MASK, POWER6, PPCVLE, {FRTp, FRAp, SH16}},
7109{"dscliq.", ZRC(63,66,1), Z_MASK|Q_MASK, POWER6, PPCVLE, {FRTp, FRAp, SH16}},
702f0fb4 7110
73f07bff
AM		 7111{"dquaiq", ZRC(63,67,0), Z2_MASK|Q_MASK, POWER6, PPCVLE, {TE, FRTp, FRBp, RMC}},
7112{"dquaiq.", ZRC(63,67,1), Z2_MASK|Q_MASK, POWER6, PPCVLE, {TE, FRTp, FRBp, RMC}},
702f0fb4 7113
14b57c7c
AM		 7114{"mtfsb0", XRC(63,70,0), XRARB_MASK, COM, PPCVLE, {BT}},
7115{"mtfsb0.", XRC(63,70,1), XRARB_MASK, COM, PPCVLE, {BT}},
252b5132 7116
14b57c7c
AM		 7117{"fmr", XRC(63,72,0), XRA_MASK, COM, PPCEFS|PPCVLE, {FRT, FRB}},
7118{"fmr.", XRC(63,72,1), XRA_MASK, COM, PPCEFS|PPCVLE, {FRT, FRB}},
252b5132 7119
73f07bff
AM		 7120{"dscriq", ZRC(63,98,0), Z_MASK|Q_MASK, POWER6, PPCVLE, {FRTp, FRAp, SH16}},
7121{"dscriq.", ZRC(63,98,1), Z_MASK|Q_MASK, POWER6, PPCVLE, {FRTp, FRAp, SH16}},
702f0fb4 7122
73f07bff
AM		 7123{"drintxq", ZRC(63,99,0), Z2_MASK|Q_MASK, POWER6, PPCVLE, {R, FRTp, FRBp, RMC}},
7124{"drintxq.", ZRC(63,99,1), Z2_MASK|Q_MASK, POWER6, PPCVLE, {R, FRTp, FRBp, RMC}},
702f0fb4 7125
14b57c7c 7126{"xscpsgnqp", X(63,100), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}},
a680de9a 7127
14b57c7c 7128{"ftdiv", X(63,128), XBF_MASK, POWER7, PPCVLE, {BF, FRA, FRB}},
066be9f7 7129
14b57c7c 7130{"dcmpoq", X(63,130), X_MASK, POWER6, PPCVLE, {BF, FRAp, FRBp}},
702f0fb4 7131
14b57c7c 7132{"xscmpoqp", X(63,132), XBF_MASK, PPCVSX3, PPCVLE, {BF, VA, VB}},
a680de9a 7133
14b57c7c
AM		 7134{"mtfsfi", XRC(63,134,0), XWRA_MASK|(3<<21)|(1<<11), POWER6|PPCA2|PPC476, PPCVLE, {BFF, U, W}},
7135{"mtfsfi", XRC(63,134,0), XRA_MASK|(3<<21)|(1<<11), COM, POWER6|PPCA2|PPC476|PPCVLE, {BFF, U}},
7136{"mtfsfi.", XRC(63,134,1), XWRA_MASK|(3<<21)|(1<<11), POWER6|PPCA2|PPC476, PPCVLE, {BFF, U, W}},
7137{"mtfsfi.", XRC(63,134,1), XRA_MASK|(3<<21)|(1<<11), COM, POWER6|PPCA2|PPC476|PPCVLE, {BFF, U}},
252b5132 7138
14b57c7c
AM		 7139{"fnabs", XRC(63,136,0), XRA_MASK, COM, PPCEFS|PPCVLE, {FRT, FRB}},
7140{"fnabs.", XRC(63,136,1), XRA_MASK, COM, PPCEFS|PPCVLE, {FRT, FRB}},
252b5132 7141
14b57c7c
AM		 7142{"fctiwu", XRC(63,142,0), XRA_MASK, POWER7, PPCVLE, {FRT, FRB}},
7143{"fctiwu.", XRC(63,142,1), XRA_MASK, POWER7, PPCVLE, {FRT, FRB}},
7144{"fctiwuz", XRC(63,143,0), XRA_MASK, POWER7, PPCVLE, {FRT, FRB}},
7145{"fctiwuz.", XRC(63,143,1), XRA_MASK, POWER7, PPCVLE, {FRT, FRB}},
066be9f7 7146
14b57c7c 7147{"ftsqrt", X(63,160), XBF_MASK|FRA_MASK, POWER7, PPCVLE, {BF, FRB}},
066be9f7 7148
14b57c7c 7149{"dtstexq", X(63,162), X_MASK, POWER6, PPCVLE, {BF, FRAp, FRBp}},
a680de9a 7150
14b57c7c 7151{"xscmpexpqp", X(63,164), XBF_MASK, PPCVSX3, PPCVLE, {BF, VA, VB}},
a680de9a 7152
14b57c7c
AM		 7153{"dtstdcq", Z(63,194), Z_MASK, POWER6, PPCVLE, {BF, FRAp, DCM}},
7154{"dtstdgq", Z(63,226), Z_MASK, POWER6, PPCVLE, {BF, FRAp, DGM}},
702f0fb4 7155
73f07bff
AM		 7156{"drintnq", ZRC(63,227,0), Z2_MASK|Q_MASK, POWER6, PPCVLE, {R, FRTp, FRBp, RMC}},
7157{"drintnq.", ZRC(63,227,1), Z2_MASK|Q_MASK, POWER6, PPCVLE, {R, FRTp, FRBp, RMC}},
702f0fb4 7158
73f07bff
AM		 7159{"dctqpq", XRC(63,258,0), X_MASK|Q_MASK, POWER6, PPCVLE, {FRTp, FRB}},
7160{"dctqpq.", XRC(63,258,1), X_MASK|Q_MASK, POWER6, PPCVLE, {FRTp, FRB}},
702f0fb4 7161
14b57c7c
AM		 7162{"fabs", XRC(63,264,0), XRA_MASK, COM, PPCEFS|PPCVLE, {FRT, FRB}},
7163{"fabs.", XRC(63,264,1), XRA_MASK, COM, PPCEFS|PPCVLE, {FRT, FRB}},
252b5132 7164
14b57c7c
AM		 7165{"dctfixq", XRC(63,290,0), X_MASK, POWER6, PPCVLE, {FRT, FRBp}},
7166{"dctfixq.", XRC(63,290,1), X_MASK, POWER6, PPCVLE, {FRT, FRBp}},
702f0fb4 7167
73f07bff
AM		 7168{"ddedpdq", XRC(63,322,0), X_MASK|Q_MASK, POWER6, PPCVLE, {SP, FRTp, FRBp}},
7169{"ddedpdq.", XRC(63,322,1), X_MASK|Q_MASK, POWER6, PPCVLE, {SP, FRTp, FRBp}},
702f0fb4 7170
14b57c7c
AM		 7171{"dxexq", XRC(63,354,0), X_MASK, POWER6, PPCVLE, {FRT, FRBp}},
7172{"dxexq.", XRC(63,354,1), X_MASK, POWER6, PPCVLE, {FRT, FRBp}},
702f0fb4 7173
14b57c7c
AM		 7174{"xsmaddqp", XRC(63,388,0), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}},
7175{"xsmaddqpo", XRC(63,388,1), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}},
a680de9a 7176
14b57c7c
AM		 7177{"frin", XRC(63,392,0), XRA_MASK, POWER5, PPCVLE, {FRT, FRB}},
7178{"frin.", XRC(63,392,1), XRA_MASK, POWER5, PPCVLE, {FRT, FRB}},
a680de9a 7179
14b57c7c
AM		 7180{"xsmsubqp", XRC(63,420,0), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}},
7181{"xsmsubqpo", XRC(63,420,1), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}},
a680de9a 7182
14b57c7c
AM		 7183{"friz", XRC(63,424,0), XRA_MASK, POWER5, PPCVLE, {FRT, FRB}},
7184{"friz.", XRC(63,424,1), XRA_MASK, POWER5, PPCVLE, {FRT, FRB}},
a680de9a 7185
14b57c7c
AM		 7186{"xsnmaddqp", XRC(63,452,0), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}},
7187{"xsnmaddqpo", XRC(63,452,1), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}},
a680de9a 7188
14b57c7c
AM		 7189{"frip", XRC(63,456,0), XRA_MASK, POWER5, PPCVLE, {FRT, FRB}},
7190{"frip.", XRC(63,456,1), XRA_MASK, POWER5, PPCVLE, {FRT, FRB}},
a680de9a 7191
14b57c7c
AM		 7192{"xsnmsubqp", XRC(63,484,0), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}},
7193{"xsnmsubqpo", XRC(63,484,1), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}},
a680de9a 7194
14b57c7c
AM		 7195{"frim", XRC(63,488,0), XRA_MASK, POWER5, PPCVLE, {FRT, FRB}},
7196{"frim.", XRC(63,488,1), XRA_MASK, POWER5, PPCVLE, {FRT, FRB}},
ce7a772b 7197
73f07bff
AM		 7198{"dsubq", XRC(63,514,0), X_MASK|Q_MASK, POWER6, PPCVLE, {FRTp, FRAp, FRBp}},
7199{"dsubq.", XRC(63,514,1), X_MASK|Q_MASK, POWER6, PPCVLE, {FRTp, FRAp, FRBp}},
702f0fb4 7200
14b57c7c
AM		 7201{"xssubqp", XRC(63,516,0), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}},
7202{"xssubqpo", XRC(63,516,1), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}},
a680de9a 7203
73f07bff
AM		 7204{"ddivq", XRC(63,546,0), X_MASK|Q_MASK, POWER6, PPCVLE, {FRTp, FRAp, FRBp}},
7205{"ddivq.", XRC(63,546,1), X_MASK|Q_MASK, POWER6, PPCVLE, {FRTp, FRAp, FRBp}},
702f0fb4 7206
14b57c7c
AM		 7207{"xsdivqp", XRC(63,548,0), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}},
7208{"xsdivqpo", XRC(63,548,1), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}},
a680de9a 7209
14b57c7c
AM		 7210{"mffs", XRC(63,583,0), XRARB_MASK, COM, PPCEFS|PPCVLE, {FRT}},
7211{"mffs.", XRC(63,583,1), XRARB_MASK, COM, PPCEFS|PPCVLE, {FRT}},
252b5132 7212
6fd3a02d
PB		 7213{"mffsce", XMMF(63,583,0,1), XMMF_MASK|RB_MASK, POWER9, PPCVLE, {FRT}},
7214{"mffscdrn", XMMF(63,583,2,4), XMMF_MASK, POWER9, PPCVLE, {FRT, FRB}},
7215{"mffscdrni", XMMF(63,583,2,5), XMMF_MASK|(3<<14), POWER9, PPCVLE, {FRT, DRM}},
7216{"mffscrn", XMMF(63,583,2,6), XMMF_MASK, POWER9, PPCVLE, {FRT, FRB}},
7217{"mffscrni", XMMF(63,583,2,7), XMMF_MASK|(7<<13), POWER9, PPCVLE, {FRT, RM}},
7218{"mffsl", XMMF(63,583,3,0), XMMF_MASK|RB_MASK, POWER9, PPCVLE, {FRT}},
7219
14b57c7c 7220{"dcmpuq", X(63,642), X_MASK, POWER6, PPCVLE, {BF, FRAp, FRBp}},
702f0fb4 7221
14b57c7c 7222{"xscmpuqp", X(63,644), XBF_MASK, PPCVSX3, PPCVLE, {BF, VA, VB}},
a680de9a 7223
14b57c7c
AM		 7224{"dtstsfq", X(63,674), X_MASK, POWER6, PPCVLE, {BF, FRA, FRBp}},
7225{"dtstsfiq", X(63,675), X_MASK|1<<22,POWER9, PPCVLE, {BF, UIM6, FRBp}},
a680de9a 7226
14b57c7c 7227{"xststdcqp", X(63,708), X_MASK, PPCVSX3, PPCVLE, {BF, VB, DCMX}},
702f0fb4 7228
14b57c7c
AM		 7229{"mtfsf", XFL(63,711,0), XFL_MASK, POWER6|PPCA2|PPC476, PPCVLE, {FLM, FRB, XFL_L, W}},
7230{"mtfsf", XFL(63,711,0), XFL_MASK, COM, POWER6|PPCA2|PPC476|PPCEFS|PPCVLE, {FLM, FRB}},
7231{"mtfsf.", XFL(63,711,1), XFL_MASK, POWER6|PPCA2|PPC476, PPCVLE, {FLM, FRB, XFL_L, W}},
7232{"mtfsf.", XFL(63,711,1), XFL_MASK, COM, POWER6|PPCA2|PPC476|PPCEFS|PPCVLE, {FLM, FRB}},
252b5132 7233
73f07bff
AM		 7234{"drdpq", XRC(63,770,0), X_MASK|Q_MASK, POWER6, PPCVLE, {FRTp, FRBp}},
7235{"drdpq.", XRC(63,770,1), X_MASK|Q_MASK, POWER6, PPCVLE, {FRTp, FRBp}},
702f0fb4 7236
73f07bff
AM		 7237{"dcffixq", XRC(63,802,0), X_MASK|Q_MASK, POWER6, PPCVLE, {FRTp, FRB}},
7238{"dcffixq.", XRC(63,802,1), X_MASK|Q_MASK, POWER6, PPCVLE, {FRTp, FRB}},
702f0fb4 7239
14b57c7c
AM		 7240{"xsabsqp", XVA(63,804,0), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}},
7241{"xsxexpqp", XVA(63,804,2), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}},
7242{"xsnabsqp", XVA(63,804,8), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}},
7243{"xsnegqp", XVA(63,804,16), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}},
7244{"xsxsigqp", XVA(63,804,18), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}},
7245{"xssqrtqp", XVARC(63,804,27,0), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}},
7246{"xssqrtqpo", XVARC(63,804,27,1), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}},
a680de9a 7247
14b57c7c
AM		 7248{"fctid", XRC(63,814,0), XRA_MASK, PPC64, PPCVLE, {FRT, FRB}},
7249{"fctid", XRC(63,814,0), XRA_MASK, PPC476, PPCVLE, {FRT, FRB}},
7250{"fctid.", XRC(63,814,1), XRA_MASK, PPC64, PPCVLE, {FRT, FRB}},
7251{"fctid.", XRC(63,814,1), XRA_MASK, PPC476, PPCVLE, {FRT, FRB}},
252b5132 7252
14b57c7c
AM		 7253{"fctidz", XRC(63,815,0), XRA_MASK, PPC64, PPCVLE, {FRT, FRB}},
7254{"fctidz", XRC(63,815,0), XRA_MASK, PPC476, PPCVLE, {FRT, FRB}},
7255{"fctidz.", XRC(63,815,1), XRA_MASK, PPC64, PPCVLE, {FRT, FRB}},
7256{"fctidz.", XRC(63,815,1), XRA_MASK, PPC476, PPCVLE, {FRT, FRB}},
252b5132 7257
73f07bff
AM		 7258{"denbcdq", XRC(63,834,0), X_MASK|Q_MASK, POWER6, PPCVLE, {S, FRTp, FRBp}},
7259{"denbcdq.", XRC(63,834,1), X_MASK|Q_MASK, POWER6, PPCVLE, {S, FRTp, FRBp}},
702f0fb4 7260
14b57c7c
AM		 7261{"xscvqpuwz", XVA(63,836,1), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}},
7262{"xscvudqp", XVA(63,836,2), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}},
7263{"xscvqpswz", XVA(63,836,9), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}},
7264{"xscvsdqp", XVA(63,836,10), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}},
7265{"xscvqpudz", XVA(63,836,17), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}},
7266{"xscvqpdp", XVARC(63,836,20,0), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}},
7267{"xscvqpdpo", XVARC(63,836,20,1), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}},
7268{"xscvdpqp", XVA(63,836,22), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}},
7269{"xscvqpsdz", XVA(63,836,25), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}},
a680de9a 7270
14b57c7c 7271{"fmrgow", X(63,838), X_MASK, PPCVSX2, PPCVLE, {FRT, FRA, FRB}},
c0637f3a 7272
14b57c7c
AM		 7273{"fcfid", XRC(63,846,0), XRA_MASK, PPC64, PPCVLE, {FRT, FRB}},
7274{"fcfid", XRC(63,846,0), XRA_MASK, PPC476, PPCVLE, {FRT, FRB}},
7275{"fcfid.", XRC(63,846,1), XRA_MASK, PPC64, PPCVLE, {FRT, FRB}},
7276{"fcfid.", XRC(63,846,1), XRA_MASK, PPC476, PPCVLE, {FRT, FRB}},
252b5132 7277
73f07bff
AM		 7278{"diexq", XRC(63,866,0), X_MASK|Q_MASK, POWER6, PPCVLE, {FRTp, FRA, FRBp}},
7279{"diexq.", XRC(63,866,1), X_MASK|Q_MASK, POWER6, PPCVLE, {FRTp, FRA, FRBp}},
702f0fb4 7280
14b57c7c 7281{"xsiexpqp", X(63,868), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}},
a680de9a 7282
14b57c7c
AM		 7283{"fctidu", XRC(63,942,0), XRA_MASK, POWER7|PPCA2, PPCVLE, {FRT, FRB}},
7284{"fctidu.", XRC(63,942,1), XRA_MASK, POWER7|PPCA2, PPCVLE, {FRT, FRB}},
066be9f7 7285
14b57c7c
AM		 7286{"fctiduz", XRC(63,943,0), XRA_MASK, POWER7|PPCA2, PPCVLE, {FRT, FRB}},
7287{"fctiduz.", XRC(63,943,1), XRA_MASK, POWER7|PPCA2, PPCVLE, {FRT, FRB}},
066be9f7 7288
14b57c7c 7289{"fmrgew", X(63,966), X_MASK, PPCVSX2, PPCVLE, {FRT, FRA, FRB}},
c0637f3a 7290
14b57c7c
AM		 7291{"fcfidu", XRC(63,974,0), XRA_MASK, POWER7|PPCA2, PPCVLE, {FRT, FRB}},
7292{"fcfidu.", XRC(63,974,1), XRA_MASK, POWER7|PPCA2, PPCVLE, {FRT, FRB}},
252b5132
RH		 7293};
7294
7295const int powerpc_num_opcodes =
7296 sizeof (powerpc_opcodes) / sizeof (powerpc_opcodes[0]);
7297\f
b9c361e0
JL		 7298/* The VLE opcode table.
7299
7300 The format of this opcode table is the same as the main opcode table. */
7301
7302const struct powerpc_opcode vle_opcodes[] = {
14b57c7c
AM		 7303{"se_illegal", C(0), C_MASK, PPCVLE, 0, {}},
7304{"se_isync", C(1), C_MASK, PPCVLE, 0, {}},
7305{"se_sc", C(2), C_MASK, PPCVLE, 0, {}},
7306{"se_blr", C_LK(2,0), C_LK_MASK, PPCVLE, 0, {}},
7307{"se_blrl", C_LK(2,1), C_LK_MASK, PPCVLE, 0, {}},
7308{"se_bctr", C_LK(3,0), C_LK_MASK, PPCVLE, 0, {}},
7309{"se_bctrl", C_LK(3,1), C_LK_MASK, PPCVLE, 0, {}},
7310{"se_rfi", C(8), C_MASK, PPCVLE, 0, {}},
7311{"se_rfci", C(9), C_MASK, PPCVLE, 0, {}},
7312{"se_rfdi", C(10), C_MASK, PPCVLE, 0, {}},
7313{"se_rfmci", C(11), C_MASK, PPCRFMCI|PPCVLE, 0, {}},
a8cc8a54 7314{"se_rfgi", C(12), C_MASK, PPCVLE, 0, {}},
14b57c7c
AM		 7315{"se_not", SE_R(0,2), SE_R_MASK, PPCVLE, 0, {RX}},
7316{"se_neg", SE_R(0,3), SE_R_MASK, PPCVLE, 0, {RX}},
7317{"se_mflr", SE_R(0,8), SE_R_MASK, PPCVLE, 0, {RX}},
7318{"se_mtlr", SE_R(0,9), SE_R_MASK, PPCVLE, 0, {RX}},
7319{"se_mfctr", SE_R(0,10), SE_R_MASK, PPCVLE, 0, {RX}},
7320{"se_mtctr", SE_R(0,11), SE_R_MASK, PPCVLE, 0, {RX}},
7321{"se_extzb", SE_R(0,12), SE_R_MASK, PPCVLE, 0, {RX}},
7322{"se_extsb", SE_R(0,13), SE_R_MASK, PPCVLE, 0, {RX}},
7323{"se_extzh", SE_R(0,14), SE_R_MASK, PPCVLE, 0, {RX}},
7324{"se_extsh", SE_R(0,15), SE_R_MASK, PPCVLE, 0, {RX}},
7325{"se_mr", SE_RR(0,1), SE_RR_MASK, PPCVLE, 0, {RX, RY}},
7326{"se_mtar", SE_RR(0,2), SE_RR_MASK, PPCVLE, 0, {ARX, RY}},
7327{"se_mfar", SE_RR(0,3), SE_RR_MASK, PPCVLE, 0, {RX, ARY}},
7328{"se_add", SE_RR(1,0), SE_RR_MASK, PPCVLE, 0, {RX, RY}},
7329{"se_mullw", SE_RR(1,1), SE_RR_MASK, PPCVLE, 0, {RX, RY}},
7330{"se_sub", SE_RR(1,2), SE_RR_MASK, PPCVLE, 0, {RX, RY}},
7331{"se_subf", SE_RR(1,3), SE_RR_MASK, PPCVLE, 0, {RX, RY}},
7332{"se_cmp", SE_RR(3,0), SE_RR_MASK, PPCVLE, 0, {RX, RY}},
7333{"se_cmpl", SE_RR(3,1), SE_RR_MASK, PPCVLE, 0, {RX, RY}},
7334{"se_cmph", SE_RR(3,2), SE_RR_MASK, PPCVLE, 0, {RX, RY}},
7335{"se_cmphl", SE_RR(3,3), SE_RR_MASK, PPCVLE, 0, {RX, RY}},
7336
e3c2f928
AF		 7337/* by major opcode */
7338{"zvaddih", VX(4, 0x200), VX_MASK, PPCLSP, 0, {RD, RA, EVUIMM}},
7339{"zvsubifh", VX(4, 0x201), VX_MASK, PPCLSP, 0, {RD, RA, EVUIMM}},
7340{"zvaddh", VX(4, 0x204), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7341{"zvsubfh", VX(4, 0x205), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7342{"zvaddsubfh", VX(4, 0x206), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7343{"zvsubfaddh", VX(4, 0x207), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7344{"zvaddhx", VX(4, 0x20C), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7345{"zvsubfhx", VX(4, 0x20D), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7346{"zvaddsubfhx", VX(4, 0x20E), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7347{"zvsubfaddhx", VX(4, 0x20F), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7348{"zaddwus", VX(4, 0x210), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7349{"zsubfwus", VX(4, 0x211), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7350{"zaddwss", VX(4, 0x212), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7351{"zsubfwss", VX(4, 0x213), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7352{"zvaddhus", VX(4, 0x214), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7353{"zvsubfhus", VX(4, 0x215), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7354{"zvaddhss", VX(4, 0x216), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7355{"zvsubfhss", VX(4, 0x217), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7356{"zvaddsubfhss", VX(4, 0x21A), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7357{"zvsubfaddhss", VX(4, 0x21B), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7358{"zvaddhxss", VX(4, 0x21C), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7359{"zvsubfhxss", VX(4, 0x21D), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7360{"zvaddsubfhxss", VX(4, 0x21E), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7361{"zvsubfaddhxss", VX(4, 0x21F), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7362{"zaddheuw", VX(4, 0x220), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7363{"zsubfheuw", VX(4, 0x221), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7364{"zaddhesw", VX(4, 0x222), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7365{"zsubfhesw", VX(4, 0x223), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7366{"zaddhouw", VX(4, 0x224), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7367{"zsubfhouw", VX(4, 0x225), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7368{"zaddhosw", VX(4, 0x226), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7369{"zsubfhosw", VX(4, 0x227), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7370{"zvmergehih", VX(4, 0x22C), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7371{"zvmergeloh", VX(4, 0x22D), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7372{"zvmergehiloh", VX(4, 0x22E), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7373{"zvmergelohih", VX(4, 0x22F), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7374{"zvcmpgthu", VX(4, 0x230), VX_MASK, PPCLSP, 0, {CRFD, RA, RB}},
7375{"zvcmpgths", VX(4, 0x230), VX_MASK, PPCLSP, 0, {CRFD, RA, RB}},
7376{"zvcmplthu", VX(4, 0x231), VX_MASK, PPCLSP, 0, {CRFD, RA, RB}},
7377{"zvcmplths", VX(4, 0x231), VX_MASK, PPCLSP, 0, {CRFD, RA, RB}},
7378{"zvcmpeqh", VX(4, 0x232), VX_MASK, PPCLSP, 0, {CRFD, RA, RB}},
7379{"zpkswgshfrs", VX(4, 0x238), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7380{"zpkswgswfrs", VX(4, 0x239), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7381{"zvpkshgwshfrs", VX(4, 0x23A), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7382{"zvpkswshfrs", VX(4, 0x23B), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7383{"zvpkswuhs", VX(4, 0x23C), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7384{"zvpkswshs", VX(4, 0x23D), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7385{"zvpkuwuhs", VX(4, 0x23E), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7386{"zvsplatih", VX_LSP(4, 0x23F), VX_LSP_MASK, PPCLSP, 0, {RD, SIMM}},
7387{"zvsplatfih", VX_LSP(4, 0xA3F), VX_LSP_MASK, PPCLSP, 0, {RD, SIMM}},
7388{"zcntlsw", VX_LSP(4, 0x2A3F), VX_LSP_MASK, PPCLSP, 0, {RD, RA}},
7389{"zvcntlzh", VX_LSP(4, 0x323F), VX_LSP_MASK, PPCLSP, 0, {RD, RA}},
7390{"zvcntlsh", VX_LSP(4, 0x3A3F), VX_LSP_MASK, PPCLSP, 0, {RD, RA}},
7391{"znegws", VX_LSP(4, 0x4A3F), VX_LSP_MASK, PPCLSP, 0, {RD, RA}},
7392{"zvnegh", VX_LSP(4, 0x523F), VX_LSP_MASK, PPCLSP, 0, {RD, RA}},
7393{"zvneghs", VX_LSP(4, 0x5A3F), VX_LSP_MASK, PPCLSP, 0, {RD, RA}},
7394{"zvnegho", VX_LSP(4, 0x623F), VX_LSP_MASK, PPCLSP, 0, {RD, RA}},
7395{"zvneghos", VX_LSP(4, 0x6A3F), VX_LSP_MASK, PPCLSP, 0, {RD, RA}},
7396{"zrndwh", VX_LSP(4, 0x823F), VX_LSP_MASK, PPCLSP, 0, {RD, RA}},
7397{"zrndwhss", VX_LSP(4, 0x8A3F), VX_LSP_MASK, PPCLSP, 0, {RD, RA}},
7398{"zvabsh", VX_LSP(4, 0xA23F), VX_LSP_MASK, PPCLSP, 0, {RD, RA}},
7399{"zvabshs", VX_LSP(4, 0xAA3F), VX_LSP_MASK, PPCLSP, 0, {RD, RA}},
7400{"zabsw", VX_LSP(4, 0xB23F), VX_LSP_MASK, PPCLSP, 0, {RD, RA}},
7401{"zabsws", VX_LSP(4, 0xBA3F), VX_LSP_MASK, PPCLSP, 0, {RD, RA}},
7402{"zsatswuw", VX_LSP(4, 0xC23F), VX_LSP_MASK, PPCLSP, 0, {RD, RA}},
7403{"zsatuwsw", VX_LSP(4, 0xCA3F), VX_LSP_MASK, PPCLSP, 0, {RD, RA}},
7404{"zsatswuh", VX_LSP(4, 0xD23F), VX_LSP_MASK, PPCLSP, 0, {RD, RA}},
7405{"zsatswsh", VX_LSP(4, 0xDA3F), VX_LSP_MASK, PPCLSP, 0, {RD, RA}},
7406{"zvsatshuh", VX_LSP(4, 0xE23F), VX_LSP_MASK, PPCLSP, 0, {RD, RA}},
7407{"zvsatuhsh", VX_LSP(4, 0xEA3F), VX_LSP_MASK, PPCLSP, 0, {RD, RA}},
7408{"zsatuwuh", VX_LSP(4, 0xF23F), VX_LSP_MASK, PPCLSP, 0, {RD, RA}},
7409{"zsatuwsh", VX_LSP(4, 0xFA3F), VX_LSP_MASK, PPCLSP, 0, {RD, RA}},
7410{"zsatsduw", VX(4, 0x260), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7411{"zsatsdsw", VX(4, 0x261), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7412{"zsatuduw", VX(4, 0x262), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7413{"zvselh", VX(4, 0x264), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7414{"zxtrw", VX(4, 0x264), VX_LSP_OFF_MASK, PPCLSP, 0, {RD, RA, RB, VX_OFF}},
7415{"zbrminc", VX(4, 0x268), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7416{"zcircinc", VX(4, 0x269), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7417{"zdivwsf", VX(4, 0x26B), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7418{"zvsrhu", VX(4, 0x270), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7419{"zvsrhs", VX(4, 0x271), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7420{"zvsrhiu", VX(4, 0x272), VX_MASK, PPCLSP, 0, {RD, RA, EVUIMM_LT16}},
7421{"zvsrhis", VX(4, 0x273), VX_MASK, PPCLSP, 0, {RD, RA, EVUIMM_LT16}},
7422{"zvslh", VX(4, 0x274), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7423{"zvrlh", VX(4, 0x275), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7424{"zvslhi", VX(4, 0x276), VX_MASK, PPCLSP, 0, {RD, RA, EVUIMM_LT16}},
7425{"zvrlhi", VX(4, 0x277), VX_MASK, PPCLSP, 0, {RD, RA, EVUIMM_LT16}},
7426{"zvslhus", VX(4, 0x278), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7427{"zvslhss", VX(4, 0x279), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7428{"zvslhius", VX(4, 0x27A), VX_MASK, PPCLSP, 0, {RD, RA, EVUIMM_LT16}},
7429{"zvslhiss", VX(4, 0x27B), VX_MASK, PPCLSP, 0, {RD, RA, EVUIMM_LT16}},
7430{"zslwus", VX(4, 0x27C), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7431{"zslwss", VX(4, 0x27D), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7432{"zslwius", VX(4, 0x27E), VX_MASK, PPCLSP, 0, {RD, RA, EVUIMM}},
7433{"zslwiss", VX(4, 0x27F), VX_MASK, PPCLSP, 0, {RD, RA, EVUIMM}},
7434{"zaddwgui", VX(4, 0x460), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7435{"zsubfwgui", VX(4, 0x461), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7436{"zaddd", VX(4, 0x462), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7437{"zsubfd", VX(4, 0x463), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7438{"zvaddsubfw", VX(4, 0x464), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7439{"zvsubfaddw", VX(4, 0x465), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7440{"zvaddw", VX(4, 0x466), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7441{"zvsubfw", VX(4, 0x467), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7442{"zaddwgsi", VX(4, 0x468), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7443{"zsubfwgsi", VX(4, 0x469), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7444{"zadddss", VX(4, 0x46A), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7445{"zsubfdss", VX(4, 0x46B), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7446{"zvaddsubfwss", VX(4, 0x46C), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7447{"zvsubfaddwss", VX(4, 0x46D), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7448{"zvaddwss", VX(4, 0x46E), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7449{"zvsubfwss", VX(4, 0x46F), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7450{"zaddwgsf", VX(4, 0x470), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7451{"zsubfwgsf", VX(4, 0x471), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7452{"zadddus", VX(4, 0x472), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7453{"zsubfdus", VX(4, 0x473), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7454{"zvaddwus", VX(4, 0x476), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7455{"zvsubfwus", VX(4, 0x477), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7456{"zvunpkhgwsf", VX_LSP(4, 0x478), VX_LSP_MASK, PPCLSP, 0, {RD_EVEN, RA}},
7457{"zvunpkhsf", VX_LSP(4, 0xC78), VX_LSP_MASK, PPCLSP, 0, {RD_EVEN, RA}},
7458{"zvunpkhui", VX_LSP(4, 0x1478), VX_LSP_MASK, PPCLSP, 0, {RD_EVEN, RA}},
7459{"zvunpkhsi", VX_LSP(4, 0x1C78), VX_LSP_MASK, PPCLSP, 0, {RD_EVEN, RA}},
7460{"zunpkwgsf", VX_LSP(4, 0x2478), VX_LSP_MASK, PPCLSP, 0, {RD_EVEN, RA}},
7461{"zvdotphgwasmf", VX(4, 0x488), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7462{"zvdotphgwasmfr", VX(4, 0x489), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7463{"zvdotphgwasmfaa", VX(4, 0x48A), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7464{"zvdotphgwasmfraa", VX(4, 0x48B), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7465{"zvdotphgwasmfan", VX(4, 0x48C), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7466{"zvdotphgwasmfran", VX(4, 0x48D), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7467{"zvmhulgwsmf", VX(4, 0x490), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7468{"zvmhulgwsmfr", VX(4, 0x491), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7469{"zvmhulgwsmfaa", VX(4, 0x492), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7470{"zvmhulgwsmfraa", VX(4, 0x493), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7471{"zvmhulgwsmfan", VX(4, 0x494), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7472{"zvmhulgwsmfran", VX(4, 0x495), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7473{"zvmhulgwsmfanp", VX(4, 0x496), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7474{"zvmhulgwsmfranp", VX(4, 0x497), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7475{"zmhegwsmf", VX(4, 0x498), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7476{"zmhegwsmfr", VX(4, 0x499), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7477{"zmhegwsmfaa", VX(4, 0x49A), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7478{"zmhegwsmfraa", VX(4, 0x49B), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7479{"zmhegwsmfan", VX(4, 0x49C), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7480{"zmhegwsmfran", VX(4, 0x49D), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7481{"zvdotphxgwasmf", VX(4, 0x4A8), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7482{"zvdotphxgwasmfr", VX(4, 0x4A9), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7483{"zvdotphxgwasmfaa", VX(4, 0x4AA), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7484{"zvdotphxgwasmfraa", VX(4, 0x4AB), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7485{"zvdotphxgwasmfan", VX(4, 0x4AC), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7486{"zvdotphxgwasmfran", VX(4, 0x4AD), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7487{"zvmhllgwsmf", VX(4, 0x4B0), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7488{"zvmhllgwsmfr", VX(4, 0x4B1), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7489{"zvmhllgwsmfaa", VX(4, 0x4B2), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7490{"zvmhllgwsmfraa", VX(4, 0x4B3), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7491{"zvmhllgwsmfan", VX(4, 0x4B4), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7492{"zvmhllgwsmfran", VX(4, 0x4B5), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7493{"zvmhllgwsmfanp", VX(4, 0x4B6), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7494{"zvmhllgwsmfranp", VX(4, 0x4B7), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7495{"zmheogwsmf", VX(4, 0x4B8), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7496{"zmheogwsmfr", VX(4, 0x4B9), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7497{"zmheogwsmfaa", VX(4, 0x4BA), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7498{"zmheogwsmfraa", VX(4, 0x4BB), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7499{"zmheogwsmfan", VX(4, 0x4BC), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7500{"zmheogwsmfran", VX(4, 0x4BD), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7501{"zvdotphgwssmf", VX(4, 0x4C8), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7502{"zvdotphgwssmfr", VX(4, 0x4C9), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7503{"zvdotphgwssmfaa", VX(4, 0x4CA), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7504{"zvdotphgwssmfraa", VX(4, 0x4CB), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7505{"zvdotphgwssmfan", VX(4, 0x4CC), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7506{"zvdotphgwssmfran", VX(4, 0x4CD), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7507{"zvmhuugwsmf", VX(4, 0x4D0), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7508{"zvmhuugwsmfr", VX(4, 0x4D1), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7509{"zvmhuugwsmfaa", VX(4, 0x4D2), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7510{"zvmhuugwsmfraa", VX(4, 0x4D3), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7511{"zvmhuugwsmfan", VX(4, 0x4D4), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7512{"zvmhuugwsmfran", VX(4, 0x4D5), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7513{"zvmhuugwsmfanp", VX(4, 0x4D6), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7514{"zvmhuugwsmfranp", VX(4, 0x4D7), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7515{"zmhogwsmf", VX(4, 0x4D8), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7516{"zmhogwsmfr", VX(4, 0x4D9), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7517{"zmhogwsmfaa", VX(4, 0x4DA), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7518{"zmhogwsmfraa", VX(4, 0x4DB), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7519{"zmhogwsmfan", VX(4, 0x4DC), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7520{"zmhogwsmfran", VX(4, 0x4DD), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7521{"zvmhxlgwsmf", VX(4, 0x4F0), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7522{"zvmhxlgwsmfr", VX(4, 0x4F1), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7523{"zvmhxlgwsmfaa", VX(4, 0x4F2), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7524{"zvmhxlgwsmfraa", VX(4, 0x4F3), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7525{"zvmhxlgwsmfan", VX(4, 0x4F4), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7526{"zvmhxlgwsmfran", VX(4, 0x4F5), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7527{"zvmhxlgwsmfanp", VX(4, 0x4F6), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7528{"zvmhxlgwsmfranp", VX(4, 0x4F7), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7529{"zmhegui", VX(4, 0x500), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7530{"zvdotphgaui", VX(4, 0x501), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7531{"zmheguiaa", VX(4, 0x502), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7532{"zvdotphgauiaa", VX(4, 0x503), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7533{"zmheguian", VX(4, 0x504), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7534{"zvdotphgauian", VX(4, 0x505), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7535{"zmhegsi", VX(4, 0x508), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7536{"zvdotphgasi", VX(4, 0x509), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7537{"zmhegsiaa", VX(4, 0x50A), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7538{"zvdotphgasiaa", VX(4, 0x50B), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7539{"zmhegsian", VX(4, 0x50C), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7540{"zvdotphgasian", VX(4, 0x50D), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7541{"zmhegsui", VX(4, 0x510), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7542{"zvdotphgasui", VX(4, 0x511), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7543{"zmhegsuiaa", VX(4, 0x512), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7544{"zvdotphgasuiaa", VX(4, 0x513), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7545{"zmhegsuian", VX(4, 0x514), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7546{"zvdotphgasuian", VX(4, 0x515), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7547{"zmhegsmf", VX(4, 0x518), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7548{"zvdotphgasmf", VX(4, 0x519), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7549{"zmhegsmfaa", VX(4, 0x51A), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7550{"zvdotphgasmfaa", VX(4, 0x51B), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7551{"zmhegsmfan", VX(4, 0x51C), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7552{"zvdotphgasmfan", VX(4, 0x51D), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7553{"zmheogui", VX(4, 0x520), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7554{"zvdotphxgaui", VX(4, 0x521), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7555{"zmheoguiaa", VX(4, 0x522), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7556{"zvdotphxgauiaa", VX(4, 0x523), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7557{"zmheoguian", VX(4, 0x524), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7558{"zvdotphxgauian", VX(4, 0x525), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7559{"zmheogsi", VX(4, 0x528), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7560{"zvdotphxgasi", VX(4, 0x529), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7561{"zmheogsiaa", VX(4, 0x52A), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7562{"zvdotphxgasiaa", VX(4, 0x52B), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7563{"zmheogsian", VX(4, 0x52C), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7564{"zvdotphxgasian", VX(4, 0x52D), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7565{"zmheogsui", VX(4, 0x530), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7566{"zvdotphxgasui", VX(4, 0x531), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7567{"zmheogsuiaa", VX(4, 0x532), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7568{"zvdotphxgasuiaa", VX(4, 0x533), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7569{"zmheogsuian", VX(4, 0x534), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7570{"zvdotphxgasuian", VX(4, 0x535), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7571{"zmheogsmf", VX(4, 0x538), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7572{"zvdotphxgasmf", VX(4, 0x539), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7573{"zmheogsmfaa", VX(4, 0x53A), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7574{"zvdotphxgasmfaa", VX(4, 0x53B), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7575{"zmheogsmfan", VX(4, 0x53C), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7576{"zvdotphxgasmfan", VX(4, 0x53D), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7577{"zmhogui", VX(4, 0x540), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7578{"zvdotphgsui", VX(4, 0x541), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7579{"zmhoguiaa", VX(4, 0x542), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7580{"zvdotphgsuiaa", VX(4, 0x543), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7581{"zmhoguian", VX(4, 0x544), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7582{"zvdotphgsuian", VX(4, 0x545), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7583{"zmhogsi", VX(4, 0x548), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7584{"zvdotphgssi", VX(4, 0x549), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7585{"zmhogsiaa", VX(4, 0x54A), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7586{"zvdotphgssiaa", VX(4, 0x54B), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7587{"zmhogsian", VX(4, 0x54C), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7588{"zvdotphgssian", VX(4, 0x54D), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7589{"zmhogsui", VX(4, 0x550), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7590{"zvdotphgssui", VX(4, 0x551), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7591{"zmhogsuiaa", VX(4, 0x552), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7592{"zvdotphgssuiaa", VX(4, 0x553), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7593{"zmhogsuian", VX(4, 0x554), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7594{"zvdotphgssuian", VX(4, 0x555), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7595{"zmhogsmf", VX(4, 0x558), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7596{"zvdotphgssmf", VX(4, 0x559), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7597{"zmhogsmfaa", VX(4, 0x55A), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7598{"zvdotphgssmfaa", VX(4, 0x55B), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7599{"zmhogsmfan", VX(4, 0x55C), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7600{"zvdotphgssmfan", VX(4, 0x55D), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7601{"zmwgui", VX(4, 0x560), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7602{"zmwguiaa", VX(4, 0x562), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7603{"zmwguiaas", VX(4, 0x563), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7604{"zmwguian", VX(4, 0x564), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7605{"zmwguians", VX(4, 0x565), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7606{"zmwgsi", VX(4, 0x568), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7607{"zmwgsiaa", VX(4, 0x56A), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7608{"zmwgsiaas", VX(4, 0x56B), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7609{"zmwgsian", VX(4, 0x56C), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7610{"zmwgsians", VX(4, 0x56D), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7611{"zmwgsui", VX(4, 0x570), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7612{"zmwgsuiaa", VX(4, 0x572), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7613{"zmwgsuiaas", VX(4, 0x573), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7614{"zmwgsuian", VX(4, 0x574), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7615{"zmwgsuians", VX(4, 0x575), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7616{"zmwgsmf", VX(4, 0x578), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7617{"zmwgsmfr", VX(4, 0x579), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7618{"zmwgsmfaa", VX(4, 0x57A), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7619{"zmwgsmfraa", VX(4, 0x57B), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7620{"zmwgsmfan", VX(4, 0x57C), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7621{"zmwgsmfran", VX(4, 0x57D), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7622{"zvmhului", VX(4, 0x580), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7623{"zvmhuluiaa", VX(4, 0x582), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7624{"zvmhuluiaas", VX(4, 0x583), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7625{"zvmhuluian", VX(4, 0x584), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7626{"zvmhuluians", VX(4, 0x585), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7627{"zvmhuluianp", VX(4, 0x586), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7628{"zvmhuluianps", VX(4, 0x587), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7629{"zvmhulsi", VX(4, 0x588), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7630{"zvmhulsiaa", VX(4, 0x58A), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7631{"zvmhulsiaas", VX(4, 0x58B), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7632{"zvmhulsian", VX(4, 0x58C), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7633{"zvmhulsians", VX(4, 0x58D), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7634{"zvmhulsianp", VX(4, 0x58E), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7635{"zvmhulsianps", VX(4, 0x58F), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7636{"zvmhulsui", VX(4, 0x590), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7637{"zvmhulsuiaa", VX(4, 0x592), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7638{"zvmhulsuiaas", VX(4, 0x593), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7639{"zvmhulsuian", VX(4, 0x594), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7640{"zvmhulsuians", VX(4, 0x595), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7641{"zvmhulsuianp", VX(4, 0x596), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7642{"zvmhulsuianps", VX(4, 0x597), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7643{"zvmhulsf", VX(4, 0x598), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7644{"zvmhulsfr", VX(4, 0x599), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7645{"zvmhulsfaas", VX(4, 0x59A), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7646{"zvmhulsfraas", VX(4, 0x59B), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7647{"zvmhulsfans", VX(4, 0x59C), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7648{"zvmhulsfrans", VX(4, 0x59D), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7649{"zvmhulsfanps", VX(4, 0x59E), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7650{"zvmhulsfranps", VX(4, 0x59F), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7651{"zvmhllui", VX(4, 0x5A0), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7652{"zvmhlluiaa", VX(4, 0x5A2), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7653{"zvmhlluiaas", VX(4, 0x5A3), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7654{"zvmhlluian", VX(4, 0x5A4), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7655{"zvmhlluians", VX(4, 0x5A5), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7656{"zvmhlluianp", VX(4, 0x5A6), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7657{"zvmhlluianps", VX(4, 0x5A7), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7658{"zvmhllsi", VX(4, 0x5A8), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7659{"zvmhllsiaa", VX(4, 0x5AA), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7660{"zvmhllsiaas", VX(4, 0x5AB), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7661{"zvmhllsian", VX(4, 0x5AC), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7662{"zvmhllsians", VX(4, 0x5AD), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7663{"zvmhllsianp", VX(4, 0x5AE), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7664{"zvmhllsianps", VX(4, 0x5AF), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7665{"zvmhllsui", VX(4, 0x5B0), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7666{"zvmhllsuiaa", VX(4, 0x5B2), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7667{"zvmhllsuiaas", VX(4, 0x5B3), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7668{"zvmhllsuian", VX(4, 0x5B4), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7669{"zvmhllsuians", VX(4, 0x5B5), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7670{"zvmhllsuianp", VX(4, 0x5B6), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7671{"zvmhllsuianps", VX(4, 0x5B7), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7672{"zvmhllsf", VX(4, 0x5B8), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7673{"zvmhllsfr", VX(4, 0x5B9), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7674{"zvmhllsfaas", VX(4, 0x5BA), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7675{"zvmhllsfraas", VX(4, 0x5BB), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7676{"zvmhllsfans", VX(4, 0x5BC), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7677{"zvmhllsfrans", VX(4, 0x5BD), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7678{"zvmhllsfanps", VX(4, 0x5BE), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7679{"zvmhllsfranps", VX(4, 0x5BF), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7680{"zvmhuuui", VX(4, 0x5C0), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7681{"zvmhuuuiaa", VX(4, 0x5C2), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7682{"zvmhuuuiaas", VX(4, 0x5C3), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7683{"zvmhuuuian", VX(4, 0x5C4), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7684{"zvmhuuuians", VX(4, 0x5C5), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7685{"zvmhuuuianp", VX(4, 0x5C6), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7686{"zvmhuuuianps", VX(4, 0x5C7), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7687{"zvmhuusi", VX(4, 0x5C8), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7688{"zvmhuusiaa", VX(4, 0x5CA), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7689{"zvmhuusiaas", VX(4, 0x5CB), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7690{"zvmhuusian", VX(4, 0x5CC), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7691{"zvmhuusians", VX(4, 0x5CD), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7692{"zvmhuusianp", VX(4, 0x5CE), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7693{"zvmhuusianps", VX(4, 0x5CF), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7694{"zvmhuusui", VX(4, 0x5D0), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7695{"zvmhuusuiaa", VX(4, 0x5D2), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7696{"zvmhuusuiaas", VX(4, 0x5D3), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7697{"zvmhuusuian", VX(4, 0x5D4), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7698{"zvmhuusuians", VX(4, 0x5D5), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7699{"zvmhuusuianp", VX(4, 0x5D6), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7700{"zvmhuusuianps", VX(4, 0x5D7), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7701{"zvmhuusf", VX(4, 0x5D8), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7702{"zvmhuusfr", VX(4, 0x5D9), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7703{"zvmhuusfaas", VX(4, 0x5DA), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7704{"zvmhuusfraas", VX(4, 0x5DB), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7705{"zvmhuusfans", VX(4, 0x5DC), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7706{"zvmhuusfrans", VX(4, 0x5DD), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7707{"zvmhuusfanps", VX(4, 0x5DE), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7708{"zvmhuusfranps", VX(4, 0x5DF), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7709{"zvmhxlui", VX(4, 0x5E0), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7710{"zvmhxluiaa", VX(4, 0x5E2), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7711{"zvmhxluiaas", VX(4, 0x5E3), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7712{"zvmhxluian", VX(4, 0x5E4), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7713{"zvmhxluians", VX(4, 0x5E5), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7714{"zvmhxluianp", VX(4, 0x5E6), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7715{"zvmhxluianps", VX(4, 0x5E7), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7716{"zvmhxlsi", VX(4, 0x5E8), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7717{"zvmhxlsiaa", VX(4, 0x5EA), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7718{"zvmhxlsiaas", VX(4, 0x5EB), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7719{"zvmhxlsian", VX(4, 0x5EC), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7720{"zvmhxlsians", VX(4, 0x5ED), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7721{"zvmhxlsianp", VX(4, 0x5EE), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7722{"zvmhxlsianps", VX(4, 0x5EF), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7723{"zvmhxlsui", VX(4, 0x5F0), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7724{"zvmhxlsuiaa", VX(4, 0x5F2), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7725{"zvmhxlsuiaas", VX(4, 0x5F3), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7726{"zvmhxlsuian", VX(4, 0x5F4), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7727{"zvmhxlsuians", VX(4, 0x5F5), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7728{"zvmhxlsuianp", VX(4, 0x5F6), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7729{"zvmhxlsuianps", VX(4, 0x5F7), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7730{"zvmhxlsf", VX(4, 0x5F8), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7731{"zvmhxlsfr", VX(4, 0x5F9), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7732{"zvmhxlsfaas", VX(4, 0x5FA), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7733{"zvmhxlsfraas", VX(4, 0x5FB), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7734{"zvmhxlsfans", VX(4, 0x5FC), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7735{"zvmhxlsfrans", VX(4, 0x5FD), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7736{"zvmhxlsfanps", VX(4, 0x5FE), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7737{"zvmhxlsfranps", VX(4, 0x5FF), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7738{"zmheui", VX(4, 0x600), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7739{"zmheuiaa", VX(4, 0x602), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7740{"zmheuiaas", VX(4, 0x603), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7741{"zmheuian", VX(4, 0x604), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7742{"zmheuians", VX(4, 0x605), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7743{"zmhesi", VX(4, 0x608), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7744{"zmhesiaa", VX(4, 0x60A), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7745{"zmhesiaas", VX(4, 0x60B), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7746{"zmhesian", VX(4, 0x60C), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7747{"zmhesians", VX(4, 0x60D), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7748{"zmhesui", VX(4, 0x610), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7749{"zmhesuiaa", VX(4, 0x612), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7750{"zmhesuiaas", VX(4, 0x613), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7751{"zmhesuian", VX(4, 0x614), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7752{"zmhesuians", VX(4, 0x615), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7753{"zmhesf", VX(4, 0x618), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7754{"zmhesfr", VX(4, 0x619), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7755{"zmhesfaas", VX(4, 0x61A), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7756{"zmhesfraas", VX(4, 0x61B), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7757{"zmhesfans", VX(4, 0x61C), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7758{"zmhesfrans", VX(4, 0x61D), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7759{"zmheoui", VX(4, 0x620), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7760{"zmheouiaa", VX(4, 0x622), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7761{"zmheouiaas", VX(4, 0x623), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7762{"zmheouian", VX(4, 0x624), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7763{"zmheouians", VX(4, 0x625), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7764{"zmheosi", VX(4, 0x628), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7765{"zmheosiaa", VX(4, 0x62A), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7766{"zmheosiaas", VX(4, 0x62B), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7767{"zmheosian", VX(4, 0x62C), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7768{"zmheosians", VX(4, 0x62D), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7769{"zmheosui", VX(4, 0x630), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7770{"zmheosuiaa", VX(4, 0x632), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7771{"zmheosuiaas", VX(4, 0x633), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7772{"zmheosuian", VX(4, 0x634), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7773{"zmheosuians", VX(4, 0x635), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7774{"zmheosf", VX(4, 0x638), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7775{"zmheosfr", VX(4, 0x639), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7776{"zmheosfaas", VX(4, 0x63A), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7777{"zmheosfraas", VX(4, 0x63B), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7778{"zmheosfans", VX(4, 0x63C), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7779{"zmheosfrans", VX(4, 0x63D), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7780{"zmhoui", VX(4, 0x640), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7781{"zmhouiaa", VX(4, 0x642), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7782{"zmhouiaas", VX(4, 0x643), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7783{"zmhouian", VX(4, 0x644), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7784{"zmhouians", VX(4, 0x645), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7785{"zmhosi", VX(4, 0x648), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7786{"zmhosiaa", VX(4, 0x64A), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7787{"zmhosiaas", VX(4, 0x64B), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7788{"zmhosian", VX(4, 0x64C), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7789{"zmhosians", VX(4, 0x64D), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7790{"zmhosui", VX(4, 0x650), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7791{"zmhosuiaa", VX(4, 0x652), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7792{"zmhosuiaas", VX(4, 0x653), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7793{"zmhosuian", VX(4, 0x654), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7794{"zmhosuians", VX(4, 0x655), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7795{"zmhosf", VX(4, 0x658), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7796{"zmhosfr", VX(4, 0x659), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7797{"zmhosfaas", VX(4, 0x65A), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7798{"zmhosfraas", VX(4, 0x65B), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7799{"zmhosfans", VX(4, 0x65C), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7800{"zmhosfrans", VX(4, 0x65D), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7801{"zvmhuih", VX(4, 0x660), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7802{"zvmhuihs", VX(4, 0x661), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7803{"zvmhuiaah", VX(4, 0x662), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7804{"zvmhuiaahs", VX(4, 0x663), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7805{"zvmhuianh", VX(4, 0x664), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7806{"zvmhuianhs", VX(4, 0x665), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7807{"zvmhsihs", VX(4, 0x669), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7808{"zvmhsiaahs", VX(4, 0x66B), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7809{"zvmhsianhs", VX(4, 0x66D), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7810{"zvmhsuihs", VX(4, 0x671), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7811{"zvmhsuiaahs", VX(4, 0x673), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7812{"zvmhsuianhs", VX(4, 0x675), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7813{"zvmhsfh", VX(4, 0x678), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7814{"zvmhsfrh", VX(4, 0x679), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7815{"zvmhsfaahs", VX(4, 0x67A), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7816{"zvmhsfraahs", VX(4, 0x67B), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7817{"zvmhsfanhs", VX(4, 0x67C), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7818{"zvmhsfranhs", VX(4, 0x67D), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7819{"zvdotphaui", VX(4, 0x680), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7820{"zvdotphauis", VX(4, 0x681), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7821{"zvdotphauiaa", VX(4, 0x682), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7822{"zvdotphauiaas", VX(4, 0x683), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7823{"zvdotphauian", VX(4, 0x684), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7824{"zvdotphauians", VX(4, 0x685), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7825{"zvdotphasi", VX(4, 0x688), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7826{"zvdotphasis", VX(4, 0x689), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7827{"zvdotphasiaa", VX(4, 0x68A), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7828{"zvdotphasiaas", VX(4, 0x68B), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7829{"zvdotphasian", VX(4, 0x68C), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7830{"zvdotphasians", VX(4, 0x68D), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7831{"zvdotphasui", VX(4, 0x690), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7832{"zvdotphasuis", VX(4, 0x691), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7833{"zvdotphasuiaa", VX(4, 0x692), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7834{"zvdotphasuiaas", VX(4, 0x693), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7835{"zvdotphasuian", VX(4, 0x694), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7836{"zvdotphasuians", VX(4, 0x695), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7837{"zvdotphasfs", VX(4, 0x698), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7838{"zvdotphasfrs", VX(4, 0x699), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7839{"zvdotphasfaas", VX(4, 0x69A), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7840{"zvdotphasfraas", VX(4, 0x69B), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7841{"zvdotphasfans", VX(4, 0x69C), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7842{"zvdotphasfrans", VX(4, 0x69D), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7843{"zvdotphxaui", VX(4, 0x6A0), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7844{"zvdotphxauis", VX(4, 0x6A1), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7845{"zvdotphxauiaa", VX(4, 0x6A2), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7846{"zvdotphxauiaas", VX(4, 0x6A3), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7847{"zvdotphxauian", VX(4, 0x6A4), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7848{"zvdotphxauians", VX(4, 0x6A5), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7849{"zvdotphxasi", VX(4, 0x6A8), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7850{"zvdotphxasis", VX(4, 0x6A9), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7851{"zvdotphxasiaa", VX(4, 0x6AA), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7852{"zvdotphxasiaas", VX(4, 0x6AB), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7853{"zvdotphxasian", VX(4, 0x6AC), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7854{"zvdotphxasians", VX(4, 0x6AD), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7855{"zvdotphxasui", VX(4, 0x6B0), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7856{"zvdotphxasuis", VX(4, 0x6B1), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7857{"zvdotphxasuiaa", VX(4, 0x6B2), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7858{"zvdotphxasuiaas", VX(4, 0x6B3), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7859{"zvdotphxasuian", VX(4, 0x6B4), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7860{"zvdotphxasuians", VX(4, 0x6B5), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7861{"zvdotphxasfs", VX(4, 0x6B8), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7862{"zvdotphxasfrs", VX(4, 0x6B9), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7863{"zvdotphxasfaas", VX(4, 0x6BA), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7864{"zvdotphxasfraas", VX(4, 0x6BB), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7865{"zvdotphxasfans", VX(4, 0x6BC), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7866{"zvdotphxasfrans", VX(4, 0x6BD), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7867{"zvdotphsui", VX(4, 0x6C0), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7868{"zvdotphsuis", VX(4, 0x6C1), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7869{"zvdotphsuiaa", VX(4, 0x6C2), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7870{"zvdotphsuiaas", VX(4, 0x6C3), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7871{"zvdotphsuian", VX(4, 0x6C4), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7872{"zvdotphsuians", VX(4, 0x6C5), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7873{"zvdotphssi", VX(4, 0x6C8), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7874{"zvdotphssis", VX(4, 0x6C9), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7875{"zvdotphssiaa", VX(4, 0x6CA), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7876{"zvdotphssiaas", VX(4, 0x6CB), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7877{"zvdotphssian", VX(4, 0x6CC), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7878{"zvdotphssians", VX(4, 0x6CD), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7879{"zvdotphssui", VX(4, 0x6D0), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7880{"zvdotphssuis", VX(4, 0x6D1), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7881{"zvdotphssuiaa", VX(4, 0x6D2), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7882{"zvdotphssuiaas", VX(4, 0x6D3), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7883{"zvdotphssuian", VX(4, 0x6D4), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7884{"zvdotphssuians", VX(4, 0x6D5), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7885{"zvdotphssfs", VX(4, 0x6D8), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7886{"zvdotphssfrs", VX(4, 0x6D9), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7887{"zvdotphssfaas", VX(4, 0x6DA), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7888{"zvdotphssfraas", VX(4, 0x6DB), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7889{"zvdotphssfans", VX(4, 0x6DC), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7890{"zvdotphssfrans", VX(4, 0x6DD), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7891{"zmwluis", VX(4, 0x6E1), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7892{"zmwluiaa", VX(4, 0x6E2), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7893{"zmwluiaas", VX(4, 0x6E3), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7894{"zmwluian", VX(4, 0x6E4), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7895{"zmwluians", VX(4, 0x6E5), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7896{"zmwlsis", VX(4, 0x6E9), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7897{"zmwlsiaas", VX(4, 0x6EB), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7898{"zmwlsians", VX(4, 0x6ED), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7899{"zmwlsuis", VX(4, 0x6F1), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7900{"zmwlsuiaas", VX(4, 0x6F3), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7901{"zmwlsuians", VX(4, 0x6F5), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7902{"zmwsf", VX(4, 0x6F8), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7903{"zmwsfr", VX(4, 0x6F9), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7904{"zmwsfaas", VX(4, 0x6FA), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7905{"zmwsfraas", VX(4, 0x6FB), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7906{"zmwsfans", VX(4, 0x6FC), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7907{"zmwsfrans", VX(4, 0x6FD), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7908{"zlddx", VX(4, 0x300), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7909{"zldd", VX(4, 0x301), VX_MASK, PPCLSP, 0, {RD_EVEN, EVUIMM_8, RA}},
7910{"zldwx", VX(4, 0x302), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7911{"zldw", VX(4, 0x303), VX_MASK, PPCLSP, 0, {RD_EVEN, EVUIMM_8, RA}},
7912{"zldhx", VX(4, 0x304), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7913{"zldh", VX(4, 0x305), VX_MASK, PPCLSP, 0, {RD_EVEN, EVUIMM_8, RA}},
7914{"zlwgsfdx", VX(4, 0x308), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7915{"zlwgsfd", VX(4, 0x309), VX_MASK, PPCLSP, 0, {RD_EVEN, EVUIMM_4, RA}},
7916{"zlwwosdx", VX(4, 0x30A), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7917{"zlwwosd", VX(4, 0x30B), VX_MASK, PPCLSP, 0, {RD_EVEN, EVUIMM_4, RA}},
7918{"zlwhsplatwdx", VX(4, 0x30C), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7919{"zlwhsplatwd", VX(4, 0x30D), VX_MASK, PPCLSP, 0, {RD_EVEN, EVUIMM_4, RA}},
7920{"zlwhsplatdx", VX(4, 0x30E), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7921{"zlwhsplatd", VX(4, 0x30F), VX_MASK, PPCLSP, 0, {RD_EVEN, EVUIMM_4, RA}},
7922{"zlwhgwsfdx", VX(4, 0x310), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7923{"zlwhgwsfd", VX(4, 0x311), VX_MASK, PPCLSP, 0, {RD_EVEN, EVUIMM_4, RA}},
7924{"zlwhedx", VX(4, 0x312), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7925{"zlwhed", VX(4, 0x313), VX_MASK, PPCLSP, 0, {RD_EVEN, EVUIMM_4, RA}},
7926{"zlwhosdx", VX(4, 0x314), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7927{"zlwhosd", VX(4, 0x315), VX_MASK, PPCLSP, 0, {RD_EVEN, EVUIMM_4, RA}},
7928{"zlwhoudx", VX(4, 0x316), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7929{"zlwhoud", VX(4, 0x317), VX_MASK, PPCLSP, 0, {RD_EVEN, EVUIMM_4, RA}},
7930{"zlwhx", VX(4, 0x318), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7931{"zlwh", VX(4, 0x319), VX_MASK, PPCLSP, 0, {RD, EVUIMM_4, RA}},
7932{"zlwwx", VX(4, 0x31A), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7933{"zlww", VX(4, 0x31B), VX_MASK, PPCLSP, 0, {RD, EVUIMM_4, RA}},
7934{"zlhgwsfx", VX(4, 0x31C), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7935{"zlhgwsf", VX(4, 0x31D), VX_MASK, PPCLSP, 0, {RD, EVUIMM_2, RA}},
7936{"zlhhsplatx", VX(4, 0x31E), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7937{"zlhhsplat", VX(4, 0x31F), VX_MASK, PPCLSP, 0, {RD, EVUIMM_2, RA}},
7938{"zstddx", VX(4, 0x320), VX_MASK, PPCLSP, 0, {RS_EVEN, RA, RB}},
7939{"zstdd", VX(4, 0x321), VX_MASK, PPCLSP, 0, {RS_EVEN, EVUIMM_8, RA}},
7940{"zstdwx", VX(4, 0x322), VX_MASK, PPCLSP, 0, {RS_EVEN, RA, RB}},
7941{"zstdw", VX(4, 0x323), VX_MASK, PPCLSP, 0, {RS_EVEN, EVUIMM_8, RA}},
7942{"zstdhx", VX(4, 0x324), VX_MASK, PPCLSP, 0, {RS_EVEN, RA, RB}},
7943{"zstdh", VX(4, 0x325), VX_MASK, PPCLSP, 0, {RS_EVEN, EVUIMM_8, RA}},
7944{"zstwhedx", VX(4, 0x328), VX_MASK, PPCLSP, 0, {RS_EVEN, RA, RB}},
7945{"zstwhed", VX(4, 0x329), VX_MASK, PPCLSP, 0, {RS_EVEN, EVUIMM_4, RA}},
7946{"zstwhodx", VX(4, 0x32A), VX_MASK, PPCLSP, 0, {RS_EVEN, RA, RB}},
7947{"zstwhod", VX(4, 0x32B), VX_MASK, PPCLSP, 0, {RS_EVEN, EVUIMM_4, RA}},
7948{"zlhhex", VX(4, 0x330), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7949{"zlhhe", VX(4, 0x331), VX_MASK, PPCLSP, 0, {RD, EVUIMM_2, RA}},
7950{"zlhhosx", VX(4, 0x332), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7951{"zlhhos", VX(4, 0x333), VX_MASK, PPCLSP, 0, {RD, EVUIMM_2, RA}},
7952{"zlhhoux", VX(4, 0x334), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7953{"zlhhou", VX(4, 0x335), VX_MASK, PPCLSP, 0, {RD, EVUIMM_2, RA}},
7954{"zsthex", VX(4, 0x338), VX_MASK, PPCLSP, 0, {RS, RA, RB}},
7955{"zsthe", VX(4, 0x339), VX_MASK, PPCLSP, 0, {RS, EVUIMM_2, RA}},
7956{"zsthox", VX(4, 0x33A), VX_MASK, PPCLSP, 0, {RS, RA, RB}},
7957{"zstho", VX(4, 0x33B), VX_MASK, PPCLSP, 0, {RS, EVUIMM_2, RA}},
7958{"zstwhx", VX(4, 0x33C), VX_MASK, PPCLSP, 0, {RS, RA, RB}},
7959{"zstwh", VX(4, 0x33D), VX_MASK, PPCLSP, 0, {RS, EVUIMM_4, RA}},
7960{"zstwwx", VX(4, 0x33E), VX_MASK, PPCLSP, 0, {RS, RA, RB}},
7961{"zstww", VX(4, 0x33F), VX_MASK, PPCLSP, 0, {RS, EVUIMM_4, RA}},
7962{"zlddmx", VX(4, 0x340), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7963{"zlddu", VX(4, 0x341), VX_MASK, PPCLSP, 0, {RD_EVEN, EVUIMM_8_EX0, RA}},
7964{"zldwmx", VX(4, 0x342), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7965{"zldwu", VX(4, 0x343), VX_MASK, PPCLSP, 0, {RD_EVEN, EVUIMM_8_EX0, RA}},
7966{"zldhmx", VX(4, 0x344), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7967{"zldhu", VX(4, 0x345), VX_MASK, PPCLSP, 0, {RD_EVEN, EVUIMM_8_EX0, RA}},
7968{"zlwgsfdmx", VX(4, 0x348), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7969{"zlwgsfdu", VX(4, 0x349), VX_MASK, PPCLSP, 0, {RD_EVEN, EVUIMM_4_EX0, RA}},
7970{"zlwwosdmx", VX(4, 0x34A), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7971{"zlwwosdu", VX(4, 0x34B), VX_MASK, PPCLSP, 0, {RD_EVEN, EVUIMM_4_EX0, RA}},
7972{"zlwhsplatwdmx", VX(4, 0x34C), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7973{"zlwhsplatwdu", VX(4, 0x34D), VX_MASK, PPCLSP, 0, {RD_EVEN, EVUIMM_4_EX0, RA}},
7974{"zlwhsplatdmx", VX(4, 0x34E), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7975{"zlwhsplatdu", VX(4, 0x34F), VX_MASK, PPCLSP, 0, {RD_EVEN, EVUIMM_4_EX0, RA}},
7976{"zlwhgwsfdmx", VX(4, 0x350), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7977{"zlwhgwsfdu", VX(4, 0x351), VX_MASK, PPCLSP, 0, {RD_EVEN, EVUIMM_4_EX0, RA}},
7978{"zlwhedmx", VX(4, 0x352), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7979{"zlwhedu", VX(4, 0x353), VX_MASK, PPCLSP, 0, {RD_EVEN, EVUIMM_4_EX0, RA}},
7980{"zlwhosdmx", VX(4, 0x354), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7981{"zlwhosdu", VX(4, 0x355), VX_MASK, PPCLSP, 0, {RD_EVEN, EVUIMM_4_EX0, RA}},
7982{"zlwhoudmx", VX(4, 0x356), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
7983{"zlwhoudu", VX(4, 0x357), VX_MASK, PPCLSP, 0, {RD_EVEN, EVUIMM_4_EX0, RA}},
7984{"zlwhmx", VX(4, 0x358), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7985{"zlwhu", VX(4, 0x359), VX_MASK, PPCLSP, 0, {RD, EVUIMM_4_EX0, RA}},
7986{"zlwwmx", VX(4, 0x35A), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7987{"zlwwu", VX(4, 0x35B), VX_MASK, PPCLSP, 0, {RD, EVUIMM_4_EX0, RA}},
7988{"zlhgwsfmx", VX(4, 0x35C), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7989{"zlhgwsfu", VX(4, 0x35D), VX_MASK, PPCLSP, 0, {RD, EVUIMM_2_EX0, RA}},
7990{"zlhhsplatmx", VX(4, 0x35E), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
7991{"zlhhsplatu", VX(4, 0x35F), VX_MASK, PPCLSP, 0, {RD, EVUIMM_2_EX0, RA}},
7992{"zstddmx", VX(4, 0x360), VX_MASK, PPCLSP, 0, {RS_EVEN, RA, RB}},
7993{"zstddu", VX(4, 0x361), VX_MASK, PPCLSP, 0, {RS, EVUIMM_8_EX0, RA}},
7994{"zstdwmx", VX(4, 0x362), VX_MASK, PPCLSP, 0, {RS_EVEN, RA, RB}},
7995{"zstdwu", VX(4, 0x363), VX_MASK, PPCLSP, 0, {RS_EVEN, EVUIMM_8_EX0, RA}},
7996{"zstdhmx", VX(4, 0x364), VX_MASK, PPCLSP, 0, {RS_EVEN, RA, RB}},
7997{"zstdhu", VX(4, 0x365), VX_MASK, PPCLSP, 0, {RS_EVEN, EVUIMM_8_EX0, RA}},
7998{"zstwhedmx", VX(4, 0x368), VX_MASK, PPCLSP, 0, {RS_EVEN, RA, RB}},
7999{"zstwhedu", VX(4, 0x369), VX_MASK, PPCLSP, 0, {RS_EVEN, EVUIMM_4_EX0, RA}},
8000{"zstwhodmx", VX(4, 0x36A), VX_MASK, PPCLSP, 0, {RS_EVEN, RA, RB}},
8001{"zstwhodu", VX(4, 0x36B), VX_MASK, PPCLSP, 0, {RS_EVEN, EVUIMM_4_EX0, RA}},
8002{"zlhhemx", VX(4, 0x370), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
8003{"zlhheu", VX(4, 0x371), VX_MASK, PPCLSP, 0, {RD, EVUIMM_2_EX0, RA}},
8004{"zlhhosmx", VX(4, 0x372), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
8005{"zlhhosu", VX(4, 0x373), VX_MASK, PPCLSP, 0, {RD, EVUIMM_2_EX0, RA}},
8006{"zlhhoumx", VX(4, 0x374), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
8007{"zlhhouu", VX(4, 0x375), VX_MASK, PPCLSP, 0, {RD, EVUIMM_2_EX0, RA}},
8008{"zsthemx", VX(4, 0x378), VX_MASK, PPCLSP, 0, {RS, RA, RB}},
8009{"zstheu", VX(4, 0x379), VX_MASK, PPCLSP, 0, {RS, EVUIMM_2_EX0, RA}},
8010{"zsthomx", VX(4, 0x37A), VX_MASK, PPCLSP, 0, {RS, RA, RB}},
8011{"zsthou", VX(4, 0x37B), VX_MASK, PPCLSP, 0, {RS, EVUIMM_2_EX0, RA}},
8012{"zstwhmx", VX(4, 0x37C), VX_MASK, PPCLSP, 0, {RS, RA, RB}},
8013{"zstwhu", VX(4, 0x37D), VX_MASK, PPCLSP, 0, {RS, EVUIMM_4_EX0, RA}},
8014{"zstwwmx", VX(4, 0x37E), VX_MASK, PPCLSP, 0, {RS, RA, RB}},
8015{"zstwwu", VX(4, 0x37F), VX_MASK, PPCLSP, 0, {RS, EVUIMM_4_EX0, RA}},
8016
14b57c7c 8017{"e_cmpi", SCI8BF(6,0,21), SCI8BF_MASK, PPCVLE, 0, {CRD32, RA, SCLSCI8}},
dfdaec14 8018{"e_cmpwi", SCI8BF(6,0,21), SCI8BF_MASK, PPCVLE, 0, {CRD32, RA, SCLSCI8}},
14b57c7c 8019{"e_cmpli", SCI8BF(6,1,21), SCI8BF_MASK, PPCVLE, 0, {CRD32, RA, SCLSCI8}},
dfdaec14 8020{"e_cmplwi", SCI8BF(6,1,21), SCI8BF_MASK, PPCVLE, 0, {CRD32, RA, SCLSCI8}},
14b57c7c
AM		 8021{"e_addi", SCI8(6,16), SCI8_MASK, PPCVLE, 0, {RT, RA, SCLSCI8}},
8022{"e_subi", SCI8(6,16), SCI8_MASK, PPCVLE, 0, {RT, RA, SCLSCI8N}},
8023{"e_addi.", SCI8(6,17), SCI8_MASK, PPCVLE, 0, {RT, RA, SCLSCI8}},
8024{"e_addic", SCI8(6,18), SCI8_MASK, PPCVLE, 0, {RT, RA, SCLSCI8}},
8025{"e_subic", SCI8(6,18), SCI8_MASK, PPCVLE, 0, {RT, RA, SCLSCI8N}},
8026{"e_addic.", SCI8(6,19), SCI8_MASK, PPCVLE, 0, {RT, RA, SCLSCI8}},
8027{"e_subic.", SCI8(6,19), SCI8_MASK, PPCVLE, 0, {RT, RA, SCLSCI8N}},
8028{"e_mulli", SCI8(6,20), SCI8_MASK, PPCVLE, 0, {RT, RA, SCLSCI8}},
8029{"e_subfic", SCI8(6,22), SCI8_MASK, PPCVLE, 0, {RT, RA, SCLSCI8}},
8030{"e_subfic.", SCI8(6,23), SCI8_MASK, PPCVLE, 0, {RT, RA, SCLSCI8}},
8031{"e_andi", SCI8(6,24), SCI8_MASK, PPCVLE, 0, {RA, RS, SCLSCI8}},
8032{"e_andi.", SCI8(6,25), SCI8_MASK, PPCVLE, 0, {RA, RS, SCLSCI8}},
8033{"e_nop", SCI8(6,26), 0xffffffff, PPCVLE, 0, {0}},
8034{"e_ori", SCI8(6,26), SCI8_MASK, PPCVLE, 0, {RA, RS, SCLSCI8}},
8035{"e_ori.", SCI8(6,27), SCI8_MASK, PPCVLE, 0, {RA, RS, SCLSCI8}},
8036{"e_xori", SCI8(6,28), SCI8_MASK, PPCVLE, 0, {RA, RS, SCLSCI8}},
8037{"e_xori.", SCI8(6,29), SCI8_MASK, PPCVLE, 0, {RA, RS, SCLSCI8}},
8038{"e_lbzu", OPVUP(6,0), OPVUP_MASK, PPCVLE, 0, {RT, D8, RA0}},
8039{"e_lhau", OPVUP(6,3), OPVUP_MASK, PPCVLE, 0, {RT, D8, RA0}},
8040{"e_lhzu", OPVUP(6,1), OPVUP_MASK, PPCVLE, 0, {RT, D8, RA0}},
8041{"e_lmw", OPVUP(6,8), OPVUP_MASK, PPCVLE, 0, {RT, D8, RA0}},
8042{"e_lwzu", OPVUP(6,2), OPVUP_MASK, PPCVLE, 0, {RT, D8, RA0}},
8043{"e_stbu", OPVUP(6,4), OPVUP_MASK, PPCVLE, 0, {RT, D8, RA0}},
8044{"e_sthu", OPVUP(6,5), OPVUP_MASK, PPCVLE, 0, {RT, D8, RA0}},
8045{"e_stwu", OPVUP(6,6), OPVUP_MASK, PPCVLE, 0, {RT, D8, RA0}},
8046{"e_stmw", OPVUP(6,9), OPVUP_MASK, PPCVLE, 0, {RT, D8, RA0}},
dfdaec14
AJ		 8047{"e_ldmvgprw", OPVUPRT(6,16,0),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}},
8048{"e_stmvgprw", OPVUPRT(6,17,0),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}},
8049{"e_ldmvsprw", OPVUPRT(6,16,1),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}},
8050{"e_stmvsprw", OPVUPRT(6,17,1),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}},
8051{"e_ldmvsrrw", OPVUPRT(6,16,4),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}},
8052{"e_stmvsrrw", OPVUPRT(6,17,4),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}},
8053{"e_ldmvcsrrw", OPVUPRT(6,16,5),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}},
8054{"e_stmvcsrrw", OPVUPRT(6,17,5),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}},
8055{"e_ldmvdsrrw", OPVUPRT(6,16,6),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}},
8056{"e_stmvdsrrw", OPVUPRT(6,17,6),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}},
14b57c7c
AM		 8057{"e_add16i", OP(7), OP_MASK, PPCVLE, 0, {RT, RA, SI}},
8058{"e_la", OP(7), OP_MASK, PPCVLE, 0, {RT, D, RA0}},
8059{"e_sub16i", OP(7), OP_MASK, PPCVLE, 0, {RT, RA, NSI}},
8060
8061{"se_addi", SE_IM5(8,0), SE_IM5_MASK, PPCVLE, 0, {RX, OIMM5}},
8062{"se_cmpli", SE_IM5(8,1), SE_IM5_MASK, PPCVLE, 0, {RX, OIMM5}},
8063{"se_subi", SE_IM5(9,0), SE_IM5_MASK, PPCVLE, 0, {RX, OIMM5}},
8064{"se_subi.", SE_IM5(9,1), SE_IM5_MASK, PPCVLE, 0, {RX, OIMM5}},
8065{"se_cmpi", SE_IM5(10,1), SE_IM5_MASK, PPCVLE, 0, {RX, UI5}},
8066{"se_bmaski", SE_IM5(11,0), SE_IM5_MASK, PPCVLE, 0, {RX, UI5}},
8067{"se_andi", SE_IM5(11,1), SE_IM5_MASK, PPCVLE, 0, {RX, UI5}},
8068
8069{"e_lbz", OP(12), OP_MASK, PPCVLE, 0, {RT, D, RA0}},
8070{"e_stb", OP(13), OP_MASK, PPCVLE, 0, {RT, D, RA0}},
8071{"e_lha", OP(14), OP_MASK, PPCVLE, 0, {RT, D, RA0}},
8072
8073{"se_srw", SE_RR(16,0), SE_RR_MASK, PPCVLE, 0, {RX, RY}},
8074{"se_sraw", SE_RR(16,1), SE_RR_MASK, PPCVLE, 0, {RX, RY}},
8075{"se_slw", SE_RR(16,2), SE_RR_MASK, PPCVLE, 0, {RX, RY}},
8076{"se_nop", SE_RR(17,0), 0xffff, PPCVLE, 0, {0}},
8077{"se_or", SE_RR(17,0), SE_RR_MASK, PPCVLE, 0, {RX, RY}},
8078{"se_andc", SE_RR(17,1), SE_RR_MASK, PPCVLE, 0, {RX, RY}},
8079{"se_and", SE_RR(17,2), SE_RR_MASK, PPCVLE, 0, {RX, RY}},
8080{"se_and.", SE_RR(17,3), SE_RR_MASK, PPCVLE, 0, {RX, RY}},
8081{"se_li", IM7(9), IM7_MASK, PPCVLE, 0, {RX, UI7}},
8082
8083{"e_lwz", OP(20), OP_MASK, PPCVLE, 0, {RT, D, RA0}},
8084{"e_stw", OP(21), OP_MASK, PPCVLE, 0, {RT, D, RA0}},
8085{"e_lhz", OP(22), OP_MASK, PPCVLE, 0, {RT, D, RA0}},
8086{"e_sth", OP(23), OP_MASK, PPCVLE, 0, {RT, D, RA0}},
8087
8088{"se_bclri", SE_IM5(24,0), SE_IM5_MASK, PPCVLE, 0, {RX, UI5}},
8089{"se_bgeni", SE_IM5(24,1), SE_IM5_MASK, PPCVLE, 0, {RX, UI5}},
8090{"se_bseti", SE_IM5(25,0), SE_IM5_MASK, PPCVLE, 0, {RX, UI5}},
8091{"se_btsti", SE_IM5(25,1), SE_IM5_MASK, PPCVLE, 0, {RX, UI5}},
8092{"se_srwi", SE_IM5(26,0), SE_IM5_MASK, PPCVLE, 0, {RX, UI5}},
8093{"se_srawi", SE_IM5(26,1), SE_IM5_MASK, PPCVLE, 0, {RX, UI5}},
8094{"se_slwi", SE_IM5(27,0), SE_IM5_MASK, PPCVLE, 0, {RX, UI5}},
8095
8096{"e_lis", I16L(28,28), I16L_MASK, PPCVLE, 0, {RD, VLEUIMML}},
8097{"e_and2is.", I16L(28,29), I16L_MASK, PPCVLE, 0, {RD, VLEUIMML}},
8098{"e_or2is", I16L(28,26), I16L_MASK, PPCVLE, 0, {RD, VLEUIMML}},
8099{"e_and2i.", I16L(28,25), I16L_MASK, PPCVLE, 0, {RD, VLEUIMML}},
8100{"e_or2i", I16L(28,24), I16L_MASK, PPCVLE, 0, {RD, VLEUIMML}},
8101{"e_cmphl16i", IA16(28,23), IA16_MASK, PPCVLE, 0, {RA, VLEUIMM}},
8102{"e_cmph16i", IA16(28,22), IA16_MASK, PPCVLE, 0, {RA, VLESIMM}},
8103{"e_cmpl16i", I16A(28,21), I16A_MASK, PPCVLE, 0, {RA, VLEUIMM}},
14b57c7c
AM		 8104{"e_mull2i", I16A(28,20), I16A_MASK, PPCVLE, 0, {RA, VLESIMM}},
8105{"e_cmp16i", IA16(28,19), IA16_MASK, PPCVLE, 0, {RA, VLESIMM}},
14b57c7c
AM		 8106{"e_sub2is", I16A(28,18), I16A_MASK, PPCVLE, 0, {RA, VLENSIMM}},
8107{"e_add2is", I16A(28,18), I16A_MASK, PPCVLE, 0, {RA, VLESIMM}},
8108{"e_sub2i.", I16A(28,17), I16A_MASK, PPCVLE, 0, {RA, VLENSIMM}},
8109{"e_add2i.", I16A(28,17), I16A_MASK, PPCVLE, 0, {RA, VLESIMM}},
8110{"e_li", LI20(28,0), LI20_MASK, PPCVLE, 0, {RT, IMM20}},
8111{"e_rlwimi", M(29,0), M_MASK, PPCVLE, 0, {RA, RS, SH, MB, ME}},
8112{"e_rlwinm", M(29,1), M_MASK, PPCVLE, 0, {RA, RT, SH, MBE, ME}},
8113{"e_b", BD24(30,0,0), BD24_MASK, PPCVLE, 0, {B24}},
8114{"e_bl", BD24(30,0,1), BD24_MASK, PPCVLE, 0, {B24}},
8115{"e_bdnz", EBD15(30,8,BO32DNZ,0), EBD15_MASK, PPCVLE, 0, {B15}},
8116{"e_bdnzl", EBD15(30,8,BO32DNZ,1), EBD15_MASK, PPCVLE, 0, {B15}},
8117{"e_bdz", EBD15(30,8,BO32DZ,0), EBD15_MASK, PPCVLE, 0, {B15}},
8118{"e_bdzl", EBD15(30,8,BO32DZ,1), EBD15_MASK, PPCVLE, 0, {B15}},
8119{"e_bge", EBD15BI(30,8,BO32F,CBLT,0), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}},
8120{"e_bgel", EBD15BI(30,8,BO32F,CBLT,1), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}},
8121{"e_bnl", EBD15BI(30,8,BO32F,CBLT,0), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}},
8122{"e_bnll", EBD15BI(30,8,BO32F,CBLT,1), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}},
8123{"e_blt", EBD15BI(30,8,BO32T,CBLT,0), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}},
8124{"e_bltl", EBD15BI(30,8,BO32T,CBLT,1), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}},
8125{"e_bgt", EBD15BI(30,8,BO32T,CBGT,0), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}},
8126{"e_bgtl", EBD15BI(30,8,BO32T,CBGT,1), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}},
8127{"e_ble", EBD15BI(30,8,BO32F,CBGT,0), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}},
8128{"e_blel", EBD15BI(30,8,BO32F,CBGT,1), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}},
8129{"e_bng", EBD15BI(30,8,BO32F,CBGT,0), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}},
8130{"e_bngl", EBD15BI(30,8,BO32F,CBGT,1), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}},
8131{"e_bne", EBD15BI(30,8,BO32F,CBEQ,0), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}},
8132{"e_bnel", EBD15BI(30,8,BO32F,CBEQ,1), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}},
8133{"e_beq", EBD15BI(30,8,BO32T,CBEQ,0), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}},
8134{"e_beql", EBD15BI(30,8,BO32T,CBEQ,1), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}},
8135{"e_bso", EBD15BI(30,8,BO32T,CBSO,0), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}},
8136{"e_bsol", EBD15BI(30,8,BO32T,CBSO,1), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}},
8137{"e_bun", EBD15BI(30,8,BO32T,CBSO,0), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}},
8138{"e_bunl", EBD15BI(30,8,BO32T,CBSO,1), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}},
8139{"e_bns", EBD15BI(30,8,BO32F,CBSO,0), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}},
8140{"e_bnsl", EBD15BI(30,8,BO32F,CBSO,1), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}},
8141{"e_bnu", EBD15BI(30,8,BO32F,CBSO,0), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}},
8142{"e_bnul", EBD15BI(30,8,BO32F,CBSO,1), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}},
8143{"e_bc", BD15(30,8,0), BD15_MASK, PPCVLE, 0, {BO32, BI32, B15}},
8144{"e_bcl", BD15(30,8,1), BD15_MASK, PPCVLE, 0, {BO32, BI32, B15}},
8145
8146{"e_bf", EBD15(30,8,BO32F,0), EBD15_MASK, PPCVLE, 0, {BI32,B15}},
8147{"e_bfl", EBD15(30,8,BO32F,1), EBD15_MASK, PPCVLE, 0, {BI32,B15}},
8148{"e_bt", EBD15(30,8,BO32T,0), EBD15_MASK, PPCVLE, 0, {BI32,B15}},
8149{"e_btl", EBD15(30,8,BO32T,1), EBD15_MASK, PPCVLE, 0, {BI32,B15}},
8150
8151{"e_cmph", X(31,14), X_MASK, PPCVLE, 0, {CRD, RA, RB}},
a8cc8a54 8152{"e_sc", X(31,36), XRTRA_MASK, PPCVLE, 0, {ELEV}},
14b57c7c
AM		 8153{"e_cmphl", X(31,46), X_MASK, PPCVLE, 0, {CRD, RA, RB}},
8154{"e_crandc", XL(31,129), XL_MASK, PPCVLE, 0, {BT, BA, BB}},
8155{"e_crnand", XL(31,225), XL_MASK, PPCVLE, 0, {BT, BA, BB}},
8156{"e_crnot", XL(31,33), XL_MASK, PPCVLE, 0, {BT, BA, BBA}},
8157{"e_crnor", XL(31,33), XL_MASK, PPCVLE, 0, {BT, BA, BB}},
8158{"e_crclr", XL(31,193), XL_MASK, PPCVLE, 0, {BT, BAT, BBA}},
8159{"e_crxor", XL(31,193), XL_MASK, PPCVLE, 0, {BT, BA, BB}},
8160{"e_mcrf", XL(31,16), XL_MASK, PPCVLE, 0, {CRD, CR}},
8161{"e_slwi", EX(31,112), EX_MASK, PPCVLE, 0, {RA, RS, SH}},
8162{"e_slwi.", EX(31,113), EX_MASK, PPCVLE, 0, {RA, RS, SH}},
8163
8164{"e_crand", XL(31,257), XL_MASK, PPCVLE, 0, {BT, BA, BB}},
8165
8166{"e_rlw", EX(31,560), EX_MASK, PPCVLE, 0, {RA, RS, RB}},
8167{"e_rlw.", EX(31,561), EX_MASK, PPCVLE, 0, {RA, RS, RB}},
8168
8169{"e_crset", XL(31,289), XL_MASK, PPCVLE, 0, {BT, BAT, BBA}},
8170{"e_creqv", XL(31,289), XL_MASK, PPCVLE, 0, {BT, BA, BB}},
8171
8172{"e_rlwi", EX(31,624), EX_MASK, PPCVLE, 0, {RA, RS, SH}},
8173{"e_rlwi.", EX(31,625), EX_MASK, PPCVLE, 0, {RA, RS, SH}},
8174
8175{"e_crorc", XL(31,417), XL_MASK, PPCVLE, 0, {BT, BA, BB}},
8176
8177{"e_crmove", XL(31,449), XL_MASK, PPCVLE, 0, {BT, BA, BBA}},
8178{"e_cror", XL(31,449), XL_MASK, PPCVLE, 0, {BT, BA, BB}},
8179
8180{"mtmas1", XSPR(31,467,625), XSPR_MASK, PPCVLE, 0, {RS}},
8181
8182{"e_srwi", EX(31,1136), EX_MASK, PPCVLE, 0, {RA, RS, SH}},
8183{"e_srwi.", EX(31,1137), EX_MASK, PPCVLE, 0, {RA, RS, SH}},
8184
8185{"se_lbz", SD4(8), SD4_MASK, PPCVLE, 0, {RZ, SE_SD, RX}},
8186
8187{"se_stb", SD4(9), SD4_MASK, PPCVLE, 0, {RZ, SE_SD, RX}},
8188
8189{"se_lhz", SD4(10), SD4_MASK, PPCVLE, 0, {RZ, SE_SDH, RX}},
8190
8191{"se_sth", SD4(11), SD4_MASK, PPCVLE, 0, {RZ, SE_SDH, RX}},
8192
8193{"se_lwz", SD4(12), SD4_MASK, PPCVLE, 0, {RZ, SE_SDW, RX}},
8194
8195{"se_stw", SD4(13), SD4_MASK, PPCVLE, 0, {RZ, SE_SDW, RX}},
8196
8197{"se_bge", EBD8IO(28,0,0), EBD8IO3_MASK, PPCVLE, 0, {B8}},
8198{"se_bnl", EBD8IO(28,0,0), EBD8IO3_MASK, PPCVLE, 0, {B8}},
8199{"se_ble", EBD8IO(28,0,1), EBD8IO3_MASK, PPCVLE, 0, {B8}},
8200{"se_bng", EBD8IO(28,0,1), EBD8IO3_MASK, PPCVLE, 0, {B8}},
8201{"se_bne", EBD8IO(28,0,2), EBD8IO3_MASK, PPCVLE, 0, {B8}},
8202{"se_bns", EBD8IO(28,0,3), EBD8IO3_MASK, PPCVLE, 0, {B8}},
8203{"se_bnu", EBD8IO(28,0,3), EBD8IO3_MASK, PPCVLE, 0, {B8}},
8204{"se_bf", EBD8IO(28,0,0), EBD8IO2_MASK, PPCVLE, 0, {BI16, B8}},
8205{"se_blt", EBD8IO(28,1,0), EBD8IO3_MASK, PPCVLE, 0, {B8}},
8206{"se_bgt", EBD8IO(28,1,1), EBD8IO3_MASK, PPCVLE, 0, {B8}},
8207{"se_beq", EBD8IO(28,1,2), EBD8IO3_MASK, PPCVLE, 0, {B8}},
8208{"se_bso", EBD8IO(28,1,3), EBD8IO3_MASK, PPCVLE, 0, {B8}},
8209{"se_bun", EBD8IO(28,1,3), EBD8IO3_MASK, PPCVLE, 0, {B8}},
8210{"se_bt", EBD8IO(28,1,0), EBD8IO2_MASK, PPCVLE, 0, {BI16, B8}},
8211{"se_bc", BD8IO(28), BD8IO_MASK, PPCVLE, 0, {BO16, BI16, B8}},
8212{"se_b", BD8(58,0,0), BD8_MASK, PPCVLE, 0, {B8}},
8213{"se_bl", BD8(58,0,1), BD8_MASK, PPCVLE, 0, {B8}},
b9c361e0
JL		 8214};
8215
8216const int vle_num_opcodes =
8217 sizeof (vle_opcodes) / sizeof (vle_opcodes[0]);
8218\f
252b5132
RH		 8219/* The macro table. This is only used by the assembler. */
8220
8221/* The expressions of the form (-x ! 31) & (x | 31) have the value 0
8222 when x=0; 32-x when x is between 1 and 31; are negative if x is
8223 negative; and are 32 or more otherwise. This is what you want
8224 when, for instance, you are emulating a right shift by a
8225 rotate-left-and-mask, because the underlying instructions support
8226 shifts of size 0 but not shifts of size 32. By comparison, when
8227 extracting x bits from some word you want to use just 32-x, because
8228 the underlying instructions don't support extracting 0 bits but do
8229 support extracting the whole word (32 bits in this case). */
8230
8231const struct powerpc_macro powerpc_macros[] = {
de866fcc
AM		 8232{"extldi", 4, PPC64, "rldicr %0,%1,%3,(%2)-1"},
8233{"extldi.", 4, PPC64, "rldicr. %0,%1,%3,(%2)-1"},
bdc7fcfe
AM		 8234{"extrdi", 4, PPC64, "rldicl %0,%1,((%2)+(%3))&((%2)+(%3)<>64),64-(%2)"},
8235{"extrdi.", 4, PPC64, "rldicl. %0,%1,((%2)+(%3))&((%2)+(%3)<>64),64-(%2)"},
de866fcc
AM		 8236{"insrdi", 4, PPC64, "rldimi %0,%1,64-((%2)+(%3)),%3"},
8237{"insrdi.", 4, PPC64, "rldimi. %0,%1,64-((%2)+(%3)),%3"},
8238{"rotrdi", 3, PPC64, "rldicl %0,%1,(-(%2)!63)&((%2)|63),0"},
8239{"rotrdi.", 3, PPC64, "rldicl. %0,%1,(-(%2)!63)&((%2)|63),0"},
8240{"sldi", 3, PPC64, "rldicr %0,%1,%2,63-(%2)"},
8241{"sldi.", 3, PPC64, "rldicr. %0,%1,%2,63-(%2)"},
8242{"srdi", 3, PPC64, "rldicl %0,%1,(-(%2)!63)&((%2)|63),%2"},
8243{"srdi.", 3, PPC64, "rldicl. %0,%1,(-(%2)!63)&((%2)|63),%2"},
8244{"clrrdi", 3, PPC64, "rldicr %0,%1,0,63-(%2)"},
8245{"clrrdi.", 3, PPC64, "rldicr. %0,%1,0,63-(%2)"},
8246{"clrlsldi", 4, PPC64, "rldic %0,%1,%3,(%2)-(%3)"},
14b57c7c 8247{"clrlsldi.",4, PPC64, "rldic. %0,%1,%3,(%2)-(%3)"},
de866fcc
AM		 8248
8249{"extlwi", 4, PPCCOM, "rlwinm %0,%1,%3,0,(%2)-1"},
8250{"extlwi.", 4, PPCCOM, "rlwinm. %0,%1,%3,0,(%2)-1"},
8251{"extrwi", 4, PPCCOM, "rlwinm %0,%1,((%2)+(%3))&((%2)+(%3)<>32),32-(%2),31"},
8252{"extrwi.", 4, PPCCOM, "rlwinm. %0,%1,((%2)+(%3))&((%2)+(%3)<>32),32-(%2),31"},
8253{"inslwi", 4, PPCCOM, "rlwimi %0,%1,(-(%3)!31)&((%3)|31),%3,(%2)+(%3)-1"},
8254{"inslwi.", 4, PPCCOM, "rlwimi. %0,%1,(-(%3)!31)&((%3)|31),%3,(%2)+(%3)-1"},
8255{"insrwi", 4, PPCCOM, "rlwimi %0,%1,32-((%2)+(%3)),%3,(%2)+(%3)-1"},
8256{"insrwi.", 4, PPCCOM, "rlwimi. %0,%1,32-((%2)+(%3)),%3,(%2)+(%3)-1"},
8257{"rotrwi", 3, PPCCOM, "rlwinm %0,%1,(-(%2)!31)&((%2)|31),0,31"},
8258{"rotrwi.", 3, PPCCOM, "rlwinm. %0,%1,(-(%2)!31)&((%2)|31),0,31"},
8259{"slwi", 3, PPCCOM, "rlwinm %0,%1,%2,0,31-(%2)"},
8260{"sli", 3, PWRCOM, "rlinm %0,%1,%2,0,31-(%2)"},
8261{"slwi.", 3, PPCCOM, "rlwinm. %0,%1,%2,0,31-(%2)"},
8262{"sli.", 3, PWRCOM, "rlinm. %0,%1,%2,0,31-(%2)"},
8263{"srwi", 3, PPCCOM, "rlwinm %0,%1,(-(%2)!31)&((%2)|31),%2,31"},
8264{"sri", 3, PWRCOM, "rlinm %0,%1,(-(%2)!31)&((%2)|31),%2,31"},
8265{"srwi.", 3, PPCCOM, "rlwinm. %0,%1,(-(%2)!31)&((%2)|31),%2,31"},
8266{"sri.", 3, PWRCOM, "rlinm. %0,%1,(-(%2)!31)&((%2)|31),%2,31"},
8267{"clrrwi", 3, PPCCOM, "rlwinm %0,%1,0,0,31-(%2)"},
8268{"clrrwi.", 3, PPCCOM, "rlwinm. %0,%1,0,0,31-(%2)"},
8269{"clrlslwi", 4, PPCCOM, "rlwinm %0,%1,%3,(%2)-(%3),31-(%3)"},
8270{"clrlslwi.",4, PPCCOM, "rlwinm. %0,%1,%3,(%2)-(%3),31-(%3)"},
a4ebc835
AM		 8271
8272{"e_extlwi", 4, PPCVLE, "e_rlwinm %0,%1,%3,0,(%2)-1"},
8273{"e_extrwi", 4, PPCVLE, "e_rlwinm %0,%1,((%2)+(%3))&((%2)+(%3)<>32),32-(%2),31"},
8274{"e_inslwi", 4, PPCVLE, "e_rlwimi %0,%1,(-(%3)!31)&((%3)|31),%3,(%2)+(%3)-1"},
8275{"e_insrwi", 4, PPCVLE, "e_rlwimi %0,%1,32-((%2)+(%3)),%3,(%2)+(%3)-1"},
8276{"e_rotlwi", 3, PPCVLE, "e_rlwinm %0,%1,%2,0,31"},
8277{"e_rotrwi", 3, PPCVLE, "e_rlwinm %0,%1,(-(%2)!31)&((%2)|31),0,31"},
8278{"e_slwi", 3, PPCVLE, "e_rlwinm %0,%1,%2,0,31-(%2)"},
8279{"e_srwi", 3, PPCVLE, "e_rlwinm %0,%1,(-(%2)!31)&((%2)|31),%2,31"},
8280{"e_clrlwi", 3, PPCVLE, "e_rlwinm %0,%1,0,%2,31"},
8281{"e_clrrwi", 3, PPCVLE, "e_rlwinm %0,%1,0,0,31-(%2)"},
8282{"e_clrlslwi",4, PPCVLE, "e_rlwinm %0,%1,%3,(%2)-(%3),31-(%3)"},
252b5132
RH		 8283};
8284
8285const int powerpc_num_macros =
8286 sizeof (powerpc_macros) / sizeof (powerpc_macros[0]);
GDB Binutils - Deliverables
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