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[deliverable/binutils-gdb.git] / opcodes / xstormy16-desc.c
CommitLineData
93fbbb04
GK		 1/* CPU data for xstormy16.
2
3THIS FILE IS MACHINE GENERATED WITH CGEN.
4
1951c6f7 5Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc.
93fbbb04
GK		 6
7This file is part of the GNU Binutils and/or GDB, the GNU debugger.
8
9This program is free software; you can redistribute it and/or modify
10it under the terms of the GNU General Public License as published by
11the Free Software Foundation; either version 2, or (at your option)
12any later version.
13
14This program is distributed in the hope that it will be useful,
15but WITHOUT ANY WARRANTY; without even the implied warranty of
16MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17GNU General Public License for more details.
18
19You should have received a copy of the GNU General Public License along
20with this program; if not, write to the Free Software Foundation, Inc.,
2159 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
22
23*/
24
25#include "sysdep.h"
26#include <stdio.h>
27#include <stdarg.h>
28#include "ansidecl.h"
29#include "bfd.h"
30#include "symcat.h"
31#include "xstormy16-desc.h"
32#include "xstormy16-opc.h"
33#include "opintl.h"
34#include "libiberty.h"
35
36/* Attributes. */
37
38static const CGEN_ATTR_ENTRY bool_attr[] =
39{
40 { "#f", 0 },
41 { "#t", 1 },
42 { 0, 0 }
43};
44
45static const CGEN_ATTR_ENTRY MACH_attr[] =
46{
47 { "base", MACH_BASE },
48 { "xstormy16", MACH_XSTORMY16 },
49 { "max", MACH_MAX },
50 { 0, 0 }
51};
52
53static const CGEN_ATTR_ENTRY ISA_attr[] =
54{
55 { "xstormy16", ISA_XSTORMY16 },
56 { "max", ISA_MAX },
57 { 0, 0 }
58};
59
60const CGEN_ATTR_TABLE xstormy16_cgen_ifield_attr_table[] =
61{
62 { "MACH", & MACH_attr[0], & MACH_attr[0] },
63 { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
64 { "PCREL-ADDR", &bool_attr[0], &bool_attr[0] },
65 { "ABS-ADDR", &bool_attr[0], &bool_attr[0] },
66 { "RESERVED", &bool_attr[0], &bool_attr[0] },
67 { "SIGN-OPT", &bool_attr[0], &bool_attr[0] },
68 { "SIGNED", &bool_attr[0], &bool_attr[0] },
69 { 0, 0, 0 }
70};
71
72const CGEN_ATTR_TABLE xstormy16_cgen_hardware_attr_table[] =
73{
74 { "MACH", & MACH_attr[0], & MACH_attr[0] },
75 { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
76 { "CACHE-ADDR", &bool_attr[0], &bool_attr[0] },
77 { "PC", &bool_attr[0], &bool_attr[0] },
78 { "PROFILE", &bool_attr[0], &bool_attr[0] },
79 { 0, 0, 0 }
80};
81
82const CGEN_ATTR_TABLE xstormy16_cgen_operand_attr_table[] =
83{
84 { "MACH", & MACH_attr[0], & MACH_attr[0] },
85 { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
86 { "PCREL-ADDR", &bool_attr[0], &bool_attr[0] },
87 { "ABS-ADDR", &bool_attr[0], &bool_attr[0] },
88 { "SIGN-OPT", &bool_attr[0], &bool_attr[0] },
89 { "SIGNED", &bool_attr[0], &bool_attr[0] },
90 { "NEGATIVE", &bool_attr[0], &bool_attr[0] },
91 { "RELAX", &bool_attr[0], &bool_attr[0] },
92 { "SEM-ONLY", &bool_attr[0], &bool_attr[0] },
93 { 0, 0, 0 }
94};
95
96const CGEN_ATTR_TABLE xstormy16_cgen_insn_attr_table[] =
97{
98 { "MACH", & MACH_attr[0], & MACH_attr[0] },
99 { "ALIAS", &bool_attr[0], &bool_attr[0] },
100 { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
101 { "UNCOND-CTI", &bool_attr[0], &bool_attr[0] },
102 { "COND-CTI", &bool_attr[0], &bool_attr[0] },
103 { "SKIP-CTI", &bool_attr[0], &bool_attr[0] },
104 { "DELAY-SLOT", &bool_attr[0], &bool_attr[0] },
105 { "RELAXABLE", &bool_attr[0], &bool_attr[0] },
106 { "RELAX", &bool_attr[0], &bool_attr[0] },
107 { "NO-DIS", &bool_attr[0], &bool_attr[0] },
108 { "PBB", &bool_attr[0], &bool_attr[0] },
109 { 0, 0, 0 }
110};
111
112/* Instruction set variants. */
113
114static const CGEN_ISA xstormy16_cgen_isa_table[] = {
115 { "xstormy16", 32, 32, 16, 32 },
116 { 0, 0, 0, 0, 0 }
117};
118
119/* Machine variants. */
120
121static const CGEN_MACH xstormy16_cgen_mach_table[] = {
122 { "xstormy16", "xstormy16", MACH_XSTORMY16, 16 },
123 { 0, 0, 0, 0 }
124};
125
126static CGEN_KEYWORD_ENTRY xstormy16_cgen_opval_gr_names_entries[] =
127{
128 { "r0", 0, {0, {0}}, 0, 0 },
129 { "r1", 1, {0, {0}}, 0, 0 },
130 { "r2", 2, {0, {0}}, 0, 0 },
131 { "r3", 3, {0, {0}}, 0, 0 },
132 { "r4", 4, {0, {0}}, 0, 0 },
133 { "r5", 5, {0, {0}}, 0, 0 },
134 { "r6", 6, {0, {0}}, 0, 0 },
135 { "r7", 7, {0, {0}}, 0, 0 },
136 { "r8", 8, {0, {0}}, 0, 0 },
137 { "r9", 9, {0, {0}}, 0, 0 },
138 { "r10", 10, {0, {0}}, 0, 0 },
139 { "r11", 11, {0, {0}}, 0, 0 },
140 { "r12", 12, {0, {0}}, 0, 0 },
141 { "r13", 13, {0, {0}}, 0, 0 },
142 { "r14", 14, {0, {0}}, 0, 0 },
143 { "r15", 15, {0, {0}}, 0, 0 },
144 { "psw", 14, {0, {0}}, 0, 0 },
145 { "sp", 15, {0, {0}}, 0, 0 }
146};
147
148CGEN_KEYWORD xstormy16_cgen_opval_gr_names =
149{
150 & xstormy16_cgen_opval_gr_names_entries[0],
151 18,
152 0, 0, 0, 0, ""
153};
154
1951c6f7 155static CGEN_KEYWORD_ENTRY xstormy16_cgen_opval_gr_Rb_names_entries[] =
93fbbb04
GK		 156{
157 { "r8", 0, {0, {0}}, 0, 0 },
1951c6f7
MG		 158 { "r9", 1, {0, {0}}, 0, 0 },
159 { "r10", 2, {0, {0}}, 0, 0 },
160 { "r11", 3, {0, {0}}, 0, 0 },
161 { "r12", 4, {0, {0}}, 0, 0 },
162 { "r13", 5, {0, {0}}, 0, 0 },
163 { "r14", 6, {0, {0}}, 0, 0 },
164 { "r15", 7, {0, {0}}, 0, 0 },
165 { "psw", 6, {0, {0}}, 0, 0 },
166 { "sp", 7, {0, {0}}, 0, 0 }
93fbbb04
GK		 167};
168
1951c6f7 169CGEN_KEYWORD xstormy16_cgen_opval_gr_Rb_names =
93fbbb04 170{
1951c6f7
MG		 171 & xstormy16_cgen_opval_gr_Rb_names_entries[0],
172 10,
93fbbb04
GK		 173 0, 0, 0, 0, ""
174};
175
176static CGEN_KEYWORD_ENTRY xstormy16_cgen_opval_h_branchcond_entries[] =
177{
178 { "ge", 0, {0, {0}}, 0, 0 },
179 { "nc", 1, {0, {0}}, 0, 0 },
180 { "lt", 2, {0, {0}}, 0, 0 },
181 { "c", 3, {0, {0}}, 0, 0 },
182 { "gt", 4, {0, {0}}, 0, 0 },
183 { "hi", 5, {0, {0}}, 0, 0 },
184 { "le", 6, {0, {0}}, 0, 0 },
185 { "ls", 7, {0, {0}}, 0, 0 },
186 { "pl", 8, {0, {0}}, 0, 0 },
187 { "nv", 9, {0, {0}}, 0, 0 },
188 { "mi", 10, {0, {0}}, 0, 0 },
189 { "v", 11, {0, {0}}, 0, 0 },
190 { "nz.b", 12, {0, {0}}, 0, 0 },
191 { "nz", 13, {0, {0}}, 0, 0 },
192 { "z.b", 14, {0, {0}}, 0, 0 },
193 { "z", 15, {0, {0}}, 0, 0 }
194};
195
196CGEN_KEYWORD xstormy16_cgen_opval_h_branchcond =
197{
198 & xstormy16_cgen_opval_h_branchcond_entries[0],
199 16,
200 0, 0, 0, 0, ""
201};
202
203static CGEN_KEYWORD_ENTRY xstormy16_cgen_opval_h_wordsize_entries[] =
204{
205 { ".b", 0, {0, {0}}, 0, 0 },
206 { ".w", 1, {0, {0}}, 0, 0 },
207 { "", 1, {0, {0}}, 0, 0 }
208};
209
210CGEN_KEYWORD xstormy16_cgen_opval_h_wordsize =
211{
212 & xstormy16_cgen_opval_h_wordsize_entries[0],
213 3,
214 0, 0, 0, 0, ""
215};
216
217
218/* The hardware table. */
219
220#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
221#define A(a) (1 << CGEN_HW_##a)
222#else
223#define A(a) (1 << CGEN_HW_/**/a)
224#endif
225
226const CGEN_HW_ENTRY xstormy16_cgen_hw_table[] =
227{
228 { "h-memory", HW_H_MEMORY, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
229 { "h-sint", HW_H_SINT, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
230 { "h-uint", HW_H_UINT, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
231 { "h-addr", HW_H_ADDR, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
232 { "h-iaddr", HW_H_IADDR, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
233 { "h-pc", HW_H_PC, CGEN_ASM_NONE, 0, { 0|A(PC), { (1<<MACH_BASE) } } },
234 { "h-gr", HW_H_GR, CGEN_ASM_KEYWORD, (PTR) & xstormy16_cgen_opval_gr_names, { 0, { (1<<MACH_BASE) } } },
1951c6f7
MG		 235 { "h-Rb", HW_H_RB, CGEN_ASM_KEYWORD, (PTR) & xstormy16_cgen_opval_gr_Rb_names, { 0|A(VIRTUAL), { (1<<MACH_BASE) } } },
236 { "h-Rbj", HW_H_RBJ, CGEN_ASM_KEYWORD, (PTR) & xstormy16_cgen_opval_gr_Rb_names, { 0|A(VIRTUAL), { (1<<MACH_BASE) } } },
93fbbb04
GK		 237 { "h-Rpsw", HW_H_RPSW, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { (1<<MACH_BASE) } } },
238 { "h-z8", HW_H_Z8, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { (1<<MACH_BASE) } } },
239 { "h-z16", HW_H_Z16, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { (1<<MACH_BASE) } } },
240 { "h-cy", HW_H_CY, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { (1<<MACH_BASE) } } },
241 { "h-hc", HW_H_HC, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { (1<<MACH_BASE) } } },
242 { "h-ov", HW_H_OV, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { (1<<MACH_BASE) } } },
243 { "h-pt", HW_H_PT, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { (1<<MACH_BASE) } } },
244 { "h-s", HW_H_S, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { (1<<MACH_BASE) } } },
245 { "h-branchcond", HW_H_BRANCHCOND, CGEN_ASM_KEYWORD, (PTR) & xstormy16_cgen_opval_h_branchcond, { 0, { (1<<MACH_BASE) } } },
246 { "h-wordsize", HW_H_WORDSIZE, CGEN_ASM_KEYWORD, (PTR) & xstormy16_cgen_opval_h_wordsize, { 0, { (1<<MACH_BASE) } } },
247 { 0, 0, CGEN_ASM_NONE, 0, {0, {0}} }
248};
249
250#undef A
251
252
253/* The instruction field table. */
254
255#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
256#define A(a) (1 << CGEN_IFLD_##a)
257#else
258#define A(a) (1 << CGEN_IFLD_/**/a)
259#endif
260
261const CGEN_IFLD xstormy16_cgen_ifld_table[] =
262{
263 { XSTORMY16_F_NIL, "f-nil", 0, 0, 0, 0, { 0, { (1<<MACH_BASE) } } },
264 { XSTORMY16_F_ANYOF, "f-anyof", 0, 0, 0, 0, { 0, { (1<<MACH_BASE) } } },
265 { XSTORMY16_F_RD, "f-Rd", 0, 32, 12, 4, { 0, { (1<<MACH_BASE) } } },
266 { XSTORMY16_F_RDM, "f-Rdm", 0, 32, 13, 3, { 0, { (1<<MACH_BASE) } } },
267 { XSTORMY16_F_RM, "f-Rm", 0, 32, 4, 3, { 0, { (1<<MACH_BASE) } } },
268 { XSTORMY16_F_RS, "f-Rs", 0, 32, 8, 4, { 0, { (1<<MACH_BASE) } } },
269 { XSTORMY16_F_RB, "f-Rb", 0, 32, 17, 3, { 0, { (1<<MACH_BASE) } } },
270 { XSTORMY16_F_RBJ, "f-Rbj", 0, 32, 11, 1, { 0, { (1<<MACH_BASE) } } },
271 { XSTORMY16_F_OP1, "f-op1", 0, 32, 0, 4, { 0, { (1<<MACH_BASE) } } },
272 { XSTORMY16_F_OP2, "f-op2", 0, 32, 4, 4, { 0, { (1<<MACH_BASE) } } },
273 { XSTORMY16_F_OP2A, "f-op2a", 0, 32, 4, 3, { 0, { (1<<MACH_BASE) } } },
274 { XSTORMY16_F_OP2M, "f-op2m", 0, 32, 7, 1, { 0, { (1<<MACH_BASE) } } },
275 { XSTORMY16_F_OP3, "f-op3", 0, 32, 8, 4, { 0, { (1<<MACH_BASE) } } },
276 { XSTORMY16_F_OP3A, "f-op3a", 0, 32, 8, 2, { 0, { (1<<MACH_BASE) } } },
277 { XSTORMY16_F_OP3B, "f-op3b", 0, 32, 8, 3, { 0, { (1<<MACH_BASE) } } },
278 { XSTORMY16_F_OP4, "f-op4", 0, 32, 12, 4, { 0, { (1<<MACH_BASE) } } },
279 { XSTORMY16_F_OP4M, "f-op4m", 0, 32, 12, 1, { 0, { (1<<MACH_BASE) } } },
280 { XSTORMY16_F_OP4B, "f-op4b", 0, 32, 15, 1, { 0, { (1<<MACH_BASE) } } },
281 { XSTORMY16_F_OP5, "f-op5", 0, 32, 16, 4, { 0, { (1<<MACH_BASE) } } },
282 { XSTORMY16_F_OP5A, "f-op5a", 0, 32, 16, 1, { 0, { (1<<MACH_BASE) } } },
283 { XSTORMY16_F_OP, "f-op", 0, 32, 0, 16, { 0, { (1<<MACH_BASE) } } },
284 { XSTORMY16_F_IMM2, "f-imm2", 0, 32, 10, 2, { 0, { (1<<MACH_BASE) } } },
285 { XSTORMY16_F_IMM3, "f-imm3", 0, 32, 4, 3, { 0, { (1<<MACH_BASE) } } },
286 { XSTORMY16_F_IMM3B, "f-imm3b", 0, 32, 17, 3, { 0, { (1<<MACH_BASE) } } },
287 { XSTORMY16_F_IMM4, "f-imm4", 0, 32, 8, 4, { 0, { (1<<MACH_BASE) } } },
288 { XSTORMY16_F_IMM8, "f-imm8", 0, 32, 8, 8, { 0, { (1<<MACH_BASE) } } },
289 { XSTORMY16_F_IMM12, "f-imm12", 0, 32, 20, 12, { 0, { (1<<MACH_BASE) } } },
290 { XSTORMY16_F_IMM16, "f-imm16", 0, 32, 16, 16, { 0|A(SIGN_OPT), { (1<<MACH_BASE) } } },
291 { XSTORMY16_F_LMEM8, "f-lmem8", 0, 32, 8, 8, { 0|A(ABS_ADDR), { (1<<MACH_BASE) } } },
292 { XSTORMY16_F_HMEM8, "f-hmem8", 0, 32, 8, 8, { 0|A(ABS_ADDR), { (1<<MACH_BASE) } } },
293 { XSTORMY16_F_REL8_2, "f-rel8-2", 0, 32, 8, 8, { 0|A(PCREL_ADDR), { (1<<MACH_BASE) } } },
294 { XSTORMY16_F_REL8_4, "f-rel8-4", 0, 32, 8, 8, { 0|A(PCREL_ADDR), { (1<<MACH_BASE) } } },
295 { XSTORMY16_F_REL12, "f-rel12", 0, 32, 20, 12, { 0|A(PCREL_ADDR), { (1<<MACH_BASE) } } },
296 { XSTORMY16_F_REL12A, "f-rel12a", 0, 32, 4, 11, { 0|A(PCREL_ADDR), { (1<<MACH_BASE) } } },
297 { XSTORMY16_F_ABS24_1, "f-abs24-1", 0, 32, 8, 8, { 0, { (1<<MACH_BASE) } } },
298 { XSTORMY16_F_ABS24_2, "f-abs24-2", 0, 32, 16, 16, { 0, { (1<<MACH_BASE) } } },
299 { 0, 0, 0, 0, 0, 0, {0, {0}} }
300};
301
302#undef A
303
304
305/* The operand table. */
306
307#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
308#define A(a) (1 << CGEN_OPERAND_##a)
309#else
310#define A(a) (1 << CGEN_OPERAND_/**/a)
311#endif
312#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
313#define OPERAND(op) XSTORMY16_OPERAND_##op
314#else
315#define OPERAND(op) XSTORMY16_OPERAND_/**/op
316#endif
317
318const CGEN_OPERAND xstormy16_cgen_operand_table[] =
319{
320/* pc: program counter */
321 { "pc", XSTORMY16_OPERAND_PC, HW_H_PC, 0, 0,
322 { 0|A(SEM_ONLY), { (1<<MACH_BASE) } } },
323/* psw-z8: */
324 { "psw-z8", XSTORMY16_OPERAND_PSW_Z8, HW_H_Z8, 0, 0,
325 { 0|A(SEM_ONLY), { (1<<MACH_BASE) } } },
326/* psw-z16: */
327 { "psw-z16", XSTORMY16_OPERAND_PSW_Z16, HW_H_Z16, 0, 0,
328 { 0|A(SEM_ONLY), { (1<<MACH_BASE) } } },
329/* psw-cy: */
330 { "psw-cy", XSTORMY16_OPERAND_PSW_CY, HW_H_CY, 0, 0,
331 { 0|A(SEM_ONLY), { (1<<MACH_BASE) } } },
332/* psw-hc: */
333 { "psw-hc", XSTORMY16_OPERAND_PSW_HC, HW_H_HC, 0, 0,
334 { 0|A(SEM_ONLY), { (1<<MACH_BASE) } } },
335/* psw-ov: */
336 { "psw-ov", XSTORMY16_OPERAND_PSW_OV, HW_H_OV, 0, 0,
337 { 0|A(SEM_ONLY), { (1<<MACH_BASE) } } },
338/* psw-pt: */
339 { "psw-pt", XSTORMY16_OPERAND_PSW_PT, HW_H_PT, 0, 0,
340 { 0|A(SEM_ONLY), { (1<<MACH_BASE) } } },
341/* psw-s: */
342 { "psw-s", XSTORMY16_OPERAND_PSW_S, HW_H_S, 0, 0,
343 { 0|A(SEM_ONLY), { (1<<MACH_BASE) } } },
344/* Rd: general register destination */
345 { "Rd", XSTORMY16_OPERAND_RD, HW_H_GR, 12, 4,
346 { 0, { (1<<MACH_BASE) } } },
347/* Rdm: general register destination */
348 { "Rdm", XSTORMY16_OPERAND_RDM, HW_H_GR, 13, 3,
349 { 0, { (1<<MACH_BASE) } } },
350/* Rm: general register for memory */
351 { "Rm", XSTORMY16_OPERAND_RM, HW_H_GR, 4, 3,
352 { 0, { (1<<MACH_BASE) } } },
353/* Rs: general register source */
354 { "Rs", XSTORMY16_OPERAND_RS, HW_H_GR, 8, 4,
355 { 0, { (1<<MACH_BASE) } } },
356/* Rb: base register */
1951c6f7 357 { "Rb", XSTORMY16_OPERAND_RB, HW_H_RB, 17, 3,
93fbbb04
GK		 358 { 0, { (1<<MACH_BASE) } } },
359/* Rbj: base register for jump */
360 { "Rbj", XSTORMY16_OPERAND_RBJ, HW_H_RBJ, 11, 1,
361 { 0, { (1<<MACH_BASE) } } },
362/* bcond2: branch condition opcode */
363 { "bcond2", XSTORMY16_OPERAND_BCOND2, HW_H_BRANCHCOND, 4, 4,
364 { 0, { (1<<MACH_BASE) } } },
365/* ws2: word size opcode */
366 { "ws2", XSTORMY16_OPERAND_WS2, HW_H_WORDSIZE, 7, 1,
367 { 0, { (1<<MACH_BASE) } } },
368/* bcond5: branch condition opcode */
369 { "bcond5", XSTORMY16_OPERAND_BCOND5, HW_H_BRANCHCOND, 16, 4,
370 { 0, { (1<<MACH_BASE) } } },
371/* imm2: 2 bit unsigned immediate */
372 { "imm2", XSTORMY16_OPERAND_IMM2, HW_H_UINT, 10, 2,
373 { 0, { (1<<MACH_BASE) } } },
374/* imm3: 3 bit unsigned immediate */
375 { "imm3", XSTORMY16_OPERAND_IMM3, HW_H_UINT, 4, 3,
376 { 0, { (1<<MACH_BASE) } } },
377/* imm3b: 3 bit unsigned immediate for bit tests */
378 { "imm3b", XSTORMY16_OPERAND_IMM3B, HW_H_UINT, 17, 3,
379 { 0, { (1<<MACH_BASE) } } },
380/* imm4: 4 bit unsigned immediate */
381 { "imm4", XSTORMY16_OPERAND_IMM4, HW_H_UINT, 8, 4,
382 { 0, { (1<<MACH_BASE) } } },
383/* imm8: 8 bit unsigned immediate */
384 { "imm8", XSTORMY16_OPERAND_IMM8, HW_H_UINT, 8, 8,
385 { 0, { (1<<MACH_BASE) } } },
386/* imm8small: 8 bit unsigned immediate */
387 { "imm8small", XSTORMY16_OPERAND_IMM8SMALL, HW_H_UINT, 8, 8,
388 { 0, { (1<<MACH_BASE) } } },
389/* imm12: 12 bit signed immediate */
390 { "imm12", XSTORMY16_OPERAND_IMM12, HW_H_SINT, 20, 12,
391 { 0, { (1<<MACH_BASE) } } },
392/* imm16: 16 bit immediate */
393 { "imm16", XSTORMY16_OPERAND_IMM16, HW_H_UINT, 16, 16,
394 { 0|A(SIGN_OPT), { (1<<MACH_BASE) } } },
395/* lmem8: 8 bit unsigned immediate low memory */
396 { "lmem8", XSTORMY16_OPERAND_LMEM8, HW_H_UINT, 8, 8,
397 { 0|A(ABS_ADDR), { (1<<MACH_BASE) } } },
398/* hmem8: 8 bit unsigned immediate high memory */
399 { "hmem8", XSTORMY16_OPERAND_HMEM8, HW_H_UINT, 8, 8,
400 { 0|A(ABS_ADDR), { (1<<MACH_BASE) } } },
401/* rel8-2: 8 bit relative address */
402 { "rel8-2", XSTORMY16_OPERAND_REL8_2, HW_H_UINT, 8, 8,
403 { 0|A(PCREL_ADDR), { (1<<MACH_BASE) } } },
404/* rel8-4: 8 bit relative address */
405 { "rel8-4", XSTORMY16_OPERAND_REL8_4, HW_H_UINT, 8, 8,
406 { 0|A(PCREL_ADDR), { (1<<MACH_BASE) } } },
407/* rel12: 12 bit relative address */
408 { "rel12", XSTORMY16_OPERAND_REL12, HW_H_UINT, 20, 12,
409 { 0|A(PCREL_ADDR), { (1<<MACH_BASE) } } },
410/* rel12a: 12 bit relative address */
411 { "rel12a", XSTORMY16_OPERAND_REL12A, HW_H_UINT, 4, 11,
412 { 0|A(PCREL_ADDR), { (1<<MACH_BASE) } } },
413/* abs24: 24 bit absolute address */
414 { "abs24", XSTORMY16_OPERAND_ABS24, HW_H_UINT, 8, 24,
415 { 0|A(ABS_ADDR)|A(VIRTUAL), { (1<<MACH_BASE) } } },
416/* psw: program status word */
417 { "psw", XSTORMY16_OPERAND_PSW, HW_H_GR, 0, 0,
418 { 0|A(SEM_ONLY), { (1<<MACH_BASE) } } },
419/* Rpsw: N0-N3 of the program status word */
420 { "Rpsw", XSTORMY16_OPERAND_RPSW, HW_H_RPSW, 0, 0,
421 { 0|A(SEM_ONLY), { (1<<MACH_BASE) } } },
422/* sp: stack pointer */
423 { "sp", XSTORMY16_OPERAND_SP, HW_H_GR, 0, 0,
424 { 0|A(SEM_ONLY), { (1<<MACH_BASE) } } },
425/* R0: R0 */
426 { "R0", XSTORMY16_OPERAND_R0, HW_H_GR, 0, 0,
427 { 0|A(SEM_ONLY), { (1<<MACH_BASE) } } },
428/* R1: R1 */
429 { "R1", XSTORMY16_OPERAND_R1, HW_H_GR, 0, 0,
430 { 0|A(SEM_ONLY), { (1<<MACH_BASE) } } },
431/* R2: R2 */
432 { "R2", XSTORMY16_OPERAND_R2, HW_H_GR, 0, 0,
433 { 0|A(SEM_ONLY), { (1<<MACH_BASE) } } },
434/* R8: R8 */
435 { "R8", XSTORMY16_OPERAND_R8, HW_H_GR, 0, 0,
436 { 0|A(SEM_ONLY), { (1<<MACH_BASE) } } },
437 { 0, 0, 0, 0, 0, {0, {0}} }
438};
439
440#undef A
441
442
443/* The instruction table. */
444
445#define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field))
446#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
447#define A(a) (1 << CGEN_INSN_##a)
448#else
449#define A(a) (1 << CGEN_INSN_/**/a)
450#endif
451
452static const CGEN_IBASE xstormy16_cgen_insn_table[MAX_INSNS] =
453{
454 /* Special null first entry.
455 A `num' value of zero is thus invalid.
456 Also, the special `invalid' insn resides here. */
457 { 0, 0, 0, 0, {0, {0}} },
458/* mov$ws2 $lmem8,#$imm16 */
459 {
460 XSTORMY16_INSN_MOVLMEMIMM, "movlmemimm", "mov", 32,
461 { 0, { (1<<MACH_BASE) } }
462 },
463/* mov$ws2 $hmem8,#$imm16 */
464 {
465 XSTORMY16_INSN_MOVHMEMIMM, "movhmemimm", "mov", 32,
466 { 0, { (1<<MACH_BASE) } }
467 },
468/* mov$ws2 $Rm,$lmem8 */
469 {
470 XSTORMY16_INSN_MOVLGRMEM, "movlgrmem", "mov", 16,
471 { 0, { (1<<MACH_BASE) } }
472 },
473/* mov$ws2 $Rm,$hmem8 */
474 {
475 XSTORMY16_INSN_MOVHGRMEM, "movhgrmem", "mov", 16,
476 { 0, { (1<<MACH_BASE) } }
477 },
478/* mov$ws2 $lmem8,$Rm */
479 {
480 XSTORMY16_INSN_MOVLMEMGR, "movlmemgr", "mov", 16,
481 { 0, { (1<<MACH_BASE) } }
482 },
483/* mov$ws2 $hmem8,$Rm */
484 {
485 XSTORMY16_INSN_MOVHMEMGR, "movhmemgr", "mov", 16,
486 { 0, { (1<<MACH_BASE) } }
487 },
488/* mov$ws2 $Rdm,($Rs) */
489 {
490 XSTORMY16_INSN_MOVGRGRI, "movgrgri", "mov", 16,
491 { 0, { (1<<MACH_BASE) } }
492 },
493/* mov$ws2 $Rdm,($Rs++) */
494 {
495 XSTORMY16_INSN_MOVGRGRIPOSTINC, "movgrgripostinc", "mov", 16,
496 { 0, { (1<<MACH_BASE) } }
497 },
498/* mov$ws2 $Rdm,(--$Rs) */
499 {
500 XSTORMY16_INSN_MOVGRGRIPREDEC, "movgrgripredec", "mov", 16,
501 { 0, { (1<<MACH_BASE) } }
502 },
503/* mov$ws2 ($Rs),$Rdm */
504 {
505 XSTORMY16_INSN_MOVGRIGR, "movgrigr", "mov", 16,
506 { 0, { (1<<MACH_BASE) } }
507 },
508/* mov$ws2 ($Rs++),$Rdm */
509 {
510 XSTORMY16_INSN_MOVGRIPOSTINCGR, "movgripostincgr", "mov", 16,
511 { 0, { (1<<MACH_BASE) } }
512 },
513/* mov$ws2 (--$Rs),$Rdm */
514 {
515 XSTORMY16_INSN_MOVGRIPREDECGR, "movgripredecgr", "mov", 16,
516 { 0, { (1<<MACH_BASE) } }
517 },
518/* mov$ws2 $Rdm,($Rs,$imm12) */
519 {
520 XSTORMY16_INSN_MOVGRGRII, "movgrgrii", "mov", 32,
521 { 0, { (1<<MACH_BASE) } }
522 },
523/* mov$ws2 $Rdm,($Rs++,$imm12) */
524 {
525 XSTORMY16_INSN_MOVGRGRIIPOSTINC, "movgrgriipostinc", "mov", 32,
526 { 0, { (1<<MACH_BASE) } }
527 },
528/* mov$ws2 $Rdm,(--$Rs,$imm12) */
529 {
530 XSTORMY16_INSN_MOVGRGRIIPREDEC, "movgrgriipredec", "mov", 32,
531 { 0, { (1<<MACH_BASE) } }
532 },
533/* mov$ws2 ($Rs,$imm12),$Rdm */
534 {
535 XSTORMY16_INSN_MOVGRIIGR, "movgriigr", "mov", 32,
536 { 0, { (1<<MACH_BASE) } }
537 },
538/* mov$ws2 ($Rs++,$imm12),$Rdm */
539 {
540 XSTORMY16_INSN_MOVGRIIPOSTINCGR, "movgriipostincgr", "mov", 32,
541 { 0, { (1<<MACH_BASE) } }
542 },
543/* mov$ws2 (--$Rs,$imm12),$Rdm */
544 {
545 XSTORMY16_INSN_MOVGRIIPREDECGR, "movgriipredecgr", "mov", 32,
546 { 0, { (1<<MACH_BASE) } }
547 },
548/* mov $Rd,$Rs */
549 {
550 XSTORMY16_INSN_MOVGRGR, "movgrgr", "mov", 16,
551 { 0, { (1<<MACH_BASE) } }
552 },
553/* mov.w Rx,#$imm8 */
554 {
555 XSTORMY16_INSN_MOVWIMM8, "movwimm8", "mov.w", 16,
556 { 0, { (1<<MACH_BASE) } }
557 },
558/* mov.w $Rm,#$imm8small */
559 {
560 XSTORMY16_INSN_MOVWGRIMM8, "movwgrimm8", "mov.w", 16,
561 { 0, { (1<<MACH_BASE) } }
562 },
563/* mov.w $Rd,#$imm16 */
564 {
565 XSTORMY16_INSN_MOVWGRIMM16, "movwgrimm16", "mov.w", 32,
566 { 0, { (1<<MACH_BASE) } }
567 },
568/* mov.b $Rd,RxL */
569 {
570 XSTORMY16_INSN_MOVLOWGR, "movlowgr", "mov.b", 16,
571 { 0, { (1<<MACH_BASE) } }
572 },
573/* mov.b $Rd,RxH */
574 {
575 XSTORMY16_INSN_MOVHIGHGR, "movhighgr", "mov.b", 16,
576 { 0, { (1<<MACH_BASE) } }
577 },
578/* movf$ws2 $Rdm,($Rs) */
579 {
580 XSTORMY16_INSN_MOVFGRGRI, "movfgrgri", "movf", 16,
581 { 0, { (1<<MACH_BASE) } }
582 },
583/* movf$ws2 $Rdm,($Rs++) */
584 {
585 XSTORMY16_INSN_MOVFGRGRIPOSTINC, "movfgrgripostinc", "movf", 16,
586 { 0, { (1<<MACH_BASE) } }
587 },
588/* movf$ws2 $Rdm,(--$Rs) */
589 {
590 XSTORMY16_INSN_MOVFGRGRIPREDEC, "movfgrgripredec", "movf", 16,
591 { 0, { (1<<MACH_BASE) } }
592 },
593/* movf$ws2 ($Rs),$Rdm */
594 {
595 XSTORMY16_INSN_MOVFGRIGR, "movfgrigr", "movf", 16,
596 { 0, { (1<<MACH_BASE) } }
597 },
598/* movf$ws2 ($Rs++),$Rdm */
599 {
600 XSTORMY16_INSN_MOVFGRIPOSTINCGR, "movfgripostincgr", "movf", 16,
601 { 0, { (1<<MACH_BASE) } }
602 },
603/* movf$ws2 (--$Rs),$Rdm */
604 {
605 XSTORMY16_INSN_MOVFGRIPREDECGR, "movfgripredecgr", "movf", 16,
606 { 0, { (1<<MACH_BASE) } }
607 },
608/* movf$ws2 $Rdm,($Rb,$Rs,$imm12) */
609 {
610 XSTORMY16_INSN_MOVFGRGRII, "movfgrgrii", "movf", 32,
611 { 0, { (1<<MACH_BASE) } }
612 },
613/* movf$ws2 $Rdm,($Rb,$Rs++,$imm12) */
614 {
615 XSTORMY16_INSN_MOVFGRGRIIPOSTINC, "movfgrgriipostinc", "movf", 32,
616 { 0, { (1<<MACH_BASE) } }
617 },
618/* movf$ws2 $Rdm,($Rb,--$Rs,$imm12) */
619 {
620 XSTORMY16_INSN_MOVFGRGRIIPREDEC, "movfgrgriipredec", "movf", 32,
621 { 0, { (1<<MACH_BASE) } }
622 },
623/* movf$ws2 ($Rb,$Rs,$imm12),$Rdm */
624 {
625 XSTORMY16_INSN_MOVFGRIIGR, "movfgriigr", "movf", 32,
626 { 0, { (1<<MACH_BASE) } }
627 },
628/* movf$ws2 ($Rb,$Rs++,$imm12),$Rdm */
629 {
630 XSTORMY16_INSN_MOVFGRIIPOSTINCGR, "movfgriipostincgr", "movf", 32,
631 { 0, { (1<<MACH_BASE) } }
632 },
633/* movf$ws2 ($Rb,--$Rs,$imm12),$Rdm */
634 {
635 XSTORMY16_INSN_MOVFGRIIPREDECGR, "movfgriipredecgr", "movf", 32,
636 { 0, { (1<<MACH_BASE) } }
637 },
638/* mask $Rd,$Rs */
639 {
640 XSTORMY16_INSN_MASKGRGR, "maskgrgr", "mask", 16,
641 { 0, { (1<<MACH_BASE) } }
642 },
643/* mask $Rd,#$imm16 */
644 {
645 XSTORMY16_INSN_MASKGRIMM16, "maskgrimm16", "mask", 32,
646 { 0, { (1<<MACH_BASE) } }
647 },
648/* push $Rd */
649 {
650 XSTORMY16_INSN_PUSHGR, "pushgr", "push", 16,
651 { 0, { (1<<MACH_BASE) } }
652 },
653/* pop $Rd */
654 {
655 XSTORMY16_INSN_POPGR, "popgr", "pop", 16,
656 { 0, { (1<<MACH_BASE) } }
657 },
658/* swpn $Rd */
659 {
660 XSTORMY16_INSN_SWPN, "swpn", "swpn", 16,
661 { 0, { (1<<MACH_BASE) } }
662 },
663/* swpb $Rd */
664 {
665 XSTORMY16_INSN_SWPB, "swpb", "swpb", 16,
666 { 0, { (1<<MACH_BASE) } }
667 },
668/* swpw $Rd,$Rs */
669 {
670 XSTORMY16_INSN_SWPW, "swpw", "swpw", 16,
671 { 0, { (1<<MACH_BASE) } }
672 },
673/* and $Rd,$Rs */
674 {
675 XSTORMY16_INSN_ANDGRGR, "andgrgr", "and", 16,
676 { 0, { (1<<MACH_BASE) } }
677 },
678/* and Rx,#$imm8 */
679 {
680 XSTORMY16_INSN_ANDIMM8, "andimm8", "and", 16,
681 { 0, { (1<<MACH_BASE) } }
682 },
683/* and $Rd,#$imm16 */
684 {
685 XSTORMY16_INSN_ANDGRIMM16, "andgrimm16", "and", 32,
686 { 0, { (1<<MACH_BASE) } }
687 },
688/* or $Rd,$Rs */
689 {
690 XSTORMY16_INSN_ORGRGR, "orgrgr", "or", 16,
691 { 0, { (1<<MACH_BASE) } }
692 },
693/* or Rx,#$imm8 */
694 {
695 XSTORMY16_INSN_ORIMM8, "orimm8", "or", 16,
696 { 0, { (1<<MACH_BASE) } }
697 },
698/* or $Rd,#$imm16 */
699 {
700 XSTORMY16_INSN_ORGRIMM16, "orgrimm16", "or", 32,
701 { 0, { (1<<MACH_BASE) } }
702 },
703/* xor $Rd,$Rs */
704 {
705 XSTORMY16_INSN_XORGRGR, "xorgrgr", "xor", 16,
706 { 0, { (1<<MACH_BASE) } }
707 },
708/* xor Rx,#$imm8 */
709 {
710 XSTORMY16_INSN_XORIMM8, "xorimm8", "xor", 16,
711 { 0, { (1<<MACH_BASE) } }
712 },
713/* xor $Rd,#$imm16 */
714 {
715 XSTORMY16_INSN_XORGRIMM16, "xorgrimm16", "xor", 32,
716 { 0, { (1<<MACH_BASE) } }
717 },
718/* not $Rd */
719 {
720 XSTORMY16_INSN_NOTGR, "notgr", "not", 16,
721 { 0, { (1<<MACH_BASE) } }
722 },
723/* add $Rd,$Rs */
724 {
725 XSTORMY16_INSN_ADDGRGR, "addgrgr", "add", 16,
726 { 0, { (1<<MACH_BASE) } }
727 },
728/* add $Rd,#$imm4 */
729 {
730 XSTORMY16_INSN_ADDGRIMM4, "addgrimm4", "add", 16,
731 { 0, { (1<<MACH_BASE) } }
732 },
733/* add Rx,#$imm8 */
734 {
735 XSTORMY16_INSN_ADDIMM8, "addimm8", "add", 16,
736 { 0, { (1<<MACH_BASE) } }
737 },
738/* add $Rd,#$imm16 */
739 {
740 XSTORMY16_INSN_ADDGRIMM16, "addgrimm16", "add", 32,
741 { 0, { (1<<MACH_BASE) } }
742 },
743/* adc $Rd,$Rs */
744 {
745 XSTORMY16_INSN_ADCGRGR, "adcgrgr", "adc", 16,
746 { 0, { (1<<MACH_BASE) } }
747 },
748/* adc $Rd,#$imm4 */
749 {
750 XSTORMY16_INSN_ADCGRIMM4, "adcgrimm4", "adc", 16,
751 { 0, { (1<<MACH_BASE) } }
752 },
753/* adc Rx,#$imm8 */
754 {
755 XSTORMY16_INSN_ADCIMM8, "adcimm8", "adc", 16,
756 { 0, { (1<<MACH_BASE) } }
757 },
758/* adc $Rd,#$imm16 */
759 {
760 XSTORMY16_INSN_ADCGRIMM16, "adcgrimm16", "adc", 32,
761 { 0, { (1<<MACH_BASE) } }
762 },
763/* sub $Rd,$Rs */
764 {
765 XSTORMY16_INSN_SUBGRGR, "subgrgr", "sub", 16,
766 { 0, { (1<<MACH_BASE) } }
767 },
768/* sub $Rd,#$imm4 */
769 {
770 XSTORMY16_INSN_SUBGRIMM4, "subgrimm4", "sub", 16,
771 { 0, { (1<<MACH_BASE) } }
772 },
773/* sub Rx,#$imm8 */
774 {
775 XSTORMY16_INSN_SUBIMM8, "subimm8", "sub", 16,
776 { 0, { (1<<MACH_BASE) } }
777 },
778/* sub $Rd,#$imm16 */
779 {
780 XSTORMY16_INSN_SUBGRIMM16, "subgrimm16", "sub", 32,
781 { 0, { (1<<MACH_BASE) } }
782 },
783/* sbc $Rd,$Rs */
784 {
785 XSTORMY16_INSN_SBCGRGR, "sbcgrgr", "sbc", 16,
786 { 0, { (1<<MACH_BASE) } }
787 },
788/* sbc $Rd,#$imm4 */
789 {
790 XSTORMY16_INSN_SBCGRIMM4, "sbcgrimm4", "sbc", 16,
791 { 0, { (1<<MACH_BASE) } }
792 },
793/* sbc Rx,#$imm8 */
794 {
795 XSTORMY16_INSN_SBCGRIMM8, "sbcgrimm8", "sbc", 16,
796 { 0, { (1<<MACH_BASE) } }
797 },
798/* sbc $Rd,#$imm16 */
799 {
800 XSTORMY16_INSN_SBCGRIMM16, "sbcgrimm16", "sbc", 32,
801 { 0, { (1<<MACH_BASE) } }
802 },
803/* inc $Rd,#$imm2 */
804 {
805 XSTORMY16_INSN_INCGRIMM2, "incgrimm2", "inc", 16,
806 { 0, { (1<<MACH_BASE) } }
807 },
808/* dec $Rd,#$imm2 */
809 {
810 XSTORMY16_INSN_DECGRIMM2, "decgrimm2", "dec", 16,
811 { 0, { (1<<MACH_BASE) } }
812 },
813/* rrc $Rd,$Rs */
814 {
815 XSTORMY16_INSN_RRCGRGR, "rrcgrgr", "rrc", 16,
816 { 0, { (1<<MACH_BASE) } }
817 },
818/* rrc $Rd,#$imm4 */
819 {
820 XSTORMY16_INSN_RRCGRIMM4, "rrcgrimm4", "rrc", 16,
821 { 0, { (1<<MACH_BASE) } }
822 },
823/* rlc $Rd,$Rs */
824 {
825 XSTORMY16_INSN_RLCGRGR, "rlcgrgr", "rlc", 16,
826 { 0, { (1<<MACH_BASE) } }
827 },
828/* rlc $Rd,#$imm4 */
829 {
830 XSTORMY16_INSN_RLCGRIMM4, "rlcgrimm4", "rlc", 16,
831 { 0, { (1<<MACH_BASE) } }
832 },
833/* shr $Rd,$Rs */
834 {
835 XSTORMY16_INSN_SHRGRGR, "shrgrgr", "shr", 16,
836 { 0, { (1<<MACH_BASE) } }
837 },
838/* shr $Rd,#$imm4 */
839 {
840 XSTORMY16_INSN_SHRGRIMM, "shrgrimm", "shr", 16,
841 { 0, { (1<<MACH_BASE) } }
842 },
843/* shl $Rd,$Rs */
844 {
845 XSTORMY16_INSN_SHLGRGR, "shlgrgr", "shl", 16,
846 { 0, { (1<<MACH_BASE) } }
847 },
848/* shl $Rd,#$imm4 */
849 {
850 XSTORMY16_INSN_SHLGRIMM, "shlgrimm", "shl", 16,
851 { 0, { (1<<MACH_BASE) } }
852 },
853/* asr $Rd,$Rs */
854 {
855 XSTORMY16_INSN_ASRGRGR, "asrgrgr", "asr", 16,
856 { 0, { (1<<MACH_BASE) } }
857 },
858/* asr $Rd,#$imm4 */
859 {
860 XSTORMY16_INSN_ASRGRIMM, "asrgrimm", "asr", 16,
861 { 0, { (1<<MACH_BASE) } }
862 },
863/* set1 $Rd,#$imm4 */
864 {
865 XSTORMY16_INSN_SET1GRIMM, "set1grimm", "set1", 16,
866 { 0, { (1<<MACH_BASE) } }
867 },
868/* set1 $Rd,$Rs */
869 {
870 XSTORMY16_INSN_SET1GRGR, "set1grgr", "set1", 16,
871 { 0, { (1<<MACH_BASE) } }
872 },
873/* set1 $lmem8,#$imm3 */
874 {
875 XSTORMY16_INSN_SET1LMEMIMM, "set1lmemimm", "set1", 16,
876 { 0, { (1<<MACH_BASE) } }
877 },
878/* set1 $hmem8,#$imm3 */
879 {
880 XSTORMY16_INSN_SET1HMEMIMM, "set1hmemimm", "set1", 16,
881 { 0, { (1<<MACH_BASE) } }
882 },
883/* clr1 $Rd,#$imm4 */
884 {
885 XSTORMY16_INSN_CLR1GRIMM, "clr1grimm", "clr1", 16,
886 { 0, { (1<<MACH_BASE) } }
887 },
888/* clr1 $Rd,$Rs */
889 {
890 XSTORMY16_INSN_CLR1GRGR, "clr1grgr", "clr1", 16,
891 { 0, { (1<<MACH_BASE) } }
892 },
893/* clr1 $lmem8,#$imm3 */
894 {
895 XSTORMY16_INSN_CLR1LMEMIMM, "clr1lmemimm", "clr1", 16,
896 { 0, { (1<<MACH_BASE) } }
897 },
898/* clr1 $hmem8,#$imm3 */
899 {
900 XSTORMY16_INSN_CLR1HMEMIMM, "clr1hmemimm", "clr1", 16,
901 { 0, { (1<<MACH_BASE) } }
902 },
903/* cbw $Rd */
904 {
905 XSTORMY16_INSN_CBWGR, "cbwgr", "cbw", 16,
906 { 0, { (1<<MACH_BASE) } }
907 },
908/* rev $Rd */
909 {
910 XSTORMY16_INSN_REVGR, "revgr", "rev", 16,
911 { 0, { (1<<MACH_BASE) } }
912 },
913/* b$bcond5 $Rd,$Rs,$rel12 */
914 {
915 XSTORMY16_INSN_BCCGRGR, "bccgrgr", "b", 32,
916 { 0|A(COND_CTI), { (1<<MACH_BASE) } }
917 },
918/* b$bcond5 $Rm,#$imm8,$rel12 */
919 {
920 XSTORMY16_INSN_BCCGRIMM8, "bccgrimm8", "b", 32,
921 { 0|A(COND_CTI), { (1<<MACH_BASE) } }
922 },
923/* b$bcond2 Rx,#$imm16,${rel8-4} */
924 {
925 XSTORMY16_INSN_BCCIMM16, "bccimm16", "b", 32,
926 { 0|A(COND_CTI), { (1<<MACH_BASE) } }
927 },
928/* bn $Rd,#$imm4,$rel12 */
929 {
930 XSTORMY16_INSN_BNGRIMM4, "bngrimm4", "bn", 32,
931 { 0|A(COND_CTI), { (1<<MACH_BASE) } }
932 },
933/* bn $Rd,$Rs,$rel12 */
934 {
935 XSTORMY16_INSN_BNGRGR, "bngrgr", "bn", 32,
936 { 0|A(COND_CTI), { (1<<MACH_BASE) } }
937 },
938/* bn $lmem8,#$imm3b,$rel12 */
939 {
940 XSTORMY16_INSN_BNLMEMIMM, "bnlmemimm", "bn", 32,
941 { 0|A(COND_CTI), { (1<<MACH_BASE) } }
942 },
943/* bn $hmem8,#$imm3b,$rel12 */
944 {
945 XSTORMY16_INSN_BNHMEMIMM, "bnhmemimm", "bn", 32,
946 { 0|A(COND_CTI), { (1<<MACH_BASE) } }
947 },
948/* bp $Rd,#$imm4,$rel12 */
949 {
950 XSTORMY16_INSN_BPGRIMM4, "bpgrimm4", "bp", 32,
951 { 0|A(COND_CTI), { (1<<MACH_BASE) } }
952 },
953/* bp $Rd,$Rs,$rel12 */
954 {
955 XSTORMY16_INSN_BPGRGR, "bpgrgr", "bp", 32,
956 { 0|A(COND_CTI), { (1<<MACH_BASE) } }
957 },
958/* bp $lmem8,#$imm3b,$rel12 */
959 {
960 XSTORMY16_INSN_BPLMEMIMM, "bplmemimm", "bp", 32,
961 { 0|A(COND_CTI), { (1<<MACH_BASE) } }
962 },
963/* bp $hmem8,#$imm3b,$rel12 */
964 {
965 XSTORMY16_INSN_BPHMEMIMM, "bphmemimm", "bp", 32,
966 { 0|A(COND_CTI), { (1<<MACH_BASE) } }
967 },
968/* b$bcond2 ${rel8-2} */
969 {
970 XSTORMY16_INSN_BCC, "bcc", "b", 16,
971 { 0|A(COND_CTI), { (1<<MACH_BASE) } }
972 },
973/* br $Rd */
974 {
975 XSTORMY16_INSN_BGR, "bgr", "br", 16,
976 { 0|A(UNCOND_CTI), { (1<<MACH_BASE) } }
977 },
978/* br $rel12a */
979 {
980 XSTORMY16_INSN_BR, "br", "br", 16,
981 { 0|A(UNCOND_CTI), { (1<<MACH_BASE) } }
982 },
983/* jmp $Rbj,$Rd */
984 {
985 XSTORMY16_INSN_JMP, "jmp", "jmp", 16,
986 { 0|A(UNCOND_CTI), { (1<<MACH_BASE) } }
987 },
988/* jmpf $abs24 */
989 {
990 XSTORMY16_INSN_JMPF, "jmpf", "jmpf", 32,
991 { 0|A(UNCOND_CTI), { (1<<MACH_BASE) } }
992 },
993/* callr $Rd */
994 {
995 XSTORMY16_INSN_CALLRGR, "callrgr", "callr", 16,
996 { 0|A(UNCOND_CTI), { (1<<MACH_BASE) } }
997 },
998/* callr $rel12a */
999 {
1000 XSTORMY16_INSN_CALLRIMM, "callrimm", "callr", 16,
1001 { 0|A(UNCOND_CTI), { (1<<MACH_BASE) } }
1002 },
1003/* call $Rbj,$Rd */
1004 {
1005 XSTORMY16_INSN_CALLGR, "callgr", "call", 16,
1006 { 0|A(UNCOND_CTI), { (1<<MACH_BASE) } }
1007 },
1008/* callf $abs24 */
1009 {
1010 XSTORMY16_INSN_CALLFIMM, "callfimm", "callf", 32,
1011 { 0|A(UNCOND_CTI), { (1<<MACH_BASE) } }
1012 },
1013/* icallr $Rd */
1014 {
1015 XSTORMY16_INSN_ICALLRGR, "icallrgr", "icallr", 16,
1016 { 0|A(UNCOND_CTI), { (1<<MACH_BASE) } }
1017 },
1018/* icall $Rbj,$Rd */
1019 {
1020 XSTORMY16_INSN_ICALLGR, "icallgr", "icall", 16,
1021 { 0|A(UNCOND_CTI), { (1<<MACH_BASE) } }
1022 },
1023/* icallf $abs24 */
1024 {
1025 XSTORMY16_INSN_ICALLFIMM, "icallfimm", "icallf", 32,
1026 { 0|A(UNCOND_CTI), { (1<<MACH_BASE) } }
1027 },
1028/* iret */
1029 {
1030 XSTORMY16_INSN_IRET, "iret", "iret", 16,
1031 { 0|A(UNCOND_CTI), { (1<<MACH_BASE) } }
1032 },
1033/* ret */
1034 {
1035 XSTORMY16_INSN_RET, "ret", "ret", 16,
1036 { 0|A(UNCOND_CTI), { (1<<MACH_BASE) } }
1037 },
1038/* mul */
1039 {
1040 XSTORMY16_INSN_MUL, "mul", "mul", 16,
1041 { 0, { (1<<MACH_BASE) } }
1042 },
1043/* div */
1044 {
1045 XSTORMY16_INSN_DIV, "div", "div", 16,
1046 { 0, { (1<<MACH_BASE) } }
1047 },
1048/* nop */
1049 {
1050 XSTORMY16_INSN_NOP, "nop", "nop", 16,
1051 { 0, { (1<<MACH_BASE) } }
1052 },
1053/* halt */
1054 {
1055 XSTORMY16_INSN_HALT, "halt", "halt", 16,
1056 { 0, { (1<<MACH_BASE) } }
1057 },
1058/* hold */
1059 {
1060 XSTORMY16_INSN_HOLD, "hold", "hold", 16,
1061 { 0, { (1<<MACH_BASE) } }
1062 },
1951c6f7
MG		 1063/* holdx */
1064 {
1065 XSTORMY16_INSN_HOLDX, "holdx", "holdx", 16,
1066 { 0, { (1<<MACH_BASE) } }
1067 },
93fbbb04
GK		 1068/* brk */
1069 {
1070 XSTORMY16_INSN_BRK, "brk", "brk", 16,
1071 { 0, { (1<<MACH_BASE) } }
1072 },
1073/* --unused-- */
1074 {
1075 XSTORMY16_INSN_SYSCALL, "syscall", "--unused--", 16,
1076 { 0, { (1<<MACH_BASE) } }
1077 },
1078};
1079
1080#undef OP
1081#undef A
1082
1083/* Initialize anything needed to be done once, before any cpu_open call. */
1084static void init_tables PARAMS ((void));
1085
1086static void
1087init_tables ()
1088{
1089}
1090
1091static const CGEN_MACH * lookup_mach_via_bfd_name
1092 PARAMS ((const CGEN_MACH *, const char *));
1093static void build_hw_table PARAMS ((CGEN_CPU_TABLE *));
1094static void build_ifield_table PARAMS ((CGEN_CPU_TABLE *));
1095static void build_operand_table PARAMS ((CGEN_CPU_TABLE *));
1096static void build_insn_table PARAMS ((CGEN_CPU_TABLE *));
1097static void xstormy16_cgen_rebuild_tables PARAMS ((CGEN_CPU_TABLE *));
1098
1099/* Subroutine of xstormy16_cgen_cpu_open to look up a mach via its bfd name. */
1100
1101static const CGEN_MACH *
1102lookup_mach_via_bfd_name (table, name)
1103 const CGEN_MACH *table;
1104 const char *name;
1105{
1106 while (table->name)
1107 {
1108 if (strcmp (name, table->bfd_name) == 0)
1109 return table;
1110 ++table;
1111 }
1112 abort ();
1113}
1114
1115/* Subroutine of xstormy16_cgen_cpu_open to build the hardware table. */
1116
1117static void
1118build_hw_table (cd)
1119 CGEN_CPU_TABLE *cd;
1120{
1121 int i;
1122 int machs = cd->machs;
1123 const CGEN_HW_ENTRY *init = & xstormy16_cgen_hw_table[0];
1124 /* MAX_HW is only an upper bound on the number of selected entries.
1125 However each entry is indexed by it's enum so there can be holes in
1126 the table. */
1127 const CGEN_HW_ENTRY **selected =
1128 (const CGEN_HW_ENTRY **) xmalloc (MAX_HW * sizeof (CGEN_HW_ENTRY *));
1129
1130 cd->hw_table.init_entries = init;
1131 cd->hw_table.entry_size = sizeof (CGEN_HW_ENTRY);
1132 memset (selected, 0, MAX_HW * sizeof (CGEN_HW_ENTRY *));
1133 /* ??? For now we just use machs to determine which ones we want. */
1134 for (i = 0; init[i].name != NULL; ++i)
1135 if (CGEN_HW_ATTR_VALUE (&init[i], CGEN_HW_MACH)
1136 & machs)
1137 selected[init[i].type] = &init[i];
1138 cd->hw_table.entries = selected;
1139 cd->hw_table.num_entries = MAX_HW;
1140}
1141
1142/* Subroutine of xstormy16_cgen_cpu_open to build the hardware table. */
1143
1144static void
1145build_ifield_table (cd)
1146 CGEN_CPU_TABLE *cd;
1147{
1148 cd->ifld_table = & xstormy16_cgen_ifld_table[0];
1149}
1150
1151/* Subroutine of xstormy16_cgen_cpu_open to build the hardware table. */
1152
1153static void
1154build_operand_table (cd)
1155 CGEN_CPU_TABLE *cd;
1156{
1157 int i;
1158 int machs = cd->machs;
1159 const CGEN_OPERAND *init = & xstormy16_cgen_operand_table[0];
1160 /* MAX_OPERANDS is only an upper bound on the number of selected entries.
1161 However each entry is indexed by it's enum so there can be holes in
1162 the table. */
1163 const CGEN_OPERAND **selected =
1164 (const CGEN_OPERAND **) xmalloc (MAX_OPERANDS * sizeof (CGEN_OPERAND *));
1165
1166 cd->operand_table.init_entries = init;
1167 cd->operand_table.entry_size = sizeof (CGEN_OPERAND);
1168 memset (selected, 0, MAX_OPERANDS * sizeof (CGEN_OPERAND *));
1169 /* ??? For now we just use mach to determine which ones we want. */
1170 for (i = 0; init[i].name != NULL; ++i)
1171 if (CGEN_OPERAND_ATTR_VALUE (&init[i], CGEN_OPERAND_MACH)
1172 & machs)
1173 selected[init[i].type] = &init[i];
1174 cd->operand_table.entries = selected;
1175 cd->operand_table.num_entries = MAX_OPERANDS;
1176}
1177
1178/* Subroutine of xstormy16_cgen_cpu_open to build the hardware table.
1179 ??? This could leave out insns not supported by the specified mach/isa,
1180 but that would cause errors like "foo only supported by bar" to become
1181 "unknown insn", so for now we include all insns and require the app to
1182 do the checking later.
1183 ??? On the other hand, parsing of such insns may require their hardware or
1184 operand elements to be in the table [which they mightn't be]. */
1185
1186static void
1187build_insn_table (cd)
1188 CGEN_CPU_TABLE *cd;
1189{
1190 int i;
1191 const CGEN_IBASE *ib = & xstormy16_cgen_insn_table[0];
1192 CGEN_INSN *insns = (CGEN_INSN *) xmalloc (MAX_INSNS * sizeof (CGEN_INSN));
1193
1194 memset (insns, 0, MAX_INSNS * sizeof (CGEN_INSN));
1195 for (i = 0; i < MAX_INSNS; ++i)
1196 insns[i].base = &ib[i];
1197 cd->insn_table.init_entries = insns;
1198 cd->insn_table.entry_size = sizeof (CGEN_IBASE);
1199 cd->insn_table.num_init_entries = MAX_INSNS;
1200}
1201
1202/* Subroutine of xstormy16_cgen_cpu_open to rebuild the tables. */
1203
1204static void
1205xstormy16_cgen_rebuild_tables (cd)
1206 CGEN_CPU_TABLE *cd;
1207{
1208 int i;
1209 unsigned int isas = cd->isas;
1210 unsigned int machs = cd->machs;
1211
1212 cd->int_insn_p = CGEN_INT_INSN_P;
1213
1214 /* Data derived from the isa spec. */
1215#define UNSET (CGEN_SIZE_UNKNOWN + 1)
1216 cd->default_insn_bitsize = UNSET;
1217 cd->base_insn_bitsize = UNSET;
1218 cd->min_insn_bitsize = 65535; /* some ridiculously big number */
1219 cd->max_insn_bitsize = 0;
1220 for (i = 0; i < MAX_ISAS; ++i)
1221 if (((1 << i) & isas) != 0)
1222 {
1223 const CGEN_ISA *isa = & xstormy16_cgen_isa_table[i];
1224
1951c6f7
MG		 1225 /* Default insn sizes of all selected isas must be equal or we set
1226 the result to 0, meaning "unknown". */
93fbbb04
GK		 1227 if (cd->default_insn_bitsize == UNSET)
1228 cd->default_insn_bitsize = isa->default_insn_bitsize;
1229 else if (isa->default_insn_bitsize == cd->default_insn_bitsize)
1230 ; /* this is ok */
1231 else
1232 cd->default_insn_bitsize = CGEN_SIZE_UNKNOWN;
1233
1951c6f7
MG		 1234 /* Base insn sizes of all selected isas must be equal or we set
1235 the result to 0, meaning "unknown". */
93fbbb04
GK		 1236 if (cd->base_insn_bitsize == UNSET)
1237 cd->base_insn_bitsize = isa->base_insn_bitsize;
1238 else if (isa->base_insn_bitsize == cd->base_insn_bitsize)
1239 ; /* this is ok */
1240 else
1241 cd->base_insn_bitsize = CGEN_SIZE_UNKNOWN;
1242
1243 /* Set min,max insn sizes. */
1244 if (isa->min_insn_bitsize < cd->min_insn_bitsize)
1245 cd->min_insn_bitsize = isa->min_insn_bitsize;
1246 if (isa->max_insn_bitsize > cd->max_insn_bitsize)
1247 cd->max_insn_bitsize = isa->max_insn_bitsize;
1248 }
1249
1250 /* Data derived from the mach spec. */
1251 for (i = 0; i < MAX_MACHS; ++i)
1252 if (((1 << i) & machs) != 0)
1253 {
1254 const CGEN_MACH *mach = & xstormy16_cgen_mach_table[i];
1255
1256 if (mach->insn_chunk_bitsize != 0)
1257 {
1258 if (cd->insn_chunk_bitsize != 0 && cd->insn_chunk_bitsize != mach->insn_chunk_bitsize)
1259 {
1260 fprintf (stderr, "xstormy16_cgen_rebuild_tables: conflicting insn-chunk-bitsize values: `%d' vs. `%d'\n",
1261 cd->insn_chunk_bitsize, mach->insn_chunk_bitsize);
1262 abort ();
1263 }
1264
1265 cd->insn_chunk_bitsize = mach->insn_chunk_bitsize;
1266 }
1267 }
1268
1269 /* Determine which hw elements are used by MACH. */
1270 build_hw_table (cd);
1271
1272 /* Build the ifield table. */
1273 build_ifield_table (cd);
1274
1275 /* Determine which operands are used by MACH/ISA. */
1276 build_operand_table (cd);
1277
1278 /* Build the instruction table. */
1279 build_insn_table (cd);
1280}
1281
1282/* Initialize a cpu table and return a descriptor.
1283 It's much like opening a file, and must be the first function called.
1284 The arguments are a set of (type/value) pairs, terminated with
1285 CGEN_CPU_OPEN_END.
1286
1287 Currently supported values:
1288 CGEN_CPU_OPEN_ISAS: bitmap of values in enum isa_attr
1289 CGEN_CPU_OPEN_MACHS: bitmap of values in enum mach_attr
1290 CGEN_CPU_OPEN_BFDMACH: specify 1 mach using bfd name
1291 CGEN_CPU_OPEN_ENDIAN: specify endian choice
1292 CGEN_CPU_OPEN_END: terminates arguments
1293
1294 ??? Simultaneous multiple isas might not make sense, but it's not (yet)
1295 precluded.
1296
1297 ??? We only support ISO C stdargs here, not K&R.
1298 Laziness, plus experiment to see if anything requires K&R - eventually
1299 K&R will no longer be supported - e.g. GDB is currently trying this. */
1300
1301CGEN_CPU_DESC
1302xstormy16_cgen_cpu_open (enum cgen_cpu_open_arg arg_type, ...)
1303{
1304 CGEN_CPU_TABLE *cd = (CGEN_CPU_TABLE *) xmalloc (sizeof (CGEN_CPU_TABLE));
1305 static int init_p;
1306 unsigned int isas = 0; /* 0 = "unspecified" */
1307 unsigned int machs = 0; /* 0 = "unspecified" */
1308 enum cgen_endian endian = CGEN_ENDIAN_UNKNOWN;
1309 va_list ap;
1310
1311 if (! init_p)
1312 {
1313 init_tables ();
1314 init_p = 1;
1315 }
1316
1317 memset (cd, 0, sizeof (*cd));
1318
1319 va_start (ap, arg_type);
1320 while (arg_type != CGEN_CPU_OPEN_END)
1321 {
1322 switch (arg_type)
1323 {
1324 case CGEN_CPU_OPEN_ISAS :
1325 isas = va_arg (ap, unsigned int);
1326 break;
1327 case CGEN_CPU_OPEN_MACHS :
1328 machs = va_arg (ap, unsigned int);
1329 break;
1330 case CGEN_CPU_OPEN_BFDMACH :
1331 {
1332 const char *name = va_arg (ap, const char *);
1333 const CGEN_MACH *mach =
1334 lookup_mach_via_bfd_name (xstormy16_cgen_mach_table, name);
1335
1336 machs |= 1 << mach->num;
1337 break;
1338 }
1339 case CGEN_CPU_OPEN_ENDIAN :
1340 endian = va_arg (ap, enum cgen_endian);
1341 break;
1342 default :
1343 fprintf (stderr, "xstormy16_cgen_cpu_open: unsupported argument `%d'\n",
1344 arg_type);
1345 abort (); /* ??? return NULL? */
1346 }
1347 arg_type = va_arg (ap, enum cgen_cpu_open_arg);
1348 }
1349 va_end (ap);
1350
1351 /* mach unspecified means "all" */
1352 if (machs == 0)
1353 machs = (1 << MAX_MACHS) - 1;
1354 /* base mach is always selected */
1355 machs |= 1;
1356 /* isa unspecified means "all" */
1357 if (isas == 0)
1358 isas = (1 << MAX_ISAS) - 1;
1359 if (endian == CGEN_ENDIAN_UNKNOWN)
1360 {
1361 /* ??? If target has only one, could have a default. */
1362 fprintf (stderr, "xstormy16_cgen_cpu_open: no endianness specified\n");
1363 abort ();
1364 }
1365
1366 cd->isas = isas;
1367 cd->machs = machs;
1368 cd->endian = endian;
1369 /* FIXME: for the sparc case we can determine insn-endianness statically.
1370 The worry here is where both data and insn endian can be independently
1371 chosen, in which case this function will need another argument.
1372 Actually, will want to allow for more arguments in the future anyway. */
1373 cd->insn_endian = endian;
1374
1375 /* Table (re)builder. */
1376 cd->rebuild_tables = xstormy16_cgen_rebuild_tables;
1377 xstormy16_cgen_rebuild_tables (cd);
1378
1379 /* Default to not allowing signed overflow. */
1380 cd->signed_overflow_ok_p = 0;
1381
1382 return (CGEN_CPU_DESC) cd;
1383}
1384
1385/* Cover fn to xstormy16_cgen_cpu_open to handle the simple case of 1 isa, 1 mach.
1386 MACH_NAME is the bfd name of the mach. */
1387
1388CGEN_CPU_DESC
1389xstormy16_cgen_cpu_open_1 (mach_name, endian)
1390 const char *mach_name;
1391 enum cgen_endian endian;
1392{
1393 return xstormy16_cgen_cpu_open (CGEN_CPU_OPEN_BFDMACH, mach_name,
1394 CGEN_CPU_OPEN_ENDIAN, endian,
1395 CGEN_CPU_OPEN_END);
1396}
1397
1398/* Close a cpu table.
1399 ??? This can live in a machine independent file, but there's currently
1400 no place to put this file (there's no libcgen). libopcodes is the wrong
1401 place as some simulator ports use this but they don't use libopcodes. */
1402
1403void
1404xstormy16_cgen_cpu_close (cd)
1405 CGEN_CPU_DESC cd;
1406{
1407 if (cd->insn_table.init_entries)
1408 free ((CGEN_INSN *) cd->insn_table.init_entries);
1409 if (cd->hw_table.entries)
1410 free ((CGEN_HW_ENTRY *) cd->hw_table.entries);
1411 free (cd);
1412}
1413
GDB Binutils - Deliverables
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