opcodes/ChangeLog

   1 2019-12-19  Dr N.W. Filardo  <nwf20@cam.ac.uk>
   2
   3         PR 25277
   4         * microblaze-opcm.h (enum microblaze_instr): Prefix fadd, fmul and
   5         fdiv with "mbi_".
   6         * microblaze-opc.h (opcodes): Adjust to suit.
   7
   8 2019-12-18  Alan Modra  <amodra@gmail.com>
   9
  10         * alpha-opc.c (OP): Avoid signed overflow.
  11         * arm-dis.c (print_insn): Likewise.
  12         * mcore-dis.c (print_insn_mcore): Likewise.
  13         * pj-dis.c (get_int): Likewise.
  14         * ppc-opc.c (EBD15, EBD15BI): Likewise.
  15         * score7-dis.c (s7_print_insn): Likewise.
  16         * tic30-dis.c (print_insn_tic30): Likewise.
  17         * v850-opc.c (insert_SELID): Likewise.
  18         * vax-dis.c (print_insn_vax): Likewise.
  19         * arc-ext.c (create_map): Likewise.
  20         (struct ExtAuxRegister): Make "address" field unsigned int.
  21         (arcExtMap_auxRegName): Pass unsigned address.
  22         (dump_ARC_extmap): Adjust.
  23         * arc-ext.h (arcExtMap_auxRegName): Update prototype.
  24
  25 2019-12-17  Alan Modra  <amodra@gmail.com>
  26
  27         * visium-dis.c (print_insn_visium): Avoid signed overflow.
  28
  29 2019-12-17  Alan Modra  <amodra@gmail.com>
  30
  31         * aarch64-opc.c (value_fit_signed_field_p): Avoid signed overflow.
  32         (value_fit_unsigned_field_p): Likewise.
  33         (aarch64_wide_constant_p): Likewise.
  34         (operand_general_constraint_met_p): Likewise.
  35         * aarch64-opc.h (aarch64_wide_constant_p): Update prototype.
  36
  37 2019-12-17  Alan Modra  <amodra@gmail.com>
  38
  39         * nds32-dis.c (nds32_mask_opcode): Avoid signed overflow.
  40         (print_insn_nds32): Use uint64_t for "given" and "given1".
  41
  42 2019-12-17  Alan Modra  <amodra@gmail.com>
  43
  44         * tic80-dis.c: Delete file.
  45         * tic80-opc.c: Delete file.
  46         * disassemble.c: Remove tic80 support.
  47         * disassemble.h: Likewise.
  48         * Makefile.am: Likewise.
  49         * configure.ac: Likewise.
  50         * Makefile.in: Regenerate.
  51         * configure: Regenerate.
  52         * po/POTFILES.in: Regenerate.
  53
  54 2019-12-17  Alan Modra  <amodra@gmail.com>
  55
  56         * bpf-ibld.c: Regenerate.
  57
  58 2019-12-16  Alan Modra  <amodra@gmail.com>
  59
  60         * aarch64-dis.c (sign_extend): Return uint64_t.  Rewrite without
  61         conditional.
  62         (aarch64_ext_imm): Avoid signed overflow.
  63
  64 2019-12-16  Alan Modra  <amodra@gmail.com>
  65
  66         * microblaze-dis.c (read_insn_microblaze): Avoid signed overflow.
  67
  68 2019-12-16  Alan Modra  <amodra@gmail.com>
  69
  70         * nios2-dis.c (nios2_print_insn_arg): Avoid signed overflow
  71
  72 2019-12-16  Alan Modra  <amodra@gmail.com>
  73
  74         * xstormy16-ibld.c: Regenerate.
  75
  76 2019-12-16  Alan Modra  <amodra@gmail.com>
  77
  78         * score-dis.c (print_insn_score16): Move rpush/rpop imm field
  79         value adjustment so that it doesn't affect reg field too.
  80
  81 2019-12-16  Alan Modra  <amodra@gmail.com>
  82
  83         * crx-dis.c (EXTRACT, SBM): Avoid signed overflow.
  84         (get_number_of_operands, getargtype, getbits, getregname),
  85         (getcopregname, getprocregname, gettrapstring, getcinvstring),
  86         (getregliststring, get_word_at_PC, get_words_at_PC, build_mask),
  87         (powerof2, match_opcode, make_instruction, print_arguments),
  88         (print_arg): Delete forward declarations, moving static to..
  89         (getregname, getcopregname, getregliststring): ..these definitions.
  90         (build_mask): Return unsigned int mask.
  91         (match_opcode): Use unsigned int vars.
  92
  93 2019-12-16  Alan Modra  <amodra@gmail.com>
  94
  95         * bfin-dis.c (fmtconst, fmtconst_val): Avoid signed overflow.
  96
  97 2019-12-16  Alan Modra  <amodra@gmail.com>
  98
  99         * nds32-dis.c (print_insn16, print_insn32): Remove forward decls.
 100         (struct objdump_disasm_info): Delete.
 101         (nds32_parse_audio_ext, nds32_parse_opcode): Cast result of
 102         N32_IMMS to unsigned before shifting left.
 103
 104 2019-12-16  Alan Modra  <amodra@gmail.com>
 105
 106         * moxie-dis.c (INST2OFFSET): Don't left shift a signed value.
 107         (print_insn_moxie): Remove unnecessary cast.
 108
 109 2019-12-12  Alan Modra  <amodra@gmail.com>
 110
 111         * csky-dis.c (csky_chars_to_number): Remove abort and unnecessary
 112         mask.
 113
 114 2019-12-11  Alan Modra  <amodra@gmail.com>
 115
 116         * arc-dis.c (BITS): Don't truncate high bits with shifts.
 117         * nios2-dis.c (nios2_print_insn_arg): Don't sign extend with shifts.
 118         * tic54x-dis.c (print_instruction): Likewise.
 119         * tilegx-opc.c (parse_insn_tilegx): Likewise.
 120         * tilepro-opc.c (parse_insn_tilepro): Likewise.
 121         * visium-dis.c (disassem_class0): Likewise.
 122         * pdp11-dis.c (sign_extend): Likewise.
 123         (SIGN_BITS): Delete.
 124         * epiphany-ibld.c: Regenerate.
 125         * lm32-ibld.c: Regenerate.
 126         * m32c-ibld.c: Regenerate.
 127
 128 2019-12-11  Alan Modra  <amodra@gmail.com>
 129
 130         * ns32k-dis.c (sign_extend): Correct last patch.
 131
 132 2019-12-11  Alan Modra  <amodra@gmail.com>
 133
 134         * vax-dis.c (NEXTLONG): Avoid signed overflow.
 135
 136 2019-12-11  Alan Modra  <amodra@gmail.com>
 137
 138         * v850-dis.c (get_operand_value): Use unsigned arithmetic.  Don't
 139         sign extend using shifts.
 140
 141 2019-12-11  Alan Modra  <amodra@gmail.com>
 142
 143         * tic6x-dis.c (tic6x_extract_32): Avoid signed overflow.
 144
 145 2019-12-11  Alan Modra  <amodra@gmail.com>
 146
 147         * tic4x-dis.c (tic4x_print_register): Formatting.  Don't segfault
 148         on NULL registertable entry.
 149         (tic4x_hash_opcode): Use unsigned arithmetic.
 150
 151 2019-12-11  Alan Modra  <amodra@gmail.com>
 152
 153         * s12z-opc.c (z_decode_signed_value): Avoid signed overflow.
 154
 155 2019-12-11  Alan Modra  <amodra@gmail.com>
 156
 157         * ns32k-dis.c (bit_extract): Use unsigned arithmetic.
 158         (bit_extract_simple, sign_extend): Likewise.
 159
 160 2019-12-11  Alan Modra  <amodra@gmail.com>
 161
 162         * nios2-dis.c (nios2_print_insn_arg): Use 1u << 31.
 163
 164 2019-12-11  Alan Modra  <amodra@gmail.com>
 165
 166         * moxie-dis.c (INST2OFFSET): Don't sign extend using shifts.
 167
 168 2019-12-11  Alan Modra  <amodra@gmail.com>
 169
 170         * m68k-dis.c (COERCE32): Cast value first.
 171         (NEXTLONG, NEXTULONG): Avoid signed overflow.
 172
 173 2019-12-11  Alan Modra  <amodra@gmail.com>
 174
 175         * h8300-dis.c (extract_immediate): Avoid signed overflow.
 176         (bfd_h8_disassemble): Likewise.
 177
 178 2019-12-11  Alan Modra  <amodra@gmail.com>
 179
 180         * d30v-dis.c (print_insn): Make opind unsigned.  Don't access
 181         past end of operands array.
 182
 183 2019-12-11  Alan Modra  <amodra@gmail.com>
 184
 185         * csky-dis.c (csky_chars_to_number): Rewrite.  Avoid signed
 186         overflow when collecting bytes of a number.
 187
 188 2019-12-11  Alan Modra  <amodra@gmail.com>
 189
 190         * cris-dis.c (print_with_operands): Avoid signed integer
 191         overflow when collecting bytes of a 32-bit integer.
 192
 193 2019-12-11  Alan Modra  <amodra@gmail.com>
 194
 195         * cr16-dis.c (EXTRACT, SBM): Rewrite.
 196         (cr16_match_opcode): Delete duplicate bcond test.
 197
 198 2019-12-11  Alan Modra  <amodra@gmail.com>
 199
 200         * bfin-dis.c (HOST_LONG_WORD_SIZE, XFIELD): Delete.
 201         (SIGNBIT): New.
 202         (MASKBITS, SIGNEXTEND): Rewrite.
 203         (fmtconst): Don't use ? expression now that SIGNEXTEND uses
 204         unsigned arithmetic, instead assign result of SIGNEXTEND back
 205         to x.
 206         (fmtconst_val): Use 1u in shift expression.
 207
 208 2019-12-11  Alan Modra  <amodra@gmail.com>
 209
 210         * arc-dis.c (find_format_from_table): Use ull constant when
 211         shifting by up to 32.
 212
 213 2019-12-11  Alan Modra  <amodra@gmail.com>
 214
 215         PR 25270
 216         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Return
 217         false when field is zero for sve_size_tsz_bhs.
 218
 219 2019-12-11  Alan Modra  <amodra@gmail.com>
 220
 221         * epiphany-ibld.c: Regenerate.
 222
 223 2019-12-10  Alan Modra  <amodra@gmail.com>
 224
 225         PR 24960
 226         * disassemble.c (disassemble_free_target): New function.
 227
 228 2019-12-10  Alan Modra  <amodra@gmail.com>
 229
 230         * cgen-dis.in (print_insn_@arch@): Replace insn_sets with private_data.
 231         * disassemble.c (disassemble_init_for_target): Likewise.
 232         * bpf-dis.c: Regenerate.
 233         * epiphany-dis.c: Regenerate.
 234         * fr30-dis.c: Regenerate.
 235         * frv-dis.c: Regenerate.
 236         * ip2k-dis.c: Regenerate.
 237         * iq2000-dis.c: Regenerate.
 238         * lm32-dis.c: Regenerate.
 239         * m32c-dis.c: Regenerate.
 240         * m32r-dis.c: Regenerate.
 241         * mep-dis.c: Regenerate.
 242         * mt-dis.c: Regenerate.
 243         * or1k-dis.c: Regenerate.
 244         * xc16x-dis.c: Regenerate.
 245         * xstormy16-dis.c: Regenerate.
 246
 247 2019-12-10  Alan Modra  <amodra@gmail.com>
 248
 249         * ppc-dis.c (private): Delete variable.
 250         (get_powerpc_dialect): Don't segfault on NULL info->private_data.
 251         (powerpc_init_dialect): Don't use global private.
 252
 253 2019-12-10  Alan Modra  <amodra@gmail.com>
 254
 255         * s12z-opc.c: Formatting.
 256
 257 2019-12-08  Alan Modra  <amodra@gmail.com>
 258
 259         * s12z-opc.c (exg_sex_discrim): Don't leak memory on invalid
 260         registers.
 261
 262 2019-12-05  Jan Beulich  <jbeulich@suse.com>
 263
 264         * aarch64-tbl.h (aarch64_feature_crypto,
 265         aarch64_feature_crypto_v8_2, CRYPTO, CRYPTO_V8_2, CRYP_INSN,
 266         CRYPTO_V8_2_INSN): Delete.
 267
 268 2019-12-05  Alan Modra  <amodra@gmail.com>
 269
 270         PR 25249
 271         * microblaze-dis.c (NUM_STRBUFS, STRBUF_SIZE): Define.
 272         (struct string_buf): New.
 273         (strbuf): New function.
 274         (get_field): Use strbuf rather than strdup of local temp.
 275         (get_field_imm, get_field_imm5, get_field_imm5_mbar): Likewise.
 276         (get_field_rfsl, get_field_imm15): Likewise.
 277         (get_field_rd, get_field_r1, get_field_r2): Update macros.
 278         (get_field_special): Likewise.  Don't strcpy spr.  Formatting.
 279         (print_insn_microblaze): Formatting.  Init and pass string_buf to
 280         get_field functions.
 281
 282 2019-12-04  Jan Beulich  <jbeulich@suse.com>
 283
 284         * i386-opc.tbl (lfs, lgs, lss): Drop No_qSuf.
 285         * i386-tbl.h: Re-generate.
 286
 287 2019-12-04  Jan Beulich  <jbeulich@suse.com>
 288
 289         * i386-dis.c (mod_table): Use Ev instead of Em for movdiri.
 290
 291 2019-12-04  Jan Beulich  <jbeulich@suse.com>
 292
 293         * i386-opc.tbl (push, pop): Drop DefaultSize from GPR-only
 294         forms.
 295         (xbegin): Drop DefaultSize.
 296         * i386-tbl.h: Re-generate.
 297
 298 2019-11-22  Mihail Ionescu  <mihail.ionescu@arm.com>
 299
 300         * opcodes/arm-dis.c (arm_opcodes, thumb32_opcodes):
 301         Change the coproc CRC conditions to use the extension
 302         feature set, second word, base on ARM_EXT2_CRC.
 303
 304 2019-11-14  Jan Beulich  <jbeulich@suse.com>
 305
 306         * i386-opc.tbl (syscall, sysret): Drop Cpu64 forms.
 307         * i386-tbl.h: Re-generate.
 308
 309 2019-11-14  Jan Beulich  <jbeulich@suse.com>
 310
 311         * i386-gen.c (opcode_modifiers): Remove JumpDword, JumpByte,
 312         JumpInterSegment, and JumpAbsolute entries.
 313         * i386-opc.h (JUMP, JUMP_DWORD, JUMP_BYTE, JUMP_INTERSEGMENT,
 314         JUMP_ABSOLUTE): Define.
 315         (struct i386_opcode_modifier): Extend jump field to 3 bits.
 316         Remove jumpdword, jumpbyte, jumpintersegment, and jumpabsolute
 317         fields.
 318         * i386-opc.tbl (JumpByte, JumpDword, JumpAbsolute,
 319         JumpInterSegment): Define.
 320         * i386-tbl.h: Re-generate.
 321
 322 2019-11-14  Jan Beulich  <jbeulich@suse.com>
 323
 324         * i386-gen.c (operand_type_init): Remove
 325         OPERAND_TYPE_JUMPABSOLUTE entry.
 326         (opcode_modifiers): Add JumpAbsolute entry.
 327         (operand_types): Remove JumpAbsolute entry.
 328         * i386-opc.h (JumpAbsolute): Move between enums.
 329         (struct i386_opcode_modifier): Add jumpabsolute field.
 330         (union i386_operand_type): Remove jumpabsolute field.
 331         * i386-opc.tbl (call, lcall, jmp, ljmp): Move JumpAbsolute.
 332         * i386-init.h, i386-tbl.h: Re-generate.
 333
 334 2019-11-14  Jan Beulich  <jbeulich@suse.com>
 335
 336         * i386-gen.c (opcode_modifiers): Add AnySize entry.
 337         (operand_types): Remove AnySize entry.
 338         * i386-opc.h (AnySize): Move between enums.
 339         (struct i386_opcode_modifier): Add anysize field.
 340         (OTUnused): Un-comment.
 341         (union i386_operand_type): Remove anysize field.
 342         * i386-opc.tbl (lea, invlpg, clflush, prefetchnta, prefetcht0,
 343         prefetcht1, prefetcht2, prefetchtw, bndmk, bndcl, bndcu, bndcn,
 344         bndstx, bndldx, prefetchwt1, clflushopt, clwb, cldemote): Move
 345         AnySize.
 346         * i386-tbl.h: Re-generate.
 347
 348 2019-11-12  Nelson Chu  <nelson.chu@sifive.com>
 349
 350         * riscv-opc.c (riscv_insn_types): Replace the INSN_CLASS_I with
 351         INSN_CLASS_F and the INSN_CLASS_C with INSN_CLASS_F_AND_C if we
 352         use the floating point register (FPR).
 353
 354 2019-11-12  Mihail Ionescu  <mihail.ionescu@arm.com>
 355
 356         * opcodes/arm-dis.c (mve_opcodes): Enable VMOV imm to vec with
 357         cmode 1101.
 358         (is_mve_encoding_conflict): Update cmode conflict checks for
 359         MVE_VMVN_IMM.
 360
 361 2019-11-12  Jan Beulich  <jbeulich@suse.com>
 362
 363         * i386-gen.c (operand_type_init): Remove OPERAND_TYPE_ESSEG
 364         entry.
 365         (operand_types): Remove EsSeg entry.
 366         (main): Replace stale use of OTMax.
 367         * i386-opc.h (IS_STRING_ES_OP0, IS_STRING_ES_OP1): Define.
 368         (struct i386_opcode_modifier): Expand isstring field to 2 bits.
 369         (EsSeg): Delete.
 370         (OTUnused): Comment out.
 371         (union i386_operand_type): Remove esseg field.
 372         * i386-opc.tbl (IsStringEsOp0, IsStringEsOp1): Define.
 373         (cmps, scmp, scas, ssca, cmpsd): Add IsStringEsOp0.
 374         (ins, movs, smov, movsd): Add IsStringEsOpOp1.
 375         (stos, ssto): Add IsStringEsOp0/IsStringEsOpOp1.
 376         * i386-init.h, i386-tbl.h: Re-generate.
 377
 378 2019-11-12  Jan Beulich  <jbeulich@suse.com>
 379
 380         * i386-gen.c (operand_instances): Add RegB entry.
 381         * i386-opc.h (enum operand_instance): Add RegB.
 382         * i386-opc.tbl (RegC, RegD, RegB): Define.
 383         (Acc, ShiftCount, InOutPortReg): Adjust definitions.
 384         (monitor, mwait, invlpga, skinit, vmload, vmrun, vmsave, clzero,
 385         monitorx, mwaitx): Drop ImmExt and convert encodings
 386         accordingly.
 387         * i386-reg.tbl (ecx, rcx): Add Instance=RegC.
 388         (edx, rdx): Add Instance=RegD.
 389         (ebx, rbx): Add Instance=RegB.
 390         * i386-tbl.h: Re-generate.
 391
 392 2019-11-12  Jan Beulich  <jbeulich@suse.com>
 393
 394         * i386-gen.c (operand_type_init): Adjust
 395         OPERAND_TYPE_INOUTPORTREG, OPERAND_TYPE_SHIFTCOUNT,
 396         OPERAND_TYPE_FLOATACC, OPERAND_TYPE_ACC8, OPERAND_TYPE_ACC16,
 397         OPERAND_TYPE_ACC32, and OPERAND_TYPE_ACC64 entries.
 398         (operand_instances): New.
 399         (operand_types): Drop InOutPortReg, ShiftCount, and Acc entries.
 400         (output_operand_type): New parameter "instance". Process it.
 401         (process_i386_operand_type): New local variable "instance".
 402         (main): Adjust static assertions.
 403         * i386-opc.h (INSTANCE_WIDTH): Define.
 404         (enum operand_instance): New.
 405         (Acc, InOutPortReg, ShiftCount): Replace by ClassInstance.
 406         (union i386_operand_type): Replace acc, inoutportreg, and
 407         shiftcount by instance.
 408         * i386-opc.tbl (Acc, InOutPortReg, ShiftCount): Define.
 409         * i386-reg.tbl (st, al, cl, ax, dx, eax, rax, xmm0, st(0)):
 410         Add Instance=.
 411         * i386-init.h, i386-tbl.h: Re-generate.
 412
 413 2019-11-11  Jan Beulich  <jbeulich@suse.com>
 414
 415         * aarch64-tbl.h (aarch64_opcode_table): Switch SVE2's
 416         smaxp/sminp entries' "tied_operand" field to 2.
 417
 418 2019-11-11  Jan Beulich  <jbeulich@suse.com>
 419
 420         * aarch64-opc.c (operand_general_constraint_met_p): Replace
 421         "index" local variable by that of the already existing "num".
 422
 423 2019-11-08  H.J. Lu  <hongjiu.lu@intel.com>
 424
 425         PR gas/25167
 426         * i386-opc.tbl: Remove IgnoreSize from cmpsd and movsd.
 427         * i386-tbl.h: Regenerated.
 428
 429 2019-11-08  Jan Beulich  <jbeulich@suse.com>
 430
 431         * i386-gen.c (operand_type_init): Add Class= to
 432         OPERAND_TYPE_REGMASK and OPERAND_TYPE_REGBND entries. Move up
 433         OPERAND_TYPE_REGBND entry.
 434         (operand_classes): Add RegMask and RegBND entries.
 435         (operand_types): Drop RegMask and RegBND entry.
 436         * i386-opc.h (enum operand_class): Add RegMask and RegBND.
 437         (RegMask, RegBND): Delete.
 438         (union i386_operand_type): Remove regmask and regbnd fields.
 439         * i386-opc.tbl (RegMask, RegBND): Define.
 440         * i386-reg.tbl: Replace RegMask by Class=RegMask and RegBND by
 441         Class=RegBND.
 442         * i386-init.h, i386-tbl.h: Re-generate.
 443
 444 2019-11-08  Jan Beulich  <jbeulich@suse.com>
 445
 446         * i386-gen.c (operand_type_init): Add Class= to
 447         OPERAND_TYPE_REGMMX, OPERAND_TYPE_REGXMM, OPERAND_TYPE_REGYMM, and
 448         OPERAND_TYPE_REGZMM entries.
 449         (operand_classes): Add RegMMX and RegSIMD entries.
 450         (operand_types): Drop RegMMX and RegSIMD entries.
 451         * i386-opc.h (enum operand_class): Add RegMMX and RegSIMD.
 452         (RegMMX, RegSIMD): Delete.
 453         (union i386_operand_type): Remove regmmx and regsimd fields.
 454         * i386-opc.tbl (RegMMX): Define.
 455         (RegXMM, RegYMM, RegZMM): Add Class=.
 456         * i386-reg.tbl: Replace RegMMX by Class=RegMMX and RegSIMD by
 457         Class=RegSIMD.
 458         * i386-init.h, i386-tbl.h: Re-generate.
 459
 460 2019-11-08  Jan Beulich  <jbeulich@suse.com>
 461
 462         * i386-gen.c (operand_type_init): Add Class= to
 463         OPERAND_TYPE_CONTROL, OPERAND_TYPE_TEST, and OPERAND_TYPE_DEBUG
 464         entries.
 465         (operand_classes): Add RegCR, RegDR, and RegTR entries.
 466         (operand_types): Drop Control, Debug, and Test entries.
 467         * i386-opc.h (enum operand_class): Add RegCR, RegDR, and RegTR.
 468         (Control, Debug, Test): Delete.
 469         (union i386_operand_type): Remove control, debug, and test
 470         fields.
 471         * i386-opc.tbl (Control, Debug, Test): Define.
 472         * i386-reg.tbl: Replace Control by Class=RegCR, Debug by
 473         Class=RegDR, and Test by Class=RegTR.
 474         * i386-init.h, i386-tbl.h: Re-generate.
 475
 476 2019-11-08  Jan Beulich  <jbeulich@suse.com>
 477
 478         * i386-gen.c (operand_type_init): Add Class= to
 479         OPERAND_TYPE_SREG entry.
 480         (operand_classes): Add SReg entry.
 481         (operand_types): Drop SReg entry.
 482         * i386-opc.h (enum operand_class): Add SReg.
 483         (SReg): Delete.
 484         (union i386_operand_type): Remove sreg field.
 485         * i386-opc.tbl (SReg): Define.
 486         * i386-reg.tbl: Replace SReg by Class=SReg.
 487         * i386-init.h, i386-tbl.h: Re-generate.
 488
 489 2019-11-08  Jan Beulich  <jbeulich@suse.com>
 490
 491         * i386-gen.c (operand_type_init): Add Class=. New
 492         OPERAND_TYPE_ANYIMM entry.
 493         (operand_classes): New.
 494         (operand_types): Drop Reg entry.
 495         (output_operand_type): New parameter "class". Process it.
 496         (process_i386_operand_type): New local variable "class".
 497         (main): Adjust static assertions.
 498         * i386-opc.h (CLASS_WIDTH): Define.
 499         (enum operand_class): New.
 500         (Reg): Replace by Class. Adjust comment.
 501         (union i386_operand_type): Replace reg by class.
 502         * i386-opc.tbl (Reg8, Reg16, Reg32, Reg64, FloatReg): Add
 503         Class=.
 504         * i386-reg.tbl: Replace Reg by Class=Reg.
 505         * i386-init.h: Re-generate.
 506
 507 2019-11-07  Mihail Ionescu  <mihail.ionescu@arm.com>
 508
 509         * opcodes/aarch64-tbl.h (V8_6_INSN): New macro for v8.6 instructions.
 510         (aarch64_opcode_table): Add data gathering hint mnemonic.
 511         * opcodes/aarch64-dis-2.c: Account for new instruction.
 512
 513 2019-11-07  Mihail Ionescu  <mihail.ionescu@arm.com>
 514
 515         * arm-dis.c (neon_opcodes): Add i8mm SIMD instructions.
 516
 517
 518 2019-11-07  Mihail Ionescu  <mihail.ionescu@arm.com>
 519
 520         * aarch64-tbl.h (aarch64_feature_i8mm_sve, aarch64_feature_f32mm_sve,
 521         aarch64_feature_f64mm_sve, aarch64_feature_i8mm, aarch64_feature_f32mm,
 522         aarch64_feature_f64mm): New feature sets.
 523         (INT8MATMUL_INSN, F64MATMUL_SVE_INSN, F64MATMUL_INSN,
 524         F32MATMUL_SVE_INSN, F32MATMUL_INSN): New macros to define matrix multiply
 525         instructions.
 526         (I8MM_SVE, F32MM_SVE, F64MM_SVE, I8MM, F32MM, F64MM): New feature set
 527         macros.
 528         (QL_MMLA64, OP_SVE_SBB): New qualifiers.
 529         (OP_SVE_QQQ): New qualifier.
 530         (INT8MATMUL_SVE_INSNC, F64MATMUL_SVE_INSNC,
 531         F32MATMUL_SVE_INSNC): New feature set for bfloat16 instructions to support
 532         the movprfx constraint.
 533         (aarch64_opcode_table): Support for SVE_ADDR_RI_S4x32.
 534         (aarch64_opcode_table): Define new instructions smmla,
 535         ummla, usmmla, usdot, sudot, fmmla, ld1rob, ld1roh, ld1row, ld1rod,
 536         uzip{1/2}, trn{1/2}.
 537         * aarch64-opc.c (operand_general_constraint_met_p): Handle
 538         AARCH64_OPND_SVE_ADDR_RI_S4x32.
 539         (aarch64_print_operand): Handle AARCH64_OPND_SVE_ADDR_RI_S4x32.
 540         * aarch64-dis-2.c (aarch64_opcode_lookup_1, aarch64_find_next_opcode):
 541         Account for new instructions.
 542         * opcodes/aarch64-asm-2.c (aarch64_insert_operand): Support the new
 543         S4x32 operand.
 544         * aarch64-opc-2.c (aarch64_operands): Support the new S4x32 operand.
 545
 546 2019-11-07  Mihail Ionescu  <mihail.ionescu@arm.com>
 547 2019-11-07  Matthew Malcomson  <matthew.malcomson@arm.com>
 548
 549         * arm-dis.c (select_arm_features): Update bfd_march_arm_8 with
 550         Armv8.6-A.
 551         (coprocessor_opcodes): Add bfloat16 vcvt{t,b}.
 552         (neon_opcodes): Add bfloat SIMD instructions.
 553         (print_insn_coprocessor): Add new control character %b to print
 554         condition code without checking cp_num.
 555         (print_insn_neon): Account for BFloat16 instructions that have no
 556         special top-byte handling.
 557
 558 2019-11-07  Mihail Ionescu  <mihail.ionescu@arm.com>
 559 2019-11-07  Matthew Malcomson  <matthew.malcomson@arm.com>
 560
 561         * arm-dis.c (print_insn_coprocessor,
 562         print_insn_generic_coprocessor): Create wrapper functions around
 563         the implementation of the print_insn_coprocessor control codes.
 564         (print_insn_coprocessor_1): Original print_insn_coprocessor
 565         function that now takes which array to look at as an argument.
 566         (print_insn_arm): Use both print_insn_coprocessor and
 567         print_insn_generic_coprocessor.
 568         (print_insn_thumb32): As above.
 569
 570 2019-11-07  Mihail Ionescu  <mihail.ionescu@arm.com>
 571 2019-11-07  Matthew Malcomson  <matthew.malcomson@arm.com>
 572
 573         * aarch64-asm.c (aarch64_ins_reglane): Use AARCH64_OPND_QLF_S_2H
 574         in reglane special case.
 575         * aarch64-dis-2.c (aarch64_opcode_lookup_1,
 576         aarch64_find_next_opcode): Account for new instructions.
 577         * aarch64-dis.c (aarch64_ext_reglane): Use AARCH64_OPND_QLF_S_2H
 578         in reglane special case.
 579         * aarch64-opc.c (struct operand_qualifier_data): Add data for
 580         new AARCH64_OPND_QLF_S_2H qualifier.
 581         * aarch64-tbl.h (QL_BFDOT QL_BFDOT64, QL_BFDOT64I, QL_BFMMLA2,
 582         QL_BFCVT64, QL_BFCVTN64, QL_BFCVTN2_64): New qualifiers.
 583         (aarch64_feature_bfloat16, aarch64_feature_bfloat16_sve): New feature
 584         sets.
 585         (BFLOAT_SVE, BFLOAT): New feature set macros.
 586         (BFLOAT_SVE_INSN, BFLOAT_INSN): New macros to define BFloat16
 587         instructions.
 588         (aarch64_opcode_table): Define new instructions bfdot,
 589         bfmmla, bfcvt, bfcvtnt, bfdot, bfdot, bfcvtn, bfmlal[b/t]
 590         bfcvtn2, bfcvt.
 591
 592 2019-11-07  Mihail Ionescu  <mihail.ionescu@arm.com>
 593 2019-11-07  Matthew Malcomson  <matthew.malcomson@arm.com>
 594
 595         * aarch64-tbl.h (ARMV8_6): New macro.
 596
 597 2019-11-07  Jan Beulich  <jbeulich@suse.com>
 598
 599         * i386-dis.c (prefix_table): Add mcommit.
 600         (rm_table): Add rdpru.
 601         * i386-gen.c (cpu_flag_init): Adjust CPU_ZNVER2_FLAGS entry. Add
 602         CPU_RDPRU_FLAGS and CPU_MCOMMIT_FLAGS entries.
 603         (cpu_flags): Add CpuRDPRU and CpuMCOMMIT entries.
 604         * i386-opc.h (CpuRDPRU, CpuMCOMMIT): New.
 605         (union i386_cpu_flags): Add cpurdpru and cpumcommit fields.
 606         * i386-opc.tbl (mcommit, rdpru): New.
 607         * i386-init.h, i386-tbl.h: Re-generate.
 608
 609 2019-11-07  Jan Beulich  <jbeulich@suse.com>
 610
 611         * i386-dis.c (OP_Mwait): Drop local variable "names", use
 612         "names32" instead.
 613         (OP_Monitor): Drop local variable "op1_names", re-purpose
 614         "names" for it instead, and replace former "names" uses by
 615         "names32" ones.
 616
 617 2019-11-07  Jan Beulich  <jbeulich@suse.com>
 618
 619         PR/gas 25167
 620         * opcodes/i386-opc.tbl (movsd, cmpsd): Drop IgnoreSize from
 621         operand-less forms.
 622         * opcodes/i386-tbl.h: Re-generate.
 623
 624 2019-11-05  Jan Beulich  <jbeulich@suse.com>
 625
 626         * i386-dis.c (OP_Mwaitx): Delete.
 627         (prefix_table): Use OP_Mwait for mwaitx entry.
 628         (OP_Mwait): Also handle mwaitx.
 629
 630 2019-11-05  Jan Beulich  <jbeulich@suse.com>
 631
 632         * i386-dis.c (PREFIX_0F01_REG_7_MOD_3_RM_2,
 633         PREFIX_0F01_REG_7_MOD_3_RM_3): New.
 634         (prefix_table): Add respective entries.
 635         (rm_table): Link to those entries.
 636
 637 2019-11-05  Jan Beulich  <jbeulich@suse.com>
 638
 639         * i386-dis.c (REG_0F1C_MOD_0): Rename to ...
 640         (REG_0F1C_P_0_MOD_0): ... this.
 641         (REG_0F1E_MOD_3): Rename to ...
 642         (REG_0F1E_P_1_MOD_3): ... this.
 643         (RM_0F01_REG_5): Rename to ...
 644         (RM_0F01_REG_5_MOD_3): ... this.
 645         (RM_0F01_REG_7): Rename to ...
 646         (RM_0F01_REG_7_MOD_3): ... this.
 647         (RM_0F1E_MOD_3_REG_7): Rename to ...
 648         (RM_0F1E_P_1_MOD_3_REG_7): ... this.
 649         (RM_0FAE_REG_6): Rename to ...
 650         (RM_0FAE_REG_6_MOD_3_P_0): ... this.
 651         (RM_0FAE_REG_7): Rename to ...
 652         (RM_0FAE_REG_7_MOD_3): ... this.
 653         (PREFIX_MOD_0_0F01_REG_5): Rename to ...
 654         (PREFIX_0F01_REG_5_MOD_0): ... this.
 655         (PREFIX_MOD_3_0F01_REG_5_RM_0): Rename to ...
 656         (PREFIX_0F01_REG_5_MOD_3_RM_0): ... this.
 657         (PREFIX_MOD_3_0F01_REG_5_RM_2): Rename to ...
 658         (PREFIX_0F01_REG_5_MOD_3_RM_2): ... this.
 659         (PREFIX_0FAE_REG_0): Rename to ...
 660         (PREFIX_0FAE_REG_0_MOD_3): ... this.
 661         (PREFIX_0FAE_REG_1): Rename to ...
 662         (PREFIX_0FAE_REG_1_MOD_3): ... this.
 663         (PREFIX_0FAE_REG_2): Rename to ...
 664         (PREFIX_0FAE_REG_2_MOD_3): ... this.
 665         (PREFIX_0FAE_REG_3): Rename to ...
 666         (PREFIX_0FAE_REG_3_MOD_3): ... this.
 667         (PREFIX_MOD_0_0FAE_REG_4): Rename to ...
 668         (PREFIX_0FAE_REG_4_MOD_0): ... this.
 669         (PREFIX_MOD_3_0FAE_REG_4): Rename to ...
 670         (PREFIX_0FAE_REG_4_MOD_3): ... this.
 671         (PREFIX_MOD_0_0FAE_REG_5): Rename to ...
 672         (PREFIX_0FAE_REG_5_MOD_0): ... this.
 673         (PREFIX_MOD_3_0FAE_REG_5): Rename to ...
 674         (PREFIX_0FAE_REG_5_MOD_3): ... this.
 675         (PREFIX_MOD_0_0FAE_REG_6): Rename to ...
 676         (PREFIX_0FAE_REG_6_MOD_0): ... this.
 677         (PREFIX_MOD_1_0FAE_REG_6): Rename to ...
 678         (PREFIX_0FAE_REG_6_MOD_3): ... this.
 679         (PREFIX_0FAE_REG_7): Rename to ...
 680         (PREFIX_0FAE_REG_7_MOD_0): ... this.
 681         (PREFIX_MOD_0_0FC3): Rename to ...
 682         (PREFIX_0FC3_MOD_0): ... this.
 683         (PREFIX_MOD_0_0FC7_REG_6): Rename to ...
 684         (PREFIX_0FC7_REG_6_MOD_0): ... this.
 685         (PREFIX_MOD_3_0FC7_REG_6): Rename to ...
 686         (PREFIX_0FC7_REG_6_MOD_3): ... this.
 687         (PREFIX_MOD_3_0FC7_REG_7): Rename to ...
 688         (PREFIX_0FC7_REG_7_MOD_3): ... this.
 689         (reg_table, prefix_table, mod_table, rm_table): Adjust
 690         accordingly.
 691
 692 2019-11-04  Nick Clifton  <nickc@redhat.com>
 693
 694         * v850-dis.c (get_v850_sreg_name): New function.  Returns the name
 695         of a v850 system register.  Move the v850_sreg_names array into
 696         this function.
 697         (get_v850_reg_name): Likewise for ordinary register names.
 698         (get_v850_vreg_name): Likewise for vector register names.
 699         (get_v850_cc_name): Likewise for condition codes.
 700         * get_v850_float_cc_name): Likewise for floating point condition
 701         codes.
 702         (get_v850_cacheop_name): Likewise for cache-ops.
 703         (get_v850_prefop_name): Likewise for pref-ops.
 704         (disassemble): Use the new accessor functions.
 705
 706 2019-10-30  Delia Burduv   <delia.burduv@arm.com>
 707
 708         * aarch64-opc.c (print_immediate_offset_address): Don't print the
 709         immediate for the writeback form of ldraa/ldrab if it is 0.
 710         * aarch64-tbl.h: Updated the documentation for ADDR_SIMM10.
 711         * aarch64-opc-2.c: Regenerated.
 712
 713 2019-10-30  Jan Beulich  <jbeulich@suse.com>
 714
 715         * i386-gen.c (operand_type_shorthands): Delete.
 716         (operand_type_init): Expand previous shorthands.
 717         (set_bitfield_from_shorthand): Rename back to ...
 718         (set_bitfield_from_cpu_flag_init): ... this.  Drop processing
 719         of operand_type_init[].
 720         (set_bitfield): Adjust call to the above function.
 721         * i386-opc.tbl (Reg8, Reg16, Reg32, Reg64, FloatAcc, FloatReg,
 722         RegXMM, RegYMM, RegZMM): Define.
 723         * i386-reg.tbl: Expand prior shorthands.
 724
 725 2019-10-30  Jan Beulich  <jbeulich@suse.com>
 726
 727         * i386-gen.c (output_i386_opcode): Change order of fields
 728         emitted to output.
 729         * i386-opc.h (struct insn_template): Move operands field.
 730         Convert extension_opcode field to unsigned short.
 731         * i386-tbl.h: Re-generate.
 732
 733 2019-10-30  Jan Beulich  <jbeulich@suse.com>
 734
 735         * i386-gen.c (process_i386_opcode_modifier): Report bogus uses
 736         of W.
 737         * i386-opc.h (W): Extend comment.
 738         * i386-opc.tbl (mov, movabs, movq): Drop W and adjust opcodes of
 739         general purpose variants not allowing for byte operands.
 740         * i386-tbl.h: Re-generate.
 741
 742 2019-10-29  Nick Clifton  <nickc@redhat.com>
 743
 744         * tic30-dis.c (print_branch): Correct size of operand array.
 745
 746 2019-10-29  Nick Clifton  <nickc@redhat.com>
 747
 748         * d30v-dis.c (print_insn): Check that operand index is valid
 749         before attempting to access the operands array.
 750
 751 2019-10-29  Nick Clifton  <nickc@redhat.com>
 752
 753         * ia64-opc.c (locate_opcode_ent): Prevent a negative shift when
 754         locating the bit to be tested.
 755
 756 2019-10-29  Nick Clifton  <nickc@redhat.com>
 757
 758         * s12z-dis.c (opr_emit_disassembly): Check for illegal register
 759         values.
 760         (shift_size_table): Use a fixed size defined as S12Z_N_SIZES.
 761         (print_insn_s12z):  Check for illegal size values.
 762
 763 2019-10-28  Nick Clifton  <nickc@redhat.com>
 764
 765         * csky-dis.c (csky_chars_to_number): Check for a negative
 766         count. Use an unsigned integer to construct the return value.
 767
 768 2019-10-28  Nick Clifton  <nickc@redhat.com>
 769
 770         * tic30-dis.c (OPERAND_BUFFER_LEN): Define.  Use as length of
 771         operand buffer.  Set value to 15 not 13.
 772         (get_register_operand): Use OPERAND_BUFFER_LEN.
 773         (get_indirect_operand): Likewise.
 774         (print_two_operand): Likewise.
 775         (print_three_operand): Likewise.
 776         (print_oar_insn): Likewise.
 777
 778 2019-10-28  Nick Clifton  <nickc@redhat.com>
 779
 780         * ns32k-dis.c (bit_extract): Add sanitiy check of parameters.
 781         (bit_extract_simple): Likewise.
 782         (bit_copy): Likewise.
 783         (pirnt_insn_ns32k): Ensure that uninitialised elements in the
 784         index_offset array are not accessed.
 785
 786 2019-10-28  Nick Clifton  <nickc@redhat.com>
 787
 788         * xgate-dis.c (print_insn): Fix decoding of the XGATE_OP_DYA
 789         operand.
 790
 791 2019-10-25  Nick Clifton  <nickc@redhat.com>
 792
 793         * rx-dis.c (print_insn_rx): Use parenthesis to ensure correct
 794         access to opcodes.op array element.
 795
 796 2019-10-23  Nick Clifton  <nickc@redhat.com>
 797
 798         * rx-dis.c (get_register_name): Fix spelling typo in error
 799         message.
 800         (get_condition_name, get_flag_name, get_double_register_name)
 801         (get_double_register_high_name, get_double_register_low_name)
 802         (get_double_control_register_name, get_double_condition_name)
 803         (get_opsize_name, get_size_name): Likewise.
 804
 805 2019-10-22  Nick Clifton  <nickc@redhat.com>
 806
 807         * rx-dis.c (get_size_name): New function.  Provides safe
 808         access to name array.
 809         (get_opsize_name): Likewise.
 810         (print_insn_rx): Use the accessor functions.
 811
 812 2019-10-16  Nick Clifton  <nickc@redhat.com>
 813
 814         * rx-dis.c (get_register_name): New function.  Provides safe
 815         access to name array.
 816         (get_condition_name, get_flag_name, get_double_register_name)
 817         (get_double_register_high_name, get_double_register_low_name)
 818         (get_double_control_register_name, get_double_condition_name):
 819         Likewise.
 820         (print_insn_rx): Use the accessor functions.
 821
 822 2019-10-09  Nick Clifton  <nickc@redhat.com>
 823
 824         PR 25041
 825         * avr-dis.c (avr_operand): Fix construction of address for lds/sts
 826         instructions.
 827
 828 2019-10-07  Jan Beulich  <jbeulich@suse.com>
 829
 830         * opcodes/i386-opc.tbl (movsd): Add Dword and IgnoreSize.
 831         (cmpsd): Likewise. Move EsSeg to other operand.
 832         * opcodes/i386-tbl.h: Re-generate.
 833
 834 2019-09-23  Alan Modra  <amodra@gmail.com>
 835
 836         * m68k-dis.c: Include cpu-m68k.h
 837
 838 2019-09-23  Alan Modra  <amodra@gmail.com>
 839
 840         * mips-dis.c: Include elfxx-mips.h.  Move "elf-bfd.h" and
 841         "elf/mips.h" earlier.
 842
 843 2018-09-20  Jan Beulich  <jbeulich@suse.com>
 844
 845         PR gas/25012
 846         * i386-opc.tbl (push, pop): Re-instate distinct Cpu64 templates
 847         with SReg operand.
 848         * i386-tbl.h: Re-generate.
 849
 850 2019-09-18  Alan Modra  <amodra@gmail.com>
 851
 852         * arc-ext.c: Update throughout for bfd section macro changes.
 853
 854 2019-09-18  Simon Marchi  <simon.marchi@polymtl.ca>
 855
 856         * Makefile.in: Re-generate.
 857         * configure: Re-generate.
 858
 859 2019-09-17  Maxim Blinov  <maxim.blinov@embecosm.com>
 860
 861         * riscv-opc.c (riscv_opcodes): Change subset field
 862         to insn_class field for all instructions.
 863         (riscv_insn_types): Likewise.
 864
 865 2019-09-16  Phil Blundell  <pb@pbcl.net>
 866
 867         * configure: Regenerated.
 868
 869 2019-09-10  Miod Vallat  <miod@online.fr>
 870
 871         PR 24982
 872         * m68k-opc.c: Correct aliases for tdivsl and tdivul.
 873
 874 2019-09-09  Phil Blundell  <pb@pbcl.net>
 875
 876         binutils 2.33 branch created.
 877
 878 2019-09-03  Nick Clifton  <nickc@redhat.com>
 879
 880         PR 24961
 881         * tic30-dis.c (get_indirect_operand): Check for bufcnt being
 882         greater than zero before indexing via (bufcnt -1).
 883
 884 2019-09-03  Nick Clifton  <nickc@redhat.com>
 885
 886         PR 24958
 887         * mmix-dis.c (MAX_REG_NAME_LEN): Define.
 888         (MAX_SPEC_REG_NAME_LEN): Define.
 889         (struct mmix_dis_info): Use defined constants for array lengths.
 890         (get_reg_name): New function.
 891         (get_sprec_reg_name): New function.
 892         (print_insn_mmix): Use new functions.
 893
 894 2019-08-27  Srinath Parvathaneni  <srinath.parvathaneni@arm.com>
 895
 896         * arm-dis.c (mve_opcodes): Add entry for MVE_VMOV_VEC_TO_VEC.
 897         (is_mve_undefined): Add case for MVE_VMOV_VEC_TO_VEC.
 898         (print_insn_mve): Add condition to check Qm==Qn of VORR instruction.
 899
 900 2019-08-22  Kyrylo Tkachov <kyrylo.tkachov@arm.com>
 901
 902         * aarch64-opc.c (aarch64_sys_regs): Update encoding of tfsre0_el1,
 903         tfsr_el1, tfsr_el2, tfsr_el3, tfsr_el12.
 904         (aarch64_sys_reg_supported_p): Update checks for the above.
 905
 906 2019-08-12  Srinath Parvathaneni  <srinath.parvathaneni@arm.com>
 907
 908         * arm-dis.c (struct mopcode32 mve_opcodes): Modify the mask for
 909         cases MVE_SQRSHRL and MVE_UQRSHLL.
 910         (print_insn_mve): Add case for specifier 'k' to check
 911         specific bit of the instruction.
 912
 913 2019-08-07  Phillipe Antoine  <p.antoine@catenacyber.fr>
 914
 915         PR 24854
 916         * arc-dis.c (arc_insn_length): Return 0 rather than aborting when
 917         encountering an unknown machine type.
 918         (print_insn_arc): Handle arc_insn_length returning 0.  In error
 919         cases return -1 rather than calling abort.
 920
 921 2019-08-07  Jan Beulich  <jbeulich@suse.com>
 922
 923         * i386-opc.tbl (fld, fstp): Drop FloatMF from extended forms.
 924         (fldcw, fnstcw, fstcw, fnstsw, fstsw): Replace FloatMF by
 925         IgnoreSize.
 926         * i386-tbl.h: Re-generate.
 927
 928 2019-08-05  Barnaby Wilks  <barnaby.wilks@arm.com>
 929
 930         * arm-dis.c: Only accept signed variants of VQ(R)DMLAH and VQ(R)DMLASH
 931         instructions.
 932
 933 2019-07-30  Mel Chen <mel.chen@sifive.com>
 934
 935         * riscv-opc.c (riscv_opcodes): Set frsr, fssr, frcsr, fscsr, frrm,
 936         fsrm, fsrmi, frflags, fsflags, fsflagsi to alias instructions.
 937
 938         * riscv-opc.c (riscv_opcodes): Adjust order of frsr, frcsr, fssr,
 939         fscsr.
 940
 941 2019-07-24  Claudiu Zissulescu  <claziss@synopsys.com>
 942
 943         * arc-dis.c (skip_this_opcode): Check also for 0x07 major opcodes,
 944         and MPY class instructions.
 945         (parse_option): Add nps400 option.
 946         (print_arc_disassembler_options): Add nps400 info.
 947
 948 2019-07-24  Claudiu Zissulescu  <claziss@synopsys.com>
 949
 950         * arc-ext-tbl.h (bspeek): Remove it, added to main table.
 951         (bspop): Likewise.
 952         (modapp): Likewise.
 953         * arc-opc.c (RAD_CHK): Add.
 954         * arc-tbl.h: Regenerate.
 955
 956 2019-07-23  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
 957
 958         * aarch64-opc.c (aarch64_sys_regs): Add gmid_el1 entry.
 959         (aarch64_sys_reg_supported_p): Handle gmid_el1 encoding.
 960
 961 2019-07-22  Barnaby Wilks  <barnaby.wilks@arm.com>
 962
 963         * arm-dis.c (is_mve_unpredictable): Stop marking some MVE
 964         instructions as UNPREDICTABLE.
 965
 966 2019-07-19  Jose E. Marchesi  <jose.marchesi@oracle.com>
 967
 968         * bpf-desc.c: Regenerated.
 969
 970 2019-07-17  Jan Beulich  <jbeulich@suse.com>
 971
 972         * i386-gen.c (static_assert): Define.
 973         (main): Use it.
 974         * i386-opc.h (Opcode_Modifier_Max): Rename to ...
 975         (Opcode_Modifier_Num): ... this.
 976         (Mem): Delete.
 977
 978 2019-07-16  Jan Beulich  <jbeulich@suse.com>
 979
 980         * i386-gen.c (operand_types): Move RegMem ...
 981         (opcode_modifiers): ... here.
 982         * i386-opc.h (RegMem): Move to opcode modifer enum.
 983         (union i386_operand_type): Move regmem field ...
 984         (struct i386_opcode_modifier): ... here.
 985         * i386-opc.tbl (RegMem): Define.
 986         (mov, movq): Move RegMem on segment, control, debug, and test
 987         register flavors.
 988         (pextrb): Move RegMem on register only flavors. Add IgnoreSize
 989         to non-SSE2AVX flavor.
 990         (extractps, pextrw, vcvtps2ph, vextractps, vpextrb, vpextrw):
 991         Move RegMem on register only flavors. Drop IgnoreSize from
 992         legacy encoding flavors.
 993         (movss, movsd, vmovss, vmovsd): Drop RegMem from register only
 994         flavors.
 995         (vpinsrb, vpinsrw): Drop IgnoreSize where still present on
 996         register only flavors.
 997         (vmovd): Move RegMem and drop IgnoreSize on register only
 998         flavor. Change opcode and operand order to store form.
 999         * opcodes/i386-init.h, i386-tbl.h: Re-generate.
1000
1001 2019-07-16  Jan Beulich  <jbeulich@suse.com>
1002
1003         * i386-gen.c (operand_type_init, operand_types): Replace SReg
1004         entries.
1005         * i386-opc.h (SReg2, SReg3): Replace by ...
1006         (SReg): ... this.
1007         (union i386_operand_type): Replace sreg fields.
1008         * i386-opc.tbl (mov, ): Use SReg.
1009         (push, pop): Likewies. Drop i386 and x86-64 specific segment
1010         register flavors.
1011         * i386-reg.tbl (cs, ds, es, fs, gs, ss, flat): Use SReg.
1012         * opcodes/i386-init.h, i386-tbl.h: Re-generate.
1013
1014 2019-07-15  Jose E. Marchesi  <jose.marchesi@oracle.com>
1015
1016         * bpf-desc.c: Regenerate.
1017         * bpf-opc.c: Likewise.
1018         * bpf-opc.h: Likewise.
1019
1020 2019-07-14  Jose E. Marchesi  <jose.marchesi@oracle.com>
1021
1022         * bpf-desc.c: Regenerate.
1023         * bpf-opc.c: Likewise.
1024
1025 2019-07-10  Hans-Peter Nilsson  <hp@bitrange.com>
1026
1027         * arm-dis.c (print_insn_coprocessor): Rename index to
1028         index_operand.
1029
1030 2019-07-05  Kito Cheng <kito.cheng@sifive.com>
1031
1032         * riscv-opc.c (riscv_insn_types): Add r4 type.
1033
1034         * riscv-opc.c (riscv_insn_types): Add b and j type.
1035
1036         * opcodes/riscv-opc.c (riscv_insn_types): Remove incorrect
1037         format for sb type and correct s type.
1038
1039 2019-07-02  Richard Sandiford  <richard.sandiford@arm.com>
1040
1041         * aarch64-tbl.h (aarch64_opcode): Set C_SCAN_MOVPRFX for the
1042         SVE FMOV alias of FCPY.
1043
1044 2019-07-02  Richard Sandiford  <richard.sandiford@arm.com>
1045
1046         * aarch64-tbl.h (aarch64_opcode_table): Add C_MAX_ELEM flags
1047         to SVE fcvtzs, fcvtzu, scvtf and ucvtf entries.
1048
1049 2019-07-02  Richard Sandiford  <richard.sandiford@arm.com>
1050
1051         * aarch64-opc.c (verify_constraints): Skip GPRs when scanning the
1052         registers in an instruction prefixed by MOVPRFX.
1053
1054 2019-07-01  Matthew Malcomson  <matthew.malcomson@arm.com>
1055
1056         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Use new
1057         sve_size_13 icode to account for variant behaviour of
1058         pmull{t,b}.
1059         * aarch64-dis-2.c: Regenerate.
1060         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Use new
1061         sve_size_13 icode to account for variant behaviour of
1062         pmull{t,b}.
1063         * aarch64-tbl.h (OP_SVE_VVV_HD_BS): Add new qualifier.
1064         (OP_SVE_VVV_Q_D): Add new qualifier.
1065         (OP_SVE_VVV_QHD_DBS): Remove now unused qualifier.
1066         (struct aarch64_opcode): Split pmull{t,b} into those requiring
1067         AES and those not.
1068
1069 2019-07-01  Jan Beulich  <jbeulich@suse.com>
1070
1071         * opcodes/i386-gen.c (operand_type_init): Remove
1072         OPERAND_TYPE_VEC_IMM4 entry.
1073         (operand_types): Remove Vec_Imm4.
1074         * opcodes/i386-opc.h (Vec_Imm4): Delete.
1075         (union i386_operand_type): Remove vec_imm4.
1076         * i386-opc.tbl (vpermil2pd, vpermil2ps): Remove Vec_Imm4.
1077         * opcodes/i386-init.h, i386-tbl.h: Re-generate.
1078
1079 2019-07-01  Jan Beulich  <jbeulich@suse.com>
1080
1081         * i386-opc.tbl (lfence, mfence, sfence, monitor, mwait, vmcall,
1082         vmlaunch, vmresume, vmxoff, vmfunc, xgetbv, xsetbv, swapgs,
1083         rdtscp, clgi, invlpga, skinit, stgi, vmload, vmmcall, vmrun,
1084         vmsave, montmul, xsha1, xsha256, xstorerng, xcryptecb,
1085         xcryptcbc, xcryptctr, xcryptcfb, xcryptofb, xstore, clac, stac,
1086         monitorx, mwaitx): Drop ImmExt from operand-less forms.
1087         * i386-tbl.h: Re-generate.
1088
1089 2019-07-01  Jan Beulich  <jbeulich@suse.com>
1090
1091         * i386-opc.tbl (and, or): Add Optimize to forms allowing two
1092         register operands.
1093         * i386-tbl.h: Re-generate.
1094
1095 2019-07-01  Jan Beulich  <jbeulich@suse.com>
1096
1097         * i386-opc.tbl (C): New.
1098         (paddb, paddw, paddd, paddq, paddsb, paddsw, paddusb, paddusw,
1099         pand, pcmpeqb, pcmpeqw, pcmpeqd, pmaddwd, pmulhw, pmullw,
1100         por, pxor, andps, cmpeqps, cmpeqss, cmpneqps, cmpneqss,
1101         cmpordps, cmpordss, cmpunordps, cmpunordss, orps, pavgb, pavgw,
1102         pmaxsw, pmaxub, pminsw, pminub, pmulhuw, xorps, andpd, cmpeqpd,
1103         cmpeqsd, cmpneqpd, cmpneqsd, cmpordpd, cmpordsd, cmpunordpd,
1104         cmpunordsd, orpd, xorpd, pmuludq, vandpd, vandps, vcmpeq_ospd,
1105         vcmpeq_osps, vcmpeq_ossd, vcmpeq_osss, vcmpeqpd, vcmpeqps,
1106         vcmpeqsd, vcmpeqss, vcmpeq_uqpd, vcmpeq_uqps, vcmpeq_uqsd,
1107         vcmpeq_uqss, vcmpeq_uspd, vcmpeq_usps, vcmpeq_ussd,
1108         vcmpeq_usss, vcmpfalse_ospd, vcmpfalse_osps, vcmpfalse_ossd,
1109         vcmpfalse_osss, vcmpfalsepd, vcmpfalseps, vcmpfalsesd,
1110         vcmpfalsess, vcmpneq_oqpd, vcmpneq_oqps, vcmpneq_oqsd,
1111         vcmpneq_oqss, vcmpneq_ospd, vcmpneq_osps, vcmpneq_ossd,
1112         vcmpneq_osss, vcmpneqpd, vcmpneqps, vcmpneqsd, vcmpneqss,
1113         vcmpneq_uspd, vcmpneq_usps, vcmpneq_ussd, vcmpneq_usss,
1114         vcmpordpd, vcmpordps, vcmpordsd, vcmpord_spd, vcmpord_sps,
1115         vcmpordss, vcmpord_ssd, vcmpord_sss, vcmptruepd, vcmptrueps,
1116         vcmptruesd, vcmptruess, vcmptrue_uspd, vcmptrue_usps,
1117         vcmptrue_ussd, vcmptrue_usss, vcmpunordpd, vcmpunordps,
1118         vcmpunordsd, vcmpunord_spd, vcmpunord_sps, vcmpunordss,
1119         vcmpunord_ssd, vcmpunord_sss, vorpd, vorps, vpaddsb, vpaddsw,
1120         vpaddb, vpaddd, vpaddq, vpaddw, vpaddusb, vpaddusw, vpand,
1121         vpavgb, vpavgw, vpcmpeqb, vpcmpeqd, vpcmpeqw, vpmaddwd,
1122         vpmaxsw, vpmaxub, vpminsw, vpminub, vpmulhuw, vpmulhw, vpmullw,
1123         vpmuludq, vpor, vpxor, vxorpd, vxorps): Add C to VEX-encoded
1124         flavors.
1125         * i386-tbl.h: Re-generate.
1126
1127 2019-07-01  Jan Beulich  <jbeulich@suse.com>
1128
1129         * i386-opc.tbl (and, or): Add Optimize to forms allowing two
1130         register operands.
1131         * i386-tbl.h: Re-generate.
1132
1133 2019-07-01  Jan Beulich  <jbeulich@suse.com>
1134
1135         * i386-dis-evex-prefix.h: Use PCLMUL for vpclmulqdq.
1136         * i386-opc.tbl (vpclmullqlqdq, vpclmulhqlqdq, vpclmullqhqdq,
1137         vpclmulhqhqdq): Add CpuVPCLMULQDQ flavors.
1138         * i386-tbl.h: Re-generate.
1139
1140 2019-07-01  Jan Beulich  <jbeulich@suse.com>
1141
1142         * i386-opc.tbl (vextractps, vpextrw, vpinsrw): Remove
1143         Disp8MemShift from register only templates.
1144         * i386-tbl.h: Re-generate.
1145
1146 2019-07-01  Jan Beulich  <jbeulich@suse.com>
1147
1148         * i386-dis.c (EXdScalarS, MOD_EVEX_0F10_PREFIX_1,
1149         MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1,
1150         MOD_EVEX_0F11_PREFIX_3, EVEX_W_0F10_P_1_M_0,
1151         EVEX_W_0F10_P_1_M_1, EVEX_W_0F10_P_3_M_0, EVEX_W_0F10_P_3_M_1,
1152         EVEX_W_0F11_P_1_M_0, EVEX_W_0F11_P_1_M_1, EVEX_W_0F11_P_3_M_0,
1153         EVEX_W_0F11_P_3_M_1): Delete.
1154         (EVEX_W_0F10_P_1, EVEX_W_0F10_P_3, EVEX_W_0F11_P_1,
1155         EVEX_W_0F11_P_3): New.
1156         * i386-dis-evex-mod.h: Remove MOD_EVEX_0F10_PREFIX_1,
1157         MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1, and
1158         MOD_EVEX_0F11_PREFIX_3 table entries.
1159         * i386-dis-evex-prefix.h: Adjust PREFIX_EVEX_0F10 and
1160         PREFIX_EVEX_0F11 table entries.
1161         * i386-dis-evex-w.h: Replace EVEX_W_0F10_P_1_M_{0,1},
1162         EVEX_W_0F10_P_3_M_{0,1}, EVEX_W_0F11_P_1_M_{0,1}, and
1163         EVEX_W_0F11_P_3_M_{0,1} table entries.
1164
1165 2019-07-01  Jan Beulich  <jbeulich@suse.com>
1166
1167         * i386-dis.c (EXdVex, EXdVexS, EXqVex, EXqVexS, XMVex):
1168         Delete.
1169
1170 2019-06-27  H.J. Lu  <hongjiu.lu@intel.com>
1171
1172         PR binutils/24719
1173         * i386-dis-evex-len.h: Add EVEX_LEN_0F38C6_REG_1_PREFIX_2,
1174         EVEX_LEN_0F38C6_REG_2_PREFIX_2, EVEX_LEN_0F38C6_REG_5_PREFIX_2,
1175         EVEX_LEN_0F38C6_REG_6_PREFIX_2, EVEX_LEN_0F38C7_R_1_P_2_W_0,
1176         EVEX_LEN_0F38C7_R_1_P_2_W_1, EVEX_LEN_0F38C7_R_2_P_2_W_0,
1177         EVEX_LEN_0F38C7_R_2_P_2_W_1, EVEX_LEN_0F38C7_R_5_P_2_W_0,
1178         EVEX_LEN_0F38C7_R_5_P_2_W_1, EVEX_LEN_0F38C7_R_6_P_2_W_0 and
1179         EVEX_LEN_0F38C7_R_6_P_2_W_1.
1180         * i386-dis-evex-prefix.h: Update PREFIX_EVEX_0F38C6_REG_1,
1181         PREFIX_EVEX_0F38C6_REG_2, PREFIX_EVEX_0F38C6_REG_5 and
1182         PREFIX_EVEX_0F38C6_REG_6 entries.
1183         * i386-dis-evex-w.h: Update EVEX_W_0F38C7_R_1_P_2,
1184         EVEX_W_0F38C7_R_2_P_2, EVEX_W_0F38C7_R_5_P_2 and
1185         EVEX_W_0F38C7_R_6_P_2 entries.
1186         * i386-dis.c: Add EVEX_LEN_0F38C6_REG_1_PREFIX_2,
1187         EVEX_LEN_0F38C6_REG_2_PREFIX_2, EVEX_LEN_0F38C6_REG_5_PREFIX_2,
1188         EVEX_LEN_0F38C6_REG_6_PREFIX_2, EVEX_LEN_0F38C7_R_1_P_2_W_0,
1189         EVEX_LEN_0F38C7_R_1_P_2_W_1, EVEX_LEN_0F38C7_R_2_P_2_W_0,
1190         EVEX_LEN_0F38C7_R_2_P_2_W_1, EVEX_LEN_0F38C7_R_5_P_2_W_0,
1191         EVEX_LEN_0F38C7_R_5_P_2_W_1, EVEX_LEN_0F38C7_R_6_P_2_W_0 and
1192         EVEX_LEN_0F38C7_R_6_P_2_W_1 enums.
1193
1194 2019-06-27  Jan Beulich  <jbeulich@suse.com>
1195
1196         * i386-dis.c (VEX_LEN_0F2A_P_1, VEX_LEN_0F2A_P_3,
1197         VEX_LEN_0F2C_P_1, VEX_LEN_0F2C_P_3, VEX_LEN_0F2D_P_1,
1198         VEX_LEN_0F2D_P_3): Delete.
1199         (vex_len_table): Move vcvtsi2ss, vcvtsi2sd, vcvttss2si,
1200         vcvttsd2si, vcvtss2si, and vcvtsd2si leaf entries ...
1201         (prefix_table): ... here.
1202
1203 2019-06-27  Jan Beulich  <jbeulich@suse.com>
1204
1205         * i386-dis.c (Iq): Delete.
1206         (Id): New.
1207         (reg_table): Use it for lwpins, lwpval, and bextr. Use Edq for
1208         TBM insns.
1209         (vex_len_table): Use Edq for vcvtsi2ss, vcvtsi2sd. Use Gdq for
1210         vcvttss2si, vcvttsd2si, vcvtss2si, and vcvtsd2si.
1211         (OP_E_memory): Also honor needindex when deciding whether an
1212         address size prefix needs printing.
1213         (OP_I): Remove handling of q_mode. Add handling of d_mode.
1214
1215 2019-06-26  Jim Wilson  <jimw@sifive.com>
1216
1217         PR binutils/24739
1218         * riscv-dis.c (riscv_disasemble_insn): Set info->endian_code.
1219         Set info->display_endian to info->endian_code.
1220
1221 2019-06-25  Jan Beulich  <jbeulich@suse.com>
1222
1223         * i386-gen.c (operand_type_init): Correct OPERAND_TYPE_DEBUG
1224         entry. Drop OPERAND_TYPE_ACC entry. Add OPERAND_TYPE_ACC8 and
1225         OPERAND_TYPE_ACC16 entries. Adjust OPERAND_TYPE_ACC32 and
1226         OPERAND_TYPE_ACC64 entries.
1227         * i386-init.h: Re-generate.
1228
1229 2019-06-25  Jan Beulich  <jbeulich@suse.com>
1230
1231         * i386-dis.c (Edqa, dqa_mode, EVEX_W_0F2A_P_1, EVEX_W_0F7B_P_1):
1232         Delete.
1233         (intel_operand_size, OP_E_register, OP_E_memory): Drop handling
1234         of dqa_mode.
1235         * i386-dis-evex-prefix.h: Move vcvtsi2ss and vcvtusi2ss leaf
1236         entries here.
1237         * i386-dis-evex-w.h: Drop EVEX_W_0F2A_P_1 and EVEX_W_0F7B_P_1
1238         entries. Use Edq for vcvtsi2sd and vcvtusi2sd.
1239
1240 2019-06-25  Jan Beulich  <jbeulich@suse.com>
1241
1242         * i386-dis.c (OP_I64): Forword more cases to OP_I(). Drop local
1243         variables.
1244
1245 2019-06-25  Jan Beulich  <jbeulich@suse.com>
1246
1247         * i386-dis.c (prefix_table): Use Edq for cvtsi2ss and cvtsi2sd.
1248         Use Gdq for cvttss2si, cvttsd2si, cvtss2si, and cvtsd2si, and
1249         movnti.
1250         * i386-opc.tbl (movnti): Add IgnoreSize.
1251         * i386-tbl.h: Re-generate.
1252
1253 2019-06-25  Jan Beulich  <jbeulich@suse.com>
1254
1255         * i386-opc.tbl (and): Mark Imm8S form for optimization.
1256         * i386-tbl.h: Re-generate.
1257
1258 2019-06-21  H.J. Lu  <hongjiu.lu@intel.com>
1259
1260         * i386-dis-evex.h: Break into ...
1261         * i386-dis-evex-len.h: New file.
1262         * i386-dis-evex-mod.h: Likewise.
1263         * i386-dis-evex-prefix.h: Likewise.
1264         * i386-dis-evex-reg.h: Likewise.
1265         * i386-dis-evex-w.h: Likewise.
1266         * i386-dis.c: Include i386-dis-evex-reg.h, i386-dis-evex-prefix.h,
1267         i386-dis-evex.h, i386-dis-evex-len.h, i386-dis-evex-w.h and
1268         i386-dis-evex-mod.h.
1269
1270 2019-06-19  H.J. Lu  <hongjiu.lu@intel.com>
1271
1272         PR binutils/24700
1273         * i386-dis-evex.h (evex_table): Update EVEX_W_0F3819_P_2,
1274         EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2, EVEX_W_0F385A_P_2 and
1275         EVEX_W_0F385B_P_2.
1276         (evex_len_table): Add EVEX_LEN_0F3819_P_2_W_0,
1277         EVEX_LEN_0F3819_P_2_W_1, EVEX_LEN_0F381A_P_2_W_0,
1278         EVEX_LEN_0F381A_P_2_W_1, EVEX_LEN_0F381B_P_2_W_0,
1279         EVEX_LEN_0F381B_P_2_W_1, EVEX_LEN_0F385A_P_2_W_0,
1280         EVEX_LEN_0F385A_P_2_W_1, EVEX_LEN_0F385B_P_2_W_0 and
1281         EVEX_LEN_0F385B_P_2_W_1.
1282         * i386-dis.c (EVEX_LEN_0F3819_P_2_W_0): New enum.
1283         (EVEX_LEN_0F3819_P_2_W_1): Likewise.
1284         (EVEX_LEN_0F381A_P_2_W_0): Likewise.
1285         (EVEX_LEN_0F381A_P_2_W_1): Likewise.
1286         (EVEX_LEN_0F381B_P_2_W_0): Likewise.
1287         (EVEX_LEN_0F381B_P_2_W_1): Likewise.
1288         (EVEX_LEN_0F385A_P_2_W_0): Likewise.
1289         (EVEX_LEN_0F385A_P_2_W_1): Likewise.
1290         (EVEX_LEN_0F385B_P_2_W_0): Likewise.
1291         (EVEX_LEN_0F385B_P_2_W_1): Likewise.
1292
1293 2019-06-17  H.J. Lu  <hongjiu.lu@intel.com>
1294
1295         PR binutils/24691
1296         * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A23_P_2,
1297         EVEX_W_0F3A38_P_2, EVEX_W_0F3A39_P_2, EVEX_W_0F3A3A_P_2,
1298         EVEX_W_0F3A3B_P_2 and EVEX_W_0F3A43_P_2.
1299         (evex_len_table): Add EVEX_LEN_0F3A23_P_2_W_0,
1300         EVEX_LEN_0F3A23_P_2_W_1, EVEX_LEN_0F3A38_P_2_W_0,
1301         EVEX_LEN_0F3A38_P_2_W_1, EVEX_LEN_0F3A39_P_2_W_0,
1302         EVEX_LEN_0F3A39_P_2_W_1, EVEX_LEN_0F3A3A_P_2_W_0,
1303         EVEX_LEN_0F3A3A_P_2_W_1, EVEX_LEN_0F3A3B_P_2_W_0,
1304         EVEX_LEN_0F3A3B_P_2_W_1, EVEX_LEN_0F3A43_P_2_W_0 and
1305         EVEX_LEN_0F3A43_P_2_W_1.
1306         * i386-dis.c (EVEX_LEN_0F3A23_P_2_W_0): New enum.
1307         (EVEX_LEN_0F3A23_P_2_W_1): Likewise.
1308         (EVEX_LEN_0F3A38_P_2_W_0): Likewise.
1309         (EVEX_LEN_0F3A38_P_2_W_1): Likewise.
1310         (EVEX_LEN_0F3A39_P_2_W_0): Likewise.
1311         (EVEX_LEN_0F3A39_P_2_W_1): Likewise.
1312         (EVEX_LEN_0F3A3A_P_2_W_0): Likewise.
1313         (EVEX_LEN_0F3A3A_P_2_W_1): Likewise.
1314         (EVEX_LEN_0F3A3B_P_2_W_0): Likewise.
1315         (EVEX_LEN_0F3A3B_P_2_W_1): Likewise.
1316         (EVEX_LEN_0F3A43_P_2_W_0): Likewise.
1317         (EVEX_LEN_0F3A43_P_2_W_1): Likewise.
1318
1319 2019-06-14  Nick Clifton  <nickc@redhat.com>
1320
1321         * po/fr.po; Updated French translation.
1322
1323 2019-06-13  Stafford Horne  <shorne@gmail.com>
1324
1325         * or1k-asm.c: Regenerated.
1326         * or1k-desc.c: Regenerated.
1327         * or1k-desc.h: Regenerated.
1328         * or1k-dis.c: Regenerated.
1329         * or1k-ibld.c: Regenerated.
1330         * or1k-opc.c: Regenerated.
1331         * or1k-opc.h: Regenerated.
1332         * or1k-opinst.c: Regenerated.
1333
1334 2019-06-12  Peter Bergner  <bergner@linux.ibm.com>
1335
1336         * ppc-opc.c (powerpc_opcodes) <ldmx>: Delete mnemonic.
1337
1338 2019-06-05  H.J. Lu  <hongjiu.lu@intel.com>
1339
1340         PR binutils/24633
1341         * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A18_P_2,
1342         EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2 and EVEX_W_0F3A1B_P_2.
1343         (evex_len_table): EVEX_LEN_0F3A18_P_2_W_0,
1344         EVEX_LEN_0F3A18_P_2_W_1, EVEX_LEN_0F3A19_P_2_W_0,
1345         EVEX_LEN_0F3A19_P_2_W_1, EVEX_LEN_0F3A1A_P_2_W_0,
1346         EVEX_LEN_0F3A1A_P_2_W_1, EVEX_LEN_0F3A1B_P_2_W_0,
1347         EVEX_LEN_0F3A1B_P_2_W_1.
1348         * i386-dis.c (EVEX_LEN_0F3A18_P_2_W_0): New enum.
1349         (EVEX_LEN_0F3A18_P_2_W_1): Likewise.
1350         (EVEX_LEN_0F3A19_P_2_W_0): Likewise.
1351         (EVEX_LEN_0F3A19_P_2_W_1): Likewise.
1352         (EVEX_LEN_0F3A1A_P_2_W_0): Likewise.
1353         (EVEX_LEN_0F3A1A_P_2_W_1): Likewise.
1354         (EVEX_LEN_0F3A1B_P_2_W_0): Likewise.
1355         (EVEX_LEN_0F3A1B_P_2_W_1): Likewise.
1356
1357 2019-06-04  H.J. Lu  <hongjiu.lu@intel.com>
1358
1359         PR binutils/24626
1360         * i386-dis.c (print_insn): Check for unused VEX.vvvv and
1361         EVEX.vvvv when disassembling VEX and EVEX instructions.
1362         (OP_VEX): Set vex.register_specifier to 0 after readding
1363         vex.register_specifier.
1364         (OP_Vex_2src_1): Likewise.
1365         (OP_Vex_2src_2): Likewise.
1366         (OP_LWP_E): Likewise.
1367         (OP_EX_Vex): Don't check vex.register_specifier.
1368         (OP_XMM_Vex): Likewise.
1369
1370 2019-06-04  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
1371             Lili Cui  <lili.cui@intel.com>
1372
1373         * i386-dis.c (enum): Add PREFIX_EVEX_0F3868, EVEX_W_0F3868_P_3.
1374         * i386-dis-evex.h (evex_table): Add AVX512_VP2INTERSECT
1375         instructions.
1376         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VP2INTERSECT_FLAGS,
1377         CPU_ANY_AVX512_VP2INTERSECT_FLAGS.
1378         (cpu_flags): Add CpuAVX512_VP2INTERSECT.
1379         * i386-opc.h (enum): Add CpuAVX512_VP2INTERSECT.
1380         (i386_cpu_flags): Add cpuavx512_vp2intersect.
1381         * i386-opc.tbl: Add AVX512_VP2INTERSECT insns.
1382         * i386-init.h: Regenerated.
1383         * i386-tbl.h: Likewise.
1384
1385 2019-06-04  Xuepeng Guo  <xuepeng.guo@intel.com>
1386             Lili Cui  <lili.cui@intel.com>
1387
1388         * doc/c-i386.texi: Document enqcmd.
1389         * testsuite/gas/i386/enqcmd-intel.d: New file.
1390         * testsuite/gas/i386/enqcmd-inval.l: Likewise.
1391         * testsuite/gas/i386/enqcmd-inval.s: Likewise.
1392         * testsuite/gas/i386/enqcmd.d: Likewise.
1393         * testsuite/gas/i386/enqcmd.s: Likewise.
1394         * testsuite/gas/i386/x86-64-enqcmd-intel.d: Likewise.
1395         * testsuite/gas/i386/x86-64-enqcmd-inval.l: Likewise.
1396         * testsuite/gas/i386/x86-64-enqcmd-inval.s: Likewise.
1397         * testsuite/gas/i386/x86-64-enqcmd.d: Likewise.
1398         * testsuite/gas/i386/x86-64-enqcmd.s: Likewise.
1399         * testsuite/gas/i386/i386.exp: Run enqcmd-intel, enqcmd-inval,
1400         enqcmd, x86-64-enqcmd-intel, x86-64-enqcmd-inval,
1401         and x86-64-enqcmd.
1402
1403 2019-06-04  Alan Hayward  <alan.hayward@arm.com>
1404
1405         * arm-dis.c (is_mve_unpredictable): Remove spurious paranthesis.
1406
1407 2019-06-03  Alan Modra  <amodra@gmail.com>
1408
1409         * ppc-dis.c (prefix_opcd_indices): Correct size.
1410
1411 2019-05-28  H.J. Lu  <hongjiu.lu@intel.com>
1412
1413         PR gas/24625
1414         * i386-opc.tbl: Add CheckRegSize to AVX512_BF16 instructions with
1415         Disp8ShiftVL.
1416         * i386-tbl.h: Regenerated.
1417
1418 2019-05-24  Alan Modra  <amodra@gmail.com>
1419
1420         * po/POTFILES.in: Regenerate.
1421
1422 2019-05-24  Peter Bergner  <bergner@linux.ibm.com>
1423             Alan Modra  <amodra@gmail.com>
1424
1425         * ppc-opc.c (insert_d34, extract_d34, insert_nsi34, extract_nsi34),
1426         (insert_pcrel, extract_pcrel, extract_pcrel0): New functions.
1427         (extract_esync, extract_raq, extract_tbr, extract_sxl): Comment.
1428         (powerpc_operands <D34, SI34, NSI34, PRA0, PRAQ, PCREL, PCREL0,
1429         XTOP>): Define and add entries.
1430         (P8LS, PMLS, P_D_MASK, P_DRAPCREL_MASK): Define.
1431         (prefix_opcodes): Add pli, paddi, pla, psubi, plwz, plbz, pstw,
1432         pstb, plhz, plha, psth, plfs, plfd, pstfs, pstfd, plq, plxsd,
1433         plxssp, pld, plwa, pstxsd, pstxssp, pstxv, pstd, and pstq.
1434
1435 2019-05-24  Peter Bergner  <bergner@linux.ibm.com>
1436             Alan Modra  <amodra@gmail.com>
1437
1438         * ppc-dis.c (ppc_opts): Add "future" entry.
1439         (PREFIX_OPCD_SEGS): Define.
1440         (prefix_opcd_indices): New array.
1441         (disassemble_init_powerpc): Initialize prefix_opcd_indices.
1442         (lookup_prefix): New function.
1443         (print_insn_powerpc): Handle 64-bit prefix instructions.
1444         * ppc-opc.c (PREFIX_OP, PREFIX_FORM, SUFFIX_MASK, PREFIX_MASK),
1445         (PMRR, POWERXX): Define.
1446         (prefix_opcodes): New instruction table.
1447         (prefix_num_opcodes): New constant.
1448
1449 2019-05-23  Jose E. Marchesi  <jose.marchesi@oracle.com>
1450
1451         * configure.ac (SHARED_DEPENDENCIES): Add case for bfd_bpf_arch.
1452         * configure: Regenerated.
1453         * Makefile.am: Add rules for the files generated from cpu/bpf.cpu
1454         and cpu/bpf.opc.
1455         (HFILES): Add bpf-desc.h and bpf-opc.h.
1456         (TARGET_LIBOPCODES_CFILES): Add bpf-asm.c, bpf-desc.c, bpf-dis.c,
1457         bpf-ibld.c and bpf-opc.c.
1458         (BPF_DEPS): Define.
1459         * Makefile.in: Regenerated.
1460         * disassemble.c (ARCH_bpf): Define.
1461         (disassembler): Add case for bfd_arch_bpf.
1462         (disassemble_init_for_target): Likewise.
1463         (enum epbf_isa_attr): Define.
1464         * disassemble.h: extern print_insn_bpf.
1465         * bpf-asm.c: Generated.
1466         * bpf-opc.h: Likewise.
1467         * bpf-opc.c: Likewise.
1468         * bpf-ibld.c: Likewise.
1469         * bpf-dis.c: Likewise.
1470         * bpf-desc.h: Likewise.
1471         * bpf-desc.c: Likewise.
1472
1473 2019-05-21  Sudakshina Das  <sudi.das@arm.com>
1474
1475         * arm-dis.c (coprocessor_opcodes): New instructions for VMRS
1476         and VMSR with the new operands.
1477
1478 2019-05-21  Sudakshina Das  <sudi.das@arm.com>
1479
1480         * arm-dis.c (enum mve_instructions): New enum
1481         for csinc, csinv, csneg, csel, cset, csetm, cinv, cinv
1482         and cneg.
1483         (mve_opcodes): New instructions as above.
1484         (is_mve_encoding_conflict): Add cases for csinc, csinv,
1485         csneg and csel.
1486         (print_insn_mve): Accept new %<bitfield>c and %<bitfield>C.
1487
1488 2019-05-21  Sudakshina Das  <sudi.das@arm.com>
1489
1490         * arm-dis.c (emun mve_instructions): Updated for new instructions.
1491         (mve_opcodes): New instructions for asrl, lsll, lsrl, sqrshrl,
1492         sqrshr, sqshl, sqshll, srshr, srshrl, uqrshll, uqrshl, uqshll,
1493         uqshl, urshrl and urshr.
1494         (is_mve_okay_in_it): Add new instructions to TRUE list.
1495         (is_mve_unpredictable): Add cases for UNPRED_R13 and UNPRED_R15.
1496         (print_insn_mve): Updated to accept new %j,
1497         %<bitfield>m and %<bitfield>n patterns.
1498
1499 2019-05-21  Faraz Shahbazker  <fshahbazker@wavecomp.com>
1500
1501         * mips-opc.c (mips_builtin_opcodes): Change source register
1502         constraint for DAUI.
1503
1504 2019-05-20  Nick Clifton  <nickc@redhat.com>
1505
1506         * po/fr.po: Updated French translation.
1507
1508 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1509             Michael Collison <michael.collison@arm.com>
1510
1511         * arm-dis.c (thumb32_opcodes): Add new instructions.
1512         (enum mve_instructions): Likewise.
1513         (enum mve_undefined): Add new reasons.
1514         (is_mve_encoding_conflict): Handle new instructions.
1515         (is_mve_undefined): Likewise.
1516         (is_mve_unpredictable): Likewise.
1517         (print_mve_undefined): Likewise.
1518         (print_mve_size): Likewise.
1519
1520 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1521             Michael Collison <michael.collison@arm.com>
1522
1523         * arm-dis.c (thumb32_opcodes): Add new instructions.
1524         (enum mve_instructions): Likewise.
1525         (is_mve_encoding_conflict): Handle new instructions.
1526         (is_mve_undefined): Likewise.
1527         (is_mve_unpredictable): Likewise.
1528         (print_mve_size): Likewise.
1529
1530 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1531             Michael Collison <michael.collison@arm.com>
1532
1533         * arm-dis.c (thumb32_opcodes): Add new instructions.
1534         (enum mve_instructions): Likewise.
1535         (is_mve_encoding_conflict): Likewise.
1536         (is_mve_unpredictable): Likewise.
1537         (print_mve_size): Likewise.
1538
1539 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1540             Michael Collison <michael.collison@arm.com>
1541
1542         * arm-dis.c (thumb32_opcodes): Add new instructions.
1543         (enum mve_instructions): Likewise.
1544         (is_mve_encoding_conflict): Handle new instructions.
1545         (is_mve_undefined): Likewise.
1546         (is_mve_unpredictable): Likewise.
1547         (print_mve_size): Likewise.
1548
1549 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1550             Michael Collison <michael.collison@arm.com>
1551
1552         * arm-dis.c (thumb32_opcodes): Add new instructions.
1553         (enum mve_instructions): Likewise.
1554         (is_mve_encoding_conflict): Handle new instructions.
1555         (is_mve_undefined): Likewise.
1556         (is_mve_unpredictable): Likewise.
1557         (print_mve_size): Likewise.
1558         (print_insn_mve): Likewise.
1559
1560 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1561             Michael Collison <michael.collison@arm.com>
1562
1563         * arm-dis.c (thumb32_opcodes): Add new instructions.
1564         (print_insn_thumb32): Handle new instructions.
1565
1566 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1567             Michael Collison <michael.collison@arm.com>
1568
1569         * arm-dis.c (enum mve_instructions): Add new instructions.
1570         (enum mve_undefined): Add new reasons.
1571         (is_mve_encoding_conflict): Handle new instructions.
1572         (is_mve_undefined): Likewise.
1573         (is_mve_unpredictable): Likewise.
1574         (print_mve_undefined): Likewise.
1575         (print_mve_size): Likewise.
1576         (print_mve_shift_n): Likewise.
1577         (print_insn_mve): Likewise.
1578
1579 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1580             Michael Collison <michael.collison@arm.com>
1581
1582         * arm-dis.c (enum mve_instructions): Add new instructions.
1583         (is_mve_encoding_conflict): Handle new instructions.
1584         (is_mve_unpredictable): Likewise.
1585         (print_mve_rotate): Likewise.
1586         (print_mve_size): Likewise.
1587         (print_insn_mve): Likewise.
1588
1589 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1590             Michael Collison <michael.collison@arm.com>
1591
1592         * arm-dis.c (enum mve_instructions): Add new instructions.
1593         (is_mve_encoding_conflict): Handle new instructions.
1594         (is_mve_unpredictable): Likewise.
1595         (print_mve_size): Likewise.
1596         (print_insn_mve): Likewise.
1597
1598 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1599             Michael Collison <michael.collison@arm.com>
1600
1601         * arm-dis.c (enum mve_instructions): Add new instructions.
1602         (enum mve_undefined): Add new reasons.
1603         (is_mve_encoding_conflict): Handle new instructions.
1604         (is_mve_undefined): Likewise.
1605         (is_mve_unpredictable): Likewise.
1606         (print_mve_undefined): Likewise.
1607         (print_mve_size): Likewise.
1608         (print_insn_mve): Likewise.
1609
1610 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1611             Michael Collison <michael.collison@arm.com>
1612
1613         * arm-dis.c (enum mve_instructions): Add new instructions.
1614         (is_mve_encoding_conflict): Handle new instructions.
1615         (is_mve_undefined): Likewise.
1616         (is_mve_unpredictable): Likewise.
1617         (print_mve_size): Likewise.
1618         (print_insn_mve): Likewise.
1619
1620 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1621             Michael Collison <michael.collison@arm.com>
1622
1623         * arm-dis.c (enum mve_instructions): Add new instructions.
1624         (enum mve_unpredictable): Add new reasons.
1625         (enum mve_undefined): Likewise.
1626         (is_mve_okay_in_it): Handle new isntructions.
1627         (is_mve_encoding_conflict): Likewise.
1628         (is_mve_undefined): Likewise.
1629         (is_mve_unpredictable): Likewise.
1630         (print_mve_vmov_index): Likewise.
1631         (print_simd_imm8): Likewise.
1632         (print_mve_undefined): Likewise.
1633         (print_mve_unpredictable): Likewise.
1634         (print_mve_size): Likewise.
1635         (print_insn_mve): Likewise.
1636
1637 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1638             Michael Collison <michael.collison@arm.com>
1639
1640         * arm-dis.c (enum mve_instructions): Add new instructions.
1641         (enum mve_unpredictable): Add new reasons.
1642         (enum mve_undefined): Likewise.
1643         (is_mve_encoding_conflict): Handle new instructions.
1644         (is_mve_undefined): Likewise.
1645         (is_mve_unpredictable): Likewise.
1646         (print_mve_undefined): Likewise.
1647         (print_mve_unpredictable): Likewise.
1648         (print_mve_rounding_mode): Likewise.
1649         (print_mve_vcvt_size): Likewise.
1650         (print_mve_size): Likewise.
1651         (print_insn_mve): Likewise.
1652
1653 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1654             Michael Collison <michael.collison@arm.com>
1655
1656         * arm-dis.c (enum mve_instructions): Add new instructions.
1657         (enum mve_unpredictable): Add new reasons.
1658         (enum mve_undefined): Likewise.
1659         (is_mve_undefined): Handle new instructions.
1660         (is_mve_unpredictable): Likewise.
1661         (print_mve_undefined): Likewise.
1662         (print_mve_unpredictable): Likewise.
1663         (print_mve_size): Likewise.
1664         (print_insn_mve): Likewise.
1665
1666 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1667             Michael Collison <michael.collison@arm.com>
1668
1669         * arm-dis.c (enum mve_instructions): Add new instructions.
1670         (enum mve_undefined): Add new reasons.
1671         (insns): Add new instructions.
1672         (is_mve_encoding_conflict):
1673         (print_mve_vld_str_addr): New print function.
1674         (is_mve_undefined): Handle new instructions.
1675         (is_mve_unpredictable): Likewise.
1676         (print_mve_undefined): Likewise.
1677         (print_mve_size): Likewise.
1678         (print_insn_coprocessor_1): Handle MVE VLDR, VSTR instructions.
1679         (print_insn_mve):  Handle new operands.
1680
1681 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1682             Michael Collison <michael.collison@arm.com>
1683
1684         * arm-dis.c (enum mve_instructions): Add new instructions.
1685         (enum mve_unpredictable): Add new reasons.
1686         (is_mve_encoding_conflict): Handle new instructions.
1687         (is_mve_unpredictable): Likewise.
1688         (mve_opcodes): Add new instructions.
1689         (print_mve_unpredictable): Handle new reasons.
1690         (print_mve_register_blocks): New print function.
1691         (print_mve_size): Handle new instructions.
1692         (print_insn_mve): Likewise.
1693
1694 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1695             Michael Collison <michael.collison@arm.com>
1696
1697         * arm-dis.c (enum mve_instructions): Add new instructions.
1698         (enum mve_unpredictable): Add new reasons.
1699         (enum mve_undefined): Likewise.
1700         (is_mve_encoding_conflict): Handle new instructions.
1701         (is_mve_undefined): Likewise.
1702         (is_mve_unpredictable): Likewise.
1703         (coprocessor_opcodes): Move NEON VDUP from here...
1704         (neon_opcodes): ... to here.
1705         (mve_opcodes): Add new instructions.
1706         (print_mve_undefined):  Handle new reasons.
1707         (print_mve_unpredictable): Likewise.
1708         (print_mve_size): Handle new instructions.
1709         (print_insn_neon): Handle vdup.
1710         (print_insn_mve): Handle new operands.
1711
1712 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1713             Michael Collison <michael.collison@arm.com>
1714
1715         * arm-dis.c (enum mve_instructions): Add new instructions.
1716         (enum mve_unpredictable): Add new values.
1717         (mve_opcodes): Add new instructions.
1718         (vec_condnames): New array with vector conditions.
1719         (mve_predicatenames): New array with predicate suffixes.
1720         (mve_vec_sizename): New array with vector sizes.
1721         (enum vpt_pred_state): New enum with vector predication states.
1722         (struct vpt_block): New struct type for vpt blocks.
1723         (vpt_block_state): Global struct to keep track of state.
1724         (mve_extract_pred_mask): New helper function.
1725         (num_instructions_vpt_block): Likewise.
1726         (mark_outside_vpt_block): Likewise.
1727         (mark_inside_vpt_block): Likewise.
1728         (invert_next_predicate_state): Likewise.
1729         (update_next_predicate_state): Likewise.
1730         (update_vpt_block_state): Likewise.
1731         (is_vpt_instruction): Likewise.
1732         (is_mve_encoding_conflict): Add entries for new instructions.
1733         (is_mve_unpredictable): Likewise.
1734         (print_mve_unpredictable): Handle new cases.
1735         (print_instruction_predicate): Likewise.
1736         (print_mve_size): New function.
1737         (print_vec_condition): New function.
1738         (print_insn_mve): Handle vpt blocks and new print operands.
1739
1740 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1741
1742         * arm-dis.c (print_insn_coprocessor_1): Disable the use of coprocessors
1743         8, 14 and 15 for Armv8.1-M Mainline.
1744
1745 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1746             Michael Collison <michael.collison@arm.com>
1747
1748         * arm-dis.c (enum mve_instructions): New enum.
1749         (enum mve_unpredictable): Likewise.
1750         (enum mve_undefined): Likewise.
1751         (struct mopcode32): New struct.
1752         (is_mve_okay_in_it): New function.
1753         (is_mve_architecture): Likewise.
1754         (arm_decode_field): Likewise.
1755         (arm_decode_field_multiple): Likewise.
1756         (is_mve_encoding_conflict): Likewise.
1757         (is_mve_undefined): Likewise.
1758         (is_mve_unpredictable): Likewise.
1759         (print_mve_undefined): Likewise.
1760         (print_mve_unpredictable): Likewise.
1761         (print_insn_coprocessor_1): Use arm_decode_field_multiple.
1762         (print_insn_mve): New function.
1763         (print_insn_thumb32): Handle MVE architecture.
1764         (select_arm_features): Force thumb for Armv8.1-m Mainline.
1765
1766 2019-05-10  Nick Clifton  <nickc@redhat.com>
1767
1768         PR 24538
1769         * ia64-opc.c (ia64_find_matching_opcode): Check for reaching the
1770         end of the table prematurely.
1771
1772 2019-05-10  Faraz Shahbazker  <fshahbazker@wavecomp.com>
1773
1774         * mips-opc.c (mips_opcodes): Enable ADD, SUB, DADD and DSUB
1775         macros for R6.
1776
1777 2019-05-11  Alan Modra  <amodra@gmail.com>
1778
1779         * ppc-dis.c (print_insn_powerpc) Don't skip optional operands
1780         when -Mraw is in effect.
1781
1782 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1783
1784         * aarch64-dis-2.c: Regenerate.
1785         * aarch64-tbl.h (OP_SVE_BBU): New variant set.
1786         (OP_SVE_BBB): New variant set.
1787         (OP_SVE_DDDD): New variant set.
1788         (OP_SVE_HHH): New variant set.
1789         (OP_SVE_HHHU): New variant set.
1790         (OP_SVE_SSS): New variant set.
1791         (OP_SVE_SSSU): New variant set.
1792         (OP_SVE_SHH): New variant set.
1793         (OP_SVE_SBBU): New variant set.
1794         (OP_SVE_DSS): New variant set.
1795         (OP_SVE_DHHU): New variant set.
1796         (OP_SVE_VMV_HSD_BHS): New variant set.
1797         (OP_SVE_VVU_HSD_BHS): New variant set.
1798         (OP_SVE_VVVU_SD_BH): New variant set.
1799         (OP_SVE_VVVU_BHSD): New variant set.
1800         (OP_SVE_VVV_QHD_DBS): New variant set.
1801         (OP_SVE_VVV_HSD_BHS): New variant set.
1802         (OP_SVE_VVV_HSD_BHS2): New variant set.
1803         (OP_SVE_VVV_BHS_HSD): New variant set.
1804         (OP_SVE_VV_BHS_HSD): New variant set.
1805         (OP_SVE_VVV_SD): New variant set.
1806         (OP_SVE_VVU_BHS_HSD): New variant set.
1807         (OP_SVE_VZVV_SD): New variant set.
1808         (OP_SVE_VZVV_BH): New variant set.
1809         (OP_SVE_VZV_SD): New variant set.
1810         (aarch64_opcode_table): Add sve2 instructions.
1811
1812 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1813
1814         * aarch64-asm-2.c: Regenerated.
1815         * aarch64-dis-2.c: Regenerated.
1816         * aarch64-opc-2.c: Regenerated.
1817         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1818         for SVE_SHLIMM_UNPRED_22.
1819         (aarch64_print_operand): Add printing for SVE_SHLIMM_UNPRED_22.
1820         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHLIMM_UNPRED_22
1821         operand.
1822
1823 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1824
1825         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1826         sve_size_tsz_bhs iclass encode.
1827         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1828         sve_size_tsz_bhs iclass decode.
1829
1830 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1831
1832         * aarch64-asm-2.c: Regenerated.
1833         * aarch64-dis-2.c: Regenerated.
1834         * aarch64-opc-2.c: Regenerated.
1835         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1836         for SVE_Zm4_11_INDEX.
1837         (aarch64_print_operand): Add printing for SVE_Zm4_11_INDEX.
1838         (fields): Handle SVE_i2h field.
1839         * aarch64-opc.h (enum aarch64_field_kind): New SVE_i2h field.
1840         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm4_11_INDEX operand.
1841
1842 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1843
1844         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1845         sve_shift_tsz_bhsd iclass encode.
1846         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1847         sve_shift_tsz_bhsd iclass decode.
1848
1849 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1850
1851         * aarch64-asm-2.c: Regenerated.
1852         * aarch64-dis-2.c: Regenerated.
1853         * aarch64-opc-2.c: Regenerated.
1854         * aarch64-asm.c (aarch64_ins_sve_shrimm):
1855         (aarch64_encode_variant_using_iclass): Handle
1856         sve_shift_tsz_hsd iclass encode.
1857         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1858         sve_shift_tsz_hsd iclass decode.
1859         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1860         for SVE_SHRIMM_UNPRED_22.
1861         (aarch64_print_operand): Add printing for SVE_SHRIMM_UNPRED_22.
1862         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHRIMM_UNPRED_22
1863         operand.
1864
1865 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1866
1867         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1868         sve_size_013 iclass encode.
1869         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1870         sve_size_013 iclass decode.
1871
1872 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1873
1874         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1875         sve_size_bh iclass encode.
1876         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1877         sve_size_bh iclass decode.
1878
1879 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1880
1881         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1882         sve_size_sd2 iclass encode.
1883         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1884         sve_size_sd2 iclass decode.
1885         * aarch64-opc.c (fields): Handle SVE_sz2 field.
1886         * aarch64-opc.h (enum aarch64_field_kind): New SVE_sz2 field.
1887
1888 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1889
1890         * aarch64-asm-2.c: Regenerated.
1891         * aarch64-dis-2.c: Regenerated.
1892         * aarch64-opc-2.c: Regenerated.
1893         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1894         for SVE_ADDR_ZX.
1895         (aarch64_print_operand): Add printing for SVE_ADDR_ZX.
1896         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_ADDR_ZX operand.
1897
1898 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1899
1900         * aarch64-asm-2.c: Regenerated.
1901         * aarch64-dis-2.c: Regenerated.
1902         * aarch64-opc-2.c: Regenerated.
1903         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1904         for SVE_Zm3_11_INDEX.
1905         (aarch64_print_operand): Add printing for SVE_Zm3_11_INDEX.
1906         (fields): Handle SVE_i3l and SVE_i3h2 fields.
1907         * aarch64-opc.h (enum aarch64_field_kind): New SVE_i3l and SVE_i3h2
1908         fields.
1909         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm3_11_INDEX operand.
1910
1911 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1912
1913         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1914         sve_size_hsd2 iclass encode.
1915         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1916         sve_size_hsd2 iclass decode.
1917         * aarch64-opc.c (fields): Handle SVE_size field.
1918         * aarch64-opc.h (enum aarch64_field_kind): New SVE_size field.
1919
1920 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1921
1922         * aarch64-asm-2.c: Regenerated.
1923         * aarch64-dis-2.c: Regenerated.
1924         * aarch64-opc-2.c: Regenerated.
1925         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1926         for SVE_IMM_ROT3.
1927         (aarch64_print_operand): Add printing for SVE_IMM_ROT3.
1928         (fields): Handle SVE_rot3 field.
1929         * aarch64-opc.h (enum aarch64_field_kind): New SVE_rot3 field.
1930         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_IMM_ROT3 operand.
1931
1932 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1933
1934         * aarch64-opc.c (verify_constraints): Check for movprfx for sve2
1935         instructions.
1936
1937 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1938
1939         * aarch64-tbl.h
1940         (aarch64_feature_sve2, aarch64_feature_sve2aes,
1941         aarch64_feature_sve2sha3, aarch64_feature_sve2sm4,
1942         aarch64_feature_sve2bitperm): New feature sets.
1943         (SVE2, SVE2_AES, SVE2_SHA3, SVE2_SM4, SVE2_BITPERM): New macros
1944         for feature set addresses.
1945         (SVE2_INSN, SVE2_INSNC, SVE2AES_INSN, SVE2SHA3_INSN,
1946         SVE2SM4_INSN, SVE2SM4_INSNC, SVE2BITPERM_INSN): New macros.
1947
1948 2019-05-06  Andrew Bennett  <andrew.bennett@imgtec.com>
1949             Faraz Shahbazker  <fshahbazker@wavecomp.com>
1950
1951         * mips-dis.c (mips_calculate_combination_ases): Add ISA
1952         argument and set ASE_EVA_R6 appropriately.
1953         (set_default_mips_dis_options): Pass ISA to above.
1954         (parse_mips_dis_option): Likewise.
1955         * mips-opc.c (EVAR6): New macro.
1956         (mips_builtin_opcodes): Add llwpe, scwpe.
1957
1958 2019-05-01  Sudakshina Das  <sudi.das@arm.com>
1959
1960         * aarch64-asm-2.c: Regenerated.
1961         * aarch64-dis-2.c: Regenerated.
1962         * aarch64-opc-2.c: Regenerated.
1963         * aarch64-opc.c (operand_general_constraint_met_p): Add case for
1964         AARCH64_OPND_TME_UIMM16.
1965         (aarch64_print_operand): Likewise.
1966         * aarch64-tbl.h (QL_IMM_NIL): New.
1967         (TME): New.
1968         (_TME_INSN): New.
1969         (struct aarch64_opcode): Add tstart, tcommit, ttest and tcancel.
1970
1971 2019-04-29  John Darrington  <john@darrington.wattle.id.au>
1972
1973         * s12z-opc.c (shift_discrim): Return OP_INVALID when reading fails.
1974
1975 2019-04-26  Andrew Bennett  <andrew.bennett@imgtec.com>
1976             Faraz Shahbazker  <fshahbazker@wavecomp.com>
1977
1978         * mips-opc.c (mips_builtin_opcodes): Add llwp, lldp, scwp, scdp.
1979
1980 2019-04-24  John Darrington  <john@darrington.wattle.id.au>
1981
1982         * s12z-opc.h: Add extern "C" bracketing to help
1983         users who wish to use this interface in c++ code.
1984
1985 2019-04-24  John Darrington  <john@darrington.wattle.id.au>
1986
1987         * s12z-opc.c (bm_decode): Handle bit map operations with the
1988         "reserved0" mode.
1989
1990 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1991
1992         * arm-dis.c (coprocessor_opcodes): Document new %J and %K format
1993         specifier.  Add entries for VLDR and VSTR of system registers.
1994         (print_insn_coprocessor): Forbid coprocessor numbers 8, 14 and 15 in
1995         coprocessor instructions on Armv8.1-M Mainline targets.  Add handling
1996         of %J and %K format specifier.
1997
1998 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1999
2000         * arm-dis.c (coprocessor_opcodes): Document new %C format control code.
2001         Add new entries for VSCCLRM instruction.
2002         (print_insn_coprocessor): Handle new %C format control code.
2003
2004 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
2005
2006         * arm-dis.c (enum isa): New enum.
2007         (struct sopcode32): New structure.
2008         (coprocessor_opcodes): change type of entries to struct sopcode32 and
2009         set isa field of all current entries to ANY.
2010         (print_insn_coprocessor): Change type of insn to struct sopcode32.
2011         Only match an entry if its isa field allows the current mode.
2012
2013 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
2014
2015         * arm-dis.c (thumb_opcodes): Document %n control code.  Add entry for
2016         CLRM.
2017         (print_insn_thumb32): Add logic to print %n CLRM register list.
2018
2019 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
2020
2021         * arm-dis.c (print_insn_thumb32): Updated to accept new %P
2022         and %Q patterns.
2023
2024 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
2025
2026         * arm-dis.c (thumb32_opcodes): New instruction bfcsel.
2027         (print_insn_thumb32): Edit the switch case for %Z.
2028
2029 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
2030
2031         * arm-dis.c (print_insn_thumb32): Updated to accept new %Z pattern.
2032
2033 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
2034
2035         * arm-dis.c (thumb32_opcodes): New instruction bfl.
2036
2037 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
2038
2039         * arm-dis.c (print_insn_thumb32): Updated to accept new %Y pattern.
2040
2041 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
2042
2043         * arm-dis.c (print_insn_thumb32): Add '%<bitfield>S' to print an
2044         Arm register with r13 and r15 unpredictable.
2045         (thumb32_opcodes): New instructions for bfx and bflx.
2046
2047 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
2048
2049         * arm-dis.c (thumb32_opcodes): New instructions for bf.
2050
2051 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
2052
2053         * arm-dis.c (print_insn_thumb32): Updated to accept new %W pattern.
2054
2055 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
2056
2057         * arm-dis.c (print_insn_thumb32): Updated to accept new %G pattern.
2058
2059 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
2060
2061         * arm-dis.c (select_arm_features): Add logic for Armv8.1-M Mainline.
2062
2063 2019-04-12  John Darrington <john@darrington.wattle.id.au>
2064
2065         s12z-dis.c, s12z-opc.c, s12z-opc.h: Replace "operator" with
2066         "optr". ("operator" is a reserved word in c++).
2067
2068 2019-04-11  Sudakshina Das  <sudi.das@arm.com>
2069
2070         * aarch64-opc.c (aarch64_print_operand): Add case for
2071         AARCH64_OPND_Rt_SP.
2072         (verify_constraints): Likewise.
2073         * aarch64-tbl.h (QL_LDST_AT): Update to add SP qualifier.
2074         (struct aarch64_opcode): Update stg, stzg, st2g, stz2g instructions
2075         to accept Rt|SP as first operand.
2076         (AARCH64_OPERANDS): Add new Rt_SP.
2077         * aarch64-asm-2.c: Regenerated.
2078         * aarch64-dis-2.c: Regenerated.
2079         * aarch64-opc-2.c: Regenerated.
2080
2081 2019-04-11  Sudakshina Das  <sudi.das@arm.com>
2082
2083         * aarch64-asm-2.c: Regenerated.
2084         * aarch64-dis-2.c: Likewise.
2085         * aarch64-opc-2.c: Likewise.
2086         * aarch64-tbl.h (aarch64_opcode): Add new ldgm and stgm.
2087
2088 2019-04-09  Robert Suchanek  <robert.suchanek@mips.com>
2089
2090         * mips-opc.c (mips_builtin_opcodes): Add RDHWR rt rd sel.
2091
2092 2019-04-08  H.J. Lu  <hongjiu.lu@intel.com>
2093
2094         * i386-opc.tbl: Consolidate AVX512 BF16 entries.
2095         * i386-init.h: Regenerated.
2096
2097 2019-04-07  Alan Modra  <amodra@gmail.com>
2098
2099         * ppc-dis.c (print_insn_powerpc): Use a tiny state machine
2100         op_separator to control printing of spaces, comma and parens
2101         rather than need_comma, need_paren and spaces vars.
2102
2103 2019-04-07  Alan Modra  <amodra@gmail.com>
2104
2105         PR 24421
2106         * arm-dis.c (print_insn_coprocessor): Correct bracket placement.
2107         (print_insn_neon, print_insn_arm): Likewise.
2108
2109 2019-04-05  Xuepeng Guo  <xuepeng.guo@intel.com>
2110
2111         * i386-dis-evex.h (evex_table): Updated to support BF16
2112         instructions.
2113         * i386-dis.c (enum): Add EVEX_W_0F3852_P_1, EVEX_W_0F3872_P_1
2114         and EVEX_W_0F3872_P_3.
2115         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_BF16_FLAGS.
2116         (cpu_flags): Add bitfield for CpuAVX512_BF16.
2117         * i386-opc.h (enum): Add CpuAVX512_BF16.
2118         (i386_cpu_flags): Add bitfield for cpuavx512_bf16.
2119         * i386-opc.tbl: Add AVX512 BF16 instructions.
2120         * i386-init.h: Regenerated.
2121         * i386-tbl.h: Likewise.
2122
2123 2019-04-05  Alan Modra  <amodra@gmail.com>
2124
2125         * ppc-opc.c (XLBH_MASK): Subtract off BH field from BB_MASK.
2126         (powerpc_opcodes): Reorder bcctr and bclr extended mnemonics
2127         to favour printing of "-" branch hint when using the "y" bit.
2128         Allow BH field on bc{ctr,lr,tar}{,l}{-,+}.
2129
2130 2019-04-05  Alan Modra  <amodra@gmail.com>
2131
2132         * ppc-dis.c (print_insn_powerpc): Delay printing spaces after
2133         opcode until first operand is output.
2134
2135 2019-04-04  Peter Bergner  <bergner@linux.ibm.com>
2136
2137         PR gas/24349
2138         * ppc-opc.c (valid_bo_pre_v2): Add comments.
2139         (valid_bo_post_v2): Add support for 'at' branch hints.
2140         (insert_bo): Only error on branch on ctr.
2141         (get_bo_hint_mask): New function.
2142         (insert_boe): Add new 'branch_taken' formal argument.  Add support
2143         for inserting 'at' branch hints.
2144         (extract_boe): Add new 'branch_taken' formal argument.  Add support
2145         for extracting 'at' branch hints.
2146         (insert_bom, extract_bom, insert_bop, extract_bop): New functions.
2147         (BOE): Delete operand.
2148         (BOM, BOP): New operands.
2149         (RM): Update value.
2150         (XLYLK, XLYLK_MASK, XLYBB_MASK): Delete.
2151         (powerpc_opcodes) <bc-, bcl-, bca-, bcla-, bclr-, bclrl-, bcctr-,
2152         bcctrl-, bctar-, bctarl->: Replace BOE with BOM.
2153         (powerpc_opcodes) <bc+, bcl+, bca+, bcla+, bclr+, bclrl+, bcctr+,
2154         bcctrl+, bctar+, bctarl+>: Replace BOE with BOP.
2155         <bdnztar, bdnztarl, bdztar, bdztarl, btar, btarl, bdnztar-, bdnztarl-,
2156         bdnztar+, bdnztarl+, bdztar-, bdztarl-, bdztar+, bdztarl+, bgetar,
2157         bnltar, bgetarl, bnltarl, bletar, bngtar, bletarl, bngtarl, bnetar,
2158         bnetarl, bnstar, bnutar, bnstarl, bnutarl, bgetar-, bnltar-, bgetarl-,
2159         bnltarl-, bletar-, bngtar-, bletarl-, bngtarl-, bnetar-, bnetarl-,
2160         bnstar-, bnutar-, bnstarl-, bnutarl-, bgetar+, bnltar+, bgetarl+,
2161         bnltarl+, bletar+, bngtar+, bletarl+, bngtarl+, bnetar+, bnetarl+,
2162         bnstar+, bnutar+, bnstarl+, bnutarl+, blttar, blttarl, bgttar, bgttarl,
2163         beqtar, beqtarl, bsotar, buntar, bsotarl, buntarl, blttar-, blttarl-,
2164         bgttar-, bgttarl-, beqtar-, beqtarl-, bsotar-, buntar-, bsotarl-,
2165         buntarl-, blttar+, blttarl+, bgttar+, bgttarl+, beqtar+, beqtarl+,
2166         bsotar+, buntar+, bsotarl+, buntarl+, bdnzftar, bdnzftarl, bdzftar,
2167         bdzftarl, bftar, bftarl, bftar-, bftarl-, bftar+, bftarl+, bdnzttar,
2168         bdnzttarl, bdzttar, bdzttarl, bttar, bttarl, bttar-, bttarl-, bttar+,
2169         bttarl+>: New extended mnemonics.
2170
2171 2019-03-28  Alan Modra  <amodra@gmail.com>
2172
2173         PR 24390
2174         * ppc-opc.c (BTF): Define.
2175         (powerpc_opcodes): Use for mtfsb*.
2176         * ppc-dis.c (print_insn_powerpc): Print fields with both
2177         PPC_OPERAND_CR_REG and PPC_OPERAND_CR_BIT as a plain number.
2178
2179 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
2180
2181         * arm-dis.c (struct arm_private_data): Remove has_mapping_symbols.
2182         (mapping_symbol_for_insn): Implement new algorithm.
2183         (print_insn): Remove duplicate code.
2184
2185 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
2186
2187         * aarch64-dis.c (print_insn_aarch64):
2188         Implement override.
2189
2190 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
2191
2192         * aarch64-dis.c (print_insn_aarch64): Update the mapping symbol search
2193         order.
2194
2195 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
2196
2197         * aarch64-dis.c (last_stop_offset): New.
2198         (print_insn_aarch64): Use stop_offset.
2199
2200 2019-03-19  H.J. Lu  <hongjiu.lu@intel.com>
2201
2202         PR gas/24359
2203         * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS to
2204         CPU_ANY_AVX2_FLAGS.
2205         * i386-init.h: Regenerated.
2206
2207 2019-03-18  H.J. Lu  <hongjiu.lu@intel.com>
2208
2209         PR gas/24348
2210         * i386-opc.tbl: Add Optimize to vmovdqa32, vmovdqa64, vmovdqu8,
2211         vmovdqu16, vmovdqu32 and vmovdqu64.
2212         * i386-tbl.h: Regenerated.
2213
2214 2019-03-12  Andreas Krebbel  <krebbel@linux.ibm.com>
2215
2216         * s390-opc.txt: Rename selhhhr to selfhr.  Remove optional operand
2217         from vstrszb, vstrszh, and vstrszf.
2218
2219 2019-03-12  Andreas Krebbel  <krebbel@linux.ibm.com>
2220
2221         * s390-opc.txt: Add instruction descriptions.
2222
2223 2019-02-08  Jim Wilson  <jimw@sifive.com>
2224
2225         * riscv-opc.c (riscv_opcodes) <beq>: Use Cz to compress 3 operand form.
2226         <bne>: Likewise.
2227
2228 2019-02-07  Tamar Christina  <tamar.christina@arm.com>
2229
2230         * arm-dis.c (arm_opcodes): Redefine hlt to armv1.
2231
2232 2019-02-07  Tamar Christina  <tamar.christina@arm.com>
2233
2234         PR binutils/23212
2235         * aarch64-opc.h (enum aarch64_field_kind): Add FLD_sz.
2236         * aarch64-opc.c (verify_elem_sd): New.
2237         (fields): Add FLD_sz entr.
2238         * aarch64-tbl.h (_SIMD_INSN): New.
2239         (aarch64_opcode_table): Add elem_sd verifier to fmla, fmls, fmul and
2240         fmulx scalar and vector by element isns.
2241
2242 2019-02-07  Nick Clifton  <nickc@redhat.com>
2243
2244         * po/sv.po: Updated Swedish translation.
2245
2246 2019-01-31  Andreas Krebbel  <krebbel@linux.ibm.com>
2247
2248         * s390-mkopc.c (main): Accept arch13 as cpu string.
2249         * s390-opc.c: Add new instruction formats and instruction opcode
2250         masks.
2251         * s390-opc.txt: Add new arch13 instructions.
2252
2253 2019-01-25  Sudakshina Das  <sudi.das@arm.com>
2254
2255         * aarch64-tbl.h (QL_LDST_AT): Update macro.
2256         (aarch64_opcode): Change encoding for stg, stzg
2257         st2g and st2zg.
2258         * aarch64-asm-2.c: Regenerated.
2259         * aarch64-dis-2.c: Regenerated.
2260         * aarch64-opc-2.c: Regenerated.
2261
2262 2019-01-25  Sudakshina Das  <sudi.das@arm.com>
2263
2264         * aarch64-asm-2.c: Regenerated.
2265         * aarch64-dis-2.c: Likewise.
2266         * aarch64-opc-2.c: Likewise.
2267         * aarch64-tbl.h (aarch64_opcode): Add new stzgm.
2268
2269 2019-01-25  Sudakshina Das  <sudi.das@arm.com>
2270             Ramana Radhakrishnan  <ramana.radhakrishnan@arm.com>
2271
2272         * aarch64-asm.c (aarch64_ins_addr_simple_2): Remove.
2273         * aarch64-asm.h (ins_addr_simple_2): Likeiwse.
2274         * aarch64-dis.c (aarch64_ext_addr_simple_2): Likewise.
2275         * aarch64-dis.h (ext_addr_simple_2): Likewise.
2276         * aarch64-opc.c (operand_general_constraint_met_p): Remove
2277         case for ldstgv_indexed.
2278         (aarch64_print_operand): Remove case for AARCH64_OPND_ADDR_SIMPLE_2.
2279         * aarch64-tbl.h (struct aarch64_opcode): Remove ldgv and stgv.
2280         (AARCH64_OPERANDS): Remove ADDR_SIMPLE_2.
2281         * aarch64-asm-2.c: Regenerated.
2282         * aarch64-dis-2.c: Regenerated.
2283         * aarch64-opc-2.c: Regenerated.
2284
2285 2019-01-23  Nick Clifton  <nickc@redhat.com>
2286
2287         * po/pt_BR.po: Updated Brazilian Portuguese translation.
2288
2289 2019-01-21  Nick Clifton  <nickc@redhat.com>
2290
2291         * po/de.po: Updated German translation.
2292         * po/uk.po: Updated Ukranian translation.
2293
2294 2019-01-20  Chenghua Xu  <paul.hua.gm@gmail.com>
2295         * mips-dis.c (mips_arch_choices): Fix typo in
2296         gs464, gs464e and gs264e descriptors.
2297
2298 2019-01-19  Nick Clifton  <nickc@redhat.com>
2299
2300         * configure: Regenerate.
2301         * po/opcodes.pot: Regenerate.
2302
2303 2018-06-24  Nick Clifton  <nickc@redhat.com>
2304
2305         2.32 branch created.
2306
2307 2019-01-09  John Darrington <john@darrington.wattle.id.au>
2308
2309         * s12z-dis.c (print_insn_s12z):  Do not dereference an operand
2310         if it is null.
2311         -dis.c (opr_emit_disassembly): Do not omit an index if it is
2312         zero.
2313
2314 2019-01-09  Andrew Paprocki  <andrew@ishiboo.com>
2315
2316         * configure: Regenerate.
2317
2318 2019-01-07  Alan Modra  <amodra@gmail.com>
2319
2320         * configure: Regenerate.
2321         * po/POTFILES.in: Regenerate.
2322
2323 2019-01-03  John Darrington <john@darrington.wattle.id.au>
2324
2325         * s12z-opc.c: New file.
2326         * s12z-opc.h: New file.
2327         * s12z-dis.c: Removed all code not directly related to display
2328         of instructions.  Used the interface provided by the new files
2329         instead.
2330         * Makefile.am (TARGET_LIBOPCODES_CFILES) Add s12z-opc.c.
2331         * Makefile.in: Regenerate.
2332         * configure.ac (bfd_s12z_arch): Correct the dependencies.
2333         * configure: Regenerate.
2334
2335 2019-01-01  Alan Modra  <amodra@gmail.com>
2336
2337         Update year range in copyright notice of all files.
2338
2339 For older changes see ChangeLog-2018
2340 \f
2341 Copyright (C) 2019 Free Software Foundation, Inc.
2342
2343 Copying and distribution of this file, with or without modification,
2344 are permitted in any medium without royalty provided the copyright
2345 notice and this notice are preserved.
2346
2347 Local Variables:
2348 mode: change-log
2349 left-margin: 8
2350 fill-column: 74
2351 version-control: never
2352 End: