1 2019-12-17 Alan Modra <amodra@gmail.com>
3 * nds32-dis.c (nds32_mask_opcode): Avoid signed overflow.
4 (print_insn_nds32): Use uint64_t for "given" and "given1".
6 2019-12-17 Alan Modra <amodra@gmail.com>
8 * tic80-dis.c: Delete file.
9 * tic80-opc.c: Delete file.
10 * disassemble.c: Remove tic80 support.
11 * disassemble.h: Likewise.
12 * Makefile.am: Likewise.
13 * configure.ac: Likewise.
14 * Makefile.in: Regenerate.
15 * configure: Regenerate.
16 * po/POTFILES.in: Regenerate.
18 2019-12-17 Alan Modra <amodra@gmail.com>
20 * bpf-ibld.c: Regenerate.
22 2019-12-16 Alan Modra <amodra@gmail.com>
24 * aarch64-dis.c (sign_extend): Return uint64_t. Rewrite without
26 (aarch64_ext_imm): Avoid signed overflow.
28 2019-12-16 Alan Modra <amodra@gmail.com>
30 * microblaze-dis.c (read_insn_microblaze): Avoid signed overflow.
32 2019-12-16 Alan Modra <amodra@gmail.com>
34 * nios2-dis.c (nios2_print_insn_arg): Avoid signed overflow
36 2019-12-16 Alan Modra <amodra@gmail.com>
38 * xstormy16-ibld.c: Regenerate.
40 2019-12-16 Alan Modra <amodra@gmail.com>
42 * score-dis.c (print_insn_score16): Move rpush/rpop imm field
43 value adjustment so that it doesn't affect reg field too.
45 2019-12-16 Alan Modra <amodra@gmail.com>
47 * crx-dis.c (EXTRACT, SBM): Avoid signed overflow.
48 (get_number_of_operands, getargtype, getbits, getregname),
49 (getcopregname, getprocregname, gettrapstring, getcinvstring),
50 (getregliststring, get_word_at_PC, get_words_at_PC, build_mask),
51 (powerof2, match_opcode, make_instruction, print_arguments),
52 (print_arg): Delete forward declarations, moving static to..
53 (getregname, getcopregname, getregliststring): ..these definitions.
54 (build_mask): Return unsigned int mask.
55 (match_opcode): Use unsigned int vars.
57 2019-12-16 Alan Modra <amodra@gmail.com>
59 * bfin-dis.c (fmtconst, fmtconst_val): Avoid signed overflow.
61 2019-12-16 Alan Modra <amodra@gmail.com>
63 * nds32-dis.c (print_insn16, print_insn32): Remove forward decls.
64 (struct objdump_disasm_info): Delete.
65 (nds32_parse_audio_ext, nds32_parse_opcode): Cast result of
66 N32_IMMS to unsigned before shifting left.
68 2019-12-16 Alan Modra <amodra@gmail.com>
70 * moxie-dis.c (INST2OFFSET): Don't left shift a signed value.
71 (print_insn_moxie): Remove unnecessary cast.
73 2019-12-12 Alan Modra <amodra@gmail.com>
75 * csky-dis.c (csky_chars_to_number): Remove abort and unnecessary
78 2019-12-11 Alan Modra <amodra@gmail.com>
80 * arc-dis.c (BITS): Don't truncate high bits with shifts.
81 * nios2-dis.c (nios2_print_insn_arg): Don't sign extend with shifts.
82 * tic54x-dis.c (print_instruction): Likewise.
83 * tilegx-opc.c (parse_insn_tilegx): Likewise.
84 * tilepro-opc.c (parse_insn_tilepro): Likewise.
85 * visium-dis.c (disassem_class0): Likewise.
86 * pdp11-dis.c (sign_extend): Likewise.
88 * epiphany-ibld.c: Regenerate.
89 * lm32-ibld.c: Regenerate.
90 * m32c-ibld.c: Regenerate.
92 2019-12-11 Alan Modra <amodra@gmail.com>
94 * ns32k-dis.c (sign_extend): Correct last patch.
96 2019-12-11 Alan Modra <amodra@gmail.com>
98 * vax-dis.c (NEXTLONG): Avoid signed overflow.
100 2019-12-11 Alan Modra <amodra@gmail.com>
102 * v850-dis.c (get_operand_value): Use unsigned arithmetic. Don't
103 sign extend using shifts.
105 2019-12-11 Alan Modra <amodra@gmail.com>
107 * tic6x-dis.c (tic6x_extract_32): Avoid signed overflow.
109 2019-12-11 Alan Modra <amodra@gmail.com>
111 * tic4x-dis.c (tic4x_print_register): Formatting. Don't segfault
112 on NULL registertable entry.
113 (tic4x_hash_opcode): Use unsigned arithmetic.
115 2019-12-11 Alan Modra <amodra@gmail.com>
117 * s12z-opc.c (z_decode_signed_value): Avoid signed overflow.
119 2019-12-11 Alan Modra <amodra@gmail.com>
121 * ns32k-dis.c (bit_extract): Use unsigned arithmetic.
122 (bit_extract_simple, sign_extend): Likewise.
124 2019-12-11 Alan Modra <amodra@gmail.com>
126 * nios2-dis.c (nios2_print_insn_arg): Use 1u << 31.
128 2019-12-11 Alan Modra <amodra@gmail.com>
130 * moxie-dis.c (INST2OFFSET): Don't sign extend using shifts.
132 2019-12-11 Alan Modra <amodra@gmail.com>
134 * m68k-dis.c (COERCE32): Cast value first.
135 (NEXTLONG, NEXTULONG): Avoid signed overflow.
137 2019-12-11 Alan Modra <amodra@gmail.com>
139 * h8300-dis.c (extract_immediate): Avoid signed overflow.
140 (bfd_h8_disassemble): Likewise.
142 2019-12-11 Alan Modra <amodra@gmail.com>
144 * d30v-dis.c (print_insn): Make opind unsigned. Don't access
145 past end of operands array.
147 2019-12-11 Alan Modra <amodra@gmail.com>
149 * csky-dis.c (csky_chars_to_number): Rewrite. Avoid signed
150 overflow when collecting bytes of a number.
152 2019-12-11 Alan Modra <amodra@gmail.com>
154 * cris-dis.c (print_with_operands): Avoid signed integer
155 overflow when collecting bytes of a 32-bit integer.
157 2019-12-11 Alan Modra <amodra@gmail.com>
159 * cr16-dis.c (EXTRACT, SBM): Rewrite.
160 (cr16_match_opcode): Delete duplicate bcond test.
162 2019-12-11 Alan Modra <amodra@gmail.com>
164 * bfin-dis.c (HOST_LONG_WORD_SIZE, XFIELD): Delete.
166 (MASKBITS, SIGNEXTEND): Rewrite.
167 (fmtconst): Don't use ? expression now that SIGNEXTEND uses
168 unsigned arithmetic, instead assign result of SIGNEXTEND back
170 (fmtconst_val): Use 1u in shift expression.
172 2019-12-11 Alan Modra <amodra@gmail.com>
174 * arc-dis.c (find_format_from_table): Use ull constant when
175 shifting by up to 32.
177 2019-12-11 Alan Modra <amodra@gmail.com>
180 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Return
181 false when field is zero for sve_size_tsz_bhs.
183 2019-12-11 Alan Modra <amodra@gmail.com>
185 * epiphany-ibld.c: Regenerate.
187 2019-12-10 Alan Modra <amodra@gmail.com>
190 * disassemble.c (disassemble_free_target): New function.
192 2019-12-10 Alan Modra <amodra@gmail.com>
194 * cgen-dis.in (print_insn_@arch@): Replace insn_sets with private_data.
195 * disassemble.c (disassemble_init_for_target): Likewise.
196 * bpf-dis.c: Regenerate.
197 * epiphany-dis.c: Regenerate.
198 * fr30-dis.c: Regenerate.
199 * frv-dis.c: Regenerate.
200 * ip2k-dis.c: Regenerate.
201 * iq2000-dis.c: Regenerate.
202 * lm32-dis.c: Regenerate.
203 * m32c-dis.c: Regenerate.
204 * m32r-dis.c: Regenerate.
205 * mep-dis.c: Regenerate.
206 * mt-dis.c: Regenerate.
207 * or1k-dis.c: Regenerate.
208 * xc16x-dis.c: Regenerate.
209 * xstormy16-dis.c: Regenerate.
211 2019-12-10 Alan Modra <amodra@gmail.com>
213 * ppc-dis.c (private): Delete variable.
214 (get_powerpc_dialect): Don't segfault on NULL info->private_data.
215 (powerpc_init_dialect): Don't use global private.
217 2019-12-10 Alan Modra <amodra@gmail.com>
219 * s12z-opc.c: Formatting.
221 2019-12-08 Alan Modra <amodra@gmail.com>
223 * s12z-opc.c (exg_sex_discrim): Don't leak memory on invalid
226 2019-12-05 Jan Beulich <jbeulich@suse.com>
228 * aarch64-tbl.h (aarch64_feature_crypto,
229 aarch64_feature_crypto_v8_2, CRYPTO, CRYPTO_V8_2, CRYP_INSN,
230 CRYPTO_V8_2_INSN): Delete.
232 2019-12-05 Alan Modra <amodra@gmail.com>
235 * microblaze-dis.c (NUM_STRBUFS, STRBUF_SIZE): Define.
236 (struct string_buf): New.
237 (strbuf): New function.
238 (get_field): Use strbuf rather than strdup of local temp.
239 (get_field_imm, get_field_imm5, get_field_imm5_mbar): Likewise.
240 (get_field_rfsl, get_field_imm15): Likewise.
241 (get_field_rd, get_field_r1, get_field_r2): Update macros.
242 (get_field_special): Likewise. Don't strcpy spr. Formatting.
243 (print_insn_microblaze): Formatting. Init and pass string_buf to
246 2019-12-04 Jan Beulich <jbeulich@suse.com>
248 * i386-opc.tbl (lfs, lgs, lss): Drop No_qSuf.
249 * i386-tbl.h: Re-generate.
251 2019-12-04 Jan Beulich <jbeulich@suse.com>
253 * i386-dis.c (mod_table): Use Ev instead of Em for movdiri.
255 2019-12-04 Jan Beulich <jbeulich@suse.com>
257 * i386-opc.tbl (push, pop): Drop DefaultSize from GPR-only
259 (xbegin): Drop DefaultSize.
260 * i386-tbl.h: Re-generate.
262 2019-11-22 Mihail Ionescu <mihail.ionescu@arm.com>
264 * opcodes/arm-dis.c (arm_opcodes, thumb32_opcodes):
265 Change the coproc CRC conditions to use the extension
266 feature set, second word, base on ARM_EXT2_CRC.
268 2019-11-14 Jan Beulich <jbeulich@suse.com>
270 * i386-opc.tbl (syscall, sysret): Drop Cpu64 forms.
271 * i386-tbl.h: Re-generate.
273 2019-11-14 Jan Beulich <jbeulich@suse.com>
275 * i386-gen.c (opcode_modifiers): Remove JumpDword, JumpByte,
276 JumpInterSegment, and JumpAbsolute entries.
277 * i386-opc.h (JUMP, JUMP_DWORD, JUMP_BYTE, JUMP_INTERSEGMENT,
278 JUMP_ABSOLUTE): Define.
279 (struct i386_opcode_modifier): Extend jump field to 3 bits.
280 Remove jumpdword, jumpbyte, jumpintersegment, and jumpabsolute
282 * i386-opc.tbl (JumpByte, JumpDword, JumpAbsolute,
283 JumpInterSegment): Define.
284 * i386-tbl.h: Re-generate.
286 2019-11-14 Jan Beulich <jbeulich@suse.com>
288 * i386-gen.c (operand_type_init): Remove
289 OPERAND_TYPE_JUMPABSOLUTE entry.
290 (opcode_modifiers): Add JumpAbsolute entry.
291 (operand_types): Remove JumpAbsolute entry.
292 * i386-opc.h (JumpAbsolute): Move between enums.
293 (struct i386_opcode_modifier): Add jumpabsolute field.
294 (union i386_operand_type): Remove jumpabsolute field.
295 * i386-opc.tbl (call, lcall, jmp, ljmp): Move JumpAbsolute.
296 * i386-init.h, i386-tbl.h: Re-generate.
298 2019-11-14 Jan Beulich <jbeulich@suse.com>
300 * i386-gen.c (opcode_modifiers): Add AnySize entry.
301 (operand_types): Remove AnySize entry.
302 * i386-opc.h (AnySize): Move between enums.
303 (struct i386_opcode_modifier): Add anysize field.
304 (OTUnused): Un-comment.
305 (union i386_operand_type): Remove anysize field.
306 * i386-opc.tbl (lea, invlpg, clflush, prefetchnta, prefetcht0,
307 prefetcht1, prefetcht2, prefetchtw, bndmk, bndcl, bndcu, bndcn,
308 bndstx, bndldx, prefetchwt1, clflushopt, clwb, cldemote): Move
310 * i386-tbl.h: Re-generate.
312 2019-11-12 Nelson Chu <nelson.chu@sifive.com>
314 * riscv-opc.c (riscv_insn_types): Replace the INSN_CLASS_I with
315 INSN_CLASS_F and the INSN_CLASS_C with INSN_CLASS_F_AND_C if we
316 use the floating point register (FPR).
318 2019-11-12 Mihail Ionescu <mihail.ionescu@arm.com>
320 * opcodes/arm-dis.c (mve_opcodes): Enable VMOV imm to vec with
322 (is_mve_encoding_conflict): Update cmode conflict checks for
325 2019-11-12 Jan Beulich <jbeulich@suse.com>
327 * i386-gen.c (operand_type_init): Remove OPERAND_TYPE_ESSEG
329 (operand_types): Remove EsSeg entry.
330 (main): Replace stale use of OTMax.
331 * i386-opc.h (IS_STRING_ES_OP0, IS_STRING_ES_OP1): Define.
332 (struct i386_opcode_modifier): Expand isstring field to 2 bits.
334 (OTUnused): Comment out.
335 (union i386_operand_type): Remove esseg field.
336 * i386-opc.tbl (IsStringEsOp0, IsStringEsOp1): Define.
337 (cmps, scmp, scas, ssca, cmpsd): Add IsStringEsOp0.
338 (ins, movs, smov, movsd): Add IsStringEsOpOp1.
339 (stos, ssto): Add IsStringEsOp0/IsStringEsOpOp1.
340 * i386-init.h, i386-tbl.h: Re-generate.
342 2019-11-12 Jan Beulich <jbeulich@suse.com>
344 * i386-gen.c (operand_instances): Add RegB entry.
345 * i386-opc.h (enum operand_instance): Add RegB.
346 * i386-opc.tbl (RegC, RegD, RegB): Define.
347 (Acc, ShiftCount, InOutPortReg): Adjust definitions.
348 (monitor, mwait, invlpga, skinit, vmload, vmrun, vmsave, clzero,
349 monitorx, mwaitx): Drop ImmExt and convert encodings
351 * i386-reg.tbl (ecx, rcx): Add Instance=RegC.
352 (edx, rdx): Add Instance=RegD.
353 (ebx, rbx): Add Instance=RegB.
354 * i386-tbl.h: Re-generate.
356 2019-11-12 Jan Beulich <jbeulich@suse.com>
358 * i386-gen.c (operand_type_init): Adjust
359 OPERAND_TYPE_INOUTPORTREG, OPERAND_TYPE_SHIFTCOUNT,
360 OPERAND_TYPE_FLOATACC, OPERAND_TYPE_ACC8, OPERAND_TYPE_ACC16,
361 OPERAND_TYPE_ACC32, and OPERAND_TYPE_ACC64 entries.
362 (operand_instances): New.
363 (operand_types): Drop InOutPortReg, ShiftCount, and Acc entries.
364 (output_operand_type): New parameter "instance". Process it.
365 (process_i386_operand_type): New local variable "instance".
366 (main): Adjust static assertions.
367 * i386-opc.h (INSTANCE_WIDTH): Define.
368 (enum operand_instance): New.
369 (Acc, InOutPortReg, ShiftCount): Replace by ClassInstance.
370 (union i386_operand_type): Replace acc, inoutportreg, and
371 shiftcount by instance.
372 * i386-opc.tbl (Acc, InOutPortReg, ShiftCount): Define.
373 * i386-reg.tbl (st, al, cl, ax, dx, eax, rax, xmm0, st(0)):
375 * i386-init.h, i386-tbl.h: Re-generate.
377 2019-11-11 Jan Beulich <jbeulich@suse.com>
379 * aarch64-tbl.h (aarch64_opcode_table): Switch SVE2's
380 smaxp/sminp entries' "tied_operand" field to 2.
382 2019-11-11 Jan Beulich <jbeulich@suse.com>
384 * aarch64-opc.c (operand_general_constraint_met_p): Replace
385 "index" local variable by that of the already existing "num".
387 2019-11-08 H.J. Lu <hongjiu.lu@intel.com>
390 * i386-opc.tbl: Remove IgnoreSize from cmpsd and movsd.
391 * i386-tbl.h: Regenerated.
393 2019-11-08 Jan Beulich <jbeulich@suse.com>
395 * i386-gen.c (operand_type_init): Add Class= to
396 OPERAND_TYPE_REGMASK and OPERAND_TYPE_REGBND entries. Move up
397 OPERAND_TYPE_REGBND entry.
398 (operand_classes): Add RegMask and RegBND entries.
399 (operand_types): Drop RegMask and RegBND entry.
400 * i386-opc.h (enum operand_class): Add RegMask and RegBND.
401 (RegMask, RegBND): Delete.
402 (union i386_operand_type): Remove regmask and regbnd fields.
403 * i386-opc.tbl (RegMask, RegBND): Define.
404 * i386-reg.tbl: Replace RegMask by Class=RegMask and RegBND by
406 * i386-init.h, i386-tbl.h: Re-generate.
408 2019-11-08 Jan Beulich <jbeulich@suse.com>
410 * i386-gen.c (operand_type_init): Add Class= to
411 OPERAND_TYPE_REGMMX, OPERAND_TYPE_REGXMM, OPERAND_TYPE_REGYMM, and
412 OPERAND_TYPE_REGZMM entries.
413 (operand_classes): Add RegMMX and RegSIMD entries.
414 (operand_types): Drop RegMMX and RegSIMD entries.
415 * i386-opc.h (enum operand_class): Add RegMMX and RegSIMD.
416 (RegMMX, RegSIMD): Delete.
417 (union i386_operand_type): Remove regmmx and regsimd fields.
418 * i386-opc.tbl (RegMMX): Define.
419 (RegXMM, RegYMM, RegZMM): Add Class=.
420 * i386-reg.tbl: Replace RegMMX by Class=RegMMX and RegSIMD by
422 * i386-init.h, i386-tbl.h: Re-generate.
424 2019-11-08 Jan Beulich <jbeulich@suse.com>
426 * i386-gen.c (operand_type_init): Add Class= to
427 OPERAND_TYPE_CONTROL, OPERAND_TYPE_TEST, and OPERAND_TYPE_DEBUG
429 (operand_classes): Add RegCR, RegDR, and RegTR entries.
430 (operand_types): Drop Control, Debug, and Test entries.
431 * i386-opc.h (enum operand_class): Add RegCR, RegDR, and RegTR.
432 (Control, Debug, Test): Delete.
433 (union i386_operand_type): Remove control, debug, and test
435 * i386-opc.tbl (Control, Debug, Test): Define.
436 * i386-reg.tbl: Replace Control by Class=RegCR, Debug by
437 Class=RegDR, and Test by Class=RegTR.
438 * i386-init.h, i386-tbl.h: Re-generate.
440 2019-11-08 Jan Beulich <jbeulich@suse.com>
442 * i386-gen.c (operand_type_init): Add Class= to
443 OPERAND_TYPE_SREG entry.
444 (operand_classes): Add SReg entry.
445 (operand_types): Drop SReg entry.
446 * i386-opc.h (enum operand_class): Add SReg.
448 (union i386_operand_type): Remove sreg field.
449 * i386-opc.tbl (SReg): Define.
450 * i386-reg.tbl: Replace SReg by Class=SReg.
451 * i386-init.h, i386-tbl.h: Re-generate.
453 2019-11-08 Jan Beulich <jbeulich@suse.com>
455 * i386-gen.c (operand_type_init): Add Class=. New
456 OPERAND_TYPE_ANYIMM entry.
457 (operand_classes): New.
458 (operand_types): Drop Reg entry.
459 (output_operand_type): New parameter "class". Process it.
460 (process_i386_operand_type): New local variable "class".
461 (main): Adjust static assertions.
462 * i386-opc.h (CLASS_WIDTH): Define.
463 (enum operand_class): New.
464 (Reg): Replace by Class. Adjust comment.
465 (union i386_operand_type): Replace reg by class.
466 * i386-opc.tbl (Reg8, Reg16, Reg32, Reg64, FloatReg): Add
468 * i386-reg.tbl: Replace Reg by Class=Reg.
469 * i386-init.h: Re-generate.
471 2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
473 * opcodes/aarch64-tbl.h (V8_6_INSN): New macro for v8.6 instructions.
474 (aarch64_opcode_table): Add data gathering hint mnemonic.
475 * opcodes/aarch64-dis-2.c: Account for new instruction.
477 2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
479 * arm-dis.c (neon_opcodes): Add i8mm SIMD instructions.
482 2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
484 * aarch64-tbl.h (aarch64_feature_i8mm_sve, aarch64_feature_f32mm_sve,
485 aarch64_feature_f64mm_sve, aarch64_feature_i8mm, aarch64_feature_f32mm,
486 aarch64_feature_f64mm): New feature sets.
487 (INT8MATMUL_INSN, F64MATMUL_SVE_INSN, F64MATMUL_INSN,
488 F32MATMUL_SVE_INSN, F32MATMUL_INSN): New macros to define matrix multiply
490 (I8MM_SVE, F32MM_SVE, F64MM_SVE, I8MM, F32MM, F64MM): New feature set
492 (QL_MMLA64, OP_SVE_SBB): New qualifiers.
493 (OP_SVE_QQQ): New qualifier.
494 (INT8MATMUL_SVE_INSNC, F64MATMUL_SVE_INSNC,
495 F32MATMUL_SVE_INSNC): New feature set for bfloat16 instructions to support
496 the movprfx constraint.
497 (aarch64_opcode_table): Support for SVE_ADDR_RI_S4x32.
498 (aarch64_opcode_table): Define new instructions smmla,
499 ummla, usmmla, usdot, sudot, fmmla, ld1rob, ld1roh, ld1row, ld1rod,
501 * aarch64-opc.c (operand_general_constraint_met_p): Handle
502 AARCH64_OPND_SVE_ADDR_RI_S4x32.
503 (aarch64_print_operand): Handle AARCH64_OPND_SVE_ADDR_RI_S4x32.
504 * aarch64-dis-2.c (aarch64_opcode_lookup_1, aarch64_find_next_opcode):
505 Account for new instructions.
506 * opcodes/aarch64-asm-2.c (aarch64_insert_operand): Support the new
508 * aarch64-opc-2.c (aarch64_operands): Support the new S4x32 operand.
510 2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
511 2019-11-07 Matthew Malcomson <matthew.malcomson@arm.com>
513 * arm-dis.c (select_arm_features): Update bfd_march_arm_8 with
515 (coprocessor_opcodes): Add bfloat16 vcvt{t,b}.
516 (neon_opcodes): Add bfloat SIMD instructions.
517 (print_insn_coprocessor): Add new control character %b to print
518 condition code without checking cp_num.
519 (print_insn_neon): Account for BFloat16 instructions that have no
520 special top-byte handling.
522 2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
523 2019-11-07 Matthew Malcomson <matthew.malcomson@arm.com>
525 * arm-dis.c (print_insn_coprocessor,
526 print_insn_generic_coprocessor): Create wrapper functions around
527 the implementation of the print_insn_coprocessor control codes.
528 (print_insn_coprocessor_1): Original print_insn_coprocessor
529 function that now takes which array to look at as an argument.
530 (print_insn_arm): Use both print_insn_coprocessor and
531 print_insn_generic_coprocessor.
532 (print_insn_thumb32): As above.
534 2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
535 2019-11-07 Matthew Malcomson <matthew.malcomson@arm.com>
537 * aarch64-asm.c (aarch64_ins_reglane): Use AARCH64_OPND_QLF_S_2H
538 in reglane special case.
539 * aarch64-dis-2.c (aarch64_opcode_lookup_1,
540 aarch64_find_next_opcode): Account for new instructions.
541 * aarch64-dis.c (aarch64_ext_reglane): Use AARCH64_OPND_QLF_S_2H
542 in reglane special case.
543 * aarch64-opc.c (struct operand_qualifier_data): Add data for
544 new AARCH64_OPND_QLF_S_2H qualifier.
545 * aarch64-tbl.h (QL_BFDOT QL_BFDOT64, QL_BFDOT64I, QL_BFMMLA2,
546 QL_BFCVT64, QL_BFCVTN64, QL_BFCVTN2_64): New qualifiers.
547 (aarch64_feature_bfloat16, aarch64_feature_bfloat16_sve): New feature
549 (BFLOAT_SVE, BFLOAT): New feature set macros.
550 (BFLOAT_SVE_INSN, BFLOAT_INSN): New macros to define BFloat16
552 (aarch64_opcode_table): Define new instructions bfdot,
553 bfmmla, bfcvt, bfcvtnt, bfdot, bfdot, bfcvtn, bfmlal[b/t]
556 2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
557 2019-11-07 Matthew Malcomson <matthew.malcomson@arm.com>
559 * aarch64-tbl.h (ARMV8_6): New macro.
561 2019-11-07 Jan Beulich <jbeulich@suse.com>
563 * i386-dis.c (prefix_table): Add mcommit.
564 (rm_table): Add rdpru.
565 * i386-gen.c (cpu_flag_init): Adjust CPU_ZNVER2_FLAGS entry. Add
566 CPU_RDPRU_FLAGS and CPU_MCOMMIT_FLAGS entries.
567 (cpu_flags): Add CpuRDPRU and CpuMCOMMIT entries.
568 * i386-opc.h (CpuRDPRU, CpuMCOMMIT): New.
569 (union i386_cpu_flags): Add cpurdpru and cpumcommit fields.
570 * i386-opc.tbl (mcommit, rdpru): New.
571 * i386-init.h, i386-tbl.h: Re-generate.
573 2019-11-07 Jan Beulich <jbeulich@suse.com>
575 * i386-dis.c (OP_Mwait): Drop local variable "names", use
577 (OP_Monitor): Drop local variable "op1_names", re-purpose
578 "names" for it instead, and replace former "names" uses by
581 2019-11-07 Jan Beulich <jbeulich@suse.com>
584 * opcodes/i386-opc.tbl (movsd, cmpsd): Drop IgnoreSize from
586 * opcodes/i386-tbl.h: Re-generate.
588 2019-11-05 Jan Beulich <jbeulich@suse.com>
590 * i386-dis.c (OP_Mwaitx): Delete.
591 (prefix_table): Use OP_Mwait for mwaitx entry.
592 (OP_Mwait): Also handle mwaitx.
594 2019-11-05 Jan Beulich <jbeulich@suse.com>
596 * i386-dis.c (PREFIX_0F01_REG_7_MOD_3_RM_2,
597 PREFIX_0F01_REG_7_MOD_3_RM_3): New.
598 (prefix_table): Add respective entries.
599 (rm_table): Link to those entries.
601 2019-11-05 Jan Beulich <jbeulich@suse.com>
603 * i386-dis.c (REG_0F1C_MOD_0): Rename to ...
604 (REG_0F1C_P_0_MOD_0): ... this.
605 (REG_0F1E_MOD_3): Rename to ...
606 (REG_0F1E_P_1_MOD_3): ... this.
607 (RM_0F01_REG_5): Rename to ...
608 (RM_0F01_REG_5_MOD_3): ... this.
609 (RM_0F01_REG_7): Rename to ...
610 (RM_0F01_REG_7_MOD_3): ... this.
611 (RM_0F1E_MOD_3_REG_7): Rename to ...
612 (RM_0F1E_P_1_MOD_3_REG_7): ... this.
613 (RM_0FAE_REG_6): Rename to ...
614 (RM_0FAE_REG_6_MOD_3_P_0): ... this.
615 (RM_0FAE_REG_7): Rename to ...
616 (RM_0FAE_REG_7_MOD_3): ... this.
617 (PREFIX_MOD_0_0F01_REG_5): Rename to ...
618 (PREFIX_0F01_REG_5_MOD_0): ... this.
619 (PREFIX_MOD_3_0F01_REG_5_RM_0): Rename to ...
620 (PREFIX_0F01_REG_5_MOD_3_RM_0): ... this.
621 (PREFIX_MOD_3_0F01_REG_5_RM_2): Rename to ...
622 (PREFIX_0F01_REG_5_MOD_3_RM_2): ... this.
623 (PREFIX_0FAE_REG_0): Rename to ...
624 (PREFIX_0FAE_REG_0_MOD_3): ... this.
625 (PREFIX_0FAE_REG_1): Rename to ...
626 (PREFIX_0FAE_REG_1_MOD_3): ... this.
627 (PREFIX_0FAE_REG_2): Rename to ...
628 (PREFIX_0FAE_REG_2_MOD_3): ... this.
629 (PREFIX_0FAE_REG_3): Rename to ...
630 (PREFIX_0FAE_REG_3_MOD_3): ... this.
631 (PREFIX_MOD_0_0FAE_REG_4): Rename to ...
632 (PREFIX_0FAE_REG_4_MOD_0): ... this.
633 (PREFIX_MOD_3_0FAE_REG_4): Rename to ...
634 (PREFIX_0FAE_REG_4_MOD_3): ... this.
635 (PREFIX_MOD_0_0FAE_REG_5): Rename to ...
636 (PREFIX_0FAE_REG_5_MOD_0): ... this.
637 (PREFIX_MOD_3_0FAE_REG_5): Rename to ...
638 (PREFIX_0FAE_REG_5_MOD_3): ... this.
639 (PREFIX_MOD_0_0FAE_REG_6): Rename to ...
640 (PREFIX_0FAE_REG_6_MOD_0): ... this.
641 (PREFIX_MOD_1_0FAE_REG_6): Rename to ...
642 (PREFIX_0FAE_REG_6_MOD_3): ... this.
643 (PREFIX_0FAE_REG_7): Rename to ...
644 (PREFIX_0FAE_REG_7_MOD_0): ... this.
645 (PREFIX_MOD_0_0FC3): Rename to ...
646 (PREFIX_0FC3_MOD_0): ... this.
647 (PREFIX_MOD_0_0FC7_REG_6): Rename to ...
648 (PREFIX_0FC7_REG_6_MOD_0): ... this.
649 (PREFIX_MOD_3_0FC7_REG_6): Rename to ...
650 (PREFIX_0FC7_REG_6_MOD_3): ... this.
651 (PREFIX_MOD_3_0FC7_REG_7): Rename to ...
652 (PREFIX_0FC7_REG_7_MOD_3): ... this.
653 (reg_table, prefix_table, mod_table, rm_table): Adjust
656 2019-11-04 Nick Clifton <nickc@redhat.com>
658 * v850-dis.c (get_v850_sreg_name): New function. Returns the name
659 of a v850 system register. Move the v850_sreg_names array into
661 (get_v850_reg_name): Likewise for ordinary register names.
662 (get_v850_vreg_name): Likewise for vector register names.
663 (get_v850_cc_name): Likewise for condition codes.
664 * get_v850_float_cc_name): Likewise for floating point condition
666 (get_v850_cacheop_name): Likewise for cache-ops.
667 (get_v850_prefop_name): Likewise for pref-ops.
668 (disassemble): Use the new accessor functions.
670 2019-10-30 Delia Burduv <delia.burduv@arm.com>
672 * aarch64-opc.c (print_immediate_offset_address): Don't print the
673 immediate for the writeback form of ldraa/ldrab if it is 0.
674 * aarch64-tbl.h: Updated the documentation for ADDR_SIMM10.
675 * aarch64-opc-2.c: Regenerated.
677 2019-10-30 Jan Beulich <jbeulich@suse.com>
679 * i386-gen.c (operand_type_shorthands): Delete.
680 (operand_type_init): Expand previous shorthands.
681 (set_bitfield_from_shorthand): Rename back to ...
682 (set_bitfield_from_cpu_flag_init): ... this. Drop processing
683 of operand_type_init[].
684 (set_bitfield): Adjust call to the above function.
685 * i386-opc.tbl (Reg8, Reg16, Reg32, Reg64, FloatAcc, FloatReg,
686 RegXMM, RegYMM, RegZMM): Define.
687 * i386-reg.tbl: Expand prior shorthands.
689 2019-10-30 Jan Beulich <jbeulich@suse.com>
691 * i386-gen.c (output_i386_opcode): Change order of fields
693 * i386-opc.h (struct insn_template): Move operands field.
694 Convert extension_opcode field to unsigned short.
695 * i386-tbl.h: Re-generate.
697 2019-10-30 Jan Beulich <jbeulich@suse.com>
699 * i386-gen.c (process_i386_opcode_modifier): Report bogus uses
701 * i386-opc.h (W): Extend comment.
702 * i386-opc.tbl (mov, movabs, movq): Drop W and adjust opcodes of
703 general purpose variants not allowing for byte operands.
704 * i386-tbl.h: Re-generate.
706 2019-10-29 Nick Clifton <nickc@redhat.com>
708 * tic30-dis.c (print_branch): Correct size of operand array.
710 2019-10-29 Nick Clifton <nickc@redhat.com>
712 * d30v-dis.c (print_insn): Check that operand index is valid
713 before attempting to access the operands array.
715 2019-10-29 Nick Clifton <nickc@redhat.com>
717 * ia64-opc.c (locate_opcode_ent): Prevent a negative shift when
718 locating the bit to be tested.
720 2019-10-29 Nick Clifton <nickc@redhat.com>
722 * s12z-dis.c (opr_emit_disassembly): Check for illegal register
724 (shift_size_table): Use a fixed size defined as S12Z_N_SIZES.
725 (print_insn_s12z): Check for illegal size values.
727 2019-10-28 Nick Clifton <nickc@redhat.com>
729 * csky-dis.c (csky_chars_to_number): Check for a negative
730 count. Use an unsigned integer to construct the return value.
732 2019-10-28 Nick Clifton <nickc@redhat.com>
734 * tic30-dis.c (OPERAND_BUFFER_LEN): Define. Use as length of
735 operand buffer. Set value to 15 not 13.
736 (get_register_operand): Use OPERAND_BUFFER_LEN.
737 (get_indirect_operand): Likewise.
738 (print_two_operand): Likewise.
739 (print_three_operand): Likewise.
740 (print_oar_insn): Likewise.
742 2019-10-28 Nick Clifton <nickc@redhat.com>
744 * ns32k-dis.c (bit_extract): Add sanitiy check of parameters.
745 (bit_extract_simple): Likewise.
746 (bit_copy): Likewise.
747 (pirnt_insn_ns32k): Ensure that uninitialised elements in the
748 index_offset array are not accessed.
750 2019-10-28 Nick Clifton <nickc@redhat.com>
752 * xgate-dis.c (print_insn): Fix decoding of the XGATE_OP_DYA
755 2019-10-25 Nick Clifton <nickc@redhat.com>
757 * rx-dis.c (print_insn_rx): Use parenthesis to ensure correct
758 access to opcodes.op array element.
760 2019-10-23 Nick Clifton <nickc@redhat.com>
762 * rx-dis.c (get_register_name): Fix spelling typo in error
764 (get_condition_name, get_flag_name, get_double_register_name)
765 (get_double_register_high_name, get_double_register_low_name)
766 (get_double_control_register_name, get_double_condition_name)
767 (get_opsize_name, get_size_name): Likewise.
769 2019-10-22 Nick Clifton <nickc@redhat.com>
771 * rx-dis.c (get_size_name): New function. Provides safe
772 access to name array.
773 (get_opsize_name): Likewise.
774 (print_insn_rx): Use the accessor functions.
776 2019-10-16 Nick Clifton <nickc@redhat.com>
778 * rx-dis.c (get_register_name): New function. Provides safe
779 access to name array.
780 (get_condition_name, get_flag_name, get_double_register_name)
781 (get_double_register_high_name, get_double_register_low_name)
782 (get_double_control_register_name, get_double_condition_name):
784 (print_insn_rx): Use the accessor functions.
786 2019-10-09 Nick Clifton <nickc@redhat.com>
789 * avr-dis.c (avr_operand): Fix construction of address for lds/sts
792 2019-10-07 Jan Beulich <jbeulich@suse.com>
794 * opcodes/i386-opc.tbl (movsd): Add Dword and IgnoreSize.
795 (cmpsd): Likewise. Move EsSeg to other operand.
796 * opcodes/i386-tbl.h: Re-generate.
798 2019-09-23 Alan Modra <amodra@gmail.com>
800 * m68k-dis.c: Include cpu-m68k.h
802 2019-09-23 Alan Modra <amodra@gmail.com>
804 * mips-dis.c: Include elfxx-mips.h. Move "elf-bfd.h" and
805 "elf/mips.h" earlier.
807 2018-09-20 Jan Beulich <jbeulich@suse.com>
810 * i386-opc.tbl (push, pop): Re-instate distinct Cpu64 templates
812 * i386-tbl.h: Re-generate.
814 2019-09-18 Alan Modra <amodra@gmail.com>
816 * arc-ext.c: Update throughout for bfd section macro changes.
818 2019-09-18 Simon Marchi <simon.marchi@polymtl.ca>
820 * Makefile.in: Re-generate.
821 * configure: Re-generate.
823 2019-09-17 Maxim Blinov <maxim.blinov@embecosm.com>
825 * riscv-opc.c (riscv_opcodes): Change subset field
826 to insn_class field for all instructions.
827 (riscv_insn_types): Likewise.
829 2019-09-16 Phil Blundell <pb@pbcl.net>
831 * configure: Regenerated.
833 2019-09-10 Miod Vallat <miod@online.fr>
836 * m68k-opc.c: Correct aliases for tdivsl and tdivul.
838 2019-09-09 Phil Blundell <pb@pbcl.net>
840 binutils 2.33 branch created.
842 2019-09-03 Nick Clifton <nickc@redhat.com>
845 * tic30-dis.c (get_indirect_operand): Check for bufcnt being
846 greater than zero before indexing via (bufcnt -1).
848 2019-09-03 Nick Clifton <nickc@redhat.com>
851 * mmix-dis.c (MAX_REG_NAME_LEN): Define.
852 (MAX_SPEC_REG_NAME_LEN): Define.
853 (struct mmix_dis_info): Use defined constants for array lengths.
854 (get_reg_name): New function.
855 (get_sprec_reg_name): New function.
856 (print_insn_mmix): Use new functions.
858 2019-08-27 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
860 * arm-dis.c (mve_opcodes): Add entry for MVE_VMOV_VEC_TO_VEC.
861 (is_mve_undefined): Add case for MVE_VMOV_VEC_TO_VEC.
862 (print_insn_mve): Add condition to check Qm==Qn of VORR instruction.
864 2019-08-22 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
866 * aarch64-opc.c (aarch64_sys_regs): Update encoding of tfsre0_el1,
867 tfsr_el1, tfsr_el2, tfsr_el3, tfsr_el12.
868 (aarch64_sys_reg_supported_p): Update checks for the above.
870 2019-08-12 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
872 * arm-dis.c (struct mopcode32 mve_opcodes): Modify the mask for
873 cases MVE_SQRSHRL and MVE_UQRSHLL.
874 (print_insn_mve): Add case for specifier 'k' to check
875 specific bit of the instruction.
877 2019-08-07 Phillipe Antoine <p.antoine@catenacyber.fr>
880 * arc-dis.c (arc_insn_length): Return 0 rather than aborting when
881 encountering an unknown machine type.
882 (print_insn_arc): Handle arc_insn_length returning 0. In error
883 cases return -1 rather than calling abort.
885 2019-08-07 Jan Beulich <jbeulich@suse.com>
887 * i386-opc.tbl (fld, fstp): Drop FloatMF from extended forms.
888 (fldcw, fnstcw, fstcw, fnstsw, fstsw): Replace FloatMF by
890 * i386-tbl.h: Re-generate.
892 2019-08-05 Barnaby Wilks <barnaby.wilks@arm.com>
894 * arm-dis.c: Only accept signed variants of VQ(R)DMLAH and VQ(R)DMLASH
897 2019-07-30 Mel Chen <mel.chen@sifive.com>
899 * riscv-opc.c (riscv_opcodes): Set frsr, fssr, frcsr, fscsr, frrm,
900 fsrm, fsrmi, frflags, fsflags, fsflagsi to alias instructions.
902 * riscv-opc.c (riscv_opcodes): Adjust order of frsr, frcsr, fssr,
905 2019-07-24 Claudiu Zissulescu <claziss@synopsys.com>
907 * arc-dis.c (skip_this_opcode): Check also for 0x07 major opcodes,
908 and MPY class instructions.
909 (parse_option): Add nps400 option.
910 (print_arc_disassembler_options): Add nps400 info.
912 2019-07-24 Claudiu Zissulescu <claziss@synopsys.com>
914 * arc-ext-tbl.h (bspeek): Remove it, added to main table.
917 * arc-opc.c (RAD_CHK): Add.
918 * arc-tbl.h: Regenerate.
920 2019-07-23 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
922 * aarch64-opc.c (aarch64_sys_regs): Add gmid_el1 entry.
923 (aarch64_sys_reg_supported_p): Handle gmid_el1 encoding.
925 2019-07-22 Barnaby Wilks <barnaby.wilks@arm.com>
927 * arm-dis.c (is_mve_unpredictable): Stop marking some MVE
928 instructions as UNPREDICTABLE.
930 2019-07-19 Jose E. Marchesi <jose.marchesi@oracle.com>
932 * bpf-desc.c: Regenerated.
934 2019-07-17 Jan Beulich <jbeulich@suse.com>
936 * i386-gen.c (static_assert): Define.
938 * i386-opc.h (Opcode_Modifier_Max): Rename to ...
939 (Opcode_Modifier_Num): ... this.
942 2019-07-16 Jan Beulich <jbeulich@suse.com>
944 * i386-gen.c (operand_types): Move RegMem ...
945 (opcode_modifiers): ... here.
946 * i386-opc.h (RegMem): Move to opcode modifer enum.
947 (union i386_operand_type): Move regmem field ...
948 (struct i386_opcode_modifier): ... here.
949 * i386-opc.tbl (RegMem): Define.
950 (mov, movq): Move RegMem on segment, control, debug, and test
952 (pextrb): Move RegMem on register only flavors. Add IgnoreSize
953 to non-SSE2AVX flavor.
954 (extractps, pextrw, vcvtps2ph, vextractps, vpextrb, vpextrw):
955 Move RegMem on register only flavors. Drop IgnoreSize from
956 legacy encoding flavors.
957 (movss, movsd, vmovss, vmovsd): Drop RegMem from register only
959 (vpinsrb, vpinsrw): Drop IgnoreSize where still present on
960 register only flavors.
961 (vmovd): Move RegMem and drop IgnoreSize on register only
962 flavor. Change opcode and operand order to store form.
963 * opcodes/i386-init.h, i386-tbl.h: Re-generate.
965 2019-07-16 Jan Beulich <jbeulich@suse.com>
967 * i386-gen.c (operand_type_init, operand_types): Replace SReg
969 * i386-opc.h (SReg2, SReg3): Replace by ...
971 (union i386_operand_type): Replace sreg fields.
972 * i386-opc.tbl (mov, ): Use SReg.
973 (push, pop): Likewies. Drop i386 and x86-64 specific segment
975 * i386-reg.tbl (cs, ds, es, fs, gs, ss, flat): Use SReg.
976 * opcodes/i386-init.h, i386-tbl.h: Re-generate.
978 2019-07-15 Jose E. Marchesi <jose.marchesi@oracle.com>
980 * bpf-desc.c: Regenerate.
981 * bpf-opc.c: Likewise.
982 * bpf-opc.h: Likewise.
984 2019-07-14 Jose E. Marchesi <jose.marchesi@oracle.com>
986 * bpf-desc.c: Regenerate.
987 * bpf-opc.c: Likewise.
989 2019-07-10 Hans-Peter Nilsson <hp@bitrange.com>
991 * arm-dis.c (print_insn_coprocessor): Rename index to
994 2019-07-05 Kito Cheng <kito.cheng@sifive.com>
996 * riscv-opc.c (riscv_insn_types): Add r4 type.
998 * riscv-opc.c (riscv_insn_types): Add b and j type.
1000 * opcodes/riscv-opc.c (riscv_insn_types): Remove incorrect
1001 format for sb type and correct s type.
1003 2019-07-02 Richard Sandiford <richard.sandiford@arm.com>
1005 * aarch64-tbl.h (aarch64_opcode): Set C_SCAN_MOVPRFX for the
1006 SVE FMOV alias of FCPY.
1008 2019-07-02 Richard Sandiford <richard.sandiford@arm.com>
1010 * aarch64-tbl.h (aarch64_opcode_table): Add C_MAX_ELEM flags
1011 to SVE fcvtzs, fcvtzu, scvtf and ucvtf entries.
1013 2019-07-02 Richard Sandiford <richard.sandiford@arm.com>
1015 * aarch64-opc.c (verify_constraints): Skip GPRs when scanning the
1016 registers in an instruction prefixed by MOVPRFX.
1018 2019-07-01 Matthew Malcomson <matthew.malcomson@arm.com>
1020 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Use new
1021 sve_size_13 icode to account for variant behaviour of
1023 * aarch64-dis-2.c: Regenerate.
1024 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Use new
1025 sve_size_13 icode to account for variant behaviour of
1027 * aarch64-tbl.h (OP_SVE_VVV_HD_BS): Add new qualifier.
1028 (OP_SVE_VVV_Q_D): Add new qualifier.
1029 (OP_SVE_VVV_QHD_DBS): Remove now unused qualifier.
1030 (struct aarch64_opcode): Split pmull{t,b} into those requiring
1033 2019-07-01 Jan Beulich <jbeulich@suse.com>
1035 * opcodes/i386-gen.c (operand_type_init): Remove
1036 OPERAND_TYPE_VEC_IMM4 entry.
1037 (operand_types): Remove Vec_Imm4.
1038 * opcodes/i386-opc.h (Vec_Imm4): Delete.
1039 (union i386_operand_type): Remove vec_imm4.
1040 * i386-opc.tbl (vpermil2pd, vpermil2ps): Remove Vec_Imm4.
1041 * opcodes/i386-init.h, i386-tbl.h: Re-generate.
1043 2019-07-01 Jan Beulich <jbeulich@suse.com>
1045 * i386-opc.tbl (lfence, mfence, sfence, monitor, mwait, vmcall,
1046 vmlaunch, vmresume, vmxoff, vmfunc, xgetbv, xsetbv, swapgs,
1047 rdtscp, clgi, invlpga, skinit, stgi, vmload, vmmcall, vmrun,
1048 vmsave, montmul, xsha1, xsha256, xstorerng, xcryptecb,
1049 xcryptcbc, xcryptctr, xcryptcfb, xcryptofb, xstore, clac, stac,
1050 monitorx, mwaitx): Drop ImmExt from operand-less forms.
1051 * i386-tbl.h: Re-generate.
1053 2019-07-01 Jan Beulich <jbeulich@suse.com>
1055 * i386-opc.tbl (and, or): Add Optimize to forms allowing two
1057 * i386-tbl.h: Re-generate.
1059 2019-07-01 Jan Beulich <jbeulich@suse.com>
1061 * i386-opc.tbl (C): New.
1062 (paddb, paddw, paddd, paddq, paddsb, paddsw, paddusb, paddusw,
1063 pand, pcmpeqb, pcmpeqw, pcmpeqd, pmaddwd, pmulhw, pmullw,
1064 por, pxor, andps, cmpeqps, cmpeqss, cmpneqps, cmpneqss,
1065 cmpordps, cmpordss, cmpunordps, cmpunordss, orps, pavgb, pavgw,
1066 pmaxsw, pmaxub, pminsw, pminub, pmulhuw, xorps, andpd, cmpeqpd,
1067 cmpeqsd, cmpneqpd, cmpneqsd, cmpordpd, cmpordsd, cmpunordpd,
1068 cmpunordsd, orpd, xorpd, pmuludq, vandpd, vandps, vcmpeq_ospd,
1069 vcmpeq_osps, vcmpeq_ossd, vcmpeq_osss, vcmpeqpd, vcmpeqps,
1070 vcmpeqsd, vcmpeqss, vcmpeq_uqpd, vcmpeq_uqps, vcmpeq_uqsd,
1071 vcmpeq_uqss, vcmpeq_uspd, vcmpeq_usps, vcmpeq_ussd,
1072 vcmpeq_usss, vcmpfalse_ospd, vcmpfalse_osps, vcmpfalse_ossd,
1073 vcmpfalse_osss, vcmpfalsepd, vcmpfalseps, vcmpfalsesd,
1074 vcmpfalsess, vcmpneq_oqpd, vcmpneq_oqps, vcmpneq_oqsd,
1075 vcmpneq_oqss, vcmpneq_ospd, vcmpneq_osps, vcmpneq_ossd,
1076 vcmpneq_osss, vcmpneqpd, vcmpneqps, vcmpneqsd, vcmpneqss,
1077 vcmpneq_uspd, vcmpneq_usps, vcmpneq_ussd, vcmpneq_usss,
1078 vcmpordpd, vcmpordps, vcmpordsd, vcmpord_spd, vcmpord_sps,
1079 vcmpordss, vcmpord_ssd, vcmpord_sss, vcmptruepd, vcmptrueps,
1080 vcmptruesd, vcmptruess, vcmptrue_uspd, vcmptrue_usps,
1081 vcmptrue_ussd, vcmptrue_usss, vcmpunordpd, vcmpunordps,
1082 vcmpunordsd, vcmpunord_spd, vcmpunord_sps, vcmpunordss,
1083 vcmpunord_ssd, vcmpunord_sss, vorpd, vorps, vpaddsb, vpaddsw,
1084 vpaddb, vpaddd, vpaddq, vpaddw, vpaddusb, vpaddusw, vpand,
1085 vpavgb, vpavgw, vpcmpeqb, vpcmpeqd, vpcmpeqw, vpmaddwd,
1086 vpmaxsw, vpmaxub, vpminsw, vpminub, vpmulhuw, vpmulhw, vpmullw,
1087 vpmuludq, vpor, vpxor, vxorpd, vxorps): Add C to VEX-encoded
1089 * i386-tbl.h: Re-generate.
1091 2019-07-01 Jan Beulich <jbeulich@suse.com>
1093 * i386-opc.tbl (and, or): Add Optimize to forms allowing two
1095 * i386-tbl.h: Re-generate.
1097 2019-07-01 Jan Beulich <jbeulich@suse.com>
1099 * i386-dis-evex-prefix.h: Use PCLMUL for vpclmulqdq.
1100 * i386-opc.tbl (vpclmullqlqdq, vpclmulhqlqdq, vpclmullqhqdq,
1101 vpclmulhqhqdq): Add CpuVPCLMULQDQ flavors.
1102 * i386-tbl.h: Re-generate.
1104 2019-07-01 Jan Beulich <jbeulich@suse.com>
1106 * i386-opc.tbl (vextractps, vpextrw, vpinsrw): Remove
1107 Disp8MemShift from register only templates.
1108 * i386-tbl.h: Re-generate.
1110 2019-07-01 Jan Beulich <jbeulich@suse.com>
1112 * i386-dis.c (EXdScalarS, MOD_EVEX_0F10_PREFIX_1,
1113 MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1,
1114 MOD_EVEX_0F11_PREFIX_3, EVEX_W_0F10_P_1_M_0,
1115 EVEX_W_0F10_P_1_M_1, EVEX_W_0F10_P_3_M_0, EVEX_W_0F10_P_3_M_1,
1116 EVEX_W_0F11_P_1_M_0, EVEX_W_0F11_P_1_M_1, EVEX_W_0F11_P_3_M_0,
1117 EVEX_W_0F11_P_3_M_1): Delete.
1118 (EVEX_W_0F10_P_1, EVEX_W_0F10_P_3, EVEX_W_0F11_P_1,
1119 EVEX_W_0F11_P_3): New.
1120 * i386-dis-evex-mod.h: Remove MOD_EVEX_0F10_PREFIX_1,
1121 MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1, and
1122 MOD_EVEX_0F11_PREFIX_3 table entries.
1123 * i386-dis-evex-prefix.h: Adjust PREFIX_EVEX_0F10 and
1124 PREFIX_EVEX_0F11 table entries.
1125 * i386-dis-evex-w.h: Replace EVEX_W_0F10_P_1_M_{0,1},
1126 EVEX_W_0F10_P_3_M_{0,1}, EVEX_W_0F11_P_1_M_{0,1}, and
1127 EVEX_W_0F11_P_3_M_{0,1} table entries.
1129 2019-07-01 Jan Beulich <jbeulich@suse.com>
1131 * i386-dis.c (EXdVex, EXdVexS, EXqVex, EXqVexS, XMVex):
1134 2019-06-27 H.J. Lu <hongjiu.lu@intel.com>
1137 * i386-dis-evex-len.h: Add EVEX_LEN_0F38C6_REG_1_PREFIX_2,
1138 EVEX_LEN_0F38C6_REG_2_PREFIX_2, EVEX_LEN_0F38C6_REG_5_PREFIX_2,
1139 EVEX_LEN_0F38C6_REG_6_PREFIX_2, EVEX_LEN_0F38C7_R_1_P_2_W_0,
1140 EVEX_LEN_0F38C7_R_1_P_2_W_1, EVEX_LEN_0F38C7_R_2_P_2_W_0,
1141 EVEX_LEN_0F38C7_R_2_P_2_W_1, EVEX_LEN_0F38C7_R_5_P_2_W_0,
1142 EVEX_LEN_0F38C7_R_5_P_2_W_1, EVEX_LEN_0F38C7_R_6_P_2_W_0 and
1143 EVEX_LEN_0F38C7_R_6_P_2_W_1.
1144 * i386-dis-evex-prefix.h: Update PREFIX_EVEX_0F38C6_REG_1,
1145 PREFIX_EVEX_0F38C6_REG_2, PREFIX_EVEX_0F38C6_REG_5 and
1146 PREFIX_EVEX_0F38C6_REG_6 entries.
1147 * i386-dis-evex-w.h: Update EVEX_W_0F38C7_R_1_P_2,
1148 EVEX_W_0F38C7_R_2_P_2, EVEX_W_0F38C7_R_5_P_2 and
1149 EVEX_W_0F38C7_R_6_P_2 entries.
1150 * i386-dis.c: Add EVEX_LEN_0F38C6_REG_1_PREFIX_2,
1151 EVEX_LEN_0F38C6_REG_2_PREFIX_2, EVEX_LEN_0F38C6_REG_5_PREFIX_2,
1152 EVEX_LEN_0F38C6_REG_6_PREFIX_2, EVEX_LEN_0F38C7_R_1_P_2_W_0,
1153 EVEX_LEN_0F38C7_R_1_P_2_W_1, EVEX_LEN_0F38C7_R_2_P_2_W_0,
1154 EVEX_LEN_0F38C7_R_2_P_2_W_1, EVEX_LEN_0F38C7_R_5_P_2_W_0,
1155 EVEX_LEN_0F38C7_R_5_P_2_W_1, EVEX_LEN_0F38C7_R_6_P_2_W_0 and
1156 EVEX_LEN_0F38C7_R_6_P_2_W_1 enums.
1158 2019-06-27 Jan Beulich <jbeulich@suse.com>
1160 * i386-dis.c (VEX_LEN_0F2A_P_1, VEX_LEN_0F2A_P_3,
1161 VEX_LEN_0F2C_P_1, VEX_LEN_0F2C_P_3, VEX_LEN_0F2D_P_1,
1162 VEX_LEN_0F2D_P_3): Delete.
1163 (vex_len_table): Move vcvtsi2ss, vcvtsi2sd, vcvttss2si,
1164 vcvttsd2si, vcvtss2si, and vcvtsd2si leaf entries ...
1165 (prefix_table): ... here.
1167 2019-06-27 Jan Beulich <jbeulich@suse.com>
1169 * i386-dis.c (Iq): Delete.
1171 (reg_table): Use it for lwpins, lwpval, and bextr. Use Edq for
1173 (vex_len_table): Use Edq for vcvtsi2ss, vcvtsi2sd. Use Gdq for
1174 vcvttss2si, vcvttsd2si, vcvtss2si, and vcvtsd2si.
1175 (OP_E_memory): Also honor needindex when deciding whether an
1176 address size prefix needs printing.
1177 (OP_I): Remove handling of q_mode. Add handling of d_mode.
1179 2019-06-26 Jim Wilson <jimw@sifive.com>
1182 * riscv-dis.c (riscv_disasemble_insn): Set info->endian_code.
1183 Set info->display_endian to info->endian_code.
1185 2019-06-25 Jan Beulich <jbeulich@suse.com>
1187 * i386-gen.c (operand_type_init): Correct OPERAND_TYPE_DEBUG
1188 entry. Drop OPERAND_TYPE_ACC entry. Add OPERAND_TYPE_ACC8 and
1189 OPERAND_TYPE_ACC16 entries. Adjust OPERAND_TYPE_ACC32 and
1190 OPERAND_TYPE_ACC64 entries.
1191 * i386-init.h: Re-generate.
1193 2019-06-25 Jan Beulich <jbeulich@suse.com>
1195 * i386-dis.c (Edqa, dqa_mode, EVEX_W_0F2A_P_1, EVEX_W_0F7B_P_1):
1197 (intel_operand_size, OP_E_register, OP_E_memory): Drop handling
1199 * i386-dis-evex-prefix.h: Move vcvtsi2ss and vcvtusi2ss leaf
1201 * i386-dis-evex-w.h: Drop EVEX_W_0F2A_P_1 and EVEX_W_0F7B_P_1
1202 entries. Use Edq for vcvtsi2sd and vcvtusi2sd.
1204 2019-06-25 Jan Beulich <jbeulich@suse.com>
1206 * i386-dis.c (OP_I64): Forword more cases to OP_I(). Drop local
1209 2019-06-25 Jan Beulich <jbeulich@suse.com>
1211 * i386-dis.c (prefix_table): Use Edq for cvtsi2ss and cvtsi2sd.
1212 Use Gdq for cvttss2si, cvttsd2si, cvtss2si, and cvtsd2si, and
1214 * i386-opc.tbl (movnti): Add IgnoreSize.
1215 * i386-tbl.h: Re-generate.
1217 2019-06-25 Jan Beulich <jbeulich@suse.com>
1219 * i386-opc.tbl (and): Mark Imm8S form for optimization.
1220 * i386-tbl.h: Re-generate.
1222 2019-06-21 H.J. Lu <hongjiu.lu@intel.com>
1224 * i386-dis-evex.h: Break into ...
1225 * i386-dis-evex-len.h: New file.
1226 * i386-dis-evex-mod.h: Likewise.
1227 * i386-dis-evex-prefix.h: Likewise.
1228 * i386-dis-evex-reg.h: Likewise.
1229 * i386-dis-evex-w.h: Likewise.
1230 * i386-dis.c: Include i386-dis-evex-reg.h, i386-dis-evex-prefix.h,
1231 i386-dis-evex.h, i386-dis-evex-len.h, i386-dis-evex-w.h and
1232 i386-dis-evex-mod.h.
1234 2019-06-19 H.J. Lu <hongjiu.lu@intel.com>
1237 * i386-dis-evex.h (evex_table): Update EVEX_W_0F3819_P_2,
1238 EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2, EVEX_W_0F385A_P_2 and
1240 (evex_len_table): Add EVEX_LEN_0F3819_P_2_W_0,
1241 EVEX_LEN_0F3819_P_2_W_1, EVEX_LEN_0F381A_P_2_W_0,
1242 EVEX_LEN_0F381A_P_2_W_1, EVEX_LEN_0F381B_P_2_W_0,
1243 EVEX_LEN_0F381B_P_2_W_1, EVEX_LEN_0F385A_P_2_W_0,
1244 EVEX_LEN_0F385A_P_2_W_1, EVEX_LEN_0F385B_P_2_W_0 and
1245 EVEX_LEN_0F385B_P_2_W_1.
1246 * i386-dis.c (EVEX_LEN_0F3819_P_2_W_0): New enum.
1247 (EVEX_LEN_0F3819_P_2_W_1): Likewise.
1248 (EVEX_LEN_0F381A_P_2_W_0): Likewise.
1249 (EVEX_LEN_0F381A_P_2_W_1): Likewise.
1250 (EVEX_LEN_0F381B_P_2_W_0): Likewise.
1251 (EVEX_LEN_0F381B_P_2_W_1): Likewise.
1252 (EVEX_LEN_0F385A_P_2_W_0): Likewise.
1253 (EVEX_LEN_0F385A_P_2_W_1): Likewise.
1254 (EVEX_LEN_0F385B_P_2_W_0): Likewise.
1255 (EVEX_LEN_0F385B_P_2_W_1): Likewise.
1257 2019-06-17 H.J. Lu <hongjiu.lu@intel.com>
1260 * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A23_P_2,
1261 EVEX_W_0F3A38_P_2, EVEX_W_0F3A39_P_2, EVEX_W_0F3A3A_P_2,
1262 EVEX_W_0F3A3B_P_2 and EVEX_W_0F3A43_P_2.
1263 (evex_len_table): Add EVEX_LEN_0F3A23_P_2_W_0,
1264 EVEX_LEN_0F3A23_P_2_W_1, EVEX_LEN_0F3A38_P_2_W_0,
1265 EVEX_LEN_0F3A38_P_2_W_1, EVEX_LEN_0F3A39_P_2_W_0,
1266 EVEX_LEN_0F3A39_P_2_W_1, EVEX_LEN_0F3A3A_P_2_W_0,
1267 EVEX_LEN_0F3A3A_P_2_W_1, EVEX_LEN_0F3A3B_P_2_W_0,
1268 EVEX_LEN_0F3A3B_P_2_W_1, EVEX_LEN_0F3A43_P_2_W_0 and
1269 EVEX_LEN_0F3A43_P_2_W_1.
1270 * i386-dis.c (EVEX_LEN_0F3A23_P_2_W_0): New enum.
1271 (EVEX_LEN_0F3A23_P_2_W_1): Likewise.
1272 (EVEX_LEN_0F3A38_P_2_W_0): Likewise.
1273 (EVEX_LEN_0F3A38_P_2_W_1): Likewise.
1274 (EVEX_LEN_0F3A39_P_2_W_0): Likewise.
1275 (EVEX_LEN_0F3A39_P_2_W_1): Likewise.
1276 (EVEX_LEN_0F3A3A_P_2_W_0): Likewise.
1277 (EVEX_LEN_0F3A3A_P_2_W_1): Likewise.
1278 (EVEX_LEN_0F3A3B_P_2_W_0): Likewise.
1279 (EVEX_LEN_0F3A3B_P_2_W_1): Likewise.
1280 (EVEX_LEN_0F3A43_P_2_W_0): Likewise.
1281 (EVEX_LEN_0F3A43_P_2_W_1): Likewise.
1283 2019-06-14 Nick Clifton <nickc@redhat.com>
1285 * po/fr.po; Updated French translation.
1287 2019-06-13 Stafford Horne <shorne@gmail.com>
1289 * or1k-asm.c: Regenerated.
1290 * or1k-desc.c: Regenerated.
1291 * or1k-desc.h: Regenerated.
1292 * or1k-dis.c: Regenerated.
1293 * or1k-ibld.c: Regenerated.
1294 * or1k-opc.c: Regenerated.
1295 * or1k-opc.h: Regenerated.
1296 * or1k-opinst.c: Regenerated.
1298 2019-06-12 Peter Bergner <bergner@linux.ibm.com>
1300 * ppc-opc.c (powerpc_opcodes) <ldmx>: Delete mnemonic.
1302 2019-06-05 H.J. Lu <hongjiu.lu@intel.com>
1305 * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A18_P_2,
1306 EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2 and EVEX_W_0F3A1B_P_2.
1307 (evex_len_table): EVEX_LEN_0F3A18_P_2_W_0,
1308 EVEX_LEN_0F3A18_P_2_W_1, EVEX_LEN_0F3A19_P_2_W_0,
1309 EVEX_LEN_0F3A19_P_2_W_1, EVEX_LEN_0F3A1A_P_2_W_0,
1310 EVEX_LEN_0F3A1A_P_2_W_1, EVEX_LEN_0F3A1B_P_2_W_0,
1311 EVEX_LEN_0F3A1B_P_2_W_1.
1312 * i386-dis.c (EVEX_LEN_0F3A18_P_2_W_0): New enum.
1313 (EVEX_LEN_0F3A18_P_2_W_1): Likewise.
1314 (EVEX_LEN_0F3A19_P_2_W_0): Likewise.
1315 (EVEX_LEN_0F3A19_P_2_W_1): Likewise.
1316 (EVEX_LEN_0F3A1A_P_2_W_0): Likewise.
1317 (EVEX_LEN_0F3A1A_P_2_W_1): Likewise.
1318 (EVEX_LEN_0F3A1B_P_2_W_0): Likewise.
1319 (EVEX_LEN_0F3A1B_P_2_W_1): Likewise.
1321 2019-06-04 H.J. Lu <hongjiu.lu@intel.com>
1324 * i386-dis.c (print_insn): Check for unused VEX.vvvv and
1325 EVEX.vvvv when disassembling VEX and EVEX instructions.
1326 (OP_VEX): Set vex.register_specifier to 0 after readding
1327 vex.register_specifier.
1328 (OP_Vex_2src_1): Likewise.
1329 (OP_Vex_2src_2): Likewise.
1330 (OP_LWP_E): Likewise.
1331 (OP_EX_Vex): Don't check vex.register_specifier.
1332 (OP_XMM_Vex): Likewise.
1334 2019-06-04 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1335 Lili Cui <lili.cui@intel.com>
1337 * i386-dis.c (enum): Add PREFIX_EVEX_0F3868, EVEX_W_0F3868_P_3.
1338 * i386-dis-evex.h (evex_table): Add AVX512_VP2INTERSECT
1340 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VP2INTERSECT_FLAGS,
1341 CPU_ANY_AVX512_VP2INTERSECT_FLAGS.
1342 (cpu_flags): Add CpuAVX512_VP2INTERSECT.
1343 * i386-opc.h (enum): Add CpuAVX512_VP2INTERSECT.
1344 (i386_cpu_flags): Add cpuavx512_vp2intersect.
1345 * i386-opc.tbl: Add AVX512_VP2INTERSECT insns.
1346 * i386-init.h: Regenerated.
1347 * i386-tbl.h: Likewise.
1349 2019-06-04 Xuepeng Guo <xuepeng.guo@intel.com>
1350 Lili Cui <lili.cui@intel.com>
1352 * doc/c-i386.texi: Document enqcmd.
1353 * testsuite/gas/i386/enqcmd-intel.d: New file.
1354 * testsuite/gas/i386/enqcmd-inval.l: Likewise.
1355 * testsuite/gas/i386/enqcmd-inval.s: Likewise.
1356 * testsuite/gas/i386/enqcmd.d: Likewise.
1357 * testsuite/gas/i386/enqcmd.s: Likewise.
1358 * testsuite/gas/i386/x86-64-enqcmd-intel.d: Likewise.
1359 * testsuite/gas/i386/x86-64-enqcmd-inval.l: Likewise.
1360 * testsuite/gas/i386/x86-64-enqcmd-inval.s: Likewise.
1361 * testsuite/gas/i386/x86-64-enqcmd.d: Likewise.
1362 * testsuite/gas/i386/x86-64-enqcmd.s: Likewise.
1363 * testsuite/gas/i386/i386.exp: Run enqcmd-intel, enqcmd-inval,
1364 enqcmd, x86-64-enqcmd-intel, x86-64-enqcmd-inval,
1367 2019-06-04 Alan Hayward <alan.hayward@arm.com>
1369 * arm-dis.c (is_mve_unpredictable): Remove spurious paranthesis.
1371 2019-06-03 Alan Modra <amodra@gmail.com>
1373 * ppc-dis.c (prefix_opcd_indices): Correct size.
1375 2019-05-28 H.J. Lu <hongjiu.lu@intel.com>
1378 * i386-opc.tbl: Add CheckRegSize to AVX512_BF16 instructions with
1380 * i386-tbl.h: Regenerated.
1382 2019-05-24 Alan Modra <amodra@gmail.com>
1384 * po/POTFILES.in: Regenerate.
1386 2019-05-24 Peter Bergner <bergner@linux.ibm.com>
1387 Alan Modra <amodra@gmail.com>
1389 * ppc-opc.c (insert_d34, extract_d34, insert_nsi34, extract_nsi34),
1390 (insert_pcrel, extract_pcrel, extract_pcrel0): New functions.
1391 (extract_esync, extract_raq, extract_tbr, extract_sxl): Comment.
1392 (powerpc_operands <D34, SI34, NSI34, PRA0, PRAQ, PCREL, PCREL0,
1393 XTOP>): Define and add entries.
1394 (P8LS, PMLS, P_D_MASK, P_DRAPCREL_MASK): Define.
1395 (prefix_opcodes): Add pli, paddi, pla, psubi, plwz, plbz, pstw,
1396 pstb, plhz, plha, psth, plfs, plfd, pstfs, pstfd, plq, plxsd,
1397 plxssp, pld, plwa, pstxsd, pstxssp, pstxv, pstd, and pstq.
1399 2019-05-24 Peter Bergner <bergner@linux.ibm.com>
1400 Alan Modra <amodra@gmail.com>
1402 * ppc-dis.c (ppc_opts): Add "future" entry.
1403 (PREFIX_OPCD_SEGS): Define.
1404 (prefix_opcd_indices): New array.
1405 (disassemble_init_powerpc): Initialize prefix_opcd_indices.
1406 (lookup_prefix): New function.
1407 (print_insn_powerpc): Handle 64-bit prefix instructions.
1408 * ppc-opc.c (PREFIX_OP, PREFIX_FORM, SUFFIX_MASK, PREFIX_MASK),
1409 (PMRR, POWERXX): Define.
1410 (prefix_opcodes): New instruction table.
1411 (prefix_num_opcodes): New constant.
1413 2019-05-23 Jose E. Marchesi <jose.marchesi@oracle.com>
1415 * configure.ac (SHARED_DEPENDENCIES): Add case for bfd_bpf_arch.
1416 * configure: Regenerated.
1417 * Makefile.am: Add rules for the files generated from cpu/bpf.cpu
1419 (HFILES): Add bpf-desc.h and bpf-opc.h.
1420 (TARGET_LIBOPCODES_CFILES): Add bpf-asm.c, bpf-desc.c, bpf-dis.c,
1421 bpf-ibld.c and bpf-opc.c.
1423 * Makefile.in: Regenerated.
1424 * disassemble.c (ARCH_bpf): Define.
1425 (disassembler): Add case for bfd_arch_bpf.
1426 (disassemble_init_for_target): Likewise.
1427 (enum epbf_isa_attr): Define.
1428 * disassemble.h: extern print_insn_bpf.
1429 * bpf-asm.c: Generated.
1430 * bpf-opc.h: Likewise.
1431 * bpf-opc.c: Likewise.
1432 * bpf-ibld.c: Likewise.
1433 * bpf-dis.c: Likewise.
1434 * bpf-desc.h: Likewise.
1435 * bpf-desc.c: Likewise.
1437 2019-05-21 Sudakshina Das <sudi.das@arm.com>
1439 * arm-dis.c (coprocessor_opcodes): New instructions for VMRS
1440 and VMSR with the new operands.
1442 2019-05-21 Sudakshina Das <sudi.das@arm.com>
1444 * arm-dis.c (enum mve_instructions): New enum
1445 for csinc, csinv, csneg, csel, cset, csetm, cinv, cinv
1447 (mve_opcodes): New instructions as above.
1448 (is_mve_encoding_conflict): Add cases for csinc, csinv,
1450 (print_insn_mve): Accept new %<bitfield>c and %<bitfield>C.
1452 2019-05-21 Sudakshina Das <sudi.das@arm.com>
1454 * arm-dis.c (emun mve_instructions): Updated for new instructions.
1455 (mve_opcodes): New instructions for asrl, lsll, lsrl, sqrshrl,
1456 sqrshr, sqshl, sqshll, srshr, srshrl, uqrshll, uqrshl, uqshll,
1457 uqshl, urshrl and urshr.
1458 (is_mve_okay_in_it): Add new instructions to TRUE list.
1459 (is_mve_unpredictable): Add cases for UNPRED_R13 and UNPRED_R15.
1460 (print_insn_mve): Updated to accept new %j,
1461 %<bitfield>m and %<bitfield>n patterns.
1463 2019-05-21 Faraz Shahbazker <fshahbazker@wavecomp.com>
1465 * mips-opc.c (mips_builtin_opcodes): Change source register
1466 constraint for DAUI.
1468 2019-05-20 Nick Clifton <nickc@redhat.com>
1470 * po/fr.po: Updated French translation.
1472 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1473 Michael Collison <michael.collison@arm.com>
1475 * arm-dis.c (thumb32_opcodes): Add new instructions.
1476 (enum mve_instructions): Likewise.
1477 (enum mve_undefined): Add new reasons.
1478 (is_mve_encoding_conflict): Handle new instructions.
1479 (is_mve_undefined): Likewise.
1480 (is_mve_unpredictable): Likewise.
1481 (print_mve_undefined): Likewise.
1482 (print_mve_size): Likewise.
1484 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1485 Michael Collison <michael.collison@arm.com>
1487 * arm-dis.c (thumb32_opcodes): Add new instructions.
1488 (enum mve_instructions): Likewise.
1489 (is_mve_encoding_conflict): Handle new instructions.
1490 (is_mve_undefined): Likewise.
1491 (is_mve_unpredictable): Likewise.
1492 (print_mve_size): Likewise.
1494 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1495 Michael Collison <michael.collison@arm.com>
1497 * arm-dis.c (thumb32_opcodes): Add new instructions.
1498 (enum mve_instructions): Likewise.
1499 (is_mve_encoding_conflict): Likewise.
1500 (is_mve_unpredictable): Likewise.
1501 (print_mve_size): Likewise.
1503 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1504 Michael Collison <michael.collison@arm.com>
1506 * arm-dis.c (thumb32_opcodes): Add new instructions.
1507 (enum mve_instructions): Likewise.
1508 (is_mve_encoding_conflict): Handle new instructions.
1509 (is_mve_undefined): Likewise.
1510 (is_mve_unpredictable): Likewise.
1511 (print_mve_size): Likewise.
1513 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1514 Michael Collison <michael.collison@arm.com>
1516 * arm-dis.c (thumb32_opcodes): Add new instructions.
1517 (enum mve_instructions): Likewise.
1518 (is_mve_encoding_conflict): Handle new instructions.
1519 (is_mve_undefined): Likewise.
1520 (is_mve_unpredictable): Likewise.
1521 (print_mve_size): Likewise.
1522 (print_insn_mve): Likewise.
1524 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1525 Michael Collison <michael.collison@arm.com>
1527 * arm-dis.c (thumb32_opcodes): Add new instructions.
1528 (print_insn_thumb32): Handle new instructions.
1530 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1531 Michael Collison <michael.collison@arm.com>
1533 * arm-dis.c (enum mve_instructions): Add new instructions.
1534 (enum mve_undefined): Add new reasons.
1535 (is_mve_encoding_conflict): Handle new instructions.
1536 (is_mve_undefined): Likewise.
1537 (is_mve_unpredictable): Likewise.
1538 (print_mve_undefined): Likewise.
1539 (print_mve_size): Likewise.
1540 (print_mve_shift_n): Likewise.
1541 (print_insn_mve): Likewise.
1543 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1544 Michael Collison <michael.collison@arm.com>
1546 * arm-dis.c (enum mve_instructions): Add new instructions.
1547 (is_mve_encoding_conflict): Handle new instructions.
1548 (is_mve_unpredictable): Likewise.
1549 (print_mve_rotate): Likewise.
1550 (print_mve_size): Likewise.
1551 (print_insn_mve): Likewise.
1553 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1554 Michael Collison <michael.collison@arm.com>
1556 * arm-dis.c (enum mve_instructions): Add new instructions.
1557 (is_mve_encoding_conflict): Handle new instructions.
1558 (is_mve_unpredictable): Likewise.
1559 (print_mve_size): Likewise.
1560 (print_insn_mve): Likewise.
1562 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1563 Michael Collison <michael.collison@arm.com>
1565 * arm-dis.c (enum mve_instructions): Add new instructions.
1566 (enum mve_undefined): Add new reasons.
1567 (is_mve_encoding_conflict): Handle new instructions.
1568 (is_mve_undefined): Likewise.
1569 (is_mve_unpredictable): Likewise.
1570 (print_mve_undefined): Likewise.
1571 (print_mve_size): Likewise.
1572 (print_insn_mve): Likewise.
1574 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1575 Michael Collison <michael.collison@arm.com>
1577 * arm-dis.c (enum mve_instructions): Add new instructions.
1578 (is_mve_encoding_conflict): Handle new instructions.
1579 (is_mve_undefined): Likewise.
1580 (is_mve_unpredictable): Likewise.
1581 (print_mve_size): Likewise.
1582 (print_insn_mve): Likewise.
1584 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1585 Michael Collison <michael.collison@arm.com>
1587 * arm-dis.c (enum mve_instructions): Add new instructions.
1588 (enum mve_unpredictable): Add new reasons.
1589 (enum mve_undefined): Likewise.
1590 (is_mve_okay_in_it): Handle new isntructions.
1591 (is_mve_encoding_conflict): Likewise.
1592 (is_mve_undefined): Likewise.
1593 (is_mve_unpredictable): Likewise.
1594 (print_mve_vmov_index): Likewise.
1595 (print_simd_imm8): Likewise.
1596 (print_mve_undefined): Likewise.
1597 (print_mve_unpredictable): Likewise.
1598 (print_mve_size): Likewise.
1599 (print_insn_mve): Likewise.
1601 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1602 Michael Collison <michael.collison@arm.com>
1604 * arm-dis.c (enum mve_instructions): Add new instructions.
1605 (enum mve_unpredictable): Add new reasons.
1606 (enum mve_undefined): Likewise.
1607 (is_mve_encoding_conflict): Handle new instructions.
1608 (is_mve_undefined): Likewise.
1609 (is_mve_unpredictable): Likewise.
1610 (print_mve_undefined): Likewise.
1611 (print_mve_unpredictable): Likewise.
1612 (print_mve_rounding_mode): Likewise.
1613 (print_mve_vcvt_size): Likewise.
1614 (print_mve_size): Likewise.
1615 (print_insn_mve): Likewise.
1617 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1618 Michael Collison <michael.collison@arm.com>
1620 * arm-dis.c (enum mve_instructions): Add new instructions.
1621 (enum mve_unpredictable): Add new reasons.
1622 (enum mve_undefined): Likewise.
1623 (is_mve_undefined): Handle new instructions.
1624 (is_mve_unpredictable): Likewise.
1625 (print_mve_undefined): Likewise.
1626 (print_mve_unpredictable): Likewise.
1627 (print_mve_size): Likewise.
1628 (print_insn_mve): Likewise.
1630 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1631 Michael Collison <michael.collison@arm.com>
1633 * arm-dis.c (enum mve_instructions): Add new instructions.
1634 (enum mve_undefined): Add new reasons.
1635 (insns): Add new instructions.
1636 (is_mve_encoding_conflict):
1637 (print_mve_vld_str_addr): New print function.
1638 (is_mve_undefined): Handle new instructions.
1639 (is_mve_unpredictable): Likewise.
1640 (print_mve_undefined): Likewise.
1641 (print_mve_size): Likewise.
1642 (print_insn_coprocessor_1): Handle MVE VLDR, VSTR instructions.
1643 (print_insn_mve): Handle new operands.
1645 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1646 Michael Collison <michael.collison@arm.com>
1648 * arm-dis.c (enum mve_instructions): Add new instructions.
1649 (enum mve_unpredictable): Add new reasons.
1650 (is_mve_encoding_conflict): Handle new instructions.
1651 (is_mve_unpredictable): Likewise.
1652 (mve_opcodes): Add new instructions.
1653 (print_mve_unpredictable): Handle new reasons.
1654 (print_mve_register_blocks): New print function.
1655 (print_mve_size): Handle new instructions.
1656 (print_insn_mve): Likewise.
1658 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1659 Michael Collison <michael.collison@arm.com>
1661 * arm-dis.c (enum mve_instructions): Add new instructions.
1662 (enum mve_unpredictable): Add new reasons.
1663 (enum mve_undefined): Likewise.
1664 (is_mve_encoding_conflict): Handle new instructions.
1665 (is_mve_undefined): Likewise.
1666 (is_mve_unpredictable): Likewise.
1667 (coprocessor_opcodes): Move NEON VDUP from here...
1668 (neon_opcodes): ... to here.
1669 (mve_opcodes): Add new instructions.
1670 (print_mve_undefined): Handle new reasons.
1671 (print_mve_unpredictable): Likewise.
1672 (print_mve_size): Handle new instructions.
1673 (print_insn_neon): Handle vdup.
1674 (print_insn_mve): Handle new operands.
1676 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1677 Michael Collison <michael.collison@arm.com>
1679 * arm-dis.c (enum mve_instructions): Add new instructions.
1680 (enum mve_unpredictable): Add new values.
1681 (mve_opcodes): Add new instructions.
1682 (vec_condnames): New array with vector conditions.
1683 (mve_predicatenames): New array with predicate suffixes.
1684 (mve_vec_sizename): New array with vector sizes.
1685 (enum vpt_pred_state): New enum with vector predication states.
1686 (struct vpt_block): New struct type for vpt blocks.
1687 (vpt_block_state): Global struct to keep track of state.
1688 (mve_extract_pred_mask): New helper function.
1689 (num_instructions_vpt_block): Likewise.
1690 (mark_outside_vpt_block): Likewise.
1691 (mark_inside_vpt_block): Likewise.
1692 (invert_next_predicate_state): Likewise.
1693 (update_next_predicate_state): Likewise.
1694 (update_vpt_block_state): Likewise.
1695 (is_vpt_instruction): Likewise.
1696 (is_mve_encoding_conflict): Add entries for new instructions.
1697 (is_mve_unpredictable): Likewise.
1698 (print_mve_unpredictable): Handle new cases.
1699 (print_instruction_predicate): Likewise.
1700 (print_mve_size): New function.
1701 (print_vec_condition): New function.
1702 (print_insn_mve): Handle vpt blocks and new print operands.
1704 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1706 * arm-dis.c (print_insn_coprocessor_1): Disable the use of coprocessors
1707 8, 14 and 15 for Armv8.1-M Mainline.
1709 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1710 Michael Collison <michael.collison@arm.com>
1712 * arm-dis.c (enum mve_instructions): New enum.
1713 (enum mve_unpredictable): Likewise.
1714 (enum mve_undefined): Likewise.
1715 (struct mopcode32): New struct.
1716 (is_mve_okay_in_it): New function.
1717 (is_mve_architecture): Likewise.
1718 (arm_decode_field): Likewise.
1719 (arm_decode_field_multiple): Likewise.
1720 (is_mve_encoding_conflict): Likewise.
1721 (is_mve_undefined): Likewise.
1722 (is_mve_unpredictable): Likewise.
1723 (print_mve_undefined): Likewise.
1724 (print_mve_unpredictable): Likewise.
1725 (print_insn_coprocessor_1): Use arm_decode_field_multiple.
1726 (print_insn_mve): New function.
1727 (print_insn_thumb32): Handle MVE architecture.
1728 (select_arm_features): Force thumb for Armv8.1-m Mainline.
1730 2019-05-10 Nick Clifton <nickc@redhat.com>
1733 * ia64-opc.c (ia64_find_matching_opcode): Check for reaching the
1734 end of the table prematurely.
1736 2019-05-10 Faraz Shahbazker <fshahbazker@wavecomp.com>
1738 * mips-opc.c (mips_opcodes): Enable ADD, SUB, DADD and DSUB
1741 2019-05-11 Alan Modra <amodra@gmail.com>
1743 * ppc-dis.c (print_insn_powerpc) Don't skip optional operands
1744 when -Mraw is in effect.
1746 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1748 * aarch64-dis-2.c: Regenerate.
1749 * aarch64-tbl.h (OP_SVE_BBU): New variant set.
1750 (OP_SVE_BBB): New variant set.
1751 (OP_SVE_DDDD): New variant set.
1752 (OP_SVE_HHH): New variant set.
1753 (OP_SVE_HHHU): New variant set.
1754 (OP_SVE_SSS): New variant set.
1755 (OP_SVE_SSSU): New variant set.
1756 (OP_SVE_SHH): New variant set.
1757 (OP_SVE_SBBU): New variant set.
1758 (OP_SVE_DSS): New variant set.
1759 (OP_SVE_DHHU): New variant set.
1760 (OP_SVE_VMV_HSD_BHS): New variant set.
1761 (OP_SVE_VVU_HSD_BHS): New variant set.
1762 (OP_SVE_VVVU_SD_BH): New variant set.
1763 (OP_SVE_VVVU_BHSD): New variant set.
1764 (OP_SVE_VVV_QHD_DBS): New variant set.
1765 (OP_SVE_VVV_HSD_BHS): New variant set.
1766 (OP_SVE_VVV_HSD_BHS2): New variant set.
1767 (OP_SVE_VVV_BHS_HSD): New variant set.
1768 (OP_SVE_VV_BHS_HSD): New variant set.
1769 (OP_SVE_VVV_SD): New variant set.
1770 (OP_SVE_VVU_BHS_HSD): New variant set.
1771 (OP_SVE_VZVV_SD): New variant set.
1772 (OP_SVE_VZVV_BH): New variant set.
1773 (OP_SVE_VZV_SD): New variant set.
1774 (aarch64_opcode_table): Add sve2 instructions.
1776 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1778 * aarch64-asm-2.c: Regenerated.
1779 * aarch64-dis-2.c: Regenerated.
1780 * aarch64-opc-2.c: Regenerated.
1781 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1782 for SVE_SHLIMM_UNPRED_22.
1783 (aarch64_print_operand): Add printing for SVE_SHLIMM_UNPRED_22.
1784 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHLIMM_UNPRED_22
1787 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1789 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1790 sve_size_tsz_bhs iclass encode.
1791 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1792 sve_size_tsz_bhs iclass decode.
1794 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1796 * aarch64-asm-2.c: Regenerated.
1797 * aarch64-dis-2.c: Regenerated.
1798 * aarch64-opc-2.c: Regenerated.
1799 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1800 for SVE_Zm4_11_INDEX.
1801 (aarch64_print_operand): Add printing for SVE_Zm4_11_INDEX.
1802 (fields): Handle SVE_i2h field.
1803 * aarch64-opc.h (enum aarch64_field_kind): New SVE_i2h field.
1804 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm4_11_INDEX operand.
1806 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1808 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1809 sve_shift_tsz_bhsd iclass encode.
1810 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1811 sve_shift_tsz_bhsd iclass decode.
1813 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1815 * aarch64-asm-2.c: Regenerated.
1816 * aarch64-dis-2.c: Regenerated.
1817 * aarch64-opc-2.c: Regenerated.
1818 * aarch64-asm.c (aarch64_ins_sve_shrimm):
1819 (aarch64_encode_variant_using_iclass): Handle
1820 sve_shift_tsz_hsd iclass encode.
1821 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1822 sve_shift_tsz_hsd iclass decode.
1823 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1824 for SVE_SHRIMM_UNPRED_22.
1825 (aarch64_print_operand): Add printing for SVE_SHRIMM_UNPRED_22.
1826 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHRIMM_UNPRED_22
1829 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1831 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1832 sve_size_013 iclass encode.
1833 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1834 sve_size_013 iclass decode.
1836 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1838 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1839 sve_size_bh iclass encode.
1840 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1841 sve_size_bh iclass decode.
1843 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1845 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1846 sve_size_sd2 iclass encode.
1847 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1848 sve_size_sd2 iclass decode.
1849 * aarch64-opc.c (fields): Handle SVE_sz2 field.
1850 * aarch64-opc.h (enum aarch64_field_kind): New SVE_sz2 field.
1852 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1854 * aarch64-asm-2.c: Regenerated.
1855 * aarch64-dis-2.c: Regenerated.
1856 * aarch64-opc-2.c: Regenerated.
1857 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1859 (aarch64_print_operand): Add printing for SVE_ADDR_ZX.
1860 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_ADDR_ZX operand.
1862 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1864 * aarch64-asm-2.c: Regenerated.
1865 * aarch64-dis-2.c: Regenerated.
1866 * aarch64-opc-2.c: Regenerated.
1867 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1868 for SVE_Zm3_11_INDEX.
1869 (aarch64_print_operand): Add printing for SVE_Zm3_11_INDEX.
1870 (fields): Handle SVE_i3l and SVE_i3h2 fields.
1871 * aarch64-opc.h (enum aarch64_field_kind): New SVE_i3l and SVE_i3h2
1873 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm3_11_INDEX operand.
1875 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1877 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1878 sve_size_hsd2 iclass encode.
1879 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1880 sve_size_hsd2 iclass decode.
1881 * aarch64-opc.c (fields): Handle SVE_size field.
1882 * aarch64-opc.h (enum aarch64_field_kind): New SVE_size field.
1884 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1886 * aarch64-asm-2.c: Regenerated.
1887 * aarch64-dis-2.c: Regenerated.
1888 * aarch64-opc-2.c: Regenerated.
1889 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1891 (aarch64_print_operand): Add printing for SVE_IMM_ROT3.
1892 (fields): Handle SVE_rot3 field.
1893 * aarch64-opc.h (enum aarch64_field_kind): New SVE_rot3 field.
1894 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_IMM_ROT3 operand.
1896 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1898 * aarch64-opc.c (verify_constraints): Check for movprfx for sve2
1901 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1904 (aarch64_feature_sve2, aarch64_feature_sve2aes,
1905 aarch64_feature_sve2sha3, aarch64_feature_sve2sm4,
1906 aarch64_feature_sve2bitperm): New feature sets.
1907 (SVE2, SVE2_AES, SVE2_SHA3, SVE2_SM4, SVE2_BITPERM): New macros
1908 for feature set addresses.
1909 (SVE2_INSN, SVE2_INSNC, SVE2AES_INSN, SVE2SHA3_INSN,
1910 SVE2SM4_INSN, SVE2SM4_INSNC, SVE2BITPERM_INSN): New macros.
1912 2019-05-06 Andrew Bennett <andrew.bennett@imgtec.com>
1913 Faraz Shahbazker <fshahbazker@wavecomp.com>
1915 * mips-dis.c (mips_calculate_combination_ases): Add ISA
1916 argument and set ASE_EVA_R6 appropriately.
1917 (set_default_mips_dis_options): Pass ISA to above.
1918 (parse_mips_dis_option): Likewise.
1919 * mips-opc.c (EVAR6): New macro.
1920 (mips_builtin_opcodes): Add llwpe, scwpe.
1922 2019-05-01 Sudakshina Das <sudi.das@arm.com>
1924 * aarch64-asm-2.c: Regenerated.
1925 * aarch64-dis-2.c: Regenerated.
1926 * aarch64-opc-2.c: Regenerated.
1927 * aarch64-opc.c (operand_general_constraint_met_p): Add case for
1928 AARCH64_OPND_TME_UIMM16.
1929 (aarch64_print_operand): Likewise.
1930 * aarch64-tbl.h (QL_IMM_NIL): New.
1933 (struct aarch64_opcode): Add tstart, tcommit, ttest and tcancel.
1935 2019-04-29 John Darrington <john@darrington.wattle.id.au>
1937 * s12z-opc.c (shift_discrim): Return OP_INVALID when reading fails.
1939 2019-04-26 Andrew Bennett <andrew.bennett@imgtec.com>
1940 Faraz Shahbazker <fshahbazker@wavecomp.com>
1942 * mips-opc.c (mips_builtin_opcodes): Add llwp, lldp, scwp, scdp.
1944 2019-04-24 John Darrington <john@darrington.wattle.id.au>
1946 * s12z-opc.h: Add extern "C" bracketing to help
1947 users who wish to use this interface in c++ code.
1949 2019-04-24 John Darrington <john@darrington.wattle.id.au>
1951 * s12z-opc.c (bm_decode): Handle bit map operations with the
1954 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
1956 * arm-dis.c (coprocessor_opcodes): Document new %J and %K format
1957 specifier. Add entries for VLDR and VSTR of system registers.
1958 (print_insn_coprocessor): Forbid coprocessor numbers 8, 14 and 15 in
1959 coprocessor instructions on Armv8.1-M Mainline targets. Add handling
1960 of %J and %K format specifier.
1962 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
1964 * arm-dis.c (coprocessor_opcodes): Document new %C format control code.
1965 Add new entries for VSCCLRM instruction.
1966 (print_insn_coprocessor): Handle new %C format control code.
1968 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
1970 * arm-dis.c (enum isa): New enum.
1971 (struct sopcode32): New structure.
1972 (coprocessor_opcodes): change type of entries to struct sopcode32 and
1973 set isa field of all current entries to ANY.
1974 (print_insn_coprocessor): Change type of insn to struct sopcode32.
1975 Only match an entry if its isa field allows the current mode.
1977 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
1979 * arm-dis.c (thumb_opcodes): Document %n control code. Add entry for
1981 (print_insn_thumb32): Add logic to print %n CLRM register list.
1983 2019-04-15 Sudakshina Das <sudi.das@arm.com>
1985 * arm-dis.c (print_insn_thumb32): Updated to accept new %P
1988 2019-04-15 Sudakshina Das <sudi.das@arm.com>
1990 * arm-dis.c (thumb32_opcodes): New instruction bfcsel.
1991 (print_insn_thumb32): Edit the switch case for %Z.
1993 2019-04-15 Sudakshina Das <sudi.das@arm.com>
1995 * arm-dis.c (print_insn_thumb32): Updated to accept new %Z pattern.
1997 2019-04-15 Sudakshina Das <sudi.das@arm.com>
1999 * arm-dis.c (thumb32_opcodes): New instruction bfl.
2001 2019-04-15 Sudakshina Das <sudi.das@arm.com>
2003 * arm-dis.c (print_insn_thumb32): Updated to accept new %Y pattern.
2005 2019-04-15 Sudakshina Das <sudi.das@arm.com>
2007 * arm-dis.c (print_insn_thumb32): Add '%<bitfield>S' to print an
2008 Arm register with r13 and r15 unpredictable.
2009 (thumb32_opcodes): New instructions for bfx and bflx.
2011 2019-04-15 Sudakshina Das <sudi.das@arm.com>
2013 * arm-dis.c (thumb32_opcodes): New instructions for bf.
2015 2019-04-15 Sudakshina Das <sudi.das@arm.com>
2017 * arm-dis.c (print_insn_thumb32): Updated to accept new %W pattern.
2019 2019-04-15 Sudakshina Das <sudi.das@arm.com>
2021 * arm-dis.c (print_insn_thumb32): Updated to accept new %G pattern.
2023 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
2025 * arm-dis.c (select_arm_features): Add logic for Armv8.1-M Mainline.
2027 2019-04-12 John Darrington <john@darrington.wattle.id.au>
2029 s12z-dis.c, s12z-opc.c, s12z-opc.h: Replace "operator" with
2030 "optr". ("operator" is a reserved word in c++).
2032 2019-04-11 Sudakshina Das <sudi.das@arm.com>
2034 * aarch64-opc.c (aarch64_print_operand): Add case for
2036 (verify_constraints): Likewise.
2037 * aarch64-tbl.h (QL_LDST_AT): Update to add SP qualifier.
2038 (struct aarch64_opcode): Update stg, stzg, st2g, stz2g instructions
2039 to accept Rt|SP as first operand.
2040 (AARCH64_OPERANDS): Add new Rt_SP.
2041 * aarch64-asm-2.c: Regenerated.
2042 * aarch64-dis-2.c: Regenerated.
2043 * aarch64-opc-2.c: Regenerated.
2045 2019-04-11 Sudakshina Das <sudi.das@arm.com>
2047 * aarch64-asm-2.c: Regenerated.
2048 * aarch64-dis-2.c: Likewise.
2049 * aarch64-opc-2.c: Likewise.
2050 * aarch64-tbl.h (aarch64_opcode): Add new ldgm and stgm.
2052 2019-04-09 Robert Suchanek <robert.suchanek@mips.com>
2054 * mips-opc.c (mips_builtin_opcodes): Add RDHWR rt rd sel.
2056 2019-04-08 H.J. Lu <hongjiu.lu@intel.com>
2058 * i386-opc.tbl: Consolidate AVX512 BF16 entries.
2059 * i386-init.h: Regenerated.
2061 2019-04-07 Alan Modra <amodra@gmail.com>
2063 * ppc-dis.c (print_insn_powerpc): Use a tiny state machine
2064 op_separator to control printing of spaces, comma and parens
2065 rather than need_comma, need_paren and spaces vars.
2067 2019-04-07 Alan Modra <amodra@gmail.com>
2070 * arm-dis.c (print_insn_coprocessor): Correct bracket placement.
2071 (print_insn_neon, print_insn_arm): Likewise.
2073 2019-04-05 Xuepeng Guo <xuepeng.guo@intel.com>
2075 * i386-dis-evex.h (evex_table): Updated to support BF16
2077 * i386-dis.c (enum): Add EVEX_W_0F3852_P_1, EVEX_W_0F3872_P_1
2078 and EVEX_W_0F3872_P_3.
2079 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_BF16_FLAGS.
2080 (cpu_flags): Add bitfield for CpuAVX512_BF16.
2081 * i386-opc.h (enum): Add CpuAVX512_BF16.
2082 (i386_cpu_flags): Add bitfield for cpuavx512_bf16.
2083 * i386-opc.tbl: Add AVX512 BF16 instructions.
2084 * i386-init.h: Regenerated.
2085 * i386-tbl.h: Likewise.
2087 2019-04-05 Alan Modra <amodra@gmail.com>
2089 * ppc-opc.c (XLBH_MASK): Subtract off BH field from BB_MASK.
2090 (powerpc_opcodes): Reorder bcctr and bclr extended mnemonics
2091 to favour printing of "-" branch hint when using the "y" bit.
2092 Allow BH field on bc{ctr,lr,tar}{,l}{-,+}.
2094 2019-04-05 Alan Modra <amodra@gmail.com>
2096 * ppc-dis.c (print_insn_powerpc): Delay printing spaces after
2097 opcode until first operand is output.
2099 2019-04-04 Peter Bergner <bergner@linux.ibm.com>
2102 * ppc-opc.c (valid_bo_pre_v2): Add comments.
2103 (valid_bo_post_v2): Add support for 'at' branch hints.
2104 (insert_bo): Only error on branch on ctr.
2105 (get_bo_hint_mask): New function.
2106 (insert_boe): Add new 'branch_taken' formal argument. Add support
2107 for inserting 'at' branch hints.
2108 (extract_boe): Add new 'branch_taken' formal argument. Add support
2109 for extracting 'at' branch hints.
2110 (insert_bom, extract_bom, insert_bop, extract_bop): New functions.
2111 (BOE): Delete operand.
2112 (BOM, BOP): New operands.
2114 (XLYLK, XLYLK_MASK, XLYBB_MASK): Delete.
2115 (powerpc_opcodes) <bc-, bcl-, bca-, bcla-, bclr-, bclrl-, bcctr-,
2116 bcctrl-, bctar-, bctarl->: Replace BOE with BOM.
2117 (powerpc_opcodes) <bc+, bcl+, bca+, bcla+, bclr+, bclrl+, bcctr+,
2118 bcctrl+, bctar+, bctarl+>: Replace BOE with BOP.
2119 <bdnztar, bdnztarl, bdztar, bdztarl, btar, btarl, bdnztar-, bdnztarl-,
2120 bdnztar+, bdnztarl+, bdztar-, bdztarl-, bdztar+, bdztarl+, bgetar,
2121 bnltar, bgetarl, bnltarl, bletar, bngtar, bletarl, bngtarl, bnetar,
2122 bnetarl, bnstar, bnutar, bnstarl, bnutarl, bgetar-, bnltar-, bgetarl-,
2123 bnltarl-, bletar-, bngtar-, bletarl-, bngtarl-, bnetar-, bnetarl-,
2124 bnstar-, bnutar-, bnstarl-, bnutarl-, bgetar+, bnltar+, bgetarl+,
2125 bnltarl+, bletar+, bngtar+, bletarl+, bngtarl+, bnetar+, bnetarl+,
2126 bnstar+, bnutar+, bnstarl+, bnutarl+, blttar, blttarl, bgttar, bgttarl,
2127 beqtar, beqtarl, bsotar, buntar, bsotarl, buntarl, blttar-, blttarl-,
2128 bgttar-, bgttarl-, beqtar-, beqtarl-, bsotar-, buntar-, bsotarl-,
2129 buntarl-, blttar+, blttarl+, bgttar+, bgttarl+, beqtar+, beqtarl+,
2130 bsotar+, buntar+, bsotarl+, buntarl+, bdnzftar, bdnzftarl, bdzftar,
2131 bdzftarl, bftar, bftarl, bftar-, bftarl-, bftar+, bftarl+, bdnzttar,
2132 bdnzttarl, bdzttar, bdzttarl, bttar, bttarl, bttar-, bttarl-, bttar+,
2133 bttarl+>: New extended mnemonics.
2135 2019-03-28 Alan Modra <amodra@gmail.com>
2138 * ppc-opc.c (BTF): Define.
2139 (powerpc_opcodes): Use for mtfsb*.
2140 * ppc-dis.c (print_insn_powerpc): Print fields with both
2141 PPC_OPERAND_CR_REG and PPC_OPERAND_CR_BIT as a plain number.
2143 2019-03-25 Tamar Christina <tamar.christina@arm.com>
2145 * arm-dis.c (struct arm_private_data): Remove has_mapping_symbols.
2146 (mapping_symbol_for_insn): Implement new algorithm.
2147 (print_insn): Remove duplicate code.
2149 2019-03-25 Tamar Christina <tamar.christina@arm.com>
2151 * aarch64-dis.c (print_insn_aarch64):
2154 2019-03-25 Tamar Christina <tamar.christina@arm.com>
2156 * aarch64-dis.c (print_insn_aarch64): Update the mapping symbol search
2159 2019-03-25 Tamar Christina <tamar.christina@arm.com>
2161 * aarch64-dis.c (last_stop_offset): New.
2162 (print_insn_aarch64): Use stop_offset.
2164 2019-03-19 H.J. Lu <hongjiu.lu@intel.com>
2167 * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS to
2169 * i386-init.h: Regenerated.
2171 2019-03-18 H.J. Lu <hongjiu.lu@intel.com>
2174 * i386-opc.tbl: Add Optimize to vmovdqa32, vmovdqa64, vmovdqu8,
2175 vmovdqu16, vmovdqu32 and vmovdqu64.
2176 * i386-tbl.h: Regenerated.
2178 2019-03-12 Andreas Krebbel <krebbel@linux.ibm.com>
2180 * s390-opc.txt: Rename selhhhr to selfhr. Remove optional operand
2181 from vstrszb, vstrszh, and vstrszf.
2183 2019-03-12 Andreas Krebbel <krebbel@linux.ibm.com>
2185 * s390-opc.txt: Add instruction descriptions.
2187 2019-02-08 Jim Wilson <jimw@sifive.com>
2189 * riscv-opc.c (riscv_opcodes) <beq>: Use Cz to compress 3 operand form.
2192 2019-02-07 Tamar Christina <tamar.christina@arm.com>
2194 * arm-dis.c (arm_opcodes): Redefine hlt to armv1.
2196 2019-02-07 Tamar Christina <tamar.christina@arm.com>
2199 * aarch64-opc.h (enum aarch64_field_kind): Add FLD_sz.
2200 * aarch64-opc.c (verify_elem_sd): New.
2201 (fields): Add FLD_sz entr.
2202 * aarch64-tbl.h (_SIMD_INSN): New.
2203 (aarch64_opcode_table): Add elem_sd verifier to fmla, fmls, fmul and
2204 fmulx scalar and vector by element isns.
2206 2019-02-07 Nick Clifton <nickc@redhat.com>
2208 * po/sv.po: Updated Swedish translation.
2210 2019-01-31 Andreas Krebbel <krebbel@linux.ibm.com>
2212 * s390-mkopc.c (main): Accept arch13 as cpu string.
2213 * s390-opc.c: Add new instruction formats and instruction opcode
2215 * s390-opc.txt: Add new arch13 instructions.
2217 2019-01-25 Sudakshina Das <sudi.das@arm.com>
2219 * aarch64-tbl.h (QL_LDST_AT): Update macro.
2220 (aarch64_opcode): Change encoding for stg, stzg
2222 * aarch64-asm-2.c: Regenerated.
2223 * aarch64-dis-2.c: Regenerated.
2224 * aarch64-opc-2.c: Regenerated.
2226 2019-01-25 Sudakshina Das <sudi.das@arm.com>
2228 * aarch64-asm-2.c: Regenerated.
2229 * aarch64-dis-2.c: Likewise.
2230 * aarch64-opc-2.c: Likewise.
2231 * aarch64-tbl.h (aarch64_opcode): Add new stzgm.
2233 2019-01-25 Sudakshina Das <sudi.das@arm.com>
2234 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
2236 * aarch64-asm.c (aarch64_ins_addr_simple_2): Remove.
2237 * aarch64-asm.h (ins_addr_simple_2): Likeiwse.
2238 * aarch64-dis.c (aarch64_ext_addr_simple_2): Likewise.
2239 * aarch64-dis.h (ext_addr_simple_2): Likewise.
2240 * aarch64-opc.c (operand_general_constraint_met_p): Remove
2241 case for ldstgv_indexed.
2242 (aarch64_print_operand): Remove case for AARCH64_OPND_ADDR_SIMPLE_2.
2243 * aarch64-tbl.h (struct aarch64_opcode): Remove ldgv and stgv.
2244 (AARCH64_OPERANDS): Remove ADDR_SIMPLE_2.
2245 * aarch64-asm-2.c: Regenerated.
2246 * aarch64-dis-2.c: Regenerated.
2247 * aarch64-opc-2.c: Regenerated.
2249 2019-01-23 Nick Clifton <nickc@redhat.com>
2251 * po/pt_BR.po: Updated Brazilian Portuguese translation.
2253 2019-01-21 Nick Clifton <nickc@redhat.com>
2255 * po/de.po: Updated German translation.
2256 * po/uk.po: Updated Ukranian translation.
2258 2019-01-20 Chenghua Xu <paul.hua.gm@gmail.com>
2259 * mips-dis.c (mips_arch_choices): Fix typo in
2260 gs464, gs464e and gs264e descriptors.
2262 2019-01-19 Nick Clifton <nickc@redhat.com>
2264 * configure: Regenerate.
2265 * po/opcodes.pot: Regenerate.
2267 2018-06-24 Nick Clifton <nickc@redhat.com>
2269 2.32 branch created.
2271 2019-01-09 John Darrington <john@darrington.wattle.id.au>
2273 * s12z-dis.c (print_insn_s12z): Do not dereference an operand
2275 -dis.c (opr_emit_disassembly): Do not omit an index if it is
2278 2019-01-09 Andrew Paprocki <andrew@ishiboo.com>
2280 * configure: Regenerate.
2282 2019-01-07 Alan Modra <amodra@gmail.com>
2284 * configure: Regenerate.
2285 * po/POTFILES.in: Regenerate.
2287 2019-01-03 John Darrington <john@darrington.wattle.id.au>
2289 * s12z-opc.c: New file.
2290 * s12z-opc.h: New file.
2291 * s12z-dis.c: Removed all code not directly related to display
2292 of instructions. Used the interface provided by the new files
2294 * Makefile.am (TARGET_LIBOPCODES_CFILES) Add s12z-opc.c.
2295 * Makefile.in: Regenerate.
2296 * configure.ac (bfd_s12z_arch): Correct the dependencies.
2297 * configure: Regenerate.
2299 2019-01-01 Alan Modra <amodra@gmail.com>
2301 Update year range in copyright notice of all files.
2303 For older changes see ChangeLog-2018
2305 Copyright (C) 2019 Free Software Foundation, Inc.
2307 Copying and distribution of this file, with or without modification,
2308 are permitted in any medium without royalty provided the copyright
2309 notice and this notice are preserved.
2315 version-control: never