opcodes/ChangeLog

   1 2019-12-12  Alan Modra  <amodra@gmail.com>
   2
   3         * csky-dis.c (csky_chars_to_number): Remove abort and unnecessary
   4         mask.
   5
   6 2019-12-11  Alan Modra  <amodra@gmail.com>
   7
   8         * arc-dis.c (BITS): Don't truncate high bits with shifts.
   9         * nios2-dis.c (nios2_print_insn_arg): Don't sign extend with shifts.
  10         * tic54x-dis.c (print_instruction): Likewise.
  11         * tilegx-opc.c (parse_insn_tilegx): Likewise.
  12         * tilepro-opc.c (parse_insn_tilepro): Likewise.
  13         * visium-dis.c (disassem_class0): Likewise.
  14         * pdp11-dis.c (sign_extend): Likewise.
  15         (SIGN_BITS): Delete.
  16         * epiphany-ibld.c: Regenerate.
  17         * lm32-ibld.c: Regenerate.
  18         * m32c-ibld.c: Regenerate.
  19
  20 2019-12-11  Alan Modra  <amodra@gmail.com>
  21
  22         * ns32k-dis.c (sign_extend): Correct last patch.
  23
  24 2019-12-11  Alan Modra  <amodra@gmail.com>
  25
  26         * vax-dis.c (NEXTLONG): Avoid signed overflow.
  27
  28 2019-12-11  Alan Modra  <amodra@gmail.com>
  29
  30         * v850-dis.c (get_operand_value): Use unsigned arithmetic.  Don't
  31         sign extend using shifts.
  32
  33 2019-12-11  Alan Modra  <amodra@gmail.com>
  34
  35         * tic6x-dis.c (tic6x_extract_32): Avoid signed overflow.
  36
  37 2019-12-11  Alan Modra  <amodra@gmail.com>
  38
  39         * tic4x-dis.c (tic4x_print_register): Formatting.  Don't segfault
  40         on NULL registertable entry.
  41         (tic4x_hash_opcode): Use unsigned arithmetic.
  42
  43 2019-12-11  Alan Modra  <amodra@gmail.com>
  44
  45         * s12z-opc.c (z_decode_signed_value): Avoid signed overflow.
  46
  47 2019-12-11  Alan Modra  <amodra@gmail.com>
  48
  49         * ns32k-dis.c (bit_extract): Use unsigned arithmetic.
  50         (bit_extract_simple, sign_extend): Likewise.
  51
  52 2019-12-11  Alan Modra  <amodra@gmail.com>
  53
  54         * nios2-dis.c (nios2_print_insn_arg): Use 1u << 31.
  55
  56 2019-12-11  Alan Modra  <amodra@gmail.com>
  57
  58         * moxie-dis.c (INST2OFFSET): Don't sign extend using shifts.
  59
  60 2019-12-11  Alan Modra  <amodra@gmail.com>
  61
  62         * m68k-dis.c (COERCE32): Cast value first.
  63         (NEXTLONG, NEXTULONG): Avoid signed overflow.
  64
  65 2019-12-11  Alan Modra  <amodra@gmail.com>
  66
  67         * h8300-dis.c (extract_immediate): Avoid signed overflow.
  68         (bfd_h8_disassemble): Likewise.
  69
  70 2019-12-11  Alan Modra  <amodra@gmail.com>
  71
  72         * d30v-dis.c (print_insn): Make opind unsigned.  Don't access
  73         past end of operands array.
  74
  75 2019-12-11  Alan Modra  <amodra@gmail.com>
  76
  77         * csky-dis.c (csky_chars_to_number): Rewrite.  Avoid signed
  78         overflow when collecting bytes of a number.
  79
  80 2019-12-11  Alan Modra  <amodra@gmail.com>
  81
  82         * cris-dis.c (print_with_operands): Avoid signed integer
  83         overflow when collecting bytes of a 32-bit integer.
  84
  85 2019-12-11  Alan Modra  <amodra@gmail.com>
  86
  87         * cr16-dis.c (EXTRACT, SBM): Rewrite.
  88         (cr16_match_opcode): Delete duplicate bcond test.
  89
  90 2019-12-11  Alan Modra  <amodra@gmail.com>
  91
  92         * bfin-dis.c (HOST_LONG_WORD_SIZE, XFIELD): Delete.
  93         (SIGNBIT): New.
  94         (MASKBITS, SIGNEXTEND): Rewrite.
  95         (fmtconst): Don't use ? expression now that SIGNEXTEND uses
  96         unsigned arithmetic, instead assign result of SIGNEXTEND back
  97         to x.
  98         (fmtconst_val): Use 1u in shift expression.
  99
 100 2019-12-11  Alan Modra  <amodra@gmail.com>
 101
 102         * arc-dis.c (find_format_from_table): Use ull constant when
 103         shifting by up to 32.
 104
 105 2019-12-11  Alan Modra  <amodra@gmail.com>
 106
 107         PR 25270
 108         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Return
 109         false when field is zero for sve_size_tsz_bhs.
 110
 111 2019-12-11  Alan Modra  <amodra@gmail.com>
 112
 113         * epiphany-ibld.c: Regenerate.
 114
 115 2019-12-10  Alan Modra  <amodra@gmail.com>
 116
 117         PR 24960
 118         * disassemble.c (disassemble_free_target): New function.
 119
 120 2019-12-10  Alan Modra  <amodra@gmail.com>
 121
 122         * cgen-dis.in (print_insn_@arch@): Replace insn_sets with private_data.
 123         * disassemble.c (disassemble_init_for_target): Likewise.
 124         * bpf-dis.c: Regenerate.
 125         * epiphany-dis.c: Regenerate.
 126         * fr30-dis.c: Regenerate.
 127         * frv-dis.c: Regenerate.
 128         * ip2k-dis.c: Regenerate.
 129         * iq2000-dis.c: Regenerate.
 130         * lm32-dis.c: Regenerate.
 131         * m32c-dis.c: Regenerate.
 132         * m32r-dis.c: Regenerate.
 133         * mep-dis.c: Regenerate.
 134         * mt-dis.c: Regenerate.
 135         * or1k-dis.c: Regenerate.
 136         * xc16x-dis.c: Regenerate.
 137         * xstormy16-dis.c: Regenerate.
 138
 139 2019-12-10  Alan Modra  <amodra@gmail.com>
 140
 141         * ppc-dis.c (private): Delete variable.
 142         (get_powerpc_dialect): Don't segfault on NULL info->private_data.
 143         (powerpc_init_dialect): Don't use global private.
 144
 145 2019-12-10  Alan Modra  <amodra@gmail.com>
 146
 147         * s12z-opc.c: Formatting.
 148
 149 2019-12-08  Alan Modra  <amodra@gmail.com>
 150
 151         * s12z-opc.c (exg_sex_discrim): Don't leak memory on invalid
 152         registers.
 153
 154 2019-12-05  Jan Beulich  <jbeulich@suse.com>
 155
 156         * aarch64-tbl.h (aarch64_feature_crypto,
 157         aarch64_feature_crypto_v8_2, CRYPTO, CRYPTO_V8_2, CRYP_INSN,
 158         CRYPTO_V8_2_INSN): Delete.
 159
 160 2019-12-05  Alan Modra  <amodra@gmail.com>
 161
 162         PR 25249
 163         * microblaze-dis.c (NUM_STRBUFS, STRBUF_SIZE): Define.
 164         (struct string_buf): New.
 165         (strbuf): New function.
 166         (get_field): Use strbuf rather than strdup of local temp.
 167         (get_field_imm, get_field_imm5, get_field_imm5_mbar): Likewise.
 168         (get_field_rfsl, get_field_imm15): Likewise.
 169         (get_field_rd, get_field_r1, get_field_r2): Update macros.
 170         (get_field_special): Likewise.  Don't strcpy spr.  Formatting.
 171         (print_insn_microblaze): Formatting.  Init and pass string_buf to
 172         get_field functions.
 173
 174 2019-12-04  Jan Beulich  <jbeulich@suse.com>
 175
 176         * i386-opc.tbl (lfs, lgs, lss): Drop No_qSuf.
 177         * i386-tbl.h: Re-generate.
 178
 179 2019-12-04  Jan Beulich  <jbeulich@suse.com>
 180
 181         * i386-dis.c (mod_table): Use Ev instead of Em for movdiri.
 182
 183 2019-12-04  Jan Beulich  <jbeulich@suse.com>
 184
 185         * i386-opc.tbl (push, pop): Drop DefaultSize from GPR-only
 186         forms.
 187         (xbegin): Drop DefaultSize.
 188         * i386-tbl.h: Re-generate.
 189
 190 2019-11-22  Mihail Ionescu  <mihail.ionescu@arm.com>
 191
 192         * opcodes/arm-dis.c (arm_opcodes, thumb32_opcodes):
 193         Change the coproc CRC conditions to use the extension
 194         feature set, second word, base on ARM_EXT2_CRC.
 195
 196 2019-11-14  Jan Beulich  <jbeulich@suse.com>
 197
 198         * i386-opc.tbl (syscall, sysret): Drop Cpu64 forms.
 199         * i386-tbl.h: Re-generate.
 200
 201 2019-11-14  Jan Beulich  <jbeulich@suse.com>
 202
 203         * i386-gen.c (opcode_modifiers): Remove JumpDword, JumpByte,
 204         JumpInterSegment, and JumpAbsolute entries.
 205         * i386-opc.h (JUMP, JUMP_DWORD, JUMP_BYTE, JUMP_INTERSEGMENT,
 206         JUMP_ABSOLUTE): Define.
 207         (struct i386_opcode_modifier): Extend jump field to 3 bits.
 208         Remove jumpdword, jumpbyte, jumpintersegment, and jumpabsolute
 209         fields.
 210         * i386-opc.tbl (JumpByte, JumpDword, JumpAbsolute,
 211         JumpInterSegment): Define.
 212         * i386-tbl.h: Re-generate.
 213
 214 2019-11-14  Jan Beulich  <jbeulich@suse.com>
 215
 216         * i386-gen.c (operand_type_init): Remove
 217         OPERAND_TYPE_JUMPABSOLUTE entry.
 218         (opcode_modifiers): Add JumpAbsolute entry.
 219         (operand_types): Remove JumpAbsolute entry.
 220         * i386-opc.h (JumpAbsolute): Move between enums.
 221         (struct i386_opcode_modifier): Add jumpabsolute field.
 222         (union i386_operand_type): Remove jumpabsolute field.
 223         * i386-opc.tbl (call, lcall, jmp, ljmp): Move JumpAbsolute.
 224         * i386-init.h, i386-tbl.h: Re-generate.
 225
 226 2019-11-14  Jan Beulich  <jbeulich@suse.com>
 227
 228         * i386-gen.c (opcode_modifiers): Add AnySize entry.
 229         (operand_types): Remove AnySize entry.
 230         * i386-opc.h (AnySize): Move between enums.
 231         (struct i386_opcode_modifier): Add anysize field.
 232         (OTUnused): Un-comment.
 233         (union i386_operand_type): Remove anysize field.
 234         * i386-opc.tbl (lea, invlpg, clflush, prefetchnta, prefetcht0,
 235         prefetcht1, prefetcht2, prefetchtw, bndmk, bndcl, bndcu, bndcn,
 236         bndstx, bndldx, prefetchwt1, clflushopt, clwb, cldemote): Move
 237         AnySize.
 238         * i386-tbl.h: Re-generate.
 239
 240 2019-11-12  Nelson Chu  <nelson.chu@sifive.com>
 241
 242         * riscv-opc.c (riscv_insn_types): Replace the INSN_CLASS_I with
 243         INSN_CLASS_F and the INSN_CLASS_C with INSN_CLASS_F_AND_C if we
 244         use the floating point register (FPR).
 245
 246 2019-11-12  Mihail Ionescu  <mihail.ionescu@arm.com>
 247
 248         * opcodes/arm-dis.c (mve_opcodes): Enable VMOV imm to vec with
 249         cmode 1101.
 250         (is_mve_encoding_conflict): Update cmode conflict checks for
 251         MVE_VMVN_IMM.
 252
 253 2019-11-12  Jan Beulich  <jbeulich@suse.com>
 254
 255         * i386-gen.c (operand_type_init): Remove OPERAND_TYPE_ESSEG
 256         entry.
 257         (operand_types): Remove EsSeg entry.
 258         (main): Replace stale use of OTMax.
 259         * i386-opc.h (IS_STRING_ES_OP0, IS_STRING_ES_OP1): Define.
 260         (struct i386_opcode_modifier): Expand isstring field to 2 bits.
 261         (EsSeg): Delete.
 262         (OTUnused): Comment out.
 263         (union i386_operand_type): Remove esseg field.
 264         * i386-opc.tbl (IsStringEsOp0, IsStringEsOp1): Define.
 265         (cmps, scmp, scas, ssca, cmpsd): Add IsStringEsOp0.
 266         (ins, movs, smov, movsd): Add IsStringEsOpOp1.
 267         (stos, ssto): Add IsStringEsOp0/IsStringEsOpOp1.
 268         * i386-init.h, i386-tbl.h: Re-generate.
 269
 270 2019-11-12  Jan Beulich  <jbeulich@suse.com>
 271
 272         * i386-gen.c (operand_instances): Add RegB entry.
 273         * i386-opc.h (enum operand_instance): Add RegB.
 274         * i386-opc.tbl (RegC, RegD, RegB): Define.
 275         (Acc, ShiftCount, InOutPortReg): Adjust definitions.
 276         (monitor, mwait, invlpga, skinit, vmload, vmrun, vmsave, clzero,
 277         monitorx, mwaitx): Drop ImmExt and convert encodings
 278         accordingly.
 279         * i386-reg.tbl (ecx, rcx): Add Instance=RegC.
 280         (edx, rdx): Add Instance=RegD.
 281         (ebx, rbx): Add Instance=RegB.
 282         * i386-tbl.h: Re-generate.
 283
 284 2019-11-12  Jan Beulich  <jbeulich@suse.com>
 285
 286         * i386-gen.c (operand_type_init): Adjust
 287         OPERAND_TYPE_INOUTPORTREG, OPERAND_TYPE_SHIFTCOUNT,
 288         OPERAND_TYPE_FLOATACC, OPERAND_TYPE_ACC8, OPERAND_TYPE_ACC16,
 289         OPERAND_TYPE_ACC32, and OPERAND_TYPE_ACC64 entries.
 290         (operand_instances): New.
 291         (operand_types): Drop InOutPortReg, ShiftCount, and Acc entries.
 292         (output_operand_type): New parameter "instance". Process it.
 293         (process_i386_operand_type): New local variable "instance".
 294         (main): Adjust static assertions.
 295         * i386-opc.h (INSTANCE_WIDTH): Define.
 296         (enum operand_instance): New.
 297         (Acc, InOutPortReg, ShiftCount): Replace by ClassInstance.
 298         (union i386_operand_type): Replace acc, inoutportreg, and
 299         shiftcount by instance.
 300         * i386-opc.tbl (Acc, InOutPortReg, ShiftCount): Define.
 301         * i386-reg.tbl (st, al, cl, ax, dx, eax, rax, xmm0, st(0)):
 302         Add Instance=.
 303         * i386-init.h, i386-tbl.h: Re-generate.
 304
 305 2019-11-11  Jan Beulich  <jbeulich@suse.com>
 306
 307         * aarch64-tbl.h (aarch64_opcode_table): Switch SVE2's
 308         smaxp/sminp entries' "tied_operand" field to 2.
 309
 310 2019-11-11  Jan Beulich  <jbeulich@suse.com>
 311
 312         * aarch64-opc.c (operand_general_constraint_met_p): Replace
 313         "index" local variable by that of the already existing "num".
 314
 315 2019-11-08  H.J. Lu  <hongjiu.lu@intel.com>
 316
 317         PR gas/25167
 318         * i386-opc.tbl: Remove IgnoreSize from cmpsd and movsd.
 319         * i386-tbl.h: Regenerated.
 320
 321 2019-11-08  Jan Beulich  <jbeulich@suse.com>
 322
 323         * i386-gen.c (operand_type_init): Add Class= to
 324         OPERAND_TYPE_REGMASK and OPERAND_TYPE_REGBND entries. Move up
 325         OPERAND_TYPE_REGBND entry.
 326         (operand_classes): Add RegMask and RegBND entries.
 327         (operand_types): Drop RegMask and RegBND entry.
 328         * i386-opc.h (enum operand_class): Add RegMask and RegBND.
 329         (RegMask, RegBND): Delete.
 330         (union i386_operand_type): Remove regmask and regbnd fields.
 331         * i386-opc.tbl (RegMask, RegBND): Define.
 332         * i386-reg.tbl: Replace RegMask by Class=RegMask and RegBND by
 333         Class=RegBND.
 334         * i386-init.h, i386-tbl.h: Re-generate.
 335
 336 2019-11-08  Jan Beulich  <jbeulich@suse.com>
 337
 338         * i386-gen.c (operand_type_init): Add Class= to
 339         OPERAND_TYPE_REGMMX, OPERAND_TYPE_REGXMM, OPERAND_TYPE_REGYMM, and
 340         OPERAND_TYPE_REGZMM entries.
 341         (operand_classes): Add RegMMX and RegSIMD entries.
 342         (operand_types): Drop RegMMX and RegSIMD entries.
 343         * i386-opc.h (enum operand_class): Add RegMMX and RegSIMD.
 344         (RegMMX, RegSIMD): Delete.
 345         (union i386_operand_type): Remove regmmx and regsimd fields.
 346         * i386-opc.tbl (RegMMX): Define.
 347         (RegXMM, RegYMM, RegZMM): Add Class=.
 348         * i386-reg.tbl: Replace RegMMX by Class=RegMMX and RegSIMD by
 349         Class=RegSIMD.
 350         * i386-init.h, i386-tbl.h: Re-generate.
 351
 352 2019-11-08  Jan Beulich  <jbeulich@suse.com>
 353
 354         * i386-gen.c (operand_type_init): Add Class= to
 355         OPERAND_TYPE_CONTROL, OPERAND_TYPE_TEST, and OPERAND_TYPE_DEBUG
 356         entries.
 357         (operand_classes): Add RegCR, RegDR, and RegTR entries.
 358         (operand_types): Drop Control, Debug, and Test entries.
 359         * i386-opc.h (enum operand_class): Add RegCR, RegDR, and RegTR.
 360         (Control, Debug, Test): Delete.
 361         (union i386_operand_type): Remove control, debug, and test
 362         fields.
 363         * i386-opc.tbl (Control, Debug, Test): Define.
 364         * i386-reg.tbl: Replace Control by Class=RegCR, Debug by
 365         Class=RegDR, and Test by Class=RegTR.
 366         * i386-init.h, i386-tbl.h: Re-generate.
 367
 368 2019-11-08  Jan Beulich  <jbeulich@suse.com>
 369
 370         * i386-gen.c (operand_type_init): Add Class= to
 371         OPERAND_TYPE_SREG entry.
 372         (operand_classes): Add SReg entry.
 373         (operand_types): Drop SReg entry.
 374         * i386-opc.h (enum operand_class): Add SReg.
 375         (SReg): Delete.
 376         (union i386_operand_type): Remove sreg field.
 377         * i386-opc.tbl (SReg): Define.
 378         * i386-reg.tbl: Replace SReg by Class=SReg.
 379         * i386-init.h, i386-tbl.h: Re-generate.
 380
 381 2019-11-08  Jan Beulich  <jbeulich@suse.com>
 382
 383         * i386-gen.c (operand_type_init): Add Class=. New
 384         OPERAND_TYPE_ANYIMM entry.
 385         (operand_classes): New.
 386         (operand_types): Drop Reg entry.
 387         (output_operand_type): New parameter "class". Process it.
 388         (process_i386_operand_type): New local variable "class".
 389         (main): Adjust static assertions.
 390         * i386-opc.h (CLASS_WIDTH): Define.
 391         (enum operand_class): New.
 392         (Reg): Replace by Class. Adjust comment.
 393         (union i386_operand_type): Replace reg by class.
 394         * i386-opc.tbl (Reg8, Reg16, Reg32, Reg64, FloatReg): Add
 395         Class=.
 396         * i386-reg.tbl: Replace Reg by Class=Reg.
 397         * i386-init.h: Re-generate.
 398
 399 2019-11-07  Mihail Ionescu  <mihail.ionescu@arm.com>
 400
 401         * opcodes/aarch64-tbl.h (V8_6_INSN): New macro for v8.6 instructions.
 402         (aarch64_opcode_table): Add data gathering hint mnemonic.
 403         * opcodes/aarch64-dis-2.c: Account for new instruction.
 404
 405 2019-11-07  Mihail Ionescu  <mihail.ionescu@arm.com>
 406
 407         * arm-dis.c (neon_opcodes): Add i8mm SIMD instructions.
 408
 409
 410 2019-11-07  Mihail Ionescu  <mihail.ionescu@arm.com>
 411
 412         * aarch64-tbl.h (aarch64_feature_i8mm_sve, aarch64_feature_f32mm_sve,
 413         aarch64_feature_f64mm_sve, aarch64_feature_i8mm, aarch64_feature_f32mm,
 414         aarch64_feature_f64mm): New feature sets.
 415         (INT8MATMUL_INSN, F64MATMUL_SVE_INSN, F64MATMUL_INSN,
 416         F32MATMUL_SVE_INSN, F32MATMUL_INSN): New macros to define matrix multiply
 417         instructions.
 418         (I8MM_SVE, F32MM_SVE, F64MM_SVE, I8MM, F32MM, F64MM): New feature set
 419         macros.
 420         (QL_MMLA64, OP_SVE_SBB): New qualifiers.
 421         (OP_SVE_QQQ): New qualifier.
 422         (INT8MATMUL_SVE_INSNC, F64MATMUL_SVE_INSNC,
 423         F32MATMUL_SVE_INSNC): New feature set for bfloat16 instructions to support
 424         the movprfx constraint.
 425         (aarch64_opcode_table): Support for SVE_ADDR_RI_S4x32.
 426         (aarch64_opcode_table): Define new instructions smmla,
 427         ummla, usmmla, usdot, sudot, fmmla, ld1rob, ld1roh, ld1row, ld1rod,
 428         uzip{1/2}, trn{1/2}.
 429         * aarch64-opc.c (operand_general_constraint_met_p): Handle
 430         AARCH64_OPND_SVE_ADDR_RI_S4x32.
 431         (aarch64_print_operand): Handle AARCH64_OPND_SVE_ADDR_RI_S4x32.
 432         * aarch64-dis-2.c (aarch64_opcode_lookup_1, aarch64_find_next_opcode):
 433         Account for new instructions.
 434         * opcodes/aarch64-asm-2.c (aarch64_insert_operand): Support the new
 435         S4x32 operand.
 436         * aarch64-opc-2.c (aarch64_operands): Support the new S4x32 operand.
 437
 438 2019-11-07  Mihail Ionescu  <mihail.ionescu@arm.com>
 439 2019-11-07  Matthew Malcomson  <matthew.malcomson@arm.com>
 440
 441         * arm-dis.c (select_arm_features): Update bfd_march_arm_8 with
 442         Armv8.6-A.
 443         (coprocessor_opcodes): Add bfloat16 vcvt{t,b}.
 444         (neon_opcodes): Add bfloat SIMD instructions.
 445         (print_insn_coprocessor): Add new control character %b to print
 446         condition code without checking cp_num.
 447         (print_insn_neon): Account for BFloat16 instructions that have no
 448         special top-byte handling.
 449
 450 2019-11-07  Mihail Ionescu  <mihail.ionescu@arm.com>
 451 2019-11-07  Matthew Malcomson  <matthew.malcomson@arm.com>
 452
 453         * arm-dis.c (print_insn_coprocessor,
 454         print_insn_generic_coprocessor): Create wrapper functions around
 455         the implementation of the print_insn_coprocessor control codes.
 456         (print_insn_coprocessor_1): Original print_insn_coprocessor
 457         function that now takes which array to look at as an argument.
 458         (print_insn_arm): Use both print_insn_coprocessor and
 459         print_insn_generic_coprocessor.
 460         (print_insn_thumb32): As above.
 461
 462 2019-11-07  Mihail Ionescu  <mihail.ionescu@arm.com>
 463 2019-11-07  Matthew Malcomson  <matthew.malcomson@arm.com>
 464
 465         * aarch64-asm.c (aarch64_ins_reglane): Use AARCH64_OPND_QLF_S_2H
 466         in reglane special case.
 467         * aarch64-dis-2.c (aarch64_opcode_lookup_1,
 468         aarch64_find_next_opcode): Account for new instructions.
 469         * aarch64-dis.c (aarch64_ext_reglane): Use AARCH64_OPND_QLF_S_2H
 470         in reglane special case.
 471         * aarch64-opc.c (struct operand_qualifier_data): Add data for
 472         new AARCH64_OPND_QLF_S_2H qualifier.
 473         * aarch64-tbl.h (QL_BFDOT QL_BFDOT64, QL_BFDOT64I, QL_BFMMLA2,
 474         QL_BFCVT64, QL_BFCVTN64, QL_BFCVTN2_64): New qualifiers.
 475         (aarch64_feature_bfloat16, aarch64_feature_bfloat16_sve): New feature
 476         sets.
 477         (BFLOAT_SVE, BFLOAT): New feature set macros.
 478         (BFLOAT_SVE_INSN, BFLOAT_INSN): New macros to define BFloat16
 479         instructions.
 480         (aarch64_opcode_table): Define new instructions bfdot,
 481         bfmmla, bfcvt, bfcvtnt, bfdot, bfdot, bfcvtn, bfmlal[b/t]
 482         bfcvtn2, bfcvt.
 483
 484 2019-11-07  Mihail Ionescu  <mihail.ionescu@arm.com>
 485 2019-11-07  Matthew Malcomson  <matthew.malcomson@arm.com>
 486
 487         * aarch64-tbl.h (ARMV8_6): New macro.
 488
 489 2019-11-07  Jan Beulich  <jbeulich@suse.com>
 490
 491         * i386-dis.c (prefix_table): Add mcommit.
 492         (rm_table): Add rdpru.
 493         * i386-gen.c (cpu_flag_init): Adjust CPU_ZNVER2_FLAGS entry. Add
 494         CPU_RDPRU_FLAGS and CPU_MCOMMIT_FLAGS entries.
 495         (cpu_flags): Add CpuRDPRU and CpuMCOMMIT entries.
 496         * i386-opc.h (CpuRDPRU, CpuMCOMMIT): New.
 497         (union i386_cpu_flags): Add cpurdpru and cpumcommit fields.
 498         * i386-opc.tbl (mcommit, rdpru): New.
 499         * i386-init.h, i386-tbl.h: Re-generate.
 500
 501 2019-11-07  Jan Beulich  <jbeulich@suse.com>
 502
 503         * i386-dis.c (OP_Mwait): Drop local variable "names", use
 504         "names32" instead.
 505         (OP_Monitor): Drop local variable "op1_names", re-purpose
 506         "names" for it instead, and replace former "names" uses by
 507         "names32" ones.
 508
 509 2019-11-07  Jan Beulich  <jbeulich@suse.com>
 510
 511         PR/gas 25167
 512         * opcodes/i386-opc.tbl (movsd, cmpsd): Drop IgnoreSize from
 513         operand-less forms.
 514         * opcodes/i386-tbl.h: Re-generate.
 515
 516 2019-11-05  Jan Beulich  <jbeulich@suse.com>
 517
 518         * i386-dis.c (OP_Mwaitx): Delete.
 519         (prefix_table): Use OP_Mwait for mwaitx entry.
 520         (OP_Mwait): Also handle mwaitx.
 521
 522 2019-11-05  Jan Beulich  <jbeulich@suse.com>
 523
 524         * i386-dis.c (PREFIX_0F01_REG_7_MOD_3_RM_2,
 525         PREFIX_0F01_REG_7_MOD_3_RM_3): New.
 526         (prefix_table): Add respective entries.
 527         (rm_table): Link to those entries.
 528
 529 2019-11-05  Jan Beulich  <jbeulich@suse.com>
 530
 531         * i386-dis.c (REG_0F1C_MOD_0): Rename to ...
 532         (REG_0F1C_P_0_MOD_0): ... this.
 533         (REG_0F1E_MOD_3): Rename to ...
 534         (REG_0F1E_P_1_MOD_3): ... this.
 535         (RM_0F01_REG_5): Rename to ...
 536         (RM_0F01_REG_5_MOD_3): ... this.
 537         (RM_0F01_REG_7): Rename to ...
 538         (RM_0F01_REG_7_MOD_3): ... this.
 539         (RM_0F1E_MOD_3_REG_7): Rename to ...
 540         (RM_0F1E_P_1_MOD_3_REG_7): ... this.
 541         (RM_0FAE_REG_6): Rename to ...
 542         (RM_0FAE_REG_6_MOD_3_P_0): ... this.
 543         (RM_0FAE_REG_7): Rename to ...
 544         (RM_0FAE_REG_7_MOD_3): ... this.
 545         (PREFIX_MOD_0_0F01_REG_5): Rename to ...
 546         (PREFIX_0F01_REG_5_MOD_0): ... this.
 547         (PREFIX_MOD_3_0F01_REG_5_RM_0): Rename to ...
 548         (PREFIX_0F01_REG_5_MOD_3_RM_0): ... this.
 549         (PREFIX_MOD_3_0F01_REG_5_RM_2): Rename to ...
 550         (PREFIX_0F01_REG_5_MOD_3_RM_2): ... this.
 551         (PREFIX_0FAE_REG_0): Rename to ...
 552         (PREFIX_0FAE_REG_0_MOD_3): ... this.
 553         (PREFIX_0FAE_REG_1): Rename to ...
 554         (PREFIX_0FAE_REG_1_MOD_3): ... this.
 555         (PREFIX_0FAE_REG_2): Rename to ...
 556         (PREFIX_0FAE_REG_2_MOD_3): ... this.
 557         (PREFIX_0FAE_REG_3): Rename to ...
 558         (PREFIX_0FAE_REG_3_MOD_3): ... this.
 559         (PREFIX_MOD_0_0FAE_REG_4): Rename to ...
 560         (PREFIX_0FAE_REG_4_MOD_0): ... this.
 561         (PREFIX_MOD_3_0FAE_REG_4): Rename to ...
 562         (PREFIX_0FAE_REG_4_MOD_3): ... this.
 563         (PREFIX_MOD_0_0FAE_REG_5): Rename to ...
 564         (PREFIX_0FAE_REG_5_MOD_0): ... this.
 565         (PREFIX_MOD_3_0FAE_REG_5): Rename to ...
 566         (PREFIX_0FAE_REG_5_MOD_3): ... this.
 567         (PREFIX_MOD_0_0FAE_REG_6): Rename to ...
 568         (PREFIX_0FAE_REG_6_MOD_0): ... this.
 569         (PREFIX_MOD_1_0FAE_REG_6): Rename to ...
 570         (PREFIX_0FAE_REG_6_MOD_3): ... this.
 571         (PREFIX_0FAE_REG_7): Rename to ...
 572         (PREFIX_0FAE_REG_7_MOD_0): ... this.
 573         (PREFIX_MOD_0_0FC3): Rename to ...
 574         (PREFIX_0FC3_MOD_0): ... this.
 575         (PREFIX_MOD_0_0FC7_REG_6): Rename to ...
 576         (PREFIX_0FC7_REG_6_MOD_0): ... this.
 577         (PREFIX_MOD_3_0FC7_REG_6): Rename to ...
 578         (PREFIX_0FC7_REG_6_MOD_3): ... this.
 579         (PREFIX_MOD_3_0FC7_REG_7): Rename to ...
 580         (PREFIX_0FC7_REG_7_MOD_3): ... this.
 581         (reg_table, prefix_table, mod_table, rm_table): Adjust
 582         accordingly.
 583
 584 2019-11-04  Nick Clifton  <nickc@redhat.com>
 585
 586         * v850-dis.c (get_v850_sreg_name): New function.  Returns the name
 587         of a v850 system register.  Move the v850_sreg_names array into
 588         this function.
 589         (get_v850_reg_name): Likewise for ordinary register names.
 590         (get_v850_vreg_name): Likewise for vector register names.
 591         (get_v850_cc_name): Likewise for condition codes.
 592         * get_v850_float_cc_name): Likewise for floating point condition
 593         codes.
 594         (get_v850_cacheop_name): Likewise for cache-ops.
 595         (get_v850_prefop_name): Likewise for pref-ops.
 596         (disassemble): Use the new accessor functions.
 597
 598 2019-10-30  Delia Burduv   <delia.burduv@arm.com>
 599
 600         * aarch64-opc.c (print_immediate_offset_address): Don't print the
 601         immediate for the writeback form of ldraa/ldrab if it is 0.
 602         * aarch64-tbl.h: Updated the documentation for ADDR_SIMM10.
 603         * aarch64-opc-2.c: Regenerated.
 604
 605 2019-10-30  Jan Beulich  <jbeulich@suse.com>
 606
 607         * i386-gen.c (operand_type_shorthands): Delete.
 608         (operand_type_init): Expand previous shorthands.
 609         (set_bitfield_from_shorthand): Rename back to ...
 610         (set_bitfield_from_cpu_flag_init): ... this.  Drop processing
 611         of operand_type_init[].
 612         (set_bitfield): Adjust call to the above function.
 613         * i386-opc.tbl (Reg8, Reg16, Reg32, Reg64, FloatAcc, FloatReg,
 614         RegXMM, RegYMM, RegZMM): Define.
 615         * i386-reg.tbl: Expand prior shorthands.
 616
 617 2019-10-30  Jan Beulich  <jbeulich@suse.com>
 618
 619         * i386-gen.c (output_i386_opcode): Change order of fields
 620         emitted to output.
 621         * i386-opc.h (struct insn_template): Move operands field.
 622         Convert extension_opcode field to unsigned short.
 623         * i386-tbl.h: Re-generate.
 624
 625 2019-10-30  Jan Beulich  <jbeulich@suse.com>
 626
 627         * i386-gen.c (process_i386_opcode_modifier): Report bogus uses
 628         of W.
 629         * i386-opc.h (W): Extend comment.
 630         * i386-opc.tbl (mov, movabs, movq): Drop W and adjust opcodes of
 631         general purpose variants not allowing for byte operands.
 632         * i386-tbl.h: Re-generate.
 633
 634 2019-10-29  Nick Clifton  <nickc@redhat.com>
 635
 636         * tic30-dis.c (print_branch): Correct size of operand array.
 637
 638 2019-10-29  Nick Clifton  <nickc@redhat.com>
 639
 640         * d30v-dis.c (print_insn): Check that operand index is valid
 641         before attempting to access the operands array.
 642
 643 2019-10-29  Nick Clifton  <nickc@redhat.com>
 644
 645         * ia64-opc.c (locate_opcode_ent): Prevent a negative shift when
 646         locating the bit to be tested.
 647
 648 2019-10-29  Nick Clifton  <nickc@redhat.com>
 649
 650         * s12z-dis.c (opr_emit_disassembly): Check for illegal register
 651         values.
 652         (shift_size_table): Use a fixed size defined as S12Z_N_SIZES.
 653         (print_insn_s12z):  Check for illegal size values.
 654
 655 2019-10-28  Nick Clifton  <nickc@redhat.com>
 656
 657         * csky-dis.c (csky_chars_to_number): Check for a negative
 658         count. Use an unsigned integer to construct the return value.
 659
 660 2019-10-28  Nick Clifton  <nickc@redhat.com>
 661
 662         * tic30-dis.c (OPERAND_BUFFER_LEN): Define.  Use as length of
 663         operand buffer.  Set value to 15 not 13.
 664         (get_register_operand): Use OPERAND_BUFFER_LEN.
 665         (get_indirect_operand): Likewise.
 666         (print_two_operand): Likewise.
 667         (print_three_operand): Likewise.
 668         (print_oar_insn): Likewise.
 669
 670 2019-10-28  Nick Clifton  <nickc@redhat.com>
 671
 672         * ns32k-dis.c (bit_extract): Add sanitiy check of parameters.
 673         (bit_extract_simple): Likewise.
 674         (bit_copy): Likewise.
 675         (pirnt_insn_ns32k): Ensure that uninitialised elements in the
 676         index_offset array are not accessed.
 677
 678 2019-10-28  Nick Clifton  <nickc@redhat.com>
 679
 680         * xgate-dis.c (print_insn): Fix decoding of the XGATE_OP_DYA
 681         operand.
 682
 683 2019-10-25  Nick Clifton  <nickc@redhat.com>
 684
 685         * rx-dis.c (print_insn_rx): Use parenthesis to ensure correct
 686         access to opcodes.op array element.
 687
 688 2019-10-23  Nick Clifton  <nickc@redhat.com>
 689
 690         * rx-dis.c (get_register_name): Fix spelling typo in error
 691         message.
 692         (get_condition_name, get_flag_name, get_double_register_name)
 693         (get_double_register_high_name, get_double_register_low_name)
 694         (get_double_control_register_name, get_double_condition_name)
 695         (get_opsize_name, get_size_name): Likewise.
 696
 697 2019-10-22  Nick Clifton  <nickc@redhat.com>
 698
 699         * rx-dis.c (get_size_name): New function.  Provides safe
 700         access to name array.
 701         (get_opsize_name): Likewise.
 702         (print_insn_rx): Use the accessor functions.
 703
 704 2019-10-16  Nick Clifton  <nickc@redhat.com>
 705
 706         * rx-dis.c (get_register_name): New function.  Provides safe
 707         access to name array.
 708         (get_condition_name, get_flag_name, get_double_register_name)
 709         (get_double_register_high_name, get_double_register_low_name)
 710         (get_double_control_register_name, get_double_condition_name):
 711         Likewise.
 712         (print_insn_rx): Use the accessor functions.
 713
 714 2019-10-09  Nick Clifton  <nickc@redhat.com>
 715
 716         PR 25041
 717         * avr-dis.c (avr_operand): Fix construction of address for lds/sts
 718         instructions.
 719
 720 2019-10-07  Jan Beulich  <jbeulich@suse.com>
 721
 722         * opcodes/i386-opc.tbl (movsd): Add Dword and IgnoreSize.
 723         (cmpsd): Likewise. Move EsSeg to other operand.
 724         * opcodes/i386-tbl.h: Re-generate.
 725
 726 2019-09-23  Alan Modra  <amodra@gmail.com>
 727
 728         * m68k-dis.c: Include cpu-m68k.h
 729
 730 2019-09-23  Alan Modra  <amodra@gmail.com>
 731
 732         * mips-dis.c: Include elfxx-mips.h.  Move "elf-bfd.h" and
 733         "elf/mips.h" earlier.
 734
 735 2018-09-20  Jan Beulich  <jbeulich@suse.com>
 736
 737         PR gas/25012
 738         * i386-opc.tbl (push, pop): Re-instate distinct Cpu64 templates
 739         with SReg operand.
 740         * i386-tbl.h: Re-generate.
 741
 742 2019-09-18  Alan Modra  <amodra@gmail.com>
 743
 744         * arc-ext.c: Update throughout for bfd section macro changes.
 745
 746 2019-09-18  Simon Marchi  <simon.marchi@polymtl.ca>
 747
 748         * Makefile.in: Re-generate.
 749         * configure: Re-generate.
 750
 751 2019-09-17  Maxim Blinov  <maxim.blinov@embecosm.com>
 752
 753         * riscv-opc.c (riscv_opcodes): Change subset field
 754         to insn_class field for all instructions.
 755         (riscv_insn_types): Likewise.
 756
 757 2019-09-16  Phil Blundell  <pb@pbcl.net>
 758
 759         * configure: Regenerated.
 760
 761 2019-09-10  Miod Vallat  <miod@online.fr>
 762
 763         PR 24982
 764         * m68k-opc.c: Correct aliases for tdivsl and tdivul.
 765
 766 2019-09-09  Phil Blundell  <pb@pbcl.net>
 767
 768         binutils 2.33 branch created.
 769
 770 2019-09-03  Nick Clifton  <nickc@redhat.com>
 771
 772         PR 24961
 773         * tic30-dis.c (get_indirect_operand): Check for bufcnt being
 774         greater than zero before indexing via (bufcnt -1).
 775
 776 2019-09-03  Nick Clifton  <nickc@redhat.com>
 777
 778         PR 24958
 779         * mmix-dis.c (MAX_REG_NAME_LEN): Define.
 780         (MAX_SPEC_REG_NAME_LEN): Define.
 781         (struct mmix_dis_info): Use defined constants for array lengths.
 782         (get_reg_name): New function.
 783         (get_sprec_reg_name): New function.
 784         (print_insn_mmix): Use new functions.
 785
 786 2019-08-27  Srinath Parvathaneni  <srinath.parvathaneni@arm.com>
 787
 788         * arm-dis.c (mve_opcodes): Add entry for MVE_VMOV_VEC_TO_VEC.
 789         (is_mve_undefined): Add case for MVE_VMOV_VEC_TO_VEC.
 790         (print_insn_mve): Add condition to check Qm==Qn of VORR instruction.
 791
 792 2019-08-22  Kyrylo Tkachov <kyrylo.tkachov@arm.com>
 793
 794         * aarch64-opc.c (aarch64_sys_regs): Update encoding of tfsre0_el1,
 795         tfsr_el1, tfsr_el2, tfsr_el3, tfsr_el12.
 796         (aarch64_sys_reg_supported_p): Update checks for the above.
 797
 798 2019-08-12  Srinath Parvathaneni  <srinath.parvathaneni@arm.com>
 799
 800         * arm-dis.c (struct mopcode32 mve_opcodes): Modify the mask for
 801         cases MVE_SQRSHRL and MVE_UQRSHLL.
 802         (print_insn_mve): Add case for specifier 'k' to check
 803         specific bit of the instruction.
 804
 805 2019-08-07  Phillipe Antoine  <p.antoine@catenacyber.fr>
 806
 807         PR 24854
 808         * arc-dis.c (arc_insn_length): Return 0 rather than aborting when
 809         encountering an unknown machine type.
 810         (print_insn_arc): Handle arc_insn_length returning 0.  In error
 811         cases return -1 rather than calling abort.
 812
 813 2019-08-07  Jan Beulich  <jbeulich@suse.com>
 814
 815         * i386-opc.tbl (fld, fstp): Drop FloatMF from extended forms.
 816         (fldcw, fnstcw, fstcw, fnstsw, fstsw): Replace FloatMF by
 817         IgnoreSize.
 818         * i386-tbl.h: Re-generate.
 819
 820 2019-08-05  Barnaby Wilks  <barnaby.wilks@arm.com>
 821
 822         * arm-dis.c: Only accept signed variants of VQ(R)DMLAH and VQ(R)DMLASH
 823         instructions.
 824
 825 2019-07-30  Mel Chen <mel.chen@sifive.com>
 826
 827         * riscv-opc.c (riscv_opcodes): Set frsr, fssr, frcsr, fscsr, frrm,
 828         fsrm, fsrmi, frflags, fsflags, fsflagsi to alias instructions.
 829
 830         * riscv-opc.c (riscv_opcodes): Adjust order of frsr, frcsr, fssr,
 831         fscsr.
 832
 833 2019-07-24  Claudiu Zissulescu  <claziss@synopsys.com>
 834
 835         * arc-dis.c (skip_this_opcode): Check also for 0x07 major opcodes,
 836         and MPY class instructions.
 837         (parse_option): Add nps400 option.
 838         (print_arc_disassembler_options): Add nps400 info.
 839
 840 2019-07-24  Claudiu Zissulescu  <claziss@synopsys.com>
 841
 842         * arc-ext-tbl.h (bspeek): Remove it, added to main table.
 843         (bspop): Likewise.
 844         (modapp): Likewise.
 845         * arc-opc.c (RAD_CHK): Add.
 846         * arc-tbl.h: Regenerate.
 847
 848 2019-07-23  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
 849
 850         * aarch64-opc.c (aarch64_sys_regs): Add gmid_el1 entry.
 851         (aarch64_sys_reg_supported_p): Handle gmid_el1 encoding.
 852
 853 2019-07-22  Barnaby Wilks  <barnaby.wilks@arm.com>
 854
 855         * arm-dis.c (is_mve_unpredictable): Stop marking some MVE
 856         instructions as UNPREDICTABLE.
 857
 858 2019-07-19  Jose E. Marchesi  <jose.marchesi@oracle.com>
 859
 860         * bpf-desc.c: Regenerated.
 861
 862 2019-07-17  Jan Beulich  <jbeulich@suse.com>
 863
 864         * i386-gen.c (static_assert): Define.
 865         (main): Use it.
 866         * i386-opc.h (Opcode_Modifier_Max): Rename to ...
 867         (Opcode_Modifier_Num): ... this.
 868         (Mem): Delete.
 869
 870 2019-07-16  Jan Beulich  <jbeulich@suse.com>
 871
 872         * i386-gen.c (operand_types): Move RegMem ...
 873         (opcode_modifiers): ... here.
 874         * i386-opc.h (RegMem): Move to opcode modifer enum.
 875         (union i386_operand_type): Move regmem field ...
 876         (struct i386_opcode_modifier): ... here.
 877         * i386-opc.tbl (RegMem): Define.
 878         (mov, movq): Move RegMem on segment, control, debug, and test
 879         register flavors.
 880         (pextrb): Move RegMem on register only flavors. Add IgnoreSize
 881         to non-SSE2AVX flavor.
 882         (extractps, pextrw, vcvtps2ph, vextractps, vpextrb, vpextrw):
 883         Move RegMem on register only flavors. Drop IgnoreSize from
 884         legacy encoding flavors.
 885         (movss, movsd, vmovss, vmovsd): Drop RegMem from register only
 886         flavors.
 887         (vpinsrb, vpinsrw): Drop IgnoreSize where still present on
 888         register only flavors.
 889         (vmovd): Move RegMem and drop IgnoreSize on register only
 890         flavor. Change opcode and operand order to store form.
 891         * opcodes/i386-init.h, i386-tbl.h: Re-generate.
 892
 893 2019-07-16  Jan Beulich  <jbeulich@suse.com>
 894
 895         * i386-gen.c (operand_type_init, operand_types): Replace SReg
 896         entries.
 897         * i386-opc.h (SReg2, SReg3): Replace by ...
 898         (SReg): ... this.
 899         (union i386_operand_type): Replace sreg fields.
 900         * i386-opc.tbl (mov, ): Use SReg.
 901         (push, pop): Likewies. Drop i386 and x86-64 specific segment
 902         register flavors.
 903         * i386-reg.tbl (cs, ds, es, fs, gs, ss, flat): Use SReg.
 904         * opcodes/i386-init.h, i386-tbl.h: Re-generate.
 905
 906 2019-07-15  Jose E. Marchesi  <jose.marchesi@oracle.com>
 907
 908         * bpf-desc.c: Regenerate.
 909         * bpf-opc.c: Likewise.
 910         * bpf-opc.h: Likewise.
 911
 912 2019-07-14  Jose E. Marchesi  <jose.marchesi@oracle.com>
 913
 914         * bpf-desc.c: Regenerate.
 915         * bpf-opc.c: Likewise.
 916
 917 2019-07-10  Hans-Peter Nilsson  <hp@bitrange.com>
 918
 919         * arm-dis.c (print_insn_coprocessor): Rename index to
 920         index_operand.
 921
 922 2019-07-05  Kito Cheng <kito.cheng@sifive.com>
 923
 924         * riscv-opc.c (riscv_insn_types): Add r4 type.
 925
 926         * riscv-opc.c (riscv_insn_types): Add b and j type.
 927
 928         * opcodes/riscv-opc.c (riscv_insn_types): Remove incorrect
 929         format for sb type and correct s type.
 930
 931 2019-07-02  Richard Sandiford  <richard.sandiford@arm.com>
 932
 933         * aarch64-tbl.h (aarch64_opcode): Set C_SCAN_MOVPRFX for the
 934         SVE FMOV alias of FCPY.
 935
 936 2019-07-02  Richard Sandiford  <richard.sandiford@arm.com>
 937
 938         * aarch64-tbl.h (aarch64_opcode_table): Add C_MAX_ELEM flags
 939         to SVE fcvtzs, fcvtzu, scvtf and ucvtf entries.
 940
 941 2019-07-02  Richard Sandiford  <richard.sandiford@arm.com>
 942
 943         * aarch64-opc.c (verify_constraints): Skip GPRs when scanning the
 944         registers in an instruction prefixed by MOVPRFX.
 945
 946 2019-07-01  Matthew Malcomson  <matthew.malcomson@arm.com>
 947
 948         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Use new
 949         sve_size_13 icode to account for variant behaviour of
 950         pmull{t,b}.
 951         * aarch64-dis-2.c: Regenerate.
 952         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Use new
 953         sve_size_13 icode to account for variant behaviour of
 954         pmull{t,b}.
 955         * aarch64-tbl.h (OP_SVE_VVV_HD_BS): Add new qualifier.
 956         (OP_SVE_VVV_Q_D): Add new qualifier.
 957         (OP_SVE_VVV_QHD_DBS): Remove now unused qualifier.
 958         (struct aarch64_opcode): Split pmull{t,b} into those requiring
 959         AES and those not.
 960
 961 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 962
 963         * opcodes/i386-gen.c (operand_type_init): Remove
 964         OPERAND_TYPE_VEC_IMM4 entry.
 965         (operand_types): Remove Vec_Imm4.
 966         * opcodes/i386-opc.h (Vec_Imm4): Delete.
 967         (union i386_operand_type): Remove vec_imm4.
 968         * i386-opc.tbl (vpermil2pd, vpermil2ps): Remove Vec_Imm4.
 969         * opcodes/i386-init.h, i386-tbl.h: Re-generate.
 970
 971 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 972
 973         * i386-opc.tbl (lfence, mfence, sfence, monitor, mwait, vmcall,
 974         vmlaunch, vmresume, vmxoff, vmfunc, xgetbv, xsetbv, swapgs,
 975         rdtscp, clgi, invlpga, skinit, stgi, vmload, vmmcall, vmrun,
 976         vmsave, montmul, xsha1, xsha256, xstorerng, xcryptecb,
 977         xcryptcbc, xcryptctr, xcryptcfb, xcryptofb, xstore, clac, stac,
 978         monitorx, mwaitx): Drop ImmExt from operand-less forms.
 979         * i386-tbl.h: Re-generate.
 980
 981 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 982
 983         * i386-opc.tbl (and, or): Add Optimize to forms allowing two
 984         register operands.
 985         * i386-tbl.h: Re-generate.
 986
 987 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 988
 989         * i386-opc.tbl (C): New.
 990         (paddb, paddw, paddd, paddq, paddsb, paddsw, paddusb, paddusw,
 991         pand, pcmpeqb, pcmpeqw, pcmpeqd, pmaddwd, pmulhw, pmullw,
 992         por, pxor, andps, cmpeqps, cmpeqss, cmpneqps, cmpneqss,
 993         cmpordps, cmpordss, cmpunordps, cmpunordss, orps, pavgb, pavgw,
 994         pmaxsw, pmaxub, pminsw, pminub, pmulhuw, xorps, andpd, cmpeqpd,
 995         cmpeqsd, cmpneqpd, cmpneqsd, cmpordpd, cmpordsd, cmpunordpd,
 996         cmpunordsd, orpd, xorpd, pmuludq, vandpd, vandps, vcmpeq_ospd,
 997         vcmpeq_osps, vcmpeq_ossd, vcmpeq_osss, vcmpeqpd, vcmpeqps,
 998         vcmpeqsd, vcmpeqss, vcmpeq_uqpd, vcmpeq_uqps, vcmpeq_uqsd,
 999         vcmpeq_uqss, vcmpeq_uspd, vcmpeq_usps, vcmpeq_ussd,
1000         vcmpeq_usss, vcmpfalse_ospd, vcmpfalse_osps, vcmpfalse_ossd,
1001         vcmpfalse_osss, vcmpfalsepd, vcmpfalseps, vcmpfalsesd,
1002         vcmpfalsess, vcmpneq_oqpd, vcmpneq_oqps, vcmpneq_oqsd,
1003         vcmpneq_oqss, vcmpneq_ospd, vcmpneq_osps, vcmpneq_ossd,
1004         vcmpneq_osss, vcmpneqpd, vcmpneqps, vcmpneqsd, vcmpneqss,
1005         vcmpneq_uspd, vcmpneq_usps, vcmpneq_ussd, vcmpneq_usss,
1006         vcmpordpd, vcmpordps, vcmpordsd, vcmpord_spd, vcmpord_sps,
1007         vcmpordss, vcmpord_ssd, vcmpord_sss, vcmptruepd, vcmptrueps,
1008         vcmptruesd, vcmptruess, vcmptrue_uspd, vcmptrue_usps,
1009         vcmptrue_ussd, vcmptrue_usss, vcmpunordpd, vcmpunordps,
1010         vcmpunordsd, vcmpunord_spd, vcmpunord_sps, vcmpunordss,
1011         vcmpunord_ssd, vcmpunord_sss, vorpd, vorps, vpaddsb, vpaddsw,
1012         vpaddb, vpaddd, vpaddq, vpaddw, vpaddusb, vpaddusw, vpand,
1013         vpavgb, vpavgw, vpcmpeqb, vpcmpeqd, vpcmpeqw, vpmaddwd,
1014         vpmaxsw, vpmaxub, vpminsw, vpminub, vpmulhuw, vpmulhw, vpmullw,
1015         vpmuludq, vpor, vpxor, vxorpd, vxorps): Add C to VEX-encoded
1016         flavors.
1017         * i386-tbl.h: Re-generate.
1018
1019 2019-07-01  Jan Beulich  <jbeulich@suse.com>
1020
1021         * i386-opc.tbl (and, or): Add Optimize to forms allowing two
1022         register operands.
1023         * i386-tbl.h: Re-generate.
1024
1025 2019-07-01  Jan Beulich  <jbeulich@suse.com>
1026
1027         * i386-dis-evex-prefix.h: Use PCLMUL for vpclmulqdq.
1028         * i386-opc.tbl (vpclmullqlqdq, vpclmulhqlqdq, vpclmullqhqdq,
1029         vpclmulhqhqdq): Add CpuVPCLMULQDQ flavors.
1030         * i386-tbl.h: Re-generate.
1031
1032 2019-07-01  Jan Beulich  <jbeulich@suse.com>
1033
1034         * i386-opc.tbl (vextractps, vpextrw, vpinsrw): Remove
1035         Disp8MemShift from register only templates.
1036         * i386-tbl.h: Re-generate.
1037
1038 2019-07-01  Jan Beulich  <jbeulich@suse.com>
1039
1040         * i386-dis.c (EXdScalarS, MOD_EVEX_0F10_PREFIX_1,
1041         MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1,
1042         MOD_EVEX_0F11_PREFIX_3, EVEX_W_0F10_P_1_M_0,
1043         EVEX_W_0F10_P_1_M_1, EVEX_W_0F10_P_3_M_0, EVEX_W_0F10_P_3_M_1,
1044         EVEX_W_0F11_P_1_M_0, EVEX_W_0F11_P_1_M_1, EVEX_W_0F11_P_3_M_0,
1045         EVEX_W_0F11_P_3_M_1): Delete.
1046         (EVEX_W_0F10_P_1, EVEX_W_0F10_P_3, EVEX_W_0F11_P_1,
1047         EVEX_W_0F11_P_3): New.
1048         * i386-dis-evex-mod.h: Remove MOD_EVEX_0F10_PREFIX_1,
1049         MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1, and
1050         MOD_EVEX_0F11_PREFIX_3 table entries.
1051         * i386-dis-evex-prefix.h: Adjust PREFIX_EVEX_0F10 and
1052         PREFIX_EVEX_0F11 table entries.
1053         * i386-dis-evex-w.h: Replace EVEX_W_0F10_P_1_M_{0,1},
1054         EVEX_W_0F10_P_3_M_{0,1}, EVEX_W_0F11_P_1_M_{0,1}, and
1055         EVEX_W_0F11_P_3_M_{0,1} table entries.
1056
1057 2019-07-01  Jan Beulich  <jbeulich@suse.com>
1058
1059         * i386-dis.c (EXdVex, EXdVexS, EXqVex, EXqVexS, XMVex):
1060         Delete.
1061
1062 2019-06-27  H.J. Lu  <hongjiu.lu@intel.com>
1063
1064         PR binutils/24719
1065         * i386-dis-evex-len.h: Add EVEX_LEN_0F38C6_REG_1_PREFIX_2,
1066         EVEX_LEN_0F38C6_REG_2_PREFIX_2, EVEX_LEN_0F38C6_REG_5_PREFIX_2,
1067         EVEX_LEN_0F38C6_REG_6_PREFIX_2, EVEX_LEN_0F38C7_R_1_P_2_W_0,
1068         EVEX_LEN_0F38C7_R_1_P_2_W_1, EVEX_LEN_0F38C7_R_2_P_2_W_0,
1069         EVEX_LEN_0F38C7_R_2_P_2_W_1, EVEX_LEN_0F38C7_R_5_P_2_W_0,
1070         EVEX_LEN_0F38C7_R_5_P_2_W_1, EVEX_LEN_0F38C7_R_6_P_2_W_0 and
1071         EVEX_LEN_0F38C7_R_6_P_2_W_1.
1072         * i386-dis-evex-prefix.h: Update PREFIX_EVEX_0F38C6_REG_1,
1073         PREFIX_EVEX_0F38C6_REG_2, PREFIX_EVEX_0F38C6_REG_5 and
1074         PREFIX_EVEX_0F38C6_REG_6 entries.
1075         * i386-dis-evex-w.h: Update EVEX_W_0F38C7_R_1_P_2,
1076         EVEX_W_0F38C7_R_2_P_2, EVEX_W_0F38C7_R_5_P_2 and
1077         EVEX_W_0F38C7_R_6_P_2 entries.
1078         * i386-dis.c: Add EVEX_LEN_0F38C6_REG_1_PREFIX_2,
1079         EVEX_LEN_0F38C6_REG_2_PREFIX_2, EVEX_LEN_0F38C6_REG_5_PREFIX_2,
1080         EVEX_LEN_0F38C6_REG_6_PREFIX_2, EVEX_LEN_0F38C7_R_1_P_2_W_0,
1081         EVEX_LEN_0F38C7_R_1_P_2_W_1, EVEX_LEN_0F38C7_R_2_P_2_W_0,
1082         EVEX_LEN_0F38C7_R_2_P_2_W_1, EVEX_LEN_0F38C7_R_5_P_2_W_0,
1083         EVEX_LEN_0F38C7_R_5_P_2_W_1, EVEX_LEN_0F38C7_R_6_P_2_W_0 and
1084         EVEX_LEN_0F38C7_R_6_P_2_W_1 enums.
1085
1086 2019-06-27  Jan Beulich  <jbeulich@suse.com>
1087
1088         * i386-dis.c (VEX_LEN_0F2A_P_1, VEX_LEN_0F2A_P_3,
1089         VEX_LEN_0F2C_P_1, VEX_LEN_0F2C_P_3, VEX_LEN_0F2D_P_1,
1090         VEX_LEN_0F2D_P_3): Delete.
1091         (vex_len_table): Move vcvtsi2ss, vcvtsi2sd, vcvttss2si,
1092         vcvttsd2si, vcvtss2si, and vcvtsd2si leaf entries ...
1093         (prefix_table): ... here.
1094
1095 2019-06-27  Jan Beulich  <jbeulich@suse.com>
1096
1097         * i386-dis.c (Iq): Delete.
1098         (Id): New.
1099         (reg_table): Use it for lwpins, lwpval, and bextr. Use Edq for
1100         TBM insns.
1101         (vex_len_table): Use Edq for vcvtsi2ss, vcvtsi2sd. Use Gdq for
1102         vcvttss2si, vcvttsd2si, vcvtss2si, and vcvtsd2si.
1103         (OP_E_memory): Also honor needindex when deciding whether an
1104         address size prefix needs printing.
1105         (OP_I): Remove handling of q_mode. Add handling of d_mode.
1106
1107 2019-06-26  Jim Wilson  <jimw@sifive.com>
1108
1109         PR binutils/24739
1110         * riscv-dis.c (riscv_disasemble_insn): Set info->endian_code.
1111         Set info->display_endian to info->endian_code.
1112
1113 2019-06-25  Jan Beulich  <jbeulich@suse.com>
1114
1115         * i386-gen.c (operand_type_init): Correct OPERAND_TYPE_DEBUG
1116         entry. Drop OPERAND_TYPE_ACC entry. Add OPERAND_TYPE_ACC8 and
1117         OPERAND_TYPE_ACC16 entries. Adjust OPERAND_TYPE_ACC32 and
1118         OPERAND_TYPE_ACC64 entries.
1119         * i386-init.h: Re-generate.
1120
1121 2019-06-25  Jan Beulich  <jbeulich@suse.com>
1122
1123         * i386-dis.c (Edqa, dqa_mode, EVEX_W_0F2A_P_1, EVEX_W_0F7B_P_1):
1124         Delete.
1125         (intel_operand_size, OP_E_register, OP_E_memory): Drop handling
1126         of dqa_mode.
1127         * i386-dis-evex-prefix.h: Move vcvtsi2ss and vcvtusi2ss leaf
1128         entries here.
1129         * i386-dis-evex-w.h: Drop EVEX_W_0F2A_P_1 and EVEX_W_0F7B_P_1
1130         entries. Use Edq for vcvtsi2sd and vcvtusi2sd.
1131
1132 2019-06-25  Jan Beulich  <jbeulich@suse.com>
1133
1134         * i386-dis.c (OP_I64): Forword more cases to OP_I(). Drop local
1135         variables.
1136
1137 2019-06-25  Jan Beulich  <jbeulich@suse.com>
1138
1139         * i386-dis.c (prefix_table): Use Edq for cvtsi2ss and cvtsi2sd.
1140         Use Gdq for cvttss2si, cvttsd2si, cvtss2si, and cvtsd2si, and
1141         movnti.
1142         * i386-opc.tbl (movnti): Add IgnoreSize.
1143         * i386-tbl.h: Re-generate.
1144
1145 2019-06-25  Jan Beulich  <jbeulich@suse.com>
1146
1147         * i386-opc.tbl (and): Mark Imm8S form for optimization.
1148         * i386-tbl.h: Re-generate.
1149
1150 2019-06-21  H.J. Lu  <hongjiu.lu@intel.com>
1151
1152         * i386-dis-evex.h: Break into ...
1153         * i386-dis-evex-len.h: New file.
1154         * i386-dis-evex-mod.h: Likewise.
1155         * i386-dis-evex-prefix.h: Likewise.
1156         * i386-dis-evex-reg.h: Likewise.
1157         * i386-dis-evex-w.h: Likewise.
1158         * i386-dis.c: Include i386-dis-evex-reg.h, i386-dis-evex-prefix.h,
1159         i386-dis-evex.h, i386-dis-evex-len.h, i386-dis-evex-w.h and
1160         i386-dis-evex-mod.h.
1161
1162 2019-06-19  H.J. Lu  <hongjiu.lu@intel.com>
1163
1164         PR binutils/24700
1165         * i386-dis-evex.h (evex_table): Update EVEX_W_0F3819_P_2,
1166         EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2, EVEX_W_0F385A_P_2 and
1167         EVEX_W_0F385B_P_2.
1168         (evex_len_table): Add EVEX_LEN_0F3819_P_2_W_0,
1169         EVEX_LEN_0F3819_P_2_W_1, EVEX_LEN_0F381A_P_2_W_0,
1170         EVEX_LEN_0F381A_P_2_W_1, EVEX_LEN_0F381B_P_2_W_0,
1171         EVEX_LEN_0F381B_P_2_W_1, EVEX_LEN_0F385A_P_2_W_0,
1172         EVEX_LEN_0F385A_P_2_W_1, EVEX_LEN_0F385B_P_2_W_0 and
1173         EVEX_LEN_0F385B_P_2_W_1.
1174         * i386-dis.c (EVEX_LEN_0F3819_P_2_W_0): New enum.
1175         (EVEX_LEN_0F3819_P_2_W_1): Likewise.
1176         (EVEX_LEN_0F381A_P_2_W_0): Likewise.
1177         (EVEX_LEN_0F381A_P_2_W_1): Likewise.
1178         (EVEX_LEN_0F381B_P_2_W_0): Likewise.
1179         (EVEX_LEN_0F381B_P_2_W_1): Likewise.
1180         (EVEX_LEN_0F385A_P_2_W_0): Likewise.
1181         (EVEX_LEN_0F385A_P_2_W_1): Likewise.
1182         (EVEX_LEN_0F385B_P_2_W_0): Likewise.
1183         (EVEX_LEN_0F385B_P_2_W_1): Likewise.
1184
1185 2019-06-17  H.J. Lu  <hongjiu.lu@intel.com>
1186
1187         PR binutils/24691
1188         * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A23_P_2,
1189         EVEX_W_0F3A38_P_2, EVEX_W_0F3A39_P_2, EVEX_W_0F3A3A_P_2,
1190         EVEX_W_0F3A3B_P_2 and EVEX_W_0F3A43_P_2.
1191         (evex_len_table): Add EVEX_LEN_0F3A23_P_2_W_0,
1192         EVEX_LEN_0F3A23_P_2_W_1, EVEX_LEN_0F3A38_P_2_W_0,
1193         EVEX_LEN_0F3A38_P_2_W_1, EVEX_LEN_0F3A39_P_2_W_0,
1194         EVEX_LEN_0F3A39_P_2_W_1, EVEX_LEN_0F3A3A_P_2_W_0,
1195         EVEX_LEN_0F3A3A_P_2_W_1, EVEX_LEN_0F3A3B_P_2_W_0,
1196         EVEX_LEN_0F3A3B_P_2_W_1, EVEX_LEN_0F3A43_P_2_W_0 and
1197         EVEX_LEN_0F3A43_P_2_W_1.
1198         * i386-dis.c (EVEX_LEN_0F3A23_P_2_W_0): New enum.
1199         (EVEX_LEN_0F3A23_P_2_W_1): Likewise.
1200         (EVEX_LEN_0F3A38_P_2_W_0): Likewise.
1201         (EVEX_LEN_0F3A38_P_2_W_1): Likewise.
1202         (EVEX_LEN_0F3A39_P_2_W_0): Likewise.
1203         (EVEX_LEN_0F3A39_P_2_W_1): Likewise.
1204         (EVEX_LEN_0F3A3A_P_2_W_0): Likewise.
1205         (EVEX_LEN_0F3A3A_P_2_W_1): Likewise.
1206         (EVEX_LEN_0F3A3B_P_2_W_0): Likewise.
1207         (EVEX_LEN_0F3A3B_P_2_W_1): Likewise.
1208         (EVEX_LEN_0F3A43_P_2_W_0): Likewise.
1209         (EVEX_LEN_0F3A43_P_2_W_1): Likewise.
1210
1211 2019-06-14  Nick Clifton  <nickc@redhat.com>
1212
1213         * po/fr.po; Updated French translation.
1214
1215 2019-06-13  Stafford Horne  <shorne@gmail.com>
1216
1217         * or1k-asm.c: Regenerated.
1218         * or1k-desc.c: Regenerated.
1219         * or1k-desc.h: Regenerated.
1220         * or1k-dis.c: Regenerated.
1221         * or1k-ibld.c: Regenerated.
1222         * or1k-opc.c: Regenerated.
1223         * or1k-opc.h: Regenerated.
1224         * or1k-opinst.c: Regenerated.
1225
1226 2019-06-12  Peter Bergner  <bergner@linux.ibm.com>
1227
1228         * ppc-opc.c (powerpc_opcodes) <ldmx>: Delete mnemonic.
1229
1230 2019-06-05  H.J. Lu  <hongjiu.lu@intel.com>
1231
1232         PR binutils/24633
1233         * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A18_P_2,
1234         EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2 and EVEX_W_0F3A1B_P_2.
1235         (evex_len_table): EVEX_LEN_0F3A18_P_2_W_0,
1236         EVEX_LEN_0F3A18_P_2_W_1, EVEX_LEN_0F3A19_P_2_W_0,
1237         EVEX_LEN_0F3A19_P_2_W_1, EVEX_LEN_0F3A1A_P_2_W_0,
1238         EVEX_LEN_0F3A1A_P_2_W_1, EVEX_LEN_0F3A1B_P_2_W_0,
1239         EVEX_LEN_0F3A1B_P_2_W_1.
1240         * i386-dis.c (EVEX_LEN_0F3A18_P_2_W_0): New enum.
1241         (EVEX_LEN_0F3A18_P_2_W_1): Likewise.
1242         (EVEX_LEN_0F3A19_P_2_W_0): Likewise.
1243         (EVEX_LEN_0F3A19_P_2_W_1): Likewise.
1244         (EVEX_LEN_0F3A1A_P_2_W_0): Likewise.
1245         (EVEX_LEN_0F3A1A_P_2_W_1): Likewise.
1246         (EVEX_LEN_0F3A1B_P_2_W_0): Likewise.
1247         (EVEX_LEN_0F3A1B_P_2_W_1): Likewise.
1248
1249 2019-06-04  H.J. Lu  <hongjiu.lu@intel.com>
1250
1251         PR binutils/24626
1252         * i386-dis.c (print_insn): Check for unused VEX.vvvv and
1253         EVEX.vvvv when disassembling VEX and EVEX instructions.
1254         (OP_VEX): Set vex.register_specifier to 0 after readding
1255         vex.register_specifier.
1256         (OP_Vex_2src_1): Likewise.
1257         (OP_Vex_2src_2): Likewise.
1258         (OP_LWP_E): Likewise.
1259         (OP_EX_Vex): Don't check vex.register_specifier.
1260         (OP_XMM_Vex): Likewise.
1261
1262 2019-06-04  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
1263             Lili Cui  <lili.cui@intel.com>
1264
1265         * i386-dis.c (enum): Add PREFIX_EVEX_0F3868, EVEX_W_0F3868_P_3.
1266         * i386-dis-evex.h (evex_table): Add AVX512_VP2INTERSECT
1267         instructions.
1268         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VP2INTERSECT_FLAGS,
1269         CPU_ANY_AVX512_VP2INTERSECT_FLAGS.
1270         (cpu_flags): Add CpuAVX512_VP2INTERSECT.
1271         * i386-opc.h (enum): Add CpuAVX512_VP2INTERSECT.
1272         (i386_cpu_flags): Add cpuavx512_vp2intersect.
1273         * i386-opc.tbl: Add AVX512_VP2INTERSECT insns.
1274         * i386-init.h: Regenerated.
1275         * i386-tbl.h: Likewise.
1276
1277 2019-06-04  Xuepeng Guo  <xuepeng.guo@intel.com>
1278             Lili Cui  <lili.cui@intel.com>
1279
1280         * doc/c-i386.texi: Document enqcmd.
1281         * testsuite/gas/i386/enqcmd-intel.d: New file.
1282         * testsuite/gas/i386/enqcmd-inval.l: Likewise.
1283         * testsuite/gas/i386/enqcmd-inval.s: Likewise.
1284         * testsuite/gas/i386/enqcmd.d: Likewise.
1285         * testsuite/gas/i386/enqcmd.s: Likewise.
1286         * testsuite/gas/i386/x86-64-enqcmd-intel.d: Likewise.
1287         * testsuite/gas/i386/x86-64-enqcmd-inval.l: Likewise.
1288         * testsuite/gas/i386/x86-64-enqcmd-inval.s: Likewise.
1289         * testsuite/gas/i386/x86-64-enqcmd.d: Likewise.
1290         * testsuite/gas/i386/x86-64-enqcmd.s: Likewise.
1291         * testsuite/gas/i386/i386.exp: Run enqcmd-intel, enqcmd-inval,
1292         enqcmd, x86-64-enqcmd-intel, x86-64-enqcmd-inval,
1293         and x86-64-enqcmd.
1294
1295 2019-06-04  Alan Hayward  <alan.hayward@arm.com>
1296
1297         * arm-dis.c (is_mve_unpredictable): Remove spurious paranthesis.
1298
1299 2019-06-03  Alan Modra  <amodra@gmail.com>
1300
1301         * ppc-dis.c (prefix_opcd_indices): Correct size.
1302
1303 2019-05-28  H.J. Lu  <hongjiu.lu@intel.com>
1304
1305         PR gas/24625
1306         * i386-opc.tbl: Add CheckRegSize to AVX512_BF16 instructions with
1307         Disp8ShiftVL.
1308         * i386-tbl.h: Regenerated.
1309
1310 2019-05-24  Alan Modra  <amodra@gmail.com>
1311
1312         * po/POTFILES.in: Regenerate.
1313
1314 2019-05-24  Peter Bergner  <bergner@linux.ibm.com>
1315             Alan Modra  <amodra@gmail.com>
1316
1317         * ppc-opc.c (insert_d34, extract_d34, insert_nsi34, extract_nsi34),
1318         (insert_pcrel, extract_pcrel, extract_pcrel0): New functions.
1319         (extract_esync, extract_raq, extract_tbr, extract_sxl): Comment.
1320         (powerpc_operands <D34, SI34, NSI34, PRA0, PRAQ, PCREL, PCREL0,
1321         XTOP>): Define and add entries.
1322         (P8LS, PMLS, P_D_MASK, P_DRAPCREL_MASK): Define.
1323         (prefix_opcodes): Add pli, paddi, pla, psubi, plwz, plbz, pstw,
1324         pstb, plhz, plha, psth, plfs, plfd, pstfs, pstfd, plq, plxsd,
1325         plxssp, pld, plwa, pstxsd, pstxssp, pstxv, pstd, and pstq.
1326
1327 2019-05-24  Peter Bergner  <bergner@linux.ibm.com>
1328             Alan Modra  <amodra@gmail.com>
1329
1330         * ppc-dis.c (ppc_opts): Add "future" entry.
1331         (PREFIX_OPCD_SEGS): Define.
1332         (prefix_opcd_indices): New array.
1333         (disassemble_init_powerpc): Initialize prefix_opcd_indices.
1334         (lookup_prefix): New function.
1335         (print_insn_powerpc): Handle 64-bit prefix instructions.
1336         * ppc-opc.c (PREFIX_OP, PREFIX_FORM, SUFFIX_MASK, PREFIX_MASK),
1337         (PMRR, POWERXX): Define.
1338         (prefix_opcodes): New instruction table.
1339         (prefix_num_opcodes): New constant.
1340
1341 2019-05-23  Jose E. Marchesi  <jose.marchesi@oracle.com>
1342
1343         * configure.ac (SHARED_DEPENDENCIES): Add case for bfd_bpf_arch.
1344         * configure: Regenerated.
1345         * Makefile.am: Add rules for the files generated from cpu/bpf.cpu
1346         and cpu/bpf.opc.
1347         (HFILES): Add bpf-desc.h and bpf-opc.h.
1348         (TARGET_LIBOPCODES_CFILES): Add bpf-asm.c, bpf-desc.c, bpf-dis.c,
1349         bpf-ibld.c and bpf-opc.c.
1350         (BPF_DEPS): Define.
1351         * Makefile.in: Regenerated.
1352         * disassemble.c (ARCH_bpf): Define.
1353         (disassembler): Add case for bfd_arch_bpf.
1354         (disassemble_init_for_target): Likewise.
1355         (enum epbf_isa_attr): Define.
1356         * disassemble.h: extern print_insn_bpf.
1357         * bpf-asm.c: Generated.
1358         * bpf-opc.h: Likewise.
1359         * bpf-opc.c: Likewise.
1360         * bpf-ibld.c: Likewise.
1361         * bpf-dis.c: Likewise.
1362         * bpf-desc.h: Likewise.
1363         * bpf-desc.c: Likewise.
1364
1365 2019-05-21  Sudakshina Das  <sudi.das@arm.com>
1366
1367         * arm-dis.c (coprocessor_opcodes): New instructions for VMRS
1368         and VMSR with the new operands.
1369
1370 2019-05-21  Sudakshina Das  <sudi.das@arm.com>
1371
1372         * arm-dis.c (enum mve_instructions): New enum
1373         for csinc, csinv, csneg, csel, cset, csetm, cinv, cinv
1374         and cneg.
1375         (mve_opcodes): New instructions as above.
1376         (is_mve_encoding_conflict): Add cases for csinc, csinv,
1377         csneg and csel.
1378         (print_insn_mve): Accept new %<bitfield>c and %<bitfield>C.
1379
1380 2019-05-21  Sudakshina Das  <sudi.das@arm.com>
1381
1382         * arm-dis.c (emun mve_instructions): Updated for new instructions.
1383         (mve_opcodes): New instructions for asrl, lsll, lsrl, sqrshrl,
1384         sqrshr, sqshl, sqshll, srshr, srshrl, uqrshll, uqrshl, uqshll,
1385         uqshl, urshrl and urshr.
1386         (is_mve_okay_in_it): Add new instructions to TRUE list.
1387         (is_mve_unpredictable): Add cases for UNPRED_R13 and UNPRED_R15.
1388         (print_insn_mve): Updated to accept new %j,
1389         %<bitfield>m and %<bitfield>n patterns.
1390
1391 2019-05-21  Faraz Shahbazker  <fshahbazker@wavecomp.com>
1392
1393         * mips-opc.c (mips_builtin_opcodes): Change source register
1394         constraint for DAUI.
1395
1396 2019-05-20  Nick Clifton  <nickc@redhat.com>
1397
1398         * po/fr.po: Updated French translation.
1399
1400 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1401             Michael Collison <michael.collison@arm.com>
1402
1403         * arm-dis.c (thumb32_opcodes): Add new instructions.
1404         (enum mve_instructions): Likewise.
1405         (enum mve_undefined): Add new reasons.
1406         (is_mve_encoding_conflict): Handle new instructions.
1407         (is_mve_undefined): Likewise.
1408         (is_mve_unpredictable): Likewise.
1409         (print_mve_undefined): Likewise.
1410         (print_mve_size): Likewise.
1411
1412 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1413             Michael Collison <michael.collison@arm.com>
1414
1415         * arm-dis.c (thumb32_opcodes): Add new instructions.
1416         (enum mve_instructions): Likewise.
1417         (is_mve_encoding_conflict): Handle new instructions.
1418         (is_mve_undefined): Likewise.
1419         (is_mve_unpredictable): Likewise.
1420         (print_mve_size): Likewise.
1421
1422 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1423             Michael Collison <michael.collison@arm.com>
1424
1425         * arm-dis.c (thumb32_opcodes): Add new instructions.
1426         (enum mve_instructions): Likewise.
1427         (is_mve_encoding_conflict): Likewise.
1428         (is_mve_unpredictable): Likewise.
1429         (print_mve_size): Likewise.
1430
1431 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1432             Michael Collison <michael.collison@arm.com>
1433
1434         * arm-dis.c (thumb32_opcodes): Add new instructions.
1435         (enum mve_instructions): Likewise.
1436         (is_mve_encoding_conflict): Handle new instructions.
1437         (is_mve_undefined): Likewise.
1438         (is_mve_unpredictable): Likewise.
1439         (print_mve_size): Likewise.
1440
1441 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1442             Michael Collison <michael.collison@arm.com>
1443
1444         * arm-dis.c (thumb32_opcodes): Add new instructions.
1445         (enum mve_instructions): Likewise.
1446         (is_mve_encoding_conflict): Handle new instructions.
1447         (is_mve_undefined): Likewise.
1448         (is_mve_unpredictable): Likewise.
1449         (print_mve_size): Likewise.
1450         (print_insn_mve): Likewise.
1451
1452 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1453             Michael Collison <michael.collison@arm.com>
1454
1455         * arm-dis.c (thumb32_opcodes): Add new instructions.
1456         (print_insn_thumb32): Handle new instructions.
1457
1458 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1459             Michael Collison <michael.collison@arm.com>
1460
1461         * arm-dis.c (enum mve_instructions): Add new instructions.
1462         (enum mve_undefined): Add new reasons.
1463         (is_mve_encoding_conflict): Handle new instructions.
1464         (is_mve_undefined): Likewise.
1465         (is_mve_unpredictable): Likewise.
1466         (print_mve_undefined): Likewise.
1467         (print_mve_size): Likewise.
1468         (print_mve_shift_n): Likewise.
1469         (print_insn_mve): Likewise.
1470
1471 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1472             Michael Collison <michael.collison@arm.com>
1473
1474         * arm-dis.c (enum mve_instructions): Add new instructions.
1475         (is_mve_encoding_conflict): Handle new instructions.
1476         (is_mve_unpredictable): Likewise.
1477         (print_mve_rotate): Likewise.
1478         (print_mve_size): Likewise.
1479         (print_insn_mve): Likewise.
1480
1481 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1482             Michael Collison <michael.collison@arm.com>
1483
1484         * arm-dis.c (enum mve_instructions): Add new instructions.
1485         (is_mve_encoding_conflict): Handle new instructions.
1486         (is_mve_unpredictable): Likewise.
1487         (print_mve_size): Likewise.
1488         (print_insn_mve): Likewise.
1489
1490 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1491             Michael Collison <michael.collison@arm.com>
1492
1493         * arm-dis.c (enum mve_instructions): Add new instructions.
1494         (enum mve_undefined): Add new reasons.
1495         (is_mve_encoding_conflict): Handle new instructions.
1496         (is_mve_undefined): Likewise.
1497         (is_mve_unpredictable): Likewise.
1498         (print_mve_undefined): Likewise.
1499         (print_mve_size): Likewise.
1500         (print_insn_mve): Likewise.
1501
1502 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1503             Michael Collison <michael.collison@arm.com>
1504
1505         * arm-dis.c (enum mve_instructions): Add new instructions.
1506         (is_mve_encoding_conflict): Handle new instructions.
1507         (is_mve_undefined): Likewise.
1508         (is_mve_unpredictable): Likewise.
1509         (print_mve_size): Likewise.
1510         (print_insn_mve): Likewise.
1511
1512 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1513             Michael Collison <michael.collison@arm.com>
1514
1515         * arm-dis.c (enum mve_instructions): Add new instructions.
1516         (enum mve_unpredictable): Add new reasons.
1517         (enum mve_undefined): Likewise.
1518         (is_mve_okay_in_it): Handle new isntructions.
1519         (is_mve_encoding_conflict): Likewise.
1520         (is_mve_undefined): Likewise.
1521         (is_mve_unpredictable): Likewise.
1522         (print_mve_vmov_index): Likewise.
1523         (print_simd_imm8): Likewise.
1524         (print_mve_undefined): Likewise.
1525         (print_mve_unpredictable): Likewise.
1526         (print_mve_size): Likewise.
1527         (print_insn_mve): Likewise.
1528
1529 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1530             Michael Collison <michael.collison@arm.com>
1531
1532         * arm-dis.c (enum mve_instructions): Add new instructions.
1533         (enum mve_unpredictable): Add new reasons.
1534         (enum mve_undefined): Likewise.
1535         (is_mve_encoding_conflict): Handle new instructions.
1536         (is_mve_undefined): Likewise.
1537         (is_mve_unpredictable): Likewise.
1538         (print_mve_undefined): Likewise.
1539         (print_mve_unpredictable): Likewise.
1540         (print_mve_rounding_mode): Likewise.
1541         (print_mve_vcvt_size): Likewise.
1542         (print_mve_size): Likewise.
1543         (print_insn_mve): Likewise.
1544
1545 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1546             Michael Collison <michael.collison@arm.com>
1547
1548         * arm-dis.c (enum mve_instructions): Add new instructions.
1549         (enum mve_unpredictable): Add new reasons.
1550         (enum mve_undefined): Likewise.
1551         (is_mve_undefined): Handle new instructions.
1552         (is_mve_unpredictable): Likewise.
1553         (print_mve_undefined): Likewise.
1554         (print_mve_unpredictable): Likewise.
1555         (print_mve_size): Likewise.
1556         (print_insn_mve): Likewise.
1557
1558 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1559             Michael Collison <michael.collison@arm.com>
1560
1561         * arm-dis.c (enum mve_instructions): Add new instructions.
1562         (enum mve_undefined): Add new reasons.
1563         (insns): Add new instructions.
1564         (is_mve_encoding_conflict):
1565         (print_mve_vld_str_addr): New print function.
1566         (is_mve_undefined): Handle new instructions.
1567         (is_mve_unpredictable): Likewise.
1568         (print_mve_undefined): Likewise.
1569         (print_mve_size): Likewise.
1570         (print_insn_coprocessor_1): Handle MVE VLDR, VSTR instructions.
1571         (print_insn_mve):  Handle new operands.
1572
1573 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1574             Michael Collison <michael.collison@arm.com>
1575
1576         * arm-dis.c (enum mve_instructions): Add new instructions.
1577         (enum mve_unpredictable): Add new reasons.
1578         (is_mve_encoding_conflict): Handle new instructions.
1579         (is_mve_unpredictable): Likewise.
1580         (mve_opcodes): Add new instructions.
1581         (print_mve_unpredictable): Handle new reasons.
1582         (print_mve_register_blocks): New print function.
1583         (print_mve_size): Handle new instructions.
1584         (print_insn_mve): Likewise.
1585
1586 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1587             Michael Collison <michael.collison@arm.com>
1588
1589         * arm-dis.c (enum mve_instructions): Add new instructions.
1590         (enum mve_unpredictable): Add new reasons.
1591         (enum mve_undefined): Likewise.
1592         (is_mve_encoding_conflict): Handle new instructions.
1593         (is_mve_undefined): Likewise.
1594         (is_mve_unpredictable): Likewise.
1595         (coprocessor_opcodes): Move NEON VDUP from here...
1596         (neon_opcodes): ... to here.
1597         (mve_opcodes): Add new instructions.
1598         (print_mve_undefined):  Handle new reasons.
1599         (print_mve_unpredictable): Likewise.
1600         (print_mve_size): Handle new instructions.
1601         (print_insn_neon): Handle vdup.
1602         (print_insn_mve): Handle new operands.
1603
1604 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1605             Michael Collison <michael.collison@arm.com>
1606
1607         * arm-dis.c (enum mve_instructions): Add new instructions.
1608         (enum mve_unpredictable): Add new values.
1609         (mve_opcodes): Add new instructions.
1610         (vec_condnames): New array with vector conditions.
1611         (mve_predicatenames): New array with predicate suffixes.
1612         (mve_vec_sizename): New array with vector sizes.
1613         (enum vpt_pred_state): New enum with vector predication states.
1614         (struct vpt_block): New struct type for vpt blocks.
1615         (vpt_block_state): Global struct to keep track of state.
1616         (mve_extract_pred_mask): New helper function.
1617         (num_instructions_vpt_block): Likewise.
1618         (mark_outside_vpt_block): Likewise.
1619         (mark_inside_vpt_block): Likewise.
1620         (invert_next_predicate_state): Likewise.
1621         (update_next_predicate_state): Likewise.
1622         (update_vpt_block_state): Likewise.
1623         (is_vpt_instruction): Likewise.
1624         (is_mve_encoding_conflict): Add entries for new instructions.
1625         (is_mve_unpredictable): Likewise.
1626         (print_mve_unpredictable): Handle new cases.
1627         (print_instruction_predicate): Likewise.
1628         (print_mve_size): New function.
1629         (print_vec_condition): New function.
1630         (print_insn_mve): Handle vpt blocks and new print operands.
1631
1632 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1633
1634         * arm-dis.c (print_insn_coprocessor_1): Disable the use of coprocessors
1635         8, 14 and 15 for Armv8.1-M Mainline.
1636
1637 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1638             Michael Collison <michael.collison@arm.com>
1639
1640         * arm-dis.c (enum mve_instructions): New enum.
1641         (enum mve_unpredictable): Likewise.
1642         (enum mve_undefined): Likewise.
1643         (struct mopcode32): New struct.
1644         (is_mve_okay_in_it): New function.
1645         (is_mve_architecture): Likewise.
1646         (arm_decode_field): Likewise.
1647         (arm_decode_field_multiple): Likewise.
1648         (is_mve_encoding_conflict): Likewise.
1649         (is_mve_undefined): Likewise.
1650         (is_mve_unpredictable): Likewise.
1651         (print_mve_undefined): Likewise.
1652         (print_mve_unpredictable): Likewise.
1653         (print_insn_coprocessor_1): Use arm_decode_field_multiple.
1654         (print_insn_mve): New function.
1655         (print_insn_thumb32): Handle MVE architecture.
1656         (select_arm_features): Force thumb for Armv8.1-m Mainline.
1657
1658 2019-05-10  Nick Clifton  <nickc@redhat.com>
1659
1660         PR 24538
1661         * ia64-opc.c (ia64_find_matching_opcode): Check for reaching the
1662         end of the table prematurely.
1663
1664 2019-05-10  Faraz Shahbazker  <fshahbazker@wavecomp.com>
1665
1666         * mips-opc.c (mips_opcodes): Enable ADD, SUB, DADD and DSUB
1667         macros for R6.
1668
1669 2019-05-11  Alan Modra  <amodra@gmail.com>
1670
1671         * ppc-dis.c (print_insn_powerpc) Don't skip optional operands
1672         when -Mraw is in effect.
1673
1674 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1675
1676         * aarch64-dis-2.c: Regenerate.
1677         * aarch64-tbl.h (OP_SVE_BBU): New variant set.
1678         (OP_SVE_BBB): New variant set.
1679         (OP_SVE_DDDD): New variant set.
1680         (OP_SVE_HHH): New variant set.
1681         (OP_SVE_HHHU): New variant set.
1682         (OP_SVE_SSS): New variant set.
1683         (OP_SVE_SSSU): New variant set.
1684         (OP_SVE_SHH): New variant set.
1685         (OP_SVE_SBBU): New variant set.
1686         (OP_SVE_DSS): New variant set.
1687         (OP_SVE_DHHU): New variant set.
1688         (OP_SVE_VMV_HSD_BHS): New variant set.
1689         (OP_SVE_VVU_HSD_BHS): New variant set.
1690         (OP_SVE_VVVU_SD_BH): New variant set.
1691         (OP_SVE_VVVU_BHSD): New variant set.
1692         (OP_SVE_VVV_QHD_DBS): New variant set.
1693         (OP_SVE_VVV_HSD_BHS): New variant set.
1694         (OP_SVE_VVV_HSD_BHS2): New variant set.
1695         (OP_SVE_VVV_BHS_HSD): New variant set.
1696         (OP_SVE_VV_BHS_HSD): New variant set.
1697         (OP_SVE_VVV_SD): New variant set.
1698         (OP_SVE_VVU_BHS_HSD): New variant set.
1699         (OP_SVE_VZVV_SD): New variant set.
1700         (OP_SVE_VZVV_BH): New variant set.
1701         (OP_SVE_VZV_SD): New variant set.
1702         (aarch64_opcode_table): Add sve2 instructions.
1703
1704 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1705
1706         * aarch64-asm-2.c: Regenerated.
1707         * aarch64-dis-2.c: Regenerated.
1708         * aarch64-opc-2.c: Regenerated.
1709         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1710         for SVE_SHLIMM_UNPRED_22.
1711         (aarch64_print_operand): Add printing for SVE_SHLIMM_UNPRED_22.
1712         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHLIMM_UNPRED_22
1713         operand.
1714
1715 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1716
1717         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1718         sve_size_tsz_bhs iclass encode.
1719         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1720         sve_size_tsz_bhs iclass decode.
1721
1722 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1723
1724         * aarch64-asm-2.c: Regenerated.
1725         * aarch64-dis-2.c: Regenerated.
1726         * aarch64-opc-2.c: Regenerated.
1727         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1728         for SVE_Zm4_11_INDEX.
1729         (aarch64_print_operand): Add printing for SVE_Zm4_11_INDEX.
1730         (fields): Handle SVE_i2h field.
1731         * aarch64-opc.h (enum aarch64_field_kind): New SVE_i2h field.
1732         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm4_11_INDEX operand.
1733
1734 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1735
1736         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1737         sve_shift_tsz_bhsd iclass encode.
1738         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1739         sve_shift_tsz_bhsd iclass decode.
1740
1741 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1742
1743         * aarch64-asm-2.c: Regenerated.
1744         * aarch64-dis-2.c: Regenerated.
1745         * aarch64-opc-2.c: Regenerated.
1746         * aarch64-asm.c (aarch64_ins_sve_shrimm):
1747         (aarch64_encode_variant_using_iclass): Handle
1748         sve_shift_tsz_hsd iclass encode.
1749         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1750         sve_shift_tsz_hsd iclass decode.
1751         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1752         for SVE_SHRIMM_UNPRED_22.
1753         (aarch64_print_operand): Add printing for SVE_SHRIMM_UNPRED_22.
1754         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHRIMM_UNPRED_22
1755         operand.
1756
1757 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1758
1759         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1760         sve_size_013 iclass encode.
1761         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1762         sve_size_013 iclass decode.
1763
1764 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1765
1766         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1767         sve_size_bh iclass encode.
1768         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1769         sve_size_bh iclass decode.
1770
1771 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1772
1773         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1774         sve_size_sd2 iclass encode.
1775         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1776         sve_size_sd2 iclass decode.
1777         * aarch64-opc.c (fields): Handle SVE_sz2 field.
1778         * aarch64-opc.h (enum aarch64_field_kind): New SVE_sz2 field.
1779
1780 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1781
1782         * aarch64-asm-2.c: Regenerated.
1783         * aarch64-dis-2.c: Regenerated.
1784         * aarch64-opc-2.c: Regenerated.
1785         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1786         for SVE_ADDR_ZX.
1787         (aarch64_print_operand): Add printing for SVE_ADDR_ZX.
1788         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_ADDR_ZX operand.
1789
1790 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1791
1792         * aarch64-asm-2.c: Regenerated.
1793         * aarch64-dis-2.c: Regenerated.
1794         * aarch64-opc-2.c: Regenerated.
1795         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1796         for SVE_Zm3_11_INDEX.
1797         (aarch64_print_operand): Add printing for SVE_Zm3_11_INDEX.
1798         (fields): Handle SVE_i3l and SVE_i3h2 fields.
1799         * aarch64-opc.h (enum aarch64_field_kind): New SVE_i3l and SVE_i3h2
1800         fields.
1801         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm3_11_INDEX operand.
1802
1803 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1804
1805         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1806         sve_size_hsd2 iclass encode.
1807         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1808         sve_size_hsd2 iclass decode.
1809         * aarch64-opc.c (fields): Handle SVE_size field.
1810         * aarch64-opc.h (enum aarch64_field_kind): New SVE_size field.
1811
1812 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1813
1814         * aarch64-asm-2.c: Regenerated.
1815         * aarch64-dis-2.c: Regenerated.
1816         * aarch64-opc-2.c: Regenerated.
1817         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1818         for SVE_IMM_ROT3.
1819         (aarch64_print_operand): Add printing for SVE_IMM_ROT3.
1820         (fields): Handle SVE_rot3 field.
1821         * aarch64-opc.h (enum aarch64_field_kind): New SVE_rot3 field.
1822         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_IMM_ROT3 operand.
1823
1824 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1825
1826         * aarch64-opc.c (verify_constraints): Check for movprfx for sve2
1827         instructions.
1828
1829 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1830
1831         * aarch64-tbl.h
1832         (aarch64_feature_sve2, aarch64_feature_sve2aes,
1833         aarch64_feature_sve2sha3, aarch64_feature_sve2sm4,
1834         aarch64_feature_sve2bitperm): New feature sets.
1835         (SVE2, SVE2_AES, SVE2_SHA3, SVE2_SM4, SVE2_BITPERM): New macros
1836         for feature set addresses.
1837         (SVE2_INSN, SVE2_INSNC, SVE2AES_INSN, SVE2SHA3_INSN,
1838         SVE2SM4_INSN, SVE2SM4_INSNC, SVE2BITPERM_INSN): New macros.
1839
1840 2019-05-06  Andrew Bennett  <andrew.bennett@imgtec.com>
1841             Faraz Shahbazker  <fshahbazker@wavecomp.com>
1842
1843         * mips-dis.c (mips_calculate_combination_ases): Add ISA
1844         argument and set ASE_EVA_R6 appropriately.
1845         (set_default_mips_dis_options): Pass ISA to above.
1846         (parse_mips_dis_option): Likewise.
1847         * mips-opc.c (EVAR6): New macro.
1848         (mips_builtin_opcodes): Add llwpe, scwpe.
1849
1850 2019-05-01  Sudakshina Das  <sudi.das@arm.com>
1851
1852         * aarch64-asm-2.c: Regenerated.
1853         * aarch64-dis-2.c: Regenerated.
1854         * aarch64-opc-2.c: Regenerated.
1855         * aarch64-opc.c (operand_general_constraint_met_p): Add case for
1856         AARCH64_OPND_TME_UIMM16.
1857         (aarch64_print_operand): Likewise.
1858         * aarch64-tbl.h (QL_IMM_NIL): New.
1859         (TME): New.
1860         (_TME_INSN): New.
1861         (struct aarch64_opcode): Add tstart, tcommit, ttest and tcancel.
1862
1863 2019-04-29  John Darrington  <john@darrington.wattle.id.au>
1864
1865         * s12z-opc.c (shift_discrim): Return OP_INVALID when reading fails.
1866
1867 2019-04-26  Andrew Bennett  <andrew.bennett@imgtec.com>
1868             Faraz Shahbazker  <fshahbazker@wavecomp.com>
1869
1870         * mips-opc.c (mips_builtin_opcodes): Add llwp, lldp, scwp, scdp.
1871
1872 2019-04-24  John Darrington  <john@darrington.wattle.id.au>
1873
1874         * s12z-opc.h: Add extern "C" bracketing to help
1875         users who wish to use this interface in c++ code.
1876
1877 2019-04-24  John Darrington  <john@darrington.wattle.id.au>
1878
1879         * s12z-opc.c (bm_decode): Handle bit map operations with the
1880         "reserved0" mode.
1881
1882 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1883
1884         * arm-dis.c (coprocessor_opcodes): Document new %J and %K format
1885         specifier.  Add entries for VLDR and VSTR of system registers.
1886         (print_insn_coprocessor): Forbid coprocessor numbers 8, 14 and 15 in
1887         coprocessor instructions on Armv8.1-M Mainline targets.  Add handling
1888         of %J and %K format specifier.
1889
1890 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1891
1892         * arm-dis.c (coprocessor_opcodes): Document new %C format control code.
1893         Add new entries for VSCCLRM instruction.
1894         (print_insn_coprocessor): Handle new %C format control code.
1895
1896 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1897
1898         * arm-dis.c (enum isa): New enum.
1899         (struct sopcode32): New structure.
1900         (coprocessor_opcodes): change type of entries to struct sopcode32 and
1901         set isa field of all current entries to ANY.
1902         (print_insn_coprocessor): Change type of insn to struct sopcode32.
1903         Only match an entry if its isa field allows the current mode.
1904
1905 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1906
1907         * arm-dis.c (thumb_opcodes): Document %n control code.  Add entry for
1908         CLRM.
1909         (print_insn_thumb32): Add logic to print %n CLRM register list.
1910
1911 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1912
1913         * arm-dis.c (print_insn_thumb32): Updated to accept new %P
1914         and %Q patterns.
1915
1916 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1917
1918         * arm-dis.c (thumb32_opcodes): New instruction bfcsel.
1919         (print_insn_thumb32): Edit the switch case for %Z.
1920
1921 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1922
1923         * arm-dis.c (print_insn_thumb32): Updated to accept new %Z pattern.
1924
1925 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1926
1927         * arm-dis.c (thumb32_opcodes): New instruction bfl.
1928
1929 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1930
1931         * arm-dis.c (print_insn_thumb32): Updated to accept new %Y pattern.
1932
1933 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1934
1935         * arm-dis.c (print_insn_thumb32): Add '%<bitfield>S' to print an
1936         Arm register with r13 and r15 unpredictable.
1937         (thumb32_opcodes): New instructions for bfx and bflx.
1938
1939 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1940
1941         * arm-dis.c (thumb32_opcodes): New instructions for bf.
1942
1943 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1944
1945         * arm-dis.c (print_insn_thumb32): Updated to accept new %W pattern.
1946
1947 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1948
1949         * arm-dis.c (print_insn_thumb32): Updated to accept new %G pattern.
1950
1951 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1952
1953         * arm-dis.c (select_arm_features): Add logic for Armv8.1-M Mainline.
1954
1955 2019-04-12  John Darrington <john@darrington.wattle.id.au>
1956
1957         s12z-dis.c, s12z-opc.c, s12z-opc.h: Replace "operator" with
1958         "optr". ("operator" is a reserved word in c++).
1959
1960 2019-04-11  Sudakshina Das  <sudi.das@arm.com>
1961
1962         * aarch64-opc.c (aarch64_print_operand): Add case for
1963         AARCH64_OPND_Rt_SP.
1964         (verify_constraints): Likewise.
1965         * aarch64-tbl.h (QL_LDST_AT): Update to add SP qualifier.
1966         (struct aarch64_opcode): Update stg, stzg, st2g, stz2g instructions
1967         to accept Rt|SP as first operand.
1968         (AARCH64_OPERANDS): Add new Rt_SP.
1969         * aarch64-asm-2.c: Regenerated.
1970         * aarch64-dis-2.c: Regenerated.
1971         * aarch64-opc-2.c: Regenerated.
1972
1973 2019-04-11  Sudakshina Das  <sudi.das@arm.com>
1974
1975         * aarch64-asm-2.c: Regenerated.
1976         * aarch64-dis-2.c: Likewise.
1977         * aarch64-opc-2.c: Likewise.
1978         * aarch64-tbl.h (aarch64_opcode): Add new ldgm and stgm.
1979
1980 2019-04-09  Robert Suchanek  <robert.suchanek@mips.com>
1981
1982         * mips-opc.c (mips_builtin_opcodes): Add RDHWR rt rd sel.
1983
1984 2019-04-08  H.J. Lu  <hongjiu.lu@intel.com>
1985
1986         * i386-opc.tbl: Consolidate AVX512 BF16 entries.
1987         * i386-init.h: Regenerated.
1988
1989 2019-04-07  Alan Modra  <amodra@gmail.com>
1990
1991         * ppc-dis.c (print_insn_powerpc): Use a tiny state machine
1992         op_separator to control printing of spaces, comma and parens
1993         rather than need_comma, need_paren and spaces vars.
1994
1995 2019-04-07  Alan Modra  <amodra@gmail.com>
1996
1997         PR 24421
1998         * arm-dis.c (print_insn_coprocessor): Correct bracket placement.
1999         (print_insn_neon, print_insn_arm): Likewise.
2000
2001 2019-04-05  Xuepeng Guo  <xuepeng.guo@intel.com>
2002
2003         * i386-dis-evex.h (evex_table): Updated to support BF16
2004         instructions.
2005         * i386-dis.c (enum): Add EVEX_W_0F3852_P_1, EVEX_W_0F3872_P_1
2006         and EVEX_W_0F3872_P_3.
2007         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_BF16_FLAGS.
2008         (cpu_flags): Add bitfield for CpuAVX512_BF16.
2009         * i386-opc.h (enum): Add CpuAVX512_BF16.
2010         (i386_cpu_flags): Add bitfield for cpuavx512_bf16.
2011         * i386-opc.tbl: Add AVX512 BF16 instructions.
2012         * i386-init.h: Regenerated.
2013         * i386-tbl.h: Likewise.
2014
2015 2019-04-05  Alan Modra  <amodra@gmail.com>
2016
2017         * ppc-opc.c (XLBH_MASK): Subtract off BH field from BB_MASK.
2018         (powerpc_opcodes): Reorder bcctr and bclr extended mnemonics
2019         to favour printing of "-" branch hint when using the "y" bit.
2020         Allow BH field on bc{ctr,lr,tar}{,l}{-,+}.
2021
2022 2019-04-05  Alan Modra  <amodra@gmail.com>
2023
2024         * ppc-dis.c (print_insn_powerpc): Delay printing spaces after
2025         opcode until first operand is output.
2026
2027 2019-04-04  Peter Bergner  <bergner@linux.ibm.com>
2028
2029         PR gas/24349
2030         * ppc-opc.c (valid_bo_pre_v2): Add comments.
2031         (valid_bo_post_v2): Add support for 'at' branch hints.
2032         (insert_bo): Only error on branch on ctr.
2033         (get_bo_hint_mask): New function.
2034         (insert_boe): Add new 'branch_taken' formal argument.  Add support
2035         for inserting 'at' branch hints.
2036         (extract_boe): Add new 'branch_taken' formal argument.  Add support
2037         for extracting 'at' branch hints.
2038         (insert_bom, extract_bom, insert_bop, extract_bop): New functions.
2039         (BOE): Delete operand.
2040         (BOM, BOP): New operands.
2041         (RM): Update value.
2042         (XLYLK, XLYLK_MASK, XLYBB_MASK): Delete.
2043         (powerpc_opcodes) <bc-, bcl-, bca-, bcla-, bclr-, bclrl-, bcctr-,
2044         bcctrl-, bctar-, bctarl->: Replace BOE with BOM.
2045         (powerpc_opcodes) <bc+, bcl+, bca+, bcla+, bclr+, bclrl+, bcctr+,
2046         bcctrl+, bctar+, bctarl+>: Replace BOE with BOP.
2047         <bdnztar, bdnztarl, bdztar, bdztarl, btar, btarl, bdnztar-, bdnztarl-,
2048         bdnztar+, bdnztarl+, bdztar-, bdztarl-, bdztar+, bdztarl+, bgetar,
2049         bnltar, bgetarl, bnltarl, bletar, bngtar, bletarl, bngtarl, bnetar,
2050         bnetarl, bnstar, bnutar, bnstarl, bnutarl, bgetar-, bnltar-, bgetarl-,
2051         bnltarl-, bletar-, bngtar-, bletarl-, bngtarl-, bnetar-, bnetarl-,
2052         bnstar-, bnutar-, bnstarl-, bnutarl-, bgetar+, bnltar+, bgetarl+,
2053         bnltarl+, bletar+, bngtar+, bletarl+, bngtarl+, bnetar+, bnetarl+,
2054         bnstar+, bnutar+, bnstarl+, bnutarl+, blttar, blttarl, bgttar, bgttarl,
2055         beqtar, beqtarl, bsotar, buntar, bsotarl, buntarl, blttar-, blttarl-,
2056         bgttar-, bgttarl-, beqtar-, beqtarl-, bsotar-, buntar-, bsotarl-,
2057         buntarl-, blttar+, blttarl+, bgttar+, bgttarl+, beqtar+, beqtarl+,
2058         bsotar+, buntar+, bsotarl+, buntarl+, bdnzftar, bdnzftarl, bdzftar,
2059         bdzftarl, bftar, bftarl, bftar-, bftarl-, bftar+, bftarl+, bdnzttar,
2060         bdnzttarl, bdzttar, bdzttarl, bttar, bttarl, bttar-, bttarl-, bttar+,
2061         bttarl+>: New extended mnemonics.
2062
2063 2019-03-28  Alan Modra  <amodra@gmail.com>
2064
2065         PR 24390
2066         * ppc-opc.c (BTF): Define.
2067         (powerpc_opcodes): Use for mtfsb*.
2068         * ppc-dis.c (print_insn_powerpc): Print fields with both
2069         PPC_OPERAND_CR_REG and PPC_OPERAND_CR_BIT as a plain number.
2070
2071 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
2072
2073         * arm-dis.c (struct arm_private_data): Remove has_mapping_symbols.
2074         (mapping_symbol_for_insn): Implement new algorithm.
2075         (print_insn): Remove duplicate code.
2076
2077 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
2078
2079         * aarch64-dis.c (print_insn_aarch64):
2080         Implement override.
2081
2082 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
2083
2084         * aarch64-dis.c (print_insn_aarch64): Update the mapping symbol search
2085         order.
2086
2087 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
2088
2089         * aarch64-dis.c (last_stop_offset): New.
2090         (print_insn_aarch64): Use stop_offset.
2091
2092 2019-03-19  H.J. Lu  <hongjiu.lu@intel.com>
2093
2094         PR gas/24359
2095         * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS to
2096         CPU_ANY_AVX2_FLAGS.
2097         * i386-init.h: Regenerated.
2098
2099 2019-03-18  H.J. Lu  <hongjiu.lu@intel.com>
2100
2101         PR gas/24348
2102         * i386-opc.tbl: Add Optimize to vmovdqa32, vmovdqa64, vmovdqu8,
2103         vmovdqu16, vmovdqu32 and vmovdqu64.
2104         * i386-tbl.h: Regenerated.
2105
2106 2019-03-12  Andreas Krebbel  <krebbel@linux.ibm.com>
2107
2108         * s390-opc.txt: Rename selhhhr to selfhr.  Remove optional operand
2109         from vstrszb, vstrszh, and vstrszf.
2110
2111 2019-03-12  Andreas Krebbel  <krebbel@linux.ibm.com>
2112
2113         * s390-opc.txt: Add instruction descriptions.
2114
2115 2019-02-08  Jim Wilson  <jimw@sifive.com>
2116
2117         * riscv-opc.c (riscv_opcodes) <beq>: Use Cz to compress 3 operand form.
2118         <bne>: Likewise.
2119
2120 2019-02-07  Tamar Christina  <tamar.christina@arm.com>
2121
2122         * arm-dis.c (arm_opcodes): Redefine hlt to armv1.
2123
2124 2019-02-07  Tamar Christina  <tamar.christina@arm.com>
2125
2126         PR binutils/23212
2127         * aarch64-opc.h (enum aarch64_field_kind): Add FLD_sz.
2128         * aarch64-opc.c (verify_elem_sd): New.
2129         (fields): Add FLD_sz entr.
2130         * aarch64-tbl.h (_SIMD_INSN): New.
2131         (aarch64_opcode_table): Add elem_sd verifier to fmla, fmls, fmul and
2132         fmulx scalar and vector by element isns.
2133
2134 2019-02-07  Nick Clifton  <nickc@redhat.com>
2135
2136         * po/sv.po: Updated Swedish translation.
2137
2138 2019-01-31  Andreas Krebbel  <krebbel@linux.ibm.com>
2139
2140         * s390-mkopc.c (main): Accept arch13 as cpu string.
2141         * s390-opc.c: Add new instruction formats and instruction opcode
2142         masks.
2143         * s390-opc.txt: Add new arch13 instructions.
2144
2145 2019-01-25  Sudakshina Das  <sudi.das@arm.com>
2146
2147         * aarch64-tbl.h (QL_LDST_AT): Update macro.
2148         (aarch64_opcode): Change encoding for stg, stzg
2149         st2g and st2zg.
2150         * aarch64-asm-2.c: Regenerated.
2151         * aarch64-dis-2.c: Regenerated.
2152         * aarch64-opc-2.c: Regenerated.
2153
2154 2019-01-25  Sudakshina Das  <sudi.das@arm.com>
2155
2156         * aarch64-asm-2.c: Regenerated.
2157         * aarch64-dis-2.c: Likewise.
2158         * aarch64-opc-2.c: Likewise.
2159         * aarch64-tbl.h (aarch64_opcode): Add new stzgm.
2160
2161 2019-01-25  Sudakshina Das  <sudi.das@arm.com>
2162             Ramana Radhakrishnan  <ramana.radhakrishnan@arm.com>
2163
2164         * aarch64-asm.c (aarch64_ins_addr_simple_2): Remove.
2165         * aarch64-asm.h (ins_addr_simple_2): Likeiwse.
2166         * aarch64-dis.c (aarch64_ext_addr_simple_2): Likewise.
2167         * aarch64-dis.h (ext_addr_simple_2): Likewise.
2168         * aarch64-opc.c (operand_general_constraint_met_p): Remove
2169         case for ldstgv_indexed.
2170         (aarch64_print_operand): Remove case for AARCH64_OPND_ADDR_SIMPLE_2.
2171         * aarch64-tbl.h (struct aarch64_opcode): Remove ldgv and stgv.
2172         (AARCH64_OPERANDS): Remove ADDR_SIMPLE_2.
2173         * aarch64-asm-2.c: Regenerated.
2174         * aarch64-dis-2.c: Regenerated.
2175         * aarch64-opc-2.c: Regenerated.
2176
2177 2019-01-23  Nick Clifton  <nickc@redhat.com>
2178
2179         * po/pt_BR.po: Updated Brazilian Portuguese translation.
2180
2181 2019-01-21  Nick Clifton  <nickc@redhat.com>
2182
2183         * po/de.po: Updated German translation.
2184         * po/uk.po: Updated Ukranian translation.
2185
2186 2019-01-20  Chenghua Xu  <paul.hua.gm@gmail.com>
2187         * mips-dis.c (mips_arch_choices): Fix typo in
2188         gs464, gs464e and gs264e descriptors.
2189
2190 2019-01-19  Nick Clifton  <nickc@redhat.com>
2191
2192         * configure: Regenerate.
2193         * po/opcodes.pot: Regenerate.
2194
2195 2018-06-24  Nick Clifton  <nickc@redhat.com>
2196
2197         2.32 branch created.
2198
2199 2019-01-09  John Darrington <john@darrington.wattle.id.au>
2200
2201         * s12z-dis.c (print_insn_s12z):  Do not dereference an operand
2202         if it is null.
2203         -dis.c (opr_emit_disassembly): Do not omit an index if it is
2204         zero.
2205
2206 2019-01-09  Andrew Paprocki  <andrew@ishiboo.com>
2207
2208         * configure: Regenerate.
2209
2210 2019-01-07  Alan Modra  <amodra@gmail.com>
2211
2212         * configure: Regenerate.
2213         * po/POTFILES.in: Regenerate.
2214
2215 2019-01-03  John Darrington <john@darrington.wattle.id.au>
2216
2217         * s12z-opc.c: New file.
2218         * s12z-opc.h: New file.
2219         * s12z-dis.c: Removed all code not directly related to display
2220         of instructions.  Used the interface provided by the new files
2221         instead.
2222         * Makefile.am (TARGET_LIBOPCODES_CFILES) Add s12z-opc.c.
2223         * Makefile.in: Regenerate.
2224         * configure.ac (bfd_s12z_arch): Correct the dependencies.
2225         * configure: Regenerate.
2226
2227 2019-01-01  Alan Modra  <amodra@gmail.com>
2228
2229         Update year range in copyright notice of all files.
2230
2231 For older changes see ChangeLog-2018
2232 \f
2233 Copyright (C) 2019 Free Software Foundation, Inc.
2234
2235 Copying and distribution of this file, with or without modification,
2236 are permitted in any medium without royalty provided the copyright
2237 notice and this notice are preserved.
2238
2239 Local Variables:
2240 mode: change-log
2241 left-margin: 8
2242 fill-column: 74
2243 version-control: never
2244 End: