opcodes/ChangeLog

   1 2020-07-06  Jan Beulich  <jbeulich@suse.com>
   2
   3         * i386-dis.c (EVEX_LEN_0F3816_P_2, EVEX_LEN_0F3836_P_2,
   4         EVEX_LEN_0F3A00_P_2_W_1, EVEX_LEN_0F3A01_P_2_W_1): New
   5         enumerators.
   6         * i386-dis-evex-len.h (evex_len_table): New EVEX_LEN_0F3816_P_2,
   7         EVEX_LEN_0F3836_P_2, EVEX_LEN_0F3A00_P_2_W_1, and
   8         EVEX_LEN_0F3A01_P_2_W_1 table entries.
   9         * i386-dis-evex-prefix.h, i386-dis-evex-w.h: Reference the above
  10         entries.
  11
  12 2020-07-06  Jan Beulich  <jbeulich@suse.com>
  13
  14         * i386-dis.c (EVEX_LEN_0FC4_P_2, EVEX_LEN_0FC5_P_2,
  15         EVEX_LEN_0F3A14_P_2, EVEX_LEN_0F3A15_P_2, EVEX_LEN_0F3A16_P_2,
  16         EVEX_LEN_0F3A17_P_2, EVEX_LEN_0F3A20_P_2,
  17         EVEX_LEN_0F3A21_P_2_W_0, EVEX_LEN_0F3A22_P_2): New enumerators.
  18         * i386-dis-evex-len.h (evex_len_table): New EVEX_LEN_0FC4_P_2,
  19         EVEX_LEN_0FC5_P_2, EVEX_LEN_0F3A14_P_2, EVEX_LEN_0F3A15_P_2,
  20         EVEX_LEN_0F3A16_P_2, EVEX_LEN_0F3A17_P_2, EVEX_LEN_0F3A20_P_2,
  21         EVEX_LEN_0F3A21_P_2_W_0, and EVEX_LEN_0F3A22_P_2 table entries.
  22         * i386-dis-evex-prefix.h, i386-dis-evex-w.h: Reference the above
  23         entries.
  24
  25 2020-07-06  Jan Beulich  <jbeulich@suse.com>
  26
  27         * i386-dis.c (PREFIX_EVEX_0F3A1D, EVEX_W_0F3A1D_P_2): Delete.
  28         (VEX_W_0F3813_P_2, VEX_W_0F3A1D_P_2): New enumerators.
  29         (prefix_table): Reference VEX_W_0F3813_P_2 and VEX_W_0F3A1D_P_2
  30         respectively.
  31         (vex_w_table): New VEX_W_0F3813_P_2 and VEX_W_0F3A1D_P_2 table
  32         entries.
  33         * i386-dis-evex.h (evex_table): Reference VEX table entry for
  34         opcode 0F3A1D.
  35         * i386-dis-evex-prefix.h (PREFIX_EVEX_0F3A1D): Delete table
  36         entry.
  37         * i386-dis-evex-w.h (EVEX_W_0F3A1D_P_2): Likewise.
  38
  39 2020-07-06  Jan Beulich  <jbeulich@suse.com>
  40
  41         * i386-dis.c (PREFIX_EVEX_0F60, PREFIX_EVEX_0F61,
  42         PREFIX_EVEX_0F63, PREFIX_EVEX_0F67, PREFIX_EVEX_0F68,
  43         PREFIX_EVEX_0F69, PREFIX_EVEX_0FD1, PREFIX_EVEX_0FD5,
  44         PREFIX_EVEX_0FD8, PREFIX_EVEX_0FD9, PREFIX_EVEX_0FDA,
  45         PREFIX_EVEX_0FDC, PREFIX_EVEX_0FDD, PREFIX_EVEX_0FDE,
  46         PREFIX_EVEX_0FE0, PREFIX_EVEX_0FE1, PREFIX_EVEX_0FE3,
  47         PREFIX_EVEX_0FE4, PREFIX_EVEX_0FE5, PREFIX_EVEX_0FE8,
  48         PREFIX_EVEX_0FE9, PREFIX_EVEX_0FEA, PREFIX_EVEX_0FEC,
  49         PREFIX_EVEX_0FED, PREFIX_EVEX_0FEE, PREFIX_EVEX_0FF1,
  50         PREFIX_EVEX_0FF5, PREFIX_EVEX_0FF6, PREFIX_EVEX_0FF8,
  51         PREFIX_EVEX_0FF9, PREFIX_EVEX_0FFC, PREFIX_EVEX_0FFD,
  52         PREFIX_EVEX_0F3800, PREFIX_EVEX_0F3804, PREFIX_EVEX_0F380B,
  53         PREFIX_EVEX_0F380C, PREFIX_EVEX_0F3818, PREFIX_EVEX_0F381C,
  54         PREFIX_EVEX_0F381D, PREFIX_EVEX_0F383C, PREFIX_EVEX_0F383E,
  55         PREFIX_EVEX_0F3858, PREFIX_EVEX_0F3878, PREFIX_EVEX_0F3879,
  56         PREFIX_EVEX_0F3896, PREFIX_EVEX_0F3897, PREFIX_EVEX_0F3898,
  57         PREFIX_EVEX_0F3899, PREFIX_EVEX_0F389C, PREFIX_EVEX_0F389D,
  58         PREFIX_EVEX_0F389E, PREFIX_EVEX_0F389F, PREFIX_EVEX_0F38A6,
  59         PREFIX_EVEX_0F38A7, PREFIX_EVEX_0F38A8, PREFIX_EVEX_0F38A9,
  60         PREFIX_EVEX_0F38AC, PREFIX_EVEX_0F38AD, PREFIX_EVEX_0F38AE,
  61         PREFIX_EVEX_0F38AF, PREFIX_EVEX_0F38B6, PREFIX_EVEX_0F38B7,
  62         PREFIX_EVEX_0F38B8, PREFIX_EVEX_0F38B9, PREFIX_EVEX_0F38BA,
  63         PREFIX_EVEX_0F38BB, PREFIX_EVEX_0F38BC, PREFIX_EVEX_0F38BD,
  64         PREFIX_EVEX_0F38BE, PREFIX_EVEX_0F38BF, PREFIX_EVEX_0F38CF,
  65         PREFIX_EVEX_0F38DC, PREFIX_EVEX_0F38DD, PREFIX_EVEX_0F38DE,
  66         PREFIX_EVEX_0F38DF, PREFIX_EVEX_0F3A04, PREFIX_EVEX_0F3A0F,
  67         PREFIX_EVEX_0F3A44, PREFIX_EVEX_0F3ACE, PREFIX_EVEX_0F3ACF,
  68         EVEX_W_0F380C_P_2, EVEX_W_0F3818_P_2, EVEX_W_0F3858_P_2,
  69         EVEX_W_0F3878_P_2, EVEX_W_0F3879_P_2, EVEX_W_0F3A04_P_2,
  70         EVEX_W_0F3ACE_P_2, EVEX_W_0F3ACF_P_2): Delete.
  71         (prefix_table): Add EXxEVexR to FMA table entries.
  72         (OP_Rounding): Move abort() invocation.
  73         * i386-dis-evex.h (evex_table): Reference VEX table for opcodes
  74         0F60, 0F61, 0F63, 0F67, 0F68, 0F69, 0FD1, 0FD5, 0FD8, 0FD9,
  75         0FDA, 0FDC, 0FDD, 0FDE, 0FE0, 0FE1, 0FE3, 0FE4, 0FE5, 0FE8,
  76         0FE9, 0FEA, 0FEC, 0FED, 0FEE, 0FF1, 0FF5, 0FF6, 0FF8, 0FF9,
  77         0FFC, 0FFD, 0F3800, 0F3804, 0F380B, 0F380C, 0F3818, 0F381C,
  78         0F381D, 0F383C, 0F383E, 0F3858, 0F3878, 0F3879, 0F3896, 0F3897,
  79         0F3898, 0F3899, 0F389C, 0F389D, 0F389E, 0F389F, 0F38A6, 0F38A7,
  80         0F38A8, 0F38A9, 0F38AC, 0F38AD, 0F38AE, 0F38AF, 0F38B6, 0F38B7,
  81         0F38B8, 0F38B9, 0F38BA, 0F38BB, 0F38BC, 0F38BD, 0F38BE, 0F38BF,
  82         0F38CF, 0F38DC, 0F38DD, 0F38DE, 0F38DF, 0F3A04, 0F3A0F, 0F3A44,
  83         0F3ACE, 0F3ACF.
  84         * i386-dis-evex-prefix.h (PREFIX_EVEX_0F60, PREFIX_EVEX_0F61,
  85         PREFIX_EVEX_0F63, PREFIX_EVEX_0F67, PREFIX_EVEX_0F68,
  86         PREFIX_EVEX_0F69, PREFIX_EVEX_0FD1, PREFIX_EVEX_0FD5,
  87         PREFIX_EVEX_0FD8, PREFIX_EVEX_0FD9, PREFIX_EVEX_0FDA,
  88         PREFIX_EVEX_0FDC, PREFIX_EVEX_0FDD, PREFIX_EVEX_0FDE,
  89         PREFIX_EVEX_0FE0, PREFIX_EVEX_0FE1, PREFIX_EVEX_0FE3,
  90         PREFIX_EVEX_0FE4, PREFIX_EVEX_0FE5, PREFIX_EVEX_0FE8,
  91         PREFIX_EVEX_0FE9, PREFIX_EVEX_0FEA, PREFIX_EVEX_0FEC,
  92         PREFIX_EVEX_0FED, PREFIX_EVEX_0FEE, PREFIX_EVEX_0FF1,
  93         PREFIX_EVEX_0FF5, PREFIX_EVEX_0FF6, PREFIX_EVEX_0FF8,
  94         PREFIX_EVEX_0FF9, PREFIX_EVEX_0FFC, PREFIX_EVEX_0FFD,
  95         PREFIX_EVEX_0F3800, PREFIX_EVEX_0F3804, PREFIX_EVEX_0F380B,
  96         PREFIX_EVEX_0F380C, PREFIX_EVEX_0F3818, PREFIX_EVEX_0F381C,
  97         PREFIX_EVEX_0F381D, PREFIX_EVEX_0F383C, PREFIX_EVEX_0F383E,
  98         PREFIX_EVEX_0F3858, PREFIX_EVEX_0F3878, PREFIX_EVEX_0F3879,
  99         PREFIX_EVEX_0F3896, PREFIX_EVEX_0F3897, PREFIX_EVEX_0F3898,
 100         PREFIX_EVEX_0F3899, PREFIX_EVEX_0F389C, PREFIX_EVEX_0F389D,
 101         PREFIX_EVEX_0F389E, PREFIX_EVEX_0F389F, PREFIX_EVEX_0F38A6,
 102         PREFIX_EVEX_0F38A7, PREFIX_EVEX_0F38A8, PREFIX_EVEX_0F38A9,
 103         PREFIX_EVEX_0F38AC, PREFIX_EVEX_0F38AD, PREFIX_EVEX_0F38AE,
 104         PREFIX_EVEX_0F38AF, PREFIX_EVEX_0F38B6, PREFIX_EVEX_0F38B7,
 105         PREFIX_EVEX_0F38B8, PREFIX_EVEX_0F38B9, PREFIX_EVEX_0F38BA,
 106         PREFIX_EVEX_0F38BB, PREFIX_EVEX_0F38BC, PREFIX_EVEX_0F38BD,
 107         PREFIX_EVEX_0F38BE, PREFIX_EVEX_0F38BF, PREFIX_EVEX_0F38CF,
 108         PREFIX_EVEX_0F38DC, PREFIX_EVEX_0F38DD, PREFIX_EVEX_0F38DE,
 109         PREFIX_EVEX_0F38DF, PREFIX_EVEX_0F3A04, PREFIX_EVEX_0F3A0F,
 110         PREFIX_EVEX_0F3A44, PREFIX_EVEX_0F3ACE, PREFIX_EVEX_0F3ACF):
 111         Delete table entries.
 112         * i386-dis-evex-w.h (EVEX_W_0F380C_P_2, EVEX_W_0F3818_P_2,
 113         EVEX_W_0F3858_P_2, EVEX_W_0F3878_P_2, EVEX_W_0F3879_P_2,
 114         EVEX_W_0F3A04_P_2, EVEX_W_0F3ACE_P_2, EVEX_W_0F3ACF_P_2):
 115         Likewise.
 116
 117 2020-07-06  Jan Beulich  <jbeulich@suse.com>
 118
 119         * i386-dis.c (EXqScalarS): Delete.
 120         (vex_len_table): Replace EXqScalarS by EXqVexScalarS.
 121         * i386-dis-evex-w.h (vmovq): Use EXqVexScalarS.
 122
 123 2020-07-06  Jan Beulich  <jbeulich@suse.com>
 124
 125         * i386-dis.c (safe-ctype.h): Include.
 126         (EXdScalar, EXqScalar): Delete.
 127         (d_scalar_mode, q_scalar_mode): Delete.
 128         (prefix_table, vex_len_table): Use EXxmm_md in place of
 129         EXdScalar and EXxmm_mq in place of EXqScalar.
 130         (intel_operand_size, OP_E_memory, OP_EX): Remove uses of
 131         d_scalar_mode and q_scalar_mode.
 132         * i386-dis-evex-w.h (vmovss): Use EXxmm_md.
 133         (vmovsd): Use EXxmm_mq.
 134
 135 2020-07-06  Yuri Chornoivan  <yurchor@ukr.net>
 136
 137         PR 26204
 138         * arc-dis.c: Fix spelling mistake.
 139         * po/opcodes.pot: Regenerate.
 140
 141 2020-07-06  Nick Clifton  <nickc@redhat.com>
 142
 143         * po/pt_BR.po: Updated Brazilian Portugugese translation.
 144         * po/uk.po: Updated Ukranian translation.
 145
 146 2020-07-04  Nick Clifton  <nickc@redhat.com>
 147
 148         * configure: Regenerate.
 149         * po/opcodes.pot: Regenerate.
 150
 151 2020-07-04  Nick Clifton  <nickc@redhat.com>
 152
 153         Binutils 2.35 branch created.
 154
 155 2020-07-02  H.J. Lu  <hongjiu.lu@intel.com>
 156
 157         * i386-gen.c (opcode_modifiers): Add VexSwapSources.
 158         * i386-opc.h (VexSwapSources): New.
 159         (i386_opcode_modifier): Add vexswapsources.
 160         * i386-opc.tbl: Add VexSwapSources to BMI2 and BMI instructions
 161         with two source operands swapped.
 162         * i386-tbl.h: Regenerated.
 163
 164 2020-06-30  Nelson Chu  <nelson.chu@sifive.com>
 165
 166         * riscv-dis.c (print_insn_args, case 'E'): Updated.  Let the
 167         unprivileged CSR can also be initialized.
 168
 169 2020-06-29  Alan Modra  <amodra@gmail.com>
 170
 171         * arm-dis.c: Use C style comments.
 172         * cr16-opc.c: Likewise.
 173         * ft32-dis.c: Likewise.
 174         * moxie-opc.c: Likewise.
 175         * tic54x-dis.c: Likewise.
 176         * s12z-opc.c: Remove useless comment.
 177         * xgate-dis.c: Likewise.
 178
 179 2020-06-26  H.J. Lu  <hongjiu.lu@intel.com>
 180
 181         * i386-opc.tbl: Add a blank line.
 182
 183 2020-06-26  H.J. Lu  <hongjiu.lu@intel.com>
 184
 185         * i386-gen.c (opcode_modifiers): Replace VecSIB with SIB.
 186         (VecSIB128): Renamed to ...
 187         (VECSIB128): This.
 188         (VecSIB256): Renamed to ...
 189         (VECSIB256): This.
 190         (VecSIB512): Renamed to ...
 191         (VECSIB512): This.
 192         (VecSIB): Renamed to ...
 193         (SIB): This.
 194         (i386_opcode_modifier): Replace vecsib with sib.
 195         * i386-opc.tbl (VecSIB128): New.
 196         (VecSIB256): Likewise.
 197         (VecSIB512): Likewise.
 198         Replace VecSIB=1, VecSIB=2 and VecSIB=3 with VecSIB128, VecSIB256
 199         and VecSIB512, respectively.
 200
 201 2020-06-26  Jan Beulich  <jbeulich@suse.com>
 202
 203         * i386-dis.c: Adjust description of I macro.
 204         (x86_64_table): Drop use of I.
 205         (float_mem): Replace use of I.
 206         (putop): Remove handling of I. Adjust setting/clearing of "alt".
 207
 208 2020-06-26  Jan Beulich  <jbeulich@suse.com>
 209
 210         * i386-dis.c: (print_insn): Avoid straight assignment to
 211         priv.orig_sizeflag when processing -M sub-options.
 212
 213 2020-06-25  Jan Beulich  <jbeulich@suse.com>
 214
 215         * i386-dis.c: Adjust description of J macro.
 216         (dis386, x86_64_table, mod_table): Replace J.
 217         (putop): Remove handling of J.
 218
 219 2020-06-25  Jan Beulich  <jbeulich@suse.com>
 220
 221         * i386-dis.c: (float_mem): Reduce alternatives for fstpt and fldpt.
 222
 223 2020-06-25  Jan Beulich  <jbeulich@suse.com>
 224
 225         * i386-dis.c: Adjust description of "LQ" macro.
 226         (dis386_twobyte): Use LQ for sysret.
 227         (putop): Adjust handling of LQ.
 228
 229 2020-06-22  Nelson Chu  <nelson.chu@sifive.com>
 230
 231         * riscv-opc.c: Move the structures and functions to bfd/elfxx-riscv.c.
 232         * riscv-dis.c: Include elfxx-riscv.h.
 233
 234 2020-06-18  H.J. Lu  <hongjiu.lu@intel.com>
 235
 236         * i386-dis.c (prefix_table): Revert the last vmgexit change.
 237
 238 2020-06-17  Lili Cui  <lili.cui@intel.com>
 239
 240         * i386-dis.c (prefix_table): Delete the incorrect vmgexit.
 241
 242 2020-06-14  H.J. Lu  <hongjiu.lu@intel.com>
 243
 244         PR gas/26115
 245         * i386-dis.c (prefix_table): Replace xsuspldtrk with xsusldtrk.
 246         * i386-opc.tbl: Likewise.
 247         * i386-tbl.h: Regenerated.
 248
 249 2020-06-12  Nelson Chu  <nelson.chu@sifive.com>
 250
 251         * riscv-opc.c (priv_specs): Remove v1.9 and PRIV_SPEC_CLASS_1P9.
 252
 253 2020-06-11  Alex Coplan  <alex.coplan@arm.com>
 254
 255         * aarch64-opc.c (SYSREG): New macro for describing system registers.
 256         (SR_CORE): Likewise.
 257         (SR_FEAT): Likewise.
 258         (SR_RNG): Likewise.
 259         (SR_V8_1): Likewise.
 260         (SR_V8_2): Likewise.
 261         (SR_V8_3): Likewise.
 262         (SR_V8_4): Likewise.
 263         (SR_PAN): Likewise.
 264         (SR_RAS): Likewise.
 265         (SR_SSBS): Likewise.
 266         (SR_SVE): Likewise.
 267         (SR_ID_PFR2): Likewise.
 268         (SR_PROFILE): Likewise.
 269         (SR_MEMTAG): Likewise.
 270         (SR_SCXTNUM): Likewise.
 271         (aarch64_sys_regs): Refactor to store feature information in the table.
 272         (aarch64_sys_reg_supported_p): Collapse logic for system registers
 273         that now describe their own features.
 274         (aarch64_pstatefield_supported_p): Likewise.
 275
 276 2020-06-09  H.J. Lu  <hongjiu.lu@intel.com>
 277
 278         * i386-dis.c (prefix_table): Fix a typo in comments.
 279
 280 2020-06-09  Jan Beulich  <jbeulich@suse.com>
 281
 282         * i386-dis.c (rex_ignored): Delete.
 283         (ckprefix): Drop rex_ignored initialization.
 284         (get_valid_dis386): Drop setting of rex_ignored.
 285         (print_insn): Drop checking of rex_ignored. Don't record data
 286         size prefix as used with VEX-and-alike encodings.
 287
 288 2020-06-09  Jan Beulich  <jbeulich@suse.com>
 289
 290         * i386-dis.c (MOD_0F12_PREFIX_2, MOD_0F16_PREFIX_2,
 291         MOD_VEX_0F12_PREFIX_2, MOD_VEX_0F16_PREFIX_2): New enumerators.
 292         (VEX_LEN_0F12_P_2, VEX_LEN_0F16_P_2): Delete.
 293         (VEX_LEN_0F12_P_2_M_0, VEX_LEN_0F16_P_2_M_0): Define.
 294         (prefix_table): Decode MOD for cases 2 of opcodes 0F12, 0F16,
 295         VEX_0F12, and VEX_0F16.
 296         (vex_len_table): Use X for vmovlp* and vmovh*s. Drop
 297         VEX_LEN_0F12_P_2 and VEX_LEN_0F16_P_2 entries.
 298         (mod_table): Use X for movlpX and movhpX. Drop PREFIX_OPCODE
 299         from movlps and movhlps. New MOD_0F12_PREFIX_2,
 300         MOD_0F16_PREFIX_2, MOD_VEX_0F12_PREFIX_2, and
 301         MOD_VEX_0F16_PREFIX_2 entries.
 302
 303 2020-06-09  Jan Beulich  <jbeulich@suse.com>
 304
 305         * i386-dis.c (MOD_EVEX_0F12_PREFIX_2, MOD_EVEX_0F13,
 306         MOD_EVEX_0F16_PREFIX_2, MOD_EVEX_0F17, MOD_EVEX_0F2B): New enumerators.
 307         (PREFIX_EVEX_0F13, PREFIX_EVEX_0F14, PREFIX_EVEX_0F15,
 308         PREFIX_EVEX_0F17, PREFIX_EVEX_0F28, PREFIX_EVEX_0F29,
 309         PREFIX_EVEX_0F2B, PREFIX_EVEX_0F54, PREFIX_EVEX_0F55,
 310         PREFIX_EVEX_0F56, PREFIX_EVEX_0F57, PREFIX_EVEX_0FC6,
 311         EVEX_W_0F10_P_0, EVEX_W_0F10_P_2, EVEX_W_0F11_P_0,
 312         EVEX_W_0F11_P_2, EVEX_W_0F12_P_0_M_0, EVEX_W_0F12_P_2,
 313         EVEX_W_0F13_P_0, EVEX_W_0F13_P_2, EVEX_W_0F14_P_0,
 314         EVEX_W_0F14_P_2, EVEX_W_0F15_P_0, EVEX_W_0F15_P_2,
 315         EVEX_W_0F16_P_0_M_0, EVEX_W_0F16_P_2, EVEX_W_0F17_P_0,
 316         EVEX_W_0F17_P_2, EVEX_W_0F28_P_0, EVEX_W_0F28_P_2,
 317         EVEX_W_0F29_P_0, EVEX_W_0F29_P_2, EVEX_W_0F2B_P_0,
 318         EVEX_W_0F2B_P_2, EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2,
 319         EVEX_W_0F2F_P_0, EVEX_W_0F2F_P_2, EVEX_W_0F51_P_0,
 320         EVEX_W_0F51_P_2, EVEX_W_0F54_P_0, EVEX_W_0F54_P_2,
 321         EVEX_W_0F55_P_0, EVEX_W_0F55_P_2, EVEX_W_0F56_P_0,
 322         EVEX_W_0F56_P_2, EVEX_W_0F57_P_0, EVEX_W_0F57_P_2,
 323         EVEX_W_0F58_P_0, EVEX_W_0F58_P_2, EVEX_W_0F59_P_0,
 324         EVEX_W_0F59_P_2, EVEX_W_0F5C_P_0, EVEX_W_0F5C_P_2,
 325         EVEX_W_0F5D_P_0, EVEX_W_0F5D_P_2, EVEX_W_0F5E_P_0,
 326         EVEX_W_0F5E_P_2, EVEX_W_0F5F_P_0, EVEX_W_0F5F_P_2,
 327         EVEX_W_0FC2_P_0, EVEX_W_0FC2_P_2, EVEX_W_0FC6_P_0,
 328         EVEX_W_0FC6_P_2): Delete.
 329         (print_insn): Add EVEX.W vs embedded prefix consistency check
 330         to prefix validation.
 331         * i386-dis-evex.h (evex_table): Don't further descend for
 332         vunpcklpX, vunpckhpX, vmovapX, vandpX, vandnpX, vorpX, vxorpX,
 333         and vshufpX. Continue with MOD decoding for opcodes 0F13, 0F17,
 334         and 0F2B.
 335         * i386-dis-evex-mod.h: Add/adjust vmovlpX/vmovhpX entries.
 336         * i386-dis-evex-prefix.h: Don't further descend for vmovupX,
 337         vucomisX, vcomisX, vsqrtpX, vaddpX, vmulpX, vsubpX, vminpX,
 338         vdivpX, vmaxpX, and vcmppX. Continue with MOD decoding for cases
 339         2 of PREFIX_EVEX_0F12, PREFIX_EVEX_0F16, and PREFIX_EVEX_0F29.
 340         Drop PREFIX_EVEX_0F13, PREFIX_EVEX_0F14, PREFIX_EVEX_0F15,
 341         PREFIX_EVEX_0F17, PREFIX_EVEX_0F28, PREFIX_EVEX_0F2B,
 342         PREFIX_EVEX_0F54, PREFIX_EVEX_0F55, PREFIX_EVEX_0F56,
 343         PREFIX_EVEX_0F57, and PREFIX_EVEX_0FC6 entries.
 344         * i386-dis-evex-w.h: Drop EVEX_W_0F10_P_0, EVEX_W_0F10_P_2,
 345         EVEX_W_0F11_P_0, EVEX_W_0F11_P_2, EVEX_W_0F12_P_0_M_0,
 346         EVEX_W_0F12_P_2, EVEX_W_0F12_P_3, EVEX_W_0F13_P_0,
 347         EVEX_W_0F13_P_2, EVEX_W_0F14_P_0, EVEX_W_0F14_P_2,
 348         EVEX_W_0F15_P_0, EVEX_W_0F15_P_2, EVEX_W_0F16_P_0_M_0,
 349         EVEX_W_0F16_P_2, EVEX_W_0F17_P_0, EVEX_W_0F17_P_2,
 350         EVEX_W_0F28_P_0, EVEX_W_0F28_P_2, EVEX_W_0F29_P_0,
 351         EVEX_W_0F29_P_2, EVEX_W_0F2B_P_0, EVEX_W_0F2B_P_2,
 352         EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2, EVEX_W_0F2F_P_0,
 353         EVEX_W_0F2F_P_2, EVEX_W_0F51_P_0, EVEX_W_0F51_P_2,
 354         EVEX_W_0F54_P_0, EVEX_W_0F54_P_2, EVEX_W_0F55_P_0,
 355         EVEX_W_0F55_P_2, EVEX_W_0F56_P_0, EVEX_W_0F56_P_2,
 356         EVEX_W_0F57_P_0, EVEX_W_0F57_P_2, EVEX_W_0F58_P_0,
 357         EVEX_W_0F58_P_2, EVEX_W_0F59_P_0, EVEX_W_0F59_P_2,
 358         EVEX_W_0F5C_P_0, EVEX_W_0F5C_P_2, EVEX_W_0F5D_P_0,
 359         EVEX_W_0F5D_P_2, EVEX_W_0F5E_P_0, EVEX_W_0F5E_P_2,
 360         EVEX_W_0F5F_P_0, EVEX_W_0F5F_P_2, EVEX_W_0FC2_P_0,
 361         EVEX_W_0FC2_P_2, EVEX_W_0FC6_P_0, and EVEX_W_0FC6_P_2 entries.
 362
 363 2020-06-09  Jan Beulich  <jbeulich@suse.com>
 364
 365         * i386-dis.c (vex_table): Use PREFIX_OPCODE for vunpcklpX,
 366         vunpckhpX, vmovapX, vandpX, vandnpX, vorpX, vxorpX and vshufpX.
 367         (vex_len_table) : Likewise for vmovlpX, vmovhpX, vmovntpX, and
 368         vmovmskpX.
 369         (print_insn): Drop pointless check against bad_opcode. Split
 370         prefix validation into legacy and VEX-and-alike parts.
 371         (putop): Re-work 'X' macro handling.
 372
 373 2020-06-09  Jan Beulich  <jbeulich@suse.com>
 374
 375         * i386-dis.c (MOD_0F51): Rename to ...
 376         (MOD_0F50): ... this.
 377
 378 2020-06-08  Alex Coplan  <alex.coplan@arm.com>
 379
 380         * arm-dis.c (arm_opcodes): Add dfb.
 381         (thumb32_opcodes): Add dfb.
 382
 383 2020-06-08  Jan Beulich  <jbeulich@suse.com>
 384
 385         * i386-opc.h (reg_entry): Const-qualify reg_name field.
 386
 387 2020-06-06  Alan Modra  <amodra@gmail.com>
 388
 389         * ppc-dis.c (ppc_opts): Accept -mpwr10/-Mpwr10.
 390
 391 2020-06-05  Alan Modra  <amodra@gmail.com>
 392
 393         * cgen-dis.c (hash_insn_array): Increase size of buf.  Assert
 394         size is large enough.
 395
 396 2020-06-04  Jose E. Marchesi  <jose.marchesi@oracle.com>
 397
 398         * disassemble.c (disassemble_init_for_target): Set endian_code for
 399         bpf targets.
 400         * bpf-desc.c: Regenerate.
 401         * bpf-opc.c: Likewise.
 402         * bpf-dis.c: Likewise.
 403
 404 2020-06-03  Jose E. Marchesi  <jose.marchesi@oracle.com>
 405
 406         * cgen-opc.c (cgen_get_insn_value): Get an `endian' argument.
 407         (cgen_put_insn_value): Likewise.
 408         (cgen_lookup_insn): Pass endianness to cgen_{get,put}_insn_value.
 409         * cgen-dis.in (print_insn): Likewise.
 410         * cgen-ibld.in (insert_1): Likewise.
 411         (insert_1): Likewise.
 412         (insert_insn_normal): Likewise.
 413         (extract_1): Likewise.
 414         * bpf-dis.c: Regenerate.
 415         * bpf-ibld.c: Likewise.
 416         * bpf-ibld.c: Likewise.
 417         * cgen-dis.in: Likewise.
 418         * cgen-ibld.in: Likewise.
 419         * cgen-opc.c: Likewise.
 420         * epiphany-dis.c: Likewise.
 421         * epiphany-ibld.c: Likewise.
 422         * fr30-dis.c: Likewise.
 423         * fr30-ibld.c: Likewise.
 424         * frv-dis.c: Likewise.
 425         * frv-ibld.c: Likewise.
 426         * ip2k-dis.c: Likewise.
 427         * ip2k-ibld.c: Likewise.
 428         * iq2000-dis.c: Likewise.
 429         * iq2000-ibld.c: Likewise.
 430         * lm32-dis.c: Likewise.
 431         * lm32-ibld.c: Likewise.
 432         * m32c-dis.c: Likewise.
 433         * m32c-ibld.c: Likewise.
 434         * m32r-dis.c: Likewise.
 435         * m32r-ibld.c: Likewise.
 436         * mep-dis.c: Likewise.
 437         * mep-ibld.c: Likewise.
 438         * mt-dis.c: Likewise.
 439         * mt-ibld.c: Likewise.
 440         * or1k-dis.c: Likewise.
 441         * or1k-ibld.c: Likewise.
 442         * xc16x-dis.c: Likewise.
 443         * xc16x-ibld.c: Likewise.
 444         * xstormy16-dis.c: Likewise.
 445         * xstormy16-ibld.c: Likewise.
 446
 447 2020-06-04  Jose E. Marchesi  <jemarch@gnu.org>
 448
 449         * cgen-dis.in (cpu_desc_list): New field `insn_endian'.
 450         (print_insn_): Handle instruction endian.
 451         * bpf-dis.c: Regenerate.
 452         * bpf-desc.c: Regenerate.
 453         * epiphany-dis.c: Likewise.
 454         * epiphany-desc.c: Likewise.
 455         * fr30-dis.c: Likewise.
 456         * fr30-desc.c: Likewise.
 457         * frv-dis.c: Likewise.
 458         * frv-desc.c: Likewise.
 459         * ip2k-dis.c: Likewise.
 460         * ip2k-desc.c: Likewise.
 461         * iq2000-dis.c: Likewise.
 462         * iq2000-desc.c: Likewise.
 463         * lm32-dis.c: Likewise.
 464         * lm32-desc.c: Likewise.
 465         * m32c-dis.c: Likewise.
 466         * m32c-desc.c: Likewise.
 467         * m32r-dis.c: Likewise.
 468         * m32r-desc.c: Likewise.
 469         * mep-dis.c: Likewise.
 470         * mep-desc.c: Likewise.
 471         * mt-dis.c: Likewise.
 472         * mt-desc.c: Likewise.
 473         * or1k-dis.c: Likewise.
 474         * or1k-desc.c: Likewise.
 475         * xc16x-dis.c: Likewise.
 476         * xc16x-desc.c: Likewise.
 477         * xstormy16-dis.c: Likewise.
 478         * xstormy16-desc.c: Likewise.
 479
 480 2020-06-03  Nick Clifton  <nickc@redhat.com>
 481
 482         * po/sr.po: Updated Serbian translation.
 483
 484 2020-06-03  Nelson Chu  <nelson.chu@sifive.com>
 485
 486         * riscv-opc.c (riscv_get_isa_spec_class): Change bfd_boolean to int.
 487         (riscv_get_priv_spec_class): Likewise.
 488
 489 2020-06-01  Alan Modra  <amodra@gmail.com>
 490
 491         * bpf-desc.c: Regenerate.
 492
 493 2020-05-28  Jose E. Marchesi  <jose.marchesi@oracle.com>
 494             David Faust <david.faust@oracle.com>
 495
 496         * bpf-desc.c: Regenerate.
 497         * bpf-opc.h: Likewise.
 498         * bpf-opc.c: Likewise.
 499         * bpf-dis.c: Likewise.
 500
 501 2020-05-28  Alan Modra  <amodra@gmail.com>
 502
 503         * nios2-dis.c (nios2_print_insn_arg): Avoid shift left of negative
 504         values.
 505
 506 2020-05-28  Alan Modra  <amodra@gmail.com>
 507
 508         * ns32k-dis.c (print_insn_arg): Handle d value of 'f' for
 509         immediates.
 510         (print_insn_ns32k): Revert last change.
 511
 512 2020-05-28  Nick Clifton  <nickc@redhat.com>
 513
 514         * ns32k-dis.c (print_insn_ns32k): Change the arg_bufs array to
 515         static.
 516
 517 2020-05-26  Sandra Loosemore  <sandra@codesourcery.com>
 518
 519         Fix extraction of signed constants in nios2 disassembler (again).
 520
 521         * nios2-dis.c (nios2_print_insn_arg): Add explicit casts to
 522         extractions of signed fields.
 523
 524 2020-05-26  Stefan Schulze Frielinghaus  <stefansf@linux.ibm.com>
 525
 526         * s390-opc.txt: Relocate vector load/store instructions with
 527         additional alignment parameter and change architecture level
 528         constraint from z14 to z13.
 529
 530 2020-05-21  Alan Modra  <amodra@gmail.com>
 531
 532         * arc-ext.c: Replace "if (x) free (x)" with "free (x)" throughout.
 533         * sparc-dis.c: Likewise.
 534         * tic4x-dis.c: Likewise.
 535         * xtensa-dis.c: Likewise.
 536         * bpf-desc.c: Regenerate.
 537         * epiphany-desc.c: Regenerate.
 538         * fr30-desc.c: Regenerate.
 539         * frv-desc.c: Regenerate.
 540         * ip2k-desc.c: Regenerate.
 541         * iq2000-desc.c: Regenerate.
 542         * lm32-desc.c: Regenerate.
 543         * m32c-desc.c: Regenerate.
 544         * m32r-desc.c: Regenerate.
 545         * mep-asm.c: Regenerate.
 546         * mep-desc.c: Regenerate.
 547         * mt-desc.c: Regenerate.
 548         * or1k-desc.c: Regenerate.
 549         * xc16x-desc.c: Regenerate.
 550         * xstormy16-desc.c: Regenerate.
 551
 552 2020-05-20  Nelson Chu  <nelson.chu@sifive.com>
 553
 554         * riscv-opc.c (riscv_ext_version_table): The table used to store
 555         all information about the supported spec and the corresponding ISA
 556         versions.  Currently, only Zicsr is supported to verify the
 557         correctness of Z sub extension settings.  Others will be supported
 558         in the future patches.
 559         (struct isa_spec_t, isa_specs): List for all supported ISA spec
 560         classes and the corresponding strings.
 561         (riscv_get_isa_spec_class): New function.  Get the corresponding ISA
 562         spec class by giving a ISA spec string.
 563         * riscv-opc.c (struct priv_spec_t): New structure.
 564         (struct priv_spec_t priv_specs): List for all supported privilege spec
 565         classes and the corresponding strings.
 566         (riscv_get_priv_spec_class): New function.  Get the corresponding
 567         privilege spec class by giving a spec string.
 568         (riscv_get_priv_spec_name): New function.  Get the corresponding
 569         privilege spec string by giving a CSR version class.
 570         * riscv-dis.c: Updated since DECLARE_CSR is changed.
 571         * riscv-dis.c: Add new disassembler option -Mpriv-spec to dump the CSR
 572         according to the chosen version.  Build a hash table riscv_csr_hash to
 573         store the valid CSR for the chosen pirv verison.  Dump the direct
 574         CSR address rather than it's name if it is invalid.
 575         (parse_riscv_dis_option_without_args): New function.  Parse the options
 576         without arguments.
 577         (parse_riscv_dis_option): Call parse_riscv_dis_option_without_args to
 578         parse the options without arguments first, and then handle the options
 579         with arguments.  Add the new option -Mpriv-spec, which has argument.
 580         * riscv-dis.c (print_riscv_disassembler_options): Add description
 581         about the new OBJDUMP option.
 582
 583 2020-05-19  Peter Bergner  <bergner@linux.ibm.com>
 584
 585         * ppc-opc.c (insert_ls, extract_ls): Handle 3-bit L fields and new
 586         WC values on POWER10 sync, dcbf  and wait instructions.
 587         (insert_pl, extract_pl): New functions.
 588         (L2OPT, LS, WC): Use insert_ls and extract_ls.
 589         (LS3): New , 3-bit L for sync.
 590         (LS3, L3OPT): New, 3-bit L for sync and dcbf.
 591         (SC2, PL): New, 2-bit SC and PL for sync and wait.
 592         (XWCPL_MASK, XL3RT_MASK, XSYNCLS_MASK): New instruction masks.
 593         (XOPL3, XWCPL, XSYNCLS): New opcode macros.
 594         (powerpc_opcodes) <dcbflp, dcbfps, dcbstps pause_short, phwsync,
 595         plwsync, stcisync, stncisync, stsync, waitrsv>: New extended mnemonics.
 596         <wait>: Enable PL operand on POWER10.
 597         <dcbf>: Enable L3OPT operand on POWER10.
 598         <sync>: Enable SC2 operand on POWER10.
 599
 600 2020-05-19  Stafford Horne  <shorne@gmail.com>
 601
 602         PR 25184
 603         * or1k-asm.c: Regenerate.
 604         * or1k-desc.c: Regenerate.
 605         * or1k-desc.h: Regenerate.
 606         * or1k-dis.c: Regenerate.
 607         * or1k-ibld.c: Regenerate.
 608         * or1k-opc.c: Regenerate.
 609         * or1k-opc.h: Regenerate.
 610         * or1k-opinst.c: Regenerate.
 611
 612 2020-05-11  Alan Modra  <amodra@gmail.com>
 613
 614         * ppc-opc (powerpc_opcodes): Add xscmpeqqp, xscmpgeqp, xscmpgtqp,
 615         xsmaxcqp, xsmincqp.
 616
 617 2020-05-11  Alan Modra  <amodra@gmail.com>
 618
 619         * ppc-opc.c (powerpc_opcodes): Add lxvrbx, lxvrhx, lxvrwx, lxvrdx,
 620         stxvrbx, stxvrhx, stxvrwx, stxvrdx.
 621
 622 2020-05-11  Alan Modra  <amodra@gmail.com>
 623
 624         * ppc-opc.c (powerpc_opcodes): Add xvtlsbb.
 625
 626 2020-05-11  Alan Modra  <amodra@gmail.com>
 627
 628         * ppc-opc.c (powerpc_opcodes): Add vstribl, vstribr, vstrihl, vstrihr,
 629         vclrlb, vclrrb, vstribl., vstribr., vstrihl., vstrihr..
 630
 631 2020-05-11  Peter Bergner  <bergner@linux.ibm.com>
 632
 633         * ppc-opc.c (powerpc_opcodes) <setbc, setbcr, setnbc, setnbcr>: New
 634         mnemonics.
 635
 636 2020-05-11  Alan Modra  <amodra@gmail.com>
 637
 638         * ppc-opc.c (UIM8, P_U8XX4_MASK): Define.
 639         (powerpc_opcodes): Add vgnb, vcfuged, vpextd, vpdepd, vclzdm,
 640         vctzdm, cntlzdm, pdepd, pextd, cfuged, cnttzdm.
 641         (prefix_opcodes): Add xxeval.
 642
 643 2020-05-11  Alan Modra  <amodra@gmail.com>
 644
 645         * ppc-opc.c (powerpc_opcodes): Add xxgenpcvbm, xxgenpcvhm,
 646         xxgenpcvwm, xxgenpcvdm.
 647
 648 2020-05-11  Alan Modra  <amodra@gmail.com>
 649
 650         * ppc-opc.c (MP, VXVAM_MASK): Define.
 651         (VXVAPS_MASK): Use VXVA_MASK.
 652         (powerpc_opcodes): Add mtvsrbmi, vexpandbm, vexpandhm, vexpandwm,
 653         vexpanddm, vexpandqm, vextractbm, vextracthm, vextractwm,
 654         vextractdm, vextractqm, mtvsrbm, mtvsrhm, mtvsrwm, mtvsrdm, mtvsrqm,
 655         vcntmbb, vcntmbh, vcntmbw, vcntmbd.
 656
 657 2020-05-11  Alan Modra  <amodra@gmail.com>
 658             Peter Bergner  <bergner@linux.ibm.com>
 659
 660         * ppc-opc.c (insert_xa6a, extract_xa6a, insert_xb6a, extract_xb6a):
 661         New functions.
 662         (powerpc_operands): Define ACC, PMSK8, PMSK4, PMSK2, XMSK, YMSK,
 663         YMSK2, XA6a, XA6ap, XB6a entries.
 664         (PMMIRR, P_X_MASK, P_XX1_MASK, P_GER_MASK): Define
 665         (P_GER2_MASK, P_GER4_MASK, P_GER8_MASK, P_GER64_MASK): Define.
 666         (PPCVSX4): Define.
 667         (powerpc_opcodes): Add xxmfacc, xxmtacc, xxsetaccz,
 668         xvi8ger4pp, xvi8ger4, xvf16ger2pp, xvf16ger2, xvf32gerpp, xvf32ger,
 669         xvi4ger8pp, xvi4ger8, xvi16ger2spp, xvi16ger2s, xvbf16ger2pp,
 670         xvbf16ger2, xvf64gerpp, xvf64ger, xvi16ger2, xvf16ger2np,
 671         xvf32gernp, xvi8ger4spp, xvi16ger2pp, xvbf16ger2np, xvf64gernp,
 672         xvf16ger2pn, xvf32gerpn, xvbf16ger2pn, xvf64gerpn, xvf16ger2nn,
 673         xvf32gernn, xvbf16ger2nn, xvf64gernn, xvcvbf16sp, xvcvspbf16.
 674         (prefix_opcodes): Add pmxvi8ger4pp, pmxvi8ger4, pmxvf16ger2pp,
 675         pmxvf16ger2, pmxvf32gerpp, pmxvf32ger, pmxvi4ger8pp, pmxvi4ger8,
 676         pmxvi16ger2spp, pmxvi16ger2s, pmxvbf16ger2pp, pmxvbf16ger2,
 677         pmxvf64gerpp, pmxvf64ger, pmxvi16ger2, pmxvf16ger2np, pmxvf32gernp,
 678         pmxvi8ger4spp, pmxvi16ger2pp, pmxvbf16ger2np, pmxvf64gernp,
 679         pmxvf16ger2pn, pmxvf32gerpn, pmxvbf16ger2pn, pmxvf64gerpn,
 680         pmxvf16ger2nn, pmxvf32gernn, pmxvbf16ger2nn, pmxvf64gernn.
 681
 682 2020-05-11  Alan Modra  <amodra@gmail.com>
 683
 684         * ppc-opc.c (insert_imm32, extract_imm32): New functions.
 685         (insert_xts, extract_xts): New functions.
 686         (IMM32, UIM3, IX, UIM5, SH3, XTS, P8RR): Define.
 687         (P_XX4_MASK, P_UXX4_MASK, VSOP, P_VS_MASK, P_VSI_MASK): Define.
 688         (VXRC_MASK, VXSH_MASK): Define.
 689         (powerpc_opcodes): Add vinsbvlx, vsldbi, vextdubvlx, vextdubvrx,
 690         vextduhvlx, vextduhvrx, vextduwvlx, vextduwvrx, vextddvlx,
 691         vextddvrx, vinshvlx, vinswvlx, vinsw, vinsbvrx, vinshvrx,
 692         vinswvrx, vinsd, vinsblx, vsrdbi, vinshlx, vinswlx, vinsdlx,
 693         vinsbrx, vinshrx, vinswrx, vinsdrx, lxvkq.
 694         (prefix_opcodes): Add xxsplti32dx, xxspltidp, xxspltiw, xxblendvb,
 695         xxblendvh, xxblendvw, xxblendvd, xxpermx.
 696
 697 2020-05-11  Alan Modra  <amodra@gmail.com>
 698
 699         * ppc-opc.c (powerpc_opcodes): Add vrlq, vdivuq, vmsumcud, vrlqmi,
 700         vmuloud, vcmpuq, vslq, vdivsq, vcmpsq, vrlqnm, vcmpequq, vmulosd,
 701         vsrq, vdiveuq, vcmpgtuq, vmuleud, vsraq, vdivesq, vcmpgtsq, vmulesd,
 702         vcmpequq., vextsd2q, vmoduq, vcmpgtuq., vmodsq, vcmpgtsq., xscvqpuqz,
 703         xscvuqqp, xscvqpsqz, xscvsqqp, dcffixqq, dctfixqq.
 704
 705 2020-05-11  Alan Modra  <amodra@gmail.com>
 706
 707         * ppc-opc.c (insert_xtp, extract_xtp): New functions.
 708         (XTP, DQXP, DQXP_MASK): Define.
 709         (powerpc_opcodes): Add lxvp, stxvp, lxvpx, stxvpx.
 710         (prefix_opcodes): Add plxvp and pstxvp.
 711
 712 2020-05-11  Alan Modra  <amodra@gmail.com>
 713
 714         * ppc-opc.c (powerpc_opcodes): Add vdivuw, vdivud, vdivsw, vmulld,
 715         vdivsd, vmulhuw, vdiveuw, vmulhud, vdiveud, vmulhsw, vdivesw,
 716         vmulhsd, vdivesd, vmoduw, vmodud, vmodsw, vmodsd.
 717
 718 2020-05-11  Peter Bergner  <bergner@linux.ibm.com>
 719
 720         * ppc-opc.c (powerpc_opcodes) <brd, brh, brw>: New mnemonics.
 721
 722 2020-05-11  Peter Bergner  <bergner@linux.ibm.com>
 723
 724         * ppc-opc.c (insert_l1opt, extract_l1opt): New functions.
 725         (L1OPT): Define.
 726         (powerpc_opcodes) <paste.>: Add L operand for cpu POWER10.
 727
 728 2020-05-11  Peter Bergner  <bergner@linux.ibm.com>
 729
 730         * ppc-opc.c (powerpc_opcodes) <slbiag>: Add variant with L operand.
 731
 732 2020-05-11  Alan Modra  <amodra@gmail.com>
 733
 734         * ppc-dis.c (powerpc_init_dialect): Default to "power10".
 735
 736 2020-05-11  Alan Modra  <amodra@gmail.com>
 737
 738         * ppc-dis.c (ppc_opts): Add "power10" entry.
 739         (print_insn_powerpc): Update for PPC_OPCODE_POWER10 renaming.
 740         * ppc-opc.c (POWER10): Rename from POWERXX.  Update all uses.
 741
 742 2020-05-11  Nick Clifton  <nickc@redhat.com>
 743
 744         * po/fr.po: Updated French translation.
 745
 746 2020-04-30  Alex Coplan  <alex.coplan@arm.com>
 747
 748         * aarch64-opc.h (enum aarch64_field_kind): Add FLD_imm16_2.
 749         * aarch64-opc.c (fields): Add entry for FLD_imm16_2.
 750         (operand_general_constraint_met_p): validate
 751         AARCH64_OPND_UNDEFINED.
 752         * aarch64-tbl.h (aarch64_opcode_table): Add udf instruction, entry
 753         for FLD_imm16_2.
 754         * aarch64-asm-2.c: Regenerated.
 755         * aarch64-dis-2.c: Regenerated.
 756         * aarch64-opc-2.c: Regenerated.
 757
 758 2020-04-29  Nick Clifton  <nickc@redhat.com>
 759
 760         PR 22699
 761         * sh-opc.h: Also use unsigned 8-bit immediate values for the LDRC
 762         and SETRC insns.
 763
 764 2020-04-29  Nick Clifton  <nickc@redhat.com>
 765
 766         * po/sv.po: Updated Swedish translation.
 767
 768 2020-04-29  Nick Clifton  <nickc@redhat.com>
 769
 770         PR 22699
 771         * sh-opc.h (IMM0_8): Replace with IMM0_8S and IMM0_8U.  Use
 772         IMM0_8S for arithmetic insns and IMM0_8U for logical insns.
 773         * sh-dis.c (print_insn_sh): Change IMM0_8 case to IMM0_8S and add
 774         IMM0_8U case.
 775
 776 2020-04-21  Andreas Schwab  <schwab@linux-m68k.org>
 777
 778         PR 25848
 779         * m68k-opc.c (m68k_opcodes): Allow pc-rel for second operand of
 780         cmpi only on m68020up and cpu32.
 781
 782 2020-04-20  Sudakshina Das  <sudi.das@arm.com>
 783
 784         * aarch64-asm.c (aarch64_ins_none): New.
 785         * aarch64-asm.h (ins_none): New declaration.
 786         * aarch64-dis.c (aarch64_ext_none): New.
 787         * aarch64-dis.h (ext_none): New declaration.
 788         * aarch64-opc.c (aarch64_print_operand): Update case for
 789         AARCH64_OPND_BARRIER_PSB.
 790         * aarch64-tbl.h (aarch64_opcode_table): Add tsb.
 791         (AARCH64_OPERANDS): Update inserter/extracter for
 792         AARCH64_OPND_BARRIER_PSB to use new dummy functions.
 793         * aarch64-asm-2.c: Regenerated.
 794         * aarch64-dis-2.c: Regenerated.
 795         * aarch64-opc-2.c: Regenerated.
 796
 797 2020-04-20  Sudakshina Das  <sudi.das@arm.com>
 798
 799         * aarch64-tbl.h (aarch64_feature_bti, BTI, BTI_INSN): Remove.
 800         (aarch64_feature_ras, RAS): Likewise.
 801         (aarch64_feature_stat_profile, STAT_PROFILE): Likewise.
 802         (aarch64_opcode_table): Update bti, xpaclri, pacia1716, pacib1716,
 803         autia1716, autib1716, esb, psb, dgh, paciaz, paciasp, pacibz, pacibsp,
 804         autiaz, autiasp, autibz, autibsp to be CORE_INSN.
 805         * aarch64-asm-2.c: Regenerated.
 806         * aarch64-dis-2.c: Regenerated.
 807         * aarch64-opc-2.c: Regenerated.
 808
 809 2020-04-17  Fredrik Strupe  <fredrik@strupe.net>
 810
 811         * arm-dis.c (neon_opcodes): Fix VDUP instruction masks.
 812         (print_insn_neon): Support disassembly of conditional
 813         instructions.
 814
 815 2020-02-16  David Faust  <david.faust@oracle.com>
 816
 817         * bpf-desc.c: Regenerate.
 818         * bpf-desc.h: Likewise.
 819         * bpf-opc.c: Regenerate.
 820         * bpf-opc.h: Likewise.
 821
 822 2020-04-07  Lili Cui  <lili.cui@intel.com>
 823
 824         * i386-dis.c (enum): Add PREFIX_0F01_REG_5_MOD_3_RM_1,
 825         (prefix_table): New instructions (see prefixes above).
 826         (rm_table): Likewise
 827         * i386-gen.c (cpu_flag_init): Add CPU_TSXLDTRK_FLAGS,
 828         CPU_ANY_TSXLDTRK_FLAGS.
 829         (cpu_flags): Add CpuTSXLDTRK.
 830         * i386-opc.h (enum): Add CpuTSXLDTRK.
 831         (i386_cpu_flags): Add cputsxldtrk.
 832         * i386-opc.tbl: Add XSUSPLDTRK insns.
 833         * i386-init.h: Regenerate.
 834         * i386-tbl.h: Likewise.
 835
 836 2020-04-02  Lili Cui  <lili.cui@intel.com>
 837
 838         * i386-dis.c (prefix_table): New instructions serialize.
 839         * i386-gen.c (cpu_flag_init): Add CPU_SERIALIZE_FLAGS,
 840         CPU_ANY_SERIALIZE_FLAGS.
 841         (cpu_flags): Add CpuSERIALIZE.
 842         * i386-opc.h (enum): Add CpuSERIALIZE.
 843         (i386_cpu_flags): Add cpuserialize.
 844         * i386-opc.tbl: Add SERIALIZE insns.
 845         * i386-init.h: Regenerate.
 846         * i386-tbl.h: Likewise.
 847
 848 2020-03-26  Alan Modra  <amodra@gmail.com>
 849
 850         * disassemble.h (opcodes_assert): Declare.
 851         (OPCODES_ASSERT): Define.
 852         * disassemble.c: Don't include assert.h.  Include opintl.h.
 853         (opcodes_assert): New function.
 854         * h8300-dis.c (bfd_h8_disassemble_init): Use OPCODES_ASSERT.
 855         (bfd_h8_disassemble): Reduce size of data array.  Correctly
 856         calculate maxlen.  Omit insn decoding when insn length exceeds
 857         maxlen.  Exit from nibble loop when looking for E, before
 858         accessing next data byte.  Move processing of E outside loop.
 859         Replace tests of maxlen in loop with assertions.
 860
 861 2020-03-26  Alan Modra  <amodra@gmail.com>
 862
 863         * arc-dis.c (find_format): Init needs_limm.  Simplify use of limm.
 864
 865 2020-03-25  Alan Modra  <amodra@gmail.com>
 866
 867         * z80-dis.c (suffix): Init mybuf.
 868
 869 2020-03-22  Alan Modra  <amodra@gmail.com>
 870
 871         * h8300-dis.c (bfd_h8_disassemble): Limit data[] access to that
 872         successflly read from section.
 873
 874 2020-03-22  Alan Modra  <amodra@gmail.com>
 875
 876         * arc-dis.c (find_format): Use ISO C string concatenation rather
 877         than line continuation within a string.  Don't access needs_limm
 878         before testing opcode != NULL.
 879
 880 2020-03-22  Alan Modra  <amodra@gmail.com>
 881
 882         * ns32k-dis.c (print_insn_arg): Update comment.
 883         (print_insn_ns32k): Reduce size of index_offset array, and
 884         initialize, passing -1 to print_insn_arg for args that are not
 885         an index.  Don't exit arg loop early.  Abort on bad arg number.
 886
 887 2020-03-22  Alan Modra  <amodra@gmail.com>
 888
 889         * s12z-dis.c (abstract_read_memory): Don't print error on EOI.
 890         * s12z-opc.c: Formatting.
 891         (operands_f): Return an int.
 892         (opr_n_bytes_p1): Return -1 on reaching buffer memory limit.
 893         (opr_n_bytes2, bfextins_n_bytes, mul_n_bytes, bm_n_bytes),
 894         (shift_n_bytes, mov_imm_opr_n_bytes, loop_prim_n_bytes),
 895         (exg_sex_discrim): Likewise.
 896         (create_immediate_operand, create_bitfield_operand),
 897         (create_register_operand_with_size, create_register_all_operand),
 898         (create_register_all16_operand, create_simple_memory_operand),
 899         (create_memory_operand, create_memory_auto_operand): Don't
 900         segfault on malloc failure.
 901         (z_ext24_decode): Return an int status, negative on fail, zero
 902         on success.
 903         (x_imm1, imm1_decode, trap_decode, z_opr_decode, z_opr_decode2),
 904         (imm1234, reg_s_imm, reg_s_opr, z_imm1234_8base, z_imm1234_0base),
 905         (z_tfr, z_reg, reg_xy, lea_reg_xys_opr, lea_reg_xys, rel_15_7),
 906         (decode_rel_15_7, cmp_xy, sub_d6_x_y, sub_d6_y_x),
 907         (ld_18bit_decode, mul_decode, bm_decode, bm_rel_decode),
 908         (mov_imm_opr, ld_18bit_decode, exg_sex_decode),
 909         (loop_primitive_decode, shift_decode, psh_pul_decode),
 910         (bit_field_decode): Similarly.
 911         (z_decode_signed_value, decode_signed_value): Similarly.  Add arg
 912         to return value, update callers.
 913         (x_opr_decode_with_size): Check all reads, returning NULL on fail.
 914         Don't segfault on NULL operand.
 915         (decode_operation): Return OP_INVALID on first fail.
 916         (decode_s12z): Check all reads, returning -1 on fail.
 917
 918 2020-03-20  Alan Modra  <amodra@gmail.com>
 919
 920         * metag-dis.c (print_insn_metag): Don't ignore status from
 921         read_memory_func.
 922
 923 2020-03-20  Alan Modra  <amodra@gmail.com>
 924
 925         * nds32-dis.c (print_insn_nds32): Remove unnecessary casts.
 926         Initialize parts of buffer not written when handling a possible
 927         2-byte insn at end of section.  Don't attempt decoding of such
 928         an insn by the 4-byte machinery.
 929
 930 2020-03-20  Alan Modra  <amodra@gmail.com>
 931
 932         * ppc-dis.c (print_insn_powerpc): Only clear needed bytes of
 933         partially filled buffer.  Prevent lookup of 4-byte insns when
 934         only VLE 2-byte insns are possible due to section size.  Print
 935         ".word" rather than ".long" for 2-byte leftovers.
 936
 937 2020-03-17  Sergey Belyashov  <sergey.belyashov@gmail.com>
 938
 939         PR 25641
 940         * z80-dis.c: Fix disassembling ED+A4/AC/B4/BC opcodes.
 941
 942 2020-03-13  Jan Beulich  <jbeulich@suse.com>
 943
 944         * i386-dis.c (X86_64_0D): Rename to ...
 945         (X86_64_0E): ... this.
 946
 947 2020-03-09  H.J. Lu  <hongjiu.lu@intel.com>
 948
 949         * Makefile.am ($(srcdir)/i386-init.h): Also pass -P to $(CPP).
 950         * Makefile.in: Regenerated.
 951
 952 2020-03-09  Jan Beulich  <jbeulich@suse.com>
 953
 954         * i386-opc.tbl (avx_irel): New. Use is for AVX512 vpcmp*
 955         3-operand pseudos.
 956         * i386-tbl.h: Re-generate.
 957
 958 2020-03-09  Jan Beulich  <jbeulich@suse.com>
 959
 960         * i386-opc.tbl (xop_elem, xop_irel, xop_sign): New. Use them for XOP vpcom*,
 961         vprot*, vpsha*, and vpshl*.
 962         * i386-tbl.h: Re-generate.
 963
 964 2020-03-09  Jan Beulich  <jbeulich@suse.com>
 965
 966         * i386-opc.tbl (avx_frel): New. Use it for AVX/AVX512 vcmpps,
 967         vcmpss, vcmppd, and vcmpsd 3-operand pseudo-ops.
 968         * i386-tbl.h: Re-generate.
 969
 970 2020-03-09  Jan Beulich  <jbeulich@suse.com>
 971
 972         * i386-gen.c (set_bitfield): Ignore zero-length field names.
 973         * i386-opc.tbl (sse_frel): New. Use it for SSE/SSE2 cmpps,
 974         cmpss, cmppd, and cmpsd 2-operand pseudo-ops.
 975         * i386-tbl.h: Re-generate.
 976
 977 2020-03-09  Jan Beulich  <jbeulich@suse.com>
 978
 979         * i386-gen.c (struct template_arg, struct template_instance,
 980         struct template_param, struct template, templates,
 981         parse_template, expand_templates): New.
 982         (process_i386_opcodes): Various local variables moved to
 983         expand_templates. Call parse_template and expand_templates.
 984         * i386-opc.tbl (cc): New. Use it for Jcc, SETcc, and CMOVcc.
 985         * i386-tbl.h: Re-generate.
 986
 987 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 988
 989         * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd, vcvtps2ph,
 990         vcvtps2qq, vcvtps2uqq, vcvttps2qq, vcvttps2uqq): Fold separate
 991         register and memory source templates. Replace VexW= by VexW*
 992         where applicable.
 993         * i386-tbl.h: Re-generate.
 994
 995 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 996
 997         * i386-opc.tbl: Drop IgnoreSize from various SIMD insns. Replace
 998         VexW= by VexW* and VexVVVV=1 by just VexVVVV where applicable.
 999         * i386-tbl.h: Re-generate.
1000
1001 2020-03-06  Jan Beulich  <jbeulich@suse.com>
1002
1003         * i386-opc.tbl (fildll, fistpll, fisttpll): Add ATTSyntax.
1004         * i386-tbl.h: Re-generate.
1005
1006 2020-03-06  Jan Beulich  <jbeulich@suse.com>
1007
1008         * i386-opc.tbl (movq): Drop NoRex64 from XMM/XMM SSE2AVX variants.
1009         (movmskps, pextrw, pinsrw, pmovmskb, movmskpd, extractps,
1010         pextrb, pinsrb, roundsd): Drop NoRex64 and where applicable use
1011         VexW0 on SSE2AVX variants.
1012         (vmovq): Drop NoRex64 from XMM/XMM variants.
1013         (vextractps, vmovmskpd, vmovmskps, vpextrb, vpextrw, vpinsrb,
1014         vpinsrw, vpmovmskb, vroundsd, vpmovmskb): Drop NoRex64 and where
1015         applicable use VexW0.
1016         * i386-tbl.h: Re-generate.
1017
1018 2020-03-06  Jan Beulich  <jbeulich@suse.com>
1019
1020         * i386-gen.c (opcode_modifiers): Remove Rex64 field.
1021         * i386-opc.h (Rex64): Delete.
1022         (struct i386_opcode_modifier): Remove rex64 field.
1023         * i386-opc.tbl (crc32): Drop Rex64.
1024         Replace Rex64 with Size64 everywhere else.
1025         * i386-tbl.h: Re-generate.
1026
1027 2020-03-06  Jan Beulich  <jbeulich@suse.com>
1028
1029         * i386-dis.c (OP_E_memory): Exclude recording of used address
1030         prefix for "bnd" modes only in 64-bit mode. Don't decode 16-bit
1031         addressed memory operands for MPX insns.
1032
1033 2020-03-06  Jan Beulich  <jbeulich@suse.com>
1034
1035         * i386-opc.tbl (movmskps, mwait, vmread, vmwrite, invept,
1036         invvpid, invpcid, rdfsbase, rdgsbase, wrfsbase, wrgsbase, adcx,
1037         adox, mwaitx, rdpid, movdiri): Add IgnoreSize.
1038         (ptwrite): Split into non-64-bit and 64-bit forms.
1039         * i386-tbl.h: Re-generate.
1040
1041 2020-03-06  Jan Beulich  <jbeulich@suse.com>
1042
1043         * i386-opc.tbl (tpause, umwait): Add IgnoreSize. Add 3-operand
1044         template.
1045         * i386-tbl.h: Re-generate.
1046
1047 2020-03-04  Jan Beulich  <jbeulich@suse.com>
1048
1049         * i386-dis.c (PREFIX_0F01_REG_3_RM_1): New.
1050         (prefix_table): Move vmmcall here. Add vmgexit.
1051         (rm_table): Replace vmmcall entry by prefix_table[] escape.
1052         * i386-gen.c (cpu_flag_init): Add CPU_SEV_ES_FLAGS entry.
1053         (cpu_flags): Add CpuSEV_ES entry.
1054         * i386-opc.h (CpuSEV_ES): New.
1055         (union i386_cpu_flags): Add cpusev_es field.
1056         * i386-opc.tbl (vmgexit): New.
1057         * i386-init.h, i386-tbl.h: Re-generate.
1058
1059 2020-03-03  H.J. Lu  <hongjiu.lu@intel.com>
1060
1061         * i386-gen.c (opcode_modifiers): Replace IgnoreSize/DefaultSize
1062         with MnemonicSize.
1063         * i386-opc.h (IGNORESIZE): New.
1064         (DEFAULTSIZE): Likewise.
1065         (IgnoreSize): Removed.
1066         (DefaultSize): Likewise.
1067         (MnemonicSize): New.
1068         (i386_opcode_modifier): Replace ignoresize/defaultsize with
1069         mnemonicsize.
1070         * i386-opc.tbl (IgnoreSize): New.
1071         (DefaultSize): Likewise.
1072         * i386-tbl.h: Regenerated.
1073
1074 2020-03-03  Sergey Belyashov  <sergey.belyashov@gmail.com>
1075
1076         PR 25627
1077         * z80-dis.c: Fix disassembly of LD IY,(HL) and D (HL),IX
1078         instructions.
1079
1080 2020-03-03  H.J. Lu  <hongjiu.lu@intel.com>
1081
1082         PR gas/25622
1083         * i386-opc.tbl: Add IgnoreSize to cvtsi2sd, cvtsi2ss, vcvtsi2sd,
1084         vcvtsi2ss, vcvtusi2sd and vcvtusi2ss for AT&T syntax.
1085         * i386-tbl.h: Regenerated.
1086
1087 2020-02-26  Alan Modra  <amodra@gmail.com>
1088
1089         * aarch64-asm.c: Indent labels correctly.
1090         * aarch64-dis.c: Likewise.
1091         * aarch64-gen.c: Likewise.
1092         * aarch64-opc.c: Likewise.
1093         * alpha-dis.c: Likewise.
1094         * i386-dis.c: Likewise.
1095         * nds32-asm.c: Likewise.
1096         * nfp-dis.c: Likewise.
1097         * visium-dis.c: Likewise.
1098
1099 2020-02-25  Claudiu Zissulescu <claziss@gmail.com>
1100
1101         * arc-regs.h (int_vector_base): Make it available for all ARC
1102         CPUs.
1103
1104 2020-02-20  Nelson Chu  <nelson.chu@sifive.com>
1105
1106         * riscv-dis.c (print_insn_args): Updated since the DECLARE_CSR is
1107         changed.
1108
1109 2020-02-19  Nelson Chu  <nelson.chu@sifive.com>
1110
1111         * riscv-opc.c (riscv_opcodes): Convert add/addi to the compressed
1112         c.mv/c.li if rs1 is zero.
1113
1114 2020-02-17  H.J. Lu  <hongjiu.lu@intel.com>
1115
1116         * i386-gen.c (cpu_flag_init): Replace CpuABM with
1117         CpuLZCNT|CpuPOPCNT.  Add CpuPOPCNT to CPU_SSE4_2_FLAGS.  Add
1118         CPU_POPCNT_FLAGS.
1119         (cpu_flags): Remove CpuABM.  Add CpuPOPCNT.
1120         * i386-opc.h (CpuABM): Removed.
1121         (CpuPOPCNT): New.
1122         (i386_cpu_flags): Remove cpuabm.  Add cpupopcnt.
1123         * i386-opc.tbl: Replace CpuABM|CpuSSE4_2 with CpuPOPCNT on
1124         popcnt.  Remove CpuABM from lzcnt.
1125         * i386-init.h: Regenerated.
1126         * i386-tbl.h: Likewise.
1127
1128 2020-02-17  Jan Beulich  <jbeulich@suse.com>
1129
1130         * i386-opc.tbl (vcvtsi2sd, vcvtsi2ss, vcvtusi2sd, vcvtusi2ss):
1131         Fold CpuNo64 and Cpu64 templates. Use VexLIG/EVexLIG and VexW0/
1132         VexW1 instead of open-coding them.
1133         * i386-tbl.h: Re-generate.
1134
1135 2020-02-17  Jan Beulich  <jbeulich@suse.com>
1136
1137         * i386-opc.tbl (AddrPrefixOpReg): Define.
1138         (monitor, invlpga, vmload, vmrun, vmsave, clzero, monitorx,
1139         umonitor, movdir64b, enqcmd, enqcmds): Fold Cpu64 and CpuNo64
1140         templates. Drop NoRex64.
1141         * i386-tbl.h: Re-generate.
1142
1143 2020-02-17  Jan Beulich  <jbeulich@suse.com>
1144
1145         PR gas/6518
1146         * i386-opc.tbl (vcvtpd2dq, vcvtpd2ps, vcvttpd2dq, vcvtpd2udq,
1147         vcvttpd2udq, vcvtqq2ps, vcvtuqq2ps): Split XMM/YMM source forms
1148         into Intel syntax instance (with Unpsecified) and AT&T one
1149         (without).
1150         (vcvtneps2bf16): Likewise, along with folding the two so far
1151         separate ones.
1152         * i386-tbl.h: Re-generate.
1153
1154 2020-02-16  H.J. Lu  <hongjiu.lu@intel.com>
1155
1156         * i386-gen.c (cpu_flag_init): Remove CPU_ANY_SSE3_FLAGS from
1157         CPU_ANY_SSE4A_FLAGS.
1158
1159 2020-02-17  Alan Modra  <amodra@gmail.com>
1160
1161         * i386-gen.c (cpu_flag_init): Correct last change.
1162
1163 2020-02-16  H.J. Lu  <hongjiu.lu@intel.com>
1164
1165         * i386-gen.c (cpu_flag_init): Add CPU_ANY_SSE4A_FLAGS.  Remove
1166         CPU_ANY_SSE4_FLAGS.
1167
1168 2020-02-14  H.J. Lu  <hongjiu.lu@intel.com>
1169
1170         * i386-opc.tbl (movsx): Remove Intel syntax comments.
1171         (movzx): Likewise.
1172
1173 2020-02-14  Jan Beulich  <jbeulich@suse.com>
1174
1175         PR gas/25438
1176         * i386-opc.tbl (movsx): Fold patterns. Also allow Reg32 as
1177         destination for Cpu64-only variant.
1178         (movzx): Fold patterns.
1179         * i386-tbl.h: Re-generate.
1180
1181 2020-02-13  Jan Beulich  <jbeulich@suse.com>
1182
1183         * i386-gen.c (cpu_flag_init): Move CpuSSE4a from
1184         CPU_ANY_SSE_FLAGS entry to CPU_ANY_SSE3_FLAGS one. Add
1185         CPU_ANY_SSE4_FLAGS entry.
1186         * i386-init.h: Re-generate.
1187
1188 2020-02-12  Jan Beulich  <jbeulich@suse.com>
1189
1190         * i386-opc.tbl (vfpclasspd, vfpclassps): Add Intel sytax form
1191         with Unspecified, making the present one AT&T syntax only.
1192         * i386-tbl.h: Re-generate.
1193
1194 2020-02-12  Jan Beulich  <jbeulich@suse.com>
1195
1196         * i386-opc.tbl (jmp): Fold CpuNo64 and Amd64 direct variants.
1197         * i386-tbl.h: Re-generate.
1198
1199 2020-02-12  Jan Beulich  <jbeulich@suse.com>
1200
1201         PR gas/24546
1202         * i386-dis.c (putop): Handle REX.W in '^' case for Intel64 mode.
1203         * i386-opc.tbl (lfs, lgs, lss, lcall, ljmp): Split into
1204         Amd64 and Intel64 templates.
1205         (call, jmp): Likewise for far indirect variants. Dro
1206         Unspecified.
1207         * i386-tbl.h: Re-generate.
1208
1209 2020-02-11  Jan Beulich  <jbeulich@suse.com>
1210
1211         * i386-gen.c (opcode_modifiers): Remove ShortForm entry.
1212         * i386-opc.h (ShortForm): Delete.
1213         (struct i386_opcode_modifier): Remove shortform field.
1214         * i386-opc.tbl (mov, movabs, push, pop, xchg, inc, dec, fld,
1215         fst, fstp, fxch, fcom, fcomp, fucom, fucomp, fadd, faddp, fsub,
1216         fsubp, fsubr, fsubrp, fmul, fmulp, fdiv, fdivp, fdivr, fdivrp,
1217         ffreep, bswap, fcmov*, fcomi, fcomip, fucomi, fucomip, movq):
1218         Drop ShortForm.
1219         * i386-tbl.h: Re-generate.
1220
1221 2020-02-11  Jan Beulich  <jbeulich@suse.com>
1222
1223         * i386-opc.tbl (fcomi, fucomi, fcomip, fcompi, fucomip,
1224         fucompi): Drop ShortForm from operand-less templates.
1225         * i386-tbl.h: Re-generate.
1226
1227 2020-02-11  Alan Modra  <amodra@gmail.com>
1228
1229         * cgen-ibld.in (extract_normal): Set *valuep on all return paths.
1230         * bpf-ibld.c, * epiphany-ibld.c, * fr30-ibld.c, * frv-ibld.c,
1231         * ip2k-ibld.c, * iq2000-ibld.c, * lm32-ibld.c, * m32c-ibld.c,
1232         * m32r-ibld.c, * mep-ibld.c, * mt-ibld.c, * or1k-ibld.c,
1233         * xc16x-ibld.c, * xstormy16-ibld.c: Regenerate.
1234
1235 2020-02-10  Matthew Malcomson  <matthew.malcomson@arm.com>
1236
1237         * arm-dis.c (print_insn_cde): Define 'V' parse character.
1238         (cde_opcodes): Add VCX* instructions.
1239
1240 2020-02-10  Stam Markianos-Wright  <stam.markianos-wright@arm.com>
1241             Matthew Malcomson  <matthew.malcomson@arm.com>
1242
1243         * arm-dis.c (struct cdeopcode32): New.
1244         (CDE_OPCODE): New macro.
1245         (cde_opcodes): New disassembly table.
1246         (regnames): New option to table.
1247         (cde_coprocs): New global variable.
1248         (print_insn_cde): New
1249         (print_insn_thumb32): Use print_insn_cde.
1250         (parse_arm_disassembler_options): Parse coprocN args.
1251
1252 2020-02-10  H.J. Lu  <hongjiu.lu@intel.com>
1253
1254         PR gas/25516
1255         * i386-gen.c (opcode_modifiers): Replace AMD64 and Intel64
1256         with ISA64.
1257         * i386-opc.h (AMD64): Removed.
1258         (Intel64): Likewose.
1259         (AMD64): New.
1260         (INTEL64): Likewise.
1261         (INTEL64ONLY): Likewise.
1262         (i386_opcode_modifier): Replace amd64 and intel64 with isa64.
1263         * i386-opc.tbl (Amd64): New.
1264         (Intel64): Likewise.
1265         (Intel64Only): Likewise.
1266         Replace AMD64 with Amd64.  Update sysenter/sysenter with
1267         Cpu64 and Intel64Only.  Remove AMD64 from sysenter/sysenter.
1268         * i386-tbl.h: Regenerated.
1269
1270 2020-02-07  Sergey Belyashov  <sergey.belyashov@gmail.com>
1271
1272         PR 25469
1273         * z80-dis.c: Add support for GBZ80 opcodes.
1274
1275 2020-02-04  Alan Modra  <amodra@gmail.com>
1276
1277         * d30v-dis.c (print_insn): Make "val" and "opnum" unsigned.
1278
1279 2020-02-03  Alan Modra  <amodra@gmail.com>
1280
1281         * m32c-ibld.c: Regenerate.
1282
1283 2020-02-01  Alan Modra  <amodra@gmail.com>
1284
1285         * frv-ibld.c: Regenerate.
1286
1287 2020-01-31  Jan Beulich  <jbeulich@suse.com>
1288
1289         * i386-dis.c (EXxmm_mdq, xmm_mdq_mode): Delete.
1290         (intel_operand_size, OP_EX): Drop xmm_mdq_mode case label.
1291         (OP_E_memory): Replace xmm_mdq_mode case label by
1292         vex_scalar_w_dq_mode one.
1293         * i386-dis-evex-prefix.h: Replace EXxmm_mdq by EXVexWdqScalar.
1294
1295 2020-01-31  Jan Beulich  <jbeulich@suse.com>
1296
1297         * i386-dis.c (EXVexWdq, vex_w_dq_mode): Delete.
1298         (vex_vsib_d_w_dq_mode, vex_vsib_q_w_dq_mode,
1299         vex_scalar_w_dq_mode): Don't refer to vex_w_dq_mode in comments.
1300         (intel_operand_size): Drop vex_w_dq_mode case label.
1301
1302 2020-01-31  Richard Sandiford  <richard.sandiford@arm.com>
1303
1304         * aarch64-tbl.h (aarch64_opcode): Set C_MAX_ELEM for SVE bfcvt.
1305         Remove C_SCAN_MOVPRFX for SVE bfcvtnt.
1306
1307 2020-01-30  Alan Modra  <amodra@gmail.com>
1308
1309         * m32c-ibld.c: Regenerate.
1310
1311 2020-01-30  Jose E. Marchesi  <jose.marchesi@oracle.com>
1312
1313         * bpf-opc.c: Regenerate.
1314
1315 2020-01-30  Jan Beulich  <jbeulich@suse.com>
1316
1317         * i386-dis.c (X86_64_C2, X86_64_C3): New enumerators.
1318         (dis386): Use them to replace C2/C3 table entries.
1319         (x86_64_table): Add X86_64_C2 and X86_64_C3 entries.
1320         * i386-opc.tbl (ret): Split Cpu64 entries into AMD64 and Intel64
1321         ones. Use Size64 instead of DefaultSize on Intel64 ones.
1322         * i386-tbl.h: Re-generate.
1323
1324 2020-01-30  Jan Beulich  <jbeulich@suse.com>
1325
1326         * i386-opc.tbl (call): Drop DefaultSize from Intel64 JumpDword
1327         forms.
1328         (fldenv, fnstenv, fstenv, fnsave, fsave, frstor): Drop
1329         DefaultSize.
1330         * i386-tbl.h: Re-generate.
1331
1332 2020-01-30  Alan Modra  <amodra@gmail.com>
1333
1334         * tic4x-dis.c (tic4x_dp): Make unsigned.
1335
1336 2020-01-27  H.J. Lu  <hongjiu.lu@intel.com>
1337             Jan Beulich  <jbeulich@suse.com>
1338
1339         PR binutils/25445
1340         * i386-dis.c (MOVSXD_Fixup): New function.
1341         (movsxd_mode): New enum.
1342         (x86_64_table): Use MOVSXD_Fixup and movsxd_mode on movsxd.
1343         (intel_operand_size): Handle movsxd_mode.
1344         (OP_E_register): Likewise.
1345         (OP_G): Likewise.
1346         * i386-opc.tbl: Remove Rex64 and allow 32-bit destination
1347         register on movsxd.  Add movsxd with 16-bit destination register
1348         for AMD64 and Intel64 ISAs.
1349         * i386-tbl.h: Regenerated.
1350
1351 2020-01-27  Tamar Christina  <tamar.christina@arm.com>
1352
1353         PR 25403
1354         * aarch64-tbl.h (struct aarch64_opcode): Re-order cfinv.
1355         * aarch64-asm-2.c: Regenerate
1356         * aarch64-dis-2.c: Likewise.
1357         * aarch64-opc-2.c: Likewise.
1358
1359 2020-01-21  Jan Beulich  <jbeulich@suse.com>
1360
1361         * i386-opc.tbl (sysret): Drop DefaultSize.
1362         * i386-tbl.h: Re-generate.
1363
1364 2020-01-21  Jan Beulich  <jbeulich@suse.com>
1365
1366         * i386-opc.tbl (vcvtneps2bf16x): Add Broadcast, Xmmword, and
1367         Dword.
1368         (vcvtneps2bf16y): Add Broadcast, Ymmword, and Dword.
1369         * i386-tbl.h: Re-generate.
1370
1371 2020-01-20  Nick Clifton  <nickc@redhat.com>
1372
1373         * po/de.po: Updated German translation.
1374         * po/pt_BR.po: Updated Brazilian Portuguese translation.
1375         * po/uk.po: Updated Ukranian translation.
1376
1377 2020-01-20  Alan Modra  <amodra@gmail.com>
1378
1379         * hppa-dis.c (fput_const): Remove useless cast.
1380
1381 2020-01-20  Alan Modra  <amodra@gmail.com>
1382
1383         * arm-dis.c (print_insn_arm): Wrap 'T' value.
1384
1385 2020-01-18  Nick Clifton  <nickc@redhat.com>
1386
1387         * configure: Regenerate.
1388         * po/opcodes.pot: Regenerate.
1389
1390 2020-01-18  Nick Clifton  <nickc@redhat.com>
1391
1392         Binutils 2.34 branch created.
1393
1394 2020-01-17  Christian Biesinger  <cbiesinger@google.com>
1395
1396         * opintl.h: Fix spelling error (seperate).
1397
1398 2020-01-17  H.J. Lu  <hongjiu.lu@intel.com>
1399
1400         * i386-opc.tbl: Add {vex} pseudo prefix.
1401         * i386-tbl.h: Regenerated.
1402
1403 2020-01-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1404
1405         PR 25376
1406         * opcodes/arm-dis.c (coprocessor_opcodes): Use CORE_HIGH for MVE bits.
1407         (neon_opcodes): Likewise.
1408         (select_arm_features): Make sure we enable MVE bits when selecting
1409         armv8.1-m.main.  Make sure we do not enable MVE bits when not selecting
1410         any architecture.
1411
1412 2020-01-16  Jan Beulich  <jbeulich@suse.com>
1413
1414         * i386-opc.tbl: Drop stale comment from XOP section.
1415
1416 2020-01-16  Jan Beulich  <jbeulich@suse.com>
1417
1418         * i386-opc.tbl (movq): Add VexWIG to SSE2AVX XMM->XMM forms.
1419         (extractps): Add VexWIG to SSE2AVX forms.
1420         * i386-tbl.h: Re-generate.
1421
1422 2020-01-16  Jan Beulich  <jbeulich@suse.com>
1423
1424         * i386-opc.tbl (pextrq, pinsrq): Drop IgnoreSize and Qword. Drop
1425         Size64 from and use VexW1 on SSE2AVX forms.
1426         (vpextrq, vpinsrq): Drop IgnoreSize and Qword. Drop Size64 from
1427         VEX-encoded forms. Add Cpu64 to EVEX-encoded forms. Use VexW1.
1428         * i386-tbl.h: Re-generate.
1429
1430 2020-01-15  Alan Modra  <amodra@gmail.com>
1431
1432         * tic4x-dis.c (tic4x_version): Make unsigned long.
1433         (optab, optab_special, registernames): New file scope vars.
1434         (tic4x_print_register): Set up registernames rather than
1435         malloc'd registertable.
1436         (tic4x_disassemble): Delete optable and optable_special.  Use
1437         optab and optab_special instead.  Throw away old optab,
1438         optab_special and registernames when info->mach changes.
1439
1440 2020-01-14  Sergey Belyashov  <sergey.belyashov@gmail.com>
1441
1442         PR 25377
1443         * z80-dis.c (suffix): Use .db instruction to generate double
1444         prefix.
1445
1446 2020-01-14  Alan Modra  <amodra@gmail.com>
1447
1448         * z8k-dis.c (unpack_instr): Formatting.  Cast unsigned short
1449         values to unsigned before shifting.
1450
1451 2020-01-13  Thomas Troeger  <tstroege@gmx.de>
1452
1453         * arm-dis.c (print_insn_arm): Fill in insn info fields for control
1454         flow instructions.
1455         (print_insn_thumb16, print_insn_thumb32): Likewise.
1456         (print_insn): Initialize the insn info.
1457         * i386-dis.c (print_insn): Initialize the insn info fields, and
1458         detect jumps.
1459
1460 2012-01-13  Claudiu Zissulescu <claziss@gmail.com>
1461
1462         * arc-opc.c (C_NE): Make it required.
1463
1464 2012-01-13  Claudiu Zissulescu <claziss@gmail.com>
1465
1466         * opcode/arc-dis.c (regnames): Correct ACCL/ACCH naming, fix typo
1467         reserved register name.
1468
1469 2020-01-13  Alan Modra  <amodra@gmail.com>
1470
1471         * ns32k-dis.c (Is_gen): Use strchr, add 'f'.
1472         (print_insn_ns32k): Adjust ioffset for 'f' index_offset.
1473
1474 2020-01-13  Alan Modra  <amodra@gmail.com>
1475
1476         * wasm32-dis.c (print_insn_wasm32): Localise variables.  Store
1477         result of wasm_read_leb128 in a uint64_t and check that bits
1478         are not lost when copying to other locals.  Use uint32_t for
1479         most locals.  Use PRId64 when printing int64_t.
1480
1481 2020-01-13  Alan Modra  <amodra@gmail.com>
1482
1483         * score-dis.c: Formatting.
1484         * score7-dis.c: Formatting.
1485
1486 2020-01-13  Alan Modra  <amodra@gmail.com>
1487
1488         * score-dis.c (print_insn_score48): Use unsigned variables for
1489         unsigned values.  Don't left shift negative values.
1490         (print_insn_score32): Likewise.
1491         * score7-dis.c (print_insn_score32, print_insn_score16): Likewise.
1492
1493 2020-01-13  Alan Modra  <amodra@gmail.com>
1494
1495         * tic4x-dis.c (tic4x_print_register): Remove dead code.
1496
1497 2020-01-13  Alan Modra  <amodra@gmail.com>
1498
1499         * fr30-ibld.c: Regenerate.
1500
1501 2020-01-13  Alan Modra  <amodra@gmail.com>
1502
1503         * xgate-dis.c (print_insn): Don't left shift signed value.
1504         (ripBits): Formatting, use 1u.
1505
1506 2020-01-10  Alan Modra  <amodra@gmail.com>
1507
1508         * tilepro-opc.c (parse_insn_tilepro): Make opval unsigned.
1509         * tilegx-opc.c (parse_insn_tilegx): Likewise.  Delete raw_opval.
1510
1511 2020-01-10  Alan Modra  <amodra@gmail.com>
1512
1513         * m10300-dis.c (disassemble): Move extraction of DREG, AREG, RREG,
1514         and XRREG value earlier to avoid a shift with negative exponent.
1515         * m10200-dis.c (disassemble): Similarly.
1516
1517 2020-01-09  Nick Clifton  <nickc@redhat.com>
1518
1519         PR 25224
1520         * z80-dis.c (ld_ii_ii): Use correct cast.
1521
1522 2020-01-03  Sergey Belyashov  <sergey.belyashov@gmail.com>
1523
1524         PR 25224
1525         * z80-dis.c (ld_ii_ii): Use character constant when checking
1526         opcode byte value.
1527
1528 2020-01-09  Jan Beulich  <jbeulich@suse.com>
1529
1530         * i386-dis.c (SEP_Fixup): New.
1531         (SEP): Define.
1532         (dis386_twobyte): Use it for sysenter/sysexit.
1533         (enum x86_64_isa): Change amd64 enumerator to value 1.
1534         (OP_J): Compare isa64 against intel64 instead of amd64.
1535         * i386-opc.tbl (sysenter, sysexit): Split into AMD64 and Intel64
1536         forms.
1537         * i386-tbl.h: Re-generate.
1538
1539 2020-01-08  Alan Modra  <amodra@gmail.com>
1540
1541         * z8k-dis.c: Include libiberty.h
1542         (instr_data_s): Make max_fetched unsigned.
1543         (z8k_lookup_instr): Make nibl_index and tabl_index unsigned.
1544         Don't exceed byte_info bounds.
1545         (output_instr): Make num_bytes unsigned.
1546         (unpack_instr): Likewise for nibl_count and loop.
1547         * z8kgen.c (gas <opcode_entry_type>): Make noperands, length and
1548         idx unsigned.
1549         * z8k-opc.h: Regenerate.
1550
1551 2020-01-07  Shahab Vahedi  <shahab@synopsys.com>
1552
1553         * arc-tbl.h (llock): Use 'LLOCK' as class.
1554         (llockd): Likewise.
1555         (scond): Use 'SCOND' as class.
1556         (scondd): Likewise.
1557         (llockd): Set data_size_mode to 'C_ZZ_D' which is 64-bit.
1558         (scondd): Likewise.
1559
1560 2020-01-06  Alan Modra  <amodra@gmail.com>
1561
1562         * m32c-ibld.c: Regenerate.
1563
1564 2020-01-06  Alan Modra  <amodra@gmail.com>
1565
1566         PR 25344
1567         * z80-dis.c (suffix): Don't use a local struct buffer copy.
1568         Peek at next byte to prevent recursion on repeated prefix bytes.
1569         Ensure uninitialised "mybuf" is not accessed.
1570         (print_insn_z80): Don't zero n_fetch and n_used here,..
1571         (print_insn_z80_buf): ..do it here instead.
1572
1573 2020-01-04  Alan Modra  <amodra@gmail.com>
1574
1575         * m32r-ibld.c: Regenerate.
1576
1577 2020-01-04  Alan Modra  <amodra@gmail.com>
1578
1579         * cr16-dis.c (cr16_match_opcode): Avoid shift left of signed value.
1580
1581 2020-01-04  Alan Modra  <amodra@gmail.com>
1582
1583         * crx-dis.c (match_opcode): Avoid shift left of signed value.
1584
1585 2020-01-04  Alan Modra  <amodra@gmail.com>
1586
1587         * d30v-dis.c (print_insn): Avoid signed overflow in left shift.
1588
1589 2020-01-03  Jan Beulich  <jbeulich@suse.com>
1590
1591         * aarch64-tbl.h (aarch64_opcode_table): Use
1592         SVE_ADDR_RX_LSL{1,2,3} for LD1RO{H,W,D}.
1593
1594 2020-01-03  Jan Beulich  <jbeulich@suse.com>
1595
1596         * aarch64-tbl.h (aarch64_opcode_table): Correct SIMD
1597         forms of SUDOT and USDOT.
1598
1599 2020-01-03  Jan Beulich  <jbeulich@suse.com>
1600
1601         * aarch64-tbl.h (aarch64_opcode_table): Drop 'i' from
1602         uzip{1,2}.
1603         * opcodes/aarch64-dis-2.c: Re-generate.
1604
1605 2020-01-03  Jan Beulich  <jbeulich@suse.com>
1606
1607         * aarch64-tbl.h (aarch64_opcode_table): Correct 64-bit
1608         FMMLA encoding.
1609         * opcodes/aarch64-dis-2.c: Re-generate.
1610
1611 2020-01-02  Sergey Belyashov  <sergey.belyashov@gmail.com>
1612
1613         * z80-dis.c: Add support for eZ80 and Z80 instructions.
1614
1615 2020-01-01  Alan Modra  <amodra@gmail.com>
1616
1617         Update year range in copyright notice of all files.
1618
1619 For older changes see ChangeLog-2019
1620 \f
1621 Copyright (C) 2020 Free Software Foundation, Inc.
1622
1623 Copying and distribution of this file, with or without modification,
1624 are permitted in any medium without royalty provided the copyright
1625 notice and this notice are preserved.
1626
1627 Local Variables:
1628 mode: change-log
1629 left-margin: 8
1630 fill-column: 74
1631 version-control: never
1632 End: