opcodes/ChangeLog

   1 2019-12-17  Alan Modra  <amodra@gmail.com>
   2
   3         * aarch64-opc.c (value_fit_signed_field_p): Avoid signed overflow.
   4         (value_fit_unsigned_field_p): Likewise.
   5         (aarch64_wide_constant_p): Likewise.
   6         (operand_general_constraint_met_p): Likewise.
   7         * aarch64-opc.h (aarch64_wide_constant_p): Update prototype.
   8
   9 2019-12-17  Alan Modra  <amodra@gmail.com>
  10
  11         * nds32-dis.c (nds32_mask_opcode): Avoid signed overflow.
  12         (print_insn_nds32): Use uint64_t for "given" and "given1".
  13
  14 2019-12-17  Alan Modra  <amodra@gmail.com>
  15
  16         * tic80-dis.c: Delete file.
  17         * tic80-opc.c: Delete file.
  18         * disassemble.c: Remove tic80 support.
  19         * disassemble.h: Likewise.
  20         * Makefile.am: Likewise.
  21         * configure.ac: Likewise.
  22         * Makefile.in: Regenerate.
  23         * configure: Regenerate.
  24         * po/POTFILES.in: Regenerate.
  25
  26 2019-12-17  Alan Modra  <amodra@gmail.com>
  27
  28         * bpf-ibld.c: Regenerate.
  29
  30 2019-12-16  Alan Modra  <amodra@gmail.com>
  31
  32         * aarch64-dis.c (sign_extend): Return uint64_t.  Rewrite without
  33         conditional.
  34         (aarch64_ext_imm): Avoid signed overflow.
  35
  36 2019-12-16  Alan Modra  <amodra@gmail.com>
  37
  38         * microblaze-dis.c (read_insn_microblaze): Avoid signed overflow.
  39
  40 2019-12-16  Alan Modra  <amodra@gmail.com>
  41
  42         * nios2-dis.c (nios2_print_insn_arg): Avoid signed overflow
  43
  44 2019-12-16  Alan Modra  <amodra@gmail.com>
  45
  46         * xstormy16-ibld.c: Regenerate.
  47
  48 2019-12-16  Alan Modra  <amodra@gmail.com>
  49
  50         * score-dis.c (print_insn_score16): Move rpush/rpop imm field
  51         value adjustment so that it doesn't affect reg field too.
  52
  53 2019-12-16  Alan Modra  <amodra@gmail.com>
  54
  55         * crx-dis.c (EXTRACT, SBM): Avoid signed overflow.
  56         (get_number_of_operands, getargtype, getbits, getregname),
  57         (getcopregname, getprocregname, gettrapstring, getcinvstring),
  58         (getregliststring, get_word_at_PC, get_words_at_PC, build_mask),
  59         (powerof2, match_opcode, make_instruction, print_arguments),
  60         (print_arg): Delete forward declarations, moving static to..
  61         (getregname, getcopregname, getregliststring): ..these definitions.
  62         (build_mask): Return unsigned int mask.
  63         (match_opcode): Use unsigned int vars.
  64
  65 2019-12-16  Alan Modra  <amodra@gmail.com>
  66
  67         * bfin-dis.c (fmtconst, fmtconst_val): Avoid signed overflow.
  68
  69 2019-12-16  Alan Modra  <amodra@gmail.com>
  70
  71         * nds32-dis.c (print_insn16, print_insn32): Remove forward decls.
  72         (struct objdump_disasm_info): Delete.
  73         (nds32_parse_audio_ext, nds32_parse_opcode): Cast result of
  74         N32_IMMS to unsigned before shifting left.
  75
  76 2019-12-16  Alan Modra  <amodra@gmail.com>
  77
  78         * moxie-dis.c (INST2OFFSET): Don't left shift a signed value.
  79         (print_insn_moxie): Remove unnecessary cast.
  80
  81 2019-12-12  Alan Modra  <amodra@gmail.com>
  82
  83         * csky-dis.c (csky_chars_to_number): Remove abort and unnecessary
  84         mask.
  85
  86 2019-12-11  Alan Modra  <amodra@gmail.com>
  87
  88         * arc-dis.c (BITS): Don't truncate high bits with shifts.
  89         * nios2-dis.c (nios2_print_insn_arg): Don't sign extend with shifts.
  90         * tic54x-dis.c (print_instruction): Likewise.
  91         * tilegx-opc.c (parse_insn_tilegx): Likewise.
  92         * tilepro-opc.c (parse_insn_tilepro): Likewise.
  93         * visium-dis.c (disassem_class0): Likewise.
  94         * pdp11-dis.c (sign_extend): Likewise.
  95         (SIGN_BITS): Delete.
  96         * epiphany-ibld.c: Regenerate.
  97         * lm32-ibld.c: Regenerate.
  98         * m32c-ibld.c: Regenerate.
  99
 100 2019-12-11  Alan Modra  <amodra@gmail.com>
 101
 102         * ns32k-dis.c (sign_extend): Correct last patch.
 103
 104 2019-12-11  Alan Modra  <amodra@gmail.com>
 105
 106         * vax-dis.c (NEXTLONG): Avoid signed overflow.
 107
 108 2019-12-11  Alan Modra  <amodra@gmail.com>
 109
 110         * v850-dis.c (get_operand_value): Use unsigned arithmetic.  Don't
 111         sign extend using shifts.
 112
 113 2019-12-11  Alan Modra  <amodra@gmail.com>
 114
 115         * tic6x-dis.c (tic6x_extract_32): Avoid signed overflow.
 116
 117 2019-12-11  Alan Modra  <amodra@gmail.com>
 118
 119         * tic4x-dis.c (tic4x_print_register): Formatting.  Don't segfault
 120         on NULL registertable entry.
 121         (tic4x_hash_opcode): Use unsigned arithmetic.
 122
 123 2019-12-11  Alan Modra  <amodra@gmail.com>
 124
 125         * s12z-opc.c (z_decode_signed_value): Avoid signed overflow.
 126
 127 2019-12-11  Alan Modra  <amodra@gmail.com>
 128
 129         * ns32k-dis.c (bit_extract): Use unsigned arithmetic.
 130         (bit_extract_simple, sign_extend): Likewise.
 131
 132 2019-12-11  Alan Modra  <amodra@gmail.com>
 133
 134         * nios2-dis.c (nios2_print_insn_arg): Use 1u << 31.
 135
 136 2019-12-11  Alan Modra  <amodra@gmail.com>
 137
 138         * moxie-dis.c (INST2OFFSET): Don't sign extend using shifts.
 139
 140 2019-12-11  Alan Modra  <amodra@gmail.com>
 141
 142         * m68k-dis.c (COERCE32): Cast value first.
 143         (NEXTLONG, NEXTULONG): Avoid signed overflow.
 144
 145 2019-12-11  Alan Modra  <amodra@gmail.com>
 146
 147         * h8300-dis.c (extract_immediate): Avoid signed overflow.
 148         (bfd_h8_disassemble): Likewise.
 149
 150 2019-12-11  Alan Modra  <amodra@gmail.com>
 151
 152         * d30v-dis.c (print_insn): Make opind unsigned.  Don't access
 153         past end of operands array.
 154
 155 2019-12-11  Alan Modra  <amodra@gmail.com>
 156
 157         * csky-dis.c (csky_chars_to_number): Rewrite.  Avoid signed
 158         overflow when collecting bytes of a number.
 159
 160 2019-12-11  Alan Modra  <amodra@gmail.com>
 161
 162         * cris-dis.c (print_with_operands): Avoid signed integer
 163         overflow when collecting bytes of a 32-bit integer.
 164
 165 2019-12-11  Alan Modra  <amodra@gmail.com>
 166
 167         * cr16-dis.c (EXTRACT, SBM): Rewrite.
 168         (cr16_match_opcode): Delete duplicate bcond test.
 169
 170 2019-12-11  Alan Modra  <amodra@gmail.com>
 171
 172         * bfin-dis.c (HOST_LONG_WORD_SIZE, XFIELD): Delete.
 173         (SIGNBIT): New.
 174         (MASKBITS, SIGNEXTEND): Rewrite.
 175         (fmtconst): Don't use ? expression now that SIGNEXTEND uses
 176         unsigned arithmetic, instead assign result of SIGNEXTEND back
 177         to x.
 178         (fmtconst_val): Use 1u in shift expression.
 179
 180 2019-12-11  Alan Modra  <amodra@gmail.com>
 181
 182         * arc-dis.c (find_format_from_table): Use ull constant when
 183         shifting by up to 32.
 184
 185 2019-12-11  Alan Modra  <amodra@gmail.com>
 186
 187         PR 25270
 188         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Return
 189         false when field is zero for sve_size_tsz_bhs.
 190
 191 2019-12-11  Alan Modra  <amodra@gmail.com>
 192
 193         * epiphany-ibld.c: Regenerate.
 194
 195 2019-12-10  Alan Modra  <amodra@gmail.com>
 196
 197         PR 24960
 198         * disassemble.c (disassemble_free_target): New function.
 199
 200 2019-12-10  Alan Modra  <amodra@gmail.com>
 201
 202         * cgen-dis.in (print_insn_@arch@): Replace insn_sets with private_data.
 203         * disassemble.c (disassemble_init_for_target): Likewise.
 204         * bpf-dis.c: Regenerate.
 205         * epiphany-dis.c: Regenerate.
 206         * fr30-dis.c: Regenerate.
 207         * frv-dis.c: Regenerate.
 208         * ip2k-dis.c: Regenerate.
 209         * iq2000-dis.c: Regenerate.
 210         * lm32-dis.c: Regenerate.
 211         * m32c-dis.c: Regenerate.
 212         * m32r-dis.c: Regenerate.
 213         * mep-dis.c: Regenerate.
 214         * mt-dis.c: Regenerate.
 215         * or1k-dis.c: Regenerate.
 216         * xc16x-dis.c: Regenerate.
 217         * xstormy16-dis.c: Regenerate.
 218
 219 2019-12-10  Alan Modra  <amodra@gmail.com>
 220
 221         * ppc-dis.c (private): Delete variable.
 222         (get_powerpc_dialect): Don't segfault on NULL info->private_data.
 223         (powerpc_init_dialect): Don't use global private.
 224
 225 2019-12-10  Alan Modra  <amodra@gmail.com>
 226
 227         * s12z-opc.c: Formatting.
 228
 229 2019-12-08  Alan Modra  <amodra@gmail.com>
 230
 231         * s12z-opc.c (exg_sex_discrim): Don't leak memory on invalid
 232         registers.
 233
 234 2019-12-05  Jan Beulich  <jbeulich@suse.com>
 235
 236         * aarch64-tbl.h (aarch64_feature_crypto,
 237         aarch64_feature_crypto_v8_2, CRYPTO, CRYPTO_V8_2, CRYP_INSN,
 238         CRYPTO_V8_2_INSN): Delete.
 239
 240 2019-12-05  Alan Modra  <amodra@gmail.com>
 241
 242         PR 25249
 243         * microblaze-dis.c (NUM_STRBUFS, STRBUF_SIZE): Define.
 244         (struct string_buf): New.
 245         (strbuf): New function.
 246         (get_field): Use strbuf rather than strdup of local temp.
 247         (get_field_imm, get_field_imm5, get_field_imm5_mbar): Likewise.
 248         (get_field_rfsl, get_field_imm15): Likewise.
 249         (get_field_rd, get_field_r1, get_field_r2): Update macros.
 250         (get_field_special): Likewise.  Don't strcpy spr.  Formatting.
 251         (print_insn_microblaze): Formatting.  Init and pass string_buf to
 252         get_field functions.
 253
 254 2019-12-04  Jan Beulich  <jbeulich@suse.com>
 255
 256         * i386-opc.tbl (lfs, lgs, lss): Drop No_qSuf.
 257         * i386-tbl.h: Re-generate.
 258
 259 2019-12-04  Jan Beulich  <jbeulich@suse.com>
 260
 261         * i386-dis.c (mod_table): Use Ev instead of Em for movdiri.
 262
 263 2019-12-04  Jan Beulich  <jbeulich@suse.com>
 264
 265         * i386-opc.tbl (push, pop): Drop DefaultSize from GPR-only
 266         forms.
 267         (xbegin): Drop DefaultSize.
 268         * i386-tbl.h: Re-generate.
 269
 270 2019-11-22  Mihail Ionescu  <mihail.ionescu@arm.com>
 271
 272         * opcodes/arm-dis.c (arm_opcodes, thumb32_opcodes):
 273         Change the coproc CRC conditions to use the extension
 274         feature set, second word, base on ARM_EXT2_CRC.
 275
 276 2019-11-14  Jan Beulich  <jbeulich@suse.com>
 277
 278         * i386-opc.tbl (syscall, sysret): Drop Cpu64 forms.
 279         * i386-tbl.h: Re-generate.
 280
 281 2019-11-14  Jan Beulich  <jbeulich@suse.com>
 282
 283         * i386-gen.c (opcode_modifiers): Remove JumpDword, JumpByte,
 284         JumpInterSegment, and JumpAbsolute entries.
 285         * i386-opc.h (JUMP, JUMP_DWORD, JUMP_BYTE, JUMP_INTERSEGMENT,
 286         JUMP_ABSOLUTE): Define.
 287         (struct i386_opcode_modifier): Extend jump field to 3 bits.
 288         Remove jumpdword, jumpbyte, jumpintersegment, and jumpabsolute
 289         fields.
 290         * i386-opc.tbl (JumpByte, JumpDword, JumpAbsolute,
 291         JumpInterSegment): Define.
 292         * i386-tbl.h: Re-generate.
 293
 294 2019-11-14  Jan Beulich  <jbeulich@suse.com>
 295
 296         * i386-gen.c (operand_type_init): Remove
 297         OPERAND_TYPE_JUMPABSOLUTE entry.
 298         (opcode_modifiers): Add JumpAbsolute entry.
 299         (operand_types): Remove JumpAbsolute entry.
 300         * i386-opc.h (JumpAbsolute): Move between enums.
 301         (struct i386_opcode_modifier): Add jumpabsolute field.
 302         (union i386_operand_type): Remove jumpabsolute field.
 303         * i386-opc.tbl (call, lcall, jmp, ljmp): Move JumpAbsolute.
 304         * i386-init.h, i386-tbl.h: Re-generate.
 305
 306 2019-11-14  Jan Beulich  <jbeulich@suse.com>
 307
 308         * i386-gen.c (opcode_modifiers): Add AnySize entry.
 309         (operand_types): Remove AnySize entry.
 310         * i386-opc.h (AnySize): Move between enums.
 311         (struct i386_opcode_modifier): Add anysize field.
 312         (OTUnused): Un-comment.
 313         (union i386_operand_type): Remove anysize field.
 314         * i386-opc.tbl (lea, invlpg, clflush, prefetchnta, prefetcht0,
 315         prefetcht1, prefetcht2, prefetchtw, bndmk, bndcl, bndcu, bndcn,
 316         bndstx, bndldx, prefetchwt1, clflushopt, clwb, cldemote): Move
 317         AnySize.
 318         * i386-tbl.h: Re-generate.
 319
 320 2019-11-12  Nelson Chu  <nelson.chu@sifive.com>
 321
 322         * riscv-opc.c (riscv_insn_types): Replace the INSN_CLASS_I with
 323         INSN_CLASS_F and the INSN_CLASS_C with INSN_CLASS_F_AND_C if we
 324         use the floating point register (FPR).
 325
 326 2019-11-12  Mihail Ionescu  <mihail.ionescu@arm.com>
 327
 328         * opcodes/arm-dis.c (mve_opcodes): Enable VMOV imm to vec with
 329         cmode 1101.
 330         (is_mve_encoding_conflict): Update cmode conflict checks for
 331         MVE_VMVN_IMM.
 332
 333 2019-11-12  Jan Beulich  <jbeulich@suse.com>
 334
 335         * i386-gen.c (operand_type_init): Remove OPERAND_TYPE_ESSEG
 336         entry.
 337         (operand_types): Remove EsSeg entry.
 338         (main): Replace stale use of OTMax.
 339         * i386-opc.h (IS_STRING_ES_OP0, IS_STRING_ES_OP1): Define.
 340         (struct i386_opcode_modifier): Expand isstring field to 2 bits.
 341         (EsSeg): Delete.
 342         (OTUnused): Comment out.
 343         (union i386_operand_type): Remove esseg field.
 344         * i386-opc.tbl (IsStringEsOp0, IsStringEsOp1): Define.
 345         (cmps, scmp, scas, ssca, cmpsd): Add IsStringEsOp0.
 346         (ins, movs, smov, movsd): Add IsStringEsOpOp1.
 347         (stos, ssto): Add IsStringEsOp0/IsStringEsOpOp1.
 348         * i386-init.h, i386-tbl.h: Re-generate.
 349
 350 2019-11-12  Jan Beulich  <jbeulich@suse.com>
 351
 352         * i386-gen.c (operand_instances): Add RegB entry.
 353         * i386-opc.h (enum operand_instance): Add RegB.
 354         * i386-opc.tbl (RegC, RegD, RegB): Define.
 355         (Acc, ShiftCount, InOutPortReg): Adjust definitions.
 356         (monitor, mwait, invlpga, skinit, vmload, vmrun, vmsave, clzero,
 357         monitorx, mwaitx): Drop ImmExt and convert encodings
 358         accordingly.
 359         * i386-reg.tbl (ecx, rcx): Add Instance=RegC.
 360         (edx, rdx): Add Instance=RegD.
 361         (ebx, rbx): Add Instance=RegB.
 362         * i386-tbl.h: Re-generate.
 363
 364 2019-11-12  Jan Beulich  <jbeulich@suse.com>
 365
 366         * i386-gen.c (operand_type_init): Adjust
 367         OPERAND_TYPE_INOUTPORTREG, OPERAND_TYPE_SHIFTCOUNT,
 368         OPERAND_TYPE_FLOATACC, OPERAND_TYPE_ACC8, OPERAND_TYPE_ACC16,
 369         OPERAND_TYPE_ACC32, and OPERAND_TYPE_ACC64 entries.
 370         (operand_instances): New.
 371         (operand_types): Drop InOutPortReg, ShiftCount, and Acc entries.
 372         (output_operand_type): New parameter "instance". Process it.
 373         (process_i386_operand_type): New local variable "instance".
 374         (main): Adjust static assertions.
 375         * i386-opc.h (INSTANCE_WIDTH): Define.
 376         (enum operand_instance): New.
 377         (Acc, InOutPortReg, ShiftCount): Replace by ClassInstance.
 378         (union i386_operand_type): Replace acc, inoutportreg, and
 379         shiftcount by instance.
 380         * i386-opc.tbl (Acc, InOutPortReg, ShiftCount): Define.
 381         * i386-reg.tbl (st, al, cl, ax, dx, eax, rax, xmm0, st(0)):
 382         Add Instance=.
 383         * i386-init.h, i386-tbl.h: Re-generate.
 384
 385 2019-11-11  Jan Beulich  <jbeulich@suse.com>
 386
 387         * aarch64-tbl.h (aarch64_opcode_table): Switch SVE2's
 388         smaxp/sminp entries' "tied_operand" field to 2.
 389
 390 2019-11-11  Jan Beulich  <jbeulich@suse.com>
 391
 392         * aarch64-opc.c (operand_general_constraint_met_p): Replace
 393         "index" local variable by that of the already existing "num".
 394
 395 2019-11-08  H.J. Lu  <hongjiu.lu@intel.com>
 396
 397         PR gas/25167
 398         * i386-opc.tbl: Remove IgnoreSize from cmpsd and movsd.
 399         * i386-tbl.h: Regenerated.
 400
 401 2019-11-08  Jan Beulich  <jbeulich@suse.com>
 402
 403         * i386-gen.c (operand_type_init): Add Class= to
 404         OPERAND_TYPE_REGMASK and OPERAND_TYPE_REGBND entries. Move up
 405         OPERAND_TYPE_REGBND entry.
 406         (operand_classes): Add RegMask and RegBND entries.
 407         (operand_types): Drop RegMask and RegBND entry.
 408         * i386-opc.h (enum operand_class): Add RegMask and RegBND.
 409         (RegMask, RegBND): Delete.
 410         (union i386_operand_type): Remove regmask and regbnd fields.
 411         * i386-opc.tbl (RegMask, RegBND): Define.
 412         * i386-reg.tbl: Replace RegMask by Class=RegMask and RegBND by
 413         Class=RegBND.
 414         * i386-init.h, i386-tbl.h: Re-generate.
 415
 416 2019-11-08  Jan Beulich  <jbeulich@suse.com>
 417
 418         * i386-gen.c (operand_type_init): Add Class= to
 419         OPERAND_TYPE_REGMMX, OPERAND_TYPE_REGXMM, OPERAND_TYPE_REGYMM, and
 420         OPERAND_TYPE_REGZMM entries.
 421         (operand_classes): Add RegMMX and RegSIMD entries.
 422         (operand_types): Drop RegMMX and RegSIMD entries.
 423         * i386-opc.h (enum operand_class): Add RegMMX and RegSIMD.
 424         (RegMMX, RegSIMD): Delete.
 425         (union i386_operand_type): Remove regmmx and regsimd fields.
 426         * i386-opc.tbl (RegMMX): Define.
 427         (RegXMM, RegYMM, RegZMM): Add Class=.
 428         * i386-reg.tbl: Replace RegMMX by Class=RegMMX and RegSIMD by
 429         Class=RegSIMD.
 430         * i386-init.h, i386-tbl.h: Re-generate.
 431
 432 2019-11-08  Jan Beulich  <jbeulich@suse.com>
 433
 434         * i386-gen.c (operand_type_init): Add Class= to
 435         OPERAND_TYPE_CONTROL, OPERAND_TYPE_TEST, and OPERAND_TYPE_DEBUG
 436         entries.
 437         (operand_classes): Add RegCR, RegDR, and RegTR entries.
 438         (operand_types): Drop Control, Debug, and Test entries.
 439         * i386-opc.h (enum operand_class): Add RegCR, RegDR, and RegTR.
 440         (Control, Debug, Test): Delete.
 441         (union i386_operand_type): Remove control, debug, and test
 442         fields.
 443         * i386-opc.tbl (Control, Debug, Test): Define.
 444         * i386-reg.tbl: Replace Control by Class=RegCR, Debug by
 445         Class=RegDR, and Test by Class=RegTR.
 446         * i386-init.h, i386-tbl.h: Re-generate.
 447
 448 2019-11-08  Jan Beulich  <jbeulich@suse.com>
 449
 450         * i386-gen.c (operand_type_init): Add Class= to
 451         OPERAND_TYPE_SREG entry.
 452         (operand_classes): Add SReg entry.
 453         (operand_types): Drop SReg entry.
 454         * i386-opc.h (enum operand_class): Add SReg.
 455         (SReg): Delete.
 456         (union i386_operand_type): Remove sreg field.
 457         * i386-opc.tbl (SReg): Define.
 458         * i386-reg.tbl: Replace SReg by Class=SReg.
 459         * i386-init.h, i386-tbl.h: Re-generate.
 460
 461 2019-11-08  Jan Beulich  <jbeulich@suse.com>
 462
 463         * i386-gen.c (operand_type_init): Add Class=. New
 464         OPERAND_TYPE_ANYIMM entry.
 465         (operand_classes): New.
 466         (operand_types): Drop Reg entry.
 467         (output_operand_type): New parameter "class". Process it.
 468         (process_i386_operand_type): New local variable "class".
 469         (main): Adjust static assertions.
 470         * i386-opc.h (CLASS_WIDTH): Define.
 471         (enum operand_class): New.
 472         (Reg): Replace by Class. Adjust comment.
 473         (union i386_operand_type): Replace reg by class.
 474         * i386-opc.tbl (Reg8, Reg16, Reg32, Reg64, FloatReg): Add
 475         Class=.
 476         * i386-reg.tbl: Replace Reg by Class=Reg.
 477         * i386-init.h: Re-generate.
 478
 479 2019-11-07  Mihail Ionescu  <mihail.ionescu@arm.com>
 480
 481         * opcodes/aarch64-tbl.h (V8_6_INSN): New macro for v8.6 instructions.
 482         (aarch64_opcode_table): Add data gathering hint mnemonic.
 483         * opcodes/aarch64-dis-2.c: Account for new instruction.
 484
 485 2019-11-07  Mihail Ionescu  <mihail.ionescu@arm.com>
 486
 487         * arm-dis.c (neon_opcodes): Add i8mm SIMD instructions.
 488
 489
 490 2019-11-07  Mihail Ionescu  <mihail.ionescu@arm.com>
 491
 492         * aarch64-tbl.h (aarch64_feature_i8mm_sve, aarch64_feature_f32mm_sve,
 493         aarch64_feature_f64mm_sve, aarch64_feature_i8mm, aarch64_feature_f32mm,
 494         aarch64_feature_f64mm): New feature sets.
 495         (INT8MATMUL_INSN, F64MATMUL_SVE_INSN, F64MATMUL_INSN,
 496         F32MATMUL_SVE_INSN, F32MATMUL_INSN): New macros to define matrix multiply
 497         instructions.
 498         (I8MM_SVE, F32MM_SVE, F64MM_SVE, I8MM, F32MM, F64MM): New feature set
 499         macros.
 500         (QL_MMLA64, OP_SVE_SBB): New qualifiers.
 501         (OP_SVE_QQQ): New qualifier.
 502         (INT8MATMUL_SVE_INSNC, F64MATMUL_SVE_INSNC,
 503         F32MATMUL_SVE_INSNC): New feature set for bfloat16 instructions to support
 504         the movprfx constraint.
 505         (aarch64_opcode_table): Support for SVE_ADDR_RI_S4x32.
 506         (aarch64_opcode_table): Define new instructions smmla,
 507         ummla, usmmla, usdot, sudot, fmmla, ld1rob, ld1roh, ld1row, ld1rod,
 508         uzip{1/2}, trn{1/2}.
 509         * aarch64-opc.c (operand_general_constraint_met_p): Handle
 510         AARCH64_OPND_SVE_ADDR_RI_S4x32.
 511         (aarch64_print_operand): Handle AARCH64_OPND_SVE_ADDR_RI_S4x32.
 512         * aarch64-dis-2.c (aarch64_opcode_lookup_1, aarch64_find_next_opcode):
 513         Account for new instructions.
 514         * opcodes/aarch64-asm-2.c (aarch64_insert_operand): Support the new
 515         S4x32 operand.
 516         * aarch64-opc-2.c (aarch64_operands): Support the new S4x32 operand.
 517
 518 2019-11-07  Mihail Ionescu  <mihail.ionescu@arm.com>
 519 2019-11-07  Matthew Malcomson  <matthew.malcomson@arm.com>
 520
 521         * arm-dis.c (select_arm_features): Update bfd_march_arm_8 with
 522         Armv8.6-A.
 523         (coprocessor_opcodes): Add bfloat16 vcvt{t,b}.
 524         (neon_opcodes): Add bfloat SIMD instructions.
 525         (print_insn_coprocessor): Add new control character %b to print
 526         condition code without checking cp_num.
 527         (print_insn_neon): Account for BFloat16 instructions that have no
 528         special top-byte handling.
 529
 530 2019-11-07  Mihail Ionescu  <mihail.ionescu@arm.com>
 531 2019-11-07  Matthew Malcomson  <matthew.malcomson@arm.com>
 532
 533         * arm-dis.c (print_insn_coprocessor,
 534         print_insn_generic_coprocessor): Create wrapper functions around
 535         the implementation of the print_insn_coprocessor control codes.
 536         (print_insn_coprocessor_1): Original print_insn_coprocessor
 537         function that now takes which array to look at as an argument.
 538         (print_insn_arm): Use both print_insn_coprocessor and
 539         print_insn_generic_coprocessor.
 540         (print_insn_thumb32): As above.
 541
 542 2019-11-07  Mihail Ionescu  <mihail.ionescu@arm.com>
 543 2019-11-07  Matthew Malcomson  <matthew.malcomson@arm.com>
 544
 545         * aarch64-asm.c (aarch64_ins_reglane): Use AARCH64_OPND_QLF_S_2H
 546         in reglane special case.
 547         * aarch64-dis-2.c (aarch64_opcode_lookup_1,
 548         aarch64_find_next_opcode): Account for new instructions.
 549         * aarch64-dis.c (aarch64_ext_reglane): Use AARCH64_OPND_QLF_S_2H
 550         in reglane special case.
 551         * aarch64-opc.c (struct operand_qualifier_data): Add data for
 552         new AARCH64_OPND_QLF_S_2H qualifier.
 553         * aarch64-tbl.h (QL_BFDOT QL_BFDOT64, QL_BFDOT64I, QL_BFMMLA2,
 554         QL_BFCVT64, QL_BFCVTN64, QL_BFCVTN2_64): New qualifiers.
 555         (aarch64_feature_bfloat16, aarch64_feature_bfloat16_sve): New feature
 556         sets.
 557         (BFLOAT_SVE, BFLOAT): New feature set macros.
 558         (BFLOAT_SVE_INSN, BFLOAT_INSN): New macros to define BFloat16
 559         instructions.
 560         (aarch64_opcode_table): Define new instructions bfdot,
 561         bfmmla, bfcvt, bfcvtnt, bfdot, bfdot, bfcvtn, bfmlal[b/t]
 562         bfcvtn2, bfcvt.
 563
 564 2019-11-07  Mihail Ionescu  <mihail.ionescu@arm.com>
 565 2019-11-07  Matthew Malcomson  <matthew.malcomson@arm.com>
 566
 567         * aarch64-tbl.h (ARMV8_6): New macro.
 568
 569 2019-11-07  Jan Beulich  <jbeulich@suse.com>
 570
 571         * i386-dis.c (prefix_table): Add mcommit.
 572         (rm_table): Add rdpru.
 573         * i386-gen.c (cpu_flag_init): Adjust CPU_ZNVER2_FLAGS entry. Add
 574         CPU_RDPRU_FLAGS and CPU_MCOMMIT_FLAGS entries.
 575         (cpu_flags): Add CpuRDPRU and CpuMCOMMIT entries.
 576         * i386-opc.h (CpuRDPRU, CpuMCOMMIT): New.
 577         (union i386_cpu_flags): Add cpurdpru and cpumcommit fields.
 578         * i386-opc.tbl (mcommit, rdpru): New.
 579         * i386-init.h, i386-tbl.h: Re-generate.
 580
 581 2019-11-07  Jan Beulich  <jbeulich@suse.com>
 582
 583         * i386-dis.c (OP_Mwait): Drop local variable "names", use
 584         "names32" instead.
 585         (OP_Monitor): Drop local variable "op1_names", re-purpose
 586         "names" for it instead, and replace former "names" uses by
 587         "names32" ones.
 588
 589 2019-11-07  Jan Beulich  <jbeulich@suse.com>
 590
 591         PR/gas 25167
 592         * opcodes/i386-opc.tbl (movsd, cmpsd): Drop IgnoreSize from
 593         operand-less forms.
 594         * opcodes/i386-tbl.h: Re-generate.
 595
 596 2019-11-05  Jan Beulich  <jbeulich@suse.com>
 597
 598         * i386-dis.c (OP_Mwaitx): Delete.
 599         (prefix_table): Use OP_Mwait for mwaitx entry.
 600         (OP_Mwait): Also handle mwaitx.
 601
 602 2019-11-05  Jan Beulich  <jbeulich@suse.com>
 603
 604         * i386-dis.c (PREFIX_0F01_REG_7_MOD_3_RM_2,
 605         PREFIX_0F01_REG_7_MOD_3_RM_3): New.
 606         (prefix_table): Add respective entries.
 607         (rm_table): Link to those entries.
 608
 609 2019-11-05  Jan Beulich  <jbeulich@suse.com>
 610
 611         * i386-dis.c (REG_0F1C_MOD_0): Rename to ...
 612         (REG_0F1C_P_0_MOD_0): ... this.
 613         (REG_0F1E_MOD_3): Rename to ...
 614         (REG_0F1E_P_1_MOD_3): ... this.
 615         (RM_0F01_REG_5): Rename to ...
 616         (RM_0F01_REG_5_MOD_3): ... this.
 617         (RM_0F01_REG_7): Rename to ...
 618         (RM_0F01_REG_7_MOD_3): ... this.
 619         (RM_0F1E_MOD_3_REG_7): Rename to ...
 620         (RM_0F1E_P_1_MOD_3_REG_7): ... this.
 621         (RM_0FAE_REG_6): Rename to ...
 622         (RM_0FAE_REG_6_MOD_3_P_0): ... this.
 623         (RM_0FAE_REG_7): Rename to ...
 624         (RM_0FAE_REG_7_MOD_3): ... this.
 625         (PREFIX_MOD_0_0F01_REG_5): Rename to ...
 626         (PREFIX_0F01_REG_5_MOD_0): ... this.
 627         (PREFIX_MOD_3_0F01_REG_5_RM_0): Rename to ...
 628         (PREFIX_0F01_REG_5_MOD_3_RM_0): ... this.
 629         (PREFIX_MOD_3_0F01_REG_5_RM_2): Rename to ...
 630         (PREFIX_0F01_REG_5_MOD_3_RM_2): ... this.
 631         (PREFIX_0FAE_REG_0): Rename to ...
 632         (PREFIX_0FAE_REG_0_MOD_3): ... this.
 633         (PREFIX_0FAE_REG_1): Rename to ...
 634         (PREFIX_0FAE_REG_1_MOD_3): ... this.
 635         (PREFIX_0FAE_REG_2): Rename to ...
 636         (PREFIX_0FAE_REG_2_MOD_3): ... this.
 637         (PREFIX_0FAE_REG_3): Rename to ...
 638         (PREFIX_0FAE_REG_3_MOD_3): ... this.
 639         (PREFIX_MOD_0_0FAE_REG_4): Rename to ...
 640         (PREFIX_0FAE_REG_4_MOD_0): ... this.
 641         (PREFIX_MOD_3_0FAE_REG_4): Rename to ...
 642         (PREFIX_0FAE_REG_4_MOD_3): ... this.
 643         (PREFIX_MOD_0_0FAE_REG_5): Rename to ...
 644         (PREFIX_0FAE_REG_5_MOD_0): ... this.
 645         (PREFIX_MOD_3_0FAE_REG_5): Rename to ...
 646         (PREFIX_0FAE_REG_5_MOD_3): ... this.
 647         (PREFIX_MOD_0_0FAE_REG_6): Rename to ...
 648         (PREFIX_0FAE_REG_6_MOD_0): ... this.
 649         (PREFIX_MOD_1_0FAE_REG_6): Rename to ...
 650         (PREFIX_0FAE_REG_6_MOD_3): ... this.
 651         (PREFIX_0FAE_REG_7): Rename to ...
 652         (PREFIX_0FAE_REG_7_MOD_0): ... this.
 653         (PREFIX_MOD_0_0FC3): Rename to ...
 654         (PREFIX_0FC3_MOD_0): ... this.
 655         (PREFIX_MOD_0_0FC7_REG_6): Rename to ...
 656         (PREFIX_0FC7_REG_6_MOD_0): ... this.
 657         (PREFIX_MOD_3_0FC7_REG_6): Rename to ...
 658         (PREFIX_0FC7_REG_6_MOD_3): ... this.
 659         (PREFIX_MOD_3_0FC7_REG_7): Rename to ...
 660         (PREFIX_0FC7_REG_7_MOD_3): ... this.
 661         (reg_table, prefix_table, mod_table, rm_table): Adjust
 662         accordingly.
 663
 664 2019-11-04  Nick Clifton  <nickc@redhat.com>
 665
 666         * v850-dis.c (get_v850_sreg_name): New function.  Returns the name
 667         of a v850 system register.  Move the v850_sreg_names array into
 668         this function.
 669         (get_v850_reg_name): Likewise for ordinary register names.
 670         (get_v850_vreg_name): Likewise for vector register names.
 671         (get_v850_cc_name): Likewise for condition codes.
 672         * get_v850_float_cc_name): Likewise for floating point condition
 673         codes.
 674         (get_v850_cacheop_name): Likewise for cache-ops.
 675         (get_v850_prefop_name): Likewise for pref-ops.
 676         (disassemble): Use the new accessor functions.
 677
 678 2019-10-30  Delia Burduv   <delia.burduv@arm.com>
 679
 680         * aarch64-opc.c (print_immediate_offset_address): Don't print the
 681         immediate for the writeback form of ldraa/ldrab if it is 0.
 682         * aarch64-tbl.h: Updated the documentation for ADDR_SIMM10.
 683         * aarch64-opc-2.c: Regenerated.
 684
 685 2019-10-30  Jan Beulich  <jbeulich@suse.com>
 686
 687         * i386-gen.c (operand_type_shorthands): Delete.
 688         (operand_type_init): Expand previous shorthands.
 689         (set_bitfield_from_shorthand): Rename back to ...
 690         (set_bitfield_from_cpu_flag_init): ... this.  Drop processing
 691         of operand_type_init[].
 692         (set_bitfield): Adjust call to the above function.
 693         * i386-opc.tbl (Reg8, Reg16, Reg32, Reg64, FloatAcc, FloatReg,
 694         RegXMM, RegYMM, RegZMM): Define.
 695         * i386-reg.tbl: Expand prior shorthands.
 696
 697 2019-10-30  Jan Beulich  <jbeulich@suse.com>
 698
 699         * i386-gen.c (output_i386_opcode): Change order of fields
 700         emitted to output.
 701         * i386-opc.h (struct insn_template): Move operands field.
 702         Convert extension_opcode field to unsigned short.
 703         * i386-tbl.h: Re-generate.
 704
 705 2019-10-30  Jan Beulich  <jbeulich@suse.com>
 706
 707         * i386-gen.c (process_i386_opcode_modifier): Report bogus uses
 708         of W.
 709         * i386-opc.h (W): Extend comment.
 710         * i386-opc.tbl (mov, movabs, movq): Drop W and adjust opcodes of
 711         general purpose variants not allowing for byte operands.
 712         * i386-tbl.h: Re-generate.
 713
 714 2019-10-29  Nick Clifton  <nickc@redhat.com>
 715
 716         * tic30-dis.c (print_branch): Correct size of operand array.
 717
 718 2019-10-29  Nick Clifton  <nickc@redhat.com>
 719
 720         * d30v-dis.c (print_insn): Check that operand index is valid
 721         before attempting to access the operands array.
 722
 723 2019-10-29  Nick Clifton  <nickc@redhat.com>
 724
 725         * ia64-opc.c (locate_opcode_ent): Prevent a negative shift when
 726         locating the bit to be tested.
 727
 728 2019-10-29  Nick Clifton  <nickc@redhat.com>
 729
 730         * s12z-dis.c (opr_emit_disassembly): Check for illegal register
 731         values.
 732         (shift_size_table): Use a fixed size defined as S12Z_N_SIZES.
 733         (print_insn_s12z):  Check for illegal size values.
 734
 735 2019-10-28  Nick Clifton  <nickc@redhat.com>
 736
 737         * csky-dis.c (csky_chars_to_number): Check for a negative
 738         count. Use an unsigned integer to construct the return value.
 739
 740 2019-10-28  Nick Clifton  <nickc@redhat.com>
 741
 742         * tic30-dis.c (OPERAND_BUFFER_LEN): Define.  Use as length of
 743         operand buffer.  Set value to 15 not 13.
 744         (get_register_operand): Use OPERAND_BUFFER_LEN.
 745         (get_indirect_operand): Likewise.
 746         (print_two_operand): Likewise.
 747         (print_three_operand): Likewise.
 748         (print_oar_insn): Likewise.
 749
 750 2019-10-28  Nick Clifton  <nickc@redhat.com>
 751
 752         * ns32k-dis.c (bit_extract): Add sanitiy check of parameters.
 753         (bit_extract_simple): Likewise.
 754         (bit_copy): Likewise.
 755         (pirnt_insn_ns32k): Ensure that uninitialised elements in the
 756         index_offset array are not accessed.
 757
 758 2019-10-28  Nick Clifton  <nickc@redhat.com>
 759
 760         * xgate-dis.c (print_insn): Fix decoding of the XGATE_OP_DYA
 761         operand.
 762
 763 2019-10-25  Nick Clifton  <nickc@redhat.com>
 764
 765         * rx-dis.c (print_insn_rx): Use parenthesis to ensure correct
 766         access to opcodes.op array element.
 767
 768 2019-10-23  Nick Clifton  <nickc@redhat.com>
 769
 770         * rx-dis.c (get_register_name): Fix spelling typo in error
 771         message.
 772         (get_condition_name, get_flag_name, get_double_register_name)
 773         (get_double_register_high_name, get_double_register_low_name)
 774         (get_double_control_register_name, get_double_condition_name)
 775         (get_opsize_name, get_size_name): Likewise.
 776
 777 2019-10-22  Nick Clifton  <nickc@redhat.com>
 778
 779         * rx-dis.c (get_size_name): New function.  Provides safe
 780         access to name array.
 781         (get_opsize_name): Likewise.
 782         (print_insn_rx): Use the accessor functions.
 783
 784 2019-10-16  Nick Clifton  <nickc@redhat.com>
 785
 786         * rx-dis.c (get_register_name): New function.  Provides safe
 787         access to name array.
 788         (get_condition_name, get_flag_name, get_double_register_name)
 789         (get_double_register_high_name, get_double_register_low_name)
 790         (get_double_control_register_name, get_double_condition_name):
 791         Likewise.
 792         (print_insn_rx): Use the accessor functions.
 793
 794 2019-10-09  Nick Clifton  <nickc@redhat.com>
 795
 796         PR 25041
 797         * avr-dis.c (avr_operand): Fix construction of address for lds/sts
 798         instructions.
 799
 800 2019-10-07  Jan Beulich  <jbeulich@suse.com>
 801
 802         * opcodes/i386-opc.tbl (movsd): Add Dword and IgnoreSize.
 803         (cmpsd): Likewise. Move EsSeg to other operand.
 804         * opcodes/i386-tbl.h: Re-generate.
 805
 806 2019-09-23  Alan Modra  <amodra@gmail.com>
 807
 808         * m68k-dis.c: Include cpu-m68k.h
 809
 810 2019-09-23  Alan Modra  <amodra@gmail.com>
 811
 812         * mips-dis.c: Include elfxx-mips.h.  Move "elf-bfd.h" and
 813         "elf/mips.h" earlier.
 814
 815 2018-09-20  Jan Beulich  <jbeulich@suse.com>
 816
 817         PR gas/25012
 818         * i386-opc.tbl (push, pop): Re-instate distinct Cpu64 templates
 819         with SReg operand.
 820         * i386-tbl.h: Re-generate.
 821
 822 2019-09-18  Alan Modra  <amodra@gmail.com>
 823
 824         * arc-ext.c: Update throughout for bfd section macro changes.
 825
 826 2019-09-18  Simon Marchi  <simon.marchi@polymtl.ca>
 827
 828         * Makefile.in: Re-generate.
 829         * configure: Re-generate.
 830
 831 2019-09-17  Maxim Blinov  <maxim.blinov@embecosm.com>
 832
 833         * riscv-opc.c (riscv_opcodes): Change subset field
 834         to insn_class field for all instructions.
 835         (riscv_insn_types): Likewise.
 836
 837 2019-09-16  Phil Blundell  <pb@pbcl.net>
 838
 839         * configure: Regenerated.
 840
 841 2019-09-10  Miod Vallat  <miod@online.fr>
 842
 843         PR 24982
 844         * m68k-opc.c: Correct aliases for tdivsl and tdivul.
 845
 846 2019-09-09  Phil Blundell  <pb@pbcl.net>
 847
 848         binutils 2.33 branch created.
 849
 850 2019-09-03  Nick Clifton  <nickc@redhat.com>
 851
 852         PR 24961
 853         * tic30-dis.c (get_indirect_operand): Check for bufcnt being
 854         greater than zero before indexing via (bufcnt -1).
 855
 856 2019-09-03  Nick Clifton  <nickc@redhat.com>
 857
 858         PR 24958
 859         * mmix-dis.c (MAX_REG_NAME_LEN): Define.
 860         (MAX_SPEC_REG_NAME_LEN): Define.
 861         (struct mmix_dis_info): Use defined constants for array lengths.
 862         (get_reg_name): New function.
 863         (get_sprec_reg_name): New function.
 864         (print_insn_mmix): Use new functions.
 865
 866 2019-08-27  Srinath Parvathaneni  <srinath.parvathaneni@arm.com>
 867
 868         * arm-dis.c (mve_opcodes): Add entry for MVE_VMOV_VEC_TO_VEC.
 869         (is_mve_undefined): Add case for MVE_VMOV_VEC_TO_VEC.
 870         (print_insn_mve): Add condition to check Qm==Qn of VORR instruction.
 871
 872 2019-08-22  Kyrylo Tkachov <kyrylo.tkachov@arm.com>
 873
 874         * aarch64-opc.c (aarch64_sys_regs): Update encoding of tfsre0_el1,
 875         tfsr_el1, tfsr_el2, tfsr_el3, tfsr_el12.
 876         (aarch64_sys_reg_supported_p): Update checks for the above.
 877
 878 2019-08-12  Srinath Parvathaneni  <srinath.parvathaneni@arm.com>
 879
 880         * arm-dis.c (struct mopcode32 mve_opcodes): Modify the mask for
 881         cases MVE_SQRSHRL and MVE_UQRSHLL.
 882         (print_insn_mve): Add case for specifier 'k' to check
 883         specific bit of the instruction.
 884
 885 2019-08-07  Phillipe Antoine  <p.antoine@catenacyber.fr>
 886
 887         PR 24854
 888         * arc-dis.c (arc_insn_length): Return 0 rather than aborting when
 889         encountering an unknown machine type.
 890         (print_insn_arc): Handle arc_insn_length returning 0.  In error
 891         cases return -1 rather than calling abort.
 892
 893 2019-08-07  Jan Beulich  <jbeulich@suse.com>
 894
 895         * i386-opc.tbl (fld, fstp): Drop FloatMF from extended forms.
 896         (fldcw, fnstcw, fstcw, fnstsw, fstsw): Replace FloatMF by
 897         IgnoreSize.
 898         * i386-tbl.h: Re-generate.
 899
 900 2019-08-05  Barnaby Wilks  <barnaby.wilks@arm.com>
 901
 902         * arm-dis.c: Only accept signed variants of VQ(R)DMLAH and VQ(R)DMLASH
 903         instructions.
 904
 905 2019-07-30  Mel Chen <mel.chen@sifive.com>
 906
 907         * riscv-opc.c (riscv_opcodes): Set frsr, fssr, frcsr, fscsr, frrm,
 908         fsrm, fsrmi, frflags, fsflags, fsflagsi to alias instructions.
 909
 910         * riscv-opc.c (riscv_opcodes): Adjust order of frsr, frcsr, fssr,
 911         fscsr.
 912
 913 2019-07-24  Claudiu Zissulescu  <claziss@synopsys.com>
 914
 915         * arc-dis.c (skip_this_opcode): Check also for 0x07 major opcodes,
 916         and MPY class instructions.
 917         (parse_option): Add nps400 option.
 918         (print_arc_disassembler_options): Add nps400 info.
 919
 920 2019-07-24  Claudiu Zissulescu  <claziss@synopsys.com>
 921
 922         * arc-ext-tbl.h (bspeek): Remove it, added to main table.
 923         (bspop): Likewise.
 924         (modapp): Likewise.
 925         * arc-opc.c (RAD_CHK): Add.
 926         * arc-tbl.h: Regenerate.
 927
 928 2019-07-23  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
 929
 930         * aarch64-opc.c (aarch64_sys_regs): Add gmid_el1 entry.
 931         (aarch64_sys_reg_supported_p): Handle gmid_el1 encoding.
 932
 933 2019-07-22  Barnaby Wilks  <barnaby.wilks@arm.com>
 934
 935         * arm-dis.c (is_mve_unpredictable): Stop marking some MVE
 936         instructions as UNPREDICTABLE.
 937
 938 2019-07-19  Jose E. Marchesi  <jose.marchesi@oracle.com>
 939
 940         * bpf-desc.c: Regenerated.
 941
 942 2019-07-17  Jan Beulich  <jbeulich@suse.com>
 943
 944         * i386-gen.c (static_assert): Define.
 945         (main): Use it.
 946         * i386-opc.h (Opcode_Modifier_Max): Rename to ...
 947         (Opcode_Modifier_Num): ... this.
 948         (Mem): Delete.
 949
 950 2019-07-16  Jan Beulich  <jbeulich@suse.com>
 951
 952         * i386-gen.c (operand_types): Move RegMem ...
 953         (opcode_modifiers): ... here.
 954         * i386-opc.h (RegMem): Move to opcode modifer enum.
 955         (union i386_operand_type): Move regmem field ...
 956         (struct i386_opcode_modifier): ... here.
 957         * i386-opc.tbl (RegMem): Define.
 958         (mov, movq): Move RegMem on segment, control, debug, and test
 959         register flavors.
 960         (pextrb): Move RegMem on register only flavors. Add IgnoreSize
 961         to non-SSE2AVX flavor.
 962         (extractps, pextrw, vcvtps2ph, vextractps, vpextrb, vpextrw):
 963         Move RegMem on register only flavors. Drop IgnoreSize from
 964         legacy encoding flavors.
 965         (movss, movsd, vmovss, vmovsd): Drop RegMem from register only
 966         flavors.
 967         (vpinsrb, vpinsrw): Drop IgnoreSize where still present on
 968         register only flavors.
 969         (vmovd): Move RegMem and drop IgnoreSize on register only
 970         flavor. Change opcode and operand order to store form.
 971         * opcodes/i386-init.h, i386-tbl.h: Re-generate.
 972
 973 2019-07-16  Jan Beulich  <jbeulich@suse.com>
 974
 975         * i386-gen.c (operand_type_init, operand_types): Replace SReg
 976         entries.
 977         * i386-opc.h (SReg2, SReg3): Replace by ...
 978         (SReg): ... this.
 979         (union i386_operand_type): Replace sreg fields.
 980         * i386-opc.tbl (mov, ): Use SReg.
 981         (push, pop): Likewies. Drop i386 and x86-64 specific segment
 982         register flavors.
 983         * i386-reg.tbl (cs, ds, es, fs, gs, ss, flat): Use SReg.
 984         * opcodes/i386-init.h, i386-tbl.h: Re-generate.
 985
 986 2019-07-15  Jose E. Marchesi  <jose.marchesi@oracle.com>
 987
 988         * bpf-desc.c: Regenerate.
 989         * bpf-opc.c: Likewise.
 990         * bpf-opc.h: Likewise.
 991
 992 2019-07-14  Jose E. Marchesi  <jose.marchesi@oracle.com>
 993
 994         * bpf-desc.c: Regenerate.
 995         * bpf-opc.c: Likewise.
 996
 997 2019-07-10  Hans-Peter Nilsson  <hp@bitrange.com>
 998
 999         * arm-dis.c (print_insn_coprocessor): Rename index to
1000         index_operand.
1001
1002 2019-07-05  Kito Cheng <kito.cheng@sifive.com>
1003
1004         * riscv-opc.c (riscv_insn_types): Add r4 type.
1005
1006         * riscv-opc.c (riscv_insn_types): Add b and j type.
1007
1008         * opcodes/riscv-opc.c (riscv_insn_types): Remove incorrect
1009         format for sb type and correct s type.
1010
1011 2019-07-02  Richard Sandiford  <richard.sandiford@arm.com>
1012
1013         * aarch64-tbl.h (aarch64_opcode): Set C_SCAN_MOVPRFX for the
1014         SVE FMOV alias of FCPY.
1015
1016 2019-07-02  Richard Sandiford  <richard.sandiford@arm.com>
1017
1018         * aarch64-tbl.h (aarch64_opcode_table): Add C_MAX_ELEM flags
1019         to SVE fcvtzs, fcvtzu, scvtf and ucvtf entries.
1020
1021 2019-07-02  Richard Sandiford  <richard.sandiford@arm.com>
1022
1023         * aarch64-opc.c (verify_constraints): Skip GPRs when scanning the
1024         registers in an instruction prefixed by MOVPRFX.
1025
1026 2019-07-01  Matthew Malcomson  <matthew.malcomson@arm.com>
1027
1028         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Use new
1029         sve_size_13 icode to account for variant behaviour of
1030         pmull{t,b}.
1031         * aarch64-dis-2.c: Regenerate.
1032         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Use new
1033         sve_size_13 icode to account for variant behaviour of
1034         pmull{t,b}.
1035         * aarch64-tbl.h (OP_SVE_VVV_HD_BS): Add new qualifier.
1036         (OP_SVE_VVV_Q_D): Add new qualifier.
1037         (OP_SVE_VVV_QHD_DBS): Remove now unused qualifier.
1038         (struct aarch64_opcode): Split pmull{t,b} into those requiring
1039         AES and those not.
1040
1041 2019-07-01  Jan Beulich  <jbeulich@suse.com>
1042
1043         * opcodes/i386-gen.c (operand_type_init): Remove
1044         OPERAND_TYPE_VEC_IMM4 entry.
1045         (operand_types): Remove Vec_Imm4.
1046         * opcodes/i386-opc.h (Vec_Imm4): Delete.
1047         (union i386_operand_type): Remove vec_imm4.
1048         * i386-opc.tbl (vpermil2pd, vpermil2ps): Remove Vec_Imm4.
1049         * opcodes/i386-init.h, i386-tbl.h: Re-generate.
1050
1051 2019-07-01  Jan Beulich  <jbeulich@suse.com>
1052
1053         * i386-opc.tbl (lfence, mfence, sfence, monitor, mwait, vmcall,
1054         vmlaunch, vmresume, vmxoff, vmfunc, xgetbv, xsetbv, swapgs,
1055         rdtscp, clgi, invlpga, skinit, stgi, vmload, vmmcall, vmrun,
1056         vmsave, montmul, xsha1, xsha256, xstorerng, xcryptecb,
1057         xcryptcbc, xcryptctr, xcryptcfb, xcryptofb, xstore, clac, stac,
1058         monitorx, mwaitx): Drop ImmExt from operand-less forms.
1059         * i386-tbl.h: Re-generate.
1060
1061 2019-07-01  Jan Beulich  <jbeulich@suse.com>
1062
1063         * i386-opc.tbl (and, or): Add Optimize to forms allowing two
1064         register operands.
1065         * i386-tbl.h: Re-generate.
1066
1067 2019-07-01  Jan Beulich  <jbeulich@suse.com>
1068
1069         * i386-opc.tbl (C): New.
1070         (paddb, paddw, paddd, paddq, paddsb, paddsw, paddusb, paddusw,
1071         pand, pcmpeqb, pcmpeqw, pcmpeqd, pmaddwd, pmulhw, pmullw,
1072         por, pxor, andps, cmpeqps, cmpeqss, cmpneqps, cmpneqss,
1073         cmpordps, cmpordss, cmpunordps, cmpunordss, orps, pavgb, pavgw,
1074         pmaxsw, pmaxub, pminsw, pminub, pmulhuw, xorps, andpd, cmpeqpd,
1075         cmpeqsd, cmpneqpd, cmpneqsd, cmpordpd, cmpordsd, cmpunordpd,
1076         cmpunordsd, orpd, xorpd, pmuludq, vandpd, vandps, vcmpeq_ospd,
1077         vcmpeq_osps, vcmpeq_ossd, vcmpeq_osss, vcmpeqpd, vcmpeqps,
1078         vcmpeqsd, vcmpeqss, vcmpeq_uqpd, vcmpeq_uqps, vcmpeq_uqsd,
1079         vcmpeq_uqss, vcmpeq_uspd, vcmpeq_usps, vcmpeq_ussd,
1080         vcmpeq_usss, vcmpfalse_ospd, vcmpfalse_osps, vcmpfalse_ossd,
1081         vcmpfalse_osss, vcmpfalsepd, vcmpfalseps, vcmpfalsesd,
1082         vcmpfalsess, vcmpneq_oqpd, vcmpneq_oqps, vcmpneq_oqsd,
1083         vcmpneq_oqss, vcmpneq_ospd, vcmpneq_osps, vcmpneq_ossd,
1084         vcmpneq_osss, vcmpneqpd, vcmpneqps, vcmpneqsd, vcmpneqss,
1085         vcmpneq_uspd, vcmpneq_usps, vcmpneq_ussd, vcmpneq_usss,
1086         vcmpordpd, vcmpordps, vcmpordsd, vcmpord_spd, vcmpord_sps,
1087         vcmpordss, vcmpord_ssd, vcmpord_sss, vcmptruepd, vcmptrueps,
1088         vcmptruesd, vcmptruess, vcmptrue_uspd, vcmptrue_usps,
1089         vcmptrue_ussd, vcmptrue_usss, vcmpunordpd, vcmpunordps,
1090         vcmpunordsd, vcmpunord_spd, vcmpunord_sps, vcmpunordss,
1091         vcmpunord_ssd, vcmpunord_sss, vorpd, vorps, vpaddsb, vpaddsw,
1092         vpaddb, vpaddd, vpaddq, vpaddw, vpaddusb, vpaddusw, vpand,
1093         vpavgb, vpavgw, vpcmpeqb, vpcmpeqd, vpcmpeqw, vpmaddwd,
1094         vpmaxsw, vpmaxub, vpminsw, vpminub, vpmulhuw, vpmulhw, vpmullw,
1095         vpmuludq, vpor, vpxor, vxorpd, vxorps): Add C to VEX-encoded
1096         flavors.
1097         * i386-tbl.h: Re-generate.
1098
1099 2019-07-01  Jan Beulich  <jbeulich@suse.com>
1100
1101         * i386-opc.tbl (and, or): Add Optimize to forms allowing two
1102         register operands.
1103         * i386-tbl.h: Re-generate.
1104
1105 2019-07-01  Jan Beulich  <jbeulich@suse.com>
1106
1107         * i386-dis-evex-prefix.h: Use PCLMUL for vpclmulqdq.
1108         * i386-opc.tbl (vpclmullqlqdq, vpclmulhqlqdq, vpclmullqhqdq,
1109         vpclmulhqhqdq): Add CpuVPCLMULQDQ flavors.
1110         * i386-tbl.h: Re-generate.
1111
1112 2019-07-01  Jan Beulich  <jbeulich@suse.com>
1113
1114         * i386-opc.tbl (vextractps, vpextrw, vpinsrw): Remove
1115         Disp8MemShift from register only templates.
1116         * i386-tbl.h: Re-generate.
1117
1118 2019-07-01  Jan Beulich  <jbeulich@suse.com>
1119
1120         * i386-dis.c (EXdScalarS, MOD_EVEX_0F10_PREFIX_1,
1121         MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1,
1122         MOD_EVEX_0F11_PREFIX_3, EVEX_W_0F10_P_1_M_0,
1123         EVEX_W_0F10_P_1_M_1, EVEX_W_0F10_P_3_M_0, EVEX_W_0F10_P_3_M_1,
1124         EVEX_W_0F11_P_1_M_0, EVEX_W_0F11_P_1_M_1, EVEX_W_0F11_P_3_M_0,
1125         EVEX_W_0F11_P_3_M_1): Delete.
1126         (EVEX_W_0F10_P_1, EVEX_W_0F10_P_3, EVEX_W_0F11_P_1,
1127         EVEX_W_0F11_P_3): New.
1128         * i386-dis-evex-mod.h: Remove MOD_EVEX_0F10_PREFIX_1,
1129         MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1, and
1130         MOD_EVEX_0F11_PREFIX_3 table entries.
1131         * i386-dis-evex-prefix.h: Adjust PREFIX_EVEX_0F10 and
1132         PREFIX_EVEX_0F11 table entries.
1133         * i386-dis-evex-w.h: Replace EVEX_W_0F10_P_1_M_{0,1},
1134         EVEX_W_0F10_P_3_M_{0,1}, EVEX_W_0F11_P_1_M_{0,1}, and
1135         EVEX_W_0F11_P_3_M_{0,1} table entries.
1136
1137 2019-07-01  Jan Beulich  <jbeulich@suse.com>
1138
1139         * i386-dis.c (EXdVex, EXdVexS, EXqVex, EXqVexS, XMVex):
1140         Delete.
1141
1142 2019-06-27  H.J. Lu  <hongjiu.lu@intel.com>
1143
1144         PR binutils/24719
1145         * i386-dis-evex-len.h: Add EVEX_LEN_0F38C6_REG_1_PREFIX_2,
1146         EVEX_LEN_0F38C6_REG_2_PREFIX_2, EVEX_LEN_0F38C6_REG_5_PREFIX_2,
1147         EVEX_LEN_0F38C6_REG_6_PREFIX_2, EVEX_LEN_0F38C7_R_1_P_2_W_0,
1148         EVEX_LEN_0F38C7_R_1_P_2_W_1, EVEX_LEN_0F38C7_R_2_P_2_W_0,
1149         EVEX_LEN_0F38C7_R_2_P_2_W_1, EVEX_LEN_0F38C7_R_5_P_2_W_0,
1150         EVEX_LEN_0F38C7_R_5_P_2_W_1, EVEX_LEN_0F38C7_R_6_P_2_W_0 and
1151         EVEX_LEN_0F38C7_R_6_P_2_W_1.
1152         * i386-dis-evex-prefix.h: Update PREFIX_EVEX_0F38C6_REG_1,
1153         PREFIX_EVEX_0F38C6_REG_2, PREFIX_EVEX_0F38C6_REG_5 and
1154         PREFIX_EVEX_0F38C6_REG_6 entries.
1155         * i386-dis-evex-w.h: Update EVEX_W_0F38C7_R_1_P_2,
1156         EVEX_W_0F38C7_R_2_P_2, EVEX_W_0F38C7_R_5_P_2 and
1157         EVEX_W_0F38C7_R_6_P_2 entries.
1158         * i386-dis.c: Add EVEX_LEN_0F38C6_REG_1_PREFIX_2,
1159         EVEX_LEN_0F38C6_REG_2_PREFIX_2, EVEX_LEN_0F38C6_REG_5_PREFIX_2,
1160         EVEX_LEN_0F38C6_REG_6_PREFIX_2, EVEX_LEN_0F38C7_R_1_P_2_W_0,
1161         EVEX_LEN_0F38C7_R_1_P_2_W_1, EVEX_LEN_0F38C7_R_2_P_2_W_0,
1162         EVEX_LEN_0F38C7_R_2_P_2_W_1, EVEX_LEN_0F38C7_R_5_P_2_W_0,
1163         EVEX_LEN_0F38C7_R_5_P_2_W_1, EVEX_LEN_0F38C7_R_6_P_2_W_0 and
1164         EVEX_LEN_0F38C7_R_6_P_2_W_1 enums.
1165
1166 2019-06-27  Jan Beulich  <jbeulich@suse.com>
1167
1168         * i386-dis.c (VEX_LEN_0F2A_P_1, VEX_LEN_0F2A_P_3,
1169         VEX_LEN_0F2C_P_1, VEX_LEN_0F2C_P_3, VEX_LEN_0F2D_P_1,
1170         VEX_LEN_0F2D_P_3): Delete.
1171         (vex_len_table): Move vcvtsi2ss, vcvtsi2sd, vcvttss2si,
1172         vcvttsd2si, vcvtss2si, and vcvtsd2si leaf entries ...
1173         (prefix_table): ... here.
1174
1175 2019-06-27  Jan Beulich  <jbeulich@suse.com>
1176
1177         * i386-dis.c (Iq): Delete.
1178         (Id): New.
1179         (reg_table): Use it for lwpins, lwpval, and bextr. Use Edq for
1180         TBM insns.
1181         (vex_len_table): Use Edq for vcvtsi2ss, vcvtsi2sd. Use Gdq for
1182         vcvttss2si, vcvttsd2si, vcvtss2si, and vcvtsd2si.
1183         (OP_E_memory): Also honor needindex when deciding whether an
1184         address size prefix needs printing.
1185         (OP_I): Remove handling of q_mode. Add handling of d_mode.
1186
1187 2019-06-26  Jim Wilson  <jimw@sifive.com>
1188
1189         PR binutils/24739
1190         * riscv-dis.c (riscv_disasemble_insn): Set info->endian_code.
1191         Set info->display_endian to info->endian_code.
1192
1193 2019-06-25  Jan Beulich  <jbeulich@suse.com>
1194
1195         * i386-gen.c (operand_type_init): Correct OPERAND_TYPE_DEBUG
1196         entry. Drop OPERAND_TYPE_ACC entry. Add OPERAND_TYPE_ACC8 and
1197         OPERAND_TYPE_ACC16 entries. Adjust OPERAND_TYPE_ACC32 and
1198         OPERAND_TYPE_ACC64 entries.
1199         * i386-init.h: Re-generate.
1200
1201 2019-06-25  Jan Beulich  <jbeulich@suse.com>
1202
1203         * i386-dis.c (Edqa, dqa_mode, EVEX_W_0F2A_P_1, EVEX_W_0F7B_P_1):
1204         Delete.
1205         (intel_operand_size, OP_E_register, OP_E_memory): Drop handling
1206         of dqa_mode.
1207         * i386-dis-evex-prefix.h: Move vcvtsi2ss and vcvtusi2ss leaf
1208         entries here.
1209         * i386-dis-evex-w.h: Drop EVEX_W_0F2A_P_1 and EVEX_W_0F7B_P_1
1210         entries. Use Edq for vcvtsi2sd and vcvtusi2sd.
1211
1212 2019-06-25  Jan Beulich  <jbeulich@suse.com>
1213
1214         * i386-dis.c (OP_I64): Forword more cases to OP_I(). Drop local
1215         variables.
1216
1217 2019-06-25  Jan Beulich  <jbeulich@suse.com>
1218
1219         * i386-dis.c (prefix_table): Use Edq for cvtsi2ss and cvtsi2sd.
1220         Use Gdq for cvttss2si, cvttsd2si, cvtss2si, and cvtsd2si, and
1221         movnti.
1222         * i386-opc.tbl (movnti): Add IgnoreSize.
1223         * i386-tbl.h: Re-generate.
1224
1225 2019-06-25  Jan Beulich  <jbeulich@suse.com>
1226
1227         * i386-opc.tbl (and): Mark Imm8S form for optimization.
1228         * i386-tbl.h: Re-generate.
1229
1230 2019-06-21  H.J. Lu  <hongjiu.lu@intel.com>
1231
1232         * i386-dis-evex.h: Break into ...
1233         * i386-dis-evex-len.h: New file.
1234         * i386-dis-evex-mod.h: Likewise.
1235         * i386-dis-evex-prefix.h: Likewise.
1236         * i386-dis-evex-reg.h: Likewise.
1237         * i386-dis-evex-w.h: Likewise.
1238         * i386-dis.c: Include i386-dis-evex-reg.h, i386-dis-evex-prefix.h,
1239         i386-dis-evex.h, i386-dis-evex-len.h, i386-dis-evex-w.h and
1240         i386-dis-evex-mod.h.
1241
1242 2019-06-19  H.J. Lu  <hongjiu.lu@intel.com>
1243
1244         PR binutils/24700
1245         * i386-dis-evex.h (evex_table): Update EVEX_W_0F3819_P_2,
1246         EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2, EVEX_W_0F385A_P_2 and
1247         EVEX_W_0F385B_P_2.
1248         (evex_len_table): Add EVEX_LEN_0F3819_P_2_W_0,
1249         EVEX_LEN_0F3819_P_2_W_1, EVEX_LEN_0F381A_P_2_W_0,
1250         EVEX_LEN_0F381A_P_2_W_1, EVEX_LEN_0F381B_P_2_W_0,
1251         EVEX_LEN_0F381B_P_2_W_1, EVEX_LEN_0F385A_P_2_W_0,
1252         EVEX_LEN_0F385A_P_2_W_1, EVEX_LEN_0F385B_P_2_W_0 and
1253         EVEX_LEN_0F385B_P_2_W_1.
1254         * i386-dis.c (EVEX_LEN_0F3819_P_2_W_0): New enum.
1255         (EVEX_LEN_0F3819_P_2_W_1): Likewise.
1256         (EVEX_LEN_0F381A_P_2_W_0): Likewise.
1257         (EVEX_LEN_0F381A_P_2_W_1): Likewise.
1258         (EVEX_LEN_0F381B_P_2_W_0): Likewise.
1259         (EVEX_LEN_0F381B_P_2_W_1): Likewise.
1260         (EVEX_LEN_0F385A_P_2_W_0): Likewise.
1261         (EVEX_LEN_0F385A_P_2_W_1): Likewise.
1262         (EVEX_LEN_0F385B_P_2_W_0): Likewise.
1263         (EVEX_LEN_0F385B_P_2_W_1): Likewise.
1264
1265 2019-06-17  H.J. Lu  <hongjiu.lu@intel.com>
1266
1267         PR binutils/24691
1268         * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A23_P_2,
1269         EVEX_W_0F3A38_P_2, EVEX_W_0F3A39_P_2, EVEX_W_0F3A3A_P_2,
1270         EVEX_W_0F3A3B_P_2 and EVEX_W_0F3A43_P_2.
1271         (evex_len_table): Add EVEX_LEN_0F3A23_P_2_W_0,
1272         EVEX_LEN_0F3A23_P_2_W_1, EVEX_LEN_0F3A38_P_2_W_0,
1273         EVEX_LEN_0F3A38_P_2_W_1, EVEX_LEN_0F3A39_P_2_W_0,
1274         EVEX_LEN_0F3A39_P_2_W_1, EVEX_LEN_0F3A3A_P_2_W_0,
1275         EVEX_LEN_0F3A3A_P_2_W_1, EVEX_LEN_0F3A3B_P_2_W_0,
1276         EVEX_LEN_0F3A3B_P_2_W_1, EVEX_LEN_0F3A43_P_2_W_0 and
1277         EVEX_LEN_0F3A43_P_2_W_1.
1278         * i386-dis.c (EVEX_LEN_0F3A23_P_2_W_0): New enum.
1279         (EVEX_LEN_0F3A23_P_2_W_1): Likewise.
1280         (EVEX_LEN_0F3A38_P_2_W_0): Likewise.
1281         (EVEX_LEN_0F3A38_P_2_W_1): Likewise.
1282         (EVEX_LEN_0F3A39_P_2_W_0): Likewise.
1283         (EVEX_LEN_0F3A39_P_2_W_1): Likewise.
1284         (EVEX_LEN_0F3A3A_P_2_W_0): Likewise.
1285         (EVEX_LEN_0F3A3A_P_2_W_1): Likewise.
1286         (EVEX_LEN_0F3A3B_P_2_W_0): Likewise.
1287         (EVEX_LEN_0F3A3B_P_2_W_1): Likewise.
1288         (EVEX_LEN_0F3A43_P_2_W_0): Likewise.
1289         (EVEX_LEN_0F3A43_P_2_W_1): Likewise.
1290
1291 2019-06-14  Nick Clifton  <nickc@redhat.com>
1292
1293         * po/fr.po; Updated French translation.
1294
1295 2019-06-13  Stafford Horne  <shorne@gmail.com>
1296
1297         * or1k-asm.c: Regenerated.
1298         * or1k-desc.c: Regenerated.
1299         * or1k-desc.h: Regenerated.
1300         * or1k-dis.c: Regenerated.
1301         * or1k-ibld.c: Regenerated.
1302         * or1k-opc.c: Regenerated.
1303         * or1k-opc.h: Regenerated.
1304         * or1k-opinst.c: Regenerated.
1305
1306 2019-06-12  Peter Bergner  <bergner@linux.ibm.com>
1307
1308         * ppc-opc.c (powerpc_opcodes) <ldmx>: Delete mnemonic.
1309
1310 2019-06-05  H.J. Lu  <hongjiu.lu@intel.com>
1311
1312         PR binutils/24633
1313         * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A18_P_2,
1314         EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2 and EVEX_W_0F3A1B_P_2.
1315         (evex_len_table): EVEX_LEN_0F3A18_P_2_W_0,
1316         EVEX_LEN_0F3A18_P_2_W_1, EVEX_LEN_0F3A19_P_2_W_0,
1317         EVEX_LEN_0F3A19_P_2_W_1, EVEX_LEN_0F3A1A_P_2_W_0,
1318         EVEX_LEN_0F3A1A_P_2_W_1, EVEX_LEN_0F3A1B_P_2_W_0,
1319         EVEX_LEN_0F3A1B_P_2_W_1.
1320         * i386-dis.c (EVEX_LEN_0F3A18_P_2_W_0): New enum.
1321         (EVEX_LEN_0F3A18_P_2_W_1): Likewise.
1322         (EVEX_LEN_0F3A19_P_2_W_0): Likewise.
1323         (EVEX_LEN_0F3A19_P_2_W_1): Likewise.
1324         (EVEX_LEN_0F3A1A_P_2_W_0): Likewise.
1325         (EVEX_LEN_0F3A1A_P_2_W_1): Likewise.
1326         (EVEX_LEN_0F3A1B_P_2_W_0): Likewise.
1327         (EVEX_LEN_0F3A1B_P_2_W_1): Likewise.
1328
1329 2019-06-04  H.J. Lu  <hongjiu.lu@intel.com>
1330
1331         PR binutils/24626
1332         * i386-dis.c (print_insn): Check for unused VEX.vvvv and
1333         EVEX.vvvv when disassembling VEX and EVEX instructions.
1334         (OP_VEX): Set vex.register_specifier to 0 after readding
1335         vex.register_specifier.
1336         (OP_Vex_2src_1): Likewise.
1337         (OP_Vex_2src_2): Likewise.
1338         (OP_LWP_E): Likewise.
1339         (OP_EX_Vex): Don't check vex.register_specifier.
1340         (OP_XMM_Vex): Likewise.
1341
1342 2019-06-04  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
1343             Lili Cui  <lili.cui@intel.com>
1344
1345         * i386-dis.c (enum): Add PREFIX_EVEX_0F3868, EVEX_W_0F3868_P_3.
1346         * i386-dis-evex.h (evex_table): Add AVX512_VP2INTERSECT
1347         instructions.
1348         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VP2INTERSECT_FLAGS,
1349         CPU_ANY_AVX512_VP2INTERSECT_FLAGS.
1350         (cpu_flags): Add CpuAVX512_VP2INTERSECT.
1351         * i386-opc.h (enum): Add CpuAVX512_VP2INTERSECT.
1352         (i386_cpu_flags): Add cpuavx512_vp2intersect.
1353         * i386-opc.tbl: Add AVX512_VP2INTERSECT insns.
1354         * i386-init.h: Regenerated.
1355         * i386-tbl.h: Likewise.
1356
1357 2019-06-04  Xuepeng Guo  <xuepeng.guo@intel.com>
1358             Lili Cui  <lili.cui@intel.com>
1359
1360         * doc/c-i386.texi: Document enqcmd.
1361         * testsuite/gas/i386/enqcmd-intel.d: New file.
1362         * testsuite/gas/i386/enqcmd-inval.l: Likewise.
1363         * testsuite/gas/i386/enqcmd-inval.s: Likewise.
1364         * testsuite/gas/i386/enqcmd.d: Likewise.
1365         * testsuite/gas/i386/enqcmd.s: Likewise.
1366         * testsuite/gas/i386/x86-64-enqcmd-intel.d: Likewise.
1367         * testsuite/gas/i386/x86-64-enqcmd-inval.l: Likewise.
1368         * testsuite/gas/i386/x86-64-enqcmd-inval.s: Likewise.
1369         * testsuite/gas/i386/x86-64-enqcmd.d: Likewise.
1370         * testsuite/gas/i386/x86-64-enqcmd.s: Likewise.
1371         * testsuite/gas/i386/i386.exp: Run enqcmd-intel, enqcmd-inval,
1372         enqcmd, x86-64-enqcmd-intel, x86-64-enqcmd-inval,
1373         and x86-64-enqcmd.
1374
1375 2019-06-04  Alan Hayward  <alan.hayward@arm.com>
1376
1377         * arm-dis.c (is_mve_unpredictable): Remove spurious paranthesis.
1378
1379 2019-06-03  Alan Modra  <amodra@gmail.com>
1380
1381         * ppc-dis.c (prefix_opcd_indices): Correct size.
1382
1383 2019-05-28  H.J. Lu  <hongjiu.lu@intel.com>
1384
1385         PR gas/24625
1386         * i386-opc.tbl: Add CheckRegSize to AVX512_BF16 instructions with
1387         Disp8ShiftVL.
1388         * i386-tbl.h: Regenerated.
1389
1390 2019-05-24  Alan Modra  <amodra@gmail.com>
1391
1392         * po/POTFILES.in: Regenerate.
1393
1394 2019-05-24  Peter Bergner  <bergner@linux.ibm.com>
1395             Alan Modra  <amodra@gmail.com>
1396
1397         * ppc-opc.c (insert_d34, extract_d34, insert_nsi34, extract_nsi34),
1398         (insert_pcrel, extract_pcrel, extract_pcrel0): New functions.
1399         (extract_esync, extract_raq, extract_tbr, extract_sxl): Comment.
1400         (powerpc_operands <D34, SI34, NSI34, PRA0, PRAQ, PCREL, PCREL0,
1401         XTOP>): Define and add entries.
1402         (P8LS, PMLS, P_D_MASK, P_DRAPCREL_MASK): Define.
1403         (prefix_opcodes): Add pli, paddi, pla, psubi, plwz, plbz, pstw,
1404         pstb, plhz, plha, psth, plfs, plfd, pstfs, pstfd, plq, plxsd,
1405         plxssp, pld, plwa, pstxsd, pstxssp, pstxv, pstd, and pstq.
1406
1407 2019-05-24  Peter Bergner  <bergner@linux.ibm.com>
1408             Alan Modra  <amodra@gmail.com>
1409
1410         * ppc-dis.c (ppc_opts): Add "future" entry.
1411         (PREFIX_OPCD_SEGS): Define.
1412         (prefix_opcd_indices): New array.
1413         (disassemble_init_powerpc): Initialize prefix_opcd_indices.
1414         (lookup_prefix): New function.
1415         (print_insn_powerpc): Handle 64-bit prefix instructions.
1416         * ppc-opc.c (PREFIX_OP, PREFIX_FORM, SUFFIX_MASK, PREFIX_MASK),
1417         (PMRR, POWERXX): Define.
1418         (prefix_opcodes): New instruction table.
1419         (prefix_num_opcodes): New constant.
1420
1421 2019-05-23  Jose E. Marchesi  <jose.marchesi@oracle.com>
1422
1423         * configure.ac (SHARED_DEPENDENCIES): Add case for bfd_bpf_arch.
1424         * configure: Regenerated.
1425         * Makefile.am: Add rules for the files generated from cpu/bpf.cpu
1426         and cpu/bpf.opc.
1427         (HFILES): Add bpf-desc.h and bpf-opc.h.
1428         (TARGET_LIBOPCODES_CFILES): Add bpf-asm.c, bpf-desc.c, bpf-dis.c,
1429         bpf-ibld.c and bpf-opc.c.
1430         (BPF_DEPS): Define.
1431         * Makefile.in: Regenerated.
1432         * disassemble.c (ARCH_bpf): Define.
1433         (disassembler): Add case for bfd_arch_bpf.
1434         (disassemble_init_for_target): Likewise.
1435         (enum epbf_isa_attr): Define.
1436         * disassemble.h: extern print_insn_bpf.
1437         * bpf-asm.c: Generated.
1438         * bpf-opc.h: Likewise.
1439         * bpf-opc.c: Likewise.
1440         * bpf-ibld.c: Likewise.
1441         * bpf-dis.c: Likewise.
1442         * bpf-desc.h: Likewise.
1443         * bpf-desc.c: Likewise.
1444
1445 2019-05-21  Sudakshina Das  <sudi.das@arm.com>
1446
1447         * arm-dis.c (coprocessor_opcodes): New instructions for VMRS
1448         and VMSR with the new operands.
1449
1450 2019-05-21  Sudakshina Das  <sudi.das@arm.com>
1451
1452         * arm-dis.c (enum mve_instructions): New enum
1453         for csinc, csinv, csneg, csel, cset, csetm, cinv, cinv
1454         and cneg.
1455         (mve_opcodes): New instructions as above.
1456         (is_mve_encoding_conflict): Add cases for csinc, csinv,
1457         csneg and csel.
1458         (print_insn_mve): Accept new %<bitfield>c and %<bitfield>C.
1459
1460 2019-05-21  Sudakshina Das  <sudi.das@arm.com>
1461
1462         * arm-dis.c (emun mve_instructions): Updated for new instructions.
1463         (mve_opcodes): New instructions for asrl, lsll, lsrl, sqrshrl,
1464         sqrshr, sqshl, sqshll, srshr, srshrl, uqrshll, uqrshl, uqshll,
1465         uqshl, urshrl and urshr.
1466         (is_mve_okay_in_it): Add new instructions to TRUE list.
1467         (is_mve_unpredictable): Add cases for UNPRED_R13 and UNPRED_R15.
1468         (print_insn_mve): Updated to accept new %j,
1469         %<bitfield>m and %<bitfield>n patterns.
1470
1471 2019-05-21  Faraz Shahbazker  <fshahbazker@wavecomp.com>
1472
1473         * mips-opc.c (mips_builtin_opcodes): Change source register
1474         constraint for DAUI.
1475
1476 2019-05-20  Nick Clifton  <nickc@redhat.com>
1477
1478         * po/fr.po: Updated French translation.
1479
1480 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1481             Michael Collison <michael.collison@arm.com>
1482
1483         * arm-dis.c (thumb32_opcodes): Add new instructions.
1484         (enum mve_instructions): Likewise.
1485         (enum mve_undefined): Add new reasons.
1486         (is_mve_encoding_conflict): Handle new instructions.
1487         (is_mve_undefined): Likewise.
1488         (is_mve_unpredictable): Likewise.
1489         (print_mve_undefined): Likewise.
1490         (print_mve_size): Likewise.
1491
1492 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1493             Michael Collison <michael.collison@arm.com>
1494
1495         * arm-dis.c (thumb32_opcodes): Add new instructions.
1496         (enum mve_instructions): Likewise.
1497         (is_mve_encoding_conflict): Handle new instructions.
1498         (is_mve_undefined): Likewise.
1499         (is_mve_unpredictable): Likewise.
1500         (print_mve_size): Likewise.
1501
1502 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1503             Michael Collison <michael.collison@arm.com>
1504
1505         * arm-dis.c (thumb32_opcodes): Add new instructions.
1506         (enum mve_instructions): Likewise.
1507         (is_mve_encoding_conflict): Likewise.
1508         (is_mve_unpredictable): Likewise.
1509         (print_mve_size): Likewise.
1510
1511 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1512             Michael Collison <michael.collison@arm.com>
1513
1514         * arm-dis.c (thumb32_opcodes): Add new instructions.
1515         (enum mve_instructions): Likewise.
1516         (is_mve_encoding_conflict): Handle new instructions.
1517         (is_mve_undefined): Likewise.
1518         (is_mve_unpredictable): Likewise.
1519         (print_mve_size): Likewise.
1520
1521 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1522             Michael Collison <michael.collison@arm.com>
1523
1524         * arm-dis.c (thumb32_opcodes): Add new instructions.
1525         (enum mve_instructions): Likewise.
1526         (is_mve_encoding_conflict): Handle new instructions.
1527         (is_mve_undefined): Likewise.
1528         (is_mve_unpredictable): Likewise.
1529         (print_mve_size): Likewise.
1530         (print_insn_mve): Likewise.
1531
1532 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1533             Michael Collison <michael.collison@arm.com>
1534
1535         * arm-dis.c (thumb32_opcodes): Add new instructions.
1536         (print_insn_thumb32): Handle new instructions.
1537
1538 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1539             Michael Collison <michael.collison@arm.com>
1540
1541         * arm-dis.c (enum mve_instructions): Add new instructions.
1542         (enum mve_undefined): Add new reasons.
1543         (is_mve_encoding_conflict): Handle new instructions.
1544         (is_mve_undefined): Likewise.
1545         (is_mve_unpredictable): Likewise.
1546         (print_mve_undefined): Likewise.
1547         (print_mve_size): Likewise.
1548         (print_mve_shift_n): Likewise.
1549         (print_insn_mve): Likewise.
1550
1551 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1552             Michael Collison <michael.collison@arm.com>
1553
1554         * arm-dis.c (enum mve_instructions): Add new instructions.
1555         (is_mve_encoding_conflict): Handle new instructions.
1556         (is_mve_unpredictable): Likewise.
1557         (print_mve_rotate): Likewise.
1558         (print_mve_size): Likewise.
1559         (print_insn_mve): Likewise.
1560
1561 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1562             Michael Collison <michael.collison@arm.com>
1563
1564         * arm-dis.c (enum mve_instructions): Add new instructions.
1565         (is_mve_encoding_conflict): Handle new instructions.
1566         (is_mve_unpredictable): Likewise.
1567         (print_mve_size): Likewise.
1568         (print_insn_mve): Likewise.
1569
1570 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1571             Michael Collison <michael.collison@arm.com>
1572
1573         * arm-dis.c (enum mve_instructions): Add new instructions.
1574         (enum mve_undefined): Add new reasons.
1575         (is_mve_encoding_conflict): Handle new instructions.
1576         (is_mve_undefined): Likewise.
1577         (is_mve_unpredictable): Likewise.
1578         (print_mve_undefined): Likewise.
1579         (print_mve_size): Likewise.
1580         (print_insn_mve): Likewise.
1581
1582 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1583             Michael Collison <michael.collison@arm.com>
1584
1585         * arm-dis.c (enum mve_instructions): Add new instructions.
1586         (is_mve_encoding_conflict): Handle new instructions.
1587         (is_mve_undefined): Likewise.
1588         (is_mve_unpredictable): Likewise.
1589         (print_mve_size): Likewise.
1590         (print_insn_mve): Likewise.
1591
1592 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1593             Michael Collison <michael.collison@arm.com>
1594
1595         * arm-dis.c (enum mve_instructions): Add new instructions.
1596         (enum mve_unpredictable): Add new reasons.
1597         (enum mve_undefined): Likewise.
1598         (is_mve_okay_in_it): Handle new isntructions.
1599         (is_mve_encoding_conflict): Likewise.
1600         (is_mve_undefined): Likewise.
1601         (is_mve_unpredictable): Likewise.
1602         (print_mve_vmov_index): Likewise.
1603         (print_simd_imm8): Likewise.
1604         (print_mve_undefined): Likewise.
1605         (print_mve_unpredictable): Likewise.
1606         (print_mve_size): Likewise.
1607         (print_insn_mve): Likewise.
1608
1609 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1610             Michael Collison <michael.collison@arm.com>
1611
1612         * arm-dis.c (enum mve_instructions): Add new instructions.
1613         (enum mve_unpredictable): Add new reasons.
1614         (enum mve_undefined): Likewise.
1615         (is_mve_encoding_conflict): Handle new instructions.
1616         (is_mve_undefined): Likewise.
1617         (is_mve_unpredictable): Likewise.
1618         (print_mve_undefined): Likewise.
1619         (print_mve_unpredictable): Likewise.
1620         (print_mve_rounding_mode): Likewise.
1621         (print_mve_vcvt_size): Likewise.
1622         (print_mve_size): Likewise.
1623         (print_insn_mve): Likewise.
1624
1625 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1626             Michael Collison <michael.collison@arm.com>
1627
1628         * arm-dis.c (enum mve_instructions): Add new instructions.
1629         (enum mve_unpredictable): Add new reasons.
1630         (enum mve_undefined): Likewise.
1631         (is_mve_undefined): Handle new instructions.
1632         (is_mve_unpredictable): Likewise.
1633         (print_mve_undefined): Likewise.
1634         (print_mve_unpredictable): Likewise.
1635         (print_mve_size): Likewise.
1636         (print_insn_mve): Likewise.
1637
1638 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1639             Michael Collison <michael.collison@arm.com>
1640
1641         * arm-dis.c (enum mve_instructions): Add new instructions.
1642         (enum mve_undefined): Add new reasons.
1643         (insns): Add new instructions.
1644         (is_mve_encoding_conflict):
1645         (print_mve_vld_str_addr): New print function.
1646         (is_mve_undefined): Handle new instructions.
1647         (is_mve_unpredictable): Likewise.
1648         (print_mve_undefined): Likewise.
1649         (print_mve_size): Likewise.
1650         (print_insn_coprocessor_1): Handle MVE VLDR, VSTR instructions.
1651         (print_insn_mve):  Handle new operands.
1652
1653 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1654             Michael Collison <michael.collison@arm.com>
1655
1656         * arm-dis.c (enum mve_instructions): Add new instructions.
1657         (enum mve_unpredictable): Add new reasons.
1658         (is_mve_encoding_conflict): Handle new instructions.
1659         (is_mve_unpredictable): Likewise.
1660         (mve_opcodes): Add new instructions.
1661         (print_mve_unpredictable): Handle new reasons.
1662         (print_mve_register_blocks): New print function.
1663         (print_mve_size): Handle new instructions.
1664         (print_insn_mve): Likewise.
1665
1666 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1667             Michael Collison <michael.collison@arm.com>
1668
1669         * arm-dis.c (enum mve_instructions): Add new instructions.
1670         (enum mve_unpredictable): Add new reasons.
1671         (enum mve_undefined): Likewise.
1672         (is_mve_encoding_conflict): Handle new instructions.
1673         (is_mve_undefined): Likewise.
1674         (is_mve_unpredictable): Likewise.
1675         (coprocessor_opcodes): Move NEON VDUP from here...
1676         (neon_opcodes): ... to here.
1677         (mve_opcodes): Add new instructions.
1678         (print_mve_undefined):  Handle new reasons.
1679         (print_mve_unpredictable): Likewise.
1680         (print_mve_size): Handle new instructions.
1681         (print_insn_neon): Handle vdup.
1682         (print_insn_mve): Handle new operands.
1683
1684 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1685             Michael Collison <michael.collison@arm.com>
1686
1687         * arm-dis.c (enum mve_instructions): Add new instructions.
1688         (enum mve_unpredictable): Add new values.
1689         (mve_opcodes): Add new instructions.
1690         (vec_condnames): New array with vector conditions.
1691         (mve_predicatenames): New array with predicate suffixes.
1692         (mve_vec_sizename): New array with vector sizes.
1693         (enum vpt_pred_state): New enum with vector predication states.
1694         (struct vpt_block): New struct type for vpt blocks.
1695         (vpt_block_state): Global struct to keep track of state.
1696         (mve_extract_pred_mask): New helper function.
1697         (num_instructions_vpt_block): Likewise.
1698         (mark_outside_vpt_block): Likewise.
1699         (mark_inside_vpt_block): Likewise.
1700         (invert_next_predicate_state): Likewise.
1701         (update_next_predicate_state): Likewise.
1702         (update_vpt_block_state): Likewise.
1703         (is_vpt_instruction): Likewise.
1704         (is_mve_encoding_conflict): Add entries for new instructions.
1705         (is_mve_unpredictable): Likewise.
1706         (print_mve_unpredictable): Handle new cases.
1707         (print_instruction_predicate): Likewise.
1708         (print_mve_size): New function.
1709         (print_vec_condition): New function.
1710         (print_insn_mve): Handle vpt blocks and new print operands.
1711
1712 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1713
1714         * arm-dis.c (print_insn_coprocessor_1): Disable the use of coprocessors
1715         8, 14 and 15 for Armv8.1-M Mainline.
1716
1717 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1718             Michael Collison <michael.collison@arm.com>
1719
1720         * arm-dis.c (enum mve_instructions): New enum.
1721         (enum mve_unpredictable): Likewise.
1722         (enum mve_undefined): Likewise.
1723         (struct mopcode32): New struct.
1724         (is_mve_okay_in_it): New function.
1725         (is_mve_architecture): Likewise.
1726         (arm_decode_field): Likewise.
1727         (arm_decode_field_multiple): Likewise.
1728         (is_mve_encoding_conflict): Likewise.
1729         (is_mve_undefined): Likewise.
1730         (is_mve_unpredictable): Likewise.
1731         (print_mve_undefined): Likewise.
1732         (print_mve_unpredictable): Likewise.
1733         (print_insn_coprocessor_1): Use arm_decode_field_multiple.
1734         (print_insn_mve): New function.
1735         (print_insn_thumb32): Handle MVE architecture.
1736         (select_arm_features): Force thumb for Armv8.1-m Mainline.
1737
1738 2019-05-10  Nick Clifton  <nickc@redhat.com>
1739
1740         PR 24538
1741         * ia64-opc.c (ia64_find_matching_opcode): Check for reaching the
1742         end of the table prematurely.
1743
1744 2019-05-10  Faraz Shahbazker  <fshahbazker@wavecomp.com>
1745
1746         * mips-opc.c (mips_opcodes): Enable ADD, SUB, DADD and DSUB
1747         macros for R6.
1748
1749 2019-05-11  Alan Modra  <amodra@gmail.com>
1750
1751         * ppc-dis.c (print_insn_powerpc) Don't skip optional operands
1752         when -Mraw is in effect.
1753
1754 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1755
1756         * aarch64-dis-2.c: Regenerate.
1757         * aarch64-tbl.h (OP_SVE_BBU): New variant set.
1758         (OP_SVE_BBB): New variant set.
1759         (OP_SVE_DDDD): New variant set.
1760         (OP_SVE_HHH): New variant set.
1761         (OP_SVE_HHHU): New variant set.
1762         (OP_SVE_SSS): New variant set.
1763         (OP_SVE_SSSU): New variant set.
1764         (OP_SVE_SHH): New variant set.
1765         (OP_SVE_SBBU): New variant set.
1766         (OP_SVE_DSS): New variant set.
1767         (OP_SVE_DHHU): New variant set.
1768         (OP_SVE_VMV_HSD_BHS): New variant set.
1769         (OP_SVE_VVU_HSD_BHS): New variant set.
1770         (OP_SVE_VVVU_SD_BH): New variant set.
1771         (OP_SVE_VVVU_BHSD): New variant set.
1772         (OP_SVE_VVV_QHD_DBS): New variant set.
1773         (OP_SVE_VVV_HSD_BHS): New variant set.
1774         (OP_SVE_VVV_HSD_BHS2): New variant set.
1775         (OP_SVE_VVV_BHS_HSD): New variant set.
1776         (OP_SVE_VV_BHS_HSD): New variant set.
1777         (OP_SVE_VVV_SD): New variant set.
1778         (OP_SVE_VVU_BHS_HSD): New variant set.
1779         (OP_SVE_VZVV_SD): New variant set.
1780         (OP_SVE_VZVV_BH): New variant set.
1781         (OP_SVE_VZV_SD): New variant set.
1782         (aarch64_opcode_table): Add sve2 instructions.
1783
1784 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1785
1786         * aarch64-asm-2.c: Regenerated.
1787         * aarch64-dis-2.c: Regenerated.
1788         * aarch64-opc-2.c: Regenerated.
1789         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1790         for SVE_SHLIMM_UNPRED_22.
1791         (aarch64_print_operand): Add printing for SVE_SHLIMM_UNPRED_22.
1792         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHLIMM_UNPRED_22
1793         operand.
1794
1795 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1796
1797         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1798         sve_size_tsz_bhs iclass encode.
1799         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1800         sve_size_tsz_bhs iclass decode.
1801
1802 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1803
1804         * aarch64-asm-2.c: Regenerated.
1805         * aarch64-dis-2.c: Regenerated.
1806         * aarch64-opc-2.c: Regenerated.
1807         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1808         for SVE_Zm4_11_INDEX.
1809         (aarch64_print_operand): Add printing for SVE_Zm4_11_INDEX.
1810         (fields): Handle SVE_i2h field.
1811         * aarch64-opc.h (enum aarch64_field_kind): New SVE_i2h field.
1812         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm4_11_INDEX operand.
1813
1814 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1815
1816         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1817         sve_shift_tsz_bhsd iclass encode.
1818         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1819         sve_shift_tsz_bhsd iclass decode.
1820
1821 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1822
1823         * aarch64-asm-2.c: Regenerated.
1824         * aarch64-dis-2.c: Regenerated.
1825         * aarch64-opc-2.c: Regenerated.
1826         * aarch64-asm.c (aarch64_ins_sve_shrimm):
1827         (aarch64_encode_variant_using_iclass): Handle
1828         sve_shift_tsz_hsd iclass encode.
1829         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1830         sve_shift_tsz_hsd iclass decode.
1831         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1832         for SVE_SHRIMM_UNPRED_22.
1833         (aarch64_print_operand): Add printing for SVE_SHRIMM_UNPRED_22.
1834         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHRIMM_UNPRED_22
1835         operand.
1836
1837 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1838
1839         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1840         sve_size_013 iclass encode.
1841         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1842         sve_size_013 iclass decode.
1843
1844 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1845
1846         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1847         sve_size_bh iclass encode.
1848         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1849         sve_size_bh iclass decode.
1850
1851 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1852
1853         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1854         sve_size_sd2 iclass encode.
1855         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1856         sve_size_sd2 iclass decode.
1857         * aarch64-opc.c (fields): Handle SVE_sz2 field.
1858         * aarch64-opc.h (enum aarch64_field_kind): New SVE_sz2 field.
1859
1860 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1861
1862         * aarch64-asm-2.c: Regenerated.
1863         * aarch64-dis-2.c: Regenerated.
1864         * aarch64-opc-2.c: Regenerated.
1865         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1866         for SVE_ADDR_ZX.
1867         (aarch64_print_operand): Add printing for SVE_ADDR_ZX.
1868         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_ADDR_ZX operand.
1869
1870 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1871
1872         * aarch64-asm-2.c: Regenerated.
1873         * aarch64-dis-2.c: Regenerated.
1874         * aarch64-opc-2.c: Regenerated.
1875         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1876         for SVE_Zm3_11_INDEX.
1877         (aarch64_print_operand): Add printing for SVE_Zm3_11_INDEX.
1878         (fields): Handle SVE_i3l and SVE_i3h2 fields.
1879         * aarch64-opc.h (enum aarch64_field_kind): New SVE_i3l and SVE_i3h2
1880         fields.
1881         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm3_11_INDEX operand.
1882
1883 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1884
1885         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1886         sve_size_hsd2 iclass encode.
1887         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1888         sve_size_hsd2 iclass decode.
1889         * aarch64-opc.c (fields): Handle SVE_size field.
1890         * aarch64-opc.h (enum aarch64_field_kind): New SVE_size field.
1891
1892 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1893
1894         * aarch64-asm-2.c: Regenerated.
1895         * aarch64-dis-2.c: Regenerated.
1896         * aarch64-opc-2.c: Regenerated.
1897         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1898         for SVE_IMM_ROT3.
1899         (aarch64_print_operand): Add printing for SVE_IMM_ROT3.
1900         (fields): Handle SVE_rot3 field.
1901         * aarch64-opc.h (enum aarch64_field_kind): New SVE_rot3 field.
1902         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_IMM_ROT3 operand.
1903
1904 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1905
1906         * aarch64-opc.c (verify_constraints): Check for movprfx for sve2
1907         instructions.
1908
1909 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1910
1911         * aarch64-tbl.h
1912         (aarch64_feature_sve2, aarch64_feature_sve2aes,
1913         aarch64_feature_sve2sha3, aarch64_feature_sve2sm4,
1914         aarch64_feature_sve2bitperm): New feature sets.
1915         (SVE2, SVE2_AES, SVE2_SHA3, SVE2_SM4, SVE2_BITPERM): New macros
1916         for feature set addresses.
1917         (SVE2_INSN, SVE2_INSNC, SVE2AES_INSN, SVE2SHA3_INSN,
1918         SVE2SM4_INSN, SVE2SM4_INSNC, SVE2BITPERM_INSN): New macros.
1919
1920 2019-05-06  Andrew Bennett  <andrew.bennett@imgtec.com>
1921             Faraz Shahbazker  <fshahbazker@wavecomp.com>
1922
1923         * mips-dis.c (mips_calculate_combination_ases): Add ISA
1924         argument and set ASE_EVA_R6 appropriately.
1925         (set_default_mips_dis_options): Pass ISA to above.
1926         (parse_mips_dis_option): Likewise.
1927         * mips-opc.c (EVAR6): New macro.
1928         (mips_builtin_opcodes): Add llwpe, scwpe.
1929
1930 2019-05-01  Sudakshina Das  <sudi.das@arm.com>
1931
1932         * aarch64-asm-2.c: Regenerated.
1933         * aarch64-dis-2.c: Regenerated.
1934         * aarch64-opc-2.c: Regenerated.
1935         * aarch64-opc.c (operand_general_constraint_met_p): Add case for
1936         AARCH64_OPND_TME_UIMM16.
1937         (aarch64_print_operand): Likewise.
1938         * aarch64-tbl.h (QL_IMM_NIL): New.
1939         (TME): New.
1940         (_TME_INSN): New.
1941         (struct aarch64_opcode): Add tstart, tcommit, ttest and tcancel.
1942
1943 2019-04-29  John Darrington  <john@darrington.wattle.id.au>
1944
1945         * s12z-opc.c (shift_discrim): Return OP_INVALID when reading fails.
1946
1947 2019-04-26  Andrew Bennett  <andrew.bennett@imgtec.com>
1948             Faraz Shahbazker  <fshahbazker@wavecomp.com>
1949
1950         * mips-opc.c (mips_builtin_opcodes): Add llwp, lldp, scwp, scdp.
1951
1952 2019-04-24  John Darrington  <john@darrington.wattle.id.au>
1953
1954         * s12z-opc.h: Add extern "C" bracketing to help
1955         users who wish to use this interface in c++ code.
1956
1957 2019-04-24  John Darrington  <john@darrington.wattle.id.au>
1958
1959         * s12z-opc.c (bm_decode): Handle bit map operations with the
1960         "reserved0" mode.
1961
1962 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1963
1964         * arm-dis.c (coprocessor_opcodes): Document new %J and %K format
1965         specifier.  Add entries for VLDR and VSTR of system registers.
1966         (print_insn_coprocessor): Forbid coprocessor numbers 8, 14 and 15 in
1967         coprocessor instructions on Armv8.1-M Mainline targets.  Add handling
1968         of %J and %K format specifier.
1969
1970 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1971
1972         * arm-dis.c (coprocessor_opcodes): Document new %C format control code.
1973         Add new entries for VSCCLRM instruction.
1974         (print_insn_coprocessor): Handle new %C format control code.
1975
1976 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1977
1978         * arm-dis.c (enum isa): New enum.
1979         (struct sopcode32): New structure.
1980         (coprocessor_opcodes): change type of entries to struct sopcode32 and
1981         set isa field of all current entries to ANY.
1982         (print_insn_coprocessor): Change type of insn to struct sopcode32.
1983         Only match an entry if its isa field allows the current mode.
1984
1985 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1986
1987         * arm-dis.c (thumb_opcodes): Document %n control code.  Add entry for
1988         CLRM.
1989         (print_insn_thumb32): Add logic to print %n CLRM register list.
1990
1991 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1992
1993         * arm-dis.c (print_insn_thumb32): Updated to accept new %P
1994         and %Q patterns.
1995
1996 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1997
1998         * arm-dis.c (thumb32_opcodes): New instruction bfcsel.
1999         (print_insn_thumb32): Edit the switch case for %Z.
2000
2001 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
2002
2003         * arm-dis.c (print_insn_thumb32): Updated to accept new %Z pattern.
2004
2005 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
2006
2007         * arm-dis.c (thumb32_opcodes): New instruction bfl.
2008
2009 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
2010
2011         * arm-dis.c (print_insn_thumb32): Updated to accept new %Y pattern.
2012
2013 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
2014
2015         * arm-dis.c (print_insn_thumb32): Add '%<bitfield>S' to print an
2016         Arm register with r13 and r15 unpredictable.
2017         (thumb32_opcodes): New instructions for bfx and bflx.
2018
2019 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
2020
2021         * arm-dis.c (thumb32_opcodes): New instructions for bf.
2022
2023 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
2024
2025         * arm-dis.c (print_insn_thumb32): Updated to accept new %W pattern.
2026
2027 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
2028
2029         * arm-dis.c (print_insn_thumb32): Updated to accept new %G pattern.
2030
2031 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
2032
2033         * arm-dis.c (select_arm_features): Add logic for Armv8.1-M Mainline.
2034
2035 2019-04-12  John Darrington <john@darrington.wattle.id.au>
2036
2037         s12z-dis.c, s12z-opc.c, s12z-opc.h: Replace "operator" with
2038         "optr". ("operator" is a reserved word in c++).
2039
2040 2019-04-11  Sudakshina Das  <sudi.das@arm.com>
2041
2042         * aarch64-opc.c (aarch64_print_operand): Add case for
2043         AARCH64_OPND_Rt_SP.
2044         (verify_constraints): Likewise.
2045         * aarch64-tbl.h (QL_LDST_AT): Update to add SP qualifier.
2046         (struct aarch64_opcode): Update stg, stzg, st2g, stz2g instructions
2047         to accept Rt|SP as first operand.
2048         (AARCH64_OPERANDS): Add new Rt_SP.
2049         * aarch64-asm-2.c: Regenerated.
2050         * aarch64-dis-2.c: Regenerated.
2051         * aarch64-opc-2.c: Regenerated.
2052
2053 2019-04-11  Sudakshina Das  <sudi.das@arm.com>
2054
2055         * aarch64-asm-2.c: Regenerated.
2056         * aarch64-dis-2.c: Likewise.
2057         * aarch64-opc-2.c: Likewise.
2058         * aarch64-tbl.h (aarch64_opcode): Add new ldgm and stgm.
2059
2060 2019-04-09  Robert Suchanek  <robert.suchanek@mips.com>
2061
2062         * mips-opc.c (mips_builtin_opcodes): Add RDHWR rt rd sel.
2063
2064 2019-04-08  H.J. Lu  <hongjiu.lu@intel.com>
2065
2066         * i386-opc.tbl: Consolidate AVX512 BF16 entries.
2067         * i386-init.h: Regenerated.
2068
2069 2019-04-07  Alan Modra  <amodra@gmail.com>
2070
2071         * ppc-dis.c (print_insn_powerpc): Use a tiny state machine
2072         op_separator to control printing of spaces, comma and parens
2073         rather than need_comma, need_paren and spaces vars.
2074
2075 2019-04-07  Alan Modra  <amodra@gmail.com>
2076
2077         PR 24421
2078         * arm-dis.c (print_insn_coprocessor): Correct bracket placement.
2079         (print_insn_neon, print_insn_arm): Likewise.
2080
2081 2019-04-05  Xuepeng Guo  <xuepeng.guo@intel.com>
2082
2083         * i386-dis-evex.h (evex_table): Updated to support BF16
2084         instructions.
2085         * i386-dis.c (enum): Add EVEX_W_0F3852_P_1, EVEX_W_0F3872_P_1
2086         and EVEX_W_0F3872_P_3.
2087         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_BF16_FLAGS.
2088         (cpu_flags): Add bitfield for CpuAVX512_BF16.
2089         * i386-opc.h (enum): Add CpuAVX512_BF16.
2090         (i386_cpu_flags): Add bitfield for cpuavx512_bf16.
2091         * i386-opc.tbl: Add AVX512 BF16 instructions.
2092         * i386-init.h: Regenerated.
2093         * i386-tbl.h: Likewise.
2094
2095 2019-04-05  Alan Modra  <amodra@gmail.com>
2096
2097         * ppc-opc.c (XLBH_MASK): Subtract off BH field from BB_MASK.
2098         (powerpc_opcodes): Reorder bcctr and bclr extended mnemonics
2099         to favour printing of "-" branch hint when using the "y" bit.
2100         Allow BH field on bc{ctr,lr,tar}{,l}{-,+}.
2101
2102 2019-04-05  Alan Modra  <amodra@gmail.com>
2103
2104         * ppc-dis.c (print_insn_powerpc): Delay printing spaces after
2105         opcode until first operand is output.
2106
2107 2019-04-04  Peter Bergner  <bergner@linux.ibm.com>
2108
2109         PR gas/24349
2110         * ppc-opc.c (valid_bo_pre_v2): Add comments.
2111         (valid_bo_post_v2): Add support for 'at' branch hints.
2112         (insert_bo): Only error on branch on ctr.
2113         (get_bo_hint_mask): New function.
2114         (insert_boe): Add new 'branch_taken' formal argument.  Add support
2115         for inserting 'at' branch hints.
2116         (extract_boe): Add new 'branch_taken' formal argument.  Add support
2117         for extracting 'at' branch hints.
2118         (insert_bom, extract_bom, insert_bop, extract_bop): New functions.
2119         (BOE): Delete operand.
2120         (BOM, BOP): New operands.
2121         (RM): Update value.
2122         (XLYLK, XLYLK_MASK, XLYBB_MASK): Delete.
2123         (powerpc_opcodes) <bc-, bcl-, bca-, bcla-, bclr-, bclrl-, bcctr-,
2124         bcctrl-, bctar-, bctarl->: Replace BOE with BOM.
2125         (powerpc_opcodes) <bc+, bcl+, bca+, bcla+, bclr+, bclrl+, bcctr+,
2126         bcctrl+, bctar+, bctarl+>: Replace BOE with BOP.
2127         <bdnztar, bdnztarl, bdztar, bdztarl, btar, btarl, bdnztar-, bdnztarl-,
2128         bdnztar+, bdnztarl+, bdztar-, bdztarl-, bdztar+, bdztarl+, bgetar,
2129         bnltar, bgetarl, bnltarl, bletar, bngtar, bletarl, bngtarl, bnetar,
2130         bnetarl, bnstar, bnutar, bnstarl, bnutarl, bgetar-, bnltar-, bgetarl-,
2131         bnltarl-, bletar-, bngtar-, bletarl-, bngtarl-, bnetar-, bnetarl-,
2132         bnstar-, bnutar-, bnstarl-, bnutarl-, bgetar+, bnltar+, bgetarl+,
2133         bnltarl+, bletar+, bngtar+, bletarl+, bngtarl+, bnetar+, bnetarl+,
2134         bnstar+, bnutar+, bnstarl+, bnutarl+, blttar, blttarl, bgttar, bgttarl,
2135         beqtar, beqtarl, bsotar, buntar, bsotarl, buntarl, blttar-, blttarl-,
2136         bgttar-, bgttarl-, beqtar-, beqtarl-, bsotar-, buntar-, bsotarl-,
2137         buntarl-, blttar+, blttarl+, bgttar+, bgttarl+, beqtar+, beqtarl+,
2138         bsotar+, buntar+, bsotarl+, buntarl+, bdnzftar, bdnzftarl, bdzftar,
2139         bdzftarl, bftar, bftarl, bftar-, bftarl-, bftar+, bftarl+, bdnzttar,
2140         bdnzttarl, bdzttar, bdzttarl, bttar, bttarl, bttar-, bttarl-, bttar+,
2141         bttarl+>: New extended mnemonics.
2142
2143 2019-03-28  Alan Modra  <amodra@gmail.com>
2144
2145         PR 24390
2146         * ppc-opc.c (BTF): Define.
2147         (powerpc_opcodes): Use for mtfsb*.
2148         * ppc-dis.c (print_insn_powerpc): Print fields with both
2149         PPC_OPERAND_CR_REG and PPC_OPERAND_CR_BIT as a plain number.
2150
2151 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
2152
2153         * arm-dis.c (struct arm_private_data): Remove has_mapping_symbols.
2154         (mapping_symbol_for_insn): Implement new algorithm.
2155         (print_insn): Remove duplicate code.
2156
2157 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
2158
2159         * aarch64-dis.c (print_insn_aarch64):
2160         Implement override.
2161
2162 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
2163
2164         * aarch64-dis.c (print_insn_aarch64): Update the mapping symbol search
2165         order.
2166
2167 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
2168
2169         * aarch64-dis.c (last_stop_offset): New.
2170         (print_insn_aarch64): Use stop_offset.
2171
2172 2019-03-19  H.J. Lu  <hongjiu.lu@intel.com>
2173
2174         PR gas/24359
2175         * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS to
2176         CPU_ANY_AVX2_FLAGS.
2177         * i386-init.h: Regenerated.
2178
2179 2019-03-18  H.J. Lu  <hongjiu.lu@intel.com>
2180
2181         PR gas/24348
2182         * i386-opc.tbl: Add Optimize to vmovdqa32, vmovdqa64, vmovdqu8,
2183         vmovdqu16, vmovdqu32 and vmovdqu64.
2184         * i386-tbl.h: Regenerated.
2185
2186 2019-03-12  Andreas Krebbel  <krebbel@linux.ibm.com>
2187
2188         * s390-opc.txt: Rename selhhhr to selfhr.  Remove optional operand
2189         from vstrszb, vstrszh, and vstrszf.
2190
2191 2019-03-12  Andreas Krebbel  <krebbel@linux.ibm.com>
2192
2193         * s390-opc.txt: Add instruction descriptions.
2194
2195 2019-02-08  Jim Wilson  <jimw@sifive.com>
2196
2197         * riscv-opc.c (riscv_opcodes) <beq>: Use Cz to compress 3 operand form.
2198         <bne>: Likewise.
2199
2200 2019-02-07  Tamar Christina  <tamar.christina@arm.com>
2201
2202         * arm-dis.c (arm_opcodes): Redefine hlt to armv1.
2203
2204 2019-02-07  Tamar Christina  <tamar.christina@arm.com>
2205
2206         PR binutils/23212
2207         * aarch64-opc.h (enum aarch64_field_kind): Add FLD_sz.
2208         * aarch64-opc.c (verify_elem_sd): New.
2209         (fields): Add FLD_sz entr.
2210         * aarch64-tbl.h (_SIMD_INSN): New.
2211         (aarch64_opcode_table): Add elem_sd verifier to fmla, fmls, fmul and
2212         fmulx scalar and vector by element isns.
2213
2214 2019-02-07  Nick Clifton  <nickc@redhat.com>
2215
2216         * po/sv.po: Updated Swedish translation.
2217
2218 2019-01-31  Andreas Krebbel  <krebbel@linux.ibm.com>
2219
2220         * s390-mkopc.c (main): Accept arch13 as cpu string.
2221         * s390-opc.c: Add new instruction formats and instruction opcode
2222         masks.
2223         * s390-opc.txt: Add new arch13 instructions.
2224
2225 2019-01-25  Sudakshina Das  <sudi.das@arm.com>
2226
2227         * aarch64-tbl.h (QL_LDST_AT): Update macro.
2228         (aarch64_opcode): Change encoding for stg, stzg
2229         st2g and st2zg.
2230         * aarch64-asm-2.c: Regenerated.
2231         * aarch64-dis-2.c: Regenerated.
2232         * aarch64-opc-2.c: Regenerated.
2233
2234 2019-01-25  Sudakshina Das  <sudi.das@arm.com>
2235
2236         * aarch64-asm-2.c: Regenerated.
2237         * aarch64-dis-2.c: Likewise.
2238         * aarch64-opc-2.c: Likewise.
2239         * aarch64-tbl.h (aarch64_opcode): Add new stzgm.
2240
2241 2019-01-25  Sudakshina Das  <sudi.das@arm.com>
2242             Ramana Radhakrishnan  <ramana.radhakrishnan@arm.com>
2243
2244         * aarch64-asm.c (aarch64_ins_addr_simple_2): Remove.
2245         * aarch64-asm.h (ins_addr_simple_2): Likeiwse.
2246         * aarch64-dis.c (aarch64_ext_addr_simple_2): Likewise.
2247         * aarch64-dis.h (ext_addr_simple_2): Likewise.
2248         * aarch64-opc.c (operand_general_constraint_met_p): Remove
2249         case for ldstgv_indexed.
2250         (aarch64_print_operand): Remove case for AARCH64_OPND_ADDR_SIMPLE_2.
2251         * aarch64-tbl.h (struct aarch64_opcode): Remove ldgv and stgv.
2252         (AARCH64_OPERANDS): Remove ADDR_SIMPLE_2.
2253         * aarch64-asm-2.c: Regenerated.
2254         * aarch64-dis-2.c: Regenerated.
2255         * aarch64-opc-2.c: Regenerated.
2256
2257 2019-01-23  Nick Clifton  <nickc@redhat.com>
2258
2259         * po/pt_BR.po: Updated Brazilian Portuguese translation.
2260
2261 2019-01-21  Nick Clifton  <nickc@redhat.com>
2262
2263         * po/de.po: Updated German translation.
2264         * po/uk.po: Updated Ukranian translation.
2265
2266 2019-01-20  Chenghua Xu  <paul.hua.gm@gmail.com>
2267         * mips-dis.c (mips_arch_choices): Fix typo in
2268         gs464, gs464e and gs264e descriptors.
2269
2270 2019-01-19  Nick Clifton  <nickc@redhat.com>
2271
2272         * configure: Regenerate.
2273         * po/opcodes.pot: Regenerate.
2274
2275 2018-06-24  Nick Clifton  <nickc@redhat.com>
2276
2277         2.32 branch created.
2278
2279 2019-01-09  John Darrington <john@darrington.wattle.id.au>
2280
2281         * s12z-dis.c (print_insn_s12z):  Do not dereference an operand
2282         if it is null.
2283         -dis.c (opr_emit_disassembly): Do not omit an index if it is
2284         zero.
2285
2286 2019-01-09  Andrew Paprocki  <andrew@ishiboo.com>
2287
2288         * configure: Regenerate.
2289
2290 2019-01-07  Alan Modra  <amodra@gmail.com>
2291
2292         * configure: Regenerate.
2293         * po/POTFILES.in: Regenerate.
2294
2295 2019-01-03  John Darrington <john@darrington.wattle.id.au>
2296
2297         * s12z-opc.c: New file.
2298         * s12z-opc.h: New file.
2299         * s12z-dis.c: Removed all code not directly related to display
2300         of instructions.  Used the interface provided by the new files
2301         instead.
2302         * Makefile.am (TARGET_LIBOPCODES_CFILES) Add s12z-opc.c.
2303         * Makefile.in: Regenerate.
2304         * configure.ac (bfd_s12z_arch): Correct the dependencies.
2305         * configure: Regenerate.
2306
2307 2019-01-01  Alan Modra  <amodra@gmail.com>
2308
2309         Update year range in copyright notice of all files.
2310
2311 For older changes see ChangeLog-2018
2312 \f
2313 Copyright (C) 2019 Free Software Foundation, Inc.
2314
2315 Copying and distribution of this file, with or without modification,
2316 are permitted in any medium without royalty provided the copyright
2317 notice and this notice are preserved.
2318
2319 Local Variables:
2320 mode: change-log
2321 left-margin: 8
2322 fill-column: 74
2323 version-control: never
2324 End: