opcodes/ChangeLog

   1 2020-06-26  H.J. Lu  <hongjiu.lu@intel.com>
   2
   3         * i386-gen.c (opcode_modifiers): Replace VecSIB with SIB.
   4         (VecSIB128): Renamed to ...
   5         (VECSIB128): This.
   6         (VecSIB256): Renamed to ...
   7         (VECSIB256): This.
   8         (VecSIB512): Renamed to ...
   9         (VECSIB512): This.
  10         (VecSIB): Renamed to ...
  11         (SIB): This.
  12         (i386_opcode_modifier): Replace vecsib with sib.
  13         * i386-opc.tbl (VexSIB128): New.
  14         (VecSIB256): Likewise.
  15         (VecSIB512): Likewise.
  16         Replace VecSIB=1, VecSIB=2 and VecSIB=3 with VexSIB128, VecSIB256
  17         and VecSIB512, respectively.
  18
  19 2020-06-26  Jan Beulich  <jbeulich@suse.com>
  20
  21         * i386-dis.c: Adjust description of I macro.
  22         (x86_64_table): Drop use of I.
  23         (float_mem): Replace use of I.
  24         (putop): Remove handling of I. Adjust setting/clearing of "alt".
  25
  26 2020-06-26  Jan Beulich  <jbeulich@suse.com>
  27
  28         * i386-dis.c: (print_insn): Avoid straight assignment to
  29         priv.orig_sizeflag when processing -M sub-options.
  30
  31 2020-06-25  Jan Beulich  <jbeulich@suse.com>
  32
  33         * i386-dis.c: Adjust description of J macro.
  34         (dis386, x86_64_table, mod_table): Replace J.
  35         (putop): Remove handling of J.
  36
  37 2020-06-25  Jan Beulich  <jbeulich@suse.com>
  38
  39         * i386-dis.c: (float_mem): Reduce alternatives for fstpt and fldpt.
  40
  41 2020-06-25  Jan Beulich  <jbeulich@suse.com>
  42
  43         * i386-dis.c: Adjust description of "LQ" macro.
  44         (dis386_twobyte): Use LQ for sysret.
  45         (putop): Adjust handling of LQ.
  46
  47 2020-06-22  Nelson Chu  <nelson.chu@sifive.com>
  48
  49         * riscv-opc.c: Move the structures and functions to bfd/elfxx-riscv.c.
  50         * riscv-dis.c: Include elfxx-riscv.h.
  51
  52 2020-06-18  H.J. Lu  <hongjiu.lu@intel.com>
  53
  54         * i386-dis.c (prefix_table): Revert the last vmgexit change.
  55
  56 2020-06-17  Lili Cui  <lili.cui@intel.com>
  57
  58         * i386-dis.c (prefix_table): Delete the incorrect vmgexit.
  59
  60 2020-06-14  H.J. Lu  <hongjiu.lu@intel.com>
  61
  62         PR gas/26115
  63         * i386-dis.c (prefix_table): Replace xsuspldtrk with xsusldtrk.
  64         * i386-opc.tbl: Likewise.
  65         * i386-tbl.h: Regenerated.
  66
  67 2020-06-12  Nelson Chu  <nelson.chu@sifive.com>
  68
  69         * riscv-opc.c (priv_specs): Remove v1.9 and PRIV_SPEC_CLASS_1P9.
  70
  71 2020-06-11  Alex Coplan  <alex.coplan@arm.com>
  72
  73         * aarch64-opc.c (SYSREG): New macro for describing system registers.
  74         (SR_CORE): Likewise.
  75         (SR_FEAT): Likewise.
  76         (SR_RNG): Likewise.
  77         (SR_V8_1): Likewise.
  78         (SR_V8_2): Likewise.
  79         (SR_V8_3): Likewise.
  80         (SR_V8_4): Likewise.
  81         (SR_PAN): Likewise.
  82         (SR_RAS): Likewise.
  83         (SR_SSBS): Likewise.
  84         (SR_SVE): Likewise.
  85         (SR_ID_PFR2): Likewise.
  86         (SR_PROFILE): Likewise.
  87         (SR_MEMTAG): Likewise.
  88         (SR_SCXTNUM): Likewise.
  89         (aarch64_sys_regs): Refactor to store feature information in the table.
  90         (aarch64_sys_reg_supported_p): Collapse logic for system registers
  91         that now describe their own features.
  92         (aarch64_pstatefield_supported_p): Likewise.
  93
  94 2020-06-09  H.J. Lu  <hongjiu.lu@intel.com>
  95
  96         * i386-dis.c (prefix_table): Fix a typo in comments.
  97
  98 2020-06-09  Jan Beulich  <jbeulich@suse.com>
  99
 100         * i386-dis.c (rex_ignored): Delete.
 101         (ckprefix): Drop rex_ignored initialization.
 102         (get_valid_dis386): Drop setting of rex_ignored.
 103         (print_insn): Drop checking of rex_ignored. Don't record data
 104         size prefix as used with VEX-and-alike encodings.
 105
 106 2020-06-09  Jan Beulich  <jbeulich@suse.com>
 107
 108         * i386-dis.c (MOD_0F12_PREFIX_2, MOD_0F16_PREFIX_2,
 109         MOD_VEX_0F12_PREFIX_2, MOD_VEX_0F16_PREFIX_2): New enumerators.
 110         (VEX_LEN_0F12_P_2, VEX_LEN_0F16_P_2): Delete.
 111         (VEX_LEN_0F12_P_2_M_0, VEX_LEN_0F16_P_2_M_0): Define.
 112         (prefix_table): Decode MOD for cases 2 of opcodes 0F12, 0F16,
 113         VEX_0F12, and VEX_0F16.
 114         (vex_len_table): Use X for vmovlp* and vmovh*s. Drop
 115         VEX_LEN_0F12_P_2 and VEX_LEN_0F16_P_2 entries.
 116         (mod_table): Use X for movlpX and movhpX. Drop PREFIX_OPCODE
 117         from movlps and movhlps. New MOD_0F12_PREFIX_2,
 118         MOD_0F16_PREFIX_2, MOD_VEX_0F12_PREFIX_2, and
 119         MOD_VEX_0F16_PREFIX_2 entries.
 120
 121 2020-06-09  Jan Beulich  <jbeulich@suse.com>
 122
 123         * i386-dis.c (MOD_EVEX_0F12_PREFIX_2, MOD_EVEX_0F13,
 124         MOD_EVEX_0F16_PREFIX_2, MOD_EVEX_0F17, MOD_EVEX_0F2B): New enumerators.
 125         (PREFIX_EVEX_0F13, PREFIX_EVEX_0F14, PREFIX_EVEX_0F15,
 126         PREFIX_EVEX_0F17, PREFIX_EVEX_0F28, PREFIX_EVEX_0F29,
 127         PREFIX_EVEX_0F2B, PREFIX_EVEX_0F54, PREFIX_EVEX_0F55,
 128         PREFIX_EVEX_0F56, PREFIX_EVEX_0F57, PREFIX_EVEX_0FC6,
 129         EVEX_W_0F10_P_0, EVEX_W_0F10_P_2, EVEX_W_0F11_P_0,
 130         EVEX_W_0F11_P_2, EVEX_W_0F12_P_0_M_0, EVEX_W_0F12_P_2,
 131         EVEX_W_0F13_P_0, EVEX_W_0F13_P_2, EVEX_W_0F14_P_0,
 132         EVEX_W_0F14_P_2, EVEX_W_0F15_P_0, EVEX_W_0F15_P_2,
 133         EVEX_W_0F16_P_0_M_0, EVEX_W_0F16_P_2, EVEX_W_0F17_P_0,
 134         EVEX_W_0F17_P_2, EVEX_W_0F28_P_0, EVEX_W_0F28_P_2,
 135         EVEX_W_0F29_P_0, EVEX_W_0F29_P_2, EVEX_W_0F2B_P_0,
 136         EVEX_W_0F2B_P_2, EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2,
 137         EVEX_W_0F2F_P_0, EVEX_W_0F2F_P_2, EVEX_W_0F51_P_0,
 138         EVEX_W_0F51_P_2, EVEX_W_0F54_P_0, EVEX_W_0F54_P_2,
 139         EVEX_W_0F55_P_0, EVEX_W_0F55_P_2, EVEX_W_0F56_P_0,
 140         EVEX_W_0F56_P_2, EVEX_W_0F57_P_0, EVEX_W_0F57_P_2,
 141         EVEX_W_0F58_P_0, EVEX_W_0F58_P_2, EVEX_W_0F59_P_0,
 142         EVEX_W_0F59_P_2, EVEX_W_0F5C_P_0, EVEX_W_0F5C_P_2,
 143         EVEX_W_0F5D_P_0, EVEX_W_0F5D_P_2, EVEX_W_0F5E_P_0,
 144         EVEX_W_0F5E_P_2, EVEX_W_0F5F_P_0, EVEX_W_0F5F_P_2,
 145         EVEX_W_0FC2_P_0, EVEX_W_0FC2_P_2, EVEX_W_0FC6_P_0,
 146         EVEX_W_0FC6_P_2): Delete.
 147         (print_insn): Add EVEX.W vs embedded prefix consistency check
 148         to prefix validation.
 149         * i386-dis-evex.h (evex_table): Don't further descend for
 150         vunpcklpX, vunpckhpX, vmovapX, vandpX, vandnpX, vorpX, vxorpX,
 151         and vshufpX. Continue with MOD decoding for opcodes 0F13, 0F17,
 152         and 0F2B.
 153         * i386-dis-evex-mod.h: Add/adjust vmovlpX/vmovhpX entries.
 154         * i386-dis-evex-prefix.h: Don't further descend for vmovupX,
 155         vucomisX, vcomisX, vsqrtpX, vaddpX, vmulpX, vsubpX, vminpX,
 156         vdivpX, vmaxpX, and vcmppX. Continue with MOD decoding for cases
 157         2 of PREFIX_EVEX_0F12, PREFIX_EVEX_0F16, and PREFIX_EVEX_0F29.
 158         Drop PREFIX_EVEX_0F13, PREFIX_EVEX_0F14, PREFIX_EVEX_0F15,
 159         PREFIX_EVEX_0F17, PREFIX_EVEX_0F28, PREFIX_EVEX_0F2B,
 160         PREFIX_EVEX_0F54, PREFIX_EVEX_0F55, PREFIX_EVEX_0F56,
 161         PREFIX_EVEX_0F57, and PREFIX_EVEX_0FC6 entries.
 162         * i386-dis-evex-w.h: Drop EVEX_W_0F10_P_0, EVEX_W_0F10_P_2,
 163         EVEX_W_0F11_P_0, EVEX_W_0F11_P_2, EVEX_W_0F12_P_0_M_0,
 164         EVEX_W_0F12_P_2, EVEX_W_0F12_P_3, EVEX_W_0F13_P_0,
 165         EVEX_W_0F13_P_2, EVEX_W_0F14_P_0, EVEX_W_0F14_P_2,
 166         EVEX_W_0F15_P_0, EVEX_W_0F15_P_2, EVEX_W_0F16_P_0_M_0,
 167         EVEX_W_0F16_P_2, EVEX_W_0F17_P_0, EVEX_W_0F17_P_2,
 168         EVEX_W_0F28_P_0, EVEX_W_0F28_P_2, EVEX_W_0F29_P_0,
 169         EVEX_W_0F29_P_2, EVEX_W_0F2B_P_0, EVEX_W_0F2B_P_2,
 170         EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2, EVEX_W_0F2F_P_0,
 171         EVEX_W_0F2F_P_2, EVEX_W_0F51_P_0, EVEX_W_0F51_P_2,
 172         EVEX_W_0F54_P_0, EVEX_W_0F54_P_2, EVEX_W_0F55_P_0,
 173         EVEX_W_0F55_P_2, EVEX_W_0F56_P_0, EVEX_W_0F56_P_2,
 174         EVEX_W_0F57_P_0, EVEX_W_0F57_P_2, EVEX_W_0F58_P_0,
 175         EVEX_W_0F58_P_2, EVEX_W_0F59_P_0, EVEX_W_0F59_P_2,
 176         EVEX_W_0F5C_P_0, EVEX_W_0F5C_P_2, EVEX_W_0F5D_P_0,
 177         EVEX_W_0F5D_P_2, EVEX_W_0F5E_P_0, EVEX_W_0F5E_P_2,
 178         EVEX_W_0F5F_P_0, EVEX_W_0F5F_P_2, EVEX_W_0FC2_P_0,
 179         EVEX_W_0FC2_P_2, EVEX_W_0FC6_P_0, and EVEX_W_0FC6_P_2 entries.
 180
 181 2020-06-09  Jan Beulich  <jbeulich@suse.com>
 182
 183         * i386-dis.c (vex_table): Use PREFIX_OPCODE for vunpcklpX,
 184         vunpckhpX, vmovapX, vandpX, vandnpX, vorpX, vxorpX and vshufpX.
 185         (vex_len_table) : Likewise for vmovlpX, vmovhpX, vmovntpX, and
 186         vmovmskpX.
 187         (print_insn): Drop pointless check against bad_opcode. Split
 188         prefix validation into legacy and VEX-and-alike parts.
 189         (putop): Re-work 'X' macro handling.
 190
 191 2020-06-09  Jan Beulich  <jbeulich@suse.com>
 192
 193         * i386-dis.c (MOD_0F51): Rename to ...
 194         (MOD_0F50): ... this.
 195
 196 2020-06-08  Alex Coplan  <alex.coplan@arm.com>
 197
 198         * arm-dis.c (arm_opcodes): Add dfb.
 199         (thumb32_opcodes): Add dfb.
 200
 201 2020-06-08  Jan Beulich  <jbeulich@suse.com>
 202
 203         * i386-opc.h (reg_entry): Const-qualify reg_name field.
 204
 205 2020-06-06  Alan Modra  <amodra@gmail.com>
 206
 207         * ppc-dis.c (ppc_opts): Accept -mpwr10/-Mpwr10.
 208
 209 2020-06-05  Alan Modra  <amodra@gmail.com>
 210
 211         * cgen-dis.c (hash_insn_array): Increase size of buf.  Assert
 212         size is large enough.
 213
 214 2020-06-04  Jose E. Marchesi  <jose.marchesi@oracle.com>
 215
 216         * disassemble.c (disassemble_init_for_target): Set endian_code for
 217         bpf targets.
 218         * bpf-desc.c: Regenerate.
 219         * bpf-opc.c: Likewise.
 220         * bpf-dis.c: Likewise.
 221
 222 2020-06-03  Jose E. Marchesi  <jose.marchesi@oracle.com>
 223
 224         * cgen-opc.c (cgen_get_insn_value): Get an `endian' argument.
 225         (cgen_put_insn_value): Likewise.
 226         (cgen_lookup_insn): Pass endianness to cgen_{get,put}_insn_value.
 227         * cgen-dis.in (print_insn): Likewise.
 228         * cgen-ibld.in (insert_1): Likewise.
 229         (insert_1): Likewise.
 230         (insert_insn_normal): Likewise.
 231         (extract_1): Likewise.
 232         * bpf-dis.c: Regenerate.
 233         * bpf-ibld.c: Likewise.
 234         * bpf-ibld.c: Likewise.
 235         * cgen-dis.in: Likewise.
 236         * cgen-ibld.in: Likewise.
 237         * cgen-opc.c: Likewise.
 238         * epiphany-dis.c: Likewise.
 239         * epiphany-ibld.c: Likewise.
 240         * fr30-dis.c: Likewise.
 241         * fr30-ibld.c: Likewise.
 242         * frv-dis.c: Likewise.
 243         * frv-ibld.c: Likewise.
 244         * ip2k-dis.c: Likewise.
 245         * ip2k-ibld.c: Likewise.
 246         * iq2000-dis.c: Likewise.
 247         * iq2000-ibld.c: Likewise.
 248         * lm32-dis.c: Likewise.
 249         * lm32-ibld.c: Likewise.
 250         * m32c-dis.c: Likewise.
 251         * m32c-ibld.c: Likewise.
 252         * m32r-dis.c: Likewise.
 253         * m32r-ibld.c: Likewise.
 254         * mep-dis.c: Likewise.
 255         * mep-ibld.c: Likewise.
 256         * mt-dis.c: Likewise.
 257         * mt-ibld.c: Likewise.
 258         * or1k-dis.c: Likewise.
 259         * or1k-ibld.c: Likewise.
 260         * xc16x-dis.c: Likewise.
 261         * xc16x-ibld.c: Likewise.
 262         * xstormy16-dis.c: Likewise.
 263         * xstormy16-ibld.c: Likewise.
 264
 265 2020-06-04  Jose E. Marchesi  <jemarch@gnu.org>
 266
 267         * cgen-dis.in (cpu_desc_list): New field `insn_endian'.
 268         (print_insn_): Handle instruction endian.
 269         * bpf-dis.c: Regenerate.
 270         * bpf-desc.c: Regenerate.
 271         * epiphany-dis.c: Likewise.
 272         * epiphany-desc.c: Likewise.
 273         * fr30-dis.c: Likewise.
 274         * fr30-desc.c: Likewise.
 275         * frv-dis.c: Likewise.
 276         * frv-desc.c: Likewise.
 277         * ip2k-dis.c: Likewise.
 278         * ip2k-desc.c: Likewise.
 279         * iq2000-dis.c: Likewise.
 280         * iq2000-desc.c: Likewise.
 281         * lm32-dis.c: Likewise.
 282         * lm32-desc.c: Likewise.
 283         * m32c-dis.c: Likewise.
 284         * m32c-desc.c: Likewise.
 285         * m32r-dis.c: Likewise.
 286         * m32r-desc.c: Likewise.
 287         * mep-dis.c: Likewise.
 288         * mep-desc.c: Likewise.
 289         * mt-dis.c: Likewise.
 290         * mt-desc.c: Likewise.
 291         * or1k-dis.c: Likewise.
 292         * or1k-desc.c: Likewise.
 293         * xc16x-dis.c: Likewise.
 294         * xc16x-desc.c: Likewise.
 295         * xstormy16-dis.c: Likewise.
 296         * xstormy16-desc.c: Likewise.
 297
 298 2020-06-03  Nick Clifton  <nickc@redhat.com>
 299
 300         * po/sr.po: Updated Serbian translation.
 301
 302 2020-06-03  Nelson Chu  <nelson.chu@sifive.com>
 303
 304         * riscv-opc.c (riscv_get_isa_spec_class): Change bfd_boolean to int.
 305         (riscv_get_priv_spec_class): Likewise.
 306
 307 2020-06-01  Alan Modra  <amodra@gmail.com>
 308
 309         * bpf-desc.c: Regenerate.
 310
 311 2020-05-28  Jose E. Marchesi  <jose.marchesi@oracle.com>
 312             David Faust <david.faust@oracle.com>
 313
 314         * bpf-desc.c: Regenerate.
 315         * bpf-opc.h: Likewise.
 316         * bpf-opc.c: Likewise.
 317         * bpf-dis.c: Likewise.
 318
 319 2020-05-28  Alan Modra  <amodra@gmail.com>
 320
 321         * nios2-dis.c (nios2_print_insn_arg): Avoid shift left of negative
 322         values.
 323
 324 2020-05-28  Alan Modra  <amodra@gmail.com>
 325
 326         * ns32k-dis.c (print_insn_arg): Handle d value of 'f' for
 327         immediates.
 328         (print_insn_ns32k): Revert last change.
 329
 330 2020-05-28  Nick Clifton  <nickc@redhat.com>
 331
 332         * ns32k-dis.c (print_insn_ns32k): Change the arg_bufs array to
 333         static.
 334
 335 2020-05-26  Sandra Loosemore  <sandra@codesourcery.com>
 336
 337         Fix extraction of signed constants in nios2 disassembler (again).
 338
 339         * nios2-dis.c (nios2_print_insn_arg): Add explicit casts to
 340         extractions of signed fields.
 341
 342 2020-05-26  Stefan Schulze Frielinghaus  <stefansf@linux.ibm.com>
 343
 344         * s390-opc.txt: Relocate vector load/store instructions with
 345         additional alignment parameter and change architecture level
 346         constraint from z14 to z13.
 347
 348 2020-05-21  Alan Modra  <amodra@gmail.com>
 349
 350         * arc-ext.c: Replace "if (x) free (x)" with "free (x)" throughout.
 351         * sparc-dis.c: Likewise.
 352         * tic4x-dis.c: Likewise.
 353         * xtensa-dis.c: Likewise.
 354         * bpf-desc.c: Regenerate.
 355         * epiphany-desc.c: Regenerate.
 356         * fr30-desc.c: Regenerate.
 357         * frv-desc.c: Regenerate.
 358         * ip2k-desc.c: Regenerate.
 359         * iq2000-desc.c: Regenerate.
 360         * lm32-desc.c: Regenerate.
 361         * m32c-desc.c: Regenerate.
 362         * m32r-desc.c: Regenerate.
 363         * mep-asm.c: Regenerate.
 364         * mep-desc.c: Regenerate.
 365         * mt-desc.c: Regenerate.
 366         * or1k-desc.c: Regenerate.
 367         * xc16x-desc.c: Regenerate.
 368         * xstormy16-desc.c: Regenerate.
 369
 370 2020-05-20  Nelson Chu  <nelson.chu@sifive.com>
 371
 372         * riscv-opc.c (riscv_ext_version_table): The table used to store
 373         all information about the supported spec and the corresponding ISA
 374         versions.  Currently, only Zicsr is supported to verify the
 375         correctness of Z sub extension settings.  Others will be supported
 376         in the future patches.
 377         (struct isa_spec_t, isa_specs): List for all supported ISA spec
 378         classes and the corresponding strings.
 379         (riscv_get_isa_spec_class): New function.  Get the corresponding ISA
 380         spec class by giving a ISA spec string.
 381         * riscv-opc.c (struct priv_spec_t): New structure.
 382         (struct priv_spec_t priv_specs): List for all supported privilege spec
 383         classes and the corresponding strings.
 384         (riscv_get_priv_spec_class): New function.  Get the corresponding
 385         privilege spec class by giving a spec string.
 386         (riscv_get_priv_spec_name): New function.  Get the corresponding
 387         privilege spec string by giving a CSR version class.
 388         * riscv-dis.c: Updated since DECLARE_CSR is changed.
 389         * riscv-dis.c: Add new disassembler option -Mpriv-spec to dump the CSR
 390         according to the chosen version.  Build a hash table riscv_csr_hash to
 391         store the valid CSR for the chosen pirv verison.  Dump the direct
 392         CSR address rather than it's name if it is invalid.
 393         (parse_riscv_dis_option_without_args): New function.  Parse the options
 394         without arguments.
 395         (parse_riscv_dis_option): Call parse_riscv_dis_option_without_args to
 396         parse the options without arguments first, and then handle the options
 397         with arguments.  Add the new option -Mpriv-spec, which has argument.
 398         * riscv-dis.c (print_riscv_disassembler_options): Add description
 399         about the new OBJDUMP option.
 400
 401 2020-05-19  Peter Bergner  <bergner@linux.ibm.com>
 402
 403         * ppc-opc.c (insert_ls, extract_ls): Handle 3-bit L fields and new
 404         WC values on POWER10 sync, dcbf  and wait instructions.
 405         (insert_pl, extract_pl): New functions.
 406         (L2OPT, LS, WC): Use insert_ls and extract_ls.
 407         (LS3): New , 3-bit L for sync.
 408         (LS3, L3OPT): New, 3-bit L for sync and dcbf.
 409         (SC2, PL): New, 2-bit SC and PL for sync and wait.
 410         (XWCPL_MASK, XL3RT_MASK, XSYNCLS_MASK): New instruction masks.
 411         (XOPL3, XWCPL, XSYNCLS): New opcode macros.
 412         (powerpc_opcodes) <dcbflp, dcbfps, dcbstps pause_short, phwsync,
 413         plwsync, stcisync, stncisync, stsync, waitrsv>: New extended mnemonics.
 414         <wait>: Enable PL operand on POWER10.
 415         <dcbf>: Enable L3OPT operand on POWER10.
 416         <sync>: Enable SC2 operand on POWER10.
 417
 418 2020-05-19  Stafford Horne  <shorne@gmail.com>
 419
 420         PR 25184
 421         * or1k-asm.c: Regenerate.
 422         * or1k-desc.c: Regenerate.
 423         * or1k-desc.h: Regenerate.
 424         * or1k-dis.c: Regenerate.
 425         * or1k-ibld.c: Regenerate.
 426         * or1k-opc.c: Regenerate.
 427         * or1k-opc.h: Regenerate.
 428         * or1k-opinst.c: Regenerate.
 429
 430 2020-05-11  Alan Modra  <amodra@gmail.com>
 431
 432         * ppc-opc (powerpc_opcodes): Add xscmpeqqp, xscmpgeqp, xscmpgtqp,
 433         xsmaxcqp, xsmincqp.
 434
 435 2020-05-11  Alan Modra  <amodra@gmail.com>
 436
 437         * ppc-opc.c (powerpc_opcodes): Add lxvrbx, lxvrhx, lxvrwx, lxvrdx,
 438         stxvrbx, stxvrhx, stxvrwx, stxvrdx.
 439
 440 2020-05-11  Alan Modra  <amodra@gmail.com>
 441
 442         * ppc-opc.c (powerpc_opcodes): Add xvtlsbb.
 443
 444 2020-05-11  Alan Modra  <amodra@gmail.com>
 445
 446         * ppc-opc.c (powerpc_opcodes): Add vstribl, vstribr, vstrihl, vstrihr,
 447         vclrlb, vclrrb, vstribl., vstribr., vstrihl., vstrihr..
 448
 449 2020-05-11  Peter Bergner  <bergner@linux.ibm.com>
 450
 451         * ppc-opc.c (powerpc_opcodes) <setbc, setbcr, setnbc, setnbcr>: New
 452         mnemonics.
 453
 454 2020-05-11  Alan Modra  <amodra@gmail.com>
 455
 456         * ppc-opc.c (UIM8, P_U8XX4_MASK): Define.
 457         (powerpc_opcodes): Add vgnb, vcfuged, vpextd, vpdepd, vclzdm,
 458         vctzdm, cntlzdm, pdepd, pextd, cfuged, cnttzdm.
 459         (prefix_opcodes): Add xxeval.
 460
 461 2020-05-11  Alan Modra  <amodra@gmail.com>
 462
 463         * ppc-opc.c (powerpc_opcodes): Add xxgenpcvbm, xxgenpcvhm,
 464         xxgenpcvwm, xxgenpcvdm.
 465
 466 2020-05-11  Alan Modra  <amodra@gmail.com>
 467
 468         * ppc-opc.c (MP, VXVAM_MASK): Define.
 469         (VXVAPS_MASK): Use VXVA_MASK.
 470         (powerpc_opcodes): Add mtvsrbmi, vexpandbm, vexpandhm, vexpandwm,
 471         vexpanddm, vexpandqm, vextractbm, vextracthm, vextractwm,
 472         vextractdm, vextractqm, mtvsrbm, mtvsrhm, mtvsrwm, mtvsrdm, mtvsrqm,
 473         vcntmbb, vcntmbh, vcntmbw, vcntmbd.
 474
 475 2020-05-11  Alan Modra  <amodra@gmail.com>
 476             Peter Bergner  <bergner@linux.ibm.com>
 477
 478         * ppc-opc.c (insert_xa6a, extract_xa6a, insert_xb6a, extract_xb6a):
 479         New functions.
 480         (powerpc_operands): Define ACC, PMSK8, PMSK4, PMSK2, XMSK, YMSK,
 481         YMSK2, XA6a, XA6ap, XB6a entries.
 482         (PMMIRR, P_X_MASK, P_XX1_MASK, P_GER_MASK): Define
 483         (P_GER2_MASK, P_GER4_MASK, P_GER8_MASK, P_GER64_MASK): Define.
 484         (PPCVSX4): Define.
 485         (powerpc_opcodes): Add xxmfacc, xxmtacc, xxsetaccz,
 486         xvi8ger4pp, xvi8ger4, xvf16ger2pp, xvf16ger2, xvf32gerpp, xvf32ger,
 487         xvi4ger8pp, xvi4ger8, xvi16ger2spp, xvi16ger2s, xvbf16ger2pp,
 488         xvbf16ger2, xvf64gerpp, xvf64ger, xvi16ger2, xvf16ger2np,
 489         xvf32gernp, xvi8ger4spp, xvi16ger2pp, xvbf16ger2np, xvf64gernp,
 490         xvf16ger2pn, xvf32gerpn, xvbf16ger2pn, xvf64gerpn, xvf16ger2nn,
 491         xvf32gernn, xvbf16ger2nn, xvf64gernn, xvcvbf16sp, xvcvspbf16.
 492         (prefix_opcodes): Add pmxvi8ger4pp, pmxvi8ger4, pmxvf16ger2pp,
 493         pmxvf16ger2, pmxvf32gerpp, pmxvf32ger, pmxvi4ger8pp, pmxvi4ger8,
 494         pmxvi16ger2spp, pmxvi16ger2s, pmxvbf16ger2pp, pmxvbf16ger2,
 495         pmxvf64gerpp, pmxvf64ger, pmxvi16ger2, pmxvf16ger2np, pmxvf32gernp,
 496         pmxvi8ger4spp, pmxvi16ger2pp, pmxvbf16ger2np, pmxvf64gernp,
 497         pmxvf16ger2pn, pmxvf32gerpn, pmxvbf16ger2pn, pmxvf64gerpn,
 498         pmxvf16ger2nn, pmxvf32gernn, pmxvbf16ger2nn, pmxvf64gernn.
 499
 500 2020-05-11  Alan Modra  <amodra@gmail.com>
 501
 502         * ppc-opc.c (insert_imm32, extract_imm32): New functions.
 503         (insert_xts, extract_xts): New functions.
 504         (IMM32, UIM3, IX, UIM5, SH3, XTS, P8RR): Define.
 505         (P_XX4_MASK, P_UXX4_MASK, VSOP, P_VS_MASK, P_VSI_MASK): Define.
 506         (VXRC_MASK, VXSH_MASK): Define.
 507         (powerpc_opcodes): Add vinsbvlx, vsldbi, vextdubvlx, vextdubvrx,
 508         vextduhvlx, vextduhvrx, vextduwvlx, vextduwvrx, vextddvlx,
 509         vextddvrx, vinshvlx, vinswvlx, vinsw, vinsbvrx, vinshvrx,
 510         vinswvrx, vinsd, vinsblx, vsrdbi, vinshlx, vinswlx, vinsdlx,
 511         vinsbrx, vinshrx, vinswrx, vinsdrx, lxvkq.
 512         (prefix_opcodes): Add xxsplti32dx, xxspltidp, xxspltiw, xxblendvb,
 513         xxblendvh, xxblendvw, xxblendvd, xxpermx.
 514
 515 2020-05-11  Alan Modra  <amodra@gmail.com>
 516
 517         * ppc-opc.c (powerpc_opcodes): Add vrlq, vdivuq, vmsumcud, vrlqmi,
 518         vmuloud, vcmpuq, vslq, vdivsq, vcmpsq, vrlqnm, vcmpequq, vmulosd,
 519         vsrq, vdiveuq, vcmpgtuq, vmuleud, vsraq, vdivesq, vcmpgtsq, vmulesd,
 520         vcmpequq., vextsd2q, vmoduq, vcmpgtuq., vmodsq, vcmpgtsq., xscvqpuqz,
 521         xscvuqqp, xscvqpsqz, xscvsqqp, dcffixqq, dctfixqq.
 522
 523 2020-05-11  Alan Modra  <amodra@gmail.com>
 524
 525         * ppc-opc.c (insert_xtp, extract_xtp): New functions.
 526         (XTP, DQXP, DQXP_MASK): Define.
 527         (powerpc_opcodes): Add lxvp, stxvp, lxvpx, stxvpx.
 528         (prefix_opcodes): Add plxvp and pstxvp.
 529
 530 2020-05-11  Alan Modra  <amodra@gmail.com>
 531
 532         * ppc-opc.c (powerpc_opcodes): Add vdivuw, vdivud, vdivsw, vmulld,
 533         vdivsd, vmulhuw, vdiveuw, vmulhud, vdiveud, vmulhsw, vdivesw,
 534         vmulhsd, vdivesd, vmoduw, vmodud, vmodsw, vmodsd.
 535
 536 2020-05-11  Peter Bergner  <bergner@linux.ibm.com>
 537
 538         * ppc-opc.c (powerpc_opcodes) <brd, brh, brw>: New mnemonics.
 539
 540 2020-05-11  Peter Bergner  <bergner@linux.ibm.com>
 541
 542         * ppc-opc.c (insert_l1opt, extract_l1opt): New functions.
 543         (L1OPT): Define.
 544         (powerpc_opcodes) <paste.>: Add L operand for cpu POWER10.
 545
 546 2020-05-11  Peter Bergner  <bergner@linux.ibm.com>
 547
 548         * ppc-opc.c (powerpc_opcodes) <slbiag>: Add variant with L operand.
 549
 550 2020-05-11  Alan Modra  <amodra@gmail.com>
 551
 552         * ppc-dis.c (powerpc_init_dialect): Default to "power10".
 553
 554 2020-05-11  Alan Modra  <amodra@gmail.com>
 555
 556         * ppc-dis.c (ppc_opts): Add "power10" entry.
 557         (print_insn_powerpc): Update for PPC_OPCODE_POWER10 renaming.
 558         * ppc-opc.c (POWER10): Rename from POWERXX.  Update all uses.
 559
 560 2020-05-11  Nick Clifton  <nickc@redhat.com>
 561
 562         * po/fr.po: Updated French translation.
 563
 564 2020-04-30  Alex Coplan  <alex.coplan@arm.com>
 565
 566         * aarch64-opc.h (enum aarch64_field_kind): Add FLD_imm16_2.
 567         * aarch64-opc.c (fields): Add entry for FLD_imm16_2.
 568         (operand_general_constraint_met_p): validate
 569         AARCH64_OPND_UNDEFINED.
 570         * aarch64-tbl.h (aarch64_opcode_table): Add udf instruction, entry
 571         for FLD_imm16_2.
 572         * aarch64-asm-2.c: Regenerated.
 573         * aarch64-dis-2.c: Regenerated.
 574         * aarch64-opc-2.c: Regenerated.
 575
 576 2020-04-29  Nick Clifton  <nickc@redhat.com>
 577
 578         PR 22699
 579         * sh-opc.h: Also use unsigned 8-bit immediate values for the LDRC
 580         and SETRC insns.
 581
 582 2020-04-29  Nick Clifton  <nickc@redhat.com>
 583
 584         * po/sv.po: Updated Swedish translation.
 585
 586 2020-04-29  Nick Clifton  <nickc@redhat.com>
 587
 588         PR 22699
 589         * sh-opc.h (IMM0_8): Replace with IMM0_8S and IMM0_8U.  Use
 590         IMM0_8S for arithmetic insns and IMM0_8U for logical insns.
 591         * sh-dis.c (print_insn_sh): Change IMM0_8 case to IMM0_8S and add
 592         IMM0_8U case.
 593
 594 2020-04-21  Andreas Schwab  <schwab@linux-m68k.org>
 595
 596         PR 25848
 597         * m68k-opc.c (m68k_opcodes): Allow pc-rel for second operand of
 598         cmpi only on m68020up and cpu32.
 599
 600 2020-04-20  Sudakshina Das  <sudi.das@arm.com>
 601
 602         * aarch64-asm.c (aarch64_ins_none): New.
 603         * aarch64-asm.h (ins_none): New declaration.
 604         * aarch64-dis.c (aarch64_ext_none): New.
 605         * aarch64-dis.h (ext_none): New declaration.
 606         * aarch64-opc.c (aarch64_print_operand): Update case for
 607         AARCH64_OPND_BARRIER_PSB.
 608         * aarch64-tbl.h (aarch64_opcode_table): Add tsb.
 609         (AARCH64_OPERANDS): Update inserter/extracter for
 610         AARCH64_OPND_BARRIER_PSB to use new dummy functions.
 611         * aarch64-asm-2.c: Regenerated.
 612         * aarch64-dis-2.c: Regenerated.
 613         * aarch64-opc-2.c: Regenerated.
 614
 615 2020-04-20  Sudakshina Das  <sudi.das@arm.com>
 616
 617         * aarch64-tbl.h (aarch64_feature_bti, BTI, BTI_INSN): Remove.
 618         (aarch64_feature_ras, RAS): Likewise.
 619         (aarch64_feature_stat_profile, STAT_PROFILE): Likewise.
 620         (aarch64_opcode_table): Update bti, xpaclri, pacia1716, pacib1716,
 621         autia1716, autib1716, esb, psb, dgh, paciaz, paciasp, pacibz, pacibsp,
 622         autiaz, autiasp, autibz, autibsp to be CORE_INSN.
 623         * aarch64-asm-2.c: Regenerated.
 624         * aarch64-dis-2.c: Regenerated.
 625         * aarch64-opc-2.c: Regenerated.
 626
 627 2020-04-17  Fredrik Strupe  <fredrik@strupe.net>
 628
 629         * arm-dis.c (neon_opcodes): Fix VDUP instruction masks.
 630         (print_insn_neon): Support disassembly of conditional
 631         instructions.
 632
 633 2020-02-16  David Faust  <david.faust@oracle.com>
 634
 635         * bpf-desc.c: Regenerate.
 636         * bpf-desc.h: Likewise.
 637         * bpf-opc.c: Regenerate.
 638         * bpf-opc.h: Likewise.
 639
 640 2020-04-07  Lili Cui  <lili.cui@intel.com>
 641
 642         * i386-dis.c (enum): Add PREFIX_0F01_REG_5_MOD_3_RM_1,
 643         (prefix_table): New instructions (see prefixes above).
 644         (rm_table): Likewise
 645         * i386-gen.c (cpu_flag_init): Add CPU_TSXLDTRK_FLAGS,
 646         CPU_ANY_TSXLDTRK_FLAGS.
 647         (cpu_flags): Add CpuTSXLDTRK.
 648         * i386-opc.h (enum): Add CpuTSXLDTRK.
 649         (i386_cpu_flags): Add cputsxldtrk.
 650         * i386-opc.tbl: Add XSUSPLDTRK insns.
 651         * i386-init.h: Regenerate.
 652         * i386-tbl.h: Likewise.
 653
 654 2020-04-02  Lili Cui  <lili.cui@intel.com>
 655
 656         * i386-dis.c (prefix_table): New instructions serialize.
 657         * i386-gen.c (cpu_flag_init): Add CPU_SERIALIZE_FLAGS,
 658         CPU_ANY_SERIALIZE_FLAGS.
 659         (cpu_flags): Add CpuSERIALIZE.
 660         * i386-opc.h (enum): Add CpuSERIALIZE.
 661         (i386_cpu_flags): Add cpuserialize.
 662         * i386-opc.tbl: Add SERIALIZE insns.
 663         * i386-init.h: Regenerate.
 664         * i386-tbl.h: Likewise.
 665
 666 2020-03-26  Alan Modra  <amodra@gmail.com>
 667
 668         * disassemble.h (opcodes_assert): Declare.
 669         (OPCODES_ASSERT): Define.
 670         * disassemble.c: Don't include assert.h.  Include opintl.h.
 671         (opcodes_assert): New function.
 672         * h8300-dis.c (bfd_h8_disassemble_init): Use OPCODES_ASSERT.
 673         (bfd_h8_disassemble): Reduce size of data array.  Correctly
 674         calculate maxlen.  Omit insn decoding when insn length exceeds
 675         maxlen.  Exit from nibble loop when looking for E, before
 676         accessing next data byte.  Move processing of E outside loop.
 677         Replace tests of maxlen in loop with assertions.
 678
 679 2020-03-26  Alan Modra  <amodra@gmail.com>
 680
 681         * arc-dis.c (find_format): Init needs_limm.  Simplify use of limm.
 682
 683 2020-03-25  Alan Modra  <amodra@gmail.com>
 684
 685         * z80-dis.c (suffix): Init mybuf.
 686
 687 2020-03-22  Alan Modra  <amodra@gmail.com>
 688
 689         * h8300-dis.c (bfd_h8_disassemble): Limit data[] access to that
 690         successflly read from section.
 691
 692 2020-03-22  Alan Modra  <amodra@gmail.com>
 693
 694         * arc-dis.c (find_format): Use ISO C string concatenation rather
 695         than line continuation within a string.  Don't access needs_limm
 696         before testing opcode != NULL.
 697
 698 2020-03-22  Alan Modra  <amodra@gmail.com>
 699
 700         * ns32k-dis.c (print_insn_arg): Update comment.
 701         (print_insn_ns32k): Reduce size of index_offset array, and
 702         initialize, passing -1 to print_insn_arg for args that are not
 703         an index.  Don't exit arg loop early.  Abort on bad arg number.
 704
 705 2020-03-22  Alan Modra  <amodra@gmail.com>
 706
 707         * s12z-dis.c (abstract_read_memory): Don't print error on EOI.
 708         * s12z-opc.c: Formatting.
 709         (operands_f): Return an int.
 710         (opr_n_bytes_p1): Return -1 on reaching buffer memory limit.
 711         (opr_n_bytes2, bfextins_n_bytes, mul_n_bytes, bm_n_bytes),
 712         (shift_n_bytes, mov_imm_opr_n_bytes, loop_prim_n_bytes),
 713         (exg_sex_discrim): Likewise.
 714         (create_immediate_operand, create_bitfield_operand),
 715         (create_register_operand_with_size, create_register_all_operand),
 716         (create_register_all16_operand, create_simple_memory_operand),
 717         (create_memory_operand, create_memory_auto_operand): Don't
 718         segfault on malloc failure.
 719         (z_ext24_decode): Return an int status, negative on fail, zero
 720         on success.
 721         (x_imm1, imm1_decode, trap_decode, z_opr_decode, z_opr_decode2),
 722         (imm1234, reg_s_imm, reg_s_opr, z_imm1234_8base, z_imm1234_0base),
 723         (z_tfr, z_reg, reg_xy, lea_reg_xys_opr, lea_reg_xys, rel_15_7),
 724         (decode_rel_15_7, cmp_xy, sub_d6_x_y, sub_d6_y_x),
 725         (ld_18bit_decode, mul_decode, bm_decode, bm_rel_decode),
 726         (mov_imm_opr, ld_18bit_decode, exg_sex_decode),
 727         (loop_primitive_decode, shift_decode, psh_pul_decode),
 728         (bit_field_decode): Similarly.
 729         (z_decode_signed_value, decode_signed_value): Similarly.  Add arg
 730         to return value, update callers.
 731         (x_opr_decode_with_size): Check all reads, returning NULL on fail.
 732         Don't segfault on NULL operand.
 733         (decode_operation): Return OP_INVALID on first fail.
 734         (decode_s12z): Check all reads, returning -1 on fail.
 735
 736 2020-03-20  Alan Modra  <amodra@gmail.com>
 737
 738         * metag-dis.c (print_insn_metag): Don't ignore status from
 739         read_memory_func.
 740
 741 2020-03-20  Alan Modra  <amodra@gmail.com>
 742
 743         * nds32-dis.c (print_insn_nds32): Remove unnecessary casts.
 744         Initialize parts of buffer not written when handling a possible
 745         2-byte insn at end of section.  Don't attempt decoding of such
 746         an insn by the 4-byte machinery.
 747
 748 2020-03-20  Alan Modra  <amodra@gmail.com>
 749
 750         * ppc-dis.c (print_insn_powerpc): Only clear needed bytes of
 751         partially filled buffer.  Prevent lookup of 4-byte insns when
 752         only VLE 2-byte insns are possible due to section size.  Print
 753         ".word" rather than ".long" for 2-byte leftovers.
 754
 755 2020-03-17  Sergey Belyashov  <sergey.belyashov@gmail.com>
 756
 757         PR 25641
 758         * z80-dis.c: Fix disassembling ED+A4/AC/B4/BC opcodes.
 759
 760 2020-03-13  Jan Beulich  <jbeulich@suse.com>
 761
 762         * i386-dis.c (X86_64_0D): Rename to ...
 763         (X86_64_0E): ... this.
 764
 765 2020-03-09  H.J. Lu  <hongjiu.lu@intel.com>
 766
 767         * Makefile.am ($(srcdir)/i386-init.h): Also pass -P to $(CPP).
 768         * Makefile.in: Regenerated.
 769
 770 2020-03-09  Jan Beulich  <jbeulich@suse.com>
 771
 772         * i386-opc.tbl (avx_irel): New. Use is for AVX512 vpcmp*
 773         3-operand pseudos.
 774         * i386-tbl.h: Re-generate.
 775
 776 2020-03-09  Jan Beulich  <jbeulich@suse.com>
 777
 778         * i386-opc.tbl (xop_elem, xop_irel, xop_sign): New. Use them for XOP vpcom*,
 779         vprot*, vpsha*, and vpshl*.
 780         * i386-tbl.h: Re-generate.
 781
 782 2020-03-09  Jan Beulich  <jbeulich@suse.com>
 783
 784         * i386-opc.tbl (avx_frel): New. Use it for AVX/AVX512 vcmpps,
 785         vcmpss, vcmppd, and vcmpsd 3-operand pseudo-ops.
 786         * i386-tbl.h: Re-generate.
 787
 788 2020-03-09  Jan Beulich  <jbeulich@suse.com>
 789
 790         * i386-gen.c (set_bitfield): Ignore zero-length field names.
 791         * i386-opc.tbl (sse_frel): New. Use it for SSE/SSE2 cmpps,
 792         cmpss, cmppd, and cmpsd 2-operand pseudo-ops.
 793         * i386-tbl.h: Re-generate.
 794
 795 2020-03-09  Jan Beulich  <jbeulich@suse.com>
 796
 797         * i386-gen.c (struct template_arg, struct template_instance,
 798         struct template_param, struct template, templates,
 799         parse_template, expand_templates): New.
 800         (process_i386_opcodes): Various local variables moved to
 801         expand_templates. Call parse_template and expand_templates.
 802         * i386-opc.tbl (cc): New. Use it for Jcc, SETcc, and CMOVcc.
 803         * i386-tbl.h: Re-generate.
 804
 805 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 806
 807         * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd, vcvtps2ph,
 808         vcvtps2qq, vcvtps2uqq, vcvttps2qq, vcvttps2uqq): Fold separate
 809         register and memory source templates. Replace VexW= by VexW*
 810         where applicable.
 811         * i386-tbl.h: Re-generate.
 812
 813 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 814
 815         * i386-opc.tbl: Drop IgnoreSize from various SIMD insns. Replace
 816         VexW= by VexW* and VexVVVV=1 by just VexVVVV where applicable.
 817         * i386-tbl.h: Re-generate.
 818
 819 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 820
 821         * i386-opc.tbl (fildll, fistpll, fisttpll): Add ATTSyntax.
 822         * i386-tbl.h: Re-generate.
 823
 824 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 825
 826         * i386-opc.tbl (movq): Drop NoRex64 from XMM/XMM SSE2AVX variants.
 827         (movmskps, pextrw, pinsrw, pmovmskb, movmskpd, extractps,
 828         pextrb, pinsrb, roundsd): Drop NoRex64 and where applicable use
 829         VexW0 on SSE2AVX variants.
 830         (vmovq): Drop NoRex64 from XMM/XMM variants.
 831         (vextractps, vmovmskpd, vmovmskps, vpextrb, vpextrw, vpinsrb,
 832         vpinsrw, vpmovmskb, vroundsd, vpmovmskb): Drop NoRex64 and where
 833         applicable use VexW0.
 834         * i386-tbl.h: Re-generate.
 835
 836 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 837
 838         * i386-gen.c (opcode_modifiers): Remove Rex64 field.
 839         * i386-opc.h (Rex64): Delete.
 840         (struct i386_opcode_modifier): Remove rex64 field.
 841         * i386-opc.tbl (crc32): Drop Rex64.
 842         Replace Rex64 with Size64 everywhere else.
 843         * i386-tbl.h: Re-generate.
 844
 845 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 846
 847         * i386-dis.c (OP_E_memory): Exclude recording of used address
 848         prefix for "bnd" modes only in 64-bit mode. Don't decode 16-bit
 849         addressed memory operands for MPX insns.
 850
 851 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 852
 853         * i386-opc.tbl (movmskps, mwait, vmread, vmwrite, invept,
 854         invvpid, invpcid, rdfsbase, rdgsbase, wrfsbase, wrgsbase, adcx,
 855         adox, mwaitx, rdpid, movdiri): Add IgnoreSize.
 856         (ptwrite): Split into non-64-bit and 64-bit forms.
 857         * i386-tbl.h: Re-generate.
 858
 859 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 860
 861         * i386-opc.tbl (tpause, umwait): Add IgnoreSize. Add 3-operand
 862         template.
 863         * i386-tbl.h: Re-generate.
 864
 865 2020-03-04  Jan Beulich  <jbeulich@suse.com>
 866
 867         * i386-dis.c (PREFIX_0F01_REG_3_RM_1): New.
 868         (prefix_table): Move vmmcall here. Add vmgexit.
 869         (rm_table): Replace vmmcall entry by prefix_table[] escape.
 870         * i386-gen.c (cpu_flag_init): Add CPU_SEV_ES_FLAGS entry.
 871         (cpu_flags): Add CpuSEV_ES entry.
 872         * i386-opc.h (CpuSEV_ES): New.
 873         (union i386_cpu_flags): Add cpusev_es field.
 874         * i386-opc.tbl (vmgexit): New.
 875         * i386-init.h, i386-tbl.h: Re-generate.
 876
 877 2020-03-03  H.J. Lu  <hongjiu.lu@intel.com>
 878
 879         * i386-gen.c (opcode_modifiers): Replace IgnoreSize/DefaultSize
 880         with MnemonicSize.
 881         * i386-opc.h (IGNORESIZE): New.
 882         (DEFAULTSIZE): Likewise.
 883         (IgnoreSize): Removed.
 884         (DefaultSize): Likewise.
 885         (MnemonicSize): New.
 886         (i386_opcode_modifier): Replace ignoresize/defaultsize with
 887         mnemonicsize.
 888         * i386-opc.tbl (IgnoreSize): New.
 889         (DefaultSize): Likewise.
 890         * i386-tbl.h: Regenerated.
 891
 892 2020-03-03  Sergey Belyashov  <sergey.belyashov@gmail.com>
 893
 894         PR 25627
 895         * z80-dis.c: Fix disassembly of LD IY,(HL) and D (HL),IX
 896         instructions.
 897
 898 2020-03-03  H.J. Lu  <hongjiu.lu@intel.com>
 899
 900         PR gas/25622
 901         * i386-opc.tbl: Add IgnoreSize to cvtsi2sd, cvtsi2ss, vcvtsi2sd,
 902         vcvtsi2ss, vcvtusi2sd and vcvtusi2ss for AT&T syntax.
 903         * i386-tbl.h: Regenerated.
 904
 905 2020-02-26  Alan Modra  <amodra@gmail.com>
 906
 907         * aarch64-asm.c: Indent labels correctly.
 908         * aarch64-dis.c: Likewise.
 909         * aarch64-gen.c: Likewise.
 910         * aarch64-opc.c: Likewise.
 911         * alpha-dis.c: Likewise.
 912         * i386-dis.c: Likewise.
 913         * nds32-asm.c: Likewise.
 914         * nfp-dis.c: Likewise.
 915         * visium-dis.c: Likewise.
 916
 917 2020-02-25  Claudiu Zissulescu <claziss@gmail.com>
 918
 919         * arc-regs.h (int_vector_base): Make it available for all ARC
 920         CPUs.
 921
 922 2020-02-20  Nelson Chu  <nelson.chu@sifive.com>
 923
 924         * riscv-dis.c (print_insn_args): Updated since the DECLARE_CSR is
 925         changed.
 926
 927 2020-02-19  Nelson Chu  <nelson.chu@sifive.com>
 928
 929         * riscv-opc.c (riscv_opcodes): Convert add/addi to the compressed
 930         c.mv/c.li if rs1 is zero.
 931
 932 2020-02-17  H.J. Lu  <hongjiu.lu@intel.com>
 933
 934         * i386-gen.c (cpu_flag_init): Replace CpuABM with
 935         CpuLZCNT|CpuPOPCNT.  Add CpuPOPCNT to CPU_SSE4_2_FLAGS.  Add
 936         CPU_POPCNT_FLAGS.
 937         (cpu_flags): Remove CpuABM.  Add CpuPOPCNT.
 938         * i386-opc.h (CpuABM): Removed.
 939         (CpuPOPCNT): New.
 940         (i386_cpu_flags): Remove cpuabm.  Add cpupopcnt.
 941         * i386-opc.tbl: Replace CpuABM|CpuSSE4_2 with CpuPOPCNT on
 942         popcnt.  Remove CpuABM from lzcnt.
 943         * i386-init.h: Regenerated.
 944         * i386-tbl.h: Likewise.
 945
 946 2020-02-17  Jan Beulich  <jbeulich@suse.com>
 947
 948         * i386-opc.tbl (vcvtsi2sd, vcvtsi2ss, vcvtusi2sd, vcvtusi2ss):
 949         Fold CpuNo64 and Cpu64 templates. Use VexLIG/EVexLIG and VexW0/
 950         VexW1 instead of open-coding them.
 951         * i386-tbl.h: Re-generate.
 952
 953 2020-02-17  Jan Beulich  <jbeulich@suse.com>
 954
 955         * i386-opc.tbl (AddrPrefixOpReg): Define.
 956         (monitor, invlpga, vmload, vmrun, vmsave, clzero, monitorx,
 957         umonitor, movdir64b, enqcmd, enqcmds): Fold Cpu64 and CpuNo64
 958         templates. Drop NoRex64.
 959         * i386-tbl.h: Re-generate.
 960
 961 2020-02-17  Jan Beulich  <jbeulich@suse.com>
 962
 963         PR gas/6518
 964         * i386-opc.tbl (vcvtpd2dq, vcvtpd2ps, vcvttpd2dq, vcvtpd2udq,
 965         vcvttpd2udq, vcvtqq2ps, vcvtuqq2ps): Split XMM/YMM source forms
 966         into Intel syntax instance (with Unpsecified) and AT&T one
 967         (without).
 968         (vcvtneps2bf16): Likewise, along with folding the two so far
 969         separate ones.
 970         * i386-tbl.h: Re-generate.
 971
 972 2020-02-16  H.J. Lu  <hongjiu.lu@intel.com>
 973
 974         * i386-gen.c (cpu_flag_init): Remove CPU_ANY_SSE3_FLAGS from
 975         CPU_ANY_SSE4A_FLAGS.
 976
 977 2020-02-17  Alan Modra  <amodra@gmail.com>
 978
 979         * i386-gen.c (cpu_flag_init): Correct last change.
 980
 981 2020-02-16  H.J. Lu  <hongjiu.lu@intel.com>
 982
 983         * i386-gen.c (cpu_flag_init): Add CPU_ANY_SSE4A_FLAGS.  Remove
 984         CPU_ANY_SSE4_FLAGS.
 985
 986 2020-02-14  H.J. Lu  <hongjiu.lu@intel.com>
 987
 988         * i386-opc.tbl (movsx): Remove Intel syntax comments.
 989         (movzx): Likewise.
 990
 991 2020-02-14  Jan Beulich  <jbeulich@suse.com>
 992
 993         PR gas/25438
 994         * i386-opc.tbl (movsx): Fold patterns. Also allow Reg32 as
 995         destination for Cpu64-only variant.
 996         (movzx): Fold patterns.
 997         * i386-tbl.h: Re-generate.
 998
 999 2020-02-13  Jan Beulich  <jbeulich@suse.com>
1000
1001         * i386-gen.c (cpu_flag_init): Move CpuSSE4a from
1002         CPU_ANY_SSE_FLAGS entry to CPU_ANY_SSE3_FLAGS one. Add
1003         CPU_ANY_SSE4_FLAGS entry.
1004         * i386-init.h: Re-generate.
1005
1006 2020-02-12  Jan Beulich  <jbeulich@suse.com>
1007
1008         * i386-opc.tbl (vfpclasspd, vfpclassps): Add Intel sytax form
1009         with Unspecified, making the present one AT&T syntax only.
1010         * i386-tbl.h: Re-generate.
1011
1012 2020-02-12  Jan Beulich  <jbeulich@suse.com>
1013
1014         * i386-opc.tbl (jmp): Fold CpuNo64 and Amd64 direct variants.
1015         * i386-tbl.h: Re-generate.
1016
1017 2020-02-12  Jan Beulich  <jbeulich@suse.com>
1018
1019         PR gas/24546
1020         * i386-dis.c (putop): Handle REX.W in '^' case for Intel64 mode.
1021         * i386-opc.tbl (lfs, lgs, lss, lcall, ljmp): Split into
1022         Amd64 and Intel64 templates.
1023         (call, jmp): Likewise for far indirect variants. Dro
1024         Unspecified.
1025         * i386-tbl.h: Re-generate.
1026
1027 2020-02-11  Jan Beulich  <jbeulich@suse.com>
1028
1029         * i386-gen.c (opcode_modifiers): Remove ShortForm entry.
1030         * i386-opc.h (ShortForm): Delete.
1031         (struct i386_opcode_modifier): Remove shortform field.
1032         * i386-opc.tbl (mov, movabs, push, pop, xchg, inc, dec, fld,
1033         fst, fstp, fxch, fcom, fcomp, fucom, fucomp, fadd, faddp, fsub,
1034         fsubp, fsubr, fsubrp, fmul, fmulp, fdiv, fdivp, fdivr, fdivrp,
1035         ffreep, bswap, fcmov*, fcomi, fcomip, fucomi, fucomip, movq):
1036         Drop ShortForm.
1037         * i386-tbl.h: Re-generate.
1038
1039 2020-02-11  Jan Beulich  <jbeulich@suse.com>
1040
1041         * i386-opc.tbl (fcomi, fucomi, fcomip, fcompi, fucomip,
1042         fucompi): Drop ShortForm from operand-less templates.
1043         * i386-tbl.h: Re-generate.
1044
1045 2020-02-11  Alan Modra  <amodra@gmail.com>
1046
1047         * cgen-ibld.in (extract_normal): Set *valuep on all return paths.
1048         * bpf-ibld.c, * epiphany-ibld.c, * fr30-ibld.c, * frv-ibld.c,
1049         * ip2k-ibld.c, * iq2000-ibld.c, * lm32-ibld.c, * m32c-ibld.c,
1050         * m32r-ibld.c, * mep-ibld.c, * mt-ibld.c, * or1k-ibld.c,
1051         * xc16x-ibld.c, * xstormy16-ibld.c: Regenerate.
1052
1053 2020-02-10  Matthew Malcomson  <matthew.malcomson@arm.com>
1054
1055         * arm-dis.c (print_insn_cde): Define 'V' parse character.
1056         (cde_opcodes): Add VCX* instructions.
1057
1058 2020-02-10  Stam Markianos-Wright  <stam.markianos-wright@arm.com>
1059             Matthew Malcomson  <matthew.malcomson@arm.com>
1060
1061         * arm-dis.c (struct cdeopcode32): New.
1062         (CDE_OPCODE): New macro.
1063         (cde_opcodes): New disassembly table.
1064         (regnames): New option to table.
1065         (cde_coprocs): New global variable.
1066         (print_insn_cde): New
1067         (print_insn_thumb32): Use print_insn_cde.
1068         (parse_arm_disassembler_options): Parse coprocN args.
1069
1070 2020-02-10  H.J. Lu  <hongjiu.lu@intel.com>
1071
1072         PR gas/25516
1073         * i386-gen.c (opcode_modifiers): Replace AMD64 and Intel64
1074         with ISA64.
1075         * i386-opc.h (AMD64): Removed.
1076         (Intel64): Likewose.
1077         (AMD64): New.
1078         (INTEL64): Likewise.
1079         (INTEL64ONLY): Likewise.
1080         (i386_opcode_modifier): Replace amd64 and intel64 with isa64.
1081         * i386-opc.tbl (Amd64): New.
1082         (Intel64): Likewise.
1083         (Intel64Only): Likewise.
1084         Replace AMD64 with Amd64.  Update sysenter/sysenter with
1085         Cpu64 and Intel64Only.  Remove AMD64 from sysenter/sysenter.
1086         * i386-tbl.h: Regenerated.
1087
1088 2020-02-07  Sergey Belyashov  <sergey.belyashov@gmail.com>
1089
1090         PR 25469
1091         * z80-dis.c: Add support for GBZ80 opcodes.
1092
1093 2020-02-04  Alan Modra  <amodra@gmail.com>
1094
1095         * d30v-dis.c (print_insn): Make "val" and "opnum" unsigned.
1096
1097 2020-02-03  Alan Modra  <amodra@gmail.com>
1098
1099         * m32c-ibld.c: Regenerate.
1100
1101 2020-02-01  Alan Modra  <amodra@gmail.com>
1102
1103         * frv-ibld.c: Regenerate.
1104
1105 2020-01-31  Jan Beulich  <jbeulich@suse.com>
1106
1107         * i386-dis.c (EXxmm_mdq, xmm_mdq_mode): Delete.
1108         (intel_operand_size, OP_EX): Drop xmm_mdq_mode case label.
1109         (OP_E_memory): Replace xmm_mdq_mode case label by
1110         vex_scalar_w_dq_mode one.
1111         * i386-dis-evex-prefix.h: Replace EXxmm_mdq by EXVexWdqScalar.
1112
1113 2020-01-31  Jan Beulich  <jbeulich@suse.com>
1114
1115         * i386-dis.c (EXVexWdq, vex_w_dq_mode): Delete.
1116         (vex_vsib_d_w_dq_mode, vex_vsib_q_w_dq_mode,
1117         vex_scalar_w_dq_mode): Don't refer to vex_w_dq_mode in comments.
1118         (intel_operand_size): Drop vex_w_dq_mode case label.
1119
1120 2020-01-31  Richard Sandiford  <richard.sandiford@arm.com>
1121
1122         * aarch64-tbl.h (aarch64_opcode): Set C_MAX_ELEM for SVE bfcvt.
1123         Remove C_SCAN_MOVPRFX for SVE bfcvtnt.
1124
1125 2020-01-30  Alan Modra  <amodra@gmail.com>
1126
1127         * m32c-ibld.c: Regenerate.
1128
1129 2020-01-30  Jose E. Marchesi  <jose.marchesi@oracle.com>
1130
1131         * bpf-opc.c: Regenerate.
1132
1133 2020-01-30  Jan Beulich  <jbeulich@suse.com>
1134
1135         * i386-dis.c (X86_64_C2, X86_64_C3): New enumerators.
1136         (dis386): Use them to replace C2/C3 table entries.
1137         (x86_64_table): Add X86_64_C2 and X86_64_C3 entries.
1138         * i386-opc.tbl (ret): Split Cpu64 entries into AMD64 and Intel64
1139         ones. Use Size64 instead of DefaultSize on Intel64 ones.
1140         * i386-tbl.h: Re-generate.
1141
1142 2020-01-30  Jan Beulich  <jbeulich@suse.com>
1143
1144         * i386-opc.tbl (call): Drop DefaultSize from Intel64 JumpDword
1145         forms.
1146         (fldenv, fnstenv, fstenv, fnsave, fsave, frstor): Drop
1147         DefaultSize.
1148         * i386-tbl.h: Re-generate.
1149
1150 2020-01-30  Alan Modra  <amodra@gmail.com>
1151
1152         * tic4x-dis.c (tic4x_dp): Make unsigned.
1153
1154 2020-01-27  H.J. Lu  <hongjiu.lu@intel.com>
1155             Jan Beulich  <jbeulich@suse.com>
1156
1157         PR binutils/25445
1158         * i386-dis.c (MOVSXD_Fixup): New function.
1159         (movsxd_mode): New enum.
1160         (x86_64_table): Use MOVSXD_Fixup and movsxd_mode on movsxd.
1161         (intel_operand_size): Handle movsxd_mode.
1162         (OP_E_register): Likewise.
1163         (OP_G): Likewise.
1164         * i386-opc.tbl: Remove Rex64 and allow 32-bit destination
1165         register on movsxd.  Add movsxd with 16-bit destination register
1166         for AMD64 and Intel64 ISAs.
1167         * i386-tbl.h: Regenerated.
1168
1169 2020-01-27  Tamar Christina  <tamar.christina@arm.com>
1170
1171         PR 25403
1172         * aarch64-tbl.h (struct aarch64_opcode): Re-order cfinv.
1173         * aarch64-asm-2.c: Regenerate
1174         * aarch64-dis-2.c: Likewise.
1175         * aarch64-opc-2.c: Likewise.
1176
1177 2020-01-21  Jan Beulich  <jbeulich@suse.com>
1178
1179         * i386-opc.tbl (sysret): Drop DefaultSize.
1180         * i386-tbl.h: Re-generate.
1181
1182 2020-01-21  Jan Beulich  <jbeulich@suse.com>
1183
1184         * i386-opc.tbl (vcvtneps2bf16x): Add Broadcast, Xmmword, and
1185         Dword.
1186         (vcvtneps2bf16y): Add Broadcast, Ymmword, and Dword.
1187         * i386-tbl.h: Re-generate.
1188
1189 2020-01-20  Nick Clifton  <nickc@redhat.com>
1190
1191         * po/de.po: Updated German translation.
1192         * po/pt_BR.po: Updated Brazilian Portuguese translation.
1193         * po/uk.po: Updated Ukranian translation.
1194
1195 2020-01-20  Alan Modra  <amodra@gmail.com>
1196
1197         * hppa-dis.c (fput_const): Remove useless cast.
1198
1199 2020-01-20  Alan Modra  <amodra@gmail.com>
1200
1201         * arm-dis.c (print_insn_arm): Wrap 'T' value.
1202
1203 2020-01-18  Nick Clifton  <nickc@redhat.com>
1204
1205         * configure: Regenerate.
1206         * po/opcodes.pot: Regenerate.
1207
1208 2020-01-18  Nick Clifton  <nickc@redhat.com>
1209
1210         Binutils 2.34 branch created.
1211
1212 2020-01-17  Christian Biesinger  <cbiesinger@google.com>
1213
1214         * opintl.h: Fix spelling error (seperate).
1215
1216 2020-01-17  H.J. Lu  <hongjiu.lu@intel.com>
1217
1218         * i386-opc.tbl: Add {vex} pseudo prefix.
1219         * i386-tbl.h: Regenerated.
1220
1221 2020-01-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1222
1223         PR 25376
1224         * opcodes/arm-dis.c (coprocessor_opcodes): Use CORE_HIGH for MVE bits.
1225         (neon_opcodes): Likewise.
1226         (select_arm_features): Make sure we enable MVE bits when selecting
1227         armv8.1-m.main.  Make sure we do not enable MVE bits when not selecting
1228         any architecture.
1229
1230 2020-01-16  Jan Beulich  <jbeulich@suse.com>
1231
1232         * i386-opc.tbl: Drop stale comment from XOP section.
1233
1234 2020-01-16  Jan Beulich  <jbeulich@suse.com>
1235
1236         * i386-opc.tbl (movq): Add VexWIG to SSE2AVX XMM->XMM forms.
1237         (extractps): Add VexWIG to SSE2AVX forms.
1238         * i386-tbl.h: Re-generate.
1239
1240 2020-01-16  Jan Beulich  <jbeulich@suse.com>
1241
1242         * i386-opc.tbl (pextrq, pinsrq): Drop IgnoreSize and Qword. Drop
1243         Size64 from and use VexW1 on SSE2AVX forms.
1244         (vpextrq, vpinsrq): Drop IgnoreSize and Qword. Drop Size64 from
1245         VEX-encoded forms. Add Cpu64 to EVEX-encoded forms. Use VexW1.
1246         * i386-tbl.h: Re-generate.
1247
1248 2020-01-15  Alan Modra  <amodra@gmail.com>
1249
1250         * tic4x-dis.c (tic4x_version): Make unsigned long.
1251         (optab, optab_special, registernames): New file scope vars.
1252         (tic4x_print_register): Set up registernames rather than
1253         malloc'd registertable.
1254         (tic4x_disassemble): Delete optable and optable_special.  Use
1255         optab and optab_special instead.  Throw away old optab,
1256         optab_special and registernames when info->mach changes.
1257
1258 2020-01-14  Sergey Belyashov  <sergey.belyashov@gmail.com>
1259
1260         PR 25377
1261         * z80-dis.c (suffix): Use .db instruction to generate double
1262         prefix.
1263
1264 2020-01-14  Alan Modra  <amodra@gmail.com>
1265
1266         * z8k-dis.c (unpack_instr): Formatting.  Cast unsigned short
1267         values to unsigned before shifting.
1268
1269 2020-01-13  Thomas Troeger  <tstroege@gmx.de>
1270
1271         * arm-dis.c (print_insn_arm): Fill in insn info fields for control
1272         flow instructions.
1273         (print_insn_thumb16, print_insn_thumb32): Likewise.
1274         (print_insn): Initialize the insn info.
1275         * i386-dis.c (print_insn): Initialize the insn info fields, and
1276         detect jumps.
1277
1278 2012-01-13  Claudiu Zissulescu <claziss@gmail.com>
1279
1280         * arc-opc.c (C_NE): Make it required.
1281
1282 2012-01-13  Claudiu Zissulescu <claziss@gmail.com>
1283
1284         * opcode/arc-dis.c (regnames): Correct ACCL/ACCH naming, fix typo
1285         reserved register name.
1286
1287 2020-01-13  Alan Modra  <amodra@gmail.com>
1288
1289         * ns32k-dis.c (Is_gen): Use strchr, add 'f'.
1290         (print_insn_ns32k): Adjust ioffset for 'f' index_offset.
1291
1292 2020-01-13  Alan Modra  <amodra@gmail.com>
1293
1294         * wasm32-dis.c (print_insn_wasm32): Localise variables.  Store
1295         result of wasm_read_leb128 in a uint64_t and check that bits
1296         are not lost when copying to other locals.  Use uint32_t for
1297         most locals.  Use PRId64 when printing int64_t.
1298
1299 2020-01-13  Alan Modra  <amodra@gmail.com>
1300
1301         * score-dis.c: Formatting.
1302         * score7-dis.c: Formatting.
1303
1304 2020-01-13  Alan Modra  <amodra@gmail.com>
1305
1306         * score-dis.c (print_insn_score48): Use unsigned variables for
1307         unsigned values.  Don't left shift negative values.
1308         (print_insn_score32): Likewise.
1309         * score7-dis.c (print_insn_score32, print_insn_score16): Likewise.
1310
1311 2020-01-13  Alan Modra  <amodra@gmail.com>
1312
1313         * tic4x-dis.c (tic4x_print_register): Remove dead code.
1314
1315 2020-01-13  Alan Modra  <amodra@gmail.com>
1316
1317         * fr30-ibld.c: Regenerate.
1318
1319 2020-01-13  Alan Modra  <amodra@gmail.com>
1320
1321         * xgate-dis.c (print_insn): Don't left shift signed value.
1322         (ripBits): Formatting, use 1u.
1323
1324 2020-01-10  Alan Modra  <amodra@gmail.com>
1325
1326         * tilepro-opc.c (parse_insn_tilepro): Make opval unsigned.
1327         * tilegx-opc.c (parse_insn_tilegx): Likewise.  Delete raw_opval.
1328
1329 2020-01-10  Alan Modra  <amodra@gmail.com>
1330
1331         * m10300-dis.c (disassemble): Move extraction of DREG, AREG, RREG,
1332         and XRREG value earlier to avoid a shift with negative exponent.
1333         * m10200-dis.c (disassemble): Similarly.
1334
1335 2020-01-09  Nick Clifton  <nickc@redhat.com>
1336
1337         PR 25224
1338         * z80-dis.c (ld_ii_ii): Use correct cast.
1339
1340 2020-01-03  Sergey Belyashov  <sergey.belyashov@gmail.com>
1341
1342         PR 25224
1343         * z80-dis.c (ld_ii_ii): Use character constant when checking
1344         opcode byte value.
1345
1346 2020-01-09  Jan Beulich  <jbeulich@suse.com>
1347
1348         * i386-dis.c (SEP_Fixup): New.
1349         (SEP): Define.
1350         (dis386_twobyte): Use it for sysenter/sysexit.
1351         (enum x86_64_isa): Change amd64 enumerator to value 1.
1352         (OP_J): Compare isa64 against intel64 instead of amd64.
1353         * i386-opc.tbl (sysenter, sysexit): Split into AMD64 and Intel64
1354         forms.
1355         * i386-tbl.h: Re-generate.
1356
1357 2020-01-08  Alan Modra  <amodra@gmail.com>
1358
1359         * z8k-dis.c: Include libiberty.h
1360         (instr_data_s): Make max_fetched unsigned.
1361         (z8k_lookup_instr): Make nibl_index and tabl_index unsigned.
1362         Don't exceed byte_info bounds.
1363         (output_instr): Make num_bytes unsigned.
1364         (unpack_instr): Likewise for nibl_count and loop.
1365         * z8kgen.c (gas <opcode_entry_type>): Make noperands, length and
1366         idx unsigned.
1367         * z8k-opc.h: Regenerate.
1368
1369 2020-01-07  Shahab Vahedi  <shahab@synopsys.com>
1370
1371         * arc-tbl.h (llock): Use 'LLOCK' as class.
1372         (llockd): Likewise.
1373         (scond): Use 'SCOND' as class.
1374         (scondd): Likewise.
1375         (llockd): Set data_size_mode to 'C_ZZ_D' which is 64-bit.
1376         (scondd): Likewise.
1377
1378 2020-01-06  Alan Modra  <amodra@gmail.com>
1379
1380         * m32c-ibld.c: Regenerate.
1381
1382 2020-01-06  Alan Modra  <amodra@gmail.com>
1383
1384         PR 25344
1385         * z80-dis.c (suffix): Don't use a local struct buffer copy.
1386         Peek at next byte to prevent recursion on repeated prefix bytes.
1387         Ensure uninitialised "mybuf" is not accessed.
1388         (print_insn_z80): Don't zero n_fetch and n_used here,..
1389         (print_insn_z80_buf): ..do it here instead.
1390
1391 2020-01-04  Alan Modra  <amodra@gmail.com>
1392
1393         * m32r-ibld.c: Regenerate.
1394
1395 2020-01-04  Alan Modra  <amodra@gmail.com>
1396
1397         * cr16-dis.c (cr16_match_opcode): Avoid shift left of signed value.
1398
1399 2020-01-04  Alan Modra  <amodra@gmail.com>
1400
1401         * crx-dis.c (match_opcode): Avoid shift left of signed value.
1402
1403 2020-01-04  Alan Modra  <amodra@gmail.com>
1404
1405         * d30v-dis.c (print_insn): Avoid signed overflow in left shift.
1406
1407 2020-01-03  Jan Beulich  <jbeulich@suse.com>
1408
1409         * aarch64-tbl.h (aarch64_opcode_table): Use
1410         SVE_ADDR_RX_LSL{1,2,3} for LD1RO{H,W,D}.
1411
1412 2020-01-03  Jan Beulich  <jbeulich@suse.com>
1413
1414         * aarch64-tbl.h (aarch64_opcode_table): Correct SIMD
1415         forms of SUDOT and USDOT.
1416
1417 2020-01-03  Jan Beulich  <jbeulich@suse.com>
1418
1419         * aarch64-tbl.h (aarch64_opcode_table): Drop 'i' from
1420         uzip{1,2}.
1421         * opcodes/aarch64-dis-2.c: Re-generate.
1422
1423 2020-01-03  Jan Beulich  <jbeulich@suse.com>
1424
1425         * aarch64-tbl.h (aarch64_opcode_table): Correct 64-bit
1426         FMMLA encoding.
1427         * opcodes/aarch64-dis-2.c: Re-generate.
1428
1429 2020-01-02  Sergey Belyashov  <sergey.belyashov@gmail.com>
1430
1431         * z80-dis.c: Add support for eZ80 and Z80 instructions.
1432
1433 2020-01-01  Alan Modra  <amodra@gmail.com>
1434
1435         Update year range in copyright notice of all files.
1436
1437 For older changes see ChangeLog-2019
1438 \f
1439 Copyright (C) 2020 Free Software Foundation, Inc.
1440
1441 Copying and distribution of this file, with or without modification,
1442 are permitted in any medium without royalty provided the copyright
1443 notice and this notice are preserved.
1444
1445 Local Variables:
1446 mode: change-log
1447 left-margin: 8
1448 fill-column: 74
1449 version-control: never
1450 End: