gdb: add target_ops::supports_displaced_step

[deliverable/binutils-gdb.git] / opcodes / ia64-waw.tbl

diff --git a/opcodes/ia64-waw.tbl b/opcodes/ia64-waw.tbl
index c8a3365b1cdb42c0291ff1e7c07b53e1c053ae8a..6fe9a843506c16e6573fcea60f338021047306ee 100644 (file)
--- a/opcodes/ia64-waw.tbl
+++ b/opcodes/ia64-waw.tbl
@@ -3,7 +3,13 @@ ALAT;  IC:mem-readers-alat, IC:mem-writers, chk.a.clr, IC:invala-all;  IC:mem-read
 AR[BSP];       br.call, brl.call, br.ret, cover, IC:mov-to-AR-BSPSTORE, rfi;   br.call, brl.call, br.ret, cover, IC:mov-to-AR-BSPSTORE, rfi;   impliedF
 AR[BSPSTORE];  alloc, loadrs, flushrs, IC:mov-to-AR-BSPSTORE;  alloc, loadrs, flushrs, IC:mov-to-AR-BSPSTORE;  impliedF
 AR[CCV];       IC:mov-to-AR-CCV;       IC:mov-to-AR-CCV;       impliedF
+AR[CFLG];      IC:mov-to-AR-CFLG;      IC:mov-to-AR-CFLG;      impliedF
+AR[CSD];       ld16, IC:mov-to-AR-CSD; ld16, IC:mov-to-AR-CSD; impliedF
 AR[EC];        br.ret, IC:mod-sched-brs, IC:mov-to-AR-EC;      br.ret, IC:mod-sched-brs, IC:mov-to-AR-EC;      impliedF
+AR[EFLAG];     IC:mov-to-AR-EFLAG;     IC:mov-to-AR-EFLAG;     impliedF
+AR[FCR];       IC:mov-to-AR-FCR;       IC:mov-to-AR-FCR;       impliedF
+AR[FDR];       IC:mov-to-AR-FDR;       IC:mov-to-AR-FDR;       impliedF
+AR[FIR];       IC:mov-to-AR-FIR;       IC:mov-to-AR-FIR;       impliedF
 AR[FPSR].sf0.controls; IC:mov-to-AR-FPSR, fsetc.s0;    IC:mov-to-AR-FPSR, fsetc.s0;    impliedF
 AR[FPSR].sf1.controls; IC:mov-to-AR-FPSR, fsetc.s1;    IC:mov-to-AR-FPSR, fsetc.s1;    impliedF
 AR[FPSR].sf2.controls; IC:mov-to-AR-FPSR, fsetc.s2;    IC:mov-to-AR-FPSR, fsetc.s2;    impliedF
@@ -18,6 +24,7 @@ AR[FPSR].sf3.flags;   IC:fp-arith-s3, IC:fcmp-s3, IC:fpcmp-s3;        IC:fp-arith-s3, IC:
 AR[FPSR].sf3.flags;    fclrf.s3, IC:fcmp-s3, IC:fp-arith-s3, IC:fpcmp-s3, IC:mov-to-AR-FPSR;   fclrf.s3, IC:mov-to-AR-FPSR;    impliedF
 AR[FPSR].rv;   IC:mov-to-AR-FPSR;      IC:mov-to-AR-FPSR;      impliedF
 AR[FPSR].traps;        IC:mov-to-AR-FPSR;      IC:mov-to-AR-FPSR;      impliedF
+AR[FSR];       IC:mov-to-AR-FSR;       IC:mov-to-AR-FSR;       impliedF
 AR[ITC];       IC:mov-to-AR-ITC;       IC:mov-to-AR-ITC;       impliedF
 AR[K%], % in 0 - 7;    IC:mov-to-AR-K+1;       IC:mov-to-AR-K+1;       impliedF
 AR[LC];        IC:mod-sched-brs-counted, IC:mov-to-AR-LC;      IC:mod-sched-brs-counted, IC:mov-to-AR-LC;      impliedF
@@ -25,8 +32,10 @@ AR[PFS];     br.call, brl.call;      br.call, brl.call;      none
 AR[PFS];       br.call, brl.call;      IC:mov-to-AR-PFS;       impliedF
 AR[RNAT];      alloc, flushrs, loadrs, IC:mov-to-AR-RNAT, IC:mov-to-AR-BSPSTORE;       alloc, flushrs, loadrs, IC:mov-to-AR-RNAT, IC:mov-to-AR-BSPSTORE;       impliedF
 AR[RSC];       IC:mov-to-AR-RSC;       IC:mov-to-AR-RSC;       impliedF
+AR[RUC];       IC:mov-to-AR-RUC;       IC:mov-to-AR-RUC;       impliedF
+AR[SSD];       IC:mov-to-AR-SSD;       IC:mov-to-AR-SSD;       impliedF
 AR[UNAT]{%}, % in 0 - 63;      IC:mov-to-AR-UNAT, st8.spill;   IC:mov-to-AR-UNAT, st8.spill;   impliedF
-AR%, % in 8-15, 20, 22-23, 31, 33-35, 37-39, 41-43, 45-47, 67-111;     IC:none;        IC:none;        none
+AR%, % in 8-15, 20, 22-23, 31, 33-35, 37-39, 41-43, 46-47, 67-111;     IC:none;        IC:none;        none
 AR%, % in 48 - 63, 112-127;    IC:mov-to-AR-ig+1;      IC:mov-to-AR-ig+1;      impliedF
 BR%, % in 0 - 7;       br.call+1, brl.call+1;  IC:mov-to-BR+1; impliedF
 BR%, % in 0 - 7;       IC:mov-to-BR+1; IC:mov-to-BR+1; impliedF
@@ -35,11 +44,12 @@ CFM;        IC:mod-sched-brs, br.call, brl.call, br.ret, alloc, clrrrb, cover, rfi; IC:
 CPUID#;        IC:none;        IC:none;        none
 CR[CMCV];      IC:mov-to-CR-CMCV;      IC:mov-to-CR-CMCV;      impliedF
 CR[DCR];       IC:mov-to-CR-DCR;       IC:mov-to-CR-DCR;       impliedF
-CR[EOI];       IC:mov-to-CR-EOI;       IC:mov-to-CR-EOI;       SC Section 10.8.3.4
+CR[EOI];       IC:mov-to-CR-EOI;       IC:mov-to-CR-EOI;       SC Section 5.8.3.4, "End of External Interrupt Register (EOI - CR67)" on page 2:119
 CR[GPTA];      IC:mov-to-CR-GPTA;      IC:mov-to-CR-GPTA;      impliedF
 CR[IFA];       IC:mov-to-CR-IFA;       IC:mov-to-CR-IFA;       impliedF
 CR[IFS];       IC:mov-to-CR-IFS, cover;        IC:mov-to-CR-IFS, cover;        impliedF
 CR[IHA];       IC:mov-to-CR-IHA;       IC:mov-to-CR-IHA;       impliedF
+CR[IIB%], % in 0 - 1;  IC:mov-to-CR-IIB;       IC:mov-to-CR-IIB;       impliedF
 CR[IIM];       IC:mov-to-CR-IIM;       IC:mov-to-CR-IIM;       impliedF
 CR[IIP];       IC:mov-to-CR-IIP;       IC:mov-to-CR-IIP;       impliedF
 CR[IIPA];      IC:mov-to-CR-IIPA;      IC:mov-to-CR-IIPA;      impliedF
@@ -56,7 +66,8 @@ CR[LRR%], % in 0 - 1; IC:mov-to-CR-LRR+1;     IC:mov-to-CR-LRR+1;     impliedF
 CR[PMV];       IC:mov-to-CR-PMV;       IC:mov-to-CR-PMV;       impliedF
 CR[PTA];       IC:mov-to-CR-PTA;       IC:mov-to-CR-PTA;       impliedF
 CR[TPR];       IC:mov-to-CR-TPR;       IC:mov-to-CR-TPR;       impliedF
-CR%, % in 3-7, 10-15, 18, 26-63, 75-79, 82-127;        IC:none;        IC:none;        none
+CR%, % in 3-7, 10-15, 18, 28-63, 75-79, 82-127;        IC:none;        IC:none;        none
+DAHR%, % in 0-7;       IC:br.call, brl.call, br.ret, IC:mov-to-AR-BSPSTORE, IC:mov-to-DAHR, rfi;       IC:br.call, brl.call, br.ret, IC:mov-to-AR-BSPSTORE, IC:mov-to-DAHR, rfi;       implied
 DBR#;  IC:mov-to-IND-DBR+3;    IC:mov-to-IND-DBR+3;    impliedF
 DTC;   ptc.e, ptc.g, ptc.ga, ptc.l, ptr.i, ptr.d;      ptc.e, ptc.g, ptc.ga, ptc.l, ptr.i, ptr.d;      none
 DTC;   ptc.e, ptc.g, ptc.ga, ptc.l, ptr.i, ptr.d, itc.i, itc.d, itr.i, itr.d;  itc.i, itc.d, itr.i, itr.d;     impliedF
@@ -124,5 +135,6 @@ PSR.sp;     IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi;    IC:sys-mask-writers
 PSR.ss;        rfi;    rfi;    impliedF
 PSR.tb;        IC:mov-to-PSR-l, rfi;   IC:mov-to-PSR-l, rfi;   impliedF
 PSR.up;        IC:user-mask-writers-partial+7, IC:mov-to-PSR-um, IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi;  IC:user-mask-writers-partial+7, IC:mov-to-PSR-um, IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi;  impliedF
+PSR.vm;        rfi, vmsw;      rfi, vmsw;      impliedF
 RR#;   IC:mov-to-IND-RR+6;     IC:mov-to-IND-RR+6;     impliedF
 RSE;   IC:rse-writers+14;      IC:rse-writers+14;      impliedF