cpu/
authorRichard Sandiford <rdsandiford@googlemail.com>
Mon, 1 Mar 2004 09:42:33 +0000 (09:42 +0000)
committerRichard Sandiford <rdsandiford@googlemail.com>
Mon, 1 Mar 2004 09:42:33 +0000 (09:42 +0000)
commitc7a48b9ac9215f67421a769c2986b6eb2a69780b
tree7b7c194a858c08b0cbf6bff28a4689eda00f46a3
parent8b73069fed6ec6b73e35eccdf186887d89ecb84b
cpu/
* frv.cpu (nsdiv, nudiv, nsdivi, nudivi): Remove fr400 profiling unit.
(scutss): Change unit to I0.
(calll, callil, ccalll): Add missing FR550-MAJOR and profile unit.
(mqsaths): Fix FR400-MAJOR categorization.
(media-quad-multiply-cross-acc, media-quad-cross-multiply-cross-acc)
(media-quad-cross-multiply-acc): Change unit from MDUALACC to FMALL.
* frv.opc (fr400_check_insn_major_constraints): Check for (M-2,M-1)
combinations.

opcodes/
* frv-desc.c, frv-opc.c: Regenerate.

sim/frv/
* cache.c (frv_cache_init): Change fr400 cache statistics to match
the fr405.
(non_cache_access): Add missing breaks.
* interrupts.c (set_exception_status_registers): Always set EAR15
for data_access_errors.
* memory.c (fr400_check_write_address): Remove redundant alignment
check.
* model.c: Regenerate.
cpu/ChangeLog
cpu/frv.cpu
cpu/frv.opc
opcodes/ChangeLog
opcodes/frv-desc.c
opcodes/frv-opc.c
sim/frv/ChangeLog
sim/frv/cache.c
sim/frv/interrupts.c
sim/frv/memory.c
sim/frv/model.c
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