x86: Split vcvtps2{,u}qq and vcvttps2{,u}qq
authorH.J. Lu <hjl.tools@gmail.com>
Wed, 18 Jul 2018 12:33:36 +0000 (05:33 -0700)
committerH.J. Lu <hjl.tools@gmail.com>
Wed, 18 Jul 2018 12:33:50 +0000 (05:33 -0700)
commit11a322db5c8bc23009e97af30180d6b14d86dbd3
tree44297f3d3e8c0a2d78eeb0347f3964aed085dad9
parentafca762f598d453c563f244cd3777715b1a0cb72
x86: Split vcvtps2{,u}qq and vcvttps2{,u}qq

After

commit 1b54b8d7e4fc8055f9220a5287e8a94d8a65a88d
Author: Jan Beulich <jbeulich@novell.com>
Date:   Mon Dec 18 09:36:14 2017 +0100

    x86: fold RegXMM/RegYMM/RegZMM into RegSIMD

    ... qualified by their respective sizes, allowing to drop FirstXmm0 at
    the same time.

folded RegXMM, RegYMM and RegZMM into RegSIMD, it's no longer impossible
to distinguish if Xmmword can represent a memory reference when operand
specification contains SIMD register. For example, template operands
specification like these

RegXMM|...|Xmmword|...

and

RegXMM|...

The Xmmword bitfield is always set by RegXMM which is represented by
"RegSIMD|Xmmword".  This patch splits each of vcvtps2qq, vcvtps2uqq,
vcvttps2qq and vcvttps2uqq into 2 templates: one template only has
RegXMM source operand and the other only has mempry source operand.

gas/

PR gas/23418
* testsuite/gas/i386/xmmword.s: Add tests for vcvtps2qq,
vcvtps2uqq, vcvttps2qq and vcvttps2uqq.
* testsuite/gas/i386/xmmword.l: Updated.

opcodes/

PR gas/23418
* i386-opc.h (Byte): Update comments.
(Word): Likewise.
(Dword): Likewise.
(Fword): Likewise.
(Qword): Likewise.
(Tbyte): Likewise.
(Xmmword): Likewise.
(Ymmword): Likewise.
(Zmmword): Likewise.
* i386-opc.tbl: Split vcvtps2qq, vcvtps2uqq, vcvttps2qq and
vcvttps2uqq.
* i386-tbl.h: Regenerated.
gas/ChangeLog
gas/testsuite/gas/i386/xmmword.l
gas/testsuite/gas/i386/xmmword.s
opcodes/ChangeLog
opcodes/i386-opc.h
opcodes/i386-opc.tbl
opcodes/i386-tbl.h
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