Arm64: SVE2's smaxp/sminp require operands 1 and 3 to be the same register
authorJan Beulich <jbeulich@suse.com>
Mon, 11 Nov 2019 12:28:35 +0000 (13:28 +0100)
committerJan Beulich <jbeulich@suse.com>
Mon, 11 Nov 2019 12:28:35 +0000 (13:28 +0100)
commit91802f3cfed1524ebcfef1057afad4f98519ca78
tree3ed6ef5c73754fd451a015a5566a3a8a741b9038
parent4f5fc85d6c6e33d8282f4c5164fb5187cdff96d1
Arm64: SVE2's smaxp/sminp require operands 1 and 3 to be the same register

This is just like for their umaxp/uminp and fmaxp/fminp counterparts.
gas/ChangeLog
gas/testsuite/gas/aarch64/illegal-sve2.l
gas/testsuite/gas/aarch64/illegal-sve2.s
opcodes/ChangeLog
opcodes/aarch64-tbl.h
This page took 0.025861 seconds and 4 git commands to generate.