Ravenscar port for RISC-V
authorTom Tromey <tromey@adacore.com>
Fri, 19 Apr 2019 16:41:40 +0000 (10:41 -0600)
committerTom Tromey <tromey@adacore.com>
Thu, 12 Dec 2019 18:47:40 +0000 (11:47 -0700)
commitdb3ad2f031d4da70db35977abbcede0399d81d6b
treed1f99732683aad6b7ff3c45a573668215d7f86c6
parent2ffe5b9c792fe78dbbcbe31b6fea751285df8876
Ravenscar port for RISC-V

This adds Ravenscar support to gdb for RISC-V targets.

This was tested internally using AdaCore's test suite and qemu.

gdb/ChangeLog
2019-12-12  Tom Tromey  <tromey@adacore.com>

* Makefile.in (ALL_TARGET_OBS): Add riscv-ravenscar-thread.o.
(HFILES_NO_SRCDIR): Add riscv-ravenscar-thread.h.
(ALLDEPFILES): Add riscv-ravenscar-thread.c.
* configure.tgt (riscv-*-*): Add riscv-ravenscar-thread.o.
* riscv-ravenscar-thread.c: New file.
* riscv-ravenscar-thread.h: New file.
* riscv-tdep.c (riscv_gdbarch_init): Call
register_riscv_ravenscar_ops.

Change-Id: Ic47a3b3cfbbe80c2c82a5f48d2e0481845cac8b0
gdb/ChangeLog
gdb/Makefile.in
gdb/configure.tgt
gdb/riscv-ravenscar-thread.c [new file with mode: 0644]
gdb/riscv-ravenscar-thread.h [new file with mode: 0644]
gdb/riscv-tdep.c
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