+2019-03-19 H.J. Lu <hongjiu.lu@intel.com>
+
+ PR gas/24359
+ * testsuite/gas/i386/i386.exp: Change optimize-6a, optimize-7,
+ x86-64-optimize-7a and x86-64-optimize-8 tests to run_list_test.
+ Remove optimize-6c and x86-64-optimize-7c tests.
+ * testsuite/gas/i386/noavx-3.l: Updated.
+ * testsuite/gas/i386/noavx-4.d: Likewise.
+ * testsuite/gas/i386/noavx-5.d: Likewise.
+ * testsuite/gas/i386/noavx-3.s: Add AVX512F tests.
+ * testsuite/gas/i386/noavx-4.s: Remove AVX512F tests.
+ * testsuite/gas/i386/nosse-5.s: Likewise.
+ * testsuite/gas/i386/optimize-6a.d: Removed.
+ * testsuite/gas/i386/optimize-6c.d: Likewise.
+ * testsuite/gas/i386/optimize-7.d: Likewise.
+ * testsuite/gas/i386/x86-64-optimize-7a.d: Likewise.
+ * testsuite/gas/i386/x86-64-optimize-7c.d: Likewise.
+ * testsuite/gas/i386/x86-64-optimize-8.d: Likewise.
+ * testsuite/gas/i386/optimize-6a.l: New file.
+ * testsuite/gas/i386/optimize-6a.s: Likewise.
+ * testsuite/gas/i386/optimize-7.l: Likewise.
+ * testsuite/gas/i386/x86-64-optimize-7a.l: Likewise.
+ * testsuite/gas/i386/x86-64-optimize-7a.s: Likewise.
+ * testsuite/gas/i386/x86-64-optimize-8.l: Likewise.
+
2019-03-18 Alan Modra <amodra@gmail.com>
* config/m68k-parse.y (yylex): Use temp_ilp and restore_ilp.
run_dump_test "optimize-3"
run_dump_test "optimize-4"
run_dump_test "optimize-5"
- run_dump_test "optimize-6a"
+ run_list_test "optimize-6a" "-I${srcdir}/$subdir -march=+noavx -al"
run_dump_test "optimize-6b"
- run_dump_test "optimize-6c"
- run_dump_test "optimize-7"
+ run_list_test "optimize-7" "-I${srcdir}/$subdir -march=+noavx2 -al"
# These tests require support for 8 and 16 bit relocs,
# so we only run them for ELF and COFF targets.
run_dump_test "x86-64-optimize-4"
run_dump_test "x86-64-optimize-5"
run_dump_test "x86-64-optimize-6"
- run_dump_test "x86-64-optimize-7a"
+ run_list_test "x86-64-optimize-7a" "-I${srcdir}/$subdir -march=+noavx -al"
run_dump_test "x86-64-optimize-7b"
- run_dump_test "x86-64-optimize-7c"
- run_dump_test "x86-64-optimize-8"
+ run_list_test "x86-64-optimize-8" "-I${srcdir}/$subdir -march=+noavx2 -al"
if { ![istarget "*-*-aix*"]
&& ![istarget "*-*-beos*"]
.*:37: Error: .*noavx.*
.*:38: Error: .*noavx.*
.*:39: Error: .*noavx.*
+.*:42: Error: .*noavx.*
+.*:43: Error: .*noavx.*
+.*:44: Error: .*noavx.*
+.*:45: Error: .*noavx.*
GAS LISTING .*
#...
[ ]*1[ ]+\# Test \.arch \[\.avxX|\.noavxX\]
[ ]*39[ ]+vfrczpd %xmm7,%xmm7
[ ]*40[ ]+\?\?\?\? 0F77 emms
[ ]*41[ ]+\?\?\?\? 0FAEE8 lfence
-[ ]*42[ ]+\?\?\?\? 8DB42600 \.p2align 4
-[ ]*42[ ]+0000008D
-[ ]*42[ ]+B6000000
-[ ]*42[ ]+00
+[ ]*42[ ]+vaddps %xmm6, %xmm5, %xmm4
+[ ]*43[ ]+vaddps %ymm6, %ymm5, %ymm4
+[ ]*44[ ]+vaddps %zmm6, %zmm5, %zmm4
+[ ]*45[ ]+vaddss %xmm6, %xmm5, %xmm4
#pass
vfrczpd %xmm7,%xmm7
emms
lfence
+ vaddps %xmm6, %xmm5, %xmm4
+ vaddps %ymm6, %ymm5, %ymm4
+ vaddps %zmm6, %zmm5, %zmm4
+ vaddss %xmm6, %xmm5, %xmm4
.p2align 4
[ ]*[a-f0-9]+: 62 f1 54 2f 58 e6 vaddps %ymm6,%ymm5,%ymm4\{%k7\}
[ ]*[a-f0-9]+: 62 f1 54 48 58 e6 vaddps %zmm6,%zmm5,%zmm4
[ ]*[a-f0-9]+: c5 d2 58 e6 vaddss %xmm6,%xmm5,%xmm4
-[ ]*[a-f0-9]+: 62 f1 54 0f 58 e6 vaddps %xmm6,%xmm5,%xmm4\{%k7\}
-[ ]*[a-f0-9]+: 62 f1 54 2f 58 e6 vaddps %ymm6,%ymm5,%ymm4\{%k7\}
-[ ]*[a-f0-9]+: 62 f1 54 48 58 e6 vaddps %zmm6,%zmm5,%zmm4
[ ]*[a-f0-9]+: c5 d0 58 e6 vaddps %xmm6,%xmm5,%xmm4
[ ]*[a-f0-9]+: c5 d4 58 e6 vaddps %ymm6,%ymm5,%ymm4
[ ]*[a-f0-9]+: c5 d2 58 e6 vaddss %xmm6,%xmm5,%xmm4
-[ ]*[a-f0-9]+: 62 f1 54 08 58 e6 vaddps %xmm6,%xmm5,%xmm4
-[ ]*[a-f0-9]+: 62 f1 54 28 58 e6 vaddps %ymm6,%ymm5,%ymm4
-[ ]*[a-f0-9]+: 62 f1 54 48 58 e6 vaddps %zmm6,%zmm5,%zmm4
-[ ]*[a-f0-9]+: 62 f1 56 08 58 e6 vaddss %xmm6,%xmm5,%xmm4
#pass
vaddps %zmm6, %zmm5, %zmm4
vaddss %xmm6, %xmm5, %xmm4
.arch .noavx2
- vaddps %xmm6, %xmm5, %xmm4{%k7}
- vaddps %ymm6, %ymm5, %ymm4{%k7}
- vaddps %zmm6, %zmm5, %zmm4
vaddps %xmm6, %xmm5, %xmm4
vaddps %ymm6, %ymm5, %ymm4
vaddss %xmm6, %xmm5, %xmm4
- .arch .noavx
- vaddps %xmm6, %xmm5, %xmm4
- vaddps %ymm6, %ymm5, %ymm4
- vaddps %zmm6, %zmm5, %zmm4
- vaddss %xmm6, %xmm5, %xmm4
[ ]*[a-f0-9]+: c5 d0 58 e6 vaddps %xmm6,%xmm5,%xmm4
[ ]*[a-f0-9]+: c5 d4 58 e6 vaddps %ymm6,%ymm5,%ymm4
[ ]*[a-f0-9]+: c5 d2 58 e6 vaddss %xmm6,%xmm5,%xmm4
-[ ]*[a-f0-9]+: 62 f1 54 08 58 e6 vaddps %xmm6,%xmm5,%xmm4
-[ ]*[a-f0-9]+: 62 f1 54 28 58 e6 vaddps %ymm6,%ymm5,%ymm4
-[ ]*[a-f0-9]+: 62 f1 54 48 58 e6 vaddps %zmm6,%zmm5,%zmm4
-[ ]*[a-f0-9]+: 62 f1 56 08 58 e6 vaddss %xmm6,%xmm5,%xmm4
#pass
vaddps %xmm6, %xmm5, %xmm4
vaddps %ymm6, %ymm5, %ymm4
vaddss %xmm6, %xmm5, %xmm4
- .arch .noavx
- vaddps %xmm6, %xmm5, %xmm4
- vaddps %ymm6, %ymm5, %ymm4
- vaddps %zmm6, %zmm5, %zmm4
- vaddss %xmm6, %xmm5, %xmm4
+++ /dev/null
-#source: optimize-6.s
-#as: -O2 -march=+noavx
-#objdump: -drw
-#name: optimized encoding 6a with -O2
-
-.*: +file format .*
-
-
-Disassembly of section .text:
-
-0+ <_start>:
- +[a-f0-9]+: 62 f1 f5 4f 55 e9 vandnpd %zmm1,%zmm1,%zmm5\{%k7\}
- +[a-f0-9]+: 62 f1 f5 08 55 e9 vandnpd %xmm1,%xmm1,%xmm5
- +[a-f0-9]+: 62 f1 74 4f 55 e9 vandnps %zmm1,%zmm1,%zmm5\{%k7\}
- +[a-f0-9]+: 62 f1 74 08 55 e9 vandnps %xmm1,%xmm1,%xmm5
- +[a-f0-9]+: 62 f1 75 4f df e9 vpandnd %zmm1,%zmm1,%zmm5\{%k7\}
- +[a-f0-9]+: 62 f1 75 08 df e9 vpandnd %xmm1,%xmm1,%xmm5
- +[a-f0-9]+: 62 f1 f5 4f df e9 vpandnq %zmm1,%zmm1,%zmm5\{%k7\}
- +[a-f0-9]+: 62 f1 f5 08 df e9 vpandnq %xmm1,%xmm1,%xmm5
- +[a-f0-9]+: 62 f1 f5 4f 57 e9 vxorpd %zmm1,%zmm1,%zmm5\{%k7\}
- +[a-f0-9]+: 62 f1 f5 08 57 e9 vxorpd %xmm1,%xmm1,%xmm5
- +[a-f0-9]+: 62 f1 74 4f 57 e9 vxorps %zmm1,%zmm1,%zmm5\{%k7\}
- +[a-f0-9]+: 62 f1 74 08 57 e9 vxorps %xmm1,%xmm1,%xmm5
- +[a-f0-9]+: 62 f1 75 4f ef e9 vpxord %zmm1,%zmm1,%zmm5\{%k7\}
- +[a-f0-9]+: 62 f1 75 08 ef e9 vpxord %xmm1,%xmm1,%xmm5
- +[a-f0-9]+: 62 f1 f5 4f ef e9 vpxorq %zmm1,%zmm1,%zmm5\{%k7\}
- +[a-f0-9]+: 62 f1 f5 08 ef e9 vpxorq %xmm1,%xmm1,%xmm5
- +[a-f0-9]+: 62 f1 75 4f f8 e9 vpsubb %zmm1,%zmm1,%zmm5\{%k7\}
- +[a-f0-9]+: 62 f1 75 08 f8 e9 vpsubb %xmm1,%xmm1,%xmm5
- +[a-f0-9]+: 62 f1 75 4f f9 e9 vpsubw %zmm1,%zmm1,%zmm5\{%k7\}
- +[a-f0-9]+: 62 f1 75 08 f9 e9 vpsubw %xmm1,%xmm1,%xmm5
- +[a-f0-9]+: 62 f1 75 4f fa e9 vpsubd %zmm1,%zmm1,%zmm5\{%k7\}
- +[a-f0-9]+: 62 f1 75 08 fa e9 vpsubd %xmm1,%xmm1,%xmm5
- +[a-f0-9]+: 62 f1 f5 4f fb e9 vpsubq %zmm1,%zmm1,%zmm5\{%k7\}
- +[a-f0-9]+: 62 f1 f5 08 fb e9 vpsubq %xmm1,%xmm1,%xmm5
- +[a-f0-9]+: c5 f4 47 e9 kxorw %k1,%k1,%k5
- +[a-f0-9]+: c5 f4 47 e9 kxorw %k1,%k1,%k5
- +[a-f0-9]+: c5 f4 42 e9 kandnw %k1,%k1,%k5
- +[a-f0-9]+: c5 f4 42 e9 kandnw %k1,%k1,%k5
-#pass
--- /dev/null
+.*: Assembler messages:
+.*:6: Error: .*
+.*:7: Error: .*
+.*:9: Error: .*
+.*:10: Error: .*
+.*:12: Error: .*
+.*:13: Error: .*
+.*:15: Error: .*
+.*:16: Error: .*
+.*:18: Error: .*
+.*:19: Error: .*
+.*:21: Error: .*
+.*:22: Error: .*
+.*:24: Error: .*
+.*:25: Error: .*
+.*:27: Error: .*
+.*:28: Error: .*
+.*:30: Error: .*
+.*:31: Error: .*
+.*:33: Error: .*
+.*:34: Error: .*
+.*:36: Error: .*
+.*:37: Error: .*
+.*:39: Error: .*
+.*:40: Error: .*
+.*:42: Error: .*
+.*:43: Error: .*
+.*:45: Error: .*
+.*:46: Error: .*
+GAS LISTING .*
+
+
+[ ]*1[ ]+\# Check instructions with optimized encoding
+[ ]*2[ ]+
+[ ]*3[ ]+\.include "optimize-6\.s"
+[ ]*1[ ]+\# Check instructions with optimized encoding
+[ ]*2[ ]+
+[ ]*3[ ]+\.allow_index_reg
+[ ]*4[ ]+\.text
+[ ]*5[ ]+_start:
+[ ]*6[ ]+vandnpd %zmm1, %zmm1, %zmm5\{%k7\}
+[ ]*7[ ]+vandnpd %zmm1, %zmm1, %zmm5
+[ ]*8[ ]+
+[ ]*9[ ]+vandnps %zmm1, %zmm1, %zmm5\{%k7\}
+[ ]*10[ ]+vandnps %zmm1, %zmm1, %zmm5
+[ ]*11[ ]+
+[ ]*12[ ]+vpandnd %zmm1, %zmm1, %zmm5\{%k7\}
+[ ]*13[ ]+vpandnd %zmm1, %zmm1, %zmm5
+[ ]*14[ ]+
+[ ]*15[ ]+vpandnq %zmm1, %zmm1, %zmm5\{%k7\}
+[ ]*16[ ]+vpandnq %zmm1, %zmm1, %zmm5
+[ ]*17[ ]+
+[ ]*18[ ]+vxorpd %zmm1, %zmm1, %zmm5\{%k7\}
+[ ]*19[ ]+vxorpd %zmm1, %zmm1, %zmm5
+[ ]*20[ ]+
+[ ]*21[ ]+vxorps %zmm1, %zmm1, %zmm5\{%k7\}
+[ ]*22[ ]+vxorps %zmm1, %zmm1, %zmm5
+[ ]*23[ ]+
+[ ]*24[ ]+vpxord %zmm1, %zmm1, %zmm5\{%k7\}
+[ ]*25[ ]+vpxord %zmm1, %zmm1, %zmm5
+[ ]*26[ ]+
+[ ]*27[ ]+vpxorq %zmm1, %zmm1, %zmm5\{%k7\}
+[ ]*28[ ]+vpxorq %zmm1, %zmm1, %zmm5
+[ ]*29[ ]+
+[ ]*30[ ]+vpsubb %zmm1, %zmm1, %zmm5\{%k7\}
+[ ]*31[ ]+vpsubb %zmm1, %zmm1, %zmm5
+[ ]*32[ ]+
+[ ]*33[ ]+vpsubw %zmm1, %zmm1, %zmm5\{%k7\}
+[ ]*34[ ]+vpsubw %zmm1, %zmm1, %zmm5
+[ ]*35[ ]+
+[ ]*36[ ]+vpsubd %zmm1, %zmm1, %zmm5\{%k7\}
+[ ]*37[ ]+vpsubd %zmm1, %zmm1, %zmm5
+[ ]*38[ ]+
+[ ]*39[ ]+vpsubq %zmm1, %zmm1, %zmm5\{%k7\}
+[ ]*40[ ]+vpsubq %zmm1, %zmm1, %zmm5
+[ ]*41[ ]+
+[ ]*42[ ]+kxord %k1, %k1, %k5
+[ ]*43[ ]+kxorq %k1, %k1, %k5
+[ ]*44[ ]+
+[ ]*45[ ]+kandnd %k1, %k1, %k5
+[ ]*46[ ]+kandnq %k1, %k1, %k5
+#pass
--- /dev/null
+# Check instructions with optimized encoding
+
+.include "optimize-6.s"
+++ /dev/null
-#source: optimize-6.s
-#as: -O2 -march=+noavx+noavx512vl
-#objdump: -drw
-#name: optimized encoding 6c with -O2
-
-.*: +file format .*
-
-
-Disassembly of section .text:
-
-0+ <_start>:
- +[a-f0-9]+: 62 f1 f5 4f 55 e9 vandnpd %zmm1,%zmm1,%zmm5\{%k7\}
- +[a-f0-9]+: 62 f1 f5 48 55 e9 vandnpd %zmm1,%zmm1,%zmm5
- +[a-f0-9]+: 62 f1 74 4f 55 e9 vandnps %zmm1,%zmm1,%zmm5\{%k7\}
- +[a-f0-9]+: 62 f1 74 48 55 e9 vandnps %zmm1,%zmm1,%zmm5
- +[a-f0-9]+: 62 f1 75 4f df e9 vpandnd %zmm1,%zmm1,%zmm5\{%k7\}
- +[a-f0-9]+: 62 f1 75 48 df e9 vpandnd %zmm1,%zmm1,%zmm5
- +[a-f0-9]+: 62 f1 f5 4f df e9 vpandnq %zmm1,%zmm1,%zmm5\{%k7\}
- +[a-f0-9]+: 62 f1 f5 48 df e9 vpandnq %zmm1,%zmm1,%zmm5
- +[a-f0-9]+: 62 f1 f5 4f 57 e9 vxorpd %zmm1,%zmm1,%zmm5\{%k7\}
- +[a-f0-9]+: 62 f1 f5 48 57 e9 vxorpd %zmm1,%zmm1,%zmm5
- +[a-f0-9]+: 62 f1 74 4f 57 e9 vxorps %zmm1,%zmm1,%zmm5\{%k7\}
- +[a-f0-9]+: 62 f1 74 48 57 e9 vxorps %zmm1,%zmm1,%zmm5
- +[a-f0-9]+: 62 f1 75 4f ef e9 vpxord %zmm1,%zmm1,%zmm5\{%k7\}
- +[a-f0-9]+: 62 f1 75 48 ef e9 vpxord %zmm1,%zmm1,%zmm5
- +[a-f0-9]+: 62 f1 f5 4f ef e9 vpxorq %zmm1,%zmm1,%zmm5\{%k7\}
- +[a-f0-9]+: 62 f1 f5 48 ef e9 vpxorq %zmm1,%zmm1,%zmm5
- +[a-f0-9]+: 62 f1 75 4f f8 e9 vpsubb %zmm1,%zmm1,%zmm5\{%k7\}
- +[a-f0-9]+: 62 f1 75 48 f8 e9 vpsubb %zmm1,%zmm1,%zmm5
- +[a-f0-9]+: 62 f1 75 4f f9 e9 vpsubw %zmm1,%zmm1,%zmm5\{%k7\}
- +[a-f0-9]+: 62 f1 75 48 f9 e9 vpsubw %zmm1,%zmm1,%zmm5
- +[a-f0-9]+: 62 f1 75 4f fa e9 vpsubd %zmm1,%zmm1,%zmm5\{%k7\}
- +[a-f0-9]+: 62 f1 75 48 fa e9 vpsubd %zmm1,%zmm1,%zmm5
- +[a-f0-9]+: 62 f1 f5 4f fb e9 vpsubq %zmm1,%zmm1,%zmm5\{%k7\}
- +[a-f0-9]+: 62 f1 f5 48 fb e9 vpsubq %zmm1,%zmm1,%zmm5
- +[a-f0-9]+: c5 f4 47 e9 kxorw %k1,%k1,%k5
- +[a-f0-9]+: c5 f4 47 e9 kxorw %k1,%k1,%k5
- +[a-f0-9]+: c5 f4 42 e9 kandnw %k1,%k1,%k5
- +[a-f0-9]+: c5 f4 42 e9 kandnw %k1,%k1,%k5
-#pass
+++ /dev/null
-#as: -O2 -march=+noavx
-#objdump: -drw
-#name: optimized encoding 7 with -O2
-
-.*: +file format .*
-
-
-Disassembly of section .text:
-
-0+ <_start>:
- +[a-f0-9]+: 62 f1 7d 28 6f d1 vmovdqa32 %ymm1,%ymm2
-#pass
--- /dev/null
+.*: Assembler messages:
+.*:6: Error: .*
+GAS LISTING .*
+
+
+[ ]*1[ ]+\# Check instructions with optimized encoding
+[ ]*2[ ]+
+[ ]*3[ ]+\.allow_index_reg
+[ ]*4[ ]+\.text
+[ ]*5[ ]+_start:
+[ ]*6[ ]+vmovdqa32 %ymm1, %ymm2
+#pass
+++ /dev/null
-#source: x86-64-optimize-7.s
-#as: -O2 -march=+noavx
-#objdump: -drw
-#name: x86-64 optimized encoding 7a with -O2
-
-.*: +file format .*
-
-
-Disassembly of section .text:
-
-0+ <_start>:
- +[a-f0-9]+: 62 71 f5 4f 55 f9 vandnpd %zmm1,%zmm1,%zmm15\{%k7\}
- +[a-f0-9]+: 62 71 f5 08 55 f9 vandnpd %xmm1,%xmm1,%xmm15
- +[a-f0-9]+: 62 e1 f5 08 55 c1 vandnpd %xmm1,%xmm1,%xmm16
- +[a-f0-9]+: 62 b1 f5 00 55 c9 vandnpd %xmm17,%xmm17,%xmm1
- +[a-f0-9]+: 62 71 74 4f 55 f9 vandnps %zmm1,%zmm1,%zmm15\{%k7\}
- +[a-f0-9]+: 62 71 74 08 55 f9 vandnps %xmm1,%xmm1,%xmm15
- +[a-f0-9]+: 62 e1 74 08 55 c1 vandnps %xmm1,%xmm1,%xmm16
- +[a-f0-9]+: 62 b1 74 00 55 c9 vandnps %xmm17,%xmm17,%xmm1
- +[a-f0-9]+: 62 71 75 4f df f9 vpandnd %zmm1,%zmm1,%zmm15\{%k7\}
- +[a-f0-9]+: 62 71 75 08 df f9 vpandnd %xmm1,%xmm1,%xmm15
- +[a-f0-9]+: 62 e1 75 08 df c1 vpandnd %xmm1,%xmm1,%xmm16
- +[a-f0-9]+: 62 b1 75 00 df c9 vpandnd %xmm17,%xmm17,%xmm1
- +[a-f0-9]+: 62 71 f5 4f df f9 vpandnq %zmm1,%zmm1,%zmm15\{%k7\}
- +[a-f0-9]+: 62 71 f5 08 df f9 vpandnq %xmm1,%xmm1,%xmm15
- +[a-f0-9]+: 62 e1 f5 08 df c1 vpandnq %xmm1,%xmm1,%xmm16
- +[a-f0-9]+: 62 b1 f5 00 df c9 vpandnq %xmm17,%xmm17,%xmm1
- +[a-f0-9]+: 62 71 f5 4f 57 f9 vxorpd %zmm1,%zmm1,%zmm15\{%k7\}
- +[a-f0-9]+: 62 71 f5 08 57 f9 vxorpd %xmm1,%xmm1,%xmm15
- +[a-f0-9]+: 62 e1 f5 08 57 c1 vxorpd %xmm1,%xmm1,%xmm16
- +[a-f0-9]+: 62 b1 f5 00 57 c9 vxorpd %xmm17,%xmm17,%xmm1
- +[a-f0-9]+: 62 71 74 4f 57 f9 vxorps %zmm1,%zmm1,%zmm15\{%k7\}
- +[a-f0-9]+: 62 71 74 08 57 f9 vxorps %xmm1,%xmm1,%xmm15
- +[a-f0-9]+: 62 e1 74 08 57 c1 vxorps %xmm1,%xmm1,%xmm16
- +[a-f0-9]+: 62 b1 74 00 57 c9 vxorps %xmm17,%xmm17,%xmm1
- +[a-f0-9]+: 62 71 75 4f ef f9 vpxord %zmm1,%zmm1,%zmm15\{%k7\}
- +[a-f0-9]+: 62 71 75 08 ef f9 vpxord %xmm1,%xmm1,%xmm15
- +[a-f0-9]+: 62 e1 75 08 ef c1 vpxord %xmm1,%xmm1,%xmm16
- +[a-f0-9]+: 62 b1 75 00 ef c9 vpxord %xmm17,%xmm17,%xmm1
- +[a-f0-9]+: 62 71 f5 4f ef f9 vpxorq %zmm1,%zmm1,%zmm15\{%k7\}
- +[a-f0-9]+: 62 71 f5 08 ef f9 vpxorq %xmm1,%xmm1,%xmm15
- +[a-f0-9]+: 62 e1 f5 08 ef c1 vpxorq %xmm1,%xmm1,%xmm16
- +[a-f0-9]+: 62 b1 f5 00 ef c9 vpxorq %xmm17,%xmm17,%xmm1
- +[a-f0-9]+: 62 71 75 4f f8 f9 vpsubb %zmm1,%zmm1,%zmm15\{%k7\}
- +[a-f0-9]+: 62 71 75 08 f8 f9 vpsubb %xmm1,%xmm1,%xmm15
- +[a-f0-9]+: 62 e1 75 08 f8 c1 vpsubb %xmm1,%xmm1,%xmm16
- +[a-f0-9]+: 62 b1 75 00 f8 c9 vpsubb %xmm17,%xmm17,%xmm1
- +[a-f0-9]+: 62 71 75 4f f9 f9 vpsubw %zmm1,%zmm1,%zmm15\{%k7\}
- +[a-f0-9]+: 62 71 75 08 f9 f9 vpsubw %xmm1,%xmm1,%xmm15
- +[a-f0-9]+: 62 e1 75 08 f9 c1 vpsubw %xmm1,%xmm1,%xmm16
- +[a-f0-9]+: 62 b1 75 00 f9 c9 vpsubw %xmm17,%xmm17,%xmm1
- +[a-f0-9]+: 62 71 75 4f fa f9 vpsubd %zmm1,%zmm1,%zmm15\{%k7\}
- +[a-f0-9]+: 62 71 75 08 fa f9 vpsubd %xmm1,%xmm1,%xmm15
- +[a-f0-9]+: 62 e1 75 08 fa c1 vpsubd %xmm1,%xmm1,%xmm16
- +[a-f0-9]+: 62 b1 75 00 fa c9 vpsubd %xmm17,%xmm17,%xmm1
- +[a-f0-9]+: 62 71 f5 4f fb f9 vpsubq %zmm1,%zmm1,%zmm15\{%k7\}
- +[a-f0-9]+: 62 71 f5 08 fb f9 vpsubq %xmm1,%xmm1,%xmm15
- +[a-f0-9]+: 62 e1 f5 08 fb c1 vpsubq %xmm1,%xmm1,%xmm16
- +[a-f0-9]+: 62 b1 f5 00 fb c9 vpsubq %xmm17,%xmm17,%xmm1
-#pass
--- /dev/null
+.*: Assembler messages:
+.*:6: Error: .*
+.*:7: Error: .*
+.*:8: Error: .*
+.*:9: Error: .*
+.*:11: Error: .*
+.*:12: Error: .*
+.*:13: Error: .*
+.*:14: Error: .*
+.*:16: Error: .*
+.*:17: Error: .*
+.*:18: Error: .*
+.*:19: Error: .*
+.*:21: Error: .*
+.*:22: Error: .*
+.*:23: Error: .*
+.*:24: Error: .*
+.*:26: Error: .*
+.*:27: Error: .*
+.*:28: Error: .*
+.*:29: Error: .*
+.*:31: Error: .*
+.*:32: Error: .*
+.*:33: Error: .*
+.*:34: Error: .*
+.*:36: Error: .*
+.*:37: Error: .*
+.*:38: Error: .*
+.*:39: Error: .*
+.*:41: Error: .*
+.*:42: Error: .*
+.*:43: Error: .*
+.*:44: Error: .*
+.*:46: Error: .*
+.*:47: Error: .*
+.*:48: Error: .*
+.*:49: Error: .*
+.*:51: Error: .*
+.*:52: Error: .*
+.*:53: Error: .*
+.*:54: Error: .*
+.*:56: Error: .*
+.*:57: Error: .*
+.*:58: Error: .*
+.*:59: Error: .*
+.*:61: Error: .*
+.*:62: Error: .*
+.*:63: Error: .*
+.*:64: Error: .*
+GAS LISTING .*
+
+
+[ ]*1[ ]+\# Check 64bit instructions with optimized encoding
+[ ]*2[ ]+
+[ ]*3[ ]+\.include "x86-64-optimize-7\.s"
+[ ]*1[ ]+\# Check 64bit instructions with optimized encoding
+[ ]*2[ ]+
+[ ]*3[ ]+\.allow_index_reg
+[ ]*4[ ]+\.text
+[ ]*5[ ]+_start:
+[ ]*6[ ]+vandnpd %zmm1, %zmm1, %zmm15\{%k7\}
+[ ]*7[ ]+vandnpd %zmm1, %zmm1, %zmm15
+[ ]*8[ ]+vandnpd %zmm1, %zmm1, %zmm16
+[ ]*9[ ]+vandnpd %zmm17, %zmm17, %zmm1
+[ ]*10[ ]+
+[ ]*11[ ]+vandnps %zmm1, %zmm1, %zmm15\{%k7\}
+[ ]*12[ ]+vandnps %zmm1, %zmm1, %zmm15
+[ ]*13[ ]+vandnps %zmm1, %zmm1, %zmm16
+[ ]*14[ ]+vandnps %zmm17, %zmm17, %zmm1
+[ ]*15[ ]+
+[ ]*16[ ]+vpandnd %zmm1, %zmm1, %zmm15\{%k7\}
+[ ]*17[ ]+vpandnd %zmm1, %zmm1, %zmm15
+[ ]*18[ ]+vpandnd %zmm1, %zmm1, %zmm16
+[ ]*19[ ]+vpandnd %zmm17, %zmm17, %zmm1
+[ ]*20[ ]+
+[ ]*21[ ]+vpandnq %zmm1, %zmm1, %zmm15\{%k7\}
+[ ]*22[ ]+vpandnq %zmm1, %zmm1, %zmm15
+[ ]*23[ ]+vpandnq %zmm1, %zmm1, %zmm16
+[ ]*24[ ]+vpandnq %zmm17, %zmm17, %zmm1
+[ ]*25[ ]+
+[ ]*26[ ]+vxorpd %zmm1, %zmm1, %zmm15\{%k7\}
+[ ]*27[ ]+vxorpd %zmm1, %zmm1, %zmm15
+[ ]*28[ ]+vxorpd %zmm1, %zmm1, %zmm16
+[ ]*29[ ]+vxorpd %zmm17, %zmm17, %zmm1
+[ ]*30[ ]+
+[ ]*31[ ]+vxorps %zmm1, %zmm1, %zmm15\{%k7\}
+[ ]*32[ ]+vxorps %zmm1, %zmm1, %zmm15
+[ ]*33[ ]+vxorps %zmm1, %zmm1, %zmm16
+[ ]*34[ ]+vxorps %zmm17, %zmm17, %zmm1
+[ ]*35[ ]+
+[ ]*36[ ]+vpxord %zmm1, %zmm1, %zmm15\{%k7\}
+[ ]*37[ ]+vpxord %zmm1, %zmm1, %zmm15
+[ ]*38[ ]+vpxord %zmm1, %zmm1, %zmm16
+[ ]*39[ ]+vpxord %zmm17, %zmm17, %zmm1
+[ ]*40[ ]+
+[ ]*41[ ]+vpxorq %zmm1, %zmm1, %zmm15\{%k7\}
+[ ]*42[ ]+vpxorq %zmm1, %zmm1, %zmm15
+[ ]*43[ ]+vpxorq %zmm1, %zmm1, %zmm16
+[ ]*44[ ]+vpxorq %zmm17, %zmm17, %zmm1
+[ ]*45[ ]+
+[ ]*46[ ]+vpsubb %zmm1, %zmm1, %zmm15\{%k7\}
+[ ]*47[ ]+vpsubb %zmm1, %zmm1, %zmm15
+[ ]*48[ ]+vpsubb %zmm1, %zmm1, %zmm16
+[ ]*49[ ]+vpsubb %zmm17, %zmm17, %zmm1
+[ ]*50[ ]+
+[ ]*51[ ]+vpsubw %zmm1, %zmm1, %zmm15\{%k7\}
+[ ]*52[ ]+vpsubw %zmm1, %zmm1, %zmm15
+[ ]*53[ ]+vpsubw %zmm1, %zmm1, %zmm16
+[ ]*54[ ]+vpsubw %zmm17, %zmm17, %zmm1
+\fGAS LISTING .*
+
+
+[ ]*55[ ]+
+[ ]*56[ ]+vpsubd %zmm1, %zmm1, %zmm15\{%k7\}
+[ ]*57[ ]+vpsubd %zmm1, %zmm1, %zmm15
+[ ]*58[ ]+vpsubd %zmm1, %zmm1, %zmm16
+[ ]*59[ ]+vpsubd %zmm17, %zmm17, %zmm1
+[ ]*60[ ]+
+[ ]*61[ ]+vpsubq %zmm1, %zmm1, %zmm15\{%k7\}
+[ ]*62[ ]+vpsubq %zmm1, %zmm1, %zmm15
+[ ]*63[ ]+vpsubq %zmm1, %zmm1, %zmm16
+[ ]*64[ ]+vpsubq %zmm17, %zmm17, %zmm1
+#pass
--- /dev/null
+# Check 64bit instructions with optimized encoding
+
+.include "x86-64-optimize-7.s"
+++ /dev/null
-#source: x86-64-optimize-7.s
-#as: -O2 -march=+noavx+noavx512vl
-#objdump: -drw
-#name: x86-64 optimized encoding 7c with -O2
-
-.*: +file format .*
-
-
-Disassembly of section .text:
-
-0+ <_start>:
- +[a-f0-9]+: 62 71 f5 4f 55 f9 vandnpd %zmm1,%zmm1,%zmm15\{%k7\}
- +[a-f0-9]+: 62 71 f5 48 55 f9 vandnpd %zmm1,%zmm1,%zmm15
- +[a-f0-9]+: 62 e1 f5 48 55 c1 vandnpd %zmm1,%zmm1,%zmm16
- +[a-f0-9]+: 62 b1 f5 40 55 c9 vandnpd %zmm17,%zmm17,%zmm1
- +[a-f0-9]+: 62 71 74 4f 55 f9 vandnps %zmm1,%zmm1,%zmm15\{%k7\}
- +[a-f0-9]+: 62 71 74 48 55 f9 vandnps %zmm1,%zmm1,%zmm15
- +[a-f0-9]+: 62 e1 74 48 55 c1 vandnps %zmm1,%zmm1,%zmm16
- +[a-f0-9]+: 62 b1 74 40 55 c9 vandnps %zmm17,%zmm17,%zmm1
- +[a-f0-9]+: 62 71 75 4f df f9 vpandnd %zmm1,%zmm1,%zmm15\{%k7\}
- +[a-f0-9]+: 62 71 75 48 df f9 vpandnd %zmm1,%zmm1,%zmm15
- +[a-f0-9]+: 62 e1 75 48 df c1 vpandnd %zmm1,%zmm1,%zmm16
- +[a-f0-9]+: 62 b1 75 40 df c9 vpandnd %zmm17,%zmm17,%zmm1
- +[a-f0-9]+: 62 71 f5 4f df f9 vpandnq %zmm1,%zmm1,%zmm15\{%k7\}
- +[a-f0-9]+: 62 71 f5 48 df f9 vpandnq %zmm1,%zmm1,%zmm15
- +[a-f0-9]+: 62 e1 f5 48 df c1 vpandnq %zmm1,%zmm1,%zmm16
- +[a-f0-9]+: 62 b1 f5 40 df c9 vpandnq %zmm17,%zmm17,%zmm1
- +[a-f0-9]+: 62 71 f5 4f 57 f9 vxorpd %zmm1,%zmm1,%zmm15\{%k7\}
- +[a-f0-9]+: 62 71 f5 48 57 f9 vxorpd %zmm1,%zmm1,%zmm15
- +[a-f0-9]+: 62 e1 f5 48 57 c1 vxorpd %zmm1,%zmm1,%zmm16
- +[a-f0-9]+: 62 b1 f5 40 57 c9 vxorpd %zmm17,%zmm17,%zmm1
- +[a-f0-9]+: 62 71 74 4f 57 f9 vxorps %zmm1,%zmm1,%zmm15\{%k7\}
- +[a-f0-9]+: 62 71 74 48 57 f9 vxorps %zmm1,%zmm1,%zmm15
- +[a-f0-9]+: 62 e1 74 48 57 c1 vxorps %zmm1,%zmm1,%zmm16
- +[a-f0-9]+: 62 b1 74 40 57 c9 vxorps %zmm17,%zmm17,%zmm1
- +[a-f0-9]+: 62 71 75 4f ef f9 vpxord %zmm1,%zmm1,%zmm15\{%k7\}
- +[a-f0-9]+: 62 71 75 48 ef f9 vpxord %zmm1,%zmm1,%zmm15
- +[a-f0-9]+: 62 e1 75 48 ef c1 vpxord %zmm1,%zmm1,%zmm16
- +[a-f0-9]+: 62 b1 75 40 ef c9 vpxord %zmm17,%zmm17,%zmm1
- +[a-f0-9]+: 62 71 f5 4f ef f9 vpxorq %zmm1,%zmm1,%zmm15\{%k7\}
- +[a-f0-9]+: 62 71 f5 48 ef f9 vpxorq %zmm1,%zmm1,%zmm15
- +[a-f0-9]+: 62 e1 f5 48 ef c1 vpxorq %zmm1,%zmm1,%zmm16
- +[a-f0-9]+: 62 b1 f5 40 ef c9 vpxorq %zmm17,%zmm17,%zmm1
- +[a-f0-9]+: 62 71 75 4f f8 f9 vpsubb %zmm1,%zmm1,%zmm15\{%k7\}
- +[a-f0-9]+: 62 71 75 48 f8 f9 vpsubb %zmm1,%zmm1,%zmm15
- +[a-f0-9]+: 62 e1 75 48 f8 c1 vpsubb %zmm1,%zmm1,%zmm16
- +[a-f0-9]+: 62 b1 75 40 f8 c9 vpsubb %zmm17,%zmm17,%zmm1
- +[a-f0-9]+: 62 71 75 4f f9 f9 vpsubw %zmm1,%zmm1,%zmm15\{%k7\}
- +[a-f0-9]+: 62 71 75 48 f9 f9 vpsubw %zmm1,%zmm1,%zmm15
- +[a-f0-9]+: 62 e1 75 48 f9 c1 vpsubw %zmm1,%zmm1,%zmm16
- +[a-f0-9]+: 62 b1 75 40 f9 c9 vpsubw %zmm17,%zmm17,%zmm1
- +[a-f0-9]+: 62 71 75 4f fa f9 vpsubd %zmm1,%zmm1,%zmm15\{%k7\}
- +[a-f0-9]+: 62 71 75 48 fa f9 vpsubd %zmm1,%zmm1,%zmm15
- +[a-f0-9]+: 62 e1 75 48 fa c1 vpsubd %zmm1,%zmm1,%zmm16
- +[a-f0-9]+: 62 b1 75 40 fa c9 vpsubd %zmm17,%zmm17,%zmm1
- +[a-f0-9]+: 62 71 f5 4f fb f9 vpsubq %zmm1,%zmm1,%zmm15\{%k7\}
- +[a-f0-9]+: 62 71 f5 48 fb f9 vpsubq %zmm1,%zmm1,%zmm15
- +[a-f0-9]+: 62 e1 f5 48 fb c1 vpsubq %zmm1,%zmm1,%zmm16
- +[a-f0-9]+: 62 b1 f5 40 fb c9 vpsubq %zmm17,%zmm17,%zmm1
-#pass
+++ /dev/null
-#as: -O2 -march=+noavx
-#objdump: -drw
-#name: x86-64 optimized encoding 8 with -O2
-
-.*: +file format .*
-
-
-Disassembly of section .text:
-
-0+ <_start>:
- +[a-f0-9]+: 62 f1 7d 28 6f d1 vmovdqa32 %ymm1,%ymm2
-#pass
--- /dev/null
+.*: Assembler messages:
+.*:6: Error: .*
+GAS LISTING .*
+
+
+[ ]*1[ ]+\# Check 64bit instructions with optimized encoding
+[ ]*2[ ]+
+[ ]*3[ ]+\.allow_index_reg
+[ ]*4[ ]+\.text
+[ ]*5[ ]+_start:
+[ ]*6[ ]+vmovdqa32 %ymm1, %ymm2
+#pass
+2019-03-19 H.J. Lu <hongjiu.lu@intel.com>
+
+ PR gas/24359
+ * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS to
+ CPU_ANY_AVX2_FLAGS.
+ * i386-init.h: Regenerated.
+
2019-03-18 H.J. Lu <hongjiu.lu@intel.com>
PR gas/24348
{ "CPU_ANY_AVX_FLAGS",
"CPU_ANY_AVX2_FLAGS|CpuF16C|CpuFMA|CpuFMA4|CpuXOP|CpuAVX" },
{ "CPU_ANY_AVX2_FLAGS",
- "CpuAVX2" },
+ "CPU_ANY_AVX512F_FLAGS|CpuAVX2" },
{ "CPU_ANY_AVX512F_FLAGS",
"CpuAVX512F|CpuAVX512CD|CpuAVX512ER|CpuAVX512PF|CpuAVX512DQ|CpuAVX512BW|CpuAVX512VL|CpuAVX512IFMA|CpuAVX512VBMI|CpuAVX512_4FMAPS|CpuAVX512_4VNNIW|CpuAVX512_VPOPCNTDQ|CpuAVX512_VBMI2|CpuAVX512_VNNI|CpuAVX512_BITALG" },
{ "CPU_ANY_AVX512CD_FLAGS",
#define CPU_ANY_AVX_FLAGS \
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, \
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, \
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, \
+ 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0 } }
#define CPU_ANY_AVX2_FLAGS \
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, \
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, \
+ 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0 } }
#define CPU_ANY_AVX512F_FLAGS \
projects / deliverable / binutils-gdb.git / commitdiff
