From: Jan Beulich <jbeulich@suse.com>
Date: Thu, 9 Jan 2020 10:38:59 +0000 (+0100)
Subject: x86: consistently convert to byte registers for TEST w/ imm optimization
X-Git-Url: http://git.efficios.com/?p=deliverable%2Fbinutils-gdb.git;a=commitdiff_plain;h=7697afb662b2ffd67d044209d6d807a8e21dfed9

x86: consistently convert to byte registers for TEST w/ imm optimization

Commit ac0ab1842d ("i386: Also check R12-R15 registers when optimizing
testq to testb") didn't go quite far enough: In order to avoid confusing
other code registers would better be converted to byte ones uniformly.
---

diff --git a/gas/ChangeLog b/gas/ChangeLog
index 116617a928..c3045c13ef 100644
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,3 +1,8 @@
+2020-01-09  Jan Beulich  <jbeulich@suse.com>
+
+	* config/tc-i386.c (optimize_encoding): Generalize register
+	transformation for TEST optimization.
+
 2020-01-09  Jan Beulich  <jbeulich@suse.com>
 
 	* testsuite/gas/i386/x86-64-sysenter-amd.s,
diff --git a/gas/config/tc-i386.c b/gas/config/tc-i386.c
index d0b8f2624a..efa4365092 100644
--- a/gas/config/tc-i386.c
+++ b/gas/config/tc-i386.c
@@ -4009,17 +4009,16 @@ optimize_encoding (void)
 	  i.types[1].bitfield.byte = 1;
 	  /* Ignore the suffix.  */
 	  i.suffix = 0;
-	  if (base_regnum >= 4)
-	    {
-	      /* Handle SP, BP, SI, DI and R12-R15 registers.  */
-	      if (i.types[1].bitfield.word)
-		j = 16;
-	      else if (i.types[1].bitfield.dword)
-		j = 32;
-	      else
-		j = 48;
-	      i.op[1].regs -= j;
-	    }
+	  /* Convert to byte registers.  */
+	  if (i.types[1].bitfield.word)
+	    j = 16;
+	  else if (i.types[1].bitfield.dword)
+	    j = 32;
+	  else
+	    j = 48;
+	  if (!(i.op[1].regs->reg_flags & RegRex) && base_regnum < 4)
+	    j += 8;
+	  i.op[1].regs -= j;
 	}
     }
   else if (flag_code == CODE_64BIT