[deliverable/linux.git] / Documentation / devicetree / bindings / arm / cpus.txt

=================
ARM CPUs bindings
=================

The device tree allows to describe the layout of CPUs in a system through
the "cpus" node, which in turn contains a number of subnodes (ie "cpu")
defining properties for every cpu.

Bindings for CPU nodes follow the ePAPR v1.1 standard, available from:

https://www.power.org/documentation/epapr-version-1-1/

with updates for 32-bit and 64-bit ARM systems provided in this document.

================================
Convention used in this document
================================

This document follows the conventions described in the ePAPR v1.1, with
the addition:

- square brackets define bitfields, eg reg[7:0] value of the bitfield in
  the reg property contained in bits 7 down to 0

=====================================
cpus and cpu node bindings definition
=====================================

The ARM architecture, in accordance with the ePAPR, requires the cpus and cpu
nodes to be present and contain the properties described below.

- cpus node

	Description: Container of cpu nodes

	The node name must be "cpus".

	A cpus node must define the following properties:

	- #address-cells
		Usage: required
		Value type: <u32>

		Definition depends on ARM architecture version and
		configuration:

			# On uniprocessor ARM architectures previous to v7
			  value must be 1, to enable a simple enumeration
			  scheme for processors that do not have a HW CPU
			  identification register.
			# On 32-bit ARM 11 MPcore, ARM v7 or later systems
			  value must be 1, that corresponds to CPUID/MPIDR
			  registers sizes.
			# On ARM v8 64-bit systems value should be set to 2,
			  that corresponds to the MPIDR_EL1 register size.
			  If MPIDR_EL1[63:32] value is equal to 0 on all CPUs
			  in the system, #address-cells can be set to 1, since
			  MPIDR_EL1[63:32] bits are not used for CPUs
			  identification.
	- #size-cells
		Usage: required
		Value type: <u32>
		Definition: must be set to 0

- cpu node

	Description: Describes a CPU in an ARM based system

	PROPERTIES

	- device_type
		Usage: required
		Value type: <string>
		Definition: must be "cpu"
	- reg
		Usage and definition depend on ARM architecture version and
		configuration:

			# On uniprocessor ARM architectures previous to v7
			  this property is required and must be set to 0.

			# On ARM 11 MPcore based systems this property is
			  required and matches the CPUID[11:0] register bits.

			  Bits [11:0] in the reg cell must be set to
			  bits [11:0] in CPU ID register.

			  All other bits in the reg cell must be set to 0.

			# On 32-bit ARM v7 or later systems this property is
			  required and matches the CPU MPIDR[23:0] register
			  bits.

			  Bits [23:0] in the reg cell must be set to
			  bits [23:0] in MPIDR.

			  All other bits in the reg cell must be set to 0.

			# On ARM v8 64-bit systems this property is required
			  and matches the MPIDR_EL1 register affinity bits.

			  * If cpus node's #address-cells property is set to 2

			    The first reg cell bits [7:0] must be set to
			    bits [39:32] of MPIDR_EL1.

			    The second reg cell bits [23:0] must be set to
			    bits [23:0] of MPIDR_EL1.

			  * If cpus node's #address-cells property is set to 1

			    The reg cell bits [23:0] must be set to bits [23:0]
			    of MPIDR_EL1.

			  All other bits in the reg cells must be set to 0.

	- compatible:
		Usage: required
		Value type: <string>
		Definition: should be one of:
			    "arm,arm710t"
			    "arm,arm720t"
			    "arm,arm740t"
			    "arm,arm7ej-s"
			    "arm,arm7tdmi"
			    "arm,arm7tdmi-s"
			    "arm,arm9es"
			    "arm,arm9ej-s"
			    "arm,arm920t"
			    "arm,arm922t"
			    "arm,arm925"
			    "arm,arm926e-s"
			    "arm,arm926ej-s"
			    "arm,arm940t"
			    "arm,arm946e-s"
			    "arm,arm966e-s"
			    "arm,arm968e-s"
			    "arm,arm9tdmi"
			    "arm,arm1020e"
			    "arm,arm1020t"
			    "arm,arm1022e"
			    "arm,arm1026ej-s"
			    "arm,arm1136j-s"
			    "arm,arm1136jf-s"
			    "arm,arm1156t2-s"
			    "arm,arm1156t2f-s"
			    "arm,arm1176jzf"
			    "arm,arm1176jz-s"
			    "arm,arm1176jzf-s"
			    "arm,arm11mpcore"
			    "arm,cortex-a5"
			    "arm,cortex-a7"
			    "arm,cortex-a8"
			    "arm,cortex-a9"
			    "arm,cortex-a12"
			    "arm,cortex-a15"
			    "arm,cortex-a17"
			    "arm,cortex-a53"
			    "arm,cortex-a57"
			    "arm,cortex-a72"
			    "arm,cortex-m0"
			    "arm,cortex-m0+"
			    "arm,cortex-m1"
			    "arm,cortex-m3"
			    "arm,cortex-m4"
			    "arm,cortex-r4"
			    "arm,cortex-r5"
			    "arm,cortex-r7"
			    "brcm,brahma-b15"
			    "brcm,vulcan"
			    "cavium,thunder"
			    "faraday,fa526"
			    "intel,sa110"
			    "intel,sa1100"
			    "marvell,feroceon"
			    "marvell,mohawk"
			    "marvell,pj4a"
			    "marvell,pj4b"
			    "marvell,sheeva-v5"
			    "nvidia,tegra132-denver"
			    "qcom,krait"
			    "qcom,kryo"
			    "qcom,scorpion"
	- enable-method
		Value type: <stringlist>
		Usage and definition depend on ARM architecture version.
			# On ARM v8 64-bit this property is required and must
			  be one of:
			     "psci"
			     "spin-table"
			# On ARM 32-bit systems this property is optional and
			  can be one of:
			    "allwinner,sun6i-a31"
			    "allwinner,sun8i-a23"
			    "arm,realview-smp"
			    "brcm,bcm-nsp-smp"
			    "brcm,brahma-b15"
			    "marvell,armada-375-smp"
			    "marvell,armada-380-smp"
			    "marvell,armada-390-smp"
			    "marvell,armada-xp-smp"
			    "mediatek,mt6589-smp"
			    "mediatek,mt81xx-tz-smp"
			    "qcom,gcc-msm8660"
			    "qcom,kpss-acc-v1"
			    "qcom,kpss-acc-v2"
			    "rockchip,rk3036-smp"
			    "rockchip,rk3066-smp"
			    "ste,dbx500-smp"

	- cpu-release-addr
		Usage: required for systems that have an "enable-method"
		       property value of "spin-table".
		Value type: <prop-encoded-array>
		Definition:
			# On ARM v8 64-bit systems must be a two cell
			  property identifying a 64-bit zero-initialised
			  memory location.

	- qcom,saw
		Usage: required for systems that have an "enable-method"
		       property value of "qcom,kpss-acc-v1" or
		       "qcom,kpss-acc-v2"
		Value type: <phandle>
		Definition: Specifies the SAW[1] node associated with this CPU.

	- qcom,acc
		Usage: required for systems that have an "enable-method"
		       property value of "qcom,kpss-acc-v1" or
		       "qcom,kpss-acc-v2"
		Value type: <phandle>
		Definition: Specifies the ACC[2] node associated with this CPU.

	- cpu-idle-states
		Usage: Optional
		Value type: <prop-encoded-array>
		Definition:
			# List of phandles to idle state nodes supported
			  by this cpu [3].

	- rockchip,pmu
		Usage: optional for systems that have an "enable-method"
		       property value of "rockchip,rk3066-smp"
		       While optional, it is the preferred way to get access to
		       the cpu-core power-domains.
		Value type: <phandle>
		Definition: Specifies the syscon node controlling the cpu core
			    power domains.

	- dynamic-power-coefficient
		Usage: optional
		Value type: <prop-encoded-array>
		Definition: A u32 value that represents the running time dynamic
			    power coefficient in units of mW/MHz/uV^2. The
			    coefficient can either be calculated from power
			    measurements or derived by analysis.

			    The dynamic power consumption of the CPU  is
			    proportional to the square of the Voltage (V) and
			    the clock frequency (f). The coefficient is used to
			    calculate the dynamic power as below -

			    Pdyn = dynamic-power-coefficient * V^2 * f

			    where voltage is in uV, frequency is in MHz.

Example 1 (dual-cluster big.LITTLE system 32-bit):

	cpus {
		#size-cells = <0>;
		#address-cells = <1>;

		cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a15";
			reg = <0x0>;
		};

		cpu@1 {
			device_type = "cpu";
			compatible = "arm,cortex-a15";
			reg = <0x1>;
		};

		cpu@100 {
			device_type = "cpu";
			compatible = "arm,cortex-a7";
			reg = <0x100>;
		};

		cpu@101 {
			device_type = "cpu";
			compatible = "arm,cortex-a7";
			reg = <0x101>;
		};
	};

Example 2 (Cortex-A8 uniprocessor 32-bit system):

	cpus {
		#size-cells = <0>;
		#address-cells = <1>;

		cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a8";
			reg = <0x0>;
		};
	};

Example 3 (ARM 926EJ-S uniprocessor 32-bit system):

	cpus {
		#size-cells = <0>;
		#address-cells = <1>;

		cpu@0 {
			device_type = "cpu";
			compatible = "arm,arm926ej-s";
			reg = <0x0>;
		};
	};

Example 4 (ARM Cortex-A57 64-bit system):

cpus {
	#size-cells = <0>;
	#address-cells = <2>;

	cpu@0 {
		device_type = "cpu";
		compatible = "arm,cortex-a57";
		reg = <0x0 0x0>;
		enable-method = "spin-table";
		cpu-release-addr = <0 0x20000000>;
	};

	cpu@1 {
		device_type = "cpu";
		compatible = "arm,cortex-a57";
		reg = <0x0 0x1>;
		enable-method = "spin-table";
		cpu-release-addr = <0 0x20000000>;
	};

	cpu@100 {
		device_type = "cpu";
		compatible = "arm,cortex-a57";
		reg = <0x0 0x100>;
		enable-method = "spin-table";
		cpu-release-addr = <0 0x20000000>;
	};

	cpu@101 {
		device_type = "cpu";
		compatible = "arm,cortex-a57";
		reg = <0x0 0x101>;
		enable-method = "spin-table";
		cpu-release-addr = <0 0x20000000>;
	};

	cpu@10000 {
		device_type = "cpu";
		compatible = "arm,cortex-a57";
		reg = <0x0 0x10000>;
		enable-method = "spin-table";
		cpu-release-addr = <0 0x20000000>;
	};

	cpu@10001 {
		device_type = "cpu";
		compatible = "arm,cortex-a57";
		reg = <0x0 0x10001>;
		enable-method = "spin-table";
		cpu-release-addr = <0 0x20000000>;
	};

	cpu@10100 {
		device_type = "cpu";
		compatible = "arm,cortex-a57";
		reg = <0x0 0x10100>;
		enable-method = "spin-table";
		cpu-release-addr = <0 0x20000000>;
	};

	cpu@10101 {
		device_type = "cpu";
		compatible = "arm,cortex-a57";
		reg = <0x0 0x10101>;
		enable-method = "spin-table";
		cpu-release-addr = <0 0x20000000>;
	};

	cpu@100000000 {
		device_type = "cpu";
		compatible = "arm,cortex-a57";
		reg = <0x1 0x0>;
		enable-method = "spin-table";
		cpu-release-addr = <0 0x20000000>;
	};

	cpu@100000001 {
		device_type = "cpu";
		compatible = "arm,cortex-a57";
		reg = <0x1 0x1>;
		enable-method = "spin-table";
		cpu-release-addr = <0 0x20000000>;
	};

	cpu@100000100 {
		device_type = "cpu";
		compatible = "arm,cortex-a57";
		reg = <0x1 0x100>;
		enable-method = "spin-table";
		cpu-release-addr = <0 0x20000000>;
	};

	cpu@100000101 {
		device_type = "cpu";
		compatible = "arm,cortex-a57";
		reg = <0x1 0x101>;
		enable-method = "spin-table";
		cpu-release-addr = <0 0x20000000>;
	};

	cpu@100010000 {
		device_type = "cpu";
		compatible = "arm,cortex-a57";
		reg = <0x1 0x10000>;
		enable-method = "spin-table";
		cpu-release-addr = <0 0x20000000>;
	};

	cpu@100010001 {
		device_type = "cpu";
		compatible = "arm,cortex-a57";
		reg = <0x1 0x10001>;
		enable-method = "spin-table";
		cpu-release-addr = <0 0x20000000>;
	};

	cpu@100010100 {
		device_type = "cpu";
		compatible = "arm,cortex-a57";
		reg = <0x1 0x10100>;
		enable-method = "spin-table";
		cpu-release-addr = <0 0x20000000>;
	};

	cpu@100010101 {
		device_type = "cpu";
		compatible = "arm,cortex-a57";
		reg = <0x1 0x10101>;
		enable-method = "spin-table";
		cpu-release-addr = <0 0x20000000>;
	};
};

--
[1] arm/msm/qcom,saw2.txt
[2] arm/msm/qcom,kpss-acc.txt
[3] ARM Linux kernel documentation - idle states bindings
    Documentation/devicetree/bindings/arm/idle-states.txt
Commit	Line	Data
594f88d1 LP	1	=================
	2	ARM CPUs bindings
	3	=================
a0ae0240 LP	4
	5	The device tree allows to describe the layout of CPUs in a system through
	6	the "cpus" node, which in turn contains a number of subnodes (ie "cpu")
	7	defining properties for every cpu.
	8
594f88d1 LP	9	Bindings for CPU nodes follow the ePAPR v1.1 standard, available from:
	10
	11	https://www.power.org/documentation/epapr-version-1-1/
	12
	13	with updates for 32-bit and 64-bit ARM systems provided in this document.
	14
	15	================================
	16	Convention used in this document
	17	================================
	18
	19	This document follows the conventions described in the ePAPR v1.1, with
	20	the addition:
	21
	22	- square brackets define bitfields, eg reg[7:0] value of the bitfield in
	23	the reg property contained in bits 7 down to 0
	24
	25	=====================================
	26	cpus and cpu node bindings definition
	27	=====================================
	28
	29	The ARM architecture, in accordance with the ePAPR, requires the cpus and cpu
	30	nodes to be present and contain the properties described below.
	31
	32	- cpus node
	33
	34	Description: Container of cpu nodes
	35
	36	The node name must be "cpus".
	37
	38	A cpus node must define the following properties:
	39
	40	- #address-cells
	41	Usage: required
	42	Value type: <u32>
	43
	44	Definition depends on ARM architecture version and
	45	configuration:
	46
	47	# On uniprocessor ARM architectures previous to v7
	48	value must be 1, to enable a simple enumeration
	49	scheme for processors that do not have a HW CPU
	50	identification register.
	51	# On 32-bit ARM 11 MPcore, ARM v7 or later systems
	52	value must be 1, that corresponds to CPUID/MPIDR
	53	registers sizes.
	54	# On ARM v8 64-bit systems value should be set to 2,
	55	that corresponds to the MPIDR_EL1 register size.
	56	If MPIDR_EL1[63:32] value is equal to 0 on all CPUs
	57	in the system, #address-cells can be set to 1, since
	58	MPIDR_EL1[63:32] bits are not used for CPUs
	59	identification.
	60	- #size-cells
	61	Usage: required
	62	Value type: <u32>
	63	Definition: must be set to 0
	64
	65	- cpu node
	66
	67	Description: Describes a CPU in an ARM based system
	68
	69	PROPERTIES
	70
	71	- device_type
	72	Usage: required
73	Value type: <string>
74	Definition: must be "cpu"
75	- reg
76	Usage and definition depend on ARM architecture version and
77	configuration:
78
79	# On uniprocessor ARM architectures previous to v7
80	this property is required and must be set to 0.
81
82	# On ARM 11 MPcore based systems this property is
83	required and matches the CPUID[11:0] register bits.
84
85	Bits [11:0] in the reg cell must be set to
86	bits [11:0] in CPU ID register.
87
88	All other bits in the reg cell must be set to 0.
89
90	# On 32-bit ARM v7 or later systems this property is
91	required and matches the CPU MPIDR[23:0] register
92	bits.
93
94	Bits [23:0] in the reg cell must be set to
95	bits [23:0] in MPIDR.
96
97	All other bits in the reg cell must be set to 0.
98
99	# On ARM v8 64-bit systems this property is required
100	and matches the MPIDR_EL1 register affinity bits.
101
102	* If cpus node's #address-cells property is set to 2
103
104	The first reg cell bits [7:0] must be set to
105	bits [39:32] of MPIDR_EL1.
106
107	The second reg cell bits [23:0] must be set to
108	bits [23:0] of MPIDR_EL1.
109
110	* If cpus node's #address-cells property is set to 1
111
112	The reg cell bits [23:0] must be set to bits [23:0]
113	of MPIDR_EL1.
114
115	All other bits in the reg cells must be set to 0.
116
117	- compatible:
118	Usage: required
119	Value type: <string>
120	Definition: should be one of:
121	"arm,arm710t"
122	"arm,arm720t"
123	"arm,arm740t"
124	"arm,arm7ej-s"
125	"arm,arm7tdmi"
126	"arm,arm7tdmi-s"
127	"arm,arm9es"
128	"arm,arm9ej-s"
129	"arm,arm920t"
130	"arm,arm922t"
131	"arm,arm925"
132	"arm,arm926e-s"
133	"arm,arm926ej-s"
134	"arm,arm940t"
135	"arm,arm946e-s"
136	"arm,arm966e-s"
137	"arm,arm968e-s"
138	"arm,arm9tdmi"
139	"arm,arm1020e"
140	"arm,arm1020t"
141	"arm,arm1022e"
142	"arm,arm1026ej-s"
143	"arm,arm1136j-s"
144	"arm,arm1136jf-s"
145	"arm,arm1156t2-s"
146	"arm,arm1156t2f-s"
147	"arm,arm1176jzf"
148	"arm,arm1176jz-s"
149	"arm,arm1176jzf-s"
150	"arm,arm11mpcore"
151	"arm,cortex-a5"
152	"arm,cortex-a7"
153	"arm,cortex-a8"
154	"arm,cortex-a9"
198946b1	155	"arm,cortex-a12"
594f88d1	156	"arm,cortex-a15"
198946b1	157	"arm,cortex-a17"
594f88d1 LP	158	"arm,cortex-a53"
594f88d1 LP	159	"arm,cortex-a57"
182f4f09	160	"arm,cortex-a72"
594f88d1 LP	161	"arm,cortex-m0"
	162	"arm,cortex-m0+"
	163	"arm,cortex-m1"
	164	"arm,cortex-m3"
	165	"arm,cortex-m4"
	166	"arm,cortex-r4"
	167	"arm,cortex-r5"
	168	"arm,cortex-r7"
0a540d4b	169	"brcm,brahma-b15"
f008decc	170	"brcm,vulcan"
4c308700	171	"cavium,thunder"
594f88d1 LP	172	"faraday,fa526"
	173	"intel,sa110"
	174	"intel,sa1100"
	175	"marvell,feroceon"
	176	"marvell,mohawk"
	177	"marvell,pj4a"
	178	"marvell,pj4b"
	179	"marvell,sheeva-v5"
f634da37	180	"nvidia,tegra132-denver"
594f88d1	181	"qcom,krait"
bd301eee	182	"qcom,kryo"
594f88d1 LP	183	"qcom,scorpion"
	184	- enable-method
	185	Value type: <stringlist>
	186	Usage and definition depend on ARM architecture version.
	187	# On ARM v8 64-bit this property is required and must
	188	be one of:
594f88d1	189	"psci"
e1dc566f	190	"spin-table"
b00c927d RV	191	# On ARM 32-bit systems this property is optional and
b00c927d RV	192	can be one of:
913627b3	193	"allwinner,sun6i-a31"
7917d141	194	"allwinner,sun8i-a23"
5420b4b1	195	"arm,realview-smp"
7418111f	196	"brcm,bcm-nsp-smp"
0a540d4b	197	"brcm,brahma-b15"
1ee89e22 GC	198	"marvell,armada-375-smp"
1ee89e22 GC	199	"marvell,armada-380-smp"
007fa946	200	"marvell,armada-390-smp"
2c9b2240	201	"marvell,armada-xp-smp"
4562c910 YC	202	"mediatek,mt6589-smp"
4562c910 YC	203	"mediatek,mt81xx-tz-smp"
e1dc566f OJ	204	"qcom,gcc-msm8660"
	205	"qcom,kpss-acc-v1"
	206	"qcom,kpss-acc-v2"
9def7ccf	207	"rockchip,rk3036-smp"
26ab69cb	208	"rockchip,rk3066-smp"
bf64dd26	209	"ste,dbx500-smp"
594f88d1 LP	210
	211	- cpu-release-addr
	212	Usage: required for systems that have an "enable-method"
	213	property value of "spin-table".
	214	Value type: <prop-encoded-array>
	215	Definition:
	216	# On ARM v8 64-bit systems must be a two cell
	217	property identifying a 64-bit zero-initialised
	218	memory location.
	219
b00c927d RV	220	- qcom,saw
	221	Usage: required for systems that have an "enable-method"
	222	property value of "qcom,kpss-acc-v1" or
	223	"qcom,kpss-acc-v2"
	224	Value type: <phandle>
	225	Definition: Specifies the SAW[1] node associated with this CPU.
	226
	227	- qcom,acc
	228	Usage: required for systems that have an "enable-method"
	229	property value of "qcom,kpss-acc-v1" or
	230	"qcom,kpss-acc-v2"
	231	Value type: <phandle>
	232	Definition: Specifies the ACC[2] node associated with this CPU.
	233
3f8161b2 LP	234	- cpu-idle-states
	235	Usage: Optional
	236	Value type: <prop-encoded-array>
	237	Definition:
	238	# List of phandles to idle state nodes supported
	239	by this cpu [3].
b00c927d	240
6de2d21a HS	241	- rockchip,pmu
	242	Usage: optional for systems that have an "enable-method"
	243	property value of "rockchip,rk3066-smp"
	244	While optional, it is the preferred way to get access to
	245	the cpu-core power-domains.
	246	Value type: <phandle>
	247	Definition: Specifies the syscon node controlling the cpu core
	248	power domains.
	249
3be3f8f3 PA	250	- dynamic-power-coefficient
	251	Usage: optional
	252	Value type: <prop-encoded-array>
	253	Definition: A u32 value that represents the running time dynamic
46f1296f	254	power coefficient in units of mW/MHz/uV^2. The
3be3f8f3 PA	255	coefficient can either be calculated from power
	256	measurements or derived by analysis.
	257
	258	The dynamic power consumption of the CPU is
	259	proportional to the square of the Voltage (V) and
	260	the clock frequency (f). The coefficient is used to
	261	calculate the dynamic power as below -
	262
	263	Pdyn = dynamic-power-coefficient * V^2 * f
	264
	265	where voltage is in uV, frequency is in MHz.
	266
594f88d1	267	Example 1 (dual-cluster big.LITTLE system 32-bit):
a0ae0240 LP	268
	269	cpus {
	270	#size-cells = <0>;
	271	#address-cells = <1>;
	272
594f88d1	273	cpu@0 {
a0ae0240 LP	274	device_type = "cpu";
	275	compatible = "arm,cortex-a15";
	276	reg = <0x0>;
	277	};
	278
594f88d1	279	cpu@1 {
a0ae0240 LP	280	device_type = "cpu";
	281	compatible = "arm,cortex-a15";
	282	reg = <0x1>;
	283	};
	284
594f88d1	285	cpu@100 {
a0ae0240 LP	286	device_type = "cpu";
	287	compatible = "arm,cortex-a7";
	288	reg = <0x100>;
	289	};
	290
594f88d1	291	cpu@101 {
a0ae0240 LP	292	device_type = "cpu";
	293	compatible = "arm,cortex-a7";
	294	reg = <0x101>;
	295	};
	296	};
594f88d1 LP	297
	298	Example 2 (Cortex-A8 uniprocessor 32-bit system):
	299
	300	cpus {
	301	#size-cells = <0>;
	302	#address-cells = <1>;
	303
	304	cpu@0 {
	305	device_type = "cpu";
	306	compatible = "arm,cortex-a8";
	307	reg = <0x0>;
	308	};
	309	};
	310
	311	Example 3 (ARM 926EJ-S uniprocessor 32-bit system):
	312
	313	cpus {
	314	#size-cells = <0>;
	315	#address-cells = <1>;
	316
	317	cpu@0 {
	318	device_type = "cpu";
	319	compatible = "arm,arm926ej-s";
	320	reg = <0x0>;
	321	};
	322	};
	323
	324	Example 4 (ARM Cortex-A57 64-bit system):
	325
	326	cpus {
	327	#size-cells = <0>;
	328	#address-cells = <2>;
	329
	330	cpu@0 {
	331	device_type = "cpu";
	332	compatible = "arm,cortex-a57";
	333	reg = <0x0 0x0>;
	334	enable-method = "spin-table";
	335	cpu-release-addr = <0 0x20000000>;
	336	};
	337
	338	cpu@1 {
	339	device_type = "cpu";
	340	compatible = "arm,cortex-a57";
	341	reg = <0x0 0x1>;
	342	enable-method = "spin-table";
	343	cpu-release-addr = <0 0x20000000>;
	344	};
	345
	346	cpu@100 {
	347	device_type = "cpu";
	348	compatible = "arm,cortex-a57";
	349	reg = <0x0 0x100>;
	350	enable-method = "spin-table";
	351	cpu-release-addr = <0 0x20000000>;
	352	};
	353
	354	cpu@101 {
	355	device_type = "cpu";
	356	compatible = "arm,cortex-a57";
	357	reg = <0x0 0x101>;
	358	enable-method = "spin-table";
	359	cpu-release-addr = <0 0x20000000>;
	360	};
361
362	cpu@10000 {
363	device_type = "cpu";
364	compatible = "arm,cortex-a57";
365	reg = <0x0 0x10000>;
366	enable-method = "spin-table";
367	cpu-release-addr = <0 0x20000000>;
368	};
369
370	cpu@10001 {
371	device_type = "cpu";
372	compatible = "arm,cortex-a57";
373	reg = <0x0 0x10001>;
374	enable-method = "spin-table";
375	cpu-release-addr = <0 0x20000000>;
376	};
377
378	cpu@10100 {
379	device_type = "cpu";
380	compatible = "arm,cortex-a57";
381	reg = <0x0 0x10100>;
382	enable-method = "spin-table";
383	cpu-release-addr = <0 0x20000000>;
384	};
385
386	cpu@10101 {
387	device_type = "cpu";
388	compatible = "arm,cortex-a57";
389	reg = <0x0 0x10101>;
390	enable-method = "spin-table";
391	cpu-release-addr = <0 0x20000000>;
392	};
393
394	cpu@100000000 {
395	device_type = "cpu";
396	compatible = "arm,cortex-a57";
397	reg = <0x1 0x0>;
398	enable-method = "spin-table";
399	cpu-release-addr = <0 0x20000000>;
400	};
401
402	cpu@100000001 {
403	device_type = "cpu";
404	compatible = "arm,cortex-a57";
405	reg = <0x1 0x1>;
406	enable-method = "spin-table";
407	cpu-release-addr = <0 0x20000000>;
408	};
409
410	cpu@100000100 {
411	device_type = "cpu";
412	compatible = "arm,cortex-a57";
413	reg = <0x1 0x100>;
414	enable-method = "spin-table";
415	cpu-release-addr = <0 0x20000000>;
416	};
417
418	cpu@100000101 {
419	device_type = "cpu";
420	compatible = "arm,cortex-a57";
421	reg = <0x1 0x101>;
422	enable-method = "spin-table";
423	cpu-release-addr = <0 0x20000000>;
424	};
425
426	cpu@100010000 {
427	device_type = "cpu";
428	compatible = "arm,cortex-a57";
429	reg = <0x1 0x10000>;
430	enable-method = "spin-table";
431	cpu-release-addr = <0 0x20000000>;
432	};
433
434	cpu@100010001 {
435	device_type = "cpu";
436	compatible = "arm,cortex-a57";
437	reg = <0x1 0x10001>;
438	enable-method = "spin-table";
439	cpu-release-addr = <0 0x20000000>;
440	};
441
442	cpu@100010100 {
443	device_type = "cpu";
444	compatible = "arm,cortex-a57";
445	reg = <0x1 0x10100>;
446	enable-method = "spin-table";
447	cpu-release-addr = <0 0x20000000>;
448	};
449
450	cpu@100010101 {
451	device_type = "cpu";
452	compatible = "arm,cortex-a57";
453	reg = <0x1 0x10101>;
454	enable-method = "spin-table";
455	cpu-release-addr = <0 0x20000000>;
456	};
457	};
b00c927d RV	458
	459	--
	460	[1] arm/msm/qcom,saw2.txt
	461	[2] arm/msm/qcom,kpss-acc.txt
3f8161b2 LP	462	[3] ARM Linux kernel documentation - idle states bindings
3f8161b2 LP	463	Documentation/devicetree/bindings/arm/idle-states.txt