[deliverable/linux.git] / arch / arc / include / asm / arcregs.h

/*
 * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#ifndef _ASM_ARC_ARCREGS_H
#define _ASM_ARC_ARCREGS_H

/* Build Configuration Registers */
#define ARC_REG_DCCMBASE_BCR	0x61	/* DCCM Base Addr */
#define ARC_REG_CRC_BCR		0x62
#define ARC_REG_VECBASE_BCR	0x68
#define ARC_REG_PERIBASE_BCR	0x69
#define ARC_REG_FP_BCR		0x6B	/* ARCompact: Single-Precision FPU */
#define ARC_REG_DPFP_BCR	0x6C	/* ARCompact: Dbl Precision FPU */
#define ARC_REG_FP_V2_BCR	0xc8	/* ARCv2 FPU */
#define ARC_REG_SLC_BCR		0xce
#define ARC_REG_DCCM_BCR	0x74	/* DCCM Present + SZ */
#define ARC_REG_TIMERS_BCR	0x75
#define ARC_REG_AP_BCR		0x76
#define ARC_REG_ICCM_BCR	0x78
#define ARC_REG_XY_MEM_BCR	0x79
#define ARC_REG_MAC_BCR		0x7a
#define ARC_REG_MUL_BCR		0x7b
#define ARC_REG_SWAP_BCR	0x7c
#define ARC_REG_NORM_BCR	0x7d
#define ARC_REG_MIXMAX_BCR	0x7e
#define ARC_REG_BARREL_BCR	0x7f
#define ARC_REG_D_UNCACH_BCR	0x6A
#define ARC_REG_BPU_BCR		0xc0
#define ARC_REG_ISA_CFG_BCR	0xc1
#define ARC_REG_RTT_BCR		0xF2
#define ARC_REG_IRQ_BCR		0xF3
#define ARC_REG_SMART_BCR	0xFF
#define ARC_REG_CLUSTER_BCR	0xcf

/* status32 Bits Positions */
#define STATUS_AE_BIT		5	/* Exception active */
#define STATUS_DE_BIT		6	/* PC is in delay slot */
#define STATUS_U_BIT		7	/* User/Kernel mode */
#define STATUS_L_BIT		12	/* Loop inhibit */

/* These masks correspond to the status word(STATUS_32) bits */
#define STATUS_AE_MASK		(1<<STATUS_AE_BIT)
#define STATUS_DE_MASK		(1<<STATUS_DE_BIT)
#define STATUS_U_MASK		(1<<STATUS_U_BIT)
#define STATUS_L_MASK		(1<<STATUS_L_BIT)

/*
 * ECR: Exception Cause Reg bits-n-pieces
 * [23:16] = Exception Vector
 * [15: 8] = Exception Cause Code
 * [ 7: 0] = Exception Parameters (for certain types only)
 */
#ifdef CONFIG_ISA_ARCOMPACT
#define ECR_V_MEM_ERR			0x01
#define ECR_V_INSN_ERR			0x02
#define ECR_V_MACH_CHK			0x20
#define ECR_V_ITLB_MISS			0x21
#define ECR_V_DTLB_MISS			0x22
#define ECR_V_PROTV			0x23
#define ECR_V_TRAP			0x25
#else
#define ECR_V_MEM_ERR			0x01
#define ECR_V_INSN_ERR			0x02
#define ECR_V_MACH_CHK			0x03
#define ECR_V_ITLB_MISS			0x04
#define ECR_V_DTLB_MISS			0x05
#define ECR_V_PROTV			0x06
#define ECR_V_TRAP			0x09
#endif

/* DTLB Miss and Protection Violation Cause Codes */

#define ECR_C_PROTV_INST_FETCH		0x00
#define ECR_C_PROTV_LOAD		0x01
#define ECR_C_PROTV_STORE		0x02
#define ECR_C_PROTV_XCHG		0x03
#define ECR_C_PROTV_MISALIG_DATA	0x04

#define ECR_C_BIT_PROTV_MISALIG_DATA	10

/* Machine Check Cause Code Values */
#define ECR_C_MCHK_DUP_TLB		0x01

/* DTLB Miss Exception Cause Code Values */
#define ECR_C_BIT_DTLB_LD_MISS		8
#define ECR_C_BIT_DTLB_ST_MISS		9

/* Auxiliary registers */
#define AUX_IDENTITY		4
#define AUX_INTR_VEC_BASE	0x25
#define AUX_NON_VOL		0x5e

/*
 * Floating Pt Registers
 * Status regs are read-only (build-time) so need not be saved/restored
 */
#define ARC_AUX_FP_STAT         0x300
#define ARC_AUX_DPFP_1L         0x301
#define ARC_AUX_DPFP_1H         0x302
#define ARC_AUX_DPFP_2L         0x303
#define ARC_AUX_DPFP_2H         0x304
#define ARC_AUX_DPFP_STAT       0x305

#ifndef __ASSEMBLY__

/*
 ******************************************************************
 *      Inline ASM macros to read/write AUX Regs
 *      Essentially invocation of lr/sr insns from "C"
 */

#if 1

#define read_aux_reg(reg)	__builtin_arc_lr(reg)

/* gcc builtin sr needs reg param to be long immediate */
#define write_aux_reg(reg_immed, val)		\
		__builtin_arc_sr((unsigned int)(val), reg_immed)

#else

#define read_aux_reg(reg)		\
({					\
	unsigned int __ret;		\
	__asm__ __volatile__(		\
	"	lr    %0, [%1]"		\
	: "=r"(__ret)			\
	: "i"(reg));			\
	__ret;				\
})

/*
 * Aux Reg address is specified as long immediate by caller
 * e.g.
 *    write_aux_reg(0x69, some_val);
 * This generates tightest code.
 */
#define write_aux_reg(reg_imm, val)	\
({					\
	__asm__ __volatile__(		\
	"	sr   %0, [%1]	\n"	\
	:				\
	: "ir"(val), "i"(reg_imm));	\
})

/*
 * Aux Reg address is specified in a variable
 *  * e.g.
 *      reg_num = 0x69
 *      write_aux_reg2(reg_num, some_val);
 * This has to generate glue code to load the reg num from
 *  memory to a reg hence not recommended.
 */
#define write_aux_reg2(reg_in_var, val)		\
({						\
	unsigned int tmp;			\
						\
	__asm__ __volatile__(			\
	"	ld   %0, [%2]	\n\t"		\
	"	sr   %1, [%0]	\n\t"		\
	: "=&r"(tmp)				\
	: "r"(val), "memory"(&reg_in_var));	\
})

#endif

#define READ_BCR(reg, into)				\
{							\
	unsigned int tmp;				\
	tmp = read_aux_reg(reg);			\
	if (sizeof(tmp) == sizeof(into)) {		\
		into = *((typeof(into) *)&tmp);		\
	} else {					\
		extern void bogus_undefined(void);	\
		bogus_undefined();			\
	}						\
}

#define WRITE_AUX(reg, into)				\
{							\
	unsigned int tmp;				\
	if (sizeof(tmp) == sizeof(into)) {		\
		tmp = (*(unsigned int *)&(into));	\
		write_aux_reg(reg, tmp);		\
	} else  {					\
		extern void bogus_undefined(void);	\
		bogus_undefined();			\
	}						\
}

/* Helpers */
#define TO_KB(bytes)		((bytes) >> 10)
#define TO_MB(bytes)		(TO_KB(bytes) >> 10)
#define PAGES_TO_KB(n_pages)	((n_pages) << (PAGE_SHIFT - 10))
#define PAGES_TO_MB(n_pages)	(PAGES_TO_KB(n_pages) >> 10)


/*
 ***************************************************************
 * Build Configuration Registers, with encoded hardware config
 */
struct bcr_identity {
#ifdef CONFIG_CPU_BIG_ENDIAN
	unsigned int chip_id:16, cpu_id:8, family:8;
#else
	unsigned int family:8, cpu_id:8, chip_id:16;
#endif
};

struct bcr_isa {
#ifdef CONFIG_CPU_BIG_ENDIAN
	unsigned int div_rem:4, pad2:4, ldd:1, unalign:1, atomic:1, be:1,
		     pad1:11, atomic1:1, ver:8;
#else
	unsigned int ver:8, atomic1:1, pad1:11, be:1, atomic:1, unalign:1,
		     ldd:1, pad2:4, div_rem:4;
#endif
};

struct bcr_mpy {
#ifdef CONFIG_CPU_BIG_ENDIAN
	unsigned int pad:8, x1616:8, dsp:4, cycles:2, type:2, ver:8;
#else
	unsigned int ver:8, type:2, cycles:2, dsp:4, x1616:8, pad:8;
#endif
};

struct bcr_extn_xymem {
#ifdef CONFIG_CPU_BIG_ENDIAN
	unsigned int ram_org:2, num_banks:4, bank_sz:4, ver:8;
#else
	unsigned int ver:8, bank_sz:4, num_banks:4, ram_org:2;
#endif
};

struct bcr_perip {
#ifdef CONFIG_CPU_BIG_ENDIAN
	unsigned int start:8, pad2:8, sz:8, ver:8;
#else
	unsigned int ver:8, sz:8, pad2:8, start:8;
#endif
};

struct bcr_iccm {
#ifdef CONFIG_CPU_BIG_ENDIAN
	unsigned int base:16, pad:5, sz:3, ver:8;
#else
	unsigned int ver:8, sz:3, pad:5, base:16;
#endif
};

/* DCCM Base Address Register: ARC_REG_DCCMBASE_BCR */
struct bcr_dccm_base {
#ifdef CONFIG_CPU_BIG_ENDIAN
	unsigned int addr:24, ver:8;
#else
	unsigned int ver:8, addr:24;
#endif
};

/* DCCM RAM Configuration Register: ARC_REG_DCCM_BCR */
struct bcr_dccm {
#ifdef CONFIG_CPU_BIG_ENDIAN
	unsigned int res:21, sz:3, ver:8;
#else
	unsigned int ver:8, sz:3, res:21;
#endif
};

/* ARCompact: Both SP and DP FPU BCRs have same format */
struct bcr_fp_arcompact {
#ifdef CONFIG_CPU_BIG_ENDIAN
	unsigned int fast:1, ver:8;
#else
	unsigned int ver:8, fast:1;
#endif
};

struct bcr_fp_arcv2 {
#ifdef CONFIG_CPU_BIG_ENDIAN
	unsigned int pad2:15, dp:1, pad1:7, sp:1, ver:8;
#else
	unsigned int ver:8, sp:1, pad1:7, dp:1, pad2:15;
#endif
};

struct bcr_timer {
#ifdef CONFIG_CPU_BIG_ENDIAN
	unsigned int pad2:15, rtsc:1, pad1:5, rtc:1, t1:1, t0:1, ver:8;
#else
	unsigned int ver:8, t0:1, t1:1, rtc:1, pad1:5, rtsc:1, pad2:15;
#endif
};

struct bcr_bpu_arcompact {
#ifdef CONFIG_CPU_BIG_ENDIAN
	unsigned int pad2:19, fam:1, pad:2, ent:2, ver:8;
#else
	unsigned int ver:8, ent:2, pad:2, fam:1, pad2:19;
#endif
};

struct bcr_bpu_arcv2 {
#ifdef CONFIG_CPU_BIG_ENDIAN
	unsigned int pad:6, fbe:2, tqe:2, ts:4, ft:1, rse:2, pte:3, bce:3, ver:8;
#else
	unsigned int ver:8, bce:3, pte:3, rse:2, ft:1, ts:4, tqe:2, fbe:2, pad:6;
#endif
};

struct bcr_generic {
#ifdef CONFIG_CPU_BIG_ENDIAN
	unsigned int pad:24, ver:8;
#else
	unsigned int ver:8, pad:24;
#endif
};

/*
 *******************************************************************
 * Generic structures to hold build configuration used at runtime
 */

struct cpuinfo_arc_mmu {
	unsigned int ver:4, pg_sz_k:8, s_pg_sz_m:8, pad:10, sasid:1, pae:1;
	unsigned int sets:12, ways:4, u_dtlb:8, u_itlb:8;
};

struct cpuinfo_arc_cache {
	unsigned int sz_k:14, line_len:8, assoc:4, ver:4, alias:1, vipt:1;
};

struct cpuinfo_arc_bpu {
	unsigned int ver, full, num_cache, num_pred;
};

struct cpuinfo_arc_ccm {
	unsigned int base_addr, sz;
};

struct cpuinfo_arc {
	struct cpuinfo_arc_cache icache, dcache, slc;
	struct cpuinfo_arc_mmu mmu;
	struct cpuinfo_arc_bpu bpu;
	struct bcr_identity core;
	struct bcr_isa isa;
	unsigned int vec_base;
	struct cpuinfo_arc_ccm iccm, dccm;
	struct {
		unsigned int swap:1, norm:1, minmax:1, barrel:1, crc:1, pad1:3,
			     fpu_sp:1, fpu_dp:1, pad2:6,
			     debug:1, ap:1, smart:1, rtt:1, pad3:4,
			     timer0:1, timer1:1, rtc:1, gfrc:1, pad4:4;
	} extn;
	struct bcr_mpy extn_mpy;
	struct bcr_extn_xymem extn_xymem;
};

extern struct cpuinfo_arc cpuinfo_arc700[];

static inline int is_isa_arcv2(void)
{
	return IS_ENABLED(CONFIG_ISA_ARCV2);
}

static inline int is_isa_arcompact(void)
{
	return IS_ENABLED(CONFIG_ISA_ARCOMPACT);
}

#if defined(CONFIG_ISA_ARCOMPACT) && !defined(_CPU_DEFAULT_A7)
#error "Toolchain not configured for ARCompact builds"
#elif defined(CONFIG_ISA_ARCV2) && !defined(_CPU_DEFAULT_HS)
#error "Toolchain not configured for ARCv2 builds"
#endif

#endif /* __ASEMBLY__ */

#endif /* _ASM_ARC_ARCREGS_H */
Commit	Line	Data
ac4c244d VG	1	/*
	2	* Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
	3	*
	4	* This program is free software; you can redistribute it and/or modify
	5	* it under the terms of the GNU General Public License version 2 as
	6	* published by the Free Software Foundation.
	7	*/
	8
	9	#ifndef _ASM_ARC_ARCREGS_H
	10	#define _ASM_ARC_ARCREGS_H
	11
bacdf480	12	/* Build Configuration Registers */
af617428 VG	13	#define ARC_REG_DCCMBASE_BCR 0x61 /* DCCM Base Addr */
af617428 VG	14	#define ARC_REG_CRC_BCR 0x62
bacdf480	15	#define ARC_REG_VECBASE_BCR 0x68
af617428	16	#define ARC_REG_PERIBASE_BCR 0x69
56372082 VG	17	#define ARC_REG_FP_BCR 0x6B /* ARCompact: Single-Precision FPU */
56372082 VG	18	#define ARC_REG_DPFP_BCR 0x6C /* ARCompact: Dbl Precision FPU */
1f6ccfff	19	#define ARC_REG_FP_V2_BCR 0xc8 /* ARCv2 FPU */
d1f317d8	20	#define ARC_REG_SLC_BCR 0xce
af617428 VG	21	#define ARC_REG_DCCM_BCR 0x74 /* DCCM Present + SZ */
af617428 VG	22	#define ARC_REG_TIMERS_BCR 0x75
56372082	23	#define ARC_REG_AP_BCR 0x76
af617428 VG	24	#define ARC_REG_ICCM_BCR 0x78
	25	#define ARC_REG_XY_MEM_BCR 0x79
	26	#define ARC_REG_MAC_BCR 0x7a
	27	#define ARC_REG_MUL_BCR 0x7b
	28	#define ARC_REG_SWAP_BCR 0x7c
	29	#define ARC_REG_NORM_BCR 0x7d
	30	#define ARC_REG_MIXMAX_BCR 0x7e
	31	#define ARC_REG_BARREL_BCR 0x7f
	32	#define ARC_REG_D_UNCACH_BCR 0x6A
56372082 VG	33	#define ARC_REG_BPU_BCR 0xc0
56372082 VG	34	#define ARC_REG_ISA_CFG_BCR 0xc1
a44ec8bd	35	#define ARC_REG_RTT_BCR 0xF2
820970a5	36	#define ARC_REG_IRQ_BCR 0xF3
56372082	37	#define ARC_REG_SMART_BCR 0xFF
f2b0b25a	38	#define ARC_REG_CLUSTER_BCR 0xcf
bacdf480	39
ac4c244d	40	/* status32 Bits Positions */
ac4c244d VG	41	#define STATUS_AE_BIT 5 /* Exception active */
	42	#define STATUS_DE_BIT 6 /* PC is in delay slot */
	43	#define STATUS_U_BIT 7 /* User/Kernel mode */
	44	#define STATUS_L_BIT 12 /* Loop inhibit */
	45
	46	/* These masks correspond to the status word(STATUS_32) bits */
ac4c244d VG	47	#define STATUS_AE_MASK (1<<STATUS_AE_BIT)
	48	#define STATUS_DE_MASK (1<<STATUS_DE_BIT)
	49	#define STATUS_U_MASK (1<<STATUS_U_BIT)
	50	#define STATUS_L_MASK (1<<STATUS_L_BIT)
	51
cc562d2e VG	52	/*
	53	* ECR: Exception Cause Reg bits-n-pieces
	54	* [23:16] = Exception Vector
	55	* [15: 8] = Exception Cause Code
	56	* [ 7: 0] = Exception Parameters (for certain types only)
	57	*/
1f6ccfff	58	#ifdef CONFIG_ISA_ARCOMPACT
dc9e234f	59	#define ECR_V_MEM_ERR 0x01
cc562d2e VG	60	#define ECR_V_INSN_ERR 0x02
	61	#define ECR_V_MACH_CHK 0x20
	62	#define ECR_V_ITLB_MISS 0x21
	63	#define ECR_V_DTLB_MISS 0x22
	64	#define ECR_V_PROTV 0x23
502a0c77	65	#define ECR_V_TRAP 0x25
1f6ccfff VG	66	#else
	67	#define ECR_V_MEM_ERR 0x01
	68	#define ECR_V_INSN_ERR 0x02
	69	#define ECR_V_MACH_CHK 0x03
	70	#define ECR_V_ITLB_MISS 0x04
	71	#define ECR_V_DTLB_MISS 0x05
	72	#define ECR_V_PROTV 0x06
	73	#define ECR_V_TRAP 0x09
	74	#endif
cc562d2e	75
dc9e234f VG	76	/* DTLB Miss and Protection Violation Cause Codes */
dc9e234f VG	77
cc562d2e VG	78	#define ECR_C_PROTV_INST_FETCH 0x00
	79	#define ECR_C_PROTV_LOAD 0x01
	80	#define ECR_C_PROTV_STORE 0x02
	81	#define ECR_C_PROTV_XCHG 0x03
	82	#define ECR_C_PROTV_MISALIG_DATA 0x04
	83
1898a959 VG	84	#define ECR_C_BIT_PROTV_MISALIG_DATA 10
	85
	86	/* Machine Check Cause Code Values */
	87	#define ECR_C_MCHK_DUP_TLB 0x01
	88
cc562d2e VG	89	/* DTLB Miss Exception Cause Code Values */
	90	#define ECR_C_BIT_DTLB_LD_MISS 8
	91	#define ECR_C_BIT_DTLB_ST_MISS 9
	92
ac4c244d VG	93	/* Auxiliary registers */
	94	#define AUX_IDENTITY 4
	95	#define AUX_INTR_VEC_BASE 0x25
e13c42ec	96	#define AUX_NON_VOL 0x5e
f1f3347d	97
bf90e1ea VG	98	/*
	99	* Floating Pt Registers
	100	* Status regs are read-only (build-time) so need not be saved/restored
	101	*/
	102	#define ARC_AUX_FP_STAT 0x300
	103	#define ARC_AUX_DPFP_1L 0x301
	104	#define ARC_AUX_DPFP_1H 0x302
	105	#define ARC_AUX_DPFP_2L 0x303
	106	#define ARC_AUX_DPFP_2H 0x304
	107	#define ARC_AUX_DPFP_STAT 0x305
	108
ac4c244d VG	109	#ifndef __ASSEMBLY__
	110
	111	/*
	112	******************************************************************
	113	* Inline ASM macros to read/write AUX Regs
	114	* Essentially invocation of lr/sr insns from "C"
	115	*/
	116
	117	#if 1
	118
	119	#define read_aux_reg(reg) __builtin_arc_lr(reg)
	120
	121	/* gcc builtin sr needs reg param to be long immediate */
	122	#define write_aux_reg(reg_immed, val) \
5c35ee64	123	__builtin_arc_sr((unsigned int)(val), reg_immed)
ac4c244d VG	124
	125	#else
	126
	127	#define read_aux_reg(reg) \
	128	({ \
	129	unsigned int __ret; \
	130	__asm__ __volatile__( \
	131	" lr %0, [%1]" \
	132	: "=r"(__ret) \
	133	: "i"(reg)); \
	134	__ret; \
	135	})
	136
	137	/*
	138	* Aux Reg address is specified as long immediate by caller
	139	* e.g.
	140	* write_aux_reg(0x69, some_val);
	141	* This generates tightest code.
	142	*/
	143	#define write_aux_reg(reg_imm, val) \
	144	({ \
	145	__asm__ __volatile__( \
	146	" sr %0, [%1] \n" \
	147	: \
	148	: "ir"(val), "i"(reg_imm)); \
	149	})
	150
	151	/*
	152	* Aux Reg address is specified in a variable
	153	* * e.g.
	154	* reg_num = 0x69
	155	* write_aux_reg2(reg_num, some_val);
	156	* This has to generate glue code to load the reg num from
	157	* memory to a reg hence not recommended.
	158	*/
	159	#define write_aux_reg2(reg_in_var, val) \
	160	({ \
	161	unsigned int tmp; \
	162	\
	163	__asm__ __volatile__( \
	164	" ld %0, [%2] \n\t" \
	165	" sr %1, [%0] \n\t" \
	166	: "=&r"(tmp) \
	167	: "r"(val), "memory"(&reg_in_var)); \
	168	})
	169
	170	#endif
	171
95d6976d VG	172	#define READ_BCR(reg, into) \
	173	{ \
	174	unsigned int tmp; \
	175	tmp = read_aux_reg(reg); \
	176	if (sizeof(tmp) == sizeof(into)) { \
	177	into = ((typeof(into) )&tmp); \
	178	} else { \
	179	extern void bogus_undefined(void); \
	180	bogus_undefined(); \
	181	} \
	182	}
	183
1425d5e7	184	#define WRITE_AUX(reg, into) \
95d6976d VG	185	{ \
	186	unsigned int tmp; \
	187	if (sizeof(tmp) == sizeof(into)) { \
1425d5e7	188	tmp = ((unsigned int )&(into)); \
95d6976d VG	189	write_aux_reg(reg, tmp); \
	190	} else { \
	191	extern void bogus_undefined(void); \
	192	bogus_undefined(); \
	193	} \
	194	}
	195
c121c506 VG	196	/* Helpers */
	197	#define TO_KB(bytes) ((bytes) >> 10)
	198	#define TO_MB(bytes) (TO_KB(bytes) >> 10)
	199	#define PAGES_TO_KB(n_pages) ((n_pages) << (PAGE_SHIFT - 10))
	200	#define PAGES_TO_MB(n_pages) (PAGES_TO_KB(n_pages) >> 10)
95d6976d	201
bf90e1ea	202
95d6976d VG	203	/*
	204	***************************************************************
	205	* Build Configuration Registers, with encoded hardware config
	206	*/
af617428 VG	207	struct bcr_identity {
	208	#ifdef CONFIG_CPU_BIG_ENDIAN
	209	unsigned int chip_id:16, cpu_id:8, family:8;
	210	#else
	211	unsigned int family:8, cpu_id:8, chip_id:16;
	212	#endif
	213	};
95d6976d	214
56372082	215	struct bcr_isa {
af617428	216	#ifdef CONFIG_CPU_BIG_ENDIAN
1f6ccfff VG	217	unsigned int div_rem:4, pad2:4, ldd:1, unalign:1, atomic:1, be:1,
1f6ccfff VG	218	pad1:11, atomic1:1, ver:8;
af617428	219	#else
1f6ccfff VG	220	unsigned int ver:8, atomic1:1, pad1:11, be:1, atomic:1, unalign:1,
1f6ccfff VG	221	ldd:1, pad2:4, div_rem:4;
af617428 VG	222	#endif
	223	};
	224
56372082	225	struct bcr_mpy {
af617428	226	#ifdef CONFIG_CPU_BIG_ENDIAN
56372082	227	unsigned int pad:8, x1616:8, dsp:4, cycles:2, type:2, ver:8;
af617428	228	#else
56372082	229	unsigned int ver:8, type:2, cycles:2, dsp:4, x1616:8, pad:8;
af617428 VG	230	#endif
	231	};
	232
	233	struct bcr_extn_xymem {
	234	#ifdef CONFIG_CPU_BIG_ENDIAN
	235	unsigned int ram_org:2, num_banks:4, bank_sz:4, ver:8;
	236	#else
	237	unsigned int ver:8, bank_sz:4, num_banks:4, ram_org:2;
	238	#endif
	239	};
	240
af617428 VG	241	struct bcr_perip {
af617428 VG	242	#ifdef CONFIG_CPU_BIG_ENDIAN
e13c42ec	243	unsigned int start:8, pad2:8, sz:8, ver:8;
af617428	244	#else
e13c42ec	245	unsigned int ver:8, sz:8, pad2:8, start:8;
af617428 VG	246	#endif
af617428 VG	247	};
56372082	248
af617428 VG	249	struct bcr_iccm {
	250	#ifdef CONFIG_CPU_BIG_ENDIAN
	251	unsigned int base:16, pad:5, sz:3, ver:8;
	252	#else
	253	unsigned int ver:8, sz:3, pad:5, base:16;
	254	#endif
	255	};
	256
	257	/* DCCM Base Address Register: ARC_REG_DCCMBASE_BCR */
	258	struct bcr_dccm_base {
	259	#ifdef CONFIG_CPU_BIG_ENDIAN
	260	unsigned int addr:24, ver:8;
	261	#else
	262	unsigned int ver:8, addr:24;
	263	#endif
	264	};
	265
	266	/* DCCM RAM Configuration Register: ARC_REG_DCCM_BCR */
	267	struct bcr_dccm {
	268	#ifdef CONFIG_CPU_BIG_ENDIAN
	269	unsigned int res:21, sz:3, ver:8;
	270	#else
	271	unsigned int ver:8, sz:3, res:21;
	272	#endif
	273	};
	274
56372082 VG	275	/* ARCompact: Both SP and DP FPU BCRs have same format */
56372082 VG	276	struct bcr_fp_arcompact {
af617428 VG	277	#ifdef CONFIG_CPU_BIG_ENDIAN
	278	unsigned int fast:1, ver:8;
	279	#else
	280	unsigned int ver:8, fast:1;
	281	#endif
	282	};
	283
1f6ccfff VG	284	struct bcr_fp_arcv2 {
	285	#ifdef CONFIG_CPU_BIG_ENDIAN
	286	unsigned int pad2:15, dp:1, pad1:7, sp:1, ver:8;
	287	#else
	288	unsigned int ver:8, sp:1, pad1:7, dp:1, pad2:15;
	289	#endif
	290	};
	291
56372082 VG	292	struct bcr_timer {
56372082 VG	293	#ifdef CONFIG_CPU_BIG_ENDIAN
1f6ccfff	294	unsigned int pad2:15, rtsc:1, pad1:5, rtc:1, t1:1, t0:1, ver:8;
56372082	295	#else
1f6ccfff	296	unsigned int ver:8, t0:1, t1:1, rtc:1, pad1:5, rtsc:1, pad2:15;
56372082 VG	297	#endif
	298	};
	299
	300	struct bcr_bpu_arcompact {
	301	#ifdef CONFIG_CPU_BIG_ENDIAN
	302	unsigned int pad2:19, fam:1, pad:2, ent:2, ver:8;
	303	#else
	304	unsigned int ver:8, ent:2, pad:2, fam:1, pad2:19;
	305	#endif
	306	};
	307
1f6ccfff VG	308	struct bcr_bpu_arcv2 {
	309	#ifdef CONFIG_CPU_BIG_ENDIAN
	310	unsigned int pad:6, fbe:2, tqe:2, ts:4, ft:1, rse:2, pte:3, bce:3, ver:8;
	311	#else
	312	unsigned int ver:8, bce:3, pte:3, rse:2, ft:1, ts:4, tqe:2, fbe:2, pad:6;
	313	#endif
	314	};
	315
56372082 VG	316	struct bcr_generic {
	317	#ifdef CONFIG_CPU_BIG_ENDIAN
	318	unsigned int pad:24, ver:8;
	319	#else
	320	unsigned int ver:8, pad:24;
	321	#endif
	322	};
	323
95d6976d VG	324	/*
	325	*******************************************************************
	326	* Generic structures to hold build configuration used at runtime
	327	*/
	328
cc562d2e	329	struct cpuinfo_arc_mmu {
d0890ea5	330	unsigned int ver:4, pg_sz_k:8, s_pg_sz_m:8, pad:10, sasid:1, pae:1;
b598e17f	331	unsigned int sets:12, ways:4, u_dtlb:8, u_itlb:8;
cc562d2e VG	332	};
cc562d2e VG	333
95d6976d	334	struct cpuinfo_arc_cache {
d1f317d8	335	unsigned int sz_k:14, line_len:8, assoc:4, ver:4, alias:1, vipt:1;
95d6976d VG	336	};
95d6976d VG	337
56372082 VG	338	struct cpuinfo_arc_bpu {
	339	unsigned int ver, full, num_cache, num_pred;
	340	};
	341
af617428 VG	342	struct cpuinfo_arc_ccm {
	343	unsigned int base_addr, sz;
	344	};
	345
95d6976d	346	struct cpuinfo_arc {
d1f317d8	347	struct cpuinfo_arc_cache icache, dcache, slc;
cc562d2e	348	struct cpuinfo_arc_mmu mmu;
56372082	349	struct cpuinfo_arc_bpu bpu;
af617428	350	struct bcr_identity core;
56372082	351	struct bcr_isa isa;
af617428	352	unsigned int vec_base;
af617428	353	struct cpuinfo_arc_ccm iccm, dccm;
56372082 VG	354	struct {
	355	unsigned int swap:1, norm:1, minmax:1, barrel:1, crc:1, pad1:3,
	356	fpu_sp:1, fpu_dp:1, pad2:6,
	357	debug:1, ap:1, smart:1, rtt:1, pad3:4,
b89bd1f4	358	timer0:1, timer1:1, rtc:1, gfrc:1, pad4:4;
56372082 VG	359	} extn;
56372082 VG	360	struct bcr_mpy extn_mpy;
af617428	361	struct bcr_extn_xymem extn_xymem;
95d6976d VG	362	};
	363
	364	extern struct cpuinfo_arc cpuinfo_arc700[];
	365
1f6ccfff VG	366	static inline int is_isa_arcv2(void)
	367	{
	368	return IS_ENABLED(CONFIG_ISA_ARCV2);
	369	}
	370
	371	static inline int is_isa_arcompact(void)
	372	{
	373	return IS_ENABLED(CONFIG_ISA_ARCOMPACT);
	374	}
	375
	376	#if defined(CONFIG_ISA_ARCOMPACT) && !defined(_CPU_DEFAULT_A7)
	377	#error "Toolchain not configured for ARCompact builds"
	378	#elif defined(CONFIG_ISA_ARCV2) && !defined(_CPU_DEFAULT_HS)
	379	#error "Toolchain not configured for ARCv2 builds"
	380	#endif
	381
ac4c244d VG	382	#endif /* __ASEMBLY__ */
ac4c244d VG	383
ac4c244d	384	#endif /* _ASM_ARC_ARCREGS_H */