projects / deliverable / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| 80a8b54b SH |
1 | /include/ "skeleton.dtsi" |
| 2 | ||
| eb472c4c SH |
3 | #include <dt-bindings/gpio/gpio.h> |
| 4 | #include <dt-bindings/interrupt-controller/irq.h> | |
| 5 | ||
| 6953af77 SH |
6 | #define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16)) |
| 7 | ||
| 80a8b54b SH |
8 | / { |
| 9 | compatible = "marvell,dove"; | |
| 10 | model = "Marvell Armada 88AP510 SoC"; | |
| 0ad44659 | 11 | interrupt-parent = <&intc>; |
| 80a8b54b | 12 | |
| 9139acd1 SH |
13 | aliases { |
| 14 | gpio0 = &gpio0; | |
| 15 | gpio1 = &gpio1; | |
| 16 | gpio2 = &gpio2; | |
| 17 | }; | |
| 18 | ||
| 2d299834 SH |
19 | cpus { |
| 20 | #address-cells = <1>; | |
| 21 | #size-cells = <0>; | |
| 22 | ||
| 23 | cpu0: cpu@0 { | |
| 24 | compatible = "marvell,pj4a", "marvell,sheeva-v7"; | |
| 25 | device_type = "cpu"; | |
| 26 | next-level-cache = <&l2>; | |
| 27 | reg = <0>; | |
| 28 | }; | |
| 29 | }; | |
| 30 | ||
| 31 | l2: l2-cache { | |
| 32 | compatible = "marvell,tauros2-cache"; | |
| 33 | marvell,tauros2-cache-features = <0>; | |
| 34 | }; | |
| 35 | ||
| 6c72d8ab RK |
36 | gpu-subsystem { |
| 37 | compatible = "marvell,dove-gpu-subsystem"; | |
| 38 | cores = <&gpu>; | |
| 39 | status = "disabled"; | |
| 40 | }; | |
| 41 | ||
| 7ec7e546 SH |
42 | i2c-mux { |
| 43 | compatible = "i2c-mux-pinctrl"; | |
| 44 | #address-cells = <1>; | |
| 45 | #size-cells = <0>; | |
| 46 | ||
| 47 | i2c-parent = <&i2c>; | |
| 48 | ||
| 49 | pinctrl-names = "i2c0", "i2c1", "i2c2"; | |
| 50 | pinctrl-0 = <&pmx_i2cmux_0>; | |
| 51 | pinctrl-1 = <&pmx_i2cmux_1>; | |
| 52 | pinctrl-2 = <&pmx_i2cmux_2>; | |
| 53 | ||
| 54 | i2c0: i2c@0 { | |
| 55 | reg = <0>; | |
| 56 | #address-cells = <1>; | |
| 57 | #size-cells = <0>; | |
| 58 | status = "okay"; | |
| 59 | }; | |
| 60 | ||
| 61 | i2c1: i2c@1 { | |
| 62 | reg = <1>; | |
| 63 | #address-cells = <1>; | |
| 64 | #size-cells = <0>; | |
| 65 | /* Requires pmx_i2c1 on i2c controller node */ | |
| 66 | status = "disabled"; | |
| 67 | }; | |
| 68 | ||
| 69 | i2c2: i2c@2 { | |
| 70 | reg = <2>; | |
| 71 | #address-cells = <1>; | |
| 72 | #size-cells = <0>; | |
| 73 | /* Requires pmx_i2c2 on i2c controller node */ | |
| 74 | status = "disabled"; | |
| 75 | }; | |
| 76 | }; | |
| 77 | ||
| 960ee4e7 SH |
78 | mbus { |
| 79 | compatible = "marvell,dove-mbus", "marvell,mbus", "simple-bus"; | |
| 80 | #address-cells = <2>; | |
| 81 | #size-cells = <1>; | |
| 82 | controller = <&mbusc>; | |
| 83 | pcie-mem-aperture = <0xe0000000 0x10000000>; /* 256M MEM space */ | |
| 84 | pcie-io-aperture = <0xf2000000 0x00200000>; /* 2M I/O space */ | |
| 85 | ||
| 86 | ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x0100000 /* MBUS regs 1M */ | |
| 87 | MBUS_ID(0xf0, 0x02) 0 0xf1800000 0x1000000 /* AXI regs 16M */ | |
| 88 | MBUS_ID(0x01, 0xfd) 0 0xf8000000 0x8000000 /* BootROM 128M */ | |
| 89 | MBUS_ID(0x03, 0x01) 0 0xc8000000 0x0100000 /* CESA SRAM 1M */ | |
| 90 | MBUS_ID(0x0d, 0x00) 0 0xf0000000 0x0100000>; /* PMU SRAM 1M */ | |
| 4c3f6b86 | 91 | |
| 74ecaa40 SH |
92 | pcie: pcie-controller { |
| 93 | compatible = "marvell,dove-pcie"; | |
| 94 | status = "disabled"; | |
| 95 | device_type = "pci"; | |
| 96 | #address-cells = <3>; | |
| 97 | #size-cells = <2>; | |
| 98 | ||
| 99 | msi-parent = <&intc>; | |
| 100 | bus-range = <0x00 0xff>; | |
| 101 | ||
| 102 | ranges = <0x82000000 0x0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x2000 | |
| 103 | 0x82000000 0x0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x2000 | |
| 104 | 0x82000000 0x1 0x0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 Mem */ | |
| 105 | 0x81000000 0x1 0x0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 I/O */ | |
| 106 | 0x82000000 0x2 0x0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 1.0 Mem */ | |
| 107 | 0x81000000 0x2 0x0 MBUS_ID(0x08, 0xe0) 0 1 0>; /* Port 1.0 I/O */ | |
| 108 | ||
| 83ce82ee | 109 | pcie0: pcie-port@0 { |
| 74ecaa40 SH |
110 | device_type = "pci"; |
| 111 | status = "disabled"; | |
| 112 | assigned-addresses = <0x82000800 0 0x40000 0 0x2000>; | |
| 113 | reg = <0x0800 0 0 0 0>; | |
| 114 | clocks = <&gate_clk 4>; | |
| 115 | marvell,pcie-port = <0>; | |
| 116 | ||
| 117 | #address-cells = <3>; | |
| 118 | #size-cells = <2>; | |
| 119 | ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 | |
| 120 | 0x81000000 0 0 0x81000000 0x1 0 1 0>; | |
| 121 | ||
| 122 | #interrupt-cells = <1>; | |
| 123 | interrupt-map-mask = <0 0 0 0>; | |
| 124 | interrupt-map = <0 0 0 0 &intc 16>; | |
| 125 | }; | |
| 126 | ||
| 83ce82ee | 127 | pcie1: pcie-port@1 { |
| 74ecaa40 SH |
128 | device_type = "pci"; |
| 129 | status = "disabled"; | |
| 130 | assigned-addresses = <0x82002800 0 0x80000 0 0x2000>; | |
| 131 | reg = <0x1000 0 0 0 0>; | |
| 132 | clocks = <&gate_clk 5>; | |
| 133 | marvell,pcie-port = <1>; | |
| 134 | ||
| 135 | #address-cells = <3>; | |
| 136 | #size-cells = <2>; | |
| 137 | ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0 | |
| 138 | 0x81000000 0 0 0x81000000 0x2 0 1 0>; | |
| 139 | ||
| 140 | #interrupt-cells = <1>; | |
| 141 | interrupt-map-mask = <0 0 0 0>; | |
| 142 | interrupt-map = <0 0 0 0 &intc 18>; | |
| 143 | }; | |
| 144 | }; | |
| 145 | ||
| 0ad44659 SH |
146 | internal-regs { |
| 147 | compatible = "simple-bus"; | |
| 4c3f6b86 | 148 | #address-cells = <1>; |
| 0ad44659 SH |
149 | #size-cells = <1>; |
| 150 | ranges = <0x00000000 MBUS_ID(0xf0, 0x01) 0 0x0100000 /* MBUS regs 1M */ | |
| 151 | 0x00800000 MBUS_ID(0xf0, 0x02) 0 0x1000000 /* AXI regs 16M */ | |
| 152 | 0xffffe000 MBUS_ID(0x03, 0x01) 0 0x0000800 /* CESA SRAM 2k */ | |
| 153 | 0xfffff000 MBUS_ID(0x0d, 0x00) 0 0x0000800>; /* PMU SRAM 2k */ | |
| 154 | ||
| b31b3211 JC |
155 | spi0: spi-ctrl@10600 { |
| 156 | compatible = "marvell,orion-spi"; | |
| 157 | #address-cells = <1>; | |
| 158 | #size-cells = <0>; | |
| 159 | cell-index = <0>; | |
| 160 | interrupts = <6>; | |
| 161 | reg = <0x10600 0x28>; | |
| 0ad44659 | 162 | clocks = <&core_clk 0>; |
| b31b3211 JC |
163 | pinctrl-0 = <&pmx_spi0>; |
| 164 | pinctrl-names = "default"; | |
| 165 | status = "disabled"; | |
| 0ad44659 SH |
166 | }; |
| 167 | ||
| 7ec7e546 | 168 | i2c: i2c-ctrl@11000 { |
| b31b3211 JC |
169 | compatible = "marvell,mv64xxx-i2c"; |
| 170 | reg = <0x11000 0x20>; | |
| 171 | #address-cells = <1>; | |
| 172 | #size-cells = <0>; | |
| 173 | interrupts = <11>; | |
| 174 | clock-frequency = <400000>; | |
| 175 | timeout-ms = <1000>; | |
| 0ad44659 | 176 | clocks = <&core_clk 0>; |
| 7ec7e546 | 177 | status = "okay"; |
| 0ad44659 SH |
178 | }; |
| 179 | ||
| 180 | uart0: serial@12000 { | |
| 181 | compatible = "ns16550a"; | |
| 182 | reg = <0x12000 0x100>; | |
| 183 | reg-shift = <2>; | |
| 184 | interrupts = <7>; | |
| 185 | clocks = <&core_clk 0>; | |
| 186 | status = "disabled"; | |
| 187 | }; | |
| 188 | ||
| 189 | uart1: serial@12100 { | |
| 190 | compatible = "ns16550a"; | |
| 191 | reg = <0x12100 0x100>; | |
| 192 | reg-shift = <2>; | |
| 193 | interrupts = <8>; | |
| 194 | clocks = <&core_clk 0>; | |
| 195 | pinctrl-0 = <&pmx_uart1>; | |
| 196 | pinctrl-names = "default"; | |
| 197 | status = "disabled"; | |
| 198 | }; | |
| 199 | ||
| 200 | uart2: serial@12200 { | |
| 201 | compatible = "ns16550a"; | |
| a74cd13b | 202 | reg = <0x12200 0x100>; |
| 0ad44659 SH |
203 | reg-shift = <2>; |
| 204 | interrupts = <9>; | |
| 205 | clocks = <&core_clk 0>; | |
| 206 | status = "disabled"; | |
| 207 | }; | |
| 208 | ||
| 209 | uart3: serial@12300 { | |
| 210 | compatible = "ns16550a"; | |
| a74cd13b | 211 | reg = <0x12300 0x100>; |
| 0ad44659 SH |
212 | reg-shift = <2>; |
| 213 | interrupts = <10>; | |
| 214 | clocks = <&core_clk 0>; | |
| 215 | status = "disabled"; | |
| 216 | }; | |
| 217 | ||
| b31b3211 JC |
218 | spi1: spi-ctrl@14600 { |
| 219 | compatible = "marvell,orion-spi"; | |
| 220 | #address-cells = <1>; | |
| 221 | #size-cells = <0>; | |
| 222 | cell-index = <1>; | |
| 223 | interrupts = <5>; | |
| 224 | reg = <0x14600 0x28>; | |
| 225 | clocks = <&core_clk 0>; | |
| 226 | status = "disabled"; | |
| 227 | }; | |
| 228 | ||
| 229 | mbusc: mbus-ctrl@20000 { | |
| 230 | compatible = "marvell,mbus-controller"; | |
| 231 | reg = <0x20000 0x80>, <0x800100 0x8>; | |
| 232 | }; | |
| 233 | ||
| a16761ac SH |
234 | sysc: system-ctrl@20000 { |
| 235 | compatible = "marvell,orion-system-controller"; | |
| 236 | reg = <0x20000 0x110>; | |
| 237 | }; | |
| 238 | ||
| b31b3211 JC |
239 | bridge_intc: bridge-interrupt-ctrl@20110 { |
| 240 | compatible = "marvell,orion-bridge-intc"; | |
| 0ad44659 | 241 | interrupt-controller; |
| b31b3211 JC |
242 | #interrupt-cells = <1>; |
| 243 | reg = <0x20110 0x8>; | |
| 244 | interrupts = <0>; | |
| 245 | marvell,#interrupts = <5>; | |
| 0ad44659 SH |
246 | }; |
| 247 | ||
| b31b3211 JC |
248 | intc: main-interrupt-ctrl@20200 { |
| 249 | compatible = "marvell,orion-intc"; | |
| 0ad44659 | 250 | interrupt-controller; |
| b31b3211 JC |
251 | #interrupt-cells = <1>; |
| 252 | reg = <0x20200 0x10>, <0x20210 0x10>; | |
| 0ad44659 SH |
253 | }; |
| 254 | ||
| b31b3211 JC |
255 | timer: timer@20300 { |
| 256 | compatible = "marvell,orion-timer"; | |
| 257 | reg = <0x20300 0x20>; | |
| 258 | interrupt-parent = <&bridge_intc>; | |
| 259 | interrupts = <1>, <2>; | |
| 260 | clocks = <&core_clk 0>; | |
| 261 | }; | |
| 262 | ||
| 7a5b293f EG |
263 | watchdog@20300 { |
| 264 | compatible = "marvell,orion-wdt"; | |
| 265 | reg = <0x20300 0x28>, <0x20108 0x4>; | |
| 266 | interrupt-parent = <&bridge_intc>; | |
| 267 | interrupts = <3>; | |
| 268 | clocks = <&core_clk 0>; | |
| 269 | }; | |
| 270 | ||
| b31b3211 | 271 | crypto: crypto-engine@30000 { |
| 9b24a35c | 272 | compatible = "marvell,dove-crypto"; |
| eb69e001 BB |
273 | reg = <0x30000 0x10000>; |
| 274 | reg-names = "regs"; | |
| b31b3211 JC |
275 | interrupts = <31>; |
| 276 | clocks = <&gate_clk 15>; | |
| eb69e001 BB |
277 | marvell,crypto-srams = <&crypto_sram>; |
| 278 | marvell,crypto-sram-size = <0x800>; | |
| b31b3211 JC |
279 | status = "okay"; |
| 280 | }; | |
| 281 | ||
| 282 | ehci0: usb-host@50000 { | |
| 283 | compatible = "marvell,orion-ehci"; | |
| 284 | reg = <0x50000 0x1000>; | |
| 285 | interrupts = <24>; | |
| 286 | clocks = <&gate_clk 0>; | |
| 287 | status = "okay"; | |
| 288 | }; | |
| 289 | ||
| 290 | ehci1: usb-host@51000 { | |
| 291 | compatible = "marvell,orion-ehci"; | |
| 292 | reg = <0x51000 0x1000>; | |
| 293 | interrupts = <25>; | |
| 294 | clocks = <&gate_clk 1>; | |
| 295 | status = "okay"; | |
| 296 | }; | |
| 297 | ||
| 298 | xor0: dma-engine@60800 { | |
| 299 | compatible = "marvell,orion-xor"; | |
| 300 | reg = <0x60800 0x100 | |
| 301 | 0x60a00 0x100>; | |
| 302 | clocks = <&gate_clk 23>; | |
| 303 | status = "okay"; | |
| 304 | ||
| 305 | channel0 { | |
| 306 | interrupts = <39>; | |
| 307 | dmacap,memcpy; | |
| 308 | dmacap,xor; | |
| 309 | }; | |
| 310 | ||
| 311 | channel1 { | |
| 312 | interrupts = <40>; | |
| 313 | dmacap,memcpy; | |
| 314 | dmacap,xor; | |
| 315 | }; | |
| 316 | }; | |
| 317 | ||
| 318 | xor1: dma-engine@60900 { | |
| 319 | compatible = "marvell,orion-xor"; | |
| 320 | reg = <0x60900 0x100 | |
| 321 | 0x60b00 0x100>; | |
| 322 | clocks = <&gate_clk 24>; | |
| 323 | status = "okay"; | |
| 324 | ||
| 325 | channel0 { | |
| 326 | interrupts = <42>; | |
| 327 | dmacap,memcpy; | |
| 328 | dmacap,xor; | |
| 329 | }; | |
| 330 | ||
| 331 | channel1 { | |
| 332 | interrupts = <43>; | |
| 333 | dmacap,memcpy; | |
| 334 | dmacap,xor; | |
| 335 | }; | |
| 336 | }; | |
| 337 | ||
| 338 | sdio1: sdio-host@90000 { | |
| 339 | compatible = "marvell,dove-sdhci"; | |
| 340 | reg = <0x90000 0x100>; | |
| 341 | interrupts = <36>, <38>; | |
| 342 | clocks = <&gate_clk 9>; | |
| 343 | pinctrl-0 = <&pmx_sdio1>; | |
| 344 | pinctrl-names = "default"; | |
| 345 | status = "disabled"; | |
| 346 | }; | |
| 347 | ||
| 348 | eth: ethernet-ctrl@72000 { | |
| 349 | compatible = "marvell,orion-eth"; | |
| 350 | #address-cells = <1>; | |
| 351 | #size-cells = <0>; | |
| 352 | reg = <0x72000 0x4000>; | |
| 353 | clocks = <&gate_clk 2>; | |
| 354 | marvell,tx-checksum-limit = <1600>; | |
| 355 | status = "disabled"; | |
| 356 | ||
| 357 | ethernet-port@0 { | |
| b31b3211 JC |
358 | compatible = "marvell,orion-eth-port"; |
| 359 | reg = <0>; | |
| 360 | interrupts = <29>; | |
| 361 | /* overwrite MAC address in bootloader */ | |
| 362 | local-mac-address = [00 00 00 00 00 00]; | |
| 363 | phy-handle = <ðphy>; | |
| 364 | }; | |
| 365 | }; | |
| 366 | ||
| 367 | mdio: mdio-bus@72004 { | |
| 368 | compatible = "marvell,orion-mdio"; | |
| 369 | #address-cells = <1>; | |
| 370 | #size-cells = <0>; | |
| 371 | reg = <0x72004 0x84>; | |
| 372 | interrupts = <30>; | |
| 373 | clocks = <&gate_clk 2>; | |
| 374 | status = "disabled"; | |
| 375 | ||
| 376 | ethphy: ethernet-phy { | |
| b31b3211 JC |
377 | /* set phy address in board file */ |
| 378 | }; | |
| 379 | }; | |
| 380 | ||
| 381 | sdio0: sdio-host@92000 { | |
| 382 | compatible = "marvell,dove-sdhci"; | |
| 383 | reg = <0x92000 0x100>; | |
| 384 | interrupts = <35>, <37>; | |
| 385 | clocks = <&gate_clk 8>; | |
| 386 | pinctrl-0 = <&pmx_sdio0>; | |
| 387 | pinctrl-names = "default"; | |
| 388 | status = "disabled"; | |
| 389 | }; | |
| 390 | ||
| 391 | sata0: sata-host@a0000 { | |
| 392 | compatible = "marvell,orion-sata"; | |
| 393 | reg = <0xa0000 0x2400>; | |
| 394 | interrupts = <62>; | |
| 395 | clocks = <&gate_clk 3>; | |
| 0ad82cd8 AL |
396 | phys = <&sata_phy0>; |
| 397 | phy-names = "port0"; | |
| b31b3211 JC |
398 | nr-ports = <1>; |
| 399 | status = "disabled"; | |
| 400 | }; | |
| 401 | ||
| 0ad82cd8 AL |
402 | sata_phy0: sata-phy@a2000 { |
| 403 | compatible = "marvell,mvebu-sata-phy"; | |
| 404 | reg = <0xa2000 0x0334>; | |
| 405 | clocks = <&gate_clk 3>; | |
| 406 | clock-names = "sata"; | |
| 407 | #phy-cells = <0>; | |
| 408 | status = "ok"; | |
| 409 | }; | |
| 410 | ||
| b31b3211 JC |
411 | audio0: audio-controller@b0000 { |
| 412 | compatible = "marvell,dove-audio"; | |
| 413 | reg = <0xb0000 0x2210>; | |
| 414 | interrupts = <19>, <20>; | |
| 415 | clocks = <&gate_clk 12>; | |
| 416 | clock-names = "internal"; | |
| 417 | status = "disabled"; | |
| 418 | }; | |
| 419 | ||
| 420 | audio1: audio-controller@b4000 { | |
| 421 | compatible = "marvell,dove-audio"; | |
| 422 | reg = <0xb4000 0x2210>; | |
| 423 | interrupts = <21>, <22>; | |
| 424 | clocks = <&gate_clk 13>; | |
| 425 | clock-names = "internal"; | |
| 426 | status = "disabled"; | |
| 427 | }; | |
| 428 | ||
| 8e7c6a32 RK |
429 | pmu: power-management@d0000 { |
| 430 | compatible = "marvell,dove-pmu", "simple-bus"; | |
| 431 | reg = <0xd0000 0x8000>, <0xd8000 0x8000>; | |
| 432 | ranges = <0x00000000 0x000d0000 0x8000 | |
| 433 | 0x00008000 0x000d8000 0x8000>; | |
| 434 | interrupts = <33>; | |
| b31b3211 | 435 | interrupt-controller; |
| 8e7c6a32 RK |
436 | #address-cells = <1>; |
| 437 | #size-cells = <1>; | |
| 438 | #interrupt-cells = <1>; | |
| 439 | #reset-cells = <1>; | |
| 440 | ||
| 441 | domains { | |
| 7c2293f5 RK |
442 | vpu_domain: vpu-domain { |
| 443 | #power-domain-cells = <0>; | |
| 444 | marvell,pmu_pwr_mask = <0x00000008>; | |
| 445 | marvell,pmu_iso_mask = <0x00000001>; | |
| 446 | resets = <&pmu 16>; | |
| 447 | }; | |
| cba3bbcb RK |
448 | |
| 449 | gpu_domain: gpu-domain { | |
| 450 | #power-domain-cells = <0>; | |
| 451 | marvell,pmu_pwr_mask = <0x00000004>; | |
| 452 | marvell,pmu_iso_mask = <0x00000002>; | |
| 453 | resets = <&pmu 18>; | |
| 454 | }; | |
| 8e7c6a32 RK |
455 | }; |
| 456 | ||
| 457 | thermal: thermal-diode@001c { | |
| 458 | compatible = "marvell,dove-thermal"; | |
| 459 | reg = <0x001c 0x0c>, <0x005c 0x08>; | |
| 460 | }; | |
| 461 | ||
| 462 | gate_clk: clock-gating-ctrl@0038 { | |
| 463 | compatible = "marvell,dove-gating-clock"; | |
| 464 | reg = <0x0038 0x4>; | |
| 465 | clocks = <&core_clk 0>; | |
| 466 | #clock-cells = <1>; | |
| 467 | }; | |
| 468 | ||
| 860a8865 RK |
469 | divider_clk: core-clock@0064 { |
| 470 | compatible = "marvell,dove-divider-clock"; | |
| 471 | reg = <0x0064 0x8>; | |
| 472 | #clock-cells = <1>; | |
| 473 | }; | |
| 474 | ||
| 8e7c6a32 RK |
475 | pinctrl: pin-ctrl@0200 { |
| 476 | compatible = "marvell,dove-pinctrl"; | |
| 477 | reg = <0x0200 0x14>, | |
| 478 | <0x0440 0x04>; | |
| 479 | clocks = <&gate_clk 22>; | |
| 480 | ||
| 481 | pmx_gpio_0: pmx-gpio-0 { | |
| 482 | marvell,pins = "mpp0"; | |
| 483 | marvell,function = "gpio"; | |
| 484 | }; | |
| 485 | ||
| 486 | pmx_gpio_1: pmx-gpio-1 { | |
| 487 | marvell,pins = "mpp1"; | |
| 488 | marvell,function = "gpio"; | |
| 489 | }; | |
| 490 | ||
| 491 | pmx_gpio_2: pmx-gpio-2 { | |
| 492 | marvell,pins = "mpp2"; | |
| 493 | marvell,function = "gpio"; | |
| 494 | }; | |
| 495 | ||
| 496 | pmx_gpio_3: pmx-gpio-3 { | |
| 497 | marvell,pins = "mpp3"; | |
| 498 | marvell,function = "gpio"; | |
| 499 | }; | |
| 500 | ||
| 501 | pmx_gpio_4: pmx-gpio-4 { | |
| 502 | marvell,pins = "mpp4"; | |
| 503 | marvell,function = "gpio"; | |
| 504 | }; | |
| 505 | ||
| 506 | pmx_gpio_5: pmx-gpio-5 { | |
| 507 | marvell,pins = "mpp5"; | |
| 508 | marvell,function = "gpio"; | |
| 509 | }; | |
| 510 | ||
| 511 | pmx_gpio_6: pmx-gpio-6 { | |
| 512 | marvell,pins = "mpp6"; | |
| 513 | marvell,function = "gpio"; | |
| 514 | }; | |
| 515 | ||
| 516 | pmx_gpio_7: pmx-gpio-7 { | |
| 517 | marvell,pins = "mpp7"; | |
| 518 | marvell,function = "gpio"; | |
| 519 | }; | |
| 520 | ||
| 521 | pmx_gpio_8: pmx-gpio-8 { | |
| 522 | marvell,pins = "mpp8"; | |
| 523 | marvell,function = "gpio"; | |
| 524 | }; | |
| 525 | ||
| 526 | pmx_gpio_9: pmx-gpio-9 { | |
| 527 | marvell,pins = "mpp9"; | |
| 528 | marvell,function = "gpio"; | |
| 529 | }; | |
| 530 | ||
| 531 | pmx_pcie1_clkreq: pmx-pcie1-clkreq { | |
| 532 | marvell,pins = "mpp9"; | |
| 533 | marvell,function = "pex1"; | |
| 534 | }; | |
| 535 | ||
| 536 | pmx_gpio_10: pmx-gpio-10 { | |
| 537 | marvell,pins = "mpp10"; | |
| 538 | marvell,function = "gpio"; | |
| 539 | }; | |
| 540 | ||
| 541 | pmx_gpio_11: pmx-gpio-11 { | |
| 542 | marvell,pins = "mpp11"; | |
| 543 | marvell,function = "gpio"; | |
| 544 | }; | |
| 545 | ||
| 546 | pmx_pcie0_clkreq: pmx-pcie0-clkreq { | |
| 547 | marvell,pins = "mpp11"; | |
| 548 | marvell,function = "pex0"; | |
| 549 | }; | |
| 550 | ||
| 551 | pmx_gpio_12: pmx-gpio-12 { | |
| 552 | marvell,pins = "mpp12"; | |
| 553 | marvell,function = "gpio"; | |
| 554 | }; | |
| 555 | ||
| 556 | pmx_gpio_13: pmx-gpio-13 { | |
| 557 | marvell,pins = "mpp13"; | |
| 558 | marvell,function = "gpio"; | |
| 559 | }; | |
| 560 | ||
| 561 | pmx_audio1_extclk: pmx-audio1-extclk { | |
| 562 | marvell,pins = "mpp13"; | |
| 563 | marvell,function = "audio1"; | |
| 564 | }; | |
| 565 | ||
| 566 | pmx_gpio_14: pmx-gpio-14 { | |
| 567 | marvell,pins = "mpp14"; | |
| 568 | marvell,function = "gpio"; | |
| 569 | }; | |
| 570 | ||
| 571 | pmx_gpio_15: pmx-gpio-15 { | |
| 572 | marvell,pins = "mpp15"; | |
| 573 | marvell,function = "gpio"; | |
| 574 | }; | |
| 575 | ||
| 576 | pmx_gpio_16: pmx-gpio-16 { | |
| 577 | marvell,pins = "mpp16"; | |
| 578 | marvell,function = "gpio"; | |
| 579 | }; | |
| 580 | ||
| 581 | pmx_gpio_17: pmx-gpio-17 { | |
| 582 | marvell,pins = "mpp17"; | |
| 583 | marvell,function = "gpio"; | |
| 584 | }; | |
| 585 | ||
| 586 | pmx_gpio_18: pmx-gpio-18 { | |
| 587 | marvell,pins = "mpp18"; | |
| 588 | marvell,function = "gpio"; | |
| 589 | }; | |
| 590 | ||
| 591 | pmx_gpio_19: pmx-gpio-19 { | |
| 592 | marvell,pins = "mpp19"; | |
| 593 | marvell,function = "gpio"; | |
| 594 | }; | |
| 595 | ||
| 596 | pmx_gpio_20: pmx-gpio-20 { | |
| 597 | marvell,pins = "mpp20"; | |
| 598 | marvell,function = "gpio"; | |
| 599 | }; | |
| 600 | ||
| 601 | pmx_gpio_21: pmx-gpio-21 { | |
| 602 | marvell,pins = "mpp21"; | |
| 603 | marvell,function = "gpio"; | |
| 604 | }; | |
| 605 | ||
| 606 | pmx_camera: pmx-camera { | |
| 607 | marvell,pins = "mpp_camera"; | |
| 608 | marvell,function = "camera"; | |
| 609 | }; | |
| 610 | ||
| 611 | pmx_camera_gpio: pmx-camera-gpio { | |
| 612 | marvell,pins = "mpp_camera"; | |
| 613 | marvell,function = "gpio"; | |
| 614 | }; | |
| 615 | ||
| 616 | pmx_sdio0: pmx-sdio0 { | |
| 617 | marvell,pins = "mpp_sdio0"; | |
| 618 | marvell,function = "sdio0"; | |
| 619 | }; | |
| 620 | ||
| 621 | pmx_sdio0_gpio: pmx-sdio0-gpio { | |
| 622 | marvell,pins = "mpp_sdio0"; | |
| 623 | marvell,function = "gpio"; | |
| 624 | }; | |
| 625 | ||
| 626 | pmx_sdio1: pmx-sdio1 { | |
| 627 | marvell,pins = "mpp_sdio1"; | |
| 628 | marvell,function = "sdio1"; | |
| 629 | }; | |
| 630 | ||
| 631 | pmx_sdio1_gpio: pmx-sdio1-gpio { | |
| 632 | marvell,pins = "mpp_sdio1"; | |
| 633 | marvell,function = "gpio"; | |
| 634 | }; | |
| 635 | ||
| 636 | pmx_audio1_gpio: pmx-audio1-gpio { | |
| 637 | marvell,pins = "mpp_audio1"; | |
| 638 | marvell,function = "gpio"; | |
| 639 | }; | |
| 640 | ||
| 641 | pmx_audio1_i2s1_spdifo: pmx-audio1-i2s1-spdifo { | |
| 642 | marvell,pins = "mpp_audio1"; | |
| 643 | marvell,function = "i2s1/spdifo"; | |
| 644 | }; | |
| 645 | ||
| 646 | pmx_spi0: pmx-spi0 { | |
| 647 | marvell,pins = "mpp_spi0"; | |
| 648 | marvell,function = "spi0"; | |
| 649 | }; | |
| 650 | ||
| 651 | pmx_spi0_gpio: pmx-spi0-gpio { | |
| 652 | marvell,pins = "mpp_spi0"; | |
| 653 | marvell,function = "gpio"; | |
| 654 | }; | |
| 655 | ||
| 656 | pmx_spi1_4_7: pmx-spi1-4-7 { | |
| 657 | marvell,pins = "mpp4", "mpp5", | |
| 658 | "mpp6", "mpp7"; | |
| 659 | marvell,function = "spi1"; | |
| 660 | }; | |
| 661 | ||
| 662 | pmx_spi1_20_23: pmx-spi1-20-23 { | |
| 663 | marvell,pins = "mpp20", "mpp21", | |
| 664 | "mpp22", "mpp23"; | |
| 665 | marvell,function = "spi1"; | |
| 666 | }; | |
| 667 | ||
| 668 | pmx_uart1: pmx-uart1 { | |
| 669 | marvell,pins = "mpp_uart1"; | |
| 670 | marvell,function = "uart1"; | |
| 671 | }; | |
| 672 | ||
| 673 | pmx_uart1_gpio: pmx-uart1-gpio { | |
| 674 | marvell,pins = "mpp_uart1"; | |
| 675 | marvell,function = "gpio"; | |
| 676 | }; | |
| 677 | ||
| 678 | pmx_nand: pmx-nand { | |
| 679 | marvell,pins = "mpp_nand"; | |
| 680 | marvell,function = "nand"; | |
| 681 | }; | |
| 682 | ||
| 683 | pmx_nand_gpo: pmx-nand-gpo { | |
| 684 | marvell,pins = "mpp_nand"; | |
| 685 | marvell,function = "gpo"; | |
| 686 | }; | |
| 687 | ||
| 688 | pmx_i2c1: pmx-i2c1 { | |
| 689 | marvell,pins = "mpp17", "mpp19"; | |
| 690 | marvell,function = "twsi"; | |
| 691 | }; | |
| 692 | ||
| 693 | pmx_i2c2: pmx-i2c2 { | |
| 694 | marvell,pins = "mpp_audio1"; | |
| 695 | marvell,function = "twsi"; | |
| 696 | }; | |
| 697 | ||
| 698 | pmx_ssp_i2c2: pmx-ssp-i2c2 { | |
| 699 | marvell,pins = "mpp_audio1"; | |
| 700 | marvell,function = "ssp/twsi"; | |
| 701 | }; | |
| 702 | ||
| 703 | pmx_i2cmux_0: pmx-i2cmux-0 { | |
| 704 | marvell,pins = "twsi"; | |
| 705 | marvell,function = "twsi-opt1"; | |
| 706 | }; | |
| 707 | ||
| 708 | pmx_i2cmux_1: pmx-i2cmux-1 { | |
| 709 | marvell,pins = "twsi"; | |
| 710 | marvell,function = "twsi-opt2"; | |
| 711 | }; | |
| 712 | ||
| 713 | pmx_i2cmux_2: pmx-i2cmux-2 { | |
| 714 | marvell,pins = "twsi"; | |
| 715 | marvell,function = "twsi-opt3"; | |
| 716 | }; | |
| 717 | }; | |
| 718 | ||
| 719 | core_clk: core-clocks@0214 { | |
| 720 | compatible = "marvell,dove-core-clock"; | |
| 721 | reg = <0x0214 0x4>; | |
| 722 | #clock-cells = <1>; | |
| 723 | }; | |
| 724 | ||
| 725 | gpio0: gpio-ctrl@0400 { | |
| 726 | compatible = "marvell,orion-gpio"; | |
| 727 | #gpio-cells = <2>; | |
| 728 | gpio-controller; | |
| 729 | reg = <0x0400 0x20>; | |
| 730 | ngpios = <32>; | |
| 731 | interrupt-controller; | |
| 732 | #interrupt-cells = <2>; | |
| 733 | interrupt-parent = <&intc>; | |
| 734 | interrupts = <12>, <13>, <14>, <60>; | |
| 735 | }; | |
| 736 | ||
| 737 | gpio1: gpio-ctrl@0420 { | |
| 738 | compatible = "marvell,orion-gpio"; | |
| 739 | #gpio-cells = <2>; | |
| 740 | gpio-controller; | |
| 741 | reg = <0x0420 0x20>; | |
| 742 | ngpios = <32>; | |
| 743 | interrupt-controller; | |
| 744 | #interrupt-cells = <2>; | |
| 745 | interrupt-parent = <&intc>; | |
| 746 | interrupts = <61>; | |
| 747 | }; | |
| 748 | ||
| 749 | rtc: real-time-clock@8500 { | |
| 750 | compatible = "marvell,orion-rtc"; | |
| 751 | reg = <0x8500 0x20>; | |
| 71296a39 | 752 | interrupts = <5>; |
| 8e7c6a32 | 753 | }; |
| 0ad44659 SH |
754 | }; |
| 755 | ||
| 7a98c18f SH |
756 | gconf: global-config@e802c { |
| 757 | compatible = "marvell,dove-global-config", | |
| 758 | "syscon"; | |
| 759 | reg = <0xe802c 0x14>; | |
| 760 | }; | |
| 761 | ||
| b31b3211 JC |
762 | gpio2: gpio-ctrl@e8400 { |
| 763 | compatible = "marvell,orion-gpio"; | |
| 764 | #gpio-cells = <2>; | |
| 765 | gpio-controller; | |
| 766 | reg = <0xe8400 0x0c>; | |
| 767 | ngpios = <8>; | |
| 080972aa | 768 | }; |
| 087b0470 RK |
769 | |
| 770 | lcd1: lcd-controller@810000 { | |
| 771 | compatible = "marvell,dove-lcd"; | |
| 772 | reg = <0x810000 0x1000>; | |
| 773 | interrupts = <46>; | |
| 774 | status = "disabled"; | |
| 775 | }; | |
| 776 | ||
| 777 | lcd0: lcd-controller@820000 { | |
| 778 | compatible = "marvell,dove-lcd"; | |
| 779 | reg = <0x820000 0x1000>; | |
| 780 | interrupts = <47>; | |
| 781 | status = "disabled"; | |
| 782 | }; | |
| eb69e001 BB |
783 | |
| 784 | crypto_sram: sa-sram@ffffe000 { | |
| 785 | compatible = "mmio-sram"; | |
| 786 | reg = <0xffffe000 0x800>; | |
| 787 | clocks = <&gate_clk 15>; | |
| 788 | #address-cells = <1>; | |
| 789 | #size-cells = <1>; | |
| 790 | }; | |
| 6c72d8ab RK |
791 | |
| 792 | gpu: gpu@840000 { | |
| 793 | clocks = <÷r_clk 1>; | |
| 794 | clock-names = "core"; | |
| 795 | compatible = "vivante,gc"; | |
| 796 | interrupts = <48>; | |
| 797 | power-domains = <&gpu_domain>; | |
| 798 | reg = <0x840000 0x4000>; | |
| 799 | status = "disabled"; | |
| 800 | }; | |
| 4c3f6b86 | 801 | }; |
| 80a8b54b SH |
802 | }; |
| 803 | }; |