Commit | Line | Data |
---|---|---|
f335b8af KG |
1 | /dts-v1/; |
2 | ||
3 | #include "skeleton.dtsi" | |
4 | #include <dt-bindings/clock/qcom,gcc-msm8960.h> | |
223280b1 | 5 | #include <dt-bindings/reset/qcom,gcc-msm8960.h> |
3fe5e3ce | 6 | #include <dt-bindings/clock/qcom,mmcc-msm8960.h> |
f335b8af | 7 | #include <dt-bindings/soc/qcom,gsbi.h> |
150b065d | 8 | #include <dt-bindings/interrupt-controller/irq.h> |
8b8936fc | 9 | #include <dt-bindings/interrupt-controller/arm-gic.h> |
f335b8af KG |
10 | / { |
11 | model = "Qualcomm APQ8064"; | |
12 | compatible = "qcom,apq8064"; | |
13 | interrupt-parent = <&intc>; | |
14 | ||
24a9baf9 BA |
15 | reserved-memory { |
16 | #address-cells = <1>; | |
17 | #size-cells = <1>; | |
18 | ranges; | |
19 | ||
20 | smem_region: smem@80000000 { | |
21 | reg = <0x80000000 0x200000>; | |
22 | no-map; | |
23 | }; | |
24 | }; | |
25 | ||
f335b8af KG |
26 | cpus { |
27 | #address-cells = <1>; | |
28 | #size-cells = <0>; | |
29 | ||
30 | cpu@0 { | |
31 | compatible = "qcom,krait"; | |
32 | enable-method = "qcom,kpss-acc-v1"; | |
33 | device_type = "cpu"; | |
34 | reg = <0>; | |
35 | next-level-cache = <&L2>; | |
36 | qcom,acc = <&acc0>; | |
37 | qcom,saw = <&saw0>; | |
06c49f2b | 38 | cpu-idle-states = <&CPU_SPC>; |
f335b8af KG |
39 | }; |
40 | ||
41 | cpu@1 { | |
42 | compatible = "qcom,krait"; | |
43 | enable-method = "qcom,kpss-acc-v1"; | |
44 | device_type = "cpu"; | |
45 | reg = <1>; | |
46 | next-level-cache = <&L2>; | |
47 | qcom,acc = <&acc1>; | |
48 | qcom,saw = <&saw1>; | |
06c49f2b | 49 | cpu-idle-states = <&CPU_SPC>; |
f335b8af KG |
50 | }; |
51 | ||
52 | cpu@2 { | |
53 | compatible = "qcom,krait"; | |
54 | enable-method = "qcom,kpss-acc-v1"; | |
55 | device_type = "cpu"; | |
56 | reg = <2>; | |
57 | next-level-cache = <&L2>; | |
58 | qcom,acc = <&acc2>; | |
59 | qcom,saw = <&saw2>; | |
06c49f2b | 60 | cpu-idle-states = <&CPU_SPC>; |
f335b8af KG |
61 | }; |
62 | ||
63 | cpu@3 { | |
64 | compatible = "qcom,krait"; | |
65 | enable-method = "qcom,kpss-acc-v1"; | |
66 | device_type = "cpu"; | |
67 | reg = <3>; | |
68 | next-level-cache = <&L2>; | |
69 | qcom,acc = <&acc3>; | |
70 | qcom,saw = <&saw3>; | |
06c49f2b | 71 | cpu-idle-states = <&CPU_SPC>; |
f335b8af KG |
72 | }; |
73 | ||
74 | L2: l2-cache { | |
75 | compatible = "cache"; | |
76 | cache-level = <2>; | |
77 | }; | |
06c49f2b LI |
78 | |
79 | idle-states { | |
80 | CPU_SPC: spc { | |
81 | compatible = "qcom,idle-state-spc", | |
82 | "arm,idle-state"; | |
83 | entry-latency-us = <400>; | |
84 | exit-latency-us = <900>; | |
85 | min-residency-us = <3000>; | |
86 | }; | |
87 | }; | |
f335b8af KG |
88 | }; |
89 | ||
90 | cpu-pmu { | |
91 | compatible = "qcom,krait-pmu"; | |
92 | interrupts = <1 10 0x304>; | |
93 | }; | |
94 | ||
aa269127 GD |
95 | clocks { |
96 | cxo_board { | |
97 | compatible = "fixed-clock"; | |
98 | #clock-cells = <0>; | |
99 | clock-frequency = <19200000>; | |
100 | }; | |
101 | ||
102 | pxo_board { | |
103 | compatible = "fixed-clock"; | |
104 | #clock-cells = <0>; | |
105 | clock-frequency = <27000000>; | |
106 | }; | |
107 | ||
108 | sleep_clk { | |
109 | compatible = "fixed-clock"; | |
110 | #clock-cells = <0>; | |
111 | clock-frequency = <32768>; | |
112 | }; | |
113 | }; | |
114 | ||
24a9baf9 BA |
115 | sfpb_mutex: hwmutex { |
116 | compatible = "qcom,sfpb-mutex"; | |
117 | syscon = <&sfpb_wrapper_mutex 0x604 0x4>; | |
118 | #hwlock-cells = <1>; | |
119 | }; | |
120 | ||
121 | smem { | |
122 | compatible = "qcom,smem"; | |
123 | memory-region = <&smem_region>; | |
124 | ||
125 | hwlocks = <&sfpb_mutex 3>; | |
126 | }; | |
127 | ||
2afc5287 BA |
128 | smd { |
129 | compatible = "qcom,smd"; | |
130 | ||
131 | modem@0 { | |
132 | interrupts = <0 37 IRQ_TYPE_EDGE_RISING>; | |
133 | ||
134 | qcom,ipc = <&l2cc 8 3>; | |
135 | qcom,smd-edge = <0>; | |
136 | ||
137 | status = "disabled"; | |
138 | }; | |
139 | ||
140 | q6@1 { | |
141 | interrupts = <0 90 IRQ_TYPE_EDGE_RISING>; | |
142 | ||
143 | qcom,ipc = <&l2cc 8 15>; | |
144 | qcom,smd-edge = <1>; | |
145 | ||
146 | status = "disabled"; | |
147 | }; | |
148 | ||
149 | dsps@3 { | |
150 | interrupts = <0 138 IRQ_TYPE_EDGE_RISING>; | |
151 | ||
152 | qcom,ipc = <&sps_sic_non_secure 0x4080 0>; | |
153 | qcom,smd-edge = <3>; | |
154 | ||
155 | status = "disabled"; | |
156 | }; | |
157 | ||
158 | riva@6 { | |
159 | interrupts = <0 198 IRQ_TYPE_EDGE_RISING>; | |
160 | ||
161 | qcom,ipc = <&l2cc 8 25>; | |
162 | qcom,smd-edge = <6>; | |
163 | ||
164 | status = "disabled"; | |
165 | }; | |
166 | }; | |
167 | ||
b4d4582f BA |
168 | smsm { |
169 | compatible = "qcom,smsm"; | |
170 | ||
171 | #address-cells = <1>; | |
172 | #size-cells = <0>; | |
173 | ||
174 | qcom,ipc-1 = <&l2cc 8 4>; | |
175 | qcom,ipc-2 = <&l2cc 8 14>; | |
176 | qcom,ipc-3 = <&l2cc 8 23>; | |
177 | qcom,ipc-4 = <&sps_sic_non_secure 0x4094 0>; | |
178 | ||
179 | apps_smsm: apps@0 { | |
180 | reg = <0>; | |
30f1e2dd | 181 | #qcom,smem-state-cells = <1>; |
b4d4582f BA |
182 | }; |
183 | ||
184 | modem_smsm: modem@1 { | |
185 | reg = <1>; | |
186 | interrupts = <0 38 IRQ_TYPE_EDGE_RISING>; | |
187 | ||
188 | interrupt-controller; | |
189 | #interrupt-cells = <2>; | |
190 | }; | |
191 | ||
192 | q6_smsm: q6@2 { | |
193 | reg = <2>; | |
194 | interrupts = <0 89 IRQ_TYPE_EDGE_RISING>; | |
195 | ||
196 | interrupt-controller; | |
197 | #interrupt-cells = <2>; | |
198 | }; | |
199 | ||
200 | wcnss_smsm: wcnss@3 { | |
201 | reg = <3>; | |
202 | interrupts = <0 204 IRQ_TYPE_EDGE_RISING>; | |
203 | ||
204 | interrupt-controller; | |
205 | #interrupt-cells = <2>; | |
206 | }; | |
207 | ||
208 | dsps_smsm: dsps@4 { | |
209 | reg = <4>; | |
210 | interrupts = <0 137 IRQ_TYPE_EDGE_RISING>; | |
211 | ||
212 | interrupt-controller; | |
213 | #interrupt-cells = <2>; | |
214 | }; | |
215 | }; | |
216 | ||
9e5d41d4 AG |
217 | firmware { |
218 | scm { | |
219 | compatible = "qcom,scm-apq8064"; | |
220 | }; | |
221 | }; | |
222 | ||
f335b8af KG |
223 | soc: soc { |
224 | #address-cells = <1>; | |
225 | #size-cells = <1>; | |
226 | ranges; | |
227 | compatible = "simple-bus"; | |
228 | ||
8b8936fc PG |
229 | tlmm_pinmux: pinctrl@800000 { |
230 | compatible = "qcom,apq8064-pinctrl"; | |
231 | reg = <0x800000 0x4000>; | |
232 | ||
233 | gpio-controller; | |
234 | #gpio-cells = <2>; | |
235 | interrupt-controller; | |
236 | #interrupt-cells = <2>; | |
237 | interrupts = <0 16 IRQ_TYPE_LEVEL_HIGH>; | |
cd6dd11a PG |
238 | |
239 | pinctrl-names = "default"; | |
240 | pinctrl-0 = <&ps_hold>; | |
8b8936fc PG |
241 | }; |
242 | ||
24a9baf9 BA |
243 | sfpb_wrapper_mutex: syscon@1200000 { |
244 | compatible = "syscon"; | |
245 | reg = <0x01200000 0x8000>; | |
246 | }; | |
247 | ||
f335b8af KG |
248 | intc: interrupt-controller@2000000 { |
249 | compatible = "qcom,msm-qgic2"; | |
250 | interrupt-controller; | |
251 | #interrupt-cells = <3>; | |
252 | reg = <0x02000000 0x1000>, | |
253 | <0x02002000 0x1000>; | |
254 | }; | |
255 | ||
256 | timer@200a000 { | |
6e062696 MM |
257 | compatible = "qcom,kpss-timer", |
258 | "qcom,kpss-wdt-apq8064", "qcom,msm-timer"; | |
f335b8af KG |
259 | interrupts = <1 1 0x301>, |
260 | <1 2 0x301>, | |
261 | <1 3 0x301>; | |
262 | reg = <0x0200a000 0x100>; | |
263 | clock-frequency = <27000000>, | |
264 | <32768>; | |
265 | cpu-offset = <0x80000>; | |
266 | }; | |
267 | ||
268 | acc0: clock-controller@2088000 { | |
269 | compatible = "qcom,kpss-acc-v1"; | |
270 | reg = <0x02088000 0x1000>, <0x02008000 0x1000>; | |
271 | }; | |
272 | ||
273 | acc1: clock-controller@2098000 { | |
274 | compatible = "qcom,kpss-acc-v1"; | |
275 | reg = <0x02098000 0x1000>, <0x02008000 0x1000>; | |
276 | }; | |
277 | ||
278 | acc2: clock-controller@20a8000 { | |
279 | compatible = "qcom,kpss-acc-v1"; | |
280 | reg = <0x020a8000 0x1000>, <0x02008000 0x1000>; | |
281 | }; | |
282 | ||
283 | acc3: clock-controller@20b8000 { | |
284 | compatible = "qcom,kpss-acc-v1"; | |
285 | reg = <0x020b8000 0x1000>, <0x02008000 0x1000>; | |
286 | }; | |
287 | ||
9fc23ce3 LI |
288 | saw0: power-controller@2089000 { |
289 | compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2"; | |
f335b8af KG |
290 | reg = <0x02089000 0x1000>, <0x02009000 0x1000>; |
291 | regulator; | |
292 | }; | |
293 | ||
9fc23ce3 LI |
294 | saw1: power-controller@2099000 { |
295 | compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2"; | |
f335b8af KG |
296 | reg = <0x02099000 0x1000>, <0x02009000 0x1000>; |
297 | regulator; | |
298 | }; | |
299 | ||
9fc23ce3 LI |
300 | saw2: power-controller@20a9000 { |
301 | compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2"; | |
f335b8af KG |
302 | reg = <0x020a9000 0x1000>, <0x02009000 0x1000>; |
303 | regulator; | |
304 | }; | |
305 | ||
9fc23ce3 LI |
306 | saw3: power-controller@20b9000 { |
307 | compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2"; | |
f335b8af KG |
308 | reg = <0x020b9000 0x1000>, <0x02009000 0x1000>; |
309 | regulator; | |
310 | }; | |
311 | ||
b9e4c5e6 BA |
312 | sps_sic_non_secure: sps-sic-non-secure@12100000 { |
313 | compatible = "syscon"; | |
314 | reg = <0x12100000 0x10000>; | |
315 | }; | |
316 | ||
8c3166f5 | 317 | gsbi1: gsbi@12440000 { |
318 | status = "disabled"; | |
319 | compatible = "qcom,gsbi-v1.0.0"; | |
4105d9d6 | 320 | cell-index = <1>; |
8c3166f5 | 321 | reg = <0x12440000 0x100>; |
322 | clocks = <&gcc GSBI1_H_CLK>; | |
323 | clock-names = "iface"; | |
324 | #address-cells = <1>; | |
325 | #size-cells = <1>; | |
326 | ranges; | |
327 | ||
4105d9d6 AG |
328 | syscon-tcsr = <&tcsr>; |
329 | ||
12861674 SK |
330 | gsbi1_serial: serial@12450000 { |
331 | compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; | |
332 | reg = <0x12450000 0x100>, | |
333 | <0x12400000 0x03>; | |
334 | interrupts = <0 193 0x0>; | |
335 | clocks = <&gcc GSBI1_UART_CLK>, <&gcc GSBI1_H_CLK>; | |
336 | clock-names = "core", "iface"; | |
337 | status = "disabled"; | |
338 | }; | |
339 | ||
e07214db | 340 | gsbi1_i2c: i2c@12460000 { |
8c3166f5 | 341 | compatible = "qcom,i2c-qup-v1.1.1"; |
67b5ad57 SK |
342 | pinctrl-0 = <&i2c1_pins>; |
343 | pinctrl-1 = <&i2c1_pins_sleep>; | |
64b22b25 | 344 | pinctrl-names = "default", "sleep"; |
8c3166f5 | 345 | reg = <0x12460000 0x1000>; |
346 | interrupts = <0 194 IRQ_TYPE_NONE>; | |
347 | clocks = <&gcc GSBI1_QUP_CLK>, <&gcc GSBI1_H_CLK>; | |
348 | clock-names = "core", "iface"; | |
349 | #address-cells = <1>; | |
350 | #size-cells = <0>; | |
351 | }; | |
b2dc04c5 | 352 | |
8c3166f5 | 353 | }; |
354 | ||
355 | gsbi2: gsbi@12480000 { | |
356 | status = "disabled"; | |
357 | compatible = "qcom,gsbi-v1.0.0"; | |
4105d9d6 | 358 | cell-index = <2>; |
8c3166f5 | 359 | reg = <0x12480000 0x100>; |
360 | clocks = <&gcc GSBI2_H_CLK>; | |
361 | clock-names = "iface"; | |
362 | #address-cells = <1>; | |
363 | #size-cells = <1>; | |
364 | ranges; | |
365 | ||
4105d9d6 AG |
366 | syscon-tcsr = <&tcsr>; |
367 | ||
e07214db | 368 | gsbi2_i2c: i2c@124a0000 { |
8c3166f5 | 369 | compatible = "qcom,i2c-qup-v1.1.1"; |
370 | reg = <0x124a0000 0x1000>; | |
67b5ad57 SK |
371 | pinctrl-0 = <&i2c2_pins>; |
372 | pinctrl-1 = <&i2c2_pins_sleep>; | |
7788d439 | 373 | pinctrl-names = "default", "sleep"; |
8c3166f5 | 374 | interrupts = <0 196 IRQ_TYPE_NONE>; |
375 | clocks = <&gcc GSBI2_QUP_CLK>, <&gcc GSBI2_H_CLK>; | |
376 | clock-names = "core", "iface"; | |
377 | #address-cells = <1>; | |
378 | #size-cells = <0>; | |
379 | }; | |
380 | }; | |
381 | ||
3f62b46b SK |
382 | gsbi3: gsbi@16200000 { |
383 | status = "disabled"; | |
384 | compatible = "qcom,gsbi-v1.0.0"; | |
504155ca | 385 | cell-index = <3>; |
3f62b46b SK |
386 | reg = <0x16200000 0x100>; |
387 | clocks = <&gcc GSBI3_H_CLK>; | |
388 | clock-names = "iface"; | |
389 | #address-cells = <1>; | |
390 | #size-cells = <1>; | |
391 | ranges; | |
e07214db | 392 | gsbi3_i2c: i2c@16280000 { |
3f62b46b | 393 | compatible = "qcom,i2c-qup-v1.1.1"; |
67b5ad57 SK |
394 | pinctrl-0 = <&i2c3_pins>; |
395 | pinctrl-1 = <&i2c3_pins_sleep>; | |
64b22b25 | 396 | pinctrl-names = "default", "sleep"; |
3f62b46b SK |
397 | reg = <0x16280000 0x1000>; |
398 | interrupts = <GIC_SPI 151 IRQ_TYPE_NONE>; | |
399 | clocks = <&gcc GSBI3_QUP_CLK>, | |
400 | <&gcc GSBI3_H_CLK>; | |
401 | clock-names = "core", "iface"; | |
5d31f606 JS |
402 | #address-cells = <1>; |
403 | #size-cells = <0>; | |
1099b26e BA |
404 | }; |
405 | }; | |
406 | ||
2a5cbc15 SK |
407 | gsbi4: gsbi@16300000 { |
408 | status = "disabled"; | |
409 | compatible = "qcom,gsbi-v1.0.0"; | |
410 | cell-index = <4>; | |
411 | reg = <0x16300000 0x03>; | |
412 | clocks = <&gcc GSBI4_H_CLK>; | |
413 | clock-names = "iface"; | |
414 | #address-cells = <1>; | |
415 | #size-cells = <1>; | |
416 | ranges; | |
417 | ||
418 | gsbi4_i2c: i2c@16380000 { | |
419 | compatible = "qcom,i2c-qup-v1.1.1"; | |
67b5ad57 SK |
420 | pinctrl-0 = <&i2c4_pins>; |
421 | pinctrl-1 = <&i2c4_pins_sleep>; | |
2a5cbc15 SK |
422 | pinctrl-names = "default", "sleep"; |
423 | reg = <0x16380000 0x1000>; | |
424 | interrupts = <GIC_SPI 153 IRQ_TYPE_NONE>; | |
425 | clocks = <&gcc GSBI4_QUP_CLK>, | |
426 | <&gcc GSBI4_H_CLK>; | |
427 | clock-names = "core", "iface"; | |
428 | }; | |
429 | }; | |
430 | ||
1099b26e BA |
431 | gsbi5: gsbi@1a200000 { |
432 | status = "disabled"; | |
433 | compatible = "qcom,gsbi-v1.0.0"; | |
434 | cell-index = <5>; | |
435 | reg = <0x1a200000 0x03>; | |
436 | clocks = <&gcc GSBI5_H_CLK>; | |
437 | clock-names = "iface"; | |
438 | #address-cells = <1>; | |
439 | #size-cells = <1>; | |
440 | ranges; | |
441 | ||
442 | gsbi5_serial: serial@1a240000 { | |
443 | compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; | |
444 | reg = <0x1a240000 0x100>, | |
445 | <0x1a200000 0x03>; | |
446 | interrupts = <0 154 0x0>; | |
447 | clocks = <&gcc GSBI5_UART_CLK>, <&gcc GSBI5_H_CLK>; | |
448 | clock-names = "core", "iface"; | |
449 | status = "disabled"; | |
3f62b46b | 450 | }; |
b2dc04c5 SK |
451 | |
452 | gsbi5_spi: spi@1a280000 { | |
453 | compatible = "qcom,spi-qup-v1.1.1"; | |
454 | reg = <0x1a280000 0x1000>; | |
455 | interrupts = <0 155 0>; | |
67b5ad57 SK |
456 | pinctrl-0 = <&spi5_default>; |
457 | pinctrl-1 = <&spi5_sleep>; | |
b2dc04c5 SK |
458 | pinctrl-names = "default", "sleep"; |
459 | clocks = <&gcc GSBI5_QUP_CLK>, <&gcc GSBI5_H_CLK>; | |
460 | clock-names = "core", "iface"; | |
461 | status = "disabled"; | |
462 | #address-cells = <1>; | |
463 | #size-cells = <0>; | |
464 | }; | |
3f62b46b SK |
465 | }; |
466 | ||
86e252a4 PG |
467 | gsbi6: gsbi@16500000 { |
468 | status = "disabled"; | |
469 | compatible = "qcom,gsbi-v1.0.0"; | |
470 | cell-index = <6>; | |
471 | reg = <0x16500000 0x03>; | |
472 | clocks = <&gcc GSBI6_H_CLK>; | |
473 | clock-names = "iface"; | |
474 | #address-cells = <1>; | |
475 | #size-cells = <1>; | |
476 | ranges; | |
477 | ||
478 | gsbi6_serial: serial@16540000 { | |
479 | compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; | |
480 | reg = <0x16540000 0x100>, | |
481 | <0x16500000 0x03>; | |
482 | interrupts = <0 156 0x0>; | |
483 | clocks = <&gcc GSBI6_UART_CLK>, <&gcc GSBI6_H_CLK>; | |
484 | clock-names = "core", "iface"; | |
485 | status = "disabled"; | |
486 | }; | |
806334ed SK |
487 | |
488 | gsbi6_i2c: i2c@16580000 { | |
489 | compatible = "qcom,i2c-qup-v1.1.1"; | |
67b5ad57 SK |
490 | pinctrl-0 = <&i2c6_pins>; |
491 | pinctrl-1 = <&i2c6_pins_sleep>; | |
806334ed SK |
492 | pinctrl-names = "default", "sleep"; |
493 | reg = <0x16580000 0x1000>; | |
494 | interrupts = <GIC_SPI 157 IRQ_TYPE_NONE>; | |
495 | clocks = <&gcc GSBI6_QUP_CLK>, | |
496 | <&gcc GSBI6_H_CLK>; | |
497 | clock-names = "core", "iface"; | |
498 | }; | |
86e252a4 PG |
499 | }; |
500 | ||
f335b8af KG |
501 | gsbi7: gsbi@16600000 { |
502 | status = "disabled"; | |
503 | compatible = "qcom,gsbi-v1.0.0"; | |
4105d9d6 | 504 | cell-index = <7>; |
f335b8af KG |
505 | reg = <0x16600000 0x100>; |
506 | clocks = <&gcc GSBI7_H_CLK>; | |
507 | clock-names = "iface"; | |
508 | #address-cells = <1>; | |
509 | #size-cells = <1>; | |
510 | ranges; | |
4105d9d6 AG |
511 | syscon-tcsr = <&tcsr>; |
512 | ||
d5d4654e | 513 | gsbi7_serial: serial@16640000 { |
f335b8af KG |
514 | compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; |
515 | reg = <0x16640000 0x1000>, | |
516 | <0x16600000 0x1000>; | |
517 | interrupts = <0 158 0x0>; | |
518 | clocks = <&gcc GSBI7_UART_CLK>, <&gcc GSBI7_H_CLK>; | |
519 | clock-names = "core", "iface"; | |
520 | status = "disabled"; | |
521 | }; | |
e4b01fda SK |
522 | |
523 | gsbi7_i2c: i2c@16680000 { | |
524 | compatible = "qcom,i2c-qup-v1.1.1"; | |
525 | pinctrl-0 = <&i2c7_pins>; | |
526 | pinctrl-1 = <&i2c7_pins_sleep>; | |
527 | pinctrl-names = "default", "sleep"; | |
528 | reg = <0x16680000 0x1000>; | |
529 | interrupts = <GIC_SPI 159 IRQ_TYPE_NONE>; | |
530 | clocks = <&gcc GSBI7_QUP_CLK>, | |
531 | <&gcc GSBI7_H_CLK>; | |
532 | clock-names = "core", "iface"; | |
533 | status = "disabled"; | |
534 | }; | |
f335b8af KG |
535 | }; |
536 | ||
6a607e03 JS |
537 | rng@1a500000 { |
538 | compatible = "qcom,prng"; | |
539 | reg = <0x1a500000 0x200>; | |
540 | clocks = <&gcc PRNG_CLK>; | |
541 | clock-names = "core"; | |
542 | }; | |
543 | ||
f335b8af KG |
544 | qcom,ssbi@500000 { |
545 | compatible = "qcom,ssbi"; | |
546 | reg = <0x00500000 0x1000>; | |
547 | qcom,controller-type = "pmic-arbiter"; | |
874443fe SK |
548 | |
549 | pmicintc: pmic@0 { | |
550 | compatible = "qcom,pm8921"; | |
551 | interrupt-parent = <&tlmm_pinmux>; | |
552 | interrupts = <74 8>; | |
553 | #interrupt-cells = <2>; | |
554 | interrupt-controller; | |
555 | #address-cells = <1>; | |
556 | #size-cells = <0>; | |
557 | ||
558 | pm8921_gpio: gpio@150 { | |
559 | ||
2ca9c2a4 SB |
560 | compatible = "qcom,pm8921-gpio", |
561 | "qcom,ssbi-gpio"; | |
874443fe | 562 | reg = <0x150>; |
150b065d LW |
563 | interrupts = <192 IRQ_TYPE_NONE>, |
564 | <193 IRQ_TYPE_NONE>, | |
565 | <194 IRQ_TYPE_NONE>, | |
566 | <195 IRQ_TYPE_NONE>, | |
567 | <196 IRQ_TYPE_NONE>, | |
568 | <197 IRQ_TYPE_NONE>, | |
569 | <198 IRQ_TYPE_NONE>, | |
570 | <199 IRQ_TYPE_NONE>, | |
571 | <200 IRQ_TYPE_NONE>, | |
572 | <201 IRQ_TYPE_NONE>, | |
573 | <202 IRQ_TYPE_NONE>, | |
574 | <203 IRQ_TYPE_NONE>, | |
575 | <204 IRQ_TYPE_NONE>, | |
576 | <205 IRQ_TYPE_NONE>, | |
577 | <206 IRQ_TYPE_NONE>, | |
578 | <207 IRQ_TYPE_NONE>, | |
579 | <208 IRQ_TYPE_NONE>, | |
580 | <209 IRQ_TYPE_NONE>, | |
581 | <210 IRQ_TYPE_NONE>, | |
582 | <211 IRQ_TYPE_NONE>, | |
583 | <212 IRQ_TYPE_NONE>, | |
584 | <213 IRQ_TYPE_NONE>, | |
585 | <214 IRQ_TYPE_NONE>, | |
586 | <215 IRQ_TYPE_NONE>, | |
587 | <216 IRQ_TYPE_NONE>, | |
588 | <217 IRQ_TYPE_NONE>, | |
589 | <218 IRQ_TYPE_NONE>, | |
590 | <219 IRQ_TYPE_NONE>, | |
591 | <220 IRQ_TYPE_NONE>, | |
592 | <221 IRQ_TYPE_NONE>, | |
593 | <222 IRQ_TYPE_NONE>, | |
594 | <223 IRQ_TYPE_NONE>, | |
595 | <224 IRQ_TYPE_NONE>, | |
596 | <225 IRQ_TYPE_NONE>, | |
597 | <226 IRQ_TYPE_NONE>, | |
598 | <227 IRQ_TYPE_NONE>, | |
599 | <228 IRQ_TYPE_NONE>, | |
600 | <229 IRQ_TYPE_NONE>, | |
601 | <230 IRQ_TYPE_NONE>, | |
602 | <231 IRQ_TYPE_NONE>, | |
603 | <232 IRQ_TYPE_NONE>, | |
604 | <233 IRQ_TYPE_NONE>, | |
605 | <234 IRQ_TYPE_NONE>, | |
606 | <235 IRQ_TYPE_NONE>; | |
874443fe SK |
607 | gpio-controller; |
608 | #gpio-cells = <2>; | |
609 | ||
610 | }; | |
bce36046 SK |
611 | |
612 | pm8921_mpps: mpps@50 { | |
2ca9c2a4 SB |
613 | compatible = "qcom,pm8921-mpp", |
614 | "qcom,ssbi-mpp"; | |
bce36046 SK |
615 | reg = <0x50>; |
616 | gpio-controller; | |
617 | #gpio-cells = <2>; | |
618 | interrupts = | |
150b065d LW |
619 | <128 IRQ_TYPE_NONE>, |
620 | <129 IRQ_TYPE_NONE>, | |
621 | <130 IRQ_TYPE_NONE>, | |
622 | <131 IRQ_TYPE_NONE>, | |
623 | <132 IRQ_TYPE_NONE>, | |
624 | <133 IRQ_TYPE_NONE>, | |
625 | <134 IRQ_TYPE_NONE>, | |
626 | <135 IRQ_TYPE_NONE>, | |
627 | <136 IRQ_TYPE_NONE>, | |
628 | <137 IRQ_TYPE_NONE>, | |
629 | <138 IRQ_TYPE_NONE>, | |
630 | <139 IRQ_TYPE_NONE>; | |
bce36046 SK |
631 | }; |
632 | ||
bbf89b96 SK |
633 | rtc@11d { |
634 | compatible = "qcom,pm8921-rtc"; | |
635 | interrupt-parent = <&pmicintc>; | |
636 | interrupts = <39 1>; | |
637 | reg = <0x11d>; | |
638 | allow-set-time; | |
639 | }; | |
640 | ||
3050c5f5 SK |
641 | pwrkey@1c { |
642 | compatible = "qcom,pm8921-pwrkey"; | |
643 | reg = <0x1c>; | |
644 | interrupt-parent = <&pmicintc>; | |
645 | interrupts = <50 1>, <51 1>; | |
646 | debounce = <15625>; | |
647 | pull-up; | |
648 | }; | |
874443fe | 649 | }; |
f335b8af KG |
650 | }; |
651 | ||
652 | gcc: clock-controller@900000 { | |
653 | compatible = "qcom,gcc-apq8064"; | |
654 | reg = <0x00900000 0x4000>; | |
655 | #clock-cells = <1>; | |
656 | #reset-cells = <1>; | |
657 | }; | |
3fe5e3ce | 658 | |
1e1177bf KG |
659 | lcc: clock-controller@28000000 { |
660 | compatible = "qcom,lcc-apq8064"; | |
661 | reg = <0x28000000 0x1000>; | |
662 | #clock-cells = <1>; | |
663 | #reset-cells = <1>; | |
664 | }; | |
665 | ||
3fe5e3ce SB |
666 | mmcc: clock-controller@4000000 { |
667 | compatible = "qcom,mmcc-apq8064"; | |
668 | reg = <0x4000000 0x1000>; | |
669 | #clock-cells = <1>; | |
670 | #reset-cells = <1>; | |
671 | }; | |
045644ff | 672 | |
dc2f8152 SK |
673 | l2cc: clock-controller@2011000 { |
674 | compatible = "syscon"; | |
675 | reg = <0x2011000 0x1000>; | |
676 | }; | |
677 | ||
678 | rpm@108000 { | |
679 | compatible = "qcom,rpm-apq8064"; | |
680 | reg = <0x108000 0x1000>; | |
681 | qcom,ipc = <&l2cc 0x8 2>; | |
682 | ||
683 | interrupts = <GIC_SPI 19 IRQ_TYPE_EDGE_RISING>, | |
684 | <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>, | |
685 | <GIC_SPI 22 IRQ_TYPE_EDGE_RISING>; | |
686 | interrupt-names = "ack", "err", "wakeup"; | |
687 | ||
aac1b297 GD |
688 | rpmcc: clock-controller { |
689 | compatible = "qcom,rpmcc-apq8064", "qcom,rpmcc"; | |
690 | #clock-cells = <1>; | |
691 | }; | |
692 | ||
dc2f8152 SK |
693 | regulators { |
694 | compatible = "qcom,rpm-pm8921-regulators"; | |
695 | ||
2bce6e26 BA |
696 | pm8921_s1: s1 {}; |
697 | pm8921_s2: s2 {}; | |
698 | pm8921_s3: s3 {}; | |
699 | pm8921_s4: s4 {}; | |
700 | pm8921_s7: s7 {}; | |
701 | pm8921_s8: s8 {}; | |
702 | ||
703 | pm8921_l1: l1 {}; | |
704 | pm8921_l2: l2 {}; | |
705 | pm8921_l3: l3 {}; | |
706 | pm8921_l4: l4 {}; | |
707 | pm8921_l5: l5 {}; | |
708 | pm8921_l6: l6 {}; | |
709 | pm8921_l7: l7 {}; | |
710 | pm8921_l8: l8 {}; | |
711 | pm8921_l9: l9 {}; | |
712 | pm8921_l10: l10 {}; | |
713 | pm8921_l11: l11 {}; | |
714 | pm8921_l12: l12 {}; | |
715 | pm8921_l14: l14 {}; | |
716 | pm8921_l15: l15 {}; | |
717 | pm8921_l16: l16 {}; | |
718 | pm8921_l17: l17 {}; | |
719 | pm8921_l18: l18 {}; | |
720 | pm8921_l21: l21 {}; | |
721 | pm8921_l22: l22 {}; | |
722 | pm8921_l23: l23 {}; | |
723 | pm8921_l24: l24 {}; | |
724 | pm8921_l25: l25 {}; | |
725 | pm8921_l26: l26 {}; | |
726 | pm8921_l27: l27 {}; | |
727 | pm8921_l28: l28 {}; | |
728 | pm8921_l29: l29 {}; | |
729 | ||
730 | pm8921_lvs1: lvs1 {}; | |
731 | pm8921_lvs2: lvs2 {}; | |
732 | pm8921_lvs3: lvs3 {}; | |
733 | pm8921_lvs4: lvs4 {}; | |
734 | pm8921_lvs5: lvs5 {}; | |
735 | pm8921_lvs6: lvs6 {}; | |
736 | pm8921_lvs7: lvs7 {}; | |
737 | ||
738 | pm8921_usb_switch: usb-switch {}; | |
739 | ||
dc2f8152 SK |
740 | pm8921_hdmi_switch: hdmi-switch { |
741 | bias-pull-down; | |
742 | }; | |
2bce6e26 BA |
743 | |
744 | pm8921_ncp: ncp {}; | |
dc2f8152 SK |
745 | }; |
746 | }; | |
747 | ||
ea986611 SK |
748 | usb1_phy: phy@12500000 { |
749 | compatible = "qcom,usb-otg-ci"; | |
750 | reg = <0x12500000 0x400>; | |
751 | interrupts = <GIC_SPI 100 IRQ_TYPE_NONE>; | |
752 | status = "disabled"; | |
753 | dr_mode = "host"; | |
754 | ||
755 | clocks = <&gcc USB_HS1_XCVR_CLK>, | |
756 | <&gcc USB_HS1_H_CLK>; | |
757 | clock-names = "core", "iface"; | |
758 | ||
759 | resets = <&gcc USB_HS1_RESET>; | |
760 | reset-names = "link"; | |
761 | }; | |
762 | ||
223280b1 SK |
763 | usb3_phy: phy@12520000 { |
764 | compatible = "qcom,usb-otg-ci"; | |
765 | reg = <0x12520000 0x400>; | |
766 | interrupts = <GIC_SPI 188 IRQ_TYPE_NONE>; | |
767 | status = "disabled"; | |
768 | dr_mode = "host"; | |
769 | ||
770 | clocks = <&gcc USB_HS3_XCVR_CLK>, | |
771 | <&gcc USB_HS3_H_CLK>; | |
772 | clock-names = "core", "iface"; | |
773 | ||
774 | resets = <&gcc USB_HS3_RESET>; | |
775 | reset-names = "link"; | |
776 | }; | |
777 | ||
778 | usb4_phy: phy@12530000 { | |
779 | compatible = "qcom,usb-otg-ci"; | |
780 | reg = <0x12530000 0x400>; | |
781 | interrupts = <GIC_SPI 215 IRQ_TYPE_NONE>; | |
782 | status = "disabled"; | |
783 | dr_mode = "host"; | |
784 | ||
785 | clocks = <&gcc USB_HS4_XCVR_CLK>, | |
786 | <&gcc USB_HS4_H_CLK>; | |
787 | clock-names = "core", "iface"; | |
788 | ||
789 | resets = <&gcc USB_HS4_RESET>; | |
790 | reset-names = "link"; | |
791 | }; | |
792 | ||
ea986611 SK |
793 | gadget1: gadget@12500000 { |
794 | compatible = "qcom,ci-hdrc"; | |
795 | reg = <0x12500000 0x400>; | |
796 | status = "disabled"; | |
797 | dr_mode = "peripheral"; | |
798 | interrupts = <GIC_SPI 100 IRQ_TYPE_NONE>; | |
799 | usb-phy = <&usb1_phy>; | |
800 | }; | |
801 | ||
802 | usb1: usb@12500000 { | |
803 | compatible = "qcom,ehci-host"; | |
804 | reg = <0x12500000 0x400>; | |
805 | interrupts = <GIC_SPI 100 IRQ_TYPE_NONE>; | |
806 | status = "disabled"; | |
807 | usb-phy = <&usb1_phy>; | |
808 | }; | |
809 | ||
223280b1 SK |
810 | usb3: usb@12520000 { |
811 | compatible = "qcom,ehci-host"; | |
812 | reg = <0x12520000 0x400>; | |
813 | interrupts = <GIC_SPI 188 IRQ_TYPE_NONE>; | |
814 | status = "disabled"; | |
815 | usb-phy = <&usb3_phy>; | |
816 | }; | |
817 | ||
818 | usb4: usb@12530000 { | |
819 | compatible = "qcom,ehci-host"; | |
820 | reg = <0x12530000 0x400>; | |
821 | interrupts = <GIC_SPI 215 IRQ_TYPE_NONE>; | |
822 | status = "disabled"; | |
823 | usb-phy = <&usb4_phy>; | |
824 | }; | |
825 | ||
e629335f SK |
826 | sata_phy0: phy@1b400000 { |
827 | compatible = "qcom,apq8064-sata-phy"; | |
828 | status = "disabled"; | |
829 | reg = <0x1b400000 0x200>; | |
830 | reg-names = "phy_mem"; | |
831 | clocks = <&gcc SATA_PHY_CFG_CLK>; | |
832 | clock-names = "cfg"; | |
833 | #phy-cells = <0>; | |
834 | }; | |
835 | ||
836 | sata0: sata@29000000 { | |
bb4add2c | 837 | compatible = "qcom,apq8064-ahci", "generic-ahci"; |
e629335f SK |
838 | status = "disabled"; |
839 | reg = <0x29000000 0x180>; | |
840 | interrupts = <GIC_SPI 209 IRQ_TYPE_NONE>; | |
841 | ||
842 | clocks = <&gcc SFAB_SATA_S_H_CLK>, | |
843 | <&gcc SATA_H_CLK>, | |
844 | <&gcc SATA_A_CLK>, | |
845 | <&gcc SATA_RXOOB_CLK>, | |
846 | <&gcc SATA_PMALIVE_CLK>; | |
847 | clock-names = "slave_iface", | |
848 | "iface", | |
849 | "bus", | |
850 | "rxoob", | |
851 | "core_pmalive"; | |
852 | ||
853 | assigned-clocks = <&gcc SATA_RXOOB_CLK>, | |
854 | <&gcc SATA_PMALIVE_CLK>; | |
855 | assigned-clock-rates = <100000000>, <100000000>; | |
856 | ||
857 | phys = <&sata_phy0>; | |
858 | phy-names = "sata-phy"; | |
bb4add2c | 859 | ports-implemented = <0x1>; |
e629335f SK |
860 | }; |
861 | ||
045644ff | 862 | /* Temporary fixed regulator */ |
edb81ca3 SK |
863 | sdcc1bam:dma@12402000{ |
864 | compatible = "qcom,bam-v1.3.0"; | |
865 | reg = <0x12402000 0x8000>; | |
866 | interrupts = <0 98 0>; | |
867 | clocks = <&gcc SDC1_H_CLK>; | |
868 | clock-names = "bam_clk"; | |
869 | #dma-cells = <1>; | |
870 | qcom,ee = <0>; | |
871 | }; | |
872 | ||
873 | sdcc3bam:dma@12182000{ | |
874 | compatible = "qcom,bam-v1.3.0"; | |
875 | reg = <0x12182000 0x8000>; | |
876 | interrupts = <0 96 0>; | |
877 | clocks = <&gcc SDC3_H_CLK>; | |
878 | clock-names = "bam_clk"; | |
879 | #dma-cells = <1>; | |
880 | qcom,ee = <0>; | |
881 | }; | |
882 | ||
0be5fef1 SK |
883 | sdcc4bam:dma@121c2000{ |
884 | compatible = "qcom,bam-v1.3.0"; | |
885 | reg = <0x121c2000 0x8000>; | |
886 | interrupts = <0 95 0>; | |
887 | clocks = <&gcc SDC4_H_CLK>; | |
888 | clock-names = "bam_clk"; | |
889 | #dma-cells = <1>; | |
890 | qcom,ee = <0>; | |
891 | }; | |
892 | ||
045644ff | 893 | amba { |
2ef7d5f3 | 894 | compatible = "simple-bus"; |
045644ff SK |
895 | #address-cells = <1>; |
896 | #size-cells = <1>; | |
897 | ranges; | |
898 | sdcc1: sdcc@12400000 { | |
899 | status = "disabled"; | |
900 | compatible = "arm,pl18x", "arm,primecell"; | |
ccd140b5 SK |
901 | pinctrl-names = "default"; |
902 | pinctrl-0 = <&sdcc1_pins>; | |
045644ff SK |
903 | arm,primecell-periphid = <0x00051180>; |
904 | reg = <0x12400000 0x2000>; | |
905 | interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; | |
906 | interrupt-names = "cmd_irq"; | |
907 | clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>; | |
908 | clock-names = "mclk", "apb_pclk"; | |
909 | bus-width = <8>; | |
910 | max-frequency = <96000000>; | |
911 | non-removable; | |
912 | cap-sd-highspeed; | |
913 | cap-mmc-highspeed; | |
edb81ca3 SK |
914 | dmas = <&sdcc1bam 2>, <&sdcc1bam 1>; |
915 | dma-names = "tx", "rx"; | |
045644ff SK |
916 | }; |
917 | ||
918 | sdcc3: sdcc@12180000 { | |
919 | compatible = "arm,pl18x", "arm,primecell"; | |
920 | arm,primecell-periphid = <0x00051180>; | |
921 | status = "disabled"; | |
922 | reg = <0x12180000 0x2000>; | |
923 | interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; | |
924 | interrupt-names = "cmd_irq"; | |
925 | clocks = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>; | |
926 | clock-names = "mclk", "apb_pclk"; | |
927 | bus-width = <4>; | |
928 | cap-sd-highspeed; | |
929 | cap-mmc-highspeed; | |
930 | max-frequency = <192000000>; | |
931 | no-1-8-v; | |
edb81ca3 SK |
932 | dmas = <&sdcc3bam 2>, <&sdcc3bam 1>; |
933 | dma-names = "tx", "rx"; | |
045644ff | 934 | }; |
0be5fef1 SK |
935 | |
936 | sdcc4: sdcc@121c0000 { | |
937 | compatible = "arm,pl18x", "arm,primecell"; | |
938 | arm,primecell-periphid = <0x00051180>; | |
939 | status = "disabled"; | |
940 | reg = <0x121c0000 0x2000>; | |
941 | interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; | |
942 | interrupt-names = "cmd_irq"; | |
943 | clocks = <&gcc SDC4_CLK>, <&gcc SDC4_H_CLK>; | |
944 | clock-names = "mclk", "apb_pclk"; | |
945 | bus-width = <4>; | |
946 | cap-sd-highspeed; | |
947 | cap-mmc-highspeed; | |
948 | max-frequency = <48000000>; | |
0be5fef1 SK |
949 | dmas = <&sdcc4bam 2>, <&sdcc4bam 1>; |
950 | dma-names = "tx", "rx"; | |
951 | pinctrl-names = "default"; | |
952 | pinctrl-0 = <&sdc4_gpios>; | |
953 | }; | |
045644ff | 954 | }; |
4105d9d6 AG |
955 | |
956 | tcsr: syscon@1a400000 { | |
957 | compatible = "qcom,tcsr-apq8064", "syscon"; | |
958 | reg = <0x1a400000 0x100>; | |
959 | }; | |
bcc74b09 SV |
960 | |
961 | pcie: pci@1b500000 { | |
962 | compatible = "qcom,pcie-apq8064", "snps,dw-pcie"; | |
963 | reg = <0x1b500000 0x1000 | |
964 | 0x1b502000 0x80 | |
965 | 0x1b600000 0x100 | |
966 | 0x0ff00000 0x100000>; | |
967 | reg-names = "dbi", "elbi", "parf", "config"; | |
968 | device_type = "pci"; | |
969 | linux,pci-domain = <0>; | |
970 | bus-range = <0x00 0xff>; | |
971 | num-lanes = <1>; | |
972 | #address-cells = <3>; | |
973 | #size-cells = <2>; | |
974 | ranges = <0x81000000 0 0 0x0fe00000 0 0x00100000 /* I/O */ | |
975 | 0x82000000 0 0 0x08000000 0 0x07e00000>; /* memory */ | |
976 | interrupts = <GIC_SPI 238 IRQ_TYPE_NONE>; | |
977 | interrupt-names = "msi"; | |
978 | #interrupt-cells = <1>; | |
979 | interrupt-map-mask = <0 0 0 0x7>; | |
980 | interrupt-map = <0 0 0 1 &intc 0 36 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ | |
981 | <0 0 0 2 &intc 0 37 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ | |
982 | <0 0 0 3 &intc 0 38 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ | |
983 | <0 0 0 4 &intc 0 39 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ | |
984 | clocks = <&gcc PCIE_A_CLK>, | |
985 | <&gcc PCIE_H_CLK>, | |
986 | <&gcc PCIE_PHY_REF_CLK>; | |
987 | clock-names = "core", "iface", "phy"; | |
988 | resets = <&gcc PCIE_ACLK_RESET>, | |
989 | <&gcc PCIE_HCLK_RESET>, | |
990 | <&gcc PCIE_POR_RESET>, | |
991 | <&gcc PCIE_PCI_RESET>, | |
992 | <&gcc PCIE_PHY_RESET>; | |
993 | reset-names = "axi", "ahb", "por", "pci", "phy"; | |
994 | status = "disabled"; | |
995 | }; | |
f335b8af KG |
996 | }; |
997 | }; | |
a30e78bd | 998 | #include "qcom-apq8064-pins.dtsi" |