[deliverable/linux.git] / arch / arm / mach-exynos / pm_domains.c

/*
 * Exynos Generic power domain support.
 *
 * Copyright (c) 2012 Samsung Electronics Co., Ltd.
 *		http://www.samsung.com
 *
 * Implementation of Exynos specific power domain control which is used in
 * conjunction with runtime-pm. Support for both device-tree and non-device-tree
 * based power domain support is included.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
*/

#include <linux/io.h>
#include <linux/err.h>
#include <linux/slab.h>
#include <linux/pm_domain.h>
#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/of_address.h>
#include <linux/of_platform.h>
#include <linux/sched.h>

#define INT_LOCAL_PWR_EN	0x7
#define MAX_CLK_PER_DOMAIN	4

/*
 * Exynos specific wrapper around the generic power domain
 */
struct exynos_pm_domain {
	void __iomem *base;
	char const *name;
	bool is_off;
	struct generic_pm_domain pd;
	struct clk *oscclk;
	struct clk *clk[MAX_CLK_PER_DOMAIN];
	struct clk *pclk[MAX_CLK_PER_DOMAIN];
	struct clk *asb_clk[MAX_CLK_PER_DOMAIN];
};

static int exynos_pd_power(struct generic_pm_domain *domain, bool power_on)
{
	struct exynos_pm_domain *pd;
	void __iomem *base;
	u32 timeout, pwr;
	char *op;
	int i;

	pd = container_of(domain, struct exynos_pm_domain, pd);
	base = pd->base;

	for (i = 0; i < MAX_CLK_PER_DOMAIN; i++) {
		if (IS_ERR(pd->asb_clk[i]))
			break;
		clk_prepare_enable(pd->asb_clk[i]);
	}

	/* Set oscclk before powering off a domain*/
	if (!power_on) {
		for (i = 0; i < MAX_CLK_PER_DOMAIN; i++) {
			if (IS_ERR(pd->clk[i]))
				break;
			pd->pclk[i] = clk_get_parent(pd->clk[i]);
			if (clk_set_parent(pd->clk[i], pd->oscclk))
				pr_err("%s: error setting oscclk as parent to clock %d\n",
						pd->name, i);
		}
	}

	pwr = power_on ? INT_LOCAL_PWR_EN : 0;
	__raw_writel(pwr, base);

	/* Wait max 1ms */
	timeout = 10;

	while ((__raw_readl(base + 0x4) & INT_LOCAL_PWR_EN) != pwr) {
		if (!timeout) {
			op = (power_on) ? "enable" : "disable";
			pr_err("Power domain %s %s failed\n", domain->name, op);
			return -ETIMEDOUT;
		}
		timeout--;
		cpu_relax();
		usleep_range(80, 100);
	}

	/* Restore clocks after powering on a domain*/
	if (power_on) {
		for (i = 0; i < MAX_CLK_PER_DOMAIN; i++) {
			if (IS_ERR(pd->clk[i]))
				break;

			if (IS_ERR(pd->pclk[i]))
				continue; /* Skip on first power up */
			if (clk_set_parent(pd->clk[i], pd->pclk[i]))
				pr_err("%s: error setting parent to clock%d\n",
						pd->name, i);
		}
	}

	for (i = 0; i < MAX_CLK_PER_DOMAIN; i++) {
		if (IS_ERR(pd->asb_clk[i]))
			break;
		clk_disable_unprepare(pd->asb_clk[i]);
	}

	return 0;
}

static int exynos_pd_power_on(struct generic_pm_domain *domain)
{
	return exynos_pd_power(domain, true);
}

static int exynos_pd_power_off(struct generic_pm_domain *domain)
{
	return exynos_pd_power(domain, false);
}

static __init int exynos4_pm_init_power_domain(void)
{
	struct device_node *np;

	for_each_compatible_node(np, NULL, "samsung,exynos4210-pd") {
		struct exynos_pm_domain *pd;
		int on, i;

		pd = kzalloc(sizeof(*pd), GFP_KERNEL);
		if (!pd) {
			pr_err("%s: failed to allocate memory for domain\n",
					__func__);
			of_node_put(np);
			return -ENOMEM;
		}
		pd->pd.name = kstrdup_const(strrchr(np->full_name, '/') + 1,
					    GFP_KERNEL);
		if (!pd->pd.name) {
			kfree(pd);
			of_node_put(np);
			return -ENOMEM;
		}

		pd->name = pd->pd.name;
		pd->base = of_iomap(np, 0);
		if (!pd->base) {
			pr_warn("%s: failed to map memory\n", __func__);
			kfree_const(pd->pd.name);
			kfree(pd);
			continue;
		}

		pd->pd.power_off = exynos_pd_power_off;
		pd->pd.power_on = exynos_pd_power_on;

		for (i = 0; i < MAX_CLK_PER_DOMAIN; i++) {
			char clk_name[8];

			snprintf(clk_name, sizeof(clk_name), "asb%d", i);
			pd->asb_clk[i] = of_clk_get_by_name(np, clk_name);
			if (IS_ERR(pd->asb_clk[i]))
				break;
		}

		pd->oscclk = of_clk_get_by_name(np, "oscclk");
		if (IS_ERR(pd->oscclk))
			goto no_clk;

		for (i = 0; i < MAX_CLK_PER_DOMAIN; i++) {
			char clk_name[8];

			snprintf(clk_name, sizeof(clk_name), "clk%d", i);
			pd->clk[i] = of_clk_get_by_name(np, clk_name);
			if (IS_ERR(pd->clk[i]))
				break;
			/*
			 * Skip setting parent on first power up.
			 * The parent at this time may not be useful at all.
			 */
			pd->pclk[i] = ERR_PTR(-EINVAL);
		}

		if (IS_ERR(pd->clk[0]))
			clk_put(pd->oscclk);

no_clk:
		on = __raw_readl(pd->base + 0x4) & INT_LOCAL_PWR_EN;

		pm_genpd_init(&pd->pd, NULL, !on);
		of_genpd_add_provider_simple(np, &pd->pd);
	}

	/* Assign the child power domains to their parents */
	for_each_compatible_node(np, NULL, "samsung,exynos4210-pd") {
		struct generic_pm_domain *child_domain, *parent_domain;
		struct of_phandle_args args;

		args.np = np;
		args.args_count = 0;
		child_domain = of_genpd_get_from_provider(&args);
		if (IS_ERR(child_domain))
			continue;

		if (of_parse_phandle_with_args(np, "power-domains",
					 "#power-domain-cells", 0, &args) != 0)
			continue;

		parent_domain = of_genpd_get_from_provider(&args);
		if (IS_ERR(parent_domain))
			continue;

		if (pm_genpd_add_subdomain(parent_domain, child_domain))
			pr_warn("%s failed to add subdomain: %s\n",
				parent_domain->name, child_domain->name);
		else
			pr_info("%s has as child subdomain: %s.\n",
				parent_domain->name, child_domain->name);
	}

	return 0;
}
core_initcall(exynos4_pm_init_power_domain);
Commit	Line	Data
91cfbd4e TA	1	/*
	2	* Exynos Generic power domain support.
	3	*
	4	* Copyright (c) 2012 Samsung Electronics Co., Ltd.
	5	* http://www.samsung.com
	6	*
	7	* Implementation of Exynos specific power domain control which is used in
	8	* conjunction with runtime-pm. Support for both device-tree and non-device-tree
	9	* based power domain support is included.
	10	*
	11	* This program is free software; you can redistribute it and/or modify
	12	* it under the terms of the GNU General Public License version 2 as
	13	* published by the Free Software Foundation.
	14	*/
	15
	16	#include <linux/io.h>
	17	#include <linux/err.h>
	18	#include <linux/slab.h>
	19	#include <linux/pm_domain.h>
c760569d	20	#include <linux/clk.h>
91cfbd4e TA	21	#include <linux/delay.h>
91cfbd4e TA	22	#include <linux/of_address.h>
8a65d236 TF	23	#include <linux/of_platform.h>
8a65d236 TF	24	#include <linux/sched.h>
91cfbd4e	25
b634e38f	26	#define INT_LOCAL_PWR_EN 0x7
c760569d P	27	#define MAX_CLK_PER_DOMAIN 4
c760569d P	28
91cfbd4e TA	29	/*
	30	* Exynos specific wrapper around the generic power domain
	31	*/
	32	struct exynos_pm_domain {
	33	void __iomem *base;
	34	char const *name;
	35	bool is_off;
	36	struct generic_pm_domain pd;
c760569d P	37	struct clk *oscclk;
	38	struct clk *clk[MAX_CLK_PER_DOMAIN];
	39	struct clk *pclk[MAX_CLK_PER_DOMAIN];
528eae6c	40	struct clk *asb_clk[MAX_CLK_PER_DOMAIN];
91cfbd4e TA	41	};
	42
	43	static int exynos_pd_power(struct generic_pm_domain *domain, bool power_on)
	44	{
	45	struct exynos_pm_domain *pd;
	46	void __iomem *base;
	47	u32 timeout, pwr;
	48	char *op;
528eae6c	49	int i;
91cfbd4e TA	50
	51	pd = container_of(domain, struct exynos_pm_domain, pd);
	52	base = pd->base;
	53
528eae6c AH	54	for (i = 0; i < MAX_CLK_PER_DOMAIN; i++) {
	55	if (IS_ERR(pd->asb_clk[i]))
	56	break;
	57	clk_prepare_enable(pd->asb_clk[i]);
	58	}
	59
c760569d P	60	/* Set oscclk before powering off a domain*/
c760569d P	61	if (!power_on) {
c760569d P	62	for (i = 0; i < MAX_CLK_PER_DOMAIN; i++) {
	63	if (IS_ERR(pd->clk[i]))
	64	break;
29e5eea0	65	pd->pclk[i] = clk_get_parent(pd->clk[i]);
c760569d P	66	if (clk_set_parent(pd->clk[i], pd->oscclk))
	67	pr_err("%s: error setting oscclk as parent to clock %d\n",
	68	pd->name, i);
	69	}
	70	}
	71
b634e38f	72	pwr = power_on ? INT_LOCAL_PWR_EN : 0;
91cfbd4e TA	73	__raw_writel(pwr, base);
	74
	75	/* Wait max 1ms */
	76	timeout = 10;
	77
b634e38f	78	while ((__raw_readl(base + 0x4) & INT_LOCAL_PWR_EN) != pwr) {
91cfbd4e TA	79	if (!timeout) {
	80	op = (power_on) ? "enable" : "disable";
	81	pr_err("Power domain %s %s failed\n", domain->name, op);
	82	return -ETIMEDOUT;
	83	}
	84	timeout--;
	85	cpu_relax();
	86	usleep_range(80, 100);
	87	}
c760569d P	88
	89	/* Restore clocks after powering on a domain*/
	90	if (power_on) {
c760569d P	91	for (i = 0; i < MAX_CLK_PER_DOMAIN; i++) {
	92	if (IS_ERR(pd->clk[i]))
	93	break;
29e5eea0	94
a0a966b8	95	if (IS_ERR(pd->pclk[i]))
29e5eea0	96	continue; /* Skip on first power up */
c760569d P	97	if (clk_set_parent(pd->clk[i], pd->pclk[i]))
	98	pr_err("%s: error setting parent to clock%d\n",
	99	pd->name, i);
	100	}
	101	}
	102
528eae6c AH	103	for (i = 0; i < MAX_CLK_PER_DOMAIN; i++) {
	104	if (IS_ERR(pd->asb_clk[i]))
	105	break;
	106	clk_disable_unprepare(pd->asb_clk[i]);
	107	}
	108
91cfbd4e TA	109	return 0;
	110	}
	111
	112	static int exynos_pd_power_on(struct generic_pm_domain *domain)
	113	{
	114	return exynos_pd_power(domain, true);
	115	}
	116
	117	static int exynos_pd_power_off(struct generic_pm_domain *domain)
	118	{
	119	return exynos_pd_power(domain, false);
	120	}
	121
8eaa9e42	122	static __init int exynos4_pm_init_power_domain(void)
91cfbd4e TA	123	{
	124	struct device_node *np;
	125
	126	for_each_compatible_node(np, NULL, "samsung,exynos4210-pd") {
	127	struct exynos_pm_domain *pd;
c760569d	128	int on, i;
8a65d236	129
91cfbd4e TA	130	pd = kzalloc(sizeof(*pd), GFP_KERNEL);
	131	if (!pd) {
	132	pr_err("%s: failed to allocate memory for domain\n",
	133	__func__);
fe4034a3	134	of_node_put(np);
91cfbd4e TA	135	return -ENOMEM;
91cfbd4e TA	136	}
2be2a3ff MS	137	pd->pd.name = kstrdup_const(strrchr(np->full_name, '/') + 1,
2be2a3ff MS	138	GFP_KERNEL);
c88cad34 KK	139	if (!pd->pd.name) {
	140	kfree(pd);
	141	of_node_put(np);
	142	return -ENOMEM;
	143	}
	144
7add0ec0	145	pd->name = pd->pd.name;
91cfbd4e	146	pd->base = of_iomap(np, 0);
ef2156cf	147	if (!pd->base) {
2be2a3ff	148	pr_warn("%s: failed to map memory\n", __func__);
27bbd23f	149	kfree_const(pd->pd.name);
ef2156cf	150	kfree(pd);
ef2156cf KK	151	continue;
	152	}
	153
91cfbd4e TA	154	pd->pd.power_off = exynos_pd_power_off;
91cfbd4e TA	155	pd->pd.power_on = exynos_pd_power_on;
2ed5f236	156
528eae6c AH	157	for (i = 0; i < MAX_CLK_PER_DOMAIN; i++) {
	158	char clk_name[8];
	159
	160	snprintf(clk_name, sizeof(clk_name), "asb%d", i);
2be2a3ff	161	pd->asb_clk[i] = of_clk_get_by_name(np, clk_name);
528eae6c AH	162	if (IS_ERR(pd->asb_clk[i]))
	163	break;
	164	}
	165
2be2a3ff	166	pd->oscclk = of_clk_get_by_name(np, "oscclk");
c760569d P	167	if (IS_ERR(pd->oscclk))
	168	goto no_clk;
	169
	170	for (i = 0; i < MAX_CLK_PER_DOMAIN; i++) {
	171	char clk_name[8];
	172
	173	snprintf(clk_name, sizeof(clk_name), "clk%d", i);
2be2a3ff	174	pd->clk[i] = of_clk_get_by_name(np, clk_name);
c760569d P	175	if (IS_ERR(pd->clk[i]))
c760569d P	176	break;
29e5eea0 KK	177	/*
	178	* Skip setting parent on first power up.
	179	* The parent at this time may not be useful at all.
	180	*/
	181	pd->pclk[i] = ERR_PTR(-EINVAL);
c760569d P	182	}
	183
	184	if (IS_ERR(pd->clk[0]))
	185	clk_put(pd->oscclk);
	186
	187	no_clk:
b634e38f	188	on = __raw_readl(pd->base + 0x4) & INT_LOCAL_PWR_EN;
2ed5f236 TF	189
2ed5f236 TF	190	pm_genpd_init(&pd->pd, NULL, !on);
a4a8c2c4	191	of_genpd_add_provider_simple(np, &pd->pd);
91cfbd4e	192	}
8a65d236	193
0f780751 MS	194	/* Assign the child power domains to their parents */
	195	for_each_compatible_node(np, NULL, "samsung,exynos4210-pd") {
	196	struct generic_pm_domain child_domain, parent_domain;
	197	struct of_phandle_args args;
	198
	199	args.np = np;
	200	args.args_count = 0;
	201	child_domain = of_genpd_get_from_provider(&args);
0b7dc0ff	202	if (IS_ERR(child_domain))
51a6256b	203	continue;
0f780751 MS	204
	205	if (of_parse_phandle_with_args(np, "power-domains",
	206	"#power-domain-cells", 0, &args) != 0)
51a6256b	207	continue;
0f780751 MS	208
0f780751 MS	209	parent_domain = of_genpd_get_from_provider(&args);
0b7dc0ff	210	if (IS_ERR(parent_domain))
51a6256b	211	continue;
0f780751 MS	212
	213	if (pm_genpd_add_subdomain(parent_domain, child_domain))
	214	pr_warn("%s failed to add subdomain: %s\n",
	215	parent_domain->name, child_domain->name);
	216	else
	217	pr_info("%s has as child subdomain: %s.\n",
	218	parent_domain->name, child_domain->name);
0f780751 MS	219	}
0f780751 MS	220
91cfbd4e TA	221	return 0;
91cfbd4e TA	222	}
2be2a3ff	223	core_initcall(exynos4_pm_init_power_domain);