[deliverable/linux.git] / arch / arm / mm / nommu.c

/*
 *  linux/arch/arm/mm/nommu.c
 *
 * ARM uCLinux supporting functions.
 */
#include <linux/module.h>
#include <linux/mm.h>
#include <linux/pagemap.h>
#include <linux/io.h>
#include <linux/memblock.h>
#include <linux/kernel.h>

#include <asm/cacheflush.h>
#include <asm/sections.h>
#include <asm/page.h>
#include <asm/setup.h>
#include <asm/traps.h>
#include <asm/mach/arch.h>
#include <asm/cputype.h>
#include <asm/mpu.h>
#include <asm/procinfo.h>

#include "mm.h"

#ifdef CONFIG_ARM_MPU
struct mpu_rgn_info mpu_rgn_info;

/* Region number */
static void rgnr_write(u32 v)
{
	asm("mcr        p15, 0, %0, c6, c2, 0" : : "r" (v));
}

/* Data-side / unified region attributes */

/* Region access control register */
static void dracr_write(u32 v)
{
	asm("mcr        p15, 0, %0, c6, c1, 4" : : "r" (v));
}

/* Region size register */
static void drsr_write(u32 v)
{
	asm("mcr        p15, 0, %0, c6, c1, 2" : : "r" (v));
}

/* Region base address register */
static void drbar_write(u32 v)
{
	asm("mcr        p15, 0, %0, c6, c1, 0" : : "r" (v));
}

static u32 drbar_read(void)
{
	u32 v;
	asm("mrc        p15, 0, %0, c6, c1, 0" : "=r" (v));
	return v;
}
/* Optional instruction-side region attributes */

/* I-side Region access control register */
static void iracr_write(u32 v)
{
	asm("mcr        p15, 0, %0, c6, c1, 5" : : "r" (v));
}

/* I-side Region size register */
static void irsr_write(u32 v)
{
	asm("mcr        p15, 0, %0, c6, c1, 3" : : "r" (v));
}

/* I-side Region base address register */
static void irbar_write(u32 v)
{
	asm("mcr        p15, 0, %0, c6, c1, 1" : : "r" (v));
}

static unsigned long irbar_read(void)
{
	unsigned long v;
	asm("mrc        p15, 0, %0, c6, c1, 1" : "=r" (v));
	return v;
}

/* MPU initialisation functions */
void __init sanity_check_meminfo_mpu(void)
{
	phys_addr_t phys_offset = PHYS_OFFSET;
	phys_addr_t aligned_region_size, specified_mem_size, rounded_mem_size;
	struct memblock_region *reg;
	bool first = true;
	phys_addr_t mem_start;
	phys_addr_t mem_end;

	for_each_memblock(memory, reg) {
		if (first) {
			/*
			 * Initially only use memory continuous from
			 * PHYS_OFFSET */
			if (reg->base != phys_offset)
				panic("First memory bank must be contiguous from PHYS_OFFSET");

			mem_start = reg->base;
			mem_end = reg->base + reg->size;
			specified_mem_size = reg->size;
			first = false;
		} else {
			/*
			 * memblock auto merges contiguous blocks, remove
			 * all blocks afterwards in one go (we can't remove
			 * blocks separately while iterating)
			 */
			pr_notice("Ignoring RAM after %pa, memory at %pa ignored\n",
				  &mem_end, &reg->base);
			memblock_remove(reg->base, 0 - reg->base);
			break;
		}
	}

	/*
	 * MPU has curious alignment requirements: Size must be power of 2, and
	 * region start must be aligned to the region size
	 */
	if (phys_offset != 0)
		pr_info("PHYS_OFFSET != 0 => MPU Region size constrained by alignment requirements\n");

	/*
	 * Maximum aligned region might overflow phys_addr_t if phys_offset is
	 * 0. Hence we keep everything below 4G until we take the smaller of
	 * the aligned_region_size and rounded_mem_size, one of which is
	 * guaranteed to be smaller than the maximum physical address.
	 */
	aligned_region_size = (phys_offset - 1) ^ (phys_offset);
	/* Find the max power-of-two sized region that fits inside our bank */
	rounded_mem_size = (1 <<  __fls(specified_mem_size)) - 1;

	/* The actual region size is the smaller of the two */
	aligned_region_size = aligned_region_size < rounded_mem_size
				? aligned_region_size + 1
				: rounded_mem_size + 1;

	if (aligned_region_size != specified_mem_size) {
		pr_warn("Truncating memory from %pa to %pa (MPU region constraints)",
				&specified_mem_size, &aligned_region_size);
		memblock_remove(mem_start + aligned_region_size,
				specified_mem_size - aligned_region_size);

		mem_end = mem_start + aligned_region_size;
	}

	pr_debug("MPU Region from %pa size %pa (end %pa))\n",
		&phys_offset, &aligned_region_size, &mem_end);

}

static int mpu_present(void)
{
	return ((read_cpuid_ext(CPUID_EXT_MMFR0) & MMFR0_PMSA) == MMFR0_PMSAv7);
}

static int mpu_max_regions(void)
{
	/*
	 * We don't support a different number of I/D side regions so if we
	 * have separate instruction and data memory maps then return
	 * whichever side has a smaller number of supported regions.
	 */
	u32 dregions, iregions, mpuir;
	mpuir = read_cpuid(CPUID_MPUIR);

	dregions = iregions = (mpuir & MPUIR_DREGION_SZMASK) >> MPUIR_DREGION;

	/* Check for separate d-side and i-side memory maps */
	if (mpuir & MPUIR_nU)
		iregions = (mpuir & MPUIR_IREGION_SZMASK) >> MPUIR_IREGION;

	/* Use the smallest of the two maxima */
	return min(dregions, iregions);
}

static int mpu_iside_independent(void)
{
	/* MPUIR.nU specifies whether there is *not* a unified memory map */
	return read_cpuid(CPUID_MPUIR) & MPUIR_nU;
}

static int mpu_min_region_order(void)
{
	u32 drbar_result, irbar_result;
	/* We've kept a region free for this probing */
	rgnr_write(MPU_PROBE_REGION);
	isb();
	/*
	 * As per ARM ARM, write 0xFFFFFFFC to DRBAR to find the minimum
	 * region order
	*/
	drbar_write(0xFFFFFFFC);
	drbar_result = irbar_result = drbar_read();
	drbar_write(0x0);
	/* If the MPU is non-unified, we use the larger of the two minima*/
	if (mpu_iside_independent()) {
		irbar_write(0xFFFFFFFC);
		irbar_result = irbar_read();
		irbar_write(0x0);
	}
	isb(); /* Ensure that MPU region operations have completed */
	/* Return whichever result is larger */
	return __ffs(max(drbar_result, irbar_result));
}

static int mpu_setup_region(unsigned int number, phys_addr_t start,
			unsigned int size_order, unsigned int properties)
{
	u32 size_data;

	/* We kept a region free for probing resolution of MPU regions*/
	if (number > mpu_max_regions() || number == MPU_PROBE_REGION)
		return -ENOENT;

	if (size_order > 32)
		return -ENOMEM;

	if (size_order < mpu_min_region_order())
		return -ENOMEM;

	/* Writing N to bits 5:1 (RSR_SZ)  specifies region size 2^N+1 */
	size_data = ((size_order - 1) << MPU_RSR_SZ) | 1 << MPU_RSR_EN;

	dsb(); /* Ensure all previous data accesses occur with old mappings */
	rgnr_write(number);
	isb();
	drbar_write(start);
	dracr_write(properties);
	isb(); /* Propagate properties before enabling region */
	drsr_write(size_data);

	/* Check for independent I-side registers */
	if (mpu_iside_independent()) {
		irbar_write(start);
		iracr_write(properties);
		isb();
		irsr_write(size_data);
	}
	isb();

	/* Store region info (we treat i/d side the same, so only store d) */
	mpu_rgn_info.rgns[number].dracr = properties;
	mpu_rgn_info.rgns[number].drbar = start;
	mpu_rgn_info.rgns[number].drsr = size_data;
	return 0;
}

/*
* Set up default MPU regions, doing nothing if there is no MPU
*/
void __init mpu_setup(void)
{
	int region_err;
	if (!mpu_present())
		return;

	region_err = mpu_setup_region(MPU_RAM_REGION, PHYS_OFFSET,
					ilog2(memblock.memory.regions[0].size),
					MPU_AP_PL1RW_PL0RW | MPU_RGN_NORMAL);
	if (region_err) {
		panic("MPU region initialization failure! %d", region_err);
	} else {
		pr_info("Using ARMv7 PMSA Compliant MPU. "
			 "Region independence: %s, Max regions: %d\n",
			mpu_iside_independent() ? "Yes" : "No",
			mpu_max_regions());
	}
}
#else
static void sanity_check_meminfo_mpu(void) {}
static void __init mpu_setup(void) {}
#endif /* CONFIG_ARM_MPU */

void __init arm_mm_memblock_reserve(void)
{
#ifndef CONFIG_CPU_V7M
	/*
	 * Register the exception vector page.
	 * some architectures which the DRAM is the exception vector to trap,
	 * alloc_page breaks with error, although it is not NULL, but "0."
	 */
	memblock_reserve(CONFIG_VECTORS_BASE, 2 * PAGE_SIZE);
#else /* ifndef CONFIG_CPU_V7M */
	/*
	 * There is no dedicated vector page on V7-M. So nothing needs to be
	 * reserved here.
	 */
#endif
}

void __init sanity_check_meminfo(void)
{
	phys_addr_t end;
	sanity_check_meminfo_mpu();
	end = memblock_end_of_DRAM();
	high_memory = __va(end - 1) + 1;
	memblock_set_current_limit(end);
}

/*
 * paging_init() sets up the page tables, initialises the zone memory
 * maps, and sets up the zero page, bad page and bad page tables.
 */
void __init paging_init(const struct machine_desc *mdesc)
{
	early_trap_init((void *)CONFIG_VECTORS_BASE);
	mpu_setup();
	bootmem_init();
}

/*
 * We don't need to do anything here for nommu machines.
 */
void setup_mm_for_reboot(void)
{
}

void flush_dcache_page(struct page *page)
{
	__cpuc_flush_dcache_area(page_address(page), PAGE_SIZE);
}
EXPORT_SYMBOL(flush_dcache_page);

void flush_kernel_dcache_page(struct page *page)
{
	__cpuc_flush_dcache_area(page_address(page), PAGE_SIZE);
}
EXPORT_SYMBOL(flush_kernel_dcache_page);

void copy_to_user_page(struct vm_area_struct *vma, struct page *page,
		       unsigned long uaddr, void *dst, const void *src,
		       unsigned long len)
{
	memcpy(dst, src, len);
	if (vma->vm_flags & VM_EXEC)
		__cpuc_coherent_user_range(uaddr, uaddr + len);
}

void __iomem *__arm_ioremap_pfn(unsigned long pfn, unsigned long offset,
				size_t size, unsigned int mtype)
{
	if (pfn >= (0x100000000ULL >> PAGE_SHIFT))
		return NULL;
	return (void __iomem *) (offset + (pfn << PAGE_SHIFT));
}
EXPORT_SYMBOL(__arm_ioremap_pfn);

void __iomem *__arm_ioremap_caller(phys_addr_t phys_addr, size_t size,
				   unsigned int mtype, void *caller)
{
	return (void __iomem *)phys_addr;
}

void __iomem * (*arch_ioremap_caller)(phys_addr_t, size_t, unsigned int, void *);

void __iomem *ioremap(resource_size_t res_cookie, size_t size)
{
	return __arm_ioremap_caller(res_cookie, size, MT_DEVICE,
				    __builtin_return_address(0));
}
EXPORT_SYMBOL(ioremap);

void __iomem *ioremap_cache(resource_size_t res_cookie, size_t size)
{
	return __arm_ioremap_caller(res_cookie, size, MT_DEVICE_CACHED,
				    __builtin_return_address(0));
}
EXPORT_SYMBOL(ioremap_cache);

void __iomem *ioremap_wc(resource_size_t res_cookie, size_t size)
{
	return __arm_ioremap_caller(res_cookie, size, MT_DEVICE_WC,
				    __builtin_return_address(0));
}
EXPORT_SYMBOL(ioremap_wc);

void __iounmap(volatile void __iomem *addr)
{
}
EXPORT_SYMBOL(__iounmap);

void (*arch_iounmap)(volatile void __iomem *);

void iounmap(volatile void __iomem *addr)
{
}
EXPORT_SYMBOL(iounmap);
Commit	Line	Data
5924486d RK	1	/*
	2	* linux/arch/arm/mm/nommu.c
	3	*
	4	* ARM uCLinux supporting functions.
	5	*/
	6	#include <linux/module.h>
e6b1b38c RK	7	#include <linux/mm.h>
e6b1b38c RK	8	#include <linux/pagemap.h>
fced80c7	9	#include <linux/io.h>
2778f620	10	#include <linux/memblock.h>
5ad7dcbe	11	#include <linux/kernel.h>
5924486d	12
e6b1b38c	13	#include <asm/cacheflush.h>
37efe642	14	#include <asm/sections.h>
5924486d	15	#include <asm/page.h>
b32f3afe	16	#include <asm/setup.h>
6b8e5c91	17	#include <asm/traps.h>
3ff1559e	18	#include <asm/mach/arch.h>
5ad7dcbe JA	19	#include <asm/cputype.h>
5ad7dcbe JA	20	#include <asm/mpu.h>
83651bb9	21	#include <asm/procinfo.h>
5924486d	22
d111e8f9 RK	23	#include "mm.h"
d111e8f9 RK	24
5ad7dcbe JA	25	#ifdef CONFIG_ARM_MPU
	26	struct mpu_rgn_info mpu_rgn_info;
	27
	28	/* Region number */
	29	static void rgnr_write(u32 v)
	30	{
	31	asm("mcr p15, 0, %0, c6, c2, 0" : : "r" (v));
	32	}
	33
	34	/* Data-side / unified region attributes */
	35
	36	/* Region access control register */
	37	static void dracr_write(u32 v)
	38	{
	39	asm("mcr p15, 0, %0, c6, c1, 4" : : "r" (v));
	40	}
	41
	42	/* Region size register */
	43	static void drsr_write(u32 v)
	44	{
	45	asm("mcr p15, 0, %0, c6, c1, 2" : : "r" (v));
	46	}
	47
	48	/* Region base address register */
	49	static void drbar_write(u32 v)
	50	{
	51	asm("mcr p15, 0, %0, c6, c1, 0" : : "r" (v));
	52	}
	53
	54	static u32 drbar_read(void)
	55	{
	56	u32 v;
	57	asm("mrc p15, 0, %0, c6, c1, 0" : "=r" (v));
	58	return v;
	59	}
	60	/* Optional instruction-side region attributes */
	61
	62	/* I-side Region access control register */
	63	static void iracr_write(u32 v)
	64	{
	65	asm("mcr p15, 0, %0, c6, c1, 5" : : "r" (v));
	66	}
	67
	68	/* I-side Region size register */
	69	static void irsr_write(u32 v)
	70	{
	71	asm("mcr p15, 0, %0, c6, c1, 3" : : "r" (v));
	72	}
	73
	74	/* I-side Region base address register */
	75	static void irbar_write(u32 v)
	76	{
	77	asm("mcr p15, 0, %0, c6, c1, 1" : : "r" (v));
	78	}
	79
	80	static unsigned long irbar_read(void)
	81	{
	82	unsigned long v;
	83	asm("mrc p15, 0, %0, c6, c1, 1" : "=r" (v));
	84	return v;
	85	}
	86
	87	/* MPU initialisation functions */
	88	void __init sanity_check_meminfo_mpu(void)
89	{
5ad7dcbe JA	90	phys_addr_t phys_offset = PHYS_OFFSET;
5ad7dcbe JA	91	phys_addr_t aligned_region_size, specified_mem_size, rounded_mem_size;
1c2f87c2 LA	92	struct memblock_region *reg;
	93	bool first = true;
	94	phys_addr_t mem_start;
	95	phys_addr_t mem_end;
	96
	97	for_each_memblock(memory, reg) {
	98	if (first) {
	99	/*
	100	* Initially only use memory continuous from
	101	* PHYS_OFFSET */
	102	if (reg->base != phys_offset)
	103	panic("First memory bank must be contiguous from PHYS_OFFSET");
	104
	105	mem_start = reg->base;
	106	mem_end = reg->base + reg->size;
	107	specified_mem_size = reg->size;
	108	first = false;
5ad7dcbe	109	} else {
1c2f87c2 LA	110	/*
1c2f87c2 LA	111	* memblock auto merges contiguous blocks, remove
695665b0 JPB	112	* all blocks afterwards in one go (we can't remove
695665b0 JPB	113	* blocks separately while iterating)
1c2f87c2 LA	114	*/
1c2f87c2 LA	115	pr_notice("Ignoring RAM after %pa, memory at %pa ignored\n",
695665b0 JPB	116	&mem_end, &reg->base);
	117	memblock_remove(reg->base, 0 - reg->base);
	118	break;
5ad7dcbe JA	119	}
5ad7dcbe JA	120	}
5ad7dcbe JA	121
	122	/*
	123	* MPU has curious alignment requirements: Size must be power of 2, and
	124	* region start must be aligned to the region size
	125	*/
	126	if (phys_offset != 0)
	127	pr_info("PHYS_OFFSET != 0 => MPU Region size constrained by alignment requirements\n");
	128
	129	/*
	130	* Maximum aligned region might overflow phys_addr_t if phys_offset is
	131	* 0. Hence we keep everything below 4G until we take the smaller of
	132	* the aligned_region_size and rounded_mem_size, one of which is
	133	* guaranteed to be smaller than the maximum physical address.
	134	*/
	135	aligned_region_size = (phys_offset - 1) ^ (phys_offset);
	136	/* Find the max power-of-two sized region that fits inside our bank */
1c2f87c2	137	rounded_mem_size = (1 << __fls(specified_mem_size)) - 1;
5ad7dcbe JA	138
	139	/* The actual region size is the smaller of the two */
	140	aligned_region_size = aligned_region_size < rounded_mem_size
	141	? aligned_region_size + 1
	142	: rounded_mem_size + 1;
	143
1c2f87c2 LA	144	if (aligned_region_size != specified_mem_size) {
	145	pr_warn("Truncating memory from %pa to %pa (MPU region constraints)",
	146	&specified_mem_size, &aligned_region_size);
	147	memblock_remove(mem_start + aligned_region_size,
695665b0	148	specified_mem_size - aligned_region_size);
1c2f87c2 LA	149
	150	mem_end = mem_start + aligned_region_size;
	151	}
5ad7dcbe	152
1c2f87c2 LA	153	pr_debug("MPU Region from %pa size %pa (end %pa))\n",
1c2f87c2 LA	154	&phys_offset, &aligned_region_size, &mem_end);
5ad7dcbe JA	155
	156	}
	157
	158	static int mpu_present(void)
	159	{
	160	return ((read_cpuid_ext(CPUID_EXT_MMFR0) & MMFR0_PMSA) == MMFR0_PMSAv7);
	161	}
	162
	163	static int mpu_max_regions(void)
	164	{
	165	/*
	166	* We don't support a different number of I/D side regions so if we
	167	* have separate instruction and data memory maps then return
	168	* whichever side has a smaller number of supported regions.
	169	*/
	170	u32 dregions, iregions, mpuir;
	171	mpuir = read_cpuid(CPUID_MPUIR);
	172
	173	dregions = iregions = (mpuir & MPUIR_DREGION_SZMASK) >> MPUIR_DREGION;
	174
	175	/* Check for separate d-side and i-side memory maps */
	176	if (mpuir & MPUIR_nU)
	177	iregions = (mpuir & MPUIR_IREGION_SZMASK) >> MPUIR_IREGION;
	178
	179	/* Use the smallest of the two maxima */
	180	return min(dregions, iregions);
	181	}
	182
	183	static int mpu_iside_independent(void)
	184	{
	185	/* MPUIR.nU specifies whether there is not a unified memory map */
	186	return read_cpuid(CPUID_MPUIR) & MPUIR_nU;
	187	}
	188
	189	static int mpu_min_region_order(void)
	190	{
	191	u32 drbar_result, irbar_result;
	192	/* We've kept a region free for this probing */
	193	rgnr_write(MPU_PROBE_REGION);
	194	isb();
	195	/*
	196	* As per ARM ARM, write 0xFFFFFFFC to DRBAR to find the minimum
	197	* region order
	198	*/
	199	drbar_write(0xFFFFFFFC);
	200	drbar_result = irbar_result = drbar_read();
	201	drbar_write(0x0);
	202	/* If the MPU is non-unified, we use the larger of the two minima*/
	203	if (mpu_iside_independent()) {
	204	irbar_write(0xFFFFFFFC);
	205	irbar_result = irbar_read();
	206	irbar_write(0x0);
	207	}
	208	isb(); /* Ensure that MPU region operations have completed */
	209	/* Return whichever result is larger */
	210	return __ffs(max(drbar_result, irbar_result));
	211	}
	212
	213	static int mpu_setup_region(unsigned int number, phys_addr_t start,
	214	unsigned int size_order, unsigned int properties)
	215	{
	216	u32 size_data;
	217
	218	/* We kept a region free for probing resolution of MPU regions*/
219	if (number > mpu_max_regions() \|\| number == MPU_PROBE_REGION)
220	return -ENOENT;
221
222	if (size_order > 32)
223	return -ENOMEM;
224
225	if (size_order < mpu_min_region_order())
226	return -ENOMEM;
227
228	/* Writing N to bits 5:1 (RSR_SZ) specifies region size 2^N+1 */
229	size_data = ((size_order - 1) << MPU_RSR_SZ) \| 1 << MPU_RSR_EN;
230
231	dsb(); /* Ensure all previous data accesses occur with old mappings */
232	rgnr_write(number);
233	isb();
234	drbar_write(start);
235	dracr_write(properties);
236	isb(); /* Propagate properties before enabling region */
237	drsr_write(size_data);
238
239	/* Check for independent I-side registers */
240	if (mpu_iside_independent()) {
241	irbar_write(start);
242	iracr_write(properties);
243	isb();
244	irsr_write(size_data);
245	}
246	isb();
247
248	/* Store region info (we treat i/d side the same, so only store d) */
249	mpu_rgn_info.rgns[number].dracr = properties;
250	mpu_rgn_info.rgns[number].drbar = start;
251	mpu_rgn_info.rgns[number].drsr = size_data;
252	return 0;
253	}
254
255	/*
256	* Set up default MPU regions, doing nothing if there is no MPU
257	*/
258	void __init mpu_setup(void)
259	{
260	int region_err;
261	if (!mpu_present())
262	return;
263
264	region_err = mpu_setup_region(MPU_RAM_REGION, PHYS_OFFSET,
695665b0	265	ilog2(memblock.memory.regions[0].size),
5ad7dcbe JA	266	MPU_AP_PL1RW_PL0RW \| MPU_RGN_NORMAL);
	267	if (region_err) {
	268	panic("MPU region initialization failure! %d", region_err);
	269	} else {
	270	pr_info("Using ARMv7 PMSA Compliant MPU. "
	271	"Region independence: %s, Max regions: %d\n",
	272	mpu_iside_independent() ? "Yes" : "No",
	273	mpu_max_regions());
	274	}
	275	}
9a271567 JA	276	#else
	277	static void sanity_check_meminfo_mpu(void) {}
	278	static void __init mpu_setup(void) {}
5ad7dcbe JA	279	#endif /* CONFIG_ARM_MPU */
5ad7dcbe JA	280
2778f620	281	void __init arm_mm_memblock_reserve(void)
d111e8f9	282	{
55bdd694	283	#ifndef CONFIG_CPU_V7M
d111e8f9 RK	284	/*
	285	* Register the exception vector page.
	286	* some architectures which the DRAM is the exception vector to trap,
	287	* alloc_page breaks with error, although it is not NULL, but "0."
	288	*/
5b526bd9	289	memblock_reserve(CONFIG_VECTORS_BASE, 2 * PAGE_SIZE);
55bdd694 CM	290	#else /* ifndef CONFIG_CPU_V7M */
	291	/*
	292	* There is no dedicated vector page on V7-M. So nothing needs to be
	293	* reserved here.
	294	*/
	295	#endif
d111e8f9 RK	296	}
d111e8f9 RK	297
0371d3f7 RK	298	void __init sanity_check_meminfo(void)
0371d3f7 RK	299	{
9a271567 JA	300	phys_addr_t end;
9a271567 JA	301	sanity_check_meminfo_mpu();
1c2f87c2	302	end = memblock_end_of_DRAM();
55a8173c	303	high_memory = __va(end - 1) + 1;
6980c3e2	304	memblock_set_current_limit(end);
0371d3f7 RK	305	}
0371d3f7 RK	306
d111e8f9 RK	307	/*
	308	* paging_init() sets up the page tables, initialises the zone memory
	309	* maps, and sets up the zero page, bad page and bad page tables.
	310	*/
ff69a4c8	311	void __init paging_init(const struct machine_desc *mdesc)
d111e8f9	312	{
6b8e5c91	313	early_trap_init((void *)CONFIG_VECTORS_BASE);
9a271567	314	mpu_setup();
8d717a52	315	bootmem_init();
d111e8f9 RK	316	}
d111e8f9 RK	317
80878d6c RK	318	/*
	319	* We don't need to do anything here for nommu machines.
	320	*/
5aafec15	321	void setup_mm_for_reboot(void)
80878d6c RK	322	{
	323	}
	324
e6b1b38c RK	325	void flush_dcache_page(struct page *page)
e6b1b38c RK	326	{
2c9b9c84	327	__cpuc_flush_dcache_area(page_address(page), PAGE_SIZE);
e6b1b38c	328	}
3e361225	329	EXPORT_SYMBOL(flush_dcache_page);
e6b1b38c	330
63384fd0 SB	331	void flush_kernel_dcache_page(struct page *page)
	332	{
	333	__cpuc_flush_dcache_area(page_address(page), PAGE_SIZE);
	334	}
	335	EXPORT_SYMBOL(flush_kernel_dcache_page);
	336
b5a07faa CM	337	void copy_to_user_page(struct vm_area_struct vma, struct page page,
	338	unsigned long uaddr, void dst, const void src,
	339	unsigned long len)
	340	{
	341	memcpy(dst, src, len);
	342	if (vma->vm_flags & VM_EXEC)
	343	__cpuc_coherent_user_range(uaddr, uaddr + len);
	344	}
	345
3603ab2b RK	346	void __iomem *__arm_ioremap_pfn(unsigned long pfn, unsigned long offset,
3603ab2b RK	347	size_t size, unsigned int mtype)
5924486d RK	348	{
	349	if (pfn >= (0x100000000ULL >> PAGE_SHIFT))
	350	return NULL;
	351	return (void __iomem *) (offset + (pfn << PAGE_SHIFT));
	352	}
3603ab2b	353	EXPORT_SYMBOL(__arm_ioremap_pfn);
5924486d	354
20a1080d RK	355	void __iomem *__arm_ioremap_caller(phys_addr_t phys_addr, size_t size,
20a1080d RK	356	unsigned int mtype, void *caller)
31aa8fd6	357	{
20a1080d	358	return (void __iomem *)phys_addr;
31aa8fd6 RK	359	}
31aa8fd6 RK	360
20a1080d RK	361	void __iomem * (arch_ioremap_caller)(phys_addr_t, size_t, unsigned int, void );
	362
	363	void __iomem *ioremap(resource_size_t res_cookie, size_t size)
5924486d	364	{
20a1080d RK	365	return __arm_ioremap_caller(res_cookie, size, MT_DEVICE,
20a1080d RK	366	__builtin_return_address(0));
5924486d	367	}
20a1080d	368	EXPORT_SYMBOL(ioremap);
5924486d	369
20a1080d RK	370	void __iomem *ioremap_cache(resource_size_t res_cookie, size_t size)
	371	{
	372	return __arm_ioremap_caller(res_cookie, size, MT_DEVICE_CACHED,
	373	__builtin_return_address(0));
	374	}
	375	EXPORT_SYMBOL(ioremap_cache);
8a2b6255	376
20a1080d RK	377	void __iomem *ioremap_wc(resource_size_t res_cookie, size_t size)
	378	{
	379	return __arm_ioremap_caller(res_cookie, size, MT_DEVICE_WC,
	380	__builtin_return_address(0));
	381	}
	382	EXPORT_SYMBOL(ioremap_wc);
	383
	384	void __iounmap(volatile void __iomem *addr)
31aa8fd6	385	{
31aa8fd6	386	}
20a1080d	387	EXPORT_SYMBOL(__iounmap);
31aa8fd6	388
8a2b6255 RH	389	void (arch_iounmap)(volatile void __iomem );
8a2b6255 RH	390
20a1080d	391	void iounmap(volatile void __iomem *addr)
5924486d RK	392	{
5924486d RK	393	}
20a1080d	394	EXPORT_SYMBOL(iounmap);