projects / deliverable / linux.git / blame
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|---|---|---|
| 80ff0fd3 DD |
1 | /***********************license start*************** |
| 2 | * Author: Cavium Networks | |
| 3 | * | |
| 4 | * Contact: support@caviumnetworks.com | |
| 5 | * This file is part of the OCTEON SDK | |
| 6 | * | |
| 7 | * Copyright (c) 2003-2009 Cavium Networks | |
| 8 | * | |
| 9 | * This file is free software; you can redistribute it and/or modify | |
| 10 | * it under the terms of the GNU General Public License, Version 2, as | |
| 11 | * published by the Free Software Foundation. | |
| 12 | * | |
| 13 | * This file is distributed in the hope that it will be useful, but | |
| 14 | * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty | |
| 15 | * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or | |
| 16 | * NONINFRINGEMENT. See the GNU General Public License for more | |
| 17 | * details. | |
| 18 | * | |
| 19 | * You should have received a copy of the GNU General Public License | |
| 20 | * along with this file; if not, write to the Free Software | |
| 21 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA | |
| 22 | * or visit http://www.gnu.org/licenses/. | |
| 23 | * | |
| 24 | * This file may also be available under a different license from Cavium. | |
| 25 | * Contact Cavium Networks for more information | |
| 26 | ***********************license end**************************************/ | |
| 27 | ||
| 28 | /* | |
| 29 | * | |
| 30 | * Automatically generated functions useful for enabling | |
| 31 | * and decoding RSL_INT_BLOCKS interrupts. | |
| 32 | * | |
| 33 | */ | |
| 34 | ||
| 35 | #include <asm/octeon/octeon.h> | |
| 36 | ||
| af866496 DD |
37 | #include <asm/octeon/cvmx-gmxx-defs.h> |
| 38 | #include <asm/octeon/cvmx-pcsx-defs.h> | |
| 39 | #include <asm/octeon/cvmx-pcsxx-defs.h> | |
| 40 | #include <asm/octeon/cvmx-spxx-defs.h> | |
| 41 | #include <asm/octeon/cvmx-stxx-defs.h> | |
| 80ff0fd3 DD |
42 | |
| 43 | #ifndef PRINT_ERROR | |
| 44 | #define PRINT_ERROR(format, ...) | |
| 45 | #endif | |
| 46 | ||
| 47 | ||
| 48 | /** | |
| 49 | * __cvmx_interrupt_gmxx_rxx_int_en_enable enables all interrupt bits in cvmx_gmxx_rxx_int_en_t | |
| 50 | */ | |
| 51 | void __cvmx_interrupt_gmxx_rxx_int_en_enable(int index, int block) | |
| 52 | { | |
| 53 | union cvmx_gmxx_rxx_int_en gmx_rx_int_en; | |
| 54 | cvmx_write_csr(CVMX_GMXX_RXX_INT_REG(index, block), | |
| 55 | cvmx_read_csr(CVMX_GMXX_RXX_INT_REG(index, block))); | |
| 56 | gmx_rx_int_en.u64 = 0; | |
| 57 | if (OCTEON_IS_MODEL(OCTEON_CN56XX)) { | |
| 58 | /* Skipping gmx_rx_int_en.s.reserved_29_63 */ | |
| 59 | gmx_rx_int_en.s.hg2cc = 1; | |
| 60 | gmx_rx_int_en.s.hg2fld = 1; | |
| 61 | gmx_rx_int_en.s.undat = 1; | |
| 62 | gmx_rx_int_en.s.uneop = 1; | |
| 63 | gmx_rx_int_en.s.unsop = 1; | |
| 64 | gmx_rx_int_en.s.bad_term = 1; | |
| 65 | gmx_rx_int_en.s.bad_seq = 1; | |
| 66 | gmx_rx_int_en.s.rem_fault = 1; | |
| 67 | gmx_rx_int_en.s.loc_fault = 1; | |
| 68 | gmx_rx_int_en.s.pause_drp = 1; | |
| 69 | /* Skipping gmx_rx_int_en.s.reserved_16_18 */ | |
| 70 | /*gmx_rx_int_en.s.ifgerr = 1; */ | |
| 92a76f6d | 71 | /*gmx_rx_int_en.s.coldet = 1; // Collision detect */ |
| 80ff0fd3 DD |
72 | /*gmx_rx_int_en.s.falerr = 1; // False carrier error or extend error after slottime */ |
| 73 | /*gmx_rx_int_en.s.rsverr = 1; // RGMII reserved opcodes */ | |
| 74 | /*gmx_rx_int_en.s.pcterr = 1; // Bad Preamble / Protocol */ | |
| 75 | gmx_rx_int_en.s.ovrerr = 1; | |
| 76 | /* Skipping gmx_rx_int_en.s.reserved_9_9 */ | |
| 77 | gmx_rx_int_en.s.skperr = 1; | |
| 78 | gmx_rx_int_en.s.rcverr = 1; | |
| 79 | /* Skipping gmx_rx_int_en.s.reserved_5_6 */ | |
| 80 | /*gmx_rx_int_en.s.fcserr = 1; // FCS errors are handled when we get work */ | |
| 81 | gmx_rx_int_en.s.jabber = 1; | |
| 82 | /* Skipping gmx_rx_int_en.s.reserved_2_2 */ | |
| 83 | gmx_rx_int_en.s.carext = 1; | |
| 84 | /* Skipping gmx_rx_int_en.s.reserved_0_0 */ | |
| 85 | } | |
| 86 | if (OCTEON_IS_MODEL(OCTEON_CN30XX)) { | |
| 87 | /* Skipping gmx_rx_int_en.s.reserved_19_63 */ | |
| 88 | /*gmx_rx_int_en.s.phy_dupx = 1; */ | |
| 89 | /*gmx_rx_int_en.s.phy_spd = 1; */ | |
| 90 | /*gmx_rx_int_en.s.phy_link = 1; */ | |
| 91 | /*gmx_rx_int_en.s.ifgerr = 1; */ | |
| 92a76f6d | 92 | /*gmx_rx_int_en.s.coldet = 1; // Collision detect */ |
| 80ff0fd3 DD |
93 | /*gmx_rx_int_en.s.falerr = 1; // False carrier error or extend error after slottime */ |
| 94 | /*gmx_rx_int_en.s.rsverr = 1; // RGMII reserved opcodes */ | |
| 95 | /*gmx_rx_int_en.s.pcterr = 1; // Bad Preamble / Protocol */ | |
| 96 | gmx_rx_int_en.s.ovrerr = 1; | |
| 97 | gmx_rx_int_en.s.niberr = 1; | |
| 98 | gmx_rx_int_en.s.skperr = 1; | |
| 99 | gmx_rx_int_en.s.rcverr = 1; | |
| 100 | /*gmx_rx_int_en.s.lenerr = 1; // Length errors are handled when we get work */ | |
| 101 | gmx_rx_int_en.s.alnerr = 1; | |
| 102 | /*gmx_rx_int_en.s.fcserr = 1; // FCS errors are handled when we get work */ | |
| 103 | gmx_rx_int_en.s.jabber = 1; | |
| 104 | gmx_rx_int_en.s.maxerr = 1; | |
| 105 | gmx_rx_int_en.s.carext = 1; | |
| 106 | gmx_rx_int_en.s.minerr = 1; | |
| 107 | } | |
| 108 | if (OCTEON_IS_MODEL(OCTEON_CN50XX)) { | |
| 109 | /* Skipping gmx_rx_int_en.s.reserved_20_63 */ | |
| 110 | gmx_rx_int_en.s.pause_drp = 1; | |
| 111 | /*gmx_rx_int_en.s.phy_dupx = 1; */ | |
| 112 | /*gmx_rx_int_en.s.phy_spd = 1; */ | |
| 113 | /*gmx_rx_int_en.s.phy_link = 1; */ | |
| 114 | /*gmx_rx_int_en.s.ifgerr = 1; */ | |
| 92a76f6d | 115 | /*gmx_rx_int_en.s.coldet = 1; // Collision detect */ |
| 80ff0fd3 DD |
116 | /*gmx_rx_int_en.s.falerr = 1; // False carrier error or extend error after slottime */ |
| 117 | /*gmx_rx_int_en.s.rsverr = 1; // RGMII reserved opcodes */ | |
| 118 | /*gmx_rx_int_en.s.pcterr = 1; // Bad Preamble / Protocol */ | |
| 119 | gmx_rx_int_en.s.ovrerr = 1; | |
| 120 | gmx_rx_int_en.s.niberr = 1; | |
| 121 | gmx_rx_int_en.s.skperr = 1; | |
| 122 | gmx_rx_int_en.s.rcverr = 1; | |
| 123 | /* Skipping gmx_rx_int_en.s.reserved_6_6 */ | |
| 124 | gmx_rx_int_en.s.alnerr = 1; | |
| 125 | /*gmx_rx_int_en.s.fcserr = 1; // FCS errors are handled when we get work */ | |
| 126 | gmx_rx_int_en.s.jabber = 1; | |
| 127 | /* Skipping gmx_rx_int_en.s.reserved_2_2 */ | |
| 128 | gmx_rx_int_en.s.carext = 1; | |
| 129 | /* Skipping gmx_rx_int_en.s.reserved_0_0 */ | |
| 130 | } | |
| 131 | if (OCTEON_IS_MODEL(OCTEON_CN38XX)) { | |
| 132 | /* Skipping gmx_rx_int_en.s.reserved_19_63 */ | |
| 133 | /*gmx_rx_int_en.s.phy_dupx = 1; */ | |
| 134 | /*gmx_rx_int_en.s.phy_spd = 1; */ | |
| 135 | /*gmx_rx_int_en.s.phy_link = 1; */ | |
| 136 | /*gmx_rx_int_en.s.ifgerr = 1; */ | |
| 92a76f6d | 137 | /*gmx_rx_int_en.s.coldet = 1; // Collision detect */ |
| 80ff0fd3 DD |
138 | /*gmx_rx_int_en.s.falerr = 1; // False carrier error or extend error after slottime */ |
| 139 | /*gmx_rx_int_en.s.rsverr = 1; // RGMII reserved opcodes */ | |
| 140 | /*gmx_rx_int_en.s.pcterr = 1; // Bad Preamble / Protocol */ | |
| 141 | gmx_rx_int_en.s.ovrerr = 1; | |
| 142 | gmx_rx_int_en.s.niberr = 1; | |
| 143 | gmx_rx_int_en.s.skperr = 1; | |
| 144 | gmx_rx_int_en.s.rcverr = 1; | |
| 145 | /*gmx_rx_int_en.s.lenerr = 1; // Length errors are handled when we get work */ | |
| 146 | gmx_rx_int_en.s.alnerr = 1; | |
| 147 | /*gmx_rx_int_en.s.fcserr = 1; // FCS errors are handled when we get work */ | |
| 148 | gmx_rx_int_en.s.jabber = 1; | |
| 149 | gmx_rx_int_en.s.maxerr = 1; | |
| 150 | gmx_rx_int_en.s.carext = 1; | |
| 151 | gmx_rx_int_en.s.minerr = 1; | |
| 152 | } | |
| 153 | if (OCTEON_IS_MODEL(OCTEON_CN31XX)) { | |
| 154 | /* Skipping gmx_rx_int_en.s.reserved_19_63 */ | |
| 155 | /*gmx_rx_int_en.s.phy_dupx = 1; */ | |
| 156 | /*gmx_rx_int_en.s.phy_spd = 1; */ | |
| 157 | /*gmx_rx_int_en.s.phy_link = 1; */ | |
| 158 | /*gmx_rx_int_en.s.ifgerr = 1; */ | |
| 92a76f6d | 159 | /*gmx_rx_int_en.s.coldet = 1; // Collision detect */ |
| 80ff0fd3 DD |
160 | /*gmx_rx_int_en.s.falerr = 1; // False carrier error or extend error after slottime */ |
| 161 | /*gmx_rx_int_en.s.rsverr = 1; // RGMII reserved opcodes */ | |
| 162 | /*gmx_rx_int_en.s.pcterr = 1; // Bad Preamble / Protocol */ | |
| 163 | gmx_rx_int_en.s.ovrerr = 1; | |
| 164 | gmx_rx_int_en.s.niberr = 1; | |
| 165 | gmx_rx_int_en.s.skperr = 1; | |
| 166 | gmx_rx_int_en.s.rcverr = 1; | |
| 167 | /*gmx_rx_int_en.s.lenerr = 1; // Length errors are handled when we get work */ | |
| 168 | gmx_rx_int_en.s.alnerr = 1; | |
| 169 | /*gmx_rx_int_en.s.fcserr = 1; // FCS errors are handled when we get work */ | |
| 170 | gmx_rx_int_en.s.jabber = 1; | |
| 171 | gmx_rx_int_en.s.maxerr = 1; | |
| 172 | gmx_rx_int_en.s.carext = 1; | |
| 173 | gmx_rx_int_en.s.minerr = 1; | |
| 174 | } | |
| 175 | if (OCTEON_IS_MODEL(OCTEON_CN58XX)) { | |
| 176 | /* Skipping gmx_rx_int_en.s.reserved_20_63 */ | |
| 177 | gmx_rx_int_en.s.pause_drp = 1; | |
| 178 | /*gmx_rx_int_en.s.phy_dupx = 1; */ | |
| 179 | /*gmx_rx_int_en.s.phy_spd = 1; */ | |
| 180 | /*gmx_rx_int_en.s.phy_link = 1; */ | |
| 181 | /*gmx_rx_int_en.s.ifgerr = 1; */ | |
| 92a76f6d | 182 | /*gmx_rx_int_en.s.coldet = 1; // Collision detect */ |
| 80ff0fd3 DD |
183 | /*gmx_rx_int_en.s.falerr = 1; // False carrier error or extend error after slottime */ |
| 184 | /*gmx_rx_int_en.s.rsverr = 1; // RGMII reserved opcodes */ | |
| 185 | /*gmx_rx_int_en.s.pcterr = 1; // Bad Preamble / Protocol */ | |
| 186 | gmx_rx_int_en.s.ovrerr = 1; | |
| 187 | gmx_rx_int_en.s.niberr = 1; | |
| 188 | gmx_rx_int_en.s.skperr = 1; | |
| 189 | gmx_rx_int_en.s.rcverr = 1; | |
| 190 | /*gmx_rx_int_en.s.lenerr = 1; // Length errors are handled when we get work */ | |
| 191 | gmx_rx_int_en.s.alnerr = 1; | |
| 192 | /*gmx_rx_int_en.s.fcserr = 1; // FCS errors are handled when we get work */ | |
| 193 | gmx_rx_int_en.s.jabber = 1; | |
| 194 | gmx_rx_int_en.s.maxerr = 1; | |
| 195 | gmx_rx_int_en.s.carext = 1; | |
| 196 | gmx_rx_int_en.s.minerr = 1; | |
| 197 | } | |
| 198 | if (OCTEON_IS_MODEL(OCTEON_CN52XX)) { | |
| 199 | /* Skipping gmx_rx_int_en.s.reserved_29_63 */ | |
| 200 | gmx_rx_int_en.s.hg2cc = 1; | |
| 201 | gmx_rx_int_en.s.hg2fld = 1; | |
| 202 | gmx_rx_int_en.s.undat = 1; | |
| 203 | gmx_rx_int_en.s.uneop = 1; | |
| 204 | gmx_rx_int_en.s.unsop = 1; | |
| 205 | gmx_rx_int_en.s.bad_term = 1; | |
| 206 | gmx_rx_int_en.s.bad_seq = 0; | |
| 207 | gmx_rx_int_en.s.rem_fault = 1; | |
| 208 | gmx_rx_int_en.s.loc_fault = 0; | |
| 209 | gmx_rx_int_en.s.pause_drp = 1; | |
| 210 | /* Skipping gmx_rx_int_en.s.reserved_16_18 */ | |
| 211 | /*gmx_rx_int_en.s.ifgerr = 1; */ | |
| 92a76f6d | 212 | /*gmx_rx_int_en.s.coldet = 1; // Collision detect */ |
| 80ff0fd3 DD |
213 | /*gmx_rx_int_en.s.falerr = 1; // False carrier error or extend error after slottime */ |
| 214 | /*gmx_rx_int_en.s.rsverr = 1; // RGMII reserved opcodes */ | |
| 215 | /*gmx_rx_int_en.s.pcterr = 1; // Bad Preamble / Protocol */ | |
| 216 | gmx_rx_int_en.s.ovrerr = 1; | |
| 217 | /* Skipping gmx_rx_int_en.s.reserved_9_9 */ | |
| 218 | gmx_rx_int_en.s.skperr = 1; | |
| 219 | gmx_rx_int_en.s.rcverr = 1; | |
| 220 | /* Skipping gmx_rx_int_en.s.reserved_5_6 */ | |
| 221 | /*gmx_rx_int_en.s.fcserr = 1; // FCS errors are handled when we get work */ | |
| 222 | gmx_rx_int_en.s.jabber = 1; | |
| 223 | /* Skipping gmx_rx_int_en.s.reserved_2_2 */ | |
| 224 | gmx_rx_int_en.s.carext = 1; | |
| 225 | /* Skipping gmx_rx_int_en.s.reserved_0_0 */ | |
| 226 | } | |
| 227 | cvmx_write_csr(CVMX_GMXX_RXX_INT_EN(index, block), gmx_rx_int_en.u64); | |
| 228 | } | |
| 229 | /** | |
| 230 | * __cvmx_interrupt_pcsx_intx_en_reg_enable enables all interrupt bits in cvmx_pcsx_intx_en_reg_t | |
| 231 | */ | |
| 232 | void __cvmx_interrupt_pcsx_intx_en_reg_enable(int index, int block) | |
| 233 | { | |
| 234 | union cvmx_pcsx_intx_en_reg pcs_int_en_reg; | |
| 235 | cvmx_write_csr(CVMX_PCSX_INTX_REG(index, block), | |
| 236 | cvmx_read_csr(CVMX_PCSX_INTX_REG(index, block))); | |
| 237 | pcs_int_en_reg.u64 = 0; | |
| 238 | if (OCTEON_IS_MODEL(OCTEON_CN56XX)) { | |
| 239 | /* Skipping pcs_int_en_reg.s.reserved_12_63 */ | |
| 240 | /*pcs_int_en_reg.s.dup = 1; // This happens during normal operation */ | |
| 241 | pcs_int_en_reg.s.sync_bad_en = 1; | |
| 242 | pcs_int_en_reg.s.an_bad_en = 1; | |
| 243 | pcs_int_en_reg.s.rxlock_en = 1; | |
| 244 | pcs_int_en_reg.s.rxbad_en = 1; | |
| 245 | /*pcs_int_en_reg.s.rxerr_en = 1; // This happens during normal operation */ | |
| 246 | pcs_int_en_reg.s.txbad_en = 1; | |
| 247 | pcs_int_en_reg.s.txfifo_en = 1; | |
| 248 | pcs_int_en_reg.s.txfifu_en = 1; | |
| 249 | pcs_int_en_reg.s.an_err_en = 1; | |
| 250 | /*pcs_int_en_reg.s.xmit_en = 1; // This happens during normal operation */ | |
| 251 | /*pcs_int_en_reg.s.lnkspd_en = 1; // This happens during normal operation */ | |
| 252 | } | |
| 253 | if (OCTEON_IS_MODEL(OCTEON_CN52XX)) { | |
| 254 | /* Skipping pcs_int_en_reg.s.reserved_12_63 */ | |
| 255 | /*pcs_int_en_reg.s.dup = 1; // This happens during normal operation */ | |
| 256 | pcs_int_en_reg.s.sync_bad_en = 1; | |
| 257 | pcs_int_en_reg.s.an_bad_en = 1; | |
| 258 | pcs_int_en_reg.s.rxlock_en = 1; | |
| 259 | pcs_int_en_reg.s.rxbad_en = 1; | |
| 260 | /*pcs_int_en_reg.s.rxerr_en = 1; // This happens during normal operation */ | |
| 261 | pcs_int_en_reg.s.txbad_en = 1; | |
| 262 | pcs_int_en_reg.s.txfifo_en = 1; | |
| 263 | pcs_int_en_reg.s.txfifu_en = 1; | |
| 264 | pcs_int_en_reg.s.an_err_en = 1; | |
| 265 | /*pcs_int_en_reg.s.xmit_en = 1; // This happens during normal operation */ | |
| 266 | /*pcs_int_en_reg.s.lnkspd_en = 1; // This happens during normal operation */ | |
| 267 | } | |
| 268 | cvmx_write_csr(CVMX_PCSX_INTX_EN_REG(index, block), pcs_int_en_reg.u64); | |
| 269 | } | |
| 270 | /** | |
| 271 | * __cvmx_interrupt_pcsxx_int_en_reg_enable enables all interrupt bits in cvmx_pcsxx_int_en_reg_t | |
| 272 | */ | |
| 273 | void __cvmx_interrupt_pcsxx_int_en_reg_enable(int index) | |
| 274 | { | |
| 275 | union cvmx_pcsxx_int_en_reg pcsx_int_en_reg; | |
| 276 | cvmx_write_csr(CVMX_PCSXX_INT_REG(index), | |
| 277 | cvmx_read_csr(CVMX_PCSXX_INT_REG(index))); | |
| 278 | pcsx_int_en_reg.u64 = 0; | |
| 279 | if (OCTEON_IS_MODEL(OCTEON_CN56XX)) { | |
| 280 | /* Skipping pcsx_int_en_reg.s.reserved_6_63 */ | |
| 281 | pcsx_int_en_reg.s.algnlos_en = 1; | |
| 282 | pcsx_int_en_reg.s.synlos_en = 1; | |
| 283 | pcsx_int_en_reg.s.bitlckls_en = 1; | |
| 284 | pcsx_int_en_reg.s.rxsynbad_en = 1; | |
| 285 | pcsx_int_en_reg.s.rxbad_en = 1; | |
| 286 | pcsx_int_en_reg.s.txflt_en = 1; | |
| 287 | } | |
| 288 | if (OCTEON_IS_MODEL(OCTEON_CN52XX)) { | |
| 289 | /* Skipping pcsx_int_en_reg.s.reserved_6_63 */ | |
| 290 | pcsx_int_en_reg.s.algnlos_en = 1; | |
| 291 | pcsx_int_en_reg.s.synlos_en = 1; | |
| 292 | pcsx_int_en_reg.s.bitlckls_en = 0; /* Happens if XAUI module is not installed */ | |
| 293 | pcsx_int_en_reg.s.rxsynbad_en = 1; | |
| 294 | pcsx_int_en_reg.s.rxbad_en = 1; | |
| 295 | pcsx_int_en_reg.s.txflt_en = 1; | |
| 296 | } | |
| 297 | cvmx_write_csr(CVMX_PCSXX_INT_EN_REG(index), pcsx_int_en_reg.u64); | |
| 298 | } | |
| 299 | ||
| 300 | /** | |
| 301 | * __cvmx_interrupt_spxx_int_msk_enable enables all interrupt bits in cvmx_spxx_int_msk_t | |
| 302 | */ | |
| 303 | void __cvmx_interrupt_spxx_int_msk_enable(int index) | |
| 304 | { | |
| 305 | union cvmx_spxx_int_msk spx_int_msk; | |
| 306 | cvmx_write_csr(CVMX_SPXX_INT_REG(index), | |
| 307 | cvmx_read_csr(CVMX_SPXX_INT_REG(index))); | |
| 308 | spx_int_msk.u64 = 0; | |
| 309 | if (OCTEON_IS_MODEL(OCTEON_CN38XX)) { | |
| 310 | /* Skipping spx_int_msk.s.reserved_12_63 */ | |
| 311 | spx_int_msk.s.calerr = 1; | |
| 312 | spx_int_msk.s.syncerr = 1; | |
| 313 | spx_int_msk.s.diperr = 1; | |
| 314 | spx_int_msk.s.tpaovr = 1; | |
| 315 | spx_int_msk.s.rsverr = 1; | |
| 316 | spx_int_msk.s.drwnng = 1; | |
| 317 | spx_int_msk.s.clserr = 1; | |
| 318 | spx_int_msk.s.spiovr = 1; | |
| 319 | /* Skipping spx_int_msk.s.reserved_2_3 */ | |
| 320 | spx_int_msk.s.abnorm = 1; | |
| 321 | spx_int_msk.s.prtnxa = 1; | |
| 322 | } | |
| 323 | if (OCTEON_IS_MODEL(OCTEON_CN58XX)) { | |
| 324 | /* Skipping spx_int_msk.s.reserved_12_63 */ | |
| 325 | spx_int_msk.s.calerr = 1; | |
| 326 | spx_int_msk.s.syncerr = 1; | |
| 327 | spx_int_msk.s.diperr = 1; | |
| 328 | spx_int_msk.s.tpaovr = 1; | |
| 329 | spx_int_msk.s.rsverr = 1; | |
| 330 | spx_int_msk.s.drwnng = 1; | |
| 331 | spx_int_msk.s.clserr = 1; | |
| 332 | spx_int_msk.s.spiovr = 1; | |
| 333 | /* Skipping spx_int_msk.s.reserved_2_3 */ | |
| 334 | spx_int_msk.s.abnorm = 1; | |
| 335 | spx_int_msk.s.prtnxa = 1; | |
| 336 | } | |
| 337 | cvmx_write_csr(CVMX_SPXX_INT_MSK(index), spx_int_msk.u64); | |
| 338 | } | |
| 339 | /** | |
| 340 | * __cvmx_interrupt_stxx_int_msk_enable enables all interrupt bits in cvmx_stxx_int_msk_t | |
| 341 | */ | |
| 342 | void __cvmx_interrupt_stxx_int_msk_enable(int index) | |
| 343 | { | |
| 344 | union cvmx_stxx_int_msk stx_int_msk; | |
| 345 | cvmx_write_csr(CVMX_STXX_INT_REG(index), | |
| 346 | cvmx_read_csr(CVMX_STXX_INT_REG(index))); | |
| 347 | stx_int_msk.u64 = 0; | |
| 348 | if (OCTEON_IS_MODEL(OCTEON_CN38XX)) { | |
| 349 | /* Skipping stx_int_msk.s.reserved_8_63 */ | |
| 350 | stx_int_msk.s.frmerr = 1; | |
| 351 | stx_int_msk.s.unxfrm = 1; | |
| 352 | stx_int_msk.s.nosync = 1; | |
| 353 | stx_int_msk.s.diperr = 1; | |
| 354 | stx_int_msk.s.datovr = 1; | |
| 355 | stx_int_msk.s.ovrbst = 1; | |
| 356 | stx_int_msk.s.calpar1 = 1; | |
| 357 | stx_int_msk.s.calpar0 = 1; | |
| 358 | } | |
| 359 | if (OCTEON_IS_MODEL(OCTEON_CN58XX)) { | |
| 360 | /* Skipping stx_int_msk.s.reserved_8_63 */ | |
| 361 | stx_int_msk.s.frmerr = 1; | |
| 362 | stx_int_msk.s.unxfrm = 1; | |
| 363 | stx_int_msk.s.nosync = 1; | |
| 364 | stx_int_msk.s.diperr = 1; | |
| 365 | stx_int_msk.s.datovr = 1; | |
| 366 | stx_int_msk.s.ovrbst = 1; | |
| 367 | stx_int_msk.s.calpar1 = 1; | |
| 368 | stx_int_msk.s.calpar0 = 1; | |
| 369 | } | |
| 370 | cvmx_write_csr(CVMX_STXX_INT_MSK(index), stx_int_msk.u64); | |
| 371 | } |