[deliverable/linux.git] / arch / mips / mti-malta / malta-setup.c

/*
 * Carsten Langgaard, carstenl@mips.com
 * Copyright (C) 2000 MIPS Technologies, Inc.  All rights reserved.
 * Copyright (C) 2008 Dmitri Vorobiev
 *
 *  This program is free software; you can distribute it and/or modify it
 *  under the terms of the GNU General Public License (Version 2) as
 *  published by the Free Software Foundation.
 *
 *  This program is distributed in the hope it will be useful, but WITHOUT
 *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
 *  for more details.
 *
 *  You should have received a copy of the GNU General Public License along
 *  with this program; if not, write to the Free Software Foundation, Inc.,
 *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
 */
#include <linux/cpu.h>
#include <linux/init.h>
#include <linux/sched.h>
#include <linux/ioport.h>
#include <linux/irq.h>
#include <linux/of_fdt.h>
#include <linux/pci.h>
#include <linux/screen_info.h>
#include <linux/time.h>

#include <asm/fw/fw.h>
#include <asm/mach-malta/malta-dtshim.h>
#include <asm/mips-cm.h>
#include <asm/mips-boards/generic.h>
#include <asm/mips-boards/malta.h>
#include <asm/mips-boards/maltaint.h>
#include <asm/dma.h>
#include <asm/prom.h>
#include <asm/traps.h>
#ifdef CONFIG_VT
#include <linux/console.h>
#endif

#define ROCIT_CONFIG_GEN0		0x1f403000
#define  ROCIT_CONFIG_GEN0_PCI_IOCU	BIT(7)

extern void malta_be_init(void);
extern int malta_be_handler(struct pt_regs *regs, int is_fixup);

static struct resource standard_io_resources[] = {
	{
		.name = "dma1",
		.start = 0x00,
		.end = 0x1f,
		.flags = IORESOURCE_BUSY
	},
	{
		.name = "timer",
		.start = 0x40,
		.end = 0x5f,
		.flags = IORESOURCE_BUSY
	},
	{
		.name = "keyboard",
		.start = 0x60,
		.end = 0x6f,
		.flags = IORESOURCE_BUSY
	},
	{
		.name = "dma page reg",
		.start = 0x80,
		.end = 0x8f,
		.flags = IORESOURCE_BUSY
	},
	{
		.name = "dma2",
		.start = 0xc0,
		.end = 0xdf,
		.flags = IORESOURCE_BUSY
	},
};

const char *get_system_type(void)
{
	return "MIPS Malta";
}

const char display_string[] = "	       LINUX ON MALTA	    ";

#ifdef CONFIG_BLK_DEV_FD
static void __init fd_activate(void)
{
	/*
	 * Activate Floppy Controller in the SMSC FDC37M817 Super I/O
	 * Controller.
	 * Done by YAMON 2.00 onwards
	 */
	/* Entering config state. */
	SMSC_WRITE(SMSC_CONFIG_ENTER, SMSC_CONFIG_REG);

	/* Activate floppy controller. */
	SMSC_WRITE(SMSC_CONFIG_DEVNUM, SMSC_CONFIG_REG);
	SMSC_WRITE(SMSC_CONFIG_DEVNUM_FLOPPY, SMSC_DATA_REG);
	SMSC_WRITE(SMSC_CONFIG_ACTIVATE, SMSC_CONFIG_REG);
	SMSC_WRITE(SMSC_CONFIG_ACTIVATE_ENABLE, SMSC_DATA_REG);

	/* Exit config state. */
	SMSC_WRITE(SMSC_CONFIG_EXIT, SMSC_CONFIG_REG);
}
#endif

static int __init plat_enable_iocoherency(void)
{
	int supported = 0;
	u32 cfg;

	if (mips_revision_sconid == MIPS_REVISION_SCON_BONITO) {
		if (BONITO_PCICACHECTRL & BONITO_PCICACHECTRL_CPUCOH_PRES) {
			BONITO_PCICACHECTRL |= BONITO_PCICACHECTRL_CPUCOH_EN;
			pr_info("Enabled Bonito CPU coherency\n");
			supported = 1;
		}
		if (strstr(fw_getcmdline(), "iobcuncached")) {
			BONITO_PCICACHECTRL &= ~BONITO_PCICACHECTRL_IOBCCOH_EN;
			BONITO_PCIMEMBASECFG = BONITO_PCIMEMBASECFG &
				~(BONITO_PCIMEMBASECFG_MEMBASE0_CACHED |
				  BONITO_PCIMEMBASECFG_MEMBASE1_CACHED);
			pr_info("Disabled Bonito IOBC coherency\n");
		} else {
			BONITO_PCICACHECTRL |= BONITO_PCICACHECTRL_IOBCCOH_EN;
			BONITO_PCIMEMBASECFG |=
				(BONITO_PCIMEMBASECFG_MEMBASE0_CACHED |
				 BONITO_PCIMEMBASECFG_MEMBASE1_CACHED);
			pr_info("Enabled Bonito IOBC coherency\n");
		}
	} else if (mips_cm_numiocu() != 0) {
		/* Nothing special needs to be done to enable coherency */
		pr_info("CMP IOCU detected\n");
		cfg = __raw_readl((u32 *)CKSEG1ADDR(ROCIT_CONFIG_GEN0));
		if (!(cfg & ROCIT_CONFIG_GEN0_PCI_IOCU)) {
			pr_crit("IOCU OPERATION DISABLED BY SWITCH - DEFAULTING TO SW IO COHERENCY\n");
			return 0;
		}
		supported = 1;
	}
	hw_coherentio = supported;
	return supported;
}

static void __init plat_setup_iocoherency(void)
{
#ifdef CONFIG_DMA_NONCOHERENT
	/*
	 * Kernel has been configured with software coherency
	 * but we might choose to turn it off and use hardware
	 * coherency instead.
	 */
	if (plat_enable_iocoherency()) {
		if (coherentio == 0)
			pr_info("Hardware DMA cache coherency disabled\n");
		else
			pr_info("Hardware DMA cache coherency enabled\n");
	} else {
		if (coherentio == 1)
			pr_info("Hardware DMA cache coherency unsupported, but enabled from command line!\n");
		else
			pr_info("Software DMA cache coherency enabled\n");
	}
#else
	if (!plat_enable_iocoherency())
		panic("Hardware DMA cache coherency not supported!");
#endif
}

static void __init pci_clock_check(void)
{
	unsigned int __iomem *jmpr_p =
		(unsigned int *) ioremap(MALTA_JMPRS_REG, sizeof(unsigned int));
	int jmpr = (__raw_readl(jmpr_p) >> 2) & 0x07;
	static const int pciclocks[] __initconst = {
		33, 20, 25, 30, 12, 16, 37, 10
	};
	int pciclock = pciclocks[jmpr];
	char *optptr, *argptr = fw_getcmdline();

	/*
	 * If user passed a pci_clock= option, don't tack on another one
	 */
	optptr = strstr(argptr, "pci_clock=");
	if (optptr && (optptr == argptr || optptr[-1] == ' '))
		return;

	if (pciclock != 33) {
		pr_warn("WARNING: PCI clock is %dMHz, setting pci_clock\n",
			pciclock);
		argptr += strlen(argptr);
		sprintf(argptr, " pci_clock=%d", pciclock);
		if (pciclock < 20 || pciclock > 66)
			pr_warn("WARNING: IDE timing calculations will be "
			        "incorrect\n");
	}
}

#if defined(CONFIG_VT) && defined(CONFIG_VGA_CONSOLE)
static void __init screen_info_setup(void)
{
	screen_info = (struct screen_info) {
		.orig_x = 0,
		.orig_y = 25,
		.ext_mem_k = 0,
		.orig_video_page = 0,
		.orig_video_mode = 0,
		.orig_video_cols = 80,
		.unused2 = 0,
		.orig_video_ega_bx = 0,
		.unused3 = 0,
		.orig_video_lines = 25,
		.orig_video_isVGA = VIDEO_TYPE_VGAC,
		.orig_video_points = 16
	};
}
#endif

static void __init bonito_quirks_setup(void)
{
	char *argptr;

	argptr = fw_getcmdline();
	if (strstr(argptr, "debug")) {
		BONITO_BONGENCFG |= BONITO_BONGENCFG_DEBUGMODE;
		pr_info("Enabled Bonito debug mode\n");
	} else
		BONITO_BONGENCFG &= ~BONITO_BONGENCFG_DEBUGMODE;

#ifdef CONFIG_DMA_COHERENT
	if (BONITO_PCICACHECTRL & BONITO_PCICACHECTRL_CPUCOH_PRES) {
		BONITO_PCICACHECTRL |= BONITO_PCICACHECTRL_CPUCOH_EN;
		pr_info("Enabled Bonito CPU coherency\n");

		argptr = fw_getcmdline();
		if (strstr(argptr, "iobcuncached")) {
			BONITO_PCICACHECTRL &= ~BONITO_PCICACHECTRL_IOBCCOH_EN;
			BONITO_PCIMEMBASECFG = BONITO_PCIMEMBASECFG &
				~(BONITO_PCIMEMBASECFG_MEMBASE0_CACHED |
					BONITO_PCIMEMBASECFG_MEMBASE1_CACHED);
			pr_info("Disabled Bonito IOBC coherency\n");
		} else {
			BONITO_PCICACHECTRL |= BONITO_PCICACHECTRL_IOBCCOH_EN;
			BONITO_PCIMEMBASECFG |=
				(BONITO_PCIMEMBASECFG_MEMBASE0_CACHED |
					BONITO_PCIMEMBASECFG_MEMBASE1_CACHED);
			pr_info("Enabled Bonito IOBC coherency\n");
		}
	} else
		panic("Hardware DMA cache coherency not supported");
#endif
}

void __init *plat_get_fdt(void)
{
	return (void *)__dtb_start;
}

void __init plat_mem_setup(void)
{
	unsigned int i;
	void *fdt = plat_get_fdt();

	fdt = malta_dt_shim(fdt);
	__dt_setup_arch(fdt);

	if (IS_ENABLED(CONFIG_EVA))
		/* EVA has already been configured in mach-malta/kernel-init.h */
		pr_info("Enhanced Virtual Addressing (EVA) activated\n");

	mips_pcibios_init();

	/* Request I/O space for devices used on the Malta board. */
	for (i = 0; i < ARRAY_SIZE(standard_io_resources); i++)
		request_resource(&ioport_resource, standard_io_resources+i);

	/*
	 * Enable DMA channel 4 (cascade channel) in the PIIX4 south bridge.
	 */
	enable_dma(4);

#ifdef CONFIG_DMA_COHERENT
	if (mips_revision_sconid != MIPS_REVISION_SCON_BONITO)
		panic("Hardware DMA cache coherency not supported");
#endif

	if (mips_revision_sconid == MIPS_REVISION_SCON_BONITO)
		bonito_quirks_setup();

	plat_setup_iocoherency();

	pci_clock_check();

#ifdef CONFIG_BLK_DEV_FD
	fd_activate();
#endif

#if defined(CONFIG_VT) && defined(CONFIG_VGA_CONSOLE)
	screen_info_setup();
#endif

	board_be_init = malta_be_init;
	board_be_handler = malta_be_handler;
}
Commit	Line	Data
1da177e4 LT	1	/*
	2	* Carsten Langgaard, carstenl@mips.com
	3	* Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved.
52d65cf8	4	* Copyright (C) 2008 Dmitri Vorobiev
1da177e4 LT	5	*
	6	* This program is free software; you can distribute it and/or modify it
	7	* under the terms of the GNU General Public License (Version 2) as
	8	* published by the Free Software Foundation.
	9	*
	10	* This program is distributed in the hope it will be useful, but WITHOUT
	11	* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	12	* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
	13	* for more details.
	14	*
	15	* You should have received a copy of the GNU General Public License along
	16	* with this program; if not, write to the Free Software Foundation, Inc.,
	17	* 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
	18	*/
54bf038e	19	#include <linux/cpu.h>
1da177e4 LT	20	#include <linux/init.h>
	21	#include <linux/sched.h>
	22	#include <linux/ioport.h>
54bf038e	23	#include <linux/irq.h>
e8823d26	24	#include <linux/of_fdt.h>
1da177e4	25	#include <linux/pci.h>
894673ee	26	#include <linux/screen_info.h>
54bf038e	27	#include <linux/time.h>
1da177e4	28
b431f09d	29	#include <asm/fw/fw.h>
e81a8c7d	30	#include <asm/mach-malta/malta-dtshim.h>
237036de	31	#include <asm/mips-cm.h>
1da177e4	32	#include <asm/mips-boards/generic.h>
1da177e4 LT	33	#include <asm/mips-boards/malta.h>
	34	#include <asm/mips-boards/maltaint.h>
	35	#include <asm/dma.h>
e8823d26	36	#include <asm/prom.h>
1da177e4 LT	37	#include <asm/traps.h>
	38	#ifdef CONFIG_VT
	39	#include <linux/console.h>
	40	#endif
	41
305723ab PB	42	#define ROCIT_CONFIG_GEN0 0x1f403000
	43	#define ROCIT_CONFIG_GEN0_PCI_IOCU BIT(7)
	44
39b8d525 RB	45	extern void malta_be_init(void);
	46	extern int malta_be_handler(struct pt_regs *regs, int is_fixup);
	47
52d65cf8	48	static struct resource standard_io_resources[] = {
4ca76513 DV	49	{
	50	.name = "dma1",
	51	.start = 0x00,
	52	.end = 0x1f,
	53	.flags = IORESOURCE_BUSY
	54	},
	55	{
	56	.name = "timer",
	57	.start = 0x40,
	58	.end = 0x5f,
	59	.flags = IORESOURCE_BUSY
	60	},
	61	{
	62	.name = "keyboard",
	63	.start = 0x60,
	64	.end = 0x6f,
	65	.flags = IORESOURCE_BUSY
	66	},
	67	{
	68	.name = "dma page reg",
	69	.start = 0x80,
	70	.end = 0x8f,
	71	.flags = IORESOURCE_BUSY
	72	},
	73	{
	74	.name = "dma2",
	75	.start = 0xc0,
	76	.end = 0xdf,
	77	.flags = IORESOURCE_BUSY
	78	},
1da177e4 LT	79	};
1da177e4 LT	80
1da177e4 LT	81	const char *get_system_type(void)
	82	{
	83	return "MIPS Malta";
	84	}
	85
70342287	86	const char display_string[] = " LINUX ON MALTA ";
79894c7b	87
1da177e4	88	#ifdef CONFIG_BLK_DEV_FD
ef7645cf	89	static void __init fd_activate(void)
1da177e4 LT	90	{
	91	/*
	92	* Activate Floppy Controller in the SMSC FDC37M817 Super I/O
	93	* Controller.
	94	* Done by YAMON 2.00 onwards
	95	*/
	96	/* Entering config state. */
	97	SMSC_WRITE(SMSC_CONFIG_ENTER, SMSC_CONFIG_REG);
	98
	99	/* Activate floppy controller. */
	100	SMSC_WRITE(SMSC_CONFIG_DEVNUM, SMSC_CONFIG_REG);
	101	SMSC_WRITE(SMSC_CONFIG_DEVNUM_FLOPPY, SMSC_DATA_REG);
	102	SMSC_WRITE(SMSC_CONFIG_ACTIVATE, SMSC_CONFIG_REG);
	103	SMSC_WRITE(SMSC_CONFIG_ACTIVATE_ENABLE, SMSC_DATA_REG);
	104
	105	/* Exit config state. */
	106	SMSC_WRITE(SMSC_CONFIG_EXIT, SMSC_CONFIG_REG);
	107	}
	108	#endif
	109
b6d92b4a SH	110	static int __init plat_enable_iocoherency(void)
	111	{
	112	int supported = 0;
305723ab PB	113	u32 cfg;
305723ab PB	114
b6d92b4a SH	115	if (mips_revision_sconid == MIPS_REVISION_SCON_BONITO) {
	116	if (BONITO_PCICACHECTRL & BONITO_PCICACHECTRL_CPUCOH_PRES) {
	117	BONITO_PCICACHECTRL \|= BONITO_PCICACHECTRL_CPUCOH_EN;
	118	pr_info("Enabled Bonito CPU coherency\n");
	119	supported = 1;
	120	}
	121	if (strstr(fw_getcmdline(), "iobcuncached")) {
	122	BONITO_PCICACHECTRL &= ~BONITO_PCICACHECTRL_IOBCCOH_EN;
	123	BONITO_PCIMEMBASECFG = BONITO_PCIMEMBASECFG &
	124	~(BONITO_PCIMEMBASECFG_MEMBASE0_CACHED \|
	125	BONITO_PCIMEMBASECFG_MEMBASE1_CACHED);
	126	pr_info("Disabled Bonito IOBC coherency\n");
	127	} else {
	128	BONITO_PCICACHECTRL \|= BONITO_PCICACHECTRL_IOBCCOH_EN;
	129	BONITO_PCIMEMBASECFG \|=
	130	(BONITO_PCIMEMBASECFG_MEMBASE0_CACHED \|
	131	BONITO_PCIMEMBASECFG_MEMBASE1_CACHED);
	132	pr_info("Enabled Bonito IOBC coherency\n");
	133	}
237036de	134	} else if (mips_cm_numiocu() != 0) {
b6d92b4a SH	135	/* Nothing special needs to be done to enable coherency */
b6d92b4a SH	136	pr_info("CMP IOCU detected\n");
305723ab PB	137	cfg = __raw_readl((u32 *)CKSEG1ADDR(ROCIT_CONFIG_GEN0));
305723ab PB	138	if (!(cfg & ROCIT_CONFIG_GEN0_PCI_IOCU)) {
b6d92b4a SH	139	pr_crit("IOCU OPERATION DISABLED BY SWITCH - DEFAULTING TO SW IO COHERENCY\n");
	140	return 0;
	141	}
	142	supported = 1;
	143	}
	144	hw_coherentio = supported;
	145	return supported;
	146	}
	147
	148	static void __init plat_setup_iocoherency(void)
	149	{
	150	#ifdef CONFIG_DMA_NONCOHERENT
	151	/*
	152	* Kernel has been configured with software coherency
	153	* but we might choose to turn it off and use hardware
	154	* coherency instead.
	155	*/
	156	if (plat_enable_iocoherency()) {
	157	if (coherentio == 0)
	158	pr_info("Hardware DMA cache coherency disabled\n");
	159	else
	160	pr_info("Hardware DMA cache coherency enabled\n");
	161	} else {
	162	if (coherentio == 1)
	163	pr_info("Hardware DMA cache coherency unsupported, but enabled from command line!\n");
	164	else
	165	pr_info("Software DMA cache coherency enabled\n");
	166	}
	167	#else
	168	if (!plat_enable_iocoherency())
	169	panic("Hardware DMA cache coherency not supported!");
	170	#endif
	171	}
	172
f3a4ce95 DV	173	static void __init pci_clock_check(void)
	174	{
	175	unsigned int __iomem *jmpr_p =
	176	(unsigned int *) ioremap(MALTA_JMPRS_REG, sizeof(unsigned int));
	177	int jmpr = (__raw_readl(jmpr_p) >> 2) & 0x07;
4a043d79	178	static const int pciclocks[] __initconst = {
f3a4ce95 DV	179	33, 20, 25, 30, 12, 16, 37, 10
	180	};
	181	int pciclock = pciclocks[jmpr];
a9dde288	182	char optptr, argptr = fw_getcmdline();
f3a4ce95	183
a9dde288 RB	184	/*
	185	* If user passed a pci_clock= option, don't tack on another one
	186	*/
	187	optptr = strstr(argptr, "pci_clock=");
	188	if (optptr && (optptr == argptr \|\| optptr[-1] == ' '))
	189	return;
	190
	191	if (pciclock != 33) {
	192	pr_warn("WARNING: PCI clock is %dMHz, setting pci_clock\n",
49bffbdc	193	pciclock);
f3a4ce95	194	argptr += strlen(argptr);
a9dde288	195	sprintf(argptr, " pci_clock=%d", pciclock);
f3a4ce95	196	if (pciclock < 20 \|\| pciclock > 66)
a9dde288 RB	197	pr_warn("WARNING: IDE timing calculations will be "
a9dde288 RB	198	"incorrect\n");
f3a4ce95 DV	199	}
f3a4ce95 DV	200	}
f3a4ce95	201
a382963e DV	202	#if defined(CONFIG_VT) && defined(CONFIG_VGA_CONSOLE)
	203	static void __init screen_info_setup(void)
	204	{
	205	screen_info = (struct screen_info) {
	206	.orig_x = 0,
	207	.orig_y = 25,
	208	.ext_mem_k = 0,
	209	.orig_video_page = 0,
	210	.orig_video_mode = 0,
	211	.orig_video_cols = 80,
	212	.unused2 = 0,
	213	.orig_video_ega_bx = 0,
	214	.unused3 = 0,
	215	.orig_video_lines = 25,
	216	.orig_video_isVGA = VIDEO_TYPE_VGAC,
	217	.orig_video_points = 16
	218	};
	219	}
	220	#endif
	221
750dc31c DV	222	static void __init bonito_quirks_setup(void)
	223	{
	224	char *argptr;
	225
b431f09d	226	argptr = fw_getcmdline();
750dc31c DV	227	if (strstr(argptr, "debug")) {
750dc31c DV	228	BONITO_BONGENCFG \|= BONITO_BONGENCFG_DEBUGMODE;
49bffbdc	229	pr_info("Enabled Bonito debug mode\n");
750dc31c DV	230	} else
	231	BONITO_BONGENCFG &= ~BONITO_BONGENCFG_DEBUGMODE;
	232
	233	#ifdef CONFIG_DMA_COHERENT
	234	if (BONITO_PCICACHECTRL & BONITO_PCICACHECTRL_CPUCOH_PRES) {
	235	BONITO_PCICACHECTRL \|= BONITO_PCICACHECTRL_CPUCOH_EN;
49bffbdc	236	pr_info("Enabled Bonito CPU coherency\n");
750dc31c	237
b431f09d	238	argptr = fw_getcmdline();
750dc31c DV	239	if (strstr(argptr, "iobcuncached")) {
	240	BONITO_PCICACHECTRL &= ~BONITO_PCICACHECTRL_IOBCCOH_EN;
	241	BONITO_PCIMEMBASECFG = BONITO_PCIMEMBASECFG &
	242	~(BONITO_PCIMEMBASECFG_MEMBASE0_CACHED \|
	243	BONITO_PCIMEMBASECFG_MEMBASE1_CACHED);
49bffbdc	244	pr_info("Disabled Bonito IOBC coherency\n");
750dc31c DV	245	} else {
	246	BONITO_PCICACHECTRL \|= BONITO_PCICACHECTRL_IOBCCOH_EN;
	247	BONITO_PCIMEMBASECFG \|=
	248	(BONITO_PCIMEMBASECFG_MEMBASE0_CACHED \|
	249	BONITO_PCIMEMBASECFG_MEMBASE1_CACHED);
49bffbdc	250	pr_info("Enabled Bonito IOBC coherency\n");
750dc31c DV	251	}
	252	} else
	253	panic("Hardware DMA cache coherency not supported");
	254	#endif
	255	}
	256
5e7c1c91 MR	257	void __init *plat_get_fdt(void)
	258	{
	259	return (void *)__dtb_start;
	260	}
	261
2925aba4	262	void __init plat_mem_setup(void)
1da177e4 LT	263	{
1da177e4 LT	264	unsigned int i;
5e7c1c91	265	void *fdt = plat_get_fdt();
1da177e4	266
e81a8c7d PB	267	fdt = malta_dt_shim(fdt);
e81a8c7d PB	268	__dt_setup_arch(fdt);
e8823d26	269
97f2645f	270	if (IS_ENABLED(CONFIG_EVA))
f8b7faf1 MC	271	/* EVA has already been configured in mach-malta/kernel-init.h */
	272	pr_info("Enhanced Virtual Addressing (EVA) activated\n");
	273
c83cfc9c RB	274	mips_pcibios_init();
c83cfc9c RB	275
1da177e4 LT	276	/* Request I/O space for devices used on the Malta board. */
	277	for (i = 0; i < ARRAY_SIZE(standard_io_resources); i++)
	278	request_resource(&ioport_resource, standard_io_resources+i);
	279
	280	/*
	281	* Enable DMA channel 4 (cascade channel) in the PIIX4 south bridge.
	282	*/
	283	enable_dma(4);
	284
1da177e4	285	#ifdef CONFIG_DMA_COHERENT
750dc31c	286	if (mips_revision_sconid != MIPS_REVISION_SCON_BONITO)
1da177e4	287	panic("Hardware DMA cache coherency not supported");
1da177e4 LT	288	#endif
1da177e4 LT	289
750dc31c DV	290	if (mips_revision_sconid == MIPS_REVISION_SCON_BONITO)
	291	bonito_quirks_setup();
	292
b6d92b4a SH	293	plat_setup_iocoherency();
b6d92b4a SH	294
f3a4ce95	295	pci_clock_check();
750dc31c	296
1da177e4	297	#ifdef CONFIG_BLK_DEV_FD
49a89efb	298	fd_activate();
1da177e4	299	#endif
750dc31c	300
a382963e DV	301	#if defined(CONFIG_VT) && defined(CONFIG_VGA_CONSOLE)
a382963e DV	302	screen_info_setup();
1da177e4	303	#endif
39b8d525 RB	304
	305	board_be_init = malta_be_init;
	306	board_be_handler = malta_be_handler;
1da177e4	307	}