[deliverable/linux.git] / arch / powerpc / include / asm / processor.h

#ifndef _ASM_POWERPC_PROCESSOR_H
#define _ASM_POWERPC_PROCESSOR_H

/*
 * Copyright (C) 2001 PPC 64 Team, IBM Corp
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * as published by the Free Software Foundation; either version
 * 2 of the License, or (at your option) any later version.
 */

#include <asm/reg.h>

#ifdef CONFIG_VSX
#define TS_FPRWIDTH 2

#ifdef __BIG_ENDIAN__
#define TS_FPROFFSET 0
#define TS_VSRLOWOFFSET 1
#else
#define TS_FPROFFSET 1
#define TS_VSRLOWOFFSET 0
#endif

#else
#define TS_FPRWIDTH 1
#define TS_FPROFFSET 0
#endif

#ifdef CONFIG_PPC64
/* Default SMT priority is set to 3. Use 11- 13bits to save priority. */
#define PPR_PRIORITY 3
#ifdef __ASSEMBLY__
#define INIT_PPR (PPR_PRIORITY << 50)
#else
#define INIT_PPR ((u64)PPR_PRIORITY << 50)
#endif /* __ASSEMBLY__ */
#endif /* CONFIG_PPC64 */

#ifndef __ASSEMBLY__
#include <linux/compiler.h>
#include <linux/cache.h>
#include <asm/ptrace.h>
#include <asm/types.h>
#include <asm/hw_breakpoint.h>

/* We do _not_ want to define new machine types at all, those must die
 * in favor of using the device-tree
 * -- BenH.
 */

/* PREP sub-platform types. Unused */
#define _PREP_Motorola	0x01	/* motorola prep */
#define _PREP_Firm	0x02	/* firmworks prep */
#define _PREP_IBM	0x00	/* ibm prep */
#define _PREP_Bull	0x03	/* bull prep */

/* CHRP sub-platform types. These are arbitrary */
#define _CHRP_Motorola	0x04	/* motorola chrp, the cobra */
#define _CHRP_IBM	0x05	/* IBM chrp, the longtrail and longtrail 2 */
#define _CHRP_Pegasos	0x06	/* Genesi/bplan's Pegasos and Pegasos2 */
#define _CHRP_briq	0x07	/* TotalImpact's briQ */

#if defined(__KERNEL__) && defined(CONFIG_PPC32)

extern int _chrp_type;

#endif /* defined(__KERNEL__) && defined(CONFIG_PPC32) */

/*
 * Default implementation of macro that returns current
 * instruction pointer ("program counter").
 */
#define current_text_addr() ({ __label__ _l; _l: &&_l;})

/* Macros for adjusting thread priority (hardware multi-threading) */
#define HMT_very_low()   asm volatile("or 31,31,31   # very low priority")
#define HMT_low()	 asm volatile("or 1,1,1	     # low priority")
#define HMT_medium_low() asm volatile("or 6,6,6      # medium low priority")
#define HMT_medium()	 asm volatile("or 2,2,2	     # medium priority")
#define HMT_medium_high() asm volatile("or 5,5,5      # medium high priority")
#define HMT_high()	 asm volatile("or 3,3,3	     # high priority")

#ifdef __KERNEL__

struct task_struct;
void start_thread(struct pt_regs *regs, unsigned long fdptr, unsigned long sp);
void release_thread(struct task_struct *);

#ifdef CONFIG_PPC32

#if CONFIG_TASK_SIZE > CONFIG_KERNEL_START
#error User TASK_SIZE overlaps with KERNEL_START address
#endif
#define TASK_SIZE	(CONFIG_TASK_SIZE)

/* This decides where the kernel will search for a free chunk of vm
 * space during mmap's.
 */
#define TASK_UNMAPPED_BASE	(TASK_SIZE / 8 * 3)
#endif

#ifdef CONFIG_PPC64
/* 64-bit user address space is 46-bits (64TB user VM) */
#define TASK_SIZE_USER64 (0x0000400000000000UL)

/* 
 * 32-bit user address space is 4GB - 1 page 
 * (this 1 page is needed so referencing of 0xFFFFFFFF generates EFAULT
 */
#define TASK_SIZE_USER32 (0x0000000100000000UL - (1*PAGE_SIZE))

#define TASK_SIZE_OF(tsk) (test_tsk_thread_flag(tsk, TIF_32BIT) ? \
		TASK_SIZE_USER32 : TASK_SIZE_USER64)
#define TASK_SIZE	  TASK_SIZE_OF(current)

/* This decides where the kernel will search for a free chunk of vm
 * space during mmap's.
 */
#define TASK_UNMAPPED_BASE_USER32 (PAGE_ALIGN(TASK_SIZE_USER32 / 4))
#define TASK_UNMAPPED_BASE_USER64 (PAGE_ALIGN(TASK_SIZE_USER64 / 4))

#define TASK_UNMAPPED_BASE ((is_32bit_task()) ? \
		TASK_UNMAPPED_BASE_USER32 : TASK_UNMAPPED_BASE_USER64 )
#endif

#ifdef __powerpc64__

#define STACK_TOP_USER64 TASK_SIZE_USER64
#define STACK_TOP_USER32 TASK_SIZE_USER32

#define STACK_TOP (is_32bit_task() ? \
		   STACK_TOP_USER32 : STACK_TOP_USER64)

#define STACK_TOP_MAX STACK_TOP_USER64

#else /* __powerpc64__ */

#define STACK_TOP TASK_SIZE
#define STACK_TOP_MAX	STACK_TOP

#endif /* __powerpc64__ */

typedef struct {
	unsigned long seg;
} mm_segment_t;

#define TS_FPR(i) fp_state.fpr[i][TS_FPROFFSET]
#define TS_TRANS_FPR(i) transact_fp.fpr[i][TS_FPROFFSET]

/* FP and VSX 0-31 register set */
struct thread_fp_state {
	u64	fpr[32][TS_FPRWIDTH] __attribute__((aligned(16)));
	u64	fpscr;		/* Floating point status */
};

/* Complete AltiVec register set including VSCR */
struct thread_vr_state {
	vector128	vr[32] __attribute__((aligned(16)));
	vector128	vscr __attribute__((aligned(16)));
};

struct debug_reg {
#ifdef CONFIG_PPC_ADV_DEBUG_REGS
	/*
	 * The following help to manage the use of Debug Control Registers
	 * om the BookE platforms.
	 */
	uint32_t	dbcr0;
	uint32_t	dbcr1;
#ifdef CONFIG_BOOKE
	uint32_t	dbcr2;
#endif
	/*
	 * The stored value of the DBSR register will be the value at the
	 * last debug interrupt. This register can only be read from the
	 * user (will never be written to) and has value while helping to
	 * describe the reason for the last debug trap.  Torez
	 */
	uint32_t	dbsr;
	/*
	 * The following will contain addresses used by debug applications
	 * to help trace and trap on particular address locations.
	 * The bits in the Debug Control Registers above help define which
	 * of the following registers will contain valid data and/or addresses.
	 */
	unsigned long	iac1;
	unsigned long	iac2;
#if CONFIG_PPC_ADV_DEBUG_IACS > 2
	unsigned long	iac3;
	unsigned long	iac4;
#endif
	unsigned long	dac1;
	unsigned long	dac2;
#if CONFIG_PPC_ADV_DEBUG_DVCS > 0
	unsigned long	dvc1;
	unsigned long	dvc2;
#endif
#endif
};

struct thread_struct {
	unsigned long	ksp;		/* Kernel stack pointer */

#ifdef CONFIG_PPC64
	unsigned long	ksp_vsid;
#endif
	struct pt_regs	*regs;		/* Pointer to saved register state */
	mm_segment_t	fs;		/* for get_fs() validation */
#ifdef CONFIG_BOOKE
	/* BookE base exception scratch space; align on cacheline */
	unsigned long	normsave[8] ____cacheline_aligned;
#endif
#ifdef CONFIG_PPC32
	void		*pgdir;		/* root of page-table tree */
	unsigned long	ksp_limit;	/* if ksp <= ksp_limit stack overflow */
#endif
	/* Debug Registers */
	struct debug_reg debug;
	struct thread_fp_state	fp_state;
	struct thread_fp_state	*fp_save_area;
	int		fpexc_mode;	/* floating-point exception mode */
	unsigned int	align_ctl;	/* alignment handling control */
#ifdef CONFIG_PPC64
	unsigned long	start_tb;	/* Start purr when proc switched in */
	unsigned long	accum_tb;	/* Total accumilated purr for process */
#ifdef CONFIG_HAVE_HW_BREAKPOINT
	struct perf_event *ptrace_bps[HBP_NUM];
	/*
	 * Helps identify source of single-step exception and subsequent
	 * hw-breakpoint enablement
	 */
	struct perf_event *last_hit_ubp;
#endif /* CONFIG_HAVE_HW_BREAKPOINT */
#endif
	struct arch_hw_breakpoint hw_brk; /* info on the hardware breakpoint */
	unsigned long	trap_nr;	/* last trap # on this thread */
	u8 load_fp;
#ifdef CONFIG_ALTIVEC
	u8 load_vec;
	struct thread_vr_state vr_state;
	struct thread_vr_state *vr_save_area;
	unsigned long	vrsave;
	int		used_vr;	/* set if process has used altivec */
#endif /* CONFIG_ALTIVEC */
#ifdef CONFIG_VSX
	/* VSR status */
	int		used_vsr;	/* set if process has used VSX */
#endif /* CONFIG_VSX */
#ifdef CONFIG_SPE
	unsigned long	evr[32];	/* upper 32-bits of SPE regs */
	u64		acc;		/* Accumulator */
	unsigned long	spefscr;	/* SPE & eFP status */
	unsigned long	spefscr_last;	/* SPEFSCR value on last prctl
					   call or trap return */
	int		used_spe;	/* set if process has used spe */
#endif /* CONFIG_SPE */
#ifdef CONFIG_PPC_TRANSACTIONAL_MEM
	u64		tm_tfhar;	/* Transaction fail handler addr */
	u64		tm_texasr;	/* Transaction exception & summary */
	u64		tm_tfiar;	/* Transaction fail instr address reg */
	struct pt_regs	ckpt_regs;	/* Checkpointed registers */

	unsigned long	tm_tar;
	unsigned long	tm_ppr;
	unsigned long	tm_dscr;

	/*
	 * Transactional FP and VSX 0-31 register set.
	 * NOTE: the sense of these is the opposite of the integer ckpt_regs!
	 *
	 * When a transaction is active/signalled/scheduled etc., *regs is the
	 * most recent set of/speculated GPRs with ckpt_regs being the older
	 * checkpointed regs to which we roll back if transaction aborts.
	 *
	 * However, fpr[] is the checkpointed 'base state' of FP regs, and
	 * transact_fpr[] is the new set of transactional values.
	 * VRs work the same way.
	 */
	struct thread_fp_state transact_fp;
	struct thread_vr_state transact_vr;
	unsigned long	transact_vrsave;
#endif /* CONFIG_PPC_TRANSACTIONAL_MEM */
#ifdef CONFIG_KVM_BOOK3S_32_HANDLER
	void*		kvm_shadow_vcpu; /* KVM internal data */
#endif /* CONFIG_KVM_BOOK3S_32_HANDLER */
#if defined(CONFIG_KVM) && defined(CONFIG_BOOKE)
	struct kvm_vcpu	*kvm_vcpu;
#endif
#ifdef CONFIG_PPC64
	unsigned long	dscr;
	unsigned long	fscr;
	/*
	 * This member element dscr_inherit indicates that the process
	 * has explicitly attempted and changed the DSCR register value
	 * for itself. Hence kernel wont use the default CPU DSCR value
	 * contained in the PACA structure anymore during process context
	 * switch. Once this variable is set, this behaviour will also be
	 * inherited to all the children of this process from that point
	 * onwards.
	 */
	int		dscr_inherit;
	unsigned long	ppr;	/* used to save/restore SMT priority */
#endif
#ifdef CONFIG_PPC_BOOK3S_64
	unsigned long	tar;
	unsigned long	ebbrr;
	unsigned long	ebbhr;
	unsigned long	bescr;
	unsigned long	siar;
	unsigned long	sdar;
	unsigned long	sier;
	unsigned long	mmcr2;
	unsigned 	mmcr0;
	unsigned 	used_ebb;
#endif
};

#define ARCH_MIN_TASKALIGN 16

#define INIT_SP		(sizeof(init_stack) + (unsigned long) &init_stack)
#define INIT_SP_LIMIT \
	(_ALIGN_UP(sizeof(init_thread_info), 16) + (unsigned long) &init_stack)

#ifdef CONFIG_SPE
#define SPEFSCR_INIT \
	.spefscr = SPEFSCR_FINVE | SPEFSCR_FDBZE | SPEFSCR_FUNFE | SPEFSCR_FOVFE, \
	.spefscr_last = SPEFSCR_FINVE | SPEFSCR_FDBZE | SPEFSCR_FUNFE | SPEFSCR_FOVFE,
#else
#define SPEFSCR_INIT
#endif

#ifdef CONFIG_PPC32
#define INIT_THREAD { \
	.ksp = INIT_SP, \
	.ksp_limit = INIT_SP_LIMIT, \
	.fs = KERNEL_DS, \
	.pgdir = swapper_pg_dir, \
	.fpexc_mode = MSR_FE0 | MSR_FE1, \
	SPEFSCR_INIT \
}
#else
#define INIT_THREAD  { \
	.ksp = INIT_SP, \
	.regs = (struct pt_regs *)INIT_SP - 1, /* XXX bogus, I think */ \
	.fs = KERNEL_DS, \
	.fpexc_mode = 0, \
	.ppr = INIT_PPR, \
}
#endif

/*
 * Return saved PC of a blocked thread. For now, this is the "user" PC
 */
#define thread_saved_pc(tsk)    \
        ((tsk)->thread.regs? (tsk)->thread.regs->nip: 0)

#define task_pt_regs(tsk)	((struct pt_regs *)(tsk)->thread.regs)

unsigned long get_wchan(struct task_struct *p);

#define KSTK_EIP(tsk)  ((tsk)->thread.regs? (tsk)->thread.regs->nip: 0)
#define KSTK_ESP(tsk)  ((tsk)->thread.regs? (tsk)->thread.regs->gpr[1]: 0)

/* Get/set floating-point exception mode */
#define GET_FPEXC_CTL(tsk, adr) get_fpexc_mode((tsk), (adr))
#define SET_FPEXC_CTL(tsk, val) set_fpexc_mode((tsk), (val))

extern int get_fpexc_mode(struct task_struct *tsk, unsigned long adr);
extern int set_fpexc_mode(struct task_struct *tsk, unsigned int val);

#define GET_ENDIAN(tsk, adr) get_endian((tsk), (adr))
#define SET_ENDIAN(tsk, val) set_endian((tsk), (val))

extern int get_endian(struct task_struct *tsk, unsigned long adr);
extern int set_endian(struct task_struct *tsk, unsigned int val);

#define GET_UNALIGN_CTL(tsk, adr)	get_unalign_ctl((tsk), (adr))
#define SET_UNALIGN_CTL(tsk, val)	set_unalign_ctl((tsk), (val))

extern int get_unalign_ctl(struct task_struct *tsk, unsigned long adr);
extern int set_unalign_ctl(struct task_struct *tsk, unsigned int val);

extern void load_fp_state(struct thread_fp_state *fp);
extern void store_fp_state(struct thread_fp_state *fp);
extern void load_vr_state(struct thread_vr_state *vr);
extern void store_vr_state(struct thread_vr_state *vr);

static inline unsigned int __unpack_fe01(unsigned long msr_bits)
{
	return ((msr_bits & MSR_FE0) >> 10) | ((msr_bits & MSR_FE1) >> 8);
}

static inline unsigned long __pack_fe01(unsigned int fpmode)
{
	return ((fpmode << 10) & MSR_FE0) | ((fpmode << 8) & MSR_FE1);
}

#ifdef CONFIG_PPC64
#define cpu_relax()	do { HMT_low(); HMT_medium(); barrier(); } while (0)
#else
#define cpu_relax()	barrier()
#endif

#define cpu_relax_lowlatency() cpu_relax()

/* Check that a certain kernel stack pointer is valid in task_struct p */
int validate_sp(unsigned long sp, struct task_struct *p,
                       unsigned long nbytes);

/*
 * Prefetch macros.
 */
#define ARCH_HAS_PREFETCH
#define ARCH_HAS_PREFETCHW
#define ARCH_HAS_SPINLOCK_PREFETCH

static inline void prefetch(const void *x)
{
	if (unlikely(!x))
		return;

	__asm__ __volatile__ ("dcbt 0,%0" : : "r" (x));
}

static inline void prefetchw(const void *x)
{
	if (unlikely(!x))
		return;

	__asm__ __volatile__ ("dcbtst 0,%0" : : "r" (x));
}

#define spin_lock_prefetch(x)	prefetchw(x)

#define HAVE_ARCH_PICK_MMAP_LAYOUT

#ifdef CONFIG_PPC64
static inline unsigned long get_clean_sp(unsigned long sp, int is_32)
{
	if (is_32)
		return sp & 0x0ffffffffUL;
	return sp;
}
#else
static inline unsigned long get_clean_sp(unsigned long sp, int is_32)
{
	return sp;
}
#endif

extern unsigned long cpuidle_disable;
enum idle_boot_override {IDLE_NO_OVERRIDE = 0, IDLE_POWERSAVE_OFF};

extern int powersave_nap;	/* set if nap mode can be used in idle loop */
extern unsigned long power7_nap(int check_irq);
extern unsigned long power7_sleep(void);
extern unsigned long power7_winkle(void);
extern void flush_instruction_cache(void);
extern void hard_reset_now(void);
extern void poweroff_now(void);
extern int fix_alignment(struct pt_regs *);
extern void cvt_fd(float *from, double *to);
extern void cvt_df(double *from, float *to);
extern void _nmask_and_or_msr(unsigned long nmask, unsigned long or_val);

#ifdef CONFIG_PPC64
/*
 * We handle most unaligned accesses in hardware. On the other hand 
 * unaligned DMA can be very expensive on some ppc64 IO chips (it does
 * powers of 2 writes until it reaches sufficient alignment).
 *
 * Based on this we disable the IP header alignment in network drivers.
 */
#define NET_IP_ALIGN	0
#endif

#endif /* __KERNEL__ */
#endif /* __ASSEMBLY__ */
#endif /* _ASM_POWERPC_PROCESSOR_H */
Commit	Line	Data
9f04b9e3 PM	1	#ifndef _ASM_POWERPC_PROCESSOR_H
9f04b9e3 PM	2	#define _ASM_POWERPC_PROCESSOR_H
1da177e4 LT	3
1da177e4 LT	4	/*
9f04b9e3 PM	5	* Copyright (C) 2001 PPC 64 Team, IBM Corp
	6	*
	7	* This program is free software; you can redistribute it and/or
	8	* modify it under the terms of the GNU General Public License
	9	* as published by the Free Software Foundation; either version
	10	* 2 of the License, or (at your option) any later version.
1da177e4	11	*/
1da177e4	12
9f04b9e3	13	#include <asm/reg.h>
1da177e4	14
c6e6771b MN	15	#ifdef CONFIG_VSX
c6e6771b MN	16	#define TS_FPRWIDTH 2
e156bd8a AB	17
	18	#ifdef __BIG_ENDIAN__
	19	#define TS_FPROFFSET 0
	20	#define TS_VSRLOWOFFSET 1
	21	#else
	22	#define TS_FPROFFSET 1
	23	#define TS_VSRLOWOFFSET 0
	24	#endif
	25
c6e6771b	26	#else
9c75a31c	27	#define TS_FPRWIDTH 1
e156bd8a	28	#define TS_FPROFFSET 0
c6e6771b	29	#endif
9c75a31c	30
92779245 HM	31	#ifdef CONFIG_PPC64
	32	/* Default SMT priority is set to 3. Use 11- 13bits to save priority. */
	33	#define PPR_PRIORITY 3
	34	#ifdef __ASSEMBLY__
	35	#define INIT_PPR (PPR_PRIORITY << 50)
	36	#else
	37	#define INIT_PPR ((u64)PPR_PRIORITY << 50)
	38	#endif /* __ASSEMBLY__ */
	39	#endif /* CONFIG_PPC64 */
	40
9f04b9e3 PM	41	#ifndef __ASSEMBLY__
9f04b9e3 PM	42	#include <linux/compiler.h>
1325a684	43	#include <linux/cache.h>
1da177e4 LT	44	#include <asm/ptrace.h>
1da177e4 LT	45	#include <asm/types.h>
9422de3e	46	#include <asm/hw_breakpoint.h>
1da177e4	47
799d6046 PM	48	/* We do _not_ want to define new machine types at all, those must die
	49	* in favor of using the device-tree
	50	* -- BenH.
1da177e4	51	*/
1da177e4	52
933ee711	53	/* PREP sub-platform types. Unused */
1da177e4 LT	54	#define _PREP_Motorola 0x01 /* motorola prep */
	55	#define _PREP_Firm 0x02 /* firmworks prep */
	56	#define _PREP_IBM 0x00 /* ibm prep */
	57	#define _PREP_Bull 0x03 /* bull prep */
	58
799d6046	59	/* CHRP sub-platform types. These are arbitrary */
1da177e4 LT	60	#define _CHRP_Motorola 0x04 /* motorola chrp, the cobra */
	61	#define _CHRP_IBM 0x05 /* IBM chrp, the longtrail and longtrail 2 */
	62	#define _CHRP_Pegasos 0x06 /* Genesi/bplan's Pegasos and Pegasos2 */
26c5032e	63	#define _CHRP_briq 0x07 /* TotalImpact's briQ */
1da177e4	64
e8222502 BH	65	#if defined(__KERNEL__) && defined(CONFIG_PPC32)
	66
	67	extern int _chrp_type;
799d6046	68
e8222502 BH	69	#endif /* defined(__KERNEL__) && defined(CONFIG_PPC32) */
e8222502 BH	70
9f04b9e3 PM	71	/*
	72	* Default implementation of macro that returns current
	73	* instruction pointer ("program counter").
	74	*/
	75	#define current_text_addr() ({ __label__ _l; _l: &&_l;})
	76
	77	/* Macros for adjusting thread priority (hardware multi-threading) */
	78	#define HMT_very_low() asm volatile("or 31,31,31 # very low priority")
	79	#define HMT_low() asm volatile("or 1,1,1 # low priority")
	80	#define HMT_medium_low() asm volatile("or 6,6,6 # medium low priority")
	81	#define HMT_medium() asm volatile("or 2,2,2 # medium priority")
	82	#define HMT_medium_high() asm volatile("or 5,5,5 # medium high priority")
	83	#define HMT_high() asm volatile("or 3,3,3 # high priority")
	84
	85	#ifdef __KERNEL__
	86
1da177e4	87	struct task_struct;
9f04b9e3	88	void start_thread(struct pt_regs *regs, unsigned long fdptr, unsigned long sp);
1da177e4 LT	89	void release_thread(struct task_struct *);
1da177e4 LT	90
9f04b9e3	91	#ifdef CONFIG_PPC32
7c4f10b9 RT	92
	93	#if CONFIG_TASK_SIZE > CONFIG_KERNEL_START
	94	#error User TASK_SIZE overlaps with KERNEL_START address
	95	#endif
9f04b9e3 PM	96	#define TASK_SIZE (CONFIG_TASK_SIZE)
9f04b9e3 PM	97
1da177e4 LT	98	/* This decides where the kernel will search for a free chunk of vm
	99	* space during mmap's.
	100	*/
	101	#define TASK_UNMAPPED_BASE (TASK_SIZE / 8 * 3)
9f04b9e3 PM	102	#endif
	103
	104	#ifdef CONFIG_PPC64
048ee099 AK	105	/* 64-bit user address space is 46-bits (64TB user VM) */
048ee099 AK	106	#define TASK_SIZE_USER64 (0x0000400000000000UL)
9f04b9e3 PM	107
	108	/*
	109	* 32-bit user address space is 4GB - 1 page
	110	* (this 1 page is needed so referencing of 0xFFFFFFFF generates EFAULT
	111	*/
	112	#define TASK_SIZE_USER32 (0x0000000100000000UL - (1*PAGE_SIZE))
	113
82455257	114	#define TASK_SIZE_OF(tsk) (test_tsk_thread_flag(tsk, TIF_32BIT) ? \
9f04b9e3	115	TASK_SIZE_USER32 : TASK_SIZE_USER64)
82455257	116	#define TASK_SIZE TASK_SIZE_OF(current)
9f04b9e3 PM	117
	118	/* This decides where the kernel will search for a free chunk of vm
	119	* space during mmap's.
	120	*/
	121	#define TASK_UNMAPPED_BASE_USER32 (PAGE_ALIGN(TASK_SIZE_USER32 / 4))
	122	#define TASK_UNMAPPED_BASE_USER64 (PAGE_ALIGN(TASK_SIZE_USER64 / 4))
	123
cab175f9	124	#define TASK_UNMAPPED_BASE ((is_32bit_task()) ? \
9f04b9e3 PM	125	TASK_UNMAPPED_BASE_USER32 : TASK_UNMAPPED_BASE_USER64 )
9f04b9e3 PM	126	#endif
1da177e4	127
922a70d3 DH	128	#ifdef __powerpc64__
	129
	130	#define STACK_TOP_USER64 TASK_SIZE_USER64
	131	#define STACK_TOP_USER32 TASK_SIZE_USER32
	132
cab175f9	133	#define STACK_TOP (is_32bit_task() ? \
922a70d3 DH	134	STACK_TOP_USER32 : STACK_TOP_USER64)
	135
	136	#define STACK_TOP_MAX STACK_TOP_USER64
	137
	138	#else /* __powerpc64__ */
	139
	140	#define STACK_TOP TASK_SIZE
	141	#define STACK_TOP_MAX STACK_TOP
	142
	143	#endif /* __powerpc64__ */
922a70d3	144
1da177e4 LT	145	typedef struct {
	146	unsigned long seg;
	147	} mm_segment_t;
	148
de79f7b9 PM	149	#define TS_FPR(i) fp_state.fpr[i][TS_FPROFFSET]
	150	#define TS_TRANS_FPR(i) transact_fp.fpr[i][TS_FPROFFSET]
	151
	152	/* FP and VSX 0-31 register set */
	153	struct thread_fp_state {
	154	u64 fpr[32][TS_FPRWIDTH] __attribute__((aligned(16)));
	155	u64 fpscr; /* Floating point status */
	156	};
	157
	158	/* Complete AltiVec register set including VSCR */
	159	struct thread_vr_state {
	160	vector128 vr[32] __attribute__((aligned(16)));
	161	vector128 vscr __attribute__((aligned(16)));
	162	};
9c75a31c	163
51ae8d4a	164	struct debug_reg {
99396ac1 DK	165	#ifdef CONFIG_PPC_ADV_DEBUG_REGS
	166	/*
	167	* The following help to manage the use of Debug Control Registers
	168	* om the BookE platforms.
	169	*/
d8899bb2 BB	170	uint32_t dbcr0;
d8899bb2 BB	171	uint32_t dbcr1;
99396ac1	172	#ifdef CONFIG_BOOKE
d8899bb2	173	uint32_t dbcr2;
99396ac1 DK	174	#endif
	175	/*
	176	* The stored value of the DBSR register will be the value at the
	177	* last debug interrupt. This register can only be read from the
	178	* user (will never be written to) and has value while helping to
	179	* describe the reason for the last debug trap. Torez
	180	*/
d8899bb2	181	uint32_t dbsr;
99396ac1 DK	182	/*
	183	* The following will contain addresses used by debug applications
	184	* to help trace and trap on particular address locations.
	185	* The bits in the Debug Control Registers above help define which
	186	* of the following registers will contain valid data and/or addresses.
	187	*/
	188	unsigned long iac1;
	189	unsigned long iac2;
	190	#if CONFIG_PPC_ADV_DEBUG_IACS > 2
	191	unsigned long iac3;
	192	unsigned long iac4;
	193	#endif
	194	unsigned long dac1;
	195	unsigned long dac2;
	196	#if CONFIG_PPC_ADV_DEBUG_DVCS > 0
	197	unsigned long dvc1;
	198	unsigned long dvc2;
	199	#endif
1da177e4	200	#endif
51ae8d4a BB	201	};
	202
	203	struct thread_struct {
	204	unsigned long ksp; /* Kernel stack pointer */
95791988	205
51ae8d4a BB	206	#ifdef CONFIG_PPC64
	207	unsigned long ksp_vsid;
	208	#endif
	209	struct pt_regs regs; / Pointer to saved register state */
	210	mm_segment_t fs; /* for get_fs() validation */
	211	#ifdef CONFIG_BOOKE
	212	/* BookE base exception scratch space; align on cacheline */
	213	unsigned long normsave[8] ____cacheline_aligned;
	214	#endif
	215	#ifdef CONFIG_PPC32
	216	void pgdir; / root of page-table tree */
	217	unsigned long ksp_limit; /* if ksp <= ksp_limit stack overflow */
	218	#endif
95791988	219	/* Debug Registers */
51ae8d4a	220	struct debug_reg debug;
de79f7b9	221	struct thread_fp_state fp_state;
18461960	222	struct thread_fp_state *fp_save_area;
9f04b9e3	223	int fpexc_mode; /* floating-point exception mode */
e9370ae1	224	unsigned int align_ctl; /* alignment handling control */
9f04b9e3 PM	225	#ifdef CONFIG_PPC64
	226	unsigned long start_tb; /* Start purr when proc switched in */
	227	unsigned long accum_tb; /* Total accumilated purr for process */
5aae8a53 P	228	#ifdef CONFIG_HAVE_HW_BREAKPOINT
	229	struct perf_event *ptrace_bps[HBP_NUM];
	230	/*
	231	* Helps identify source of single-step exception and subsequent
	232	* hw-breakpoint enablement
	233	*/
	234	struct perf_event *last_hit_ubp;
	235	#endif /* CONFIG_HAVE_HW_BREAKPOINT */
9f04b9e3	236	#endif
9422de3e	237	struct arch_hw_breakpoint hw_brk; /* info on the hardware breakpoint */
41ab5266	238	unsigned long trap_nr; /* last trap # on this thread */
70fe3d98	239	u8 load_fp;
1da177e4	240	#ifdef CONFIG_ALTIVEC
70fe3d98	241	u8 load_vec;
de79f7b9	242	struct thread_vr_state vr_state;
18461960	243	struct thread_vr_state *vr_save_area;
1da177e4 LT	244	unsigned long vrsave;
	245	int used_vr; /* set if process has used altivec */
	246	#endif /* CONFIG_ALTIVEC */
c6e6771b MN	247	#ifdef CONFIG_VSX
c6e6771b MN	248	/* VSR status */
71528d8b	249	int used_vsr; /* set if process has used VSX */
c6e6771b	250	#endif /* CONFIG_VSX */
1da177e4 LT	251	#ifdef CONFIG_SPE
	252	unsigned long evr[32]; /* upper 32-bits of SPE regs */
	253	u64 acc; /* Accumulator */
	254	unsigned long spefscr; /* SPE & eFP status */
640e9225 JM	255	unsigned long spefscr_last; /* SPEFSCR value on last prctl
640e9225 JM	256	call or trap return */
1da177e4 LT	257	int used_spe; /* set if process has used spe */
1da177e4 LT	258	#endif /* CONFIG_SPE */
f4c3aff2 MN	259	#ifdef CONFIG_PPC_TRANSACTIONAL_MEM
	260	u64 tm_tfhar; /* Transaction fail handler addr */
	261	u64 tm_texasr; /* Transaction exception & summary */
	262	u64 tm_tfiar; /* Transaction fail instr address reg */
f4c3aff2 MN	263	struct pt_regs ckpt_regs; /* Checkpointed registers */
f4c3aff2 MN	264
28e61cc4 MN	265	unsigned long tm_tar;
	266	unsigned long tm_ppr;
	267	unsigned long tm_dscr;
	268
f4c3aff2 MN	269	/*
	270	* Transactional FP and VSX 0-31 register set.
	271	* NOTE: the sense of these is the opposite of the integer ckpt_regs!
	272	*
	273	* When a transaction is active/signalled/scheduled etc., *regs is the
	274	* most recent set of/speculated GPRs with ckpt_regs being the older
	275	* checkpointed regs to which we roll back if transaction aborts.
	276	*
	277	* However, fpr[] is the checkpointed 'base state' of FP regs, and
	278	* transact_fpr[] is the new set of transactional values.
	279	* VRs work the same way.
	280	*/
de79f7b9 PM	281	struct thread_fp_state transact_fp;
de79f7b9 PM	282	struct thread_vr_state transact_vr;
f4c3aff2 MN	283	unsigned long transact_vrsave;
f4c3aff2 MN	284	#endif /* CONFIG_PPC_TRANSACTIONAL_MEM */
97e49255 AG	285	#ifdef CONFIG_KVM_BOOK3S_32_HANDLER
	286	void* kvm_shadow_vcpu; /* KVM internal data */
	287	#endif /* CONFIG_KVM_BOOK3S_32_HANDLER */
d30f6e48 SW	288	#if defined(CONFIG_KVM) && defined(CONFIG_BOOKE)
	289	struct kvm_vcpu *kvm_vcpu;
	290	#endif
efcac658 AK	291	#ifdef CONFIG_PPC64
efcac658 AK	292	unsigned long dscr;
152d523e	293	unsigned long fscr;
d3cb06e0 AK	294	/*
	295	* This member element dscr_inherit indicates that the process
	296	* has explicitly attempted and changed the DSCR register value
	297	* for itself. Hence kernel wont use the default CPU DSCR value
	298	* contained in the PACA structure anymore during process context
	299	* switch. Once this variable is set, this behaviour will also be
	300	* inherited to all the children of this process from that point
	301	* onwards.
	302	*/
efcac658	303	int dscr_inherit;
92779245	304	unsigned long ppr; /* used to save/restore SMT priority */
efcac658	305	#endif
2468dcf6 IM	306	#ifdef CONFIG_PPC_BOOK3S_64
2468dcf6 IM	307	unsigned long tar;
9353374b ME	308	unsigned long ebbrr;
	309	unsigned long ebbhr;
	310	unsigned long bescr;
59affcd3 ME	311	unsigned long siar;
	312	unsigned long sdar;
	313	unsigned long sier;
59affcd3	314	unsigned long mmcr2;
330a1eb7 ME	315	unsigned mmcr0;
330a1eb7 ME	316	unsigned used_ebb;
2468dcf6	317	#endif
1da177e4 LT	318	};
	319
	320	#define ARCH_MIN_TASKALIGN 16
	321
	322	#define INIT_SP (sizeof(init_stack) + (unsigned long) &init_stack)
85218827 KG	323	#define INIT_SP_LIMIT \
85218827 KG	324	(_ALIGN_UP(sizeof(init_thread_info), 16) + (unsigned long) &init_stack)
1da177e4	325
6a800f36	326	#ifdef CONFIG_SPE
640e9225 JM	327	#define SPEFSCR_INIT \
	328	.spefscr = SPEFSCR_FINVE \| SPEFSCR_FDBZE \| SPEFSCR_FUNFE \| SPEFSCR_FOVFE, \
	329	.spefscr_last = SPEFSCR_FINVE \| SPEFSCR_FDBZE \| SPEFSCR_FUNFE \| SPEFSCR_FOVFE,
6a800f36 LY	330	#else
	331	#define SPEFSCR_INIT
	332	#endif
9f04b9e3 PM	333
9f04b9e3 PM	334	#ifdef CONFIG_PPC32
1da177e4 LT	335	#define INIT_THREAD { \
1da177e4 LT	336	.ksp = INIT_SP, \
85218827	337	.ksp_limit = INIT_SP_LIMIT, \
1da177e4 LT	338	.fs = KERNEL_DS, \
	339	.pgdir = swapper_pg_dir, \
	340	.fpexc_mode = MSR_FE0 \| MSR_FE1, \
6a800f36	341	SPEFSCR_INIT \
1da177e4	342	}
9f04b9e3 PM	343	#else
	344	#define INIT_THREAD { \
	345	.ksp = INIT_SP, \
	346	.regs = (struct pt_regs )INIT_SP - 1, / XXX bogus, I think */ \
	347	.fs = KERNEL_DS, \
ddf5f75a	348	.fpexc_mode = 0, \
92779245	349	.ppr = INIT_PPR, \
9f04b9e3 PM	350	}
9f04b9e3 PM	351	#endif
1da177e4 LT	352
	353	/*
	354	* Return saved PC of a blocked thread. For now, this is the "user" PC
	355	*/
9f04b9e3 PM	356	#define thread_saved_pc(tsk) \
9f04b9e3 PM	357	((tsk)->thread.regs? (tsk)->thread.regs->nip: 0)
1da177e4	358
e5093ff0 SD	359	#define task_pt_regs(tsk) ((struct pt_regs *)(tsk)->thread.regs)
e5093ff0 SD	360
1da177e4 LT	361	unsigned long get_wchan(struct task_struct *p);
1da177e4 LT	362
9f04b9e3 PM	363	#define KSTK_EIP(tsk) ((tsk)->thread.regs? (tsk)->thread.regs->nip: 0)
9f04b9e3 PM	364	#define KSTK_ESP(tsk) ((tsk)->thread.regs? (tsk)->thread.regs->gpr[1]: 0)
1da177e4 LT	365
1da177e4 LT	366	/* Get/set floating-point exception mode */
9f04b9e3 PM	367	#define GET_FPEXC_CTL(tsk, adr) get_fpexc_mode((tsk), (adr))
9f04b9e3 PM	368	#define SET_FPEXC_CTL(tsk, val) set_fpexc_mode((tsk), (val))
1da177e4 LT	369
	370	extern int get_fpexc_mode(struct task_struct *tsk, unsigned long adr);
	371	extern int set_fpexc_mode(struct task_struct *tsk, unsigned int val);
	372
fab5db97 PM	373	#define GET_ENDIAN(tsk, adr) get_endian((tsk), (adr))
	374	#define SET_ENDIAN(tsk, val) set_endian((tsk), (val))
	375
	376	extern int get_endian(struct task_struct *tsk, unsigned long adr);
	377	extern int set_endian(struct task_struct *tsk, unsigned int val);
	378
e9370ae1 PM	379	#define GET_UNALIGN_CTL(tsk, adr) get_unalign_ctl((tsk), (adr))
	380	#define SET_UNALIGN_CTL(tsk, val) set_unalign_ctl((tsk), (val))
	381
	382	extern int get_unalign_ctl(struct task_struct *tsk, unsigned long adr);
	383	extern int set_unalign_ctl(struct task_struct *tsk, unsigned int val);
	384
18461960 PM	385	extern void load_fp_state(struct thread_fp_state *fp);
	386	extern void store_fp_state(struct thread_fp_state *fp);
	387	extern void load_vr_state(struct thread_vr_state *vr);
	388	extern void store_vr_state(struct thread_vr_state *vr);
	389
9f04b9e3	390	static inline unsigned int __unpack_fe01(unsigned long msr_bits)
1da177e4 LT	391	{
	392	return ((msr_bits & MSR_FE0) >> 10) \| ((msr_bits & MSR_FE1) >> 8);
	393	}
	394
9f04b9e3	395	static inline unsigned long __pack_fe01(unsigned int fpmode)
1da177e4 LT	396	{
	397	return ((fpmode << 10) & MSR_FE0) \| ((fpmode << 8) & MSR_FE1);
	398	}
	399
9f04b9e3 PM	400	#ifdef CONFIG_PPC64
	401	#define cpu_relax() do { HMT_low(); HMT_medium(); barrier(); } while (0)
	402	#else
1da177e4	403	#define cpu_relax() barrier()
9f04b9e3	404	#endif
1da177e4	405
3a6bfbc9 DB	406	#define cpu_relax_lowlatency() cpu_relax()
3a6bfbc9 DB	407
2f25194d AB	408	/* Check that a certain kernel stack pointer is valid in task_struct p */
	409	int validate_sp(unsigned long sp, struct task_struct *p,
	410	unsigned long nbytes);
	411
1da177e4 LT	412	/*
	413	* Prefetch macros.
	414	*/
	415	#define ARCH_HAS_PREFETCH
	416	#define ARCH_HAS_PREFETCHW
	417	#define ARCH_HAS_SPINLOCK_PREFETCH
	418
9f04b9e3	419	static inline void prefetch(const void *x)
1da177e4	420	{
9f04b9e3 PM	421	if (unlikely(!x))
	422	return;
	423
	424	__asm__ __volatile__ ("dcbt 0,%0" : : "r" (x));
1da177e4 LT	425	}
1da177e4 LT	426
9f04b9e3	427	static inline void prefetchw(const void *x)
1da177e4	428	{
9f04b9e3 PM	429	if (unlikely(!x))
	430	return;
	431
	432	__asm__ __volatile__ ("dcbtst 0,%0" : : "r" (x));
1da177e4 LT	433	}
	434
	435	#define spin_lock_prefetch(x) prefetchw(x)
	436
9f04b9e3	437	#define HAVE_ARCH_PICK_MMAP_LAYOUT
1da177e4	438
efbda860	439	#ifdef CONFIG_PPC64
2b3f8e87	440	static inline unsigned long get_clean_sp(unsigned long sp, int is_32)
efbda860	441	{
efbda860	442	if (is_32)
2b3f8e87	443	return sp & 0x0ffffffffUL;
efbda860 JB	444	return sp;
	445	}
	446	#else
2b3f8e87	447	static inline unsigned long get_clean_sp(unsigned long sp, int is_32)
efbda860	448	{
2b3f8e87	449	return sp;
efbda860 JB	450	}
	451	#endif
	452
e8bb3e00	453	extern unsigned long cpuidle_disable;
771dae81 DD	454	enum idle_boot_override {IDLE_NO_OVERRIDE = 0, IDLE_POWERSAVE_OFF};
771dae81 DD	455
ae3a197e	456	extern int powersave_nap; /* set if nap mode can be used in idle loop */
56548fc0	457	extern unsigned long power7_nap(int check_irq);
7cba160a	458	extern unsigned long power7_sleep(void);
77b54e9f	459	extern unsigned long power7_winkle(void);
ae3a197e DH	460	extern void flush_instruction_cache(void);
	461	extern void hard_reset_now(void);
	462	extern void poweroff_now(void);
	463	extern int fix_alignment(struct pt_regs *);
	464	extern void cvt_fd(float from, double to);
	465	extern void cvt_df(double from, float to);
	466	extern void _nmask_and_or_msr(unsigned long nmask, unsigned long or_val);
	467
	468	#ifdef CONFIG_PPC64
	469	/*
	470	* We handle most unaligned accesses in hardware. On the other hand
	471	* unaligned DMA can be very expensive on some ppc64 IO chips (it does
	472	* powers of 2 writes until it reaches sufficient alignment).
	473	*
	474	* Based on this we disable the IP header alignment in network drivers.
	475	*/
	476	#define NET_IP_ALIGN 0
	477	#endif
	478
1da177e4	479	#endif /* __KERNEL__ */
9f04b9e3 PM	480	#endif /* __ASSEMBLY__ */
9f04b9e3 PM	481	#endif /* _ASM_POWERPC_PROCESSOR_H */