[deliverable/linux.git] / arch / powerpc / kernel / misc_32.S

/*
 * This file contains miscellaneous low-level functions.
 *    Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
 *
 * Largely rewritten by Cort Dougan (cort@cs.nmt.edu)
 * and Paul Mackerras.
 *
 * kexec bits:
 * Copyright (C) 2002-2003 Eric Biederman  <ebiederm@xmission.com>
 * GameCube/ppc32 port Copyright (C) 2004 Albert Herranz
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * as published by the Free Software Foundation; either version
 * 2 of the License, or (at your option) any later version.
 *
 */

#include <linux/sys.h>
#include <asm/unistd.h>
#include <asm/errno.h>
#include <asm/reg.h>
#include <asm/page.h>
#include <asm/cache.h>
#include <asm/cputable.h>
#include <asm/mmu.h>
#include <asm/ppc_asm.h>
#include <asm/thread_info.h>
#include <asm/asm-offsets.h>
#include <asm/processor.h>
#include <asm/kexec.h>
#include <asm/bug.h>
#include <asm/ptrace.h>

	.text

_GLOBAL(call_do_softirq)
	mflr	r0
	stw	r0,4(r1)
	stwu	r1,THREAD_SIZE-STACK_FRAME_OVERHEAD(r3)
	mr	r1,r3
	bl	__do_softirq
	lwz	r1,0(r1)
	lwz	r0,4(r1)
	mtlr	r0
	blr

_GLOBAL(call_handle_irq)
	mflr	r0
	stw	r0,4(r1)
	mtctr	r6
	stwu	r1,THREAD_SIZE-STACK_FRAME_OVERHEAD(r5)
	mr	r1,r5
	bctrl
	lwz	r1,0(r1)
	lwz	r0,4(r1)
	mtlr	r0
	blr

/*
 * This returns the high 64 bits of the product of two 64-bit numbers.
 */
_GLOBAL(mulhdu)
	cmpwi	r6,0
	cmpwi	cr1,r3,0
	mr	r10,r4
	mulhwu	r4,r4,r5
	beq	1f
	mulhwu	r0,r10,r6
	mullw	r7,r10,r5
	addc	r7,r0,r7
	addze	r4,r4
1:	beqlr	cr1		/* all done if high part of A is 0 */
	mr	r10,r3
	mullw	r9,r3,r5
	mulhwu	r3,r3,r5
	beq	2f
	mullw	r0,r10,r6
	mulhwu	r8,r10,r6
	addc	r7,r0,r7
	adde	r4,r4,r8
	addze	r3,r3
2:	addc	r4,r4,r9
	addze	r3,r3
	blr

/*
 * sub_reloc_offset(x) returns x - reloc_offset().
 */
_GLOBAL(sub_reloc_offset)
	mflr	r0
	bl	1f
1:	mflr	r5
	lis	r4,1b@ha
	addi	r4,r4,1b@l
	subf	r5,r4,r5
	subf	r3,r5,r3
	mtlr	r0
	blr

/*
 * reloc_got2 runs through the .got2 section adding an offset
 * to each entry.
 */
_GLOBAL(reloc_got2)
	mflr	r11
	lis	r7,__got2_start@ha
	addi	r7,r7,__got2_start@l
	lis	r8,__got2_end@ha
	addi	r8,r8,__got2_end@l
	subf	r8,r7,r8
	srwi.	r8,r8,2
	beqlr
	mtctr	r8
	bl	1f
1:	mflr	r0
	lis	r4,1b@ha
	addi	r4,r4,1b@l
	subf	r0,r4,r0
	add	r7,r0,r7
2:	lwz	r0,0(r7)
	add	r0,r0,r3
	stw	r0,0(r7)
	addi	r7,r7,4
	bdnz	2b
	mtlr	r11
	blr

/*
 * call_setup_cpu - call the setup_cpu function for this cpu
 * r3 = data offset, r24 = cpu number
 *
 * Setup function is called with:
 *   r3 = data offset
 *   r4 = ptr to CPU spec (relocated)
 */
_GLOBAL(call_setup_cpu)
	addis	r4,r3,cur_cpu_spec@ha
	addi	r4,r4,cur_cpu_spec@l
	lwz	r4,0(r4)
	add	r4,r4,r3
	lwz	r5,CPU_SPEC_SETUP(r4)
	cmpwi	0,r5,0
	add	r5,r5,r3
	beqlr
	mtctr	r5
	bctr

#if defined(CONFIG_CPU_FREQ_PMAC) && defined(CONFIG_6xx)

/* This gets called by via-pmu.c to switch the PLL selection
 * on 750fx CPU. This function should really be moved to some
 * other place (as most of the cpufreq code in via-pmu
 */
_GLOBAL(low_choose_750fx_pll)
	/* Clear MSR:EE */
	mfmsr	r7
	rlwinm	r0,r7,0,17,15
	mtmsr	r0

	/* If switching to PLL1, disable HID0:BTIC */
	cmplwi	cr0,r3,0
	beq	1f
	mfspr	r5,SPRN_HID0
	rlwinm	r5,r5,0,27,25
	sync
	mtspr	SPRN_HID0,r5
	isync
	sync

1:
	/* Calc new HID1 value */
	mfspr	r4,SPRN_HID1	/* Build a HID1:PS bit from parameter */
	rlwinm	r5,r3,16,15,15	/* Clear out HID1:PS from value read */
	rlwinm	r4,r4,0,16,14	/* Could have I used rlwimi here ? */
	or	r4,r4,r5
	mtspr	SPRN_HID1,r4

	/* Store new HID1 image */
	rlwinm	r6,r1,0,0,(31-THREAD_SHIFT)
	lwz	r6,TI_CPU(r6)
	slwi	r6,r6,2
	addis	r6,r6,nap_save_hid1@ha
	stw	r4,nap_save_hid1@l(r6)

	/* If switching to PLL0, enable HID0:BTIC */
	cmplwi	cr0,r3,0
	bne	1f
	mfspr	r5,SPRN_HID0
	ori	r5,r5,HID0_BTIC
	sync
	mtspr	SPRN_HID0,r5
	isync
	sync

1:
	/* Return */
	mtmsr	r7
	blr

_GLOBAL(low_choose_7447a_dfs)
	/* Clear MSR:EE */
	mfmsr	r7
	rlwinm	r0,r7,0,17,15
	mtmsr	r0
	
	/* Calc new HID1 value */
	mfspr	r4,SPRN_HID1
	insrwi	r4,r3,1,9	/* insert parameter into bit 9 */
	sync
	mtspr	SPRN_HID1,r4
	sync
	isync

	/* Return */
	mtmsr	r7
	blr

#endif /* CONFIG_CPU_FREQ_PMAC && CONFIG_6xx */

/*
 * complement mask on the msr then "or" some values on.
 *     _nmask_and_or_msr(nmask, value_to_or)
 */
_GLOBAL(_nmask_and_or_msr)
	mfmsr	r0		/* Get current msr */
	andc	r0,r0,r3	/* And off the bits set in r3 (first parm) */
	or	r0,r0,r4	/* Or on the bits in r4 (second parm) */
	SYNC			/* Some chip revs have problems here... */
	mtmsr	r0		/* Update machine state */
	isync
	blr			/* Done */

#ifdef CONFIG_40x

/*
 * Do an IO access in real mode
 */
_GLOBAL(real_readb)
	mfmsr	r7
	ori	r0,r7,MSR_DR
	xori	r0,r0,MSR_DR
	sync
	mtmsr	r0
	sync
	isync
	lbz	r3,0(r3)
	sync
	mtmsr	r7
	sync
	isync
	blr

	/*
 * Do an IO access in real mode
 */
_GLOBAL(real_writeb)
	mfmsr	r7
	ori	r0,r7,MSR_DR
	xori	r0,r0,MSR_DR
	sync
	mtmsr	r0
	sync
	isync
	stb	r3,0(r4)
	sync
	mtmsr	r7
	sync
	isync
	blr

#endif /* CONFIG_40x */


/*
 * Flush instruction cache.
 * This is a no-op on the 601.
 */
_GLOBAL(flush_instruction_cache)
#if defined(CONFIG_8xx)
	isync
	lis	r5, IDC_INVALL@h
	mtspr	SPRN_IC_CST, r5
#elif defined(CONFIG_4xx)
#ifdef CONFIG_403GCX
	li      r3, 512
	mtctr   r3
	lis     r4, KERNELBASE@h
1:	iccci   0, r4
	addi    r4, r4, 16
	bdnz    1b
#else
	lis	r3, KERNELBASE@h
	iccci	0,r3
#endif
#elif CONFIG_FSL_BOOKE
BEGIN_FTR_SECTION
	mfspr   r3,SPRN_L1CSR0
	ori     r3,r3,L1CSR0_CFI|L1CSR0_CLFC
	/* msync; isync recommended here */
	mtspr   SPRN_L1CSR0,r3
	isync
	blr
END_FTR_SECTION_IFSET(CPU_FTR_UNIFIED_ID_CACHE)
	mfspr	r3,SPRN_L1CSR1
	ori	r3,r3,L1CSR1_ICFI|L1CSR1_ICLFR
	mtspr	SPRN_L1CSR1,r3
#else
	mfspr	r3,SPRN_PVR
	rlwinm	r3,r3,16,16,31
	cmpwi	0,r3,1
	beqlr			/* for 601, do nothing */
	/* 603/604 processor - use invalidate-all bit in HID0 */
	mfspr	r3,SPRN_HID0
	ori	r3,r3,HID0_ICFI
	mtspr	SPRN_HID0,r3
#endif /* CONFIG_8xx/4xx */
	isync
	blr

/*
 * Write any modified data cache blocks out to memory
 * and invalidate the corresponding instruction cache blocks.
 * This is a no-op on the 601.
 *
 * flush_icache_range(unsigned long start, unsigned long stop)
 */
_KPROBE(__flush_icache_range)
BEGIN_FTR_SECTION
	blr				/* for 601, do nothing */
END_FTR_SECTION_IFSET(CPU_FTR_COHERENT_ICACHE)
	li	r5,L1_CACHE_BYTES-1
	andc	r3,r3,r5
	subf	r4,r3,r4
	add	r4,r4,r5
	srwi.	r4,r4,L1_CACHE_SHIFT
	beqlr
	mtctr	r4
	mr	r6,r3
1:	dcbst	0,r3
	addi	r3,r3,L1_CACHE_BYTES
	bdnz	1b
	sync				/* wait for dcbst's to get to ram */
#ifndef CONFIG_44x
	mtctr	r4
2:	icbi	0,r6
	addi	r6,r6,L1_CACHE_BYTES
	bdnz	2b
#else
	/* Flash invalidate on 44x because we are passed kmapped addresses and
	   this doesn't work for userspace pages due to the virtually tagged
	   icache.  Sigh. */
	iccci	0, r0
#endif
	sync				/* additional sync needed on g4 */
	isync
	blr
/*
 * Write any modified data cache blocks out to memory.
 * Does not invalidate the corresponding cache lines (especially for
 * any corresponding instruction cache).
 *
 * clean_dcache_range(unsigned long start, unsigned long stop)
 */
_GLOBAL(clean_dcache_range)
	li	r5,L1_CACHE_BYTES-1
	andc	r3,r3,r5
	subf	r4,r3,r4
	add	r4,r4,r5
	srwi.	r4,r4,L1_CACHE_SHIFT
	beqlr
	mtctr	r4

1:	dcbst	0,r3
	addi	r3,r3,L1_CACHE_BYTES
	bdnz	1b
	sync				/* wait for dcbst's to get to ram */
	blr

/*
 * Write any modified data cache blocks out to memory and invalidate them.
 * Does not invalidate the corresponding instruction cache blocks.
 *
 * flush_dcache_range(unsigned long start, unsigned long stop)
 */
_GLOBAL(flush_dcache_range)
	li	r5,L1_CACHE_BYTES-1
	andc	r3,r3,r5
	subf	r4,r3,r4
	add	r4,r4,r5
	srwi.	r4,r4,L1_CACHE_SHIFT
	beqlr
	mtctr	r4

1:	dcbf	0,r3
	addi	r3,r3,L1_CACHE_BYTES
	bdnz	1b
	sync				/* wait for dcbst's to get to ram */
	blr

/*
 * Like above, but invalidate the D-cache.  This is used by the 8xx
 * to invalidate the cache so the PPC core doesn't get stale data
 * from the CPM (no cache snooping here :-).
 *
 * invalidate_dcache_range(unsigned long start, unsigned long stop)
 */
_GLOBAL(invalidate_dcache_range)
	li	r5,L1_CACHE_BYTES-1
	andc	r3,r3,r5
	subf	r4,r3,r4
	add	r4,r4,r5
	srwi.	r4,r4,L1_CACHE_SHIFT
	beqlr
	mtctr	r4

1:	dcbi	0,r3
	addi	r3,r3,L1_CACHE_BYTES
	bdnz	1b
	sync				/* wait for dcbi's to get to ram */
	blr

/*
 * Flush a particular page from the data cache to RAM.
 * Note: this is necessary because the instruction cache does *not*
 * snoop from the data cache.
 * This is a no-op on the 601 which has a unified cache.
 *
 *	void __flush_dcache_icache(void *page)
 */
_GLOBAL(__flush_dcache_icache)
BEGIN_FTR_SECTION
	blr
END_FTR_SECTION_IFSET(CPU_FTR_COHERENT_ICACHE)
	rlwinm	r3,r3,0,0,31-PAGE_SHIFT		/* Get page base address */
	li	r4,PAGE_SIZE/L1_CACHE_BYTES	/* Number of lines in a page */
	mtctr	r4
	mr	r6,r3
0:	dcbst	0,r3				/* Write line to ram */
	addi	r3,r3,L1_CACHE_BYTES
	bdnz	0b
	sync
#ifdef CONFIG_44x
	/* We don't flush the icache on 44x. Those have a virtual icache
	 * and we don't have access to the virtual address here (it's
	 * not the page vaddr but where it's mapped in user space). The
	 * flushing of the icache on these is handled elsewhere, when
	 * a change in the address space occurs, before returning to
	 * user space
	 */
BEGIN_MMU_FTR_SECTION
	blr
END_MMU_FTR_SECTION_IFSET(MMU_FTR_TYPE_44x)
#endif /* CONFIG_44x */
	mtctr	r4
1:	icbi	0,r6
	addi	r6,r6,L1_CACHE_BYTES
	bdnz	1b
	sync
	isync
	blr

#ifndef CONFIG_BOOKE
/*
 * Flush a particular page from the data cache to RAM, identified
 * by its physical address.  We turn off the MMU so we can just use
 * the physical address (this may be a highmem page without a kernel
 * mapping).
 *
 *	void __flush_dcache_icache_phys(unsigned long physaddr)
 */
_GLOBAL(__flush_dcache_icache_phys)
BEGIN_FTR_SECTION
	blr					/* for 601, do nothing */
END_FTR_SECTION_IFSET(CPU_FTR_COHERENT_ICACHE)
	mfmsr	r10
	rlwinm	r0,r10,0,28,26			/* clear DR */
	mtmsr	r0
	isync
	rlwinm	r3,r3,0,0,31-PAGE_SHIFT		/* Get page base address */
	li	r4,PAGE_SIZE/L1_CACHE_BYTES	/* Number of lines in a page */
	mtctr	r4
	mr	r6,r3
0:	dcbst	0,r3				/* Write line to ram */
	addi	r3,r3,L1_CACHE_BYTES
	bdnz	0b
	sync
	mtctr	r4
1:	icbi	0,r6
	addi	r6,r6,L1_CACHE_BYTES
	bdnz	1b
	sync
	mtmsr	r10				/* restore DR */
	isync
	blr
#endif /* CONFIG_BOOKE */

/*
 * Clear pages using the dcbz instruction, which doesn't cause any
 * memory traffic (except to write out any cache lines which get
 * displaced).  This only works on cacheable memory.
 *
 * void clear_pages(void *page, int order) ;
 */
_GLOBAL(clear_pages)
	li	r0,PAGE_SIZE/L1_CACHE_BYTES
	slw	r0,r0,r4
	mtctr	r0
1:	dcbz	0,r3
	addi	r3,r3,L1_CACHE_BYTES
	bdnz	1b
	blr

/*
 * Copy a whole page.  We use the dcbz instruction on the destination
 * to reduce memory traffic (it eliminates the unnecessary reads of
 * the destination into cache).  This requires that the destination
 * is cacheable.
 */
#define COPY_16_BYTES		\
	lwz	r6,4(r4);	\
	lwz	r7,8(r4);	\
	lwz	r8,12(r4);	\
	lwzu	r9,16(r4);	\
	stw	r6,4(r3);	\
	stw	r7,8(r3);	\
	stw	r8,12(r3);	\
	stwu	r9,16(r3)

_GLOBAL(copy_page)
	addi	r3,r3,-4
	addi	r4,r4,-4

	li	r5,4

#if MAX_COPY_PREFETCH > 1
	li	r0,MAX_COPY_PREFETCH
	li	r11,4
	mtctr	r0
11:	dcbt	r11,r4
	addi	r11,r11,L1_CACHE_BYTES
	bdnz	11b
#else /* MAX_COPY_PREFETCH == 1 */
	dcbt	r5,r4
	li	r11,L1_CACHE_BYTES+4
#endif /* MAX_COPY_PREFETCH */
	li	r0,PAGE_SIZE/L1_CACHE_BYTES - MAX_COPY_PREFETCH
	crclr	4*cr0+eq
2:
	mtctr	r0
1:
	dcbt	r11,r4
	dcbz	r5,r3
	COPY_16_BYTES
#if L1_CACHE_BYTES >= 32
	COPY_16_BYTES
#if L1_CACHE_BYTES >= 64
	COPY_16_BYTES
	COPY_16_BYTES
#if L1_CACHE_BYTES >= 128
	COPY_16_BYTES
	COPY_16_BYTES
	COPY_16_BYTES
	COPY_16_BYTES
#endif
#endif
#endif
	bdnz	1b
	beqlr
	crnot	4*cr0+eq,4*cr0+eq
	li	r0,MAX_COPY_PREFETCH
	li	r11,4
	b	2b

/*
 * void atomic_clear_mask(atomic_t mask, atomic_t *addr)
 * void atomic_set_mask(atomic_t mask, atomic_t *addr);
 */
_GLOBAL(atomic_clear_mask)
10:	lwarx	r5,0,r4
	andc	r5,r5,r3
	PPC405_ERR77(0,r4)
	stwcx.	r5,0,r4
	bne-	10b
	blr
_GLOBAL(atomic_set_mask)
10:	lwarx	r5,0,r4
	or	r5,r5,r3
	PPC405_ERR77(0,r4)
	stwcx.	r5,0,r4
	bne-	10b
	blr

/*
 * Extended precision shifts.
 *
 * Updated to be valid for shift counts from 0 to 63 inclusive.
 * -- Gabriel
 *
 * R3/R4 has 64 bit value
 * R5    has shift count
 * result in R3/R4
 *
 *  ashrdi3: arithmetic right shift (sign propagation)	
 *  lshrdi3: logical right shift
 *  ashldi3: left shift
 */
_GLOBAL(__ashrdi3)
	subfic	r6,r5,32
	srw	r4,r4,r5	# LSW = count > 31 ? 0 : LSW >> count
	addi	r7,r5,32	# could be xori, or addi with -32
	slw	r6,r3,r6	# t1 = count > 31 ? 0 : MSW << (32-count)
	rlwinm	r8,r7,0,32	# t3 = (count < 32) ? 32 : 0
	sraw	r7,r3,r7	# t2 = MSW >> (count-32)
	or	r4,r4,r6	# LSW |= t1
	slw	r7,r7,r8	# t2 = (count < 32) ? 0 : t2
	sraw	r3,r3,r5	# MSW = MSW >> count
	or	r4,r4,r7	# LSW |= t2
	blr

_GLOBAL(__ashldi3)
	subfic	r6,r5,32
	slw	r3,r3,r5	# MSW = count > 31 ? 0 : MSW << count
	addi	r7,r5,32	# could be xori, or addi with -32
	srw	r6,r4,r6	# t1 = count > 31 ? 0 : LSW >> (32-count)
	slw	r7,r4,r7	# t2 = count < 32 ? 0 : LSW << (count-32)
	or	r3,r3,r6	# MSW |= t1
	slw	r4,r4,r5	# LSW = LSW << count
	or	r3,r3,r7	# MSW |= t2
	blr

_GLOBAL(__lshrdi3)
	subfic	r6,r5,32
	srw	r4,r4,r5	# LSW = count > 31 ? 0 : LSW >> count
	addi	r7,r5,32	# could be xori, or addi with -32
	slw	r6,r3,r6	# t1 = count > 31 ? 0 : MSW << (32-count)
	srw	r7,r3,r7	# t2 = count < 32 ? 0 : MSW >> (count-32)
	or	r4,r4,r6	# LSW |= t1
	srw	r3,r3,r5	# MSW = MSW >> count
	or	r4,r4,r7	# LSW |= t2
	blr

/*
 * 64-bit comparison: __ucmpdi2(u64 a, u64 b)
 * Returns 0 if a < b, 1 if a == b, 2 if a > b.
 */
_GLOBAL(__ucmpdi2)
	cmplw	r3,r5
	li	r3,1
	bne	1f
	cmplw	r4,r6
	beqlr
1:	li	r3,0
	bltlr
	li	r3,2
	blr

_GLOBAL(abs)
	srawi	r4,r3,31
	xor	r3,r3,r4
	sub	r3,r3,r4
	blr

/*
 * Create a kernel thread
 *   kernel_thread(fn, arg, flags)
 */
_GLOBAL(kernel_thread)
	stwu	r1,-16(r1)
	stw	r30,8(r1)
	stw	r31,12(r1)
	mr	r30,r3		/* function */
	mr	r31,r4		/* argument */
	ori	r3,r5,CLONE_VM	/* flags */
	oris	r3,r3,CLONE_UNTRACED>>16
	li	r4,0		/* new sp (unused) */
	li	r0,__NR_clone
	sc
	bns+	1f		/* did system call indicate error? */
	neg	r3,r3		/* if so, make return code negative */
1:	cmpwi	0,r3,0		/* parent or child? */
	bne	2f		/* return if parent */
	li	r0,0		/* make top-level stack frame */
	stwu	r0,-16(r1)
	mtlr	r30		/* fn addr in lr */
	mr	r3,r31		/* load arg and call fn */
	PPC440EP_ERR42
	blrl
	li	r0,__NR_exit	/* exit if function returns */
	li	r3,0
	sc
2:	lwz	r30,8(r1)
	lwz	r31,12(r1)
	addi	r1,r1,16
	blr

#ifdef CONFIG_SMP
_GLOBAL(start_secondary_resume)
	/* Reset stack */
	rlwinm	r1,r1,0,0,(31-THREAD_SHIFT)	/* current_thread_info() */
	addi	r1,r1,THREAD_SIZE-STACK_FRAME_OVERHEAD
	li	r3,0
	stw	r3,0(r1)		/* Zero the stack frame pointer	*/
	bl	start_secondary
	b	.
#endif /* CONFIG_SMP */
	
/*
 * This routine is just here to keep GCC happy - sigh...
 */
_GLOBAL(__main)
	blr

#ifdef CONFIG_KEXEC
	/*
	 * Must be relocatable PIC code callable as a C function.
	 */
	.globl relocate_new_kernel
relocate_new_kernel:
	/* r3 = page_list   */
	/* r4 = reboot_code_buffer */
	/* r5 = start_address      */

#ifdef CONFIG_FSL_BOOKE

	mr	r29, r3
	mr	r30, r4
	mr	r31, r5

#define ENTRY_MAPPING_KEXEC_SETUP
#include "fsl_booke_entry_mapping.S"
#undef ENTRY_MAPPING_KEXEC_SETUP

	mr      r3, r29
	mr      r4, r30
	mr      r5, r31

	li	r0, 0
#else
	li	r0, 0

	/*
	 * Set Machine Status Register to a known status,
	 * switch the MMU off and jump to 1: in a single step.
	 */

	mr	r8, r0
	ori     r8, r8, MSR_RI|MSR_ME
	mtspr	SPRN_SRR1, r8
	addi	r8, r4, 1f - relocate_new_kernel
	mtspr	SPRN_SRR0, r8
	sync
	rfi

1:
#endif
	/* from this point address translation is turned off */
	/* and interrupts are disabled */

	/* set a new stack at the bottom of our page... */
	/* (not really needed now) */
	addi	r1, r4, KEXEC_CONTROL_PAGE_SIZE - 8 /* for LR Save+Back Chain */
	stw	r0, 0(r1)

	/* Do the copies */
	li	r6, 0 /* checksum */
	mr	r0, r3
	b	1f

0:	/* top, read another word for the indirection page */
	lwzu	r0, 4(r3)

1:
	/* is it a destination page? (r8) */
	rlwinm.	r7, r0, 0, 31, 31 /* IND_DESTINATION (1<<0) */
	beq	2f

	rlwinm	r8, r0, 0, 0, 19 /* clear kexec flags, page align */
	b	0b

2:	/* is it an indirection page? (r3) */
	rlwinm.	r7, r0, 0, 30, 30 /* IND_INDIRECTION (1<<1) */
	beq	2f

	rlwinm	r3, r0, 0, 0, 19 /* clear kexec flags, page align */
	subi	r3, r3, 4
	b	0b

2:	/* are we done? */
	rlwinm.	r7, r0, 0, 29, 29 /* IND_DONE (1<<2) */
	beq	2f
	b	3f

2:	/* is it a source page? (r9) */
	rlwinm.	r7, r0, 0, 28, 28 /* IND_SOURCE (1<<3) */
	beq	0b

	rlwinm	r9, r0, 0, 0, 19 /* clear kexec flags, page align */

	li	r7, PAGE_SIZE / 4
	mtctr   r7
	subi    r9, r9, 4
	subi    r8, r8, 4
9:
	lwzu    r0, 4(r9)  /* do the copy */
	xor	r6, r6, r0
	stwu    r0, 4(r8)
	dcbst	0, r8
	sync
	icbi	0, r8
	bdnz    9b

	addi    r9, r9, 4
	addi    r8, r8, 4
	b	0b

3:

	/* To be certain of avoiding problems with self-modifying code
	 * execute a serializing instruction here.
	 */
	isync
	sync

	mfspr	r3, SPRN_PIR /* current core we are running on */
	mr	r4, r5 /* load physical address of chunk called */

	/* jump to the entry point, usually the setup routine */
	mtlr	r5
	blrl

1:	b	1b

relocate_new_kernel_end:

	.globl relocate_new_kernel_size
relocate_new_kernel_size:
	.long relocate_new_kernel_end - relocate_new_kernel
#endif
Commit	Line	Data
9994a338 PM	1	/*
	2	* This file contains miscellaneous low-level functions.
	3	* Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
	4	*
	5	* Largely rewritten by Cort Dougan (cort@cs.nmt.edu)
	6	* and Paul Mackerras.
	7	*
3d1229d6 ME	8	* kexec bits:
	9	* Copyright (C) 2002-2003 Eric Biederman <ebiederm@xmission.com>
	10	* GameCube/ppc32 port Copyright (C) 2004 Albert Herranz
	11	*
9994a338 PM	12	* This program is free software; you can redistribute it and/or
	13	* modify it under the terms of the GNU General Public License
	14	* as published by the Free Software Foundation; either version
	15	* 2 of the License, or (at your option) any later version.
	16	*
	17	*/
	18
9994a338 PM	19	#include <linux/sys.h>
	20	#include <asm/unistd.h>
	21	#include <asm/errno.h>
	22	#include <asm/reg.h>
	23	#include <asm/page.h>
	24	#include <asm/cache.h>
	25	#include <asm/cputable.h>
	26	#include <asm/mmu.h>
	27	#include <asm/ppc_asm.h>
	28	#include <asm/thread_info.h>
	29	#include <asm/asm-offsets.h>
3d1229d6 ME	30	#include <asm/processor.h>
3d1229d6 ME	31	#include <asm/kexec.h>
f048aace	32	#include <asm/bug.h>
46f52210	33	#include <asm/ptrace.h>
9994a338 PM	34
	35	.text
	36
85218827 KG	37	_GLOBAL(call_do_softirq)
	38	mflr r0
	39	stw r0,4(r1)
	40	stwu r1,THREAD_SIZE-STACK_FRAME_OVERHEAD(r3)
	41	mr r1,r3
	42	bl __do_softirq
	43	lwz r1,0(r1)
	44	lwz r0,4(r1)
	45	mtlr r0
	46	blr
	47
	48	_GLOBAL(call_handle_irq)
	49	mflr r0
	50	stw r0,4(r1)
	51	mtctr r6
	52	stwu r1,THREAD_SIZE-STACK_FRAME_OVERHEAD(r5)
	53	mr r1,r5
	54	bctrl
	55	lwz r1,0(r1)
	56	lwz r0,4(r1)
	57	mtlr r0
	58	blr
85218827	59
f2783c15 PM	60	/*
	61	* This returns the high 64 bits of the product of two 64-bit numbers.
	62	*/
	63	_GLOBAL(mulhdu)
	64	cmpwi r6,0
	65	cmpwi cr1,r3,0
	66	mr r10,r4
	67	mulhwu r4,r4,r5
	68	beq 1f
	69	mulhwu r0,r10,r6
	70	mullw r7,r10,r5
	71	addc r7,r0,r7
	72	addze r4,r4
	73	1: beqlr cr1 /* all done if high part of A is 0 */
	74	mr r10,r3
	75	mullw r9,r3,r5
	76	mulhwu r3,r3,r5
	77	beq 2f
	78	mullw r0,r10,r6
	79	mulhwu r8,r10,r6
	80	addc r7,r0,r7
	81	adde r4,r4,r8
	82	addze r3,r3
	83	2: addc r4,r4,r9
	84	addze r3,r3
	85	blr
	86
9994a338 PM	87	/*
	88	* sub_reloc_offset(x) returns x - reloc_offset().
	89	*/
	90	_GLOBAL(sub_reloc_offset)
	91	mflr r0
	92	bl 1f
	93	1: mflr r5
	94	lis r4,1b@ha
	95	addi r4,r4,1b@l
	96	subf r5,r4,r5
	97	subf r3,r5,r3
	98	mtlr r0
	99	blr
	100
	101	/*
	102	* reloc_got2 runs through the .got2 section adding an offset
	103	* to each entry.
	104	*/
	105	_GLOBAL(reloc_got2)
	106	mflr r11
	107	lis r7,__got2_start@ha
	108	addi r7,r7,__got2_start@l
	109	lis r8,__got2_end@ha
	110	addi r8,r8,__got2_end@l
	111	subf r8,r7,r8
	112	srwi. r8,r8,2
	113	beqlr
	114	mtctr r8
	115	bl 1f
	116	1: mflr r0
	117	lis r4,1b@ha
	118	addi r4,r4,1b@l
	119	subf r0,r4,r0
	120	add r7,r0,r7
	121	2: lwz r0,0(r7)
	122	add r0,r0,r3
	123	stw r0,0(r7)
	124	addi r7,r7,4
	125	bdnz 2b
	126	mtlr r11
	127	blr
	128
9994a338 PM	129	/*
	130	* call_setup_cpu - call the setup_cpu function for this cpu
	131	* r3 = data offset, r24 = cpu number
	132	*
	133	* Setup function is called with:
	134	* r3 = data offset
	135	* r4 = ptr to CPU spec (relocated)
	136	*/
	137	_GLOBAL(call_setup_cpu)
	138	addis r4,r3,cur_cpu_spec@ha
	139	addi r4,r4,cur_cpu_spec@l
	140	lwz r4,0(r4)
	141	add r4,r4,r3
	142	lwz r5,CPU_SPEC_SETUP(r4)
b26f100d	143	cmpwi 0,r5,0
9994a338 PM	144	add r5,r5,r3
	145	beqlr
	146	mtctr r5
	147	bctr
	148
	149	#if defined(CONFIG_CPU_FREQ_PMAC) && defined(CONFIG_6xx)
	150
	151	/* This gets called by via-pmu.c to switch the PLL selection
	152	* on 750fx CPU. This function should really be moved to some
	153	* other place (as most of the cpufreq code in via-pmu
	154	*/
	155	_GLOBAL(low_choose_750fx_pll)
	156	/* Clear MSR:EE */
	157	mfmsr r7
	158	rlwinm r0,r7,0,17,15
	159	mtmsr r0
	160
	161	/* If switching to PLL1, disable HID0:BTIC */
	162	cmplwi cr0,r3,0
	163	beq 1f
	164	mfspr r5,SPRN_HID0
	165	rlwinm r5,r5,0,27,25
	166	sync
	167	mtspr SPRN_HID0,r5
	168	isync
	169	sync
	170
	171	1:
	172	/* Calc new HID1 value */
	173	mfspr r4,SPRN_HID1 /* Build a HID1:PS bit from parameter */
	174	rlwinm r5,r3,16,15,15 /* Clear out HID1:PS from value read */
	175	rlwinm r4,r4,0,16,14 /* Could have I used rlwimi here ? */
	176	or r4,r4,r5
	177	mtspr SPRN_HID1,r4
	178
	179	/* Store new HID1 image */
f608600e	180	rlwinm r6,r1,0,0,(31-THREAD_SHIFT)
9994a338 PM	181	lwz r6,TI_CPU(r6)
	182	slwi r6,r6,2
	183	addis r6,r6,nap_save_hid1@ha
	184	stw r4,nap_save_hid1@l(r6)
	185
	186	/* If switching to PLL0, enable HID0:BTIC */
	187	cmplwi cr0,r3,0
	188	bne 1f
	189	mfspr r5,SPRN_HID0
	190	ori r5,r5,HID0_BTIC
	191	sync
	192	mtspr SPRN_HID0,r5
	193	isync
	194	sync
	195
	196	1:
	197	/* Return */
	198	mtmsr r7
	199	blr
	200
	201	_GLOBAL(low_choose_7447a_dfs)
	202	/* Clear MSR:EE */
	203	mfmsr r7
	204	rlwinm r0,r7,0,17,15
	205	mtmsr r0
	206
	207	/* Calc new HID1 value */
	208	mfspr r4,SPRN_HID1
	209	insrwi r4,r3,1,9 /* insert parameter into bit 9 */
	210	sync
	211	mtspr SPRN_HID1,r4
	212	sync
	213	isync
	214
	215	/* Return */
	216	mtmsr r7
	217	blr
	218
	219	#endif /* CONFIG_CPU_FREQ_PMAC && CONFIG_6xx */
	220
	221	/*
	222	* complement mask on the msr then "or" some values on.
	223	* _nmask_and_or_msr(nmask, value_to_or)
	224	*/
	225	_GLOBAL(_nmask_and_or_msr)
	226	mfmsr r0 /* Get current msr */
	227	andc r0,r0,r3 /* And off the bits set in r3 (first parm) */
	228	or r0,r0,r4 /* Or on the bits in r4 (second parm) */
	229	SYNC /* Some chip revs have problems here... */
	230	mtmsr r0 /* Update machine state */
	231	isync
	232	blr /* Done */
	233
9dae8afd BH	234	#ifdef CONFIG_40x
	235
	236	/*
	237	* Do an IO access in real mode
	238	*/
	239	_GLOBAL(real_readb)
	240	mfmsr r7
	241	ori r0,r7,MSR_DR
	242	xori r0,r0,MSR_DR
	243	sync
	244	mtmsr r0
	245	sync
	246	isync
	247	lbz r3,0(r3)
	248	sync
	249	mtmsr r7
	250	sync
	251	isync
	252	blr
	253
	254	/*
	255	* Do an IO access in real mode
	256	*/
	257	_GLOBAL(real_writeb)
	258	mfmsr r7
	259	ori r0,r7,MSR_DR
	260	xori r0,r0,MSR_DR
	261	sync
	262	mtmsr r0
	263	sync
	264	isync
	265	stb r3,0(r4)
	266	sync
	267	mtmsr r7
	268	sync
	269	isync
	270	blr
	271
	272	#endif /* CONFIG_40x */
9994a338	273
0ba3418b	274
9994a338 PM	275	/*
	276	* Flush instruction cache.
	277	* This is a no-op on the 601.
	278	*/
	279	_GLOBAL(flush_instruction_cache)
	280	#if defined(CONFIG_8xx)
	281	isync
	282	lis r5, IDC_INVALL@h
	283	mtspr SPRN_IC_CST, r5
	284	#elif defined(CONFIG_4xx)
	285	#ifdef CONFIG_403GCX
	286	li r3, 512
	287	mtctr r3
	288	lis r4, KERNELBASE@h
	289	1: iccci 0, r4
	290	addi r4, r4, 16
	291	bdnz 1b
	292	#else
	293	lis r3, KERNELBASE@h
	294	iccci 0,r3
	295	#endif
	296	#elif CONFIG_FSL_BOOKE
	297	BEGIN_FTR_SECTION
	298	mfspr r3,SPRN_L1CSR0
	299	ori r3,r3,L1CSR0_CFI\|L1CSR0_CLFC
	300	/* msync; isync recommended here */
	301	mtspr SPRN_L1CSR0,r3
	302	isync
	303	blr
4508dc21	304	END_FTR_SECTION_IFSET(CPU_FTR_UNIFIED_ID_CACHE)
9994a338 PM	305	mfspr r3,SPRN_L1CSR1
	306	ori r3,r3,L1CSR1_ICFI\|L1CSR1_ICLFR
	307	mtspr SPRN_L1CSR1,r3
	308	#else
	309	mfspr r3,SPRN_PVR
	310	rlwinm r3,r3,16,16,31
	311	cmpwi 0,r3,1
	312	beqlr /* for 601, do nothing */
	313	/* 603/604 processor - use invalidate-all bit in HID0 */
	314	mfspr r3,SPRN_HID0
	315	ori r3,r3,HID0_ICFI
	316	mtspr SPRN_HID0,r3
	317	#endif /* CONFIG_8xx/4xx */
	318	isync
	319	blr
	320
	321	/*
	322	* Write any modified data cache blocks out to memory
	323	* and invalidate the corresponding instruction cache blocks.
	324	* This is a no-op on the 601.
	325	*
	326	* flush_icache_range(unsigned long start, unsigned long stop)
	327	*/
b76e59d1	328	_KPROBE(__flush_icache_range)
9994a338 PM	329	BEGIN_FTR_SECTION
9994a338 PM	330	blr /* for 601, do nothing */
4508dc21	331	END_FTR_SECTION_IFSET(CPU_FTR_COHERENT_ICACHE)
7dffb720	332	li r5,L1_CACHE_BYTES-1
9994a338 PM	333	andc r3,r3,r5
	334	subf r4,r3,r4
	335	add r4,r4,r5
7dffb720	336	srwi. r4,r4,L1_CACHE_SHIFT
9994a338 PM	337	beqlr
	338	mtctr r4
	339	mr r6,r3
	340	1: dcbst 0,r3
7dffb720	341	addi r3,r3,L1_CACHE_BYTES
9994a338 PM	342	bdnz 1b
9994a338 PM	343	sync /* wait for dcbst's to get to ram */
14d75752	344	#ifndef CONFIG_44x
9994a338 PM	345	mtctr r4
9994a338 PM	346	2: icbi 0,r6
7dffb720	347	addi r6,r6,L1_CACHE_BYTES
9994a338	348	bdnz 2b
14d75752 JB	349	#else
	350	/* Flash invalidate on 44x because we are passed kmapped addresses and
	351	this doesn't work for userspace pages due to the virtually tagged
	352	icache. Sigh. */
	353	iccci 0, r0
	354	#endif
9994a338 PM	355	sync /* additional sync needed on g4 */
	356	isync
	357	blr
	358	/*
	359	* Write any modified data cache blocks out to memory.
	360	* Does not invalidate the corresponding cache lines (especially for
	361	* any corresponding instruction cache).
	362	*
	363	* clean_dcache_range(unsigned long start, unsigned long stop)
	364	*/
	365	_GLOBAL(clean_dcache_range)
7dffb720	366	li r5,L1_CACHE_BYTES-1
9994a338 PM	367	andc r3,r3,r5
	368	subf r4,r3,r4
	369	add r4,r4,r5
7dffb720	370	srwi. r4,r4,L1_CACHE_SHIFT
9994a338 PM	371	beqlr
	372	mtctr r4
	373
	374	1: dcbst 0,r3
7dffb720	375	addi r3,r3,L1_CACHE_BYTES
9994a338 PM	376	bdnz 1b
	377	sync /* wait for dcbst's to get to ram */
	378	blr
	379
	380	/*
	381	* Write any modified data cache blocks out to memory and invalidate them.
	382	* Does not invalidate the corresponding instruction cache blocks.
	383	*
	384	* flush_dcache_range(unsigned long start, unsigned long stop)
	385	*/
	386	_GLOBAL(flush_dcache_range)
7dffb720	387	li r5,L1_CACHE_BYTES-1
9994a338 PM	388	andc r3,r3,r5
	389	subf r4,r3,r4
	390	add r4,r4,r5
7dffb720	391	srwi. r4,r4,L1_CACHE_SHIFT
9994a338 PM	392	beqlr
	393	mtctr r4
	394
	395	1: dcbf 0,r3
7dffb720	396	addi r3,r3,L1_CACHE_BYTES
9994a338 PM	397	bdnz 1b
	398	sync /* wait for dcbst's to get to ram */
	399	blr
	400
	401	/*
	402	* Like above, but invalidate the D-cache. This is used by the 8xx
	403	* to invalidate the cache so the PPC core doesn't get stale data
	404	* from the CPM (no cache snooping here :-).
	405	*
	406	* invalidate_dcache_range(unsigned long start, unsigned long stop)
	407	*/
	408	_GLOBAL(invalidate_dcache_range)
7dffb720	409	li r5,L1_CACHE_BYTES-1
9994a338 PM	410	andc r3,r3,r5
	411	subf r4,r3,r4
	412	add r4,r4,r5
7dffb720	413	srwi. r4,r4,L1_CACHE_SHIFT
9994a338 PM	414	beqlr
	415	mtctr r4
	416
	417	1: dcbi 0,r3
7dffb720	418	addi r3,r3,L1_CACHE_BYTES
9994a338 PM	419	bdnz 1b
	420	sync /* wait for dcbi's to get to ram */
	421	blr
	422
9994a338 PM	423	/*
	424	* Flush a particular page from the data cache to RAM.
	425	* Note: this is necessary because the instruction cache does not
	426	* snoop from the data cache.
	427	* This is a no-op on the 601 which has a unified cache.
	428	*
	429	* void __flush_dcache_icache(void *page)
	430	*/
	431	_GLOBAL(__flush_dcache_icache)
	432	BEGIN_FTR_SECTION
4508dc21 DG	433	blr
4508dc21 DG	434	END_FTR_SECTION_IFSET(CPU_FTR_COHERENT_ICACHE)
ca9153a3 IY	435	rlwinm r3,r3,0,0,31-PAGE_SHIFT /* Get page base address */
ca9153a3 IY	436	li r4,PAGE_SIZE/L1_CACHE_BYTES /* Number of lines in a page */
9994a338 PM	437	mtctr r4
	438	mr r6,r3
	439	0: dcbst 0,r3 /* Write line to ram */
7dffb720	440	addi r3,r3,L1_CACHE_BYTES
9994a338 PM	441	bdnz 0b
9994a338 PM	442	sync
e7f75ad0	443	#ifdef CONFIG_44x
b98ac05d BH	444	/* We don't flush the icache on 44x. Those have a virtual icache
	445	* and we don't have access to the virtual address here (it's
	446	* not the page vaddr but where it's mapped in user space). The
	447	* flushing of the icache on these is handled elsewhere, when
	448	* a change in the address space occurs, before returning to
	449	* user space
	450	*/
e7f75ad0 DK	451	BEGIN_MMU_FTR_SECTION
	452	blr
	453	END_MMU_FTR_SECTION_IFSET(MMU_FTR_TYPE_44x)
	454	#endif /* CONFIG_44x */
9994a338 PM	455	mtctr r4
9994a338 PM	456	1: icbi 0,r6
7dffb720	457	addi r6,r6,L1_CACHE_BYTES
9994a338 PM	458	bdnz 1b
	459	sync
	460	isync
	461	blr
	462
e7f75ad0	463	#ifndef CONFIG_BOOKE
9994a338 PM	464	/*
	465	* Flush a particular page from the data cache to RAM, identified
	466	* by its physical address. We turn off the MMU so we can just use
	467	* the physical address (this may be a highmem page without a kernel
	468	* mapping).
	469	*
	470	* void __flush_dcache_icache_phys(unsigned long physaddr)
	471	*/
	472	_GLOBAL(__flush_dcache_icache_phys)
	473	BEGIN_FTR_SECTION
	474	blr /* for 601, do nothing */
4508dc21	475	END_FTR_SECTION_IFSET(CPU_FTR_COHERENT_ICACHE)
9994a338 PM	476	mfmsr r10
	477	rlwinm r0,r10,0,28,26 /* clear DR */
	478	mtmsr r0
	479	isync
ca9153a3 IY	480	rlwinm r3,r3,0,0,31-PAGE_SHIFT /* Get page base address */
ca9153a3 IY	481	li r4,PAGE_SIZE/L1_CACHE_BYTES /* Number of lines in a page */
9994a338 PM	482	mtctr r4
	483	mr r6,r3
	484	0: dcbst 0,r3 /* Write line to ram */
7dffb720	485	addi r3,r3,L1_CACHE_BYTES
9994a338 PM	486	bdnz 0b
	487	sync
	488	mtctr r4
	489	1: icbi 0,r6
7dffb720	490	addi r6,r6,L1_CACHE_BYTES
9994a338 PM	491	bdnz 1b
	492	sync
	493	mtmsr r10 /* restore DR */
	494	isync
	495	blr
e7f75ad0	496	#endif /* CONFIG_BOOKE */
9994a338 PM	497
	498	/*
	499	* Clear pages using the dcbz instruction, which doesn't cause any
	500	* memory traffic (except to write out any cache lines which get
	501	* displaced). This only works on cacheable memory.
	502	*
	503	* void clear_pages(void *page, int order) ;
	504	*/
	505	_GLOBAL(clear_pages)
ca9153a3	506	li r0,PAGE_SIZE/L1_CACHE_BYTES
9994a338 PM	507	slw r0,r0,r4
9994a338 PM	508	mtctr r0
9994a338	509	1: dcbz 0,r3
7dffb720	510	addi r3,r3,L1_CACHE_BYTES
9994a338 PM	511	bdnz 1b
	512	blr
	513
	514	/*
	515	* Copy a whole page. We use the dcbz instruction on the destination
	516	* to reduce memory traffic (it eliminates the unnecessary reads of
	517	* the destination into cache). This requires that the destination
	518	* is cacheable.
	519	*/
	520	#define COPY_16_BYTES \
	521	lwz r6,4(r4); \
	522	lwz r7,8(r4); \
	523	lwz r8,12(r4); \
	524	lwzu r9,16(r4); \
	525	stw r6,4(r3); \
	526	stw r7,8(r3); \
	527	stw r8,12(r3); \
	528	stwu r9,16(r3)
	529
	530	_GLOBAL(copy_page)
	531	addi r3,r3,-4
	532	addi r4,r4,-4
	533
9994a338 PM	534	li r5,4
	535
	536	#if MAX_COPY_PREFETCH > 1
	537	li r0,MAX_COPY_PREFETCH
	538	li r11,4
	539	mtctr r0
	540	11: dcbt r11,r4
7dffb720	541	addi r11,r11,L1_CACHE_BYTES
9994a338 PM	542	bdnz 11b
	543	#else /* MAX_COPY_PREFETCH == 1 */
	544	dcbt r5,r4
7dffb720	545	li r11,L1_CACHE_BYTES+4
9994a338	546	#endif /* MAX_COPY_PREFETCH */
ca9153a3	547	li r0,PAGE_SIZE/L1_CACHE_BYTES - MAX_COPY_PREFETCH
9994a338 PM	548	crclr 4*cr0+eq
	549	2:
	550	mtctr r0
	551	1:
	552	dcbt r11,r4
	553	dcbz r5,r3
	554	COPY_16_BYTES
7dffb720	555	#if L1_CACHE_BYTES >= 32
9994a338	556	COPY_16_BYTES
7dffb720	557	#if L1_CACHE_BYTES >= 64
9994a338 PM	558	COPY_16_BYTES
9994a338 PM	559	COPY_16_BYTES
7dffb720	560	#if L1_CACHE_BYTES >= 128
9994a338 PM	561	COPY_16_BYTES
	562	COPY_16_BYTES
	563	COPY_16_BYTES
	564	COPY_16_BYTES
	565	#endif
	566	#endif
	567	#endif
	568	bdnz 1b
	569	beqlr
	570	crnot 4cr0+eq,4cr0+eq
	571	li r0,MAX_COPY_PREFETCH
	572	li r11,4
	573	b 2b
9994a338 PM	574
	575	/*
	576	* void atomic_clear_mask(atomic_t mask, atomic_t *addr)
	577	* void atomic_set_mask(atomic_t mask, atomic_t *addr);
	578	*/
	579	_GLOBAL(atomic_clear_mask)
	580	10: lwarx r5,0,r4
	581	andc r5,r5,r3
	582	PPC405_ERR77(0,r4)
	583	stwcx. r5,0,r4
	584	bne- 10b
	585	blr
	586	_GLOBAL(atomic_set_mask)
	587	10: lwarx r5,0,r4
	588	or r5,r5,r3
	589	PPC405_ERR77(0,r4)
	590	stwcx. r5,0,r4
	591	bne- 10b
	592	blr
	593
9994a338 PM	594	/*
	595	* Extended precision shifts.
	596	*
	597	* Updated to be valid for shift counts from 0 to 63 inclusive.
	598	* -- Gabriel
	599	*
	600	* R3/R4 has 64 bit value
	601	* R5 has shift count
	602	* result in R3/R4
	603	*
	604	* ashrdi3: arithmetic right shift (sign propagation)
	605	* lshrdi3: logical right shift
	606	* ashldi3: left shift
	607	*/
	608	_GLOBAL(__ashrdi3)
	609	subfic r6,r5,32
	610	srw r4,r4,r5 # LSW = count > 31 ? 0 : LSW >> count
	611	addi r7,r5,32 # could be xori, or addi with -32
	612	slw r6,r3,r6 # t1 = count > 31 ? 0 : MSW << (32-count)
	613	rlwinm r8,r7,0,32 # t3 = (count < 32) ? 32 : 0
	614	sraw r7,r3,r7 # t2 = MSW >> (count-32)
	615	or r4,r4,r6 # LSW \|= t1
	616	slw r7,r7,r8 # t2 = (count < 32) ? 0 : t2
	617	sraw r3,r3,r5 # MSW = MSW >> count
	618	or r4,r4,r7 # LSW \|= t2
	619	blr
	620
	621	_GLOBAL(__ashldi3)
	622	subfic r6,r5,32
	623	slw r3,r3,r5 # MSW = count > 31 ? 0 : MSW << count
	624	addi r7,r5,32 # could be xori, or addi with -32
	625	srw r6,r4,r6 # t1 = count > 31 ? 0 : LSW >> (32-count)
	626	slw r7,r4,r7 # t2 = count < 32 ? 0 : LSW << (count-32)
	627	or r3,r3,r6 # MSW \|= t1
	628	slw r4,r4,r5 # LSW = LSW << count
	629	or r3,r3,r7 # MSW \|= t2
	630	blr
	631
	632	_GLOBAL(__lshrdi3)
	633	subfic r6,r5,32
	634	srw r4,r4,r5 # LSW = count > 31 ? 0 : LSW >> count
	635	addi r7,r5,32 # could be xori, or addi with -32
	636	slw r6,r3,r6 # t1 = count > 31 ? 0 : MSW << (32-count)
	637	srw r7,r3,r7 # t2 = count < 32 ? 0 : MSW >> (count-32)
	638	or r4,r4,r6 # LSW \|= t1
	639	srw r3,r3,r5 # MSW = MSW >> count
	640	or r4,r4,r7 # LSW \|= t2
	641	blr
	642
95ff54f5 PM	643	/*
	644	* 64-bit comparison: __ucmpdi2(u64 a, u64 b)
	645	* Returns 0 if a < b, 1 if a == b, 2 if a > b.
	646	*/
	647	_GLOBAL(__ucmpdi2)
	648	cmplw r3,r5
	649	li r3,1
	650	bne 1f
	651	cmplw r4,r6
	652	beqlr
	653	1: li r3,0
	654	bltlr
	655	li r3,2
	656	blr
	657
9994a338 PM	658	_GLOBAL(abs)
	659	srawi r4,r3,31
	660	xor r3,r3,r4
	661	sub r3,r3,r4
	662	blr
	663
9994a338 PM	664	/*
	665	* Create a kernel thread
	666	* kernel_thread(fn, arg, flags)
	667	*/
	668	_GLOBAL(kernel_thread)
	669	stwu r1,-16(r1)
	670	stw r30,8(r1)
	671	stw r31,12(r1)
	672	mr r30,r3 /* function */
	673	mr r31,r4 /* argument */
	674	ori r3,r5,CLONE_VM /* flags */
	675	oris r3,r3,CLONE_UNTRACED>>16
	676	li r4,0 /* new sp (unused) */
	677	li r0,__NR_clone
	678	sc
41c2e949 JP	679	bns+ 1f /* did system call indicate error? */
	680	neg r3,r3 /* if so, make return code negative */
	681	1: cmpwi 0,r3,0 /* parent or child? */
	682	bne 2f /* return if parent */
9994a338 PM	683	li r0,0 /* make top-level stack frame */
	684	stwu r0,-16(r1)
	685	mtlr r30 /* fn addr in lr */
	686	mr r3,r31 /* load arg and call fn */
	687	PPC440EP_ERR42
	688	blrl
	689	li r0,__NR_exit /* exit if function returns */
	690	li r3,0
	691	sc
41c2e949	692	2: lwz r30,8(r1)
9994a338 PM	693	lwz r31,12(r1)
	694	addi r1,r1,16
	695	blr
	696
69e3cea8 BH	697	#ifdef CONFIG_SMP
	698	_GLOBAL(start_secondary_resume)
	699	/* Reset stack */
	700	rlwinm r1,r1,0,0,(31-THREAD_SHIFT) /* current_thread_info() */
	701	addi r1,r1,THREAD_SIZE-STACK_FRAME_OVERHEAD
	702	li r3,0
6de06f31	703	stw r3,0(r1) /* Zero the stack frame pointer */
69e3cea8 BH	704	bl start_secondary
	705	b .
	706	#endif /* CONFIG_SMP */
	707
9994a338 PM	708	/*
	709	* This routine is just here to keep GCC happy - sigh...
	710	*/
	711	_GLOBAL(__main)
	712	blr
3d1229d6 ME	713
	714	#ifdef CONFIG_KEXEC
	715	/*
	716	* Must be relocatable PIC code callable as a C function.
	717	*/
	718	.globl relocate_new_kernel
	719	relocate_new_kernel:
	720	/* r3 = page_list */
	721	/* r4 = reboot_code_buffer */
	722	/* r5 = start_address */
	723
b3df895a SAS	724	#ifdef CONFIG_FSL_BOOKE
	725
	726	mr r29, r3
	727	mr r30, r4
	728	mr r31, r5
	729
	730	#define ENTRY_MAPPING_KEXEC_SETUP
	731	#include "fsl_booke_entry_mapping.S"
	732	#undef ENTRY_MAPPING_KEXEC_SETUP
	733
	734	mr r3, r29
	735	mr r4, r30
	736	mr r5, r31
	737
	738	li r0, 0
	739	#else
3d1229d6 ME	740	li r0, 0
	741
	742	/*
	743	* Set Machine Status Register to a known status,
	744	* switch the MMU off and jump to 1: in a single step.
	745	*/
	746
	747	mr r8, r0
	748	ori r8, r8, MSR_RI\|MSR_ME
	749	mtspr SPRN_SRR1, r8
	750	addi r8, r4, 1f - relocate_new_kernel
	751	mtspr SPRN_SRR0, r8
	752	sync
	753	rfi
	754
	755	1:
b3df895a	756	#endif
3d1229d6 ME	757	/* from this point address translation is turned off */
	758	/* and interrupts are disabled */
	759
	760	/* set a new stack at the bottom of our page... */
	761	/* (not really needed now) */
d9178f4c	762	addi r1, r4, KEXEC_CONTROL_PAGE_SIZE - 8 /* for LR Save+Back Chain */
3d1229d6 ME	763	stw r0, 0(r1)
	764
	765	/* Do the copies */
	766	li r6, 0 /* checksum */
	767	mr r0, r3
	768	b 1f
	769
	770	0: /* top, read another word for the indirection page */
	771	lwzu r0, 4(r3)
	772
	773	1:
	774	/* is it a destination page? (r8) */
	775	rlwinm. r7, r0, 0, 31, 31 /* IND_DESTINATION (1<<0) */
	776	beq 2f
	777
	778	rlwinm r8, r0, 0, 0, 19 /* clear kexec flags, page align */
	779	b 0b
	780
	781	2: /* is it an indirection page? (r3) */
	782	rlwinm. r7, r0, 0, 30, 30 /* IND_INDIRECTION (1<<1) */
	783	beq 2f
	784
	785	rlwinm r3, r0, 0, 0, 19 /* clear kexec flags, page align */
	786	subi r3, r3, 4
	787	b 0b
	788
	789	2: /* are we done? */
	790	rlwinm. r7, r0, 0, 29, 29 /* IND_DONE (1<<2) */
	791	beq 2f
	792	b 3f
	793
	794	2: /* is it a source page? (r9) */
	795	rlwinm. r7, r0, 0, 28, 28 /* IND_SOURCE (1<<3) */
	796	beq 0b
	797
	798	rlwinm r9, r0, 0, 0, 19 /* clear kexec flags, page align */
	799
	800	li r7, PAGE_SIZE / 4
	801	mtctr r7
	802	subi r9, r9, 4
	803	subi r8, r8, 4
	804	9:
	805	lwzu r0, 4(r9) /* do the copy */
	806	xor r6, r6, r0
	807	stwu r0, 4(r8)
	808	dcbst 0, r8
	809	sync
	810	icbi 0, r8
	811	bdnz 9b
	812
	813	addi r9, r9, 4
	814	addi r8, r8, 4
	815	b 0b
	816
	817	3:
	818
	819	/* To be certain of avoiding problems with self-modifying code
	820	* execute a serializing instruction here.
	821	*/
	822	isync
	823	sync
	824
4562c986 MM	825	mfspr r3, SPRN_PIR /* current core we are running on */
	826	mr r4, r5 /* load physical address of chunk called */
	827
3d1229d6 ME	828	/* jump to the entry point, usually the setup routine */
	829	mtlr r5
	830	blrl
	831
	832	1: b 1b
	833
	834	relocate_new_kernel_end:
	835
	836	.globl relocate_new_kernel_size
	837	relocate_new_kernel_size:
	838	.long relocate_new_kernel_end - relocate_new_kernel
	839	#endif